return table[SPIN_TABLE_ELEM_STATUS_IDX] == 1;
}
-int cpu_reset(int nr)
+int cpu_reset(u32 nr)
{
puts("Feature is not implemented.\n");
return 0;
}
-int cpu_disable(int nr)
+int cpu_disable(u32 nr)
{
puts("Feature is not implemented.\n");
return i;
}
-int cpu_status(int nr)
+int cpu_status(u32 nr)
{
u64 *table;
int pos;
return 0;
}
-int cpu_release(int nr, int argc, char * const argv[])
+int cpu_release(u32 nr, int argc, char * const argv[])
{
u64 boot_addr;
u64 *table = (u64 *)get_spin_tbl_addr();
return 0;
}
-int cpu_reset(int nr)
+int cpu_reset(u32 nr)
{
puts("Feature is not implemented.\n");
return 0;
udelay(0x500);
}
-int cpu_disable(int nr)
+int cpu_disable(u32 nr)
{
if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) {
u32 val = readl(&crfapb_base->rst_fpd_apu);
return 0;
}
-int cpu_status(int nr)
+int cpu_status(u32 nr)
{
if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) {
u32 addr_low = readl(((u8 *)&apu_base->rvbar_addr0_l) + nr * 8);
}
}
-int cpu_release(int nr, int argc, char * const argv[])
+int cpu_release(u32 nr, int argc, char * const argv[])
{
if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) {
u64 boot_addr = simple_strtoull(argv[0], NULL, 16);
SRC_SCR_CORE_3_ENABLE_MASK
};
-int cpu_reset(int nr)
+int cpu_reset(u32 nr)
{
/* Software reset of the CPU N */
src->scr |= cpu_reset_mask[nr];
return 0;
}
-int cpu_status(int nr)
+int cpu_status(u32 nr)
{
printf("core %d => %d\n", nr, !!(src->scr & cpu_ctrl_mask[nr]));
return 0;
}
-int cpu_release(int nr, int argc, char *const argv[])
+int cpu_release(u32 nr, int argc, char *const argv[])
{
uint32_t boot_addr;
return 1;
}
-int cpu_disable(int nr)
+int cpu_disable(u32 nr)
{
/* Disable the CPU N */
src->scr &= ~cpu_ctrl_mask[nr];
return 0;
}
-int cpu_reset(int nr)
+int cpu_reset(u32 nr)
{
volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
out_be32(&pic->pir, 1 << nr);
return 0;
}
-int cpu_status(int nr)
+int cpu_status(u32 nr)
{
u32 *table, id = get_my_id();
}
#ifdef CONFIG_FSL_CORENET
-int cpu_disable(int nr)
+int cpu_disable(u32 nr)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
return (coredisrl & (1 << nr));
}
#else
-int cpu_disable(int nr)
+int cpu_disable(u32 nr)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
BOOT_ENTRY_R3_LOWER,
};
-int cpu_release(int nr, int argc, char * const argv[])
+int cpu_release(u32 nr, int argc, char * const argv[])
{
u32 i, val, *table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY;
u64 boot_addr;
DECLARE_GLOBAL_DATA_PTR;
-int cpu_reset(int nr)
+int cpu_reset(u32 nr)
{
/* dummy function so common/cmd_mp.c will build
* should be implemented in the future, when cpu_release()
return 1;
}
-int cpu_status(int nr)
+int cpu_status(u32 nr)
{
/* dummy function so common/cmd_mp.c will build */
return 0;
}
-int cpu_disable(int nr)
+int cpu_disable(u32 nr)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
volatile ccsr_gur_t *gur = &immap->im_gur;
return 0;
}
-int cpu_release(int nr, int argc, char * const argv[])
+int cpu_release(u32 nr, int argc, char * const argv[])
{
/* dummy function so common/cmd_mp.c will build
* should be implemented in the future */
/* Multicore arch functions */
#ifdef CONFIG_MP
-int cpu_status(int nr);
-int cpu_reset(int nr);
-int cpu_disable(int nr);
-int cpu_release(int nr, int argc, char * const argv[]);
+int cpu_status(u32 nr);
+int cpu_reset(u32 nr);
+int cpu_disable(u32 nr);
+int cpu_release(u32 nr, int argc, char * const argv[]);
#endif
#else /* __ASSEMBLY__ */