]> git.sur5r.net Git - u-boot/commitdiff
arm: socfpga: timer: Pull the timer reload value from config file
authorMarek Vasut <marex@denx.de>
Mon, 8 Sep 2014 12:08:45 +0000 (14:08 +0200)
committerMarek Vasut <marex@denx.de>
Mon, 6 Oct 2014 15:46:49 +0000 (17:46 +0200)
The timer reload value is a property of the timer hardware and there
is no reason for this to be configurable. Place this into the timer
driver just like on the other hardware.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
arch/arm/cpu/armv7/socfpga/timer.c
include/configs/socfpga_cyclone5.h

index 58fc789e6451534951a169d66ecb4ceefa1ed478..253cde39d1116ae4c227ffc4a364d75ec860ff17 100644 (file)
@@ -8,6 +8,8 @@
 #include <asm/io.h>
 #include <asm/arch/timer.h>
 
+#define TIMER_LOAD_VAL         0xFFFFFFFF
+
 static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE;
 
 /*
index 708309b08f7cb00e54ac0acfe388ed74b8533a18..54343b83a489e0b864b2e443f04095e812f4b42e 100644 (file)
 /* This timer use eosc1 where the clock frequency is fixed
  * throughout any condition */
 #define CONFIG_SYS_TIMERBASE           SOCFPGA_OSC1TIMER0_ADDRESS
-/* reload value when timer count to zero */
-#define TIMER_LOAD_VAL                 0xFFFFFFFF
 /* Timer info */
 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 #define CONFIG_SYS_TIMER_RATE          2400000