add I2C4 modul for MX6DL based boards.
Signed-off-by: Heiko Schocher <hs@denx.de>
 #endif
 
 #ifdef CONFIG_SYS_I2C_MXC
-/* i2c_num can be from 0 - 2 */
+/* i2c_num can be from 0 - 3 */
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 {
        u32 reg;
        u32 mask;
 
-       if (i2c_num > 2)
+       if (i2c_num > 3)
                return -EINVAL;
-
-       mask = MXC_CCM_CCGR_CG_MASK
-               << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET + (i2c_num << 1));
-       reg = __raw_readl(&imx_ccm->CCGR2);
-       if (enable)
-               reg |= mask;
-       else
-               reg &= ~mask;
-       __raw_writel(reg, &imx_ccm->CCGR2);
+       if (i2c_num < 3) {
+               mask = MXC_CCM_CCGR_CG_MASK
+                       << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
+                       + (i2c_num << 1));
+               reg = __raw_readl(&imx_ccm->CCGR2);
+               if (enable)
+                       reg |= mask;
+               else
+                       reg &= ~mask;
+               __raw_writel(reg, &imx_ccm->CCGR2);
+       } else {
+               mask = MXC_CCM_CCGR_CG_MASK
+                       << (MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET);
+               reg = __raw_readl(&imx_ccm->CCGR1);
+               if (enable)
+                       reg |= mask;
+               else
+                       reg &= ~mask;
+               __raw_writel(reg, &imx_ccm->CCGR1);
+       }
        return 0;
 }
 #endif
 
 #ifdef I2C3_BASE_ADDR
        (void *)I2C3_BASE_ADDR,
 #endif
+#ifdef I2C4_BASE_ADDR
+       (void *)I2C4_BASE_ADDR,
+#endif
 };
 
-/* i2c_index can be from 0 - 2 */
+/* i2c_index can be from 0 - 3 */
 int setup_i2c(unsigned i2c_index, int speed, int slave_addr,
              struct i2c_pads_info *p)
 {
 
 #define MXC_CCM_CCGR2_I2C2_SERIAL_MASK                 (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
 #define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET               10
 #define MXC_CCM_CCGR2_I2C3_SERIAL_MASK                 (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
+#define MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET               8
+#define MXC_CCM_CCGR1_I2C4_SERIAL_MASK                 (3 << MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET)
 #define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET                        12
 #define MXC_CCM_CCGR2_OCOTP_CTRL_MASK                  (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET          14
 
 #define UART3_BASE                  (AIPS2_OFF_BASE_ADDR + 0x6C000)
 #define UART4_BASE                  (AIPS2_OFF_BASE_ADDR + 0x70000)
 #define UART5_BASE                  (AIPS2_OFF_BASE_ADDR + 0x74000)
+#define I2C4_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x78000)
 #define IP2APB_USBPHY1_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x78000)
 #define IP2APB_USBPHY2_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x7C000)
 
 
        { 0, I2C1_BASE_ADDR },
        { 1, I2C2_BASE_ADDR },
        { 2, I2C3_BASE_ADDR },
+#if defined(CONFIG_MX6DL)
+       { 3, I2C4_BASE_ADDR },
+#endif
 #elif defined(CONFIG_LS102XA)
        { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
        { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },