u16 data_ctl = 0;
        u16 dma_cfg = 0;
        int ret = 0;
+       unsigned long data_size = data->blocksize * data->blocks;
 
        /* Don't support write yet. */
        if (data->flags & MMC_DATA_WRITE)
                return UNUSABLE_ERR;
-       data_ctl |= ((ffs(data->blocksize) - 1) << 4);
+       data_ctl |= ((ffs(data_size) - 1) << 4);
        data_ctl |= DTX_DIR;
        bfin_write_SDH_DATA_CTL(data_ctl);
        dma_cfg = WDSIZE_32 | RESTART | WNR | DMAEN;
        bfin_write_SDH_DATA_TIMER(-1);
 
        blackfin_dcache_flush_invalidate_range(data->dest,
-                       data->dest + data->blocksize);
+                       data->dest + data_size);
        /* configure DMA */
        bfin_write_DMA_START_ADDR(data->dest);
-       bfin_write_DMA_X_COUNT(data->blocksize / 4);
+       bfin_write_DMA_X_COUNT(data_size / 4);
        bfin_write_DMA_X_MODIFY(4);
        bfin_write_DMA_CONFIG(dma_cfg);
-       bfin_write_SDH_DATA_LGTH(data->blocksize);
+       bfin_write_SDH_DATA_LGTH(data_size);
        /* kick off transfer */
        bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E);