Invalidate INIT_RAM TLB mappings

Commit 0db37dc...  (and some others) changed the INIT_RAM TLB
mappings to be unguarded.  This collided with an existing "bug"
where the mappings for the INIT_RAM were being kept around.
This meant that speculative loads to those addresses were
succeeding in the TLB, and going out to the bus, where they
were causing an exception (there's nothing at that address). The
Flash code was coincidentally causing such a speculative load.
Rather than go back to mapping the INIT RAM as guarded, we fix
it so that the entries for the INIT_RAM are invalidated.  Thus
the speculative loads will fail in the TLB, and have no effect.

Signed-off-by: Andy Fleming <afleming@freescale.com>

diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index eb24dbc430715294feea0aeac3aa49a864f0ca2c..636ef5da63f296046e9c2eeb67a342f1d69f79f5 100644 (file)
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -1007,6 +1007,17 @@ unlock_ram_in_cache:
        addi    r3,r3,CFG_CACHELINE_SIZE
        bdnz    1b
        sync                    /* Wait for all icbi to complete on bus */
+
+       /* Invalidate the TLB entries for the cache */
+       lis     r3,CFG_INIT_RAM_ADDR@h
+       ori     r3,r3,CFG_INIT_RAM_ADDR@l
+       tlbivax 0,r3
+       addi    r3,r3,0x1000
+       tlbivax 0,r3
+       addi    r3,r3,0x1000
+       tlbivax 0,r3
+       addi    r3,r3,0x1000
+       tlbivax 0,r3
        isync
        blr
 #endif