--- /dev/null
+NOP PHY driver
+
+This driver is used to stub PHY operations in a driver (USB, SATA).
+This is useful when the 'client' driver (USB, SATA, ...) uses the PHY framework
+and there is no actual PHY harwdare to drive.
+
+Required properties:
+- compatible : must contain "nop-phy"
+- #phy-cells : must contain <0>
+
+Example:
+
+nop_phy {
+ compatible = "nop-phy";
+ #phy-cells = <0>;
+};
--- /dev/null
+Broadcom STB wake-up Timer
+
+The Broadcom STB wake-up timer provides a 27Mhz resolution timer, with the
+ability to wake up the system from low-power suspend/standby modes.
+
+Required properties:
+- compatible : should contain "brcm,brcmstb-waketimer"
+- reg : the register start and length for the WKTMR block
+- interrupts : The TIMER interrupt
+- interrupt-parent: The phandle to the Always-On (AON) Power Management (PM) L2
+ interrupt controller node
+- clocks : The phandle to the UPG fixed clock (27Mhz domain)
+
+Example:
+
+waketimer@f0411580 {
+ compatible = "brcm,brcmstb-waketimer";
+ reg = <0xf0411580 0x14>;
+ interrupts = <0x3>;
+ interrupt-parent = <&aon_pm_l2_intc>;
+ clocks = <&upg_fixed>;
+};
particular needs this to operate, so that it can allocate the
initial serial device and any others that are needed.
+config SPL_SYS_MALLOC_F_LEN
+ hex "Size of malloc() pool in spl before relocation"
+ depends on SYS_MALLOC_F
+ default SYS_MALLOC_F_LEN
+ help
+ Before relocation, memory is very limited on many platforms. Still,
+ we can provide a small malloc() pool if needed. Driver model in
+ particular needs this to operate, so that it can allocate the
+ initial serial device and any others that are needed.
+
menuconfig EXPERT
bool "Configure standard U-Boot features (expert users)"
default y
F: arch/arm/cpu/arm926ejs/mx*/
F: arch/arm/cpu/armv7/mx*/
F: arch/arm/cpu/armv7/vf610/
-F: arch/arm/imx-common/
+F: arch/arm/mach-imx/
F: arch/arm/include/asm/arch-imx/
F: arch/arm/include/asm/arch-mx*/
F: arch/arm/include/asm/arch-vf610/
-F: arch/arm/include/asm/imx-common/
+F: arch/arm/include/asm/mach-imx/
F: board/freescale/*mx*/
ARM HISILICON
T: git git://git.denx.de/u-boot-mpc8xx.git
F: arch/powerpc/cpu/mpc8xx/
-POWERPC MPC82XX
-M: Wolfgang Denk <wd@denx.de>
-S: Maintained
-T: git git://git.denx.de/u-boot-mpc82xx.git
-F: arch/powerpc/cpu/mpc82*/
-
POWERPC MPC83XX
M: Mario Six <mario.six@gdsys.cc>
S: Maintained
X86
M: Simon Glass <sjg@chromium.org>
+M: Bin Meng <bmeng.cn@gmail.com>
S: Maintained
T: git git://git.denx.de/u-boot-x86.git
F: arch/x86/
AWK = awk
PERL = perl
PYTHON ?= python
-DTC = dtc
+DTC ?= dtc
CHECK = sparse
CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \
@# Otherwise, 'make silentoldconfig' would be invoked twice.
$(Q)touch include/config/auto.conf
+u-boot.cfg spl/u-boot.cfg tpl/u-boot.cfg: include/config.h FORCE
+ $(Q)$(MAKE) -f $(srctree)/scripts/Makefile.autoconf $(@)
+
-include include/autoconf.mk
-include include/autoconf.mk.dep
cmd_cfgcheck = $(srctree)/scripts/check-config.sh $2 \
$(srctree)/scripts/config_whitelist.txt $(srctree)
-all: $(ALL-y)
+all: $(ALL-y) cfg
ifeq ($(CONFIG_DM_I2C_COMPAT)$(CONFIG_SANDBOX),y)
@echo "===================== WARNING ======================"
@echo "This board uses CONFIG_DM_I2C_COMPAT. Please remove"
endif
%.imx: %.bin
- $(Q)$(MAKE) $(build)=arch/arm/imx-common $@
+ $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
%.vyb: %.imx
$(Q)$(MAKE) $(build)=arch/arm/cpu/armv7/vf610 $@
$(call if_changed,pad_cat)
SPL: spl/u-boot-spl.bin FORCE
- $(Q)$(MAKE) $(build)=arch/arm/imx-common $@
+ $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
u-boot-with-spl.imx u-boot-with-nand-spl.imx: SPL u-boot.bin FORCE
- $(Q)$(MAKE) $(build)=arch/arm/imx-common $@
+ $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
MKIMAGEFLAGS_u-boot.ubl = -n $(UBL_CONFIG) -T ublimage -e $(CONFIG_SYS_TEXT_BASE)
$(Q)$(OBJCOPY) -I binary $(PLATFORM_ELFFLAGS) $< u-boot-elf.o
$(call if_changed,u-boot-elf)
+ARCH_POSTLINK := $(wildcard $(srctree)/arch/$(ARCH)/Makefile.postlink)
+
# Rule to link u-boot
# May be overridden by arch/$(ARCH)/config.mk
quiet_cmd_u-boot__ ?= LD $@
cmd_u-boot__ ?= $(LD) $(LDFLAGS) $(LDFLAGS_u-boot) -o $@ \
-T u-boot.lds $(u-boot-init) \
--start-group $(u-boot-main) --end-group \
- $(PLATFORM_LIBS) -Map u-boot.map
+ $(PLATFORM_LIBS) -Map u-boot.map; \
+ $(if $(ARCH_POSTLINK), $(MAKE) -f $(ARCH_POSTLINK) $@, true)
quiet_cmd_smap = GEN common/system_map.o
cmd_smap = \
-c $(srctree)/common/system_map.c -o common/system_map.o
u-boot: $(u-boot-init) $(u-boot-main) u-boot.lds FORCE
- $(call if_changed,u-boot__)
+ +$(call if_changed,u-boot__)
ifeq ($(CONFIG_KALLSYMS),y)
$(call cmd,smap)
$(call cmd,u-boot__) common/system_map.o
LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_TIME "%T"'; \
LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_TZ "%z"'; \
LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_DMI_DATE "%m/%d/%Y"'; \
+ LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_BUILD_DATE 0x%Y%m%d'; \
else \
return 42; \
fi; \
LC_ALL=C date +'#define U_BOOT_TIME "%T"'; \
LC_ALL=C date +'#define U_BOOT_TZ "%z"'; \
LC_ALL=C date +'#define U_BOOT_DMI_DATE "%m/%d/%Y"'; \
+ LC_ALL=C date +'#define U_BOOT_BUILD_DATE 0x%Y%m%d'; \
fi)
endef
CONFIG_CMD_MISC Misc functions like sleep etc
CONFIG_CMD_MMC * MMC memory mapped support
CONFIG_CMD_MII * MII utility commands
- CONFIG_CMD_MTDPARTS * MTD partition support
CONFIG_CMD_NAND * NAND support
CONFIG_CMD_NET bootp, tftpboot, rarpboot
CONFIG_CMD_NFS NFS support
the malloc area (as defined by CONFIG_SYS_MALLOC_LEN) should
be at least 4MB.
- CONFIG_LZO
-
- If this option is set, support for LZO compressed images
- is included.
-
- MII/PHY support:
CONFIG_PHY_ADDR
kernel. Needed for UBI support.
- UBI support
- CONFIG_CMD_UBI
-
- Adds commands for interacting with MTD partitions formatted
- with the UBI flash translation layer
-
- Requires also defining CONFIG_RBTREE
-
CONFIG_UBI_SILENCE_MSG
Make the verbose messages from UBI stop printing. This leaves
default: 0
- UBIFS support
- CONFIG_CMD_UBIFS
-
- Adds commands for interacting with UBI volumes formatted as
- UBIFS. UBIFS is read-only in u-boot.
-
- Requires UBI support as well as CONFIG_LZO
-
CONFIG_UBIFS_SILENCE_MSG
Make the verbose messages from UBIFS stop printing. This leaves
Builds up envcrc with the target environment so that external utils
may easily extract it and embed it in final U-Boot images.
-- CONFIG_ENV_IS_IN_FLASH:
-
- Define this if the environment is in flash memory.
-
- a) The environment occupies one whole flash sector, which is
- "embedded" in the text segment with the U-Boot code. This
- happens usually with "bottom boot sector" or "top boot
- sector" type flash chips, which have several smaller
- sectors at the start or the end. For instance, such a
- layout can have sector sizes of 8, 2x4, 16, Nx32 kB. In
- such a case you would place the environment in one of the
- 4 kB sectors - with U-Boot code before and after it. With
- "top boot sector" type flash chips, you would put the
- environment in one of the last sectors, leaving a gap
- between U-Boot and the environment.
-
- - CONFIG_ENV_OFFSET:
-
- Offset of environment data (variable area) to the
- beginning of flash memory; for instance, with bottom boot
- type flash chips the second sector can be used: the offset
- for this sector is given here.
-
- CONFIG_ENV_OFFSET is used relative to CONFIG_SYS_FLASH_BASE.
-
- - CONFIG_ENV_ADDR:
-
- This is just another way to specify the start address of
- the flash sector containing the environment (instead of
- CONFIG_ENV_OFFSET).
-
- - CONFIG_ENV_SECT_SIZE:
-
- Size of the sector containing the environment.
-
-
- b) Sometimes flash chips have few, equal sized, BIG sectors.
- In such a case you don't want to spend a whole sector for
- the environment.
-
- - CONFIG_ENV_SIZE:
-
- If you use this in combination with CONFIG_ENV_IS_IN_FLASH
- and CONFIG_ENV_SECT_SIZE, you can specify to use only a part
- of this flash sector for the environment. This saves
- memory for the RAM copy of the environment.
-
- It may also save flash memory if you decide to use this
- when your environment is "embedded" within U-Boot code,
- since then the remainder of the flash sector could be used
- for U-Boot code. It should be pointed out that this is
- STRONGLY DISCOURAGED from a robustness point of view:
- updating the environment in flash makes it always
- necessary to erase the WHOLE sector. If something goes
- wrong before the contents has been restored from a copy in
- RAM, your target system will be dead.
-
- - CONFIG_ENV_ADDR_REDUND
- CONFIG_ENV_SIZE_REDUND
-
- These settings describe a second storage area used to hold
- a redundant copy of the environment data, so that there is
- a valid backup copy in case there is a power failure during
- a "saveenv" operation.
-
-BE CAREFUL! Any changes to the flash layout, and some changes to the
-source code will make it necessary to adapt <board>/u-boot.lds*
-accordingly!
-
-
-- CONFIG_ENV_IS_IN_NVRAM:
-
- Define this if you have some non-volatile memory device
- (NVRAM, battery buffered SRAM) which you want to use for the
- environment.
-
- - CONFIG_ENV_ADDR:
- - CONFIG_ENV_SIZE:
-
- These two #defines are used to determine the memory area you
- want to use for environment. It is assumed that this memory
- can just be read and written to, without any special
- provision.
-
BE CAREFUL! The first access to the environment happens quite early
in U-Boot initialization (when we try to get the setting of for the
console baudrate). You *MUST* have mapped your NVRAM area then, or
keep settings there always unmodified except somebody uses "saveenv"
to save the current settings.
-
-- CONFIG_ENV_IS_IN_EEPROM:
-
- Use this if you have an EEPROM or similar serial access
- device and a driver for it.
-
- - CONFIG_ENV_OFFSET:
- - CONFIG_ENV_SIZE:
-
- These two #defines specify the offset and size of the
- environment area within the total memory of your EEPROM.
-
- - CONFIG_SYS_I2C_EEPROM_ADDR:
- If defined, specified the chip address of the EEPROM device.
- The default address is zero.
-
- - CONFIG_SYS_I2C_EEPROM_BUS:
- If defined, specified the i2c bus of the EEPROM device.
-
- - CONFIG_SYS_EEPROM_PAGE_WRITE_BITS:
- If defined, the number of bits used to address bytes in a
- single page in the EEPROM device. A 64 byte page, for example
- would require six bits.
-
- - CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS:
- If defined, the number of milliseconds to delay between
- page writes. The default is zero milliseconds.
-
- - CONFIG_SYS_I2C_EEPROM_ADDR_LEN:
- The length in bytes of the EEPROM memory array address. Note
- that this is NOT the chip address length!
-
- - CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW:
- EEPROM chips that implement "address overflow" are ones
- like Catalyst 24WC04/08/16 which has 9/10/11 bits of
- address and the extra bits end up in the "chip address" bit
- slots. This makes a 24WC08 (1Kbyte) chip look like four 256
- byte chips.
-
- Note that we consider the length of the address field to
- still be one byte because the extra address bits are hidden
- in the chip address.
-
- - CONFIG_SYS_EEPROM_SIZE:
- The size in bytes of the EEPROM device.
-
- - CONFIG_ENV_EEPROM_IS_ON_I2C
- define this, if you have I2C and SPI activated, and your
- EEPROM, which holds the environment, is on the I2C bus.
-
- - CONFIG_I2C_ENV_EEPROM_BUS
- if you have an Environment on an EEPROM reached over
- I2C muxes, you can define here, how to reach this
- EEPROM. For example:
-
- #define CONFIG_I2C_ENV_EEPROM_BUS 1
-
- EEPROM which holds the environment, is reached over
- a pca9547 i2c mux with address 0x70, channel 3.
-
-- CONFIG_ENV_IS_IN_DATAFLASH:
-
- Define this if you have a DataFlash memory device which you
- want to use for the environment.
-
- - CONFIG_ENV_OFFSET:
- - CONFIG_ENV_ADDR:
- - CONFIG_ENV_SIZE:
-
- These three #defines specify the offset and size of the
- environment area within the total memory of your DataFlash placed
- at the specified address.
-
-- CONFIG_ENV_IS_IN_SPI_FLASH:
-
- Define this if you have a SPI Flash memory device which you
- want to use for the environment.
-
- - CONFIG_ENV_OFFSET:
- - CONFIG_ENV_SIZE:
-
- These two #defines specify the offset and size of the
- environment area within the SPI Flash. CONFIG_ENV_OFFSET must be
- aligned to an erase sector boundary.
-
- - CONFIG_ENV_SECT_SIZE:
-
- Define the SPI flash's sector size.
-
- - CONFIG_ENV_OFFSET_REDUND (optional):
-
- This setting describes a second storage area of CONFIG_ENV_SIZE
- size used to hold a redundant copy of the environment data, so
- that there is a valid backup copy in case there is a power failure
- during a "saveenv" operation. CONFIG_ENV_OFFSET_REDUND must be
- aligned to an erase sector boundary.
-
- - CONFIG_ENV_SPI_BUS (optional):
- - CONFIG_ENV_SPI_CS (optional):
-
- Define the SPI bus and chip select. If not defined they will be 0.
-
- - CONFIG_ENV_SPI_MAX_HZ (optional):
-
- Define the SPI max work clock. If not defined then use 1MHz.
-
- - CONFIG_ENV_SPI_MODE (optional):
-
- Define the SPI work mode. If not defined then use SPI_MODE_3.
-
-- CONFIG_ENV_IS_IN_REMOTE:
-
- Define this if you have a remote memory space which you
- want to use for the local device's environment.
-
- - CONFIG_ENV_ADDR:
- - CONFIG_ENV_SIZE:
-
- These two #defines specify the address and size of the
- environment area within the remote memory space. The
- local device can get the environment from remote memory
- space by SRIO or PCIE links.
-
BE CAREFUL! For some special cases, the local device can not use
"saveenv" command. For example, the local device will get the
environment stored in a remote NOR flash by SRIO or PCIE link,
but it can not erase, write this NOR flash by SRIO or PCIE interface.
-- CONFIG_ENV_IS_IN_NAND:
-
- Define this if you have a NAND device which you want to use
- for the environment.
-
- - CONFIG_ENV_OFFSET:
- - CONFIG_ENV_SIZE:
-
- These two #defines specify the offset and size of the environment
- area within the first NAND device. CONFIG_ENV_OFFSET must be
- aligned to an erase block boundary.
-
- - CONFIG_ENV_OFFSET_REDUND (optional):
-
- This setting describes a second storage area of CONFIG_ENV_SIZE
- size used to hold a redundant copy of the environment data, so
- that there is a valid backup copy in case there is a power failure
- during a "saveenv" operation. CONFIG_ENV_OFFSET_REDUND must be
- aligned to an erase block boundary.
-
- - CONFIG_ENV_RANGE (optional):
-
- Specifies the length of the region in which the environment
- can be written. This should be a multiple of the NAND device's
- block size. Specifying a range with more erase blocks than
- are needed to hold CONFIG_ENV_SIZE allows bad blocks within
- the range to be avoided.
-
- - CONFIG_ENV_OFFSET_OOB (optional):
-
- Enables support for dynamically retrieving the offset of the
- environment from block zero's out-of-band data. The
- "nand env.oob" command can be used to record this offset.
- Currently, CONFIG_ENV_OFFSET_REDUND is not supported when
- using CONFIG_ENV_OFFSET_OOB.
-
- CONFIG_NAND_ENV_DST
Defines address in RAM to which the nand_spl code should copy the
environment. If redundant environment is used, it will be copied to
CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE.
-- CONFIG_ENV_IS_IN_UBI:
-
- Define this if you have an UBI volume that you want to use for the
- environment. This has the benefit of wear-leveling the environment
- accesses, which is important on NAND.
-
- - CONFIG_ENV_UBI_PART:
-
- Define this to a string that is the mtd partition containing the UBI.
-
- - CONFIG_ENV_UBI_VOLUME:
-
- Define this to the name of the volume that you want to store the
- environment in.
-
- - CONFIG_ENV_UBI_VOLUME_REDUND:
-
- Define this to the name of another volume to store a second copy of
- the environment in. This will enable redundant environments in UBI.
- It is assumed that both volumes are in the same MTD partition.
-
- - CONFIG_UBI_SILENCE_MSG
- - CONFIG_UBIFS_SILENCE_MSG
-
- You will probably want to define these to avoid a really noisy system
- when storing the env in UBI.
-
-- CONFIG_ENV_IS_IN_FAT:
- Define this if you want to use the FAT file system for the environment.
-
- - FAT_ENV_INTERFACE:
-
- Define this to a string that is the name of the block device.
-
- - FAT_ENV_DEVICE_AND_PART:
-
- Define this to a string to specify the partition of the device. It can
- be as following:
-
- "D:P", "D:0", "D", "D:" or "D:auto" (D, P are integers. And P >= 1)
- - "D:P": device D partition P. Error occurs if device D has no
- partition table.
- - "D:0": device D.
- - "D" or "D:": device D partition 1 if device D has partition
- table, or the whole device D if has no partition
- table.
- - "D:auto": first partition in device D with bootable flag set.
- If none, first valid partition in device D. If no
- partition table then means device D.
-
- - FAT_ENV_FILE:
-
- It's a string of the FAT file name. This file use to store the
- environment.
-
- - CONFIG_FAT_WRITE:
- This must be enabled. Otherwise it cannot save the environment file.
-
-- CONFIG_ENV_IS_IN_MMC:
-
- Define this if you have an MMC device which you want to use for the
- environment.
-
- - CONFIG_SYS_MMC_ENV_DEV:
-
- Specifies which MMC device the environment is stored in.
-
- - CONFIG_SYS_MMC_ENV_PART (optional):
-
- Specifies which MMC partition the environment is stored in. If not
- set, defaults to partition 0, the user area. Common values might be
- 1 (first MMC boot partition), 2 (second MMC boot partition).
-
- - CONFIG_ENV_OFFSET:
- - CONFIG_ENV_SIZE:
-
- These two #defines specify the offset and size of the environment
- area within the specified MMC device.
-
- If offset is positive (the usual case), it is treated as relative to
- the start of the MMC partition. If offset is negative, it is treated
- as relative to the end of the MMC partition. This can be useful if
- your board may be fitted with different MMC devices, which have
- different sizes for the MMC partitions, and you always want the
- environment placed at the very end of the partition, to leave the
- maximum possible space before it, to store other data.
-
- These two values are in units of bytes, but must be aligned to an
- MMC sector boundary.
-
- - CONFIG_ENV_OFFSET_REDUND (optional):
-
- Specifies a second storage area, of CONFIG_ENV_SIZE size, used to
- hold a redundant copy of the environment data. This provides a
- valid backup copy in case the other copy is corrupted, e.g. due
- to a power failure during a "saveenv" operation.
-
- This value may also be positive or negative; this is handled in the
- same way as CONFIG_ENV_OFFSET.
-
- This value is also in units of bytes, but must also be aligned to
- an MMC sector boundary.
-
- - CONFIG_ENV_SIZE_REDUND (optional):
-
- This value need not be set, even when CONFIG_ENV_OFFSET_REDUND is
- set. If this value is set, it must be set to the same value as
- CONFIG_ENV_SIZE.
-
Please note that the environment is read-only until the monitor
has been relocated to RAM and a RAM copy of the environment has been
created; also, when using EEPROM you will have to use getenv_f()
select DM_SPI
select DM_GPIO
select DM_MMC
+ select LZO
imply CMD_GETTIME
imply CMD_HASH
imply CMD_IO
select DM_GPIO
select DM_SPI
select DM_SPI_FLASH
+ select USB
select USB_EHCI_HCD
imply CMD_FPGA_LOADMK
imply CMD_GETTIME
select DM_GPIO
select OF_CONTROL
imply FAT_WRITE
+ imply ENV_IS_IN_FAT
config TARGET_VEXPRESS_CA15_TC2
bool "Support vexpress_ca15_tc2"
select SUPPORT_SPL
select SYS_THUMB_BUILD
select CMD_POWEROFF
+ imply CMD_MTDPARTS
imply FIT
config ARCH_OMAP2PLUS
select ARCH_MISC_INIT
select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
select SYS_THUMB_BUILD
+ imply CMD_MTDPARTS
imply CRC32_VERIFY
imply FAT_WRITE
bool "Freescale Vybrid"
select CPU_V7
select SYS_FSL_ERRATUM_ESDHC111
+ imply CMD_MTDPARTS
config ARCH_ZYNQ
bool "Xilinx Zynq Platform"
select SPL_PINCTRL if SPL
select SUPPORT_SPL
imply FAT_WRITE
+ imply ENV_IS_IN_MMC
help
Support for UniPhier SoC family developed by Socionext Inc.
(formerly, System LSI Business Division of Panasonic Corporation)
source "arch/arm/cpu/armv7/ls102xa/Kconfig"
-source "arch/arm/cpu/armv7/mx7ulp/Kconfig"
+source "arch/arm/mach-imx/mx7ulp/Kconfig"
-source "arch/arm/cpu/armv7/mx7/Kconfig"
+source "arch/arm/mach-imx/mx7/Kconfig"
-source "arch/arm/cpu/armv7/mx6/Kconfig"
+source "arch/arm/mach-imx/mx6/Kconfig"
-source "arch/arm/cpu/armv7/mx5/Kconfig"
+source "arch/arm/mach-imx/mx5/Kconfig"
source "arch/arm/mach-omap2/Kconfig"
source "arch/arm/cpu/armv8/Kconfig"
-source "arch/arm/imx-common/Kconfig"
+source "arch/arm/mach-imx/Kconfig"
source "board/aries/m28evk/Kconfig"
source "board/bosch/shc/Kconfig"
ifeq ($(CONFIG_SPL_BUILD),y)
ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35))
-libs-y += arch/arm/imx-common/
+libs-y += arch/arm/mach-imx/
endif
else
ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs vf610))
-libs-y += arch/arm/imx-common/
+libs-y += arch/arm/mach-imx/
endif
endif
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
-#include <asm/imx-common/sys_proto.h>
+#include <asm/mach-imx/sys_proto.h>
#ifdef CONFIG_MMC_MXC
#include <asm/arch/mxcmmc.h>
#endif
#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
-#include <asm/imx-common/dma.h>
+#include <asm/mach-imx/dma.h>
#include <asm/arch/gpio.h>
#include <asm/arch/iomux.h>
#include <asm/arch/imx-regs.h>
obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/
obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/
obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/
-obj-$(if $(filter mx5,$(SOC)),y) += mx5/
-obj-$(CONFIG_MX6) += mx6/
-obj-$(CONFIG_MX7) += mx7/
-obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/
obj-$(CONFIG_RMOBILE) += rmobile/
obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
+++ /dev/null
-if ARCH_MX5
-
-config MX5
- bool
- default y
-
-config MX51
- bool
-
-config MX53
- bool
-
-choice
- prompt "MX5 board select"
- optional
-
-config TARGET_M53EVK
- bool "Support m53evk"
- select MX53
- select SUPPORT_SPL
-
-config TARGET_MX51EVK
- bool "Support mx51evk"
- select BOARD_LATE_INIT
- select MX51
-
-config TARGET_MX53ARD
- bool "Support mx53ard"
- select MX53
-
-config TARGET_MX53CX9020
- bool "Support CX9020"
- select BOARD_LATE_INIT
- select MX53
- select DM
- select DM_SERIAL
-
-config TARGET_MX53EVK
- bool "Support mx53evk"
- select BOARD_LATE_INIT
- select MX53
-
-config TARGET_MX53LOCO
- bool "Support mx53loco"
- select BOARD_LATE_INIT
- select MX53
-
-config TARGET_MX53SMD
- bool "Support mx53smd"
- select MX53
-
-config TARGET_TS4800
- bool "Support TS4800"
- select MX51
- select SYS_FSL_ERRATUM_ESDHC_A001
-
-config TARGET_USBARMORY
- bool "Support USB armory"
- select MX53
-
-endchoice
-
-config SYS_SOC
- default "mx5"
-
-source "board/aries/m53evk/Kconfig"
-source "board/beckhoff/mx53cx9020/Kconfig"
-source "board/freescale/mx51evk/Kconfig"
-source "board/freescale/mx53ard/Kconfig"
-source "board/freescale/mx53evk/Kconfig"
-source "board/freescale/mx53loco/Kconfig"
-source "board/freescale/mx53smd/Kconfig"
-source "board/inversepath/usbarmory/Kconfig"
-source "board/technologic/ts4800/Kconfig"
-
-endif
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2009 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := soc.o clock.o
-obj-y += lowlevel_init.o
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <linux/errno.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/clock.h>
-#include <div64.h>
-#include <asm/arch/sys_proto.h>
-
-enum pll_clocks {
- PLL1_CLOCK = 0,
- PLL2_CLOCK,
- PLL3_CLOCK,
-#ifdef CONFIG_MX53
- PLL4_CLOCK,
-#endif
- PLL_CLOCKS,
-};
-
-struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
- [PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR,
- [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
- [PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,
-#ifdef CONFIG_MX53
- [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
-#endif
-};
-
-#define AHB_CLK_ROOT 133333333
-#define SZ_DEC_1M 1000000
-#define PLL_PD_MAX 16 /* Actual pd+1 */
-#define PLL_MFI_MAX 15
-#define PLL_MFI_MIN 5
-#define ARM_DIV_MAX 8
-#define IPG_DIV_MAX 4
-#define AHB_DIV_MAX 8
-#define EMI_DIV_MAX 8
-#define NFC_DIV_MAX 8
-
-#define MX5_CBCMR 0x00015154
-#define MX5_CBCDR 0x02888945
-
-struct fixed_pll_mfd {
- u32 ref_clk_hz;
- u32 mfd;
-};
-
-const struct fixed_pll_mfd fixed_mfd[] = {
- {MXC_HCLK, 24 * 16},
-};
-
-struct pll_param {
- u32 pd;
- u32 mfi;
- u32 mfn;
- u32 mfd;
-};
-
-#define PLL_FREQ_MAX(ref_clk) (4 * (ref_clk) * PLL_MFI_MAX)
-#define PLL_FREQ_MIN(ref_clk) \
- ((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
-#define MAX_DDR_CLK 420000000
-#define NFC_CLK_MAX 34000000
-
-struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
-
-void set_usboh3_clk(void)
-{
- clrsetbits_le32(&mxc_ccm->cscmr1,
- MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK,
- MXC_CCM_CSCMR1_USBOH3_CLK_SEL(1));
- clrsetbits_le32(&mxc_ccm->cscdr1,
- MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK |
- MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK,
- MXC_CCM_CSCDR1_USBOH3_CLK_PRED(4) |
- MXC_CCM_CSCDR1_USBOH3_CLK_PODF(1));
-}
-
-void enable_usboh3_clk(bool enable)
-{
- unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
-
- clrsetbits_le32(&mxc_ccm->CCGR2,
- MXC_CCM_CCGR2_USBOH3_60M(MXC_CCM_CCGR_CG_MASK),
- MXC_CCM_CCGR2_USBOH3_60M(cg));
-}
-
-#ifdef CONFIG_SYS_I2C_MXC
-/* i2c_num can be from 0, to 1 for i.MX51 and 2 for i.MX53 */
-int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
-{
- u32 mask;
-
-#if defined(CONFIG_MX51)
- if (i2c_num > 1)
-#elif defined(CONFIG_MX53)
- if (i2c_num > 2)
-#endif
- return -EINVAL;
- mask = MXC_CCM_CCGR_CG_MASK <<
- (MXC_CCM_CCGR1_I2C1_OFFSET + (i2c_num << 1));
- if (enable)
- setbits_le32(&mxc_ccm->CCGR1, mask);
- else
- clrbits_le32(&mxc_ccm->CCGR1, mask);
- return 0;
-}
-#endif
-
-void set_usb_phy_clk(void)
-{
- clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
-}
-
-#if defined(CONFIG_MX51)
-void enable_usb_phy1_clk(bool enable)
-{
- unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
-
- clrsetbits_le32(&mxc_ccm->CCGR2,
- MXC_CCM_CCGR2_USB_PHY(MXC_CCM_CCGR_CG_MASK),
- MXC_CCM_CCGR2_USB_PHY(cg));
-}
-
-void enable_usb_phy2_clk(bool enable)
-{
- /* i.MX51 has a single USB PHY clock, so do nothing here. */
-}
-#elif defined(CONFIG_MX53)
-void enable_usb_phy1_clk(bool enable)
-{
- unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
-
- clrsetbits_le32(&mxc_ccm->CCGR4,
- MXC_CCM_CCGR4_USB_PHY1(MXC_CCM_CCGR_CG_MASK),
- MXC_CCM_CCGR4_USB_PHY1(cg));
-}
-
-void enable_usb_phy2_clk(bool enable)
-{
- unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
-
- clrsetbits_le32(&mxc_ccm->CCGR4,
- MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK),
- MXC_CCM_CCGR4_USB_PHY2(cg));
-}
-#endif
-
-/*
- * Calculate the frequency of PLLn.
- */
-static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)
-{
- uint32_t ctrl, op, mfd, mfn, mfi, pdf, ret;
- uint64_t refclk, temp;
- int32_t mfn_abs;
-
- ctrl = readl(&pll->ctrl);
-
- if (ctrl & MXC_DPLLC_CTL_HFSM) {
- mfn = readl(&pll->hfs_mfn);
- mfd = readl(&pll->hfs_mfd);
- op = readl(&pll->hfs_op);
- } else {
- mfn = readl(&pll->mfn);
- mfd = readl(&pll->mfd);
- op = readl(&pll->op);
- }
-
- mfd &= MXC_DPLLC_MFD_MFD_MASK;
- mfn &= MXC_DPLLC_MFN_MFN_MASK;
- pdf = op & MXC_DPLLC_OP_PDF_MASK;
- mfi = MXC_DPLLC_OP_MFI_RD(op);
-
- /* 21.2.3 */
- if (mfi < 5)
- mfi = 5;
-
- /* Sign extend */
- if (mfn >= 0x04000000) {
- mfn |= 0xfc000000;
- mfn_abs = -mfn;
- } else
- mfn_abs = mfn;
-
- refclk = infreq * 2;
- if (ctrl & MXC_DPLLC_CTL_DPDCK0_2_EN)
- refclk *= 2;
-
- do_div(refclk, pdf + 1);
- temp = refclk * mfn_abs;
- do_div(temp, mfd + 1);
- ret = refclk * mfi;
-
- if ((int)mfn < 0)
- ret -= temp;
- else
- ret += temp;
-
- return ret;
-}
-
-#ifdef CONFIG_MX51
-/*
- * This function returns the Frequency Pre-Multiplier clock.
- */
-static u32 get_fpm(void)
-{
- u32 mult;
- u32 ccr = readl(&mxc_ccm->ccr);
-
- if (ccr & MXC_CCM_CCR_FPM_MULT)
- mult = 1024;
- else
- mult = 512;
-
- return MXC_CLK32 * mult;
-}
-#endif
-
-/*
- * This function returns the low power audio clock.
- */
-static u32 get_lp_apm(void)
-{
- u32 ret_val = 0;
- u32 ccsr = readl(&mxc_ccm->ccsr);
-
- if (ccsr & MXC_CCM_CCSR_LP_APM)
-#if defined(CONFIG_MX51)
- ret_val = get_fpm();
-#elif defined(CONFIG_MX53)
- ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
-#endif
- else
- ret_val = MXC_HCLK;
-
- return ret_val;
-}
-
-/*
- * Get mcu main rate
- */
-u32 get_mcu_main_clk(void)
-{
- u32 reg, freq;
-
- reg = MXC_CCM_CACRR_ARM_PODF_RD(readl(&mxc_ccm->cacrr));
- freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
- return freq / (reg + 1);
-}
-
-/*
- * Get the rate of peripheral's root clock.
- */
-u32 get_periph_clk(void)
-{
- u32 reg;
-
- reg = readl(&mxc_ccm->cbcdr);
- if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
- return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
- reg = readl(&mxc_ccm->cbcmr);
- switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(reg)) {
- case 0:
- return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
- case 1:
- return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
- case 2:
- return get_lp_apm();
- default:
- return 0;
- }
- /* NOTREACHED */
-}
-
-/*
- * Get the rate of ipg clock.
- */
-static u32 get_ipg_clk(void)
-{
- uint32_t freq, reg, div;
-
- freq = get_ahb_clk();
-
- reg = readl(&mxc_ccm->cbcdr);
- div = MXC_CCM_CBCDR_IPG_PODF_RD(reg) + 1;
-
- return freq / div;
-}
-
-/*
- * Get the rate of ipg_per clock.
- */
-static u32 get_ipg_per_clk(void)
-{
- u32 freq, pred1, pred2, podf;
-
- if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
- return get_ipg_clk();
-
- if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL)
- freq = get_lp_apm();
- else
- freq = get_periph_clk();
- podf = readl(&mxc_ccm->cbcdr);
- pred1 = MXC_CCM_CBCDR_PERCLK_PRED1_RD(podf);
- pred2 = MXC_CCM_CBCDR_PERCLK_PRED2_RD(podf);
- podf = MXC_CCM_CBCDR_PERCLK_PODF_RD(podf);
- return freq / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
-}
-
-/* Get the output clock rate of a standard PLL MUX for peripherals. */
-static u32 get_standard_pll_sel_clk(u32 clk_sel)
-{
- u32 freq = 0;
-
- switch (clk_sel & 0x3) {
- case 0:
- freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
- break;
- case 1:
- freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
- break;
- case 2:
- freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
- break;
- case 3:
- freq = get_lp_apm();
- break;
- }
-
- return freq;
-}
-
-/*
- * Get the rate of uart clk.
- */
-static u32 get_uart_clk(void)
-{
- unsigned int clk_sel, freq, reg, pred, podf;
-
- reg = readl(&mxc_ccm->cscmr1);
- clk_sel = MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg);
- freq = get_standard_pll_sel_clk(clk_sel);
-
- reg = readl(&mxc_ccm->cscdr1);
- pred = MXC_CCM_CSCDR1_UART_CLK_PRED_RD(reg);
- podf = MXC_CCM_CSCDR1_UART_CLK_PODF_RD(reg);
- freq /= (pred + 1) * (podf + 1);
-
- return freq;
-}
-
-/*
- * get cspi clock rate.
- */
-static u32 imx_get_cspiclk(void)
-{
- u32 ret_val = 0, pdf, pre_pdf, clk_sel, freq;
- u32 cscmr1 = readl(&mxc_ccm->cscmr1);
- u32 cscdr2 = readl(&mxc_ccm->cscdr2);
-
- pre_pdf = MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(cscdr2);
- pdf = MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(cscdr2);
- clk_sel = MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(cscmr1);
- freq = get_standard_pll_sel_clk(clk_sel);
- ret_val = freq / ((pre_pdf + 1) * (pdf + 1));
- return ret_val;
-}
-
-/*
- * get esdhc clock rate.
- */
-static u32 get_esdhc_clk(u32 port)
-{
- u32 clk_sel = 0, pred = 0, podf = 0, freq = 0;
- u32 cscmr1 = readl(&mxc_ccm->cscmr1);
- u32 cscdr1 = readl(&mxc_ccm->cscdr1);
-
- switch (port) {
- case 0:
- clk_sel = MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(cscmr1);
- pred = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(cscdr1);
- podf = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(cscdr1);
- break;
- case 1:
- clk_sel = MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(cscmr1);
- pred = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(cscdr1);
- podf = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(cscdr1);
- break;
- case 2:
- if (cscmr1 & MXC_CCM_CSCMR1_ESDHC3_CLK_SEL)
- return get_esdhc_clk(1);
- else
- return get_esdhc_clk(0);
- case 3:
- if (cscmr1 & MXC_CCM_CSCMR1_ESDHC4_CLK_SEL)
- return get_esdhc_clk(1);
- else
- return get_esdhc_clk(0);
- default:
- break;
- }
-
- freq = get_standard_pll_sel_clk(clk_sel) / ((pred + 1) * (podf + 1));
- return freq;
-}
-
-static u32 get_axi_a_clk(void)
-{
- u32 cbcdr = readl(&mxc_ccm->cbcdr);
- u32 pdf = MXC_CCM_CBCDR_AXI_A_PODF_RD(cbcdr);
-
- return get_periph_clk() / (pdf + 1);
-}
-
-static u32 get_axi_b_clk(void)
-{
- u32 cbcdr = readl(&mxc_ccm->cbcdr);
- u32 pdf = MXC_CCM_CBCDR_AXI_B_PODF_RD(cbcdr);
-
- return get_periph_clk() / (pdf + 1);
-}
-
-static u32 get_emi_slow_clk(void)
-{
- u32 cbcdr = readl(&mxc_ccm->cbcdr);
- u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL;
- u32 pdf = MXC_CCM_CBCDR_EMI_PODF_RD(cbcdr);
-
- if (emi_clk_sel)
- return get_ahb_clk() / (pdf + 1);
-
- return get_periph_clk() / (pdf + 1);
-}
-
-static u32 get_ddr_clk(void)
-{
- u32 ret_val = 0;
- u32 cbcmr = readl(&mxc_ccm->cbcmr);
- u32 ddr_clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
-#ifdef CONFIG_MX51
- u32 cbcdr = readl(&mxc_ccm->cbcdr);
- if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) {
- u32 ddr_clk_podf = MXC_CCM_CBCDR_DDR_PODF_RD(cbcdr);
-
- ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
- ret_val /= ddr_clk_podf + 1;
-
- return ret_val;
- }
-#endif
- switch (ddr_clk_sel) {
- case 0:
- ret_val = get_axi_a_clk();
- break;
- case 1:
- ret_val = get_axi_b_clk();
- break;
- case 2:
- ret_val = get_emi_slow_clk();
- break;
- case 3:
- ret_val = get_ahb_clk();
- break;
- default:
- break;
- }
-
- return ret_val;
-}
-
-/*
- * The API of get mxc clocks.
- */
-unsigned int mxc_get_clock(enum mxc_clock clk)
-{
- switch (clk) {
- case MXC_ARM_CLK:
- return get_mcu_main_clk();
- case MXC_AHB_CLK:
- return get_ahb_clk();
- case MXC_IPG_CLK:
- return get_ipg_clk();
- case MXC_IPG_PERCLK:
- case MXC_I2C_CLK:
- return get_ipg_per_clk();
- case MXC_UART_CLK:
- return get_uart_clk();
- case MXC_CSPI_CLK:
- return imx_get_cspiclk();
- case MXC_ESDHC_CLK:
- return get_esdhc_clk(0);
- case MXC_ESDHC2_CLK:
- return get_esdhc_clk(1);
- case MXC_ESDHC3_CLK:
- return get_esdhc_clk(2);
- case MXC_ESDHC4_CLK:
- return get_esdhc_clk(3);
- case MXC_FEC_CLK:
- return get_ipg_clk();
- case MXC_SATA_CLK:
- return get_ahb_clk();
- case MXC_DDR_CLK:
- return get_ddr_clk();
- default:
- break;
- }
- return -EINVAL;
-}
-
-u32 imx_get_uartclk(void)
-{
- return get_uart_clk();
-}
-
-u32 imx_get_fecclk(void)
-{
- return get_ipg_clk();
-}
-
-static int gcd(int m, int n)
-{
- int t;
- while (m > 0) {
- if (n > m) {
- t = m;
- m = n;
- n = t;
- } /* swap */
- m -= n;
- }
- return n;
-}
-
-/*
- * This is to calculate various parameters based on reference clock and
- * targeted clock based on the equation:
- * t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1)
- * This calculation is based on a fixed MFD value for simplicity.
- */
-static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll)
-{
- u64 pd, mfi = 1, mfn, mfd, t1;
- u32 n_target = target;
- u32 n_ref = ref, i;
-
- /*
- * Make sure targeted freq is in the valid range.
- * Otherwise the following calculation might be wrong!!!
- */
- if (n_target < PLL_FREQ_MIN(ref) ||
- n_target > PLL_FREQ_MAX(ref)) {
- printf("Targeted peripheral clock should be"
- "within [%d - %d]\n",
- PLL_FREQ_MIN(ref) / SZ_DEC_1M,
- PLL_FREQ_MAX(ref) / SZ_DEC_1M);
- return -EINVAL;
- }
-
- for (i = 0; i < ARRAY_SIZE(fixed_mfd); i++) {
- if (fixed_mfd[i].ref_clk_hz == ref) {
- mfd = fixed_mfd[i].mfd;
- break;
- }
- }
-
- if (i == ARRAY_SIZE(fixed_mfd))
- return -EINVAL;
-
- /* Use n_target and n_ref to avoid overflow */
- for (pd = 1; pd <= PLL_PD_MAX; pd++) {
- t1 = n_target * pd;
- do_div(t1, (4 * n_ref));
- mfi = t1;
- if (mfi > PLL_MFI_MAX)
- return -EINVAL;
- else if (mfi < 5)
- continue;
- break;
- }
- /*
- * Now got pd and mfi already
- *
- * mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref;
- */
- t1 = n_target * pd;
- do_div(t1, 4);
- t1 -= n_ref * mfi;
- t1 *= mfd;
- do_div(t1, n_ref);
- mfn = t1;
- debug("ref=%d, target=%d, pd=%d," "mfi=%d,mfn=%d, mfd=%d\n",
- ref, n_target, (u32)pd, (u32)mfi, (u32)mfn, (u32)mfd);
- i = 1;
- if (mfn != 0)
- i = gcd(mfd, mfn);
- pll->pd = (u32)pd;
- pll->mfi = (u32)mfi;
- do_div(mfn, i);
- pll->mfn = (u32)mfn;
- do_div(mfd, i);
- pll->mfd = (u32)mfd;
-
- return 0;
-}
-
-#define calc_div(tgt_clk, src_clk, limit) ({ \
- u32 v = 0; \
- if (((src_clk) % (tgt_clk)) <= 100) \
- v = (src_clk) / (tgt_clk); \
- else \
- v = ((src_clk) / (tgt_clk)) + 1;\
- if (v > limit) \
- v = limit; \
- (v - 1); \
- })
-
-#define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \
- { \
- writel(0x1232, &pll->ctrl); \
- writel(0x2, &pll->config); \
- writel((((pd) - 1) << 0) | ((fi) << 4), \
- &pll->op); \
- writel(fn, &(pll->mfn)); \
- writel((fd) - 1, &pll->mfd); \
- writel((((pd) - 1) << 0) | ((fi) << 4), \
- &pll->hfs_op); \
- writel(fn, &pll->hfs_mfn); \
- writel((fd) - 1, &pll->hfs_mfd); \
- writel(0x1232, &pll->ctrl); \
- while (!readl(&pll->ctrl) & 0x1) \
- ;\
- }
-
-static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param)
-{
- u32 ccsr = readl(&mxc_ccm->ccsr);
- struct mxc_pll_reg *pll = mxc_plls[index];
-
- switch (index) {
- case PLL1_CLOCK:
- /* Switch ARM to PLL2 clock */
- writel(ccsr | MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
- &mxc_ccm->ccsr);
- CHANGE_PLL_SETTINGS(pll, pll_param->pd,
- pll_param->mfi, pll_param->mfn,
- pll_param->mfd);
- /* Switch back */
- writel(ccsr & ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
- &mxc_ccm->ccsr);
- break;
- case PLL2_CLOCK:
- /* Switch to pll2 bypass clock */
- writel(ccsr | MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
- &mxc_ccm->ccsr);
- CHANGE_PLL_SETTINGS(pll, pll_param->pd,
- pll_param->mfi, pll_param->mfn,
- pll_param->mfd);
- /* Switch back */
- writel(ccsr & ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
- &mxc_ccm->ccsr);
- break;
- case PLL3_CLOCK:
- /* Switch to pll3 bypass clock */
- writel(ccsr | MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
- &mxc_ccm->ccsr);
- CHANGE_PLL_SETTINGS(pll, pll_param->pd,
- pll_param->mfi, pll_param->mfn,
- pll_param->mfd);
- /* Switch back */
- writel(ccsr & ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
- &mxc_ccm->ccsr);
- break;
-#ifdef CONFIG_MX53
- case PLL4_CLOCK:
- /* Switch to pll4 bypass clock */
- writel(ccsr | MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
- &mxc_ccm->ccsr);
- CHANGE_PLL_SETTINGS(pll, pll_param->pd,
- pll_param->mfi, pll_param->mfn,
- pll_param->mfd);
- /* Switch back */
- writel(ccsr & ~MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
- &mxc_ccm->ccsr);
- break;
-#endif
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-/* Config CPU clock */
-static int config_core_clk(u32 ref, u32 freq)
-{
- int ret = 0;
- struct pll_param pll_param;
-
- memset(&pll_param, 0, sizeof(struct pll_param));
-
- /* The case that periph uses PLL1 is not considered here */
- ret = calc_pll_params(ref, freq, &pll_param);
- if (ret != 0) {
- printf("Error:Can't find pll parameters: %d\n", ret);
- return ret;
- }
-
- return config_pll_clk(PLL1_CLOCK, &pll_param);
-}
-
-static int config_nfc_clk(u32 nfc_clk)
-{
- u32 parent_rate = get_emi_slow_clk();
- u32 div;
-
- if (nfc_clk == 0)
- return -EINVAL;
- div = parent_rate / nfc_clk;
- if (div == 0)
- div++;
- if (parent_rate / div > NFC_CLK_MAX)
- div++;
- clrsetbits_le32(&mxc_ccm->cbcdr,
- MXC_CCM_CBCDR_NFC_PODF_MASK,
- MXC_CCM_CBCDR_NFC_PODF(div - 1));
- while (readl(&mxc_ccm->cdhipr) != 0)
- ;
- return 0;
-}
-
-void enable_nfc_clk(unsigned char enable)
-{
- unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
-
- clrsetbits_le32(&mxc_ccm->CCGR5,
- MXC_CCM_CCGR5_EMI_ENFC(MXC_CCM_CCGR_CG_MASK),
- MXC_CCM_CCGR5_EMI_ENFC(cg));
-}
-
-#ifdef CONFIG_FSL_IIM
-void enable_efuse_prog_supply(bool enable)
-{
- if (enable)
- setbits_le32(&mxc_ccm->cgpr,
- MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
- else
- clrbits_le32(&mxc_ccm->cgpr,
- MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
-}
-#endif
-
-/* Config main_bus_clock for periphs */
-static int config_periph_clk(u32 ref, u32 freq)
-{
- int ret = 0;
- struct pll_param pll_param;
-
- memset(&pll_param, 0, sizeof(struct pll_param));
-
- if (readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
- ret = calc_pll_params(ref, freq, &pll_param);
- if (ret != 0) {
- printf("Error:Can't find pll parameters: %d\n",
- ret);
- return ret;
- }
- switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(
- readl(&mxc_ccm->cbcmr))) {
- case 0:
- return config_pll_clk(PLL1_CLOCK, &pll_param);
- break;
- case 1:
- return config_pll_clk(PLL3_CLOCK, &pll_param);
- break;
- default:
- return -EINVAL;
- }
- }
-
- return 0;
-}
-
-static int config_ddr_clk(u32 emi_clk)
-{
- u32 clk_src;
- s32 shift = 0, clk_sel, div = 1;
- u32 cbcmr = readl(&mxc_ccm->cbcmr);
-
- if (emi_clk > MAX_DDR_CLK) {
- printf("Warning:DDR clock should not exceed %d MHz\n",
- MAX_DDR_CLK / SZ_DEC_1M);
- emi_clk = MAX_DDR_CLK;
- }
-
- clk_src = get_periph_clk();
- /* Find DDR clock input */
- clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
- switch (clk_sel) {
- case 0:
- shift = 16;
- break;
- case 1:
- shift = 19;
- break;
- case 2:
- shift = 22;
- break;
- case 3:
- shift = 10;
- break;
- default:
- return -EINVAL;
- }
-
- if ((clk_src % emi_clk) < 10000000)
- div = clk_src / emi_clk;
- else
- div = (clk_src / emi_clk) + 1;
- if (div > 8)
- div = 8;
-
- clrsetbits_le32(&mxc_ccm->cbcdr, 0x7 << shift, (div - 1) << shift);
- while (readl(&mxc_ccm->cdhipr) != 0)
- ;
- writel(0x0, &mxc_ccm->ccdr);
-
- return 0;
-}
-
-/*
- * This function assumes the expected core clock has to be changed by
- * modifying the PLL. This is NOT true always but for most of the times,
- * it is. So it assumes the PLL output freq is the same as the expected
- * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
- * In the latter case, it will try to increase the presc value until
- * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
- * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
- * on the targeted PLL and reference input clock to the PLL. Lastly,
- * it sets the register based on these values along with the dividers.
- * Note 1) There is no value checking for the passed-in divider values
- * so the caller has to make sure those values are sensible.
- * 2) Also adjust the NFC divider such that the NFC clock doesn't
- * exceed NFC_CLK_MAX.
- * 3) IPU HSP clock is independent of AHB clock. Even it can go up to
- * 177MHz for higher voltage, this function fixes the max to 133MHz.
- * 4) This function should not have allowed diag_printf() calls since
- * the serial driver has been stoped. But leave then here to allow
- * easy debugging by NOT calling the cyg_hal_plf_serial_stop().
- */
-int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
-{
- freq *= SZ_DEC_1M;
-
- switch (clk) {
- case MXC_ARM_CLK:
- if (config_core_clk(ref, freq))
- return -EINVAL;
- break;
- case MXC_PERIPH_CLK:
- if (config_periph_clk(ref, freq))
- return -EINVAL;
- break;
- case MXC_DDR_CLK:
- if (config_ddr_clk(freq))
- return -EINVAL;
- break;
- case MXC_NFC_CLK:
- if (config_nfc_clk(freq))
- return -EINVAL;
- break;
- default:
- printf("Warning:Unsupported or invalid clock type\n");
- }
-
- return 0;
-}
-
-#ifdef CONFIG_MX53
-/*
- * The clock for the external interface can be set to use internal clock
- * if fuse bank 4, row 3, bit 2 is set.
- * This is an undocumented feature and it was confirmed by Freescale's support:
- * Fuses (but not pins) may be used to configure SATA clocks.
- * Particularly the i.MX53 Fuse_Map contains the next information
- * about configuring SATA clocks : SATA_ALT_REF_CLK[1:0] (offset 0x180C)
- * '00' - 100MHz (External)
- * '01' - 50MHz (External)
- * '10' - 120MHz, internal (USB PHY)
- * '11' - Reserved
-*/
-void mxc_set_sata_internal_clock(void)
-{
- u32 *tmp_base =
- (u32 *)(IIM_BASE_ADDR + 0x180c);
-
- set_usb_phy_clk();
-
- clrsetbits_le32(tmp_base, 0x6, 0x4);
-}
-#endif
-
-/*
- * Dump some core clockes.
- */
-int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- u32 freq;
-
- freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
- printf("PLL1 %8d MHz\n", freq / 1000000);
- freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
- printf("PLL2 %8d MHz\n", freq / 1000000);
- freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
- printf("PLL3 %8d MHz\n", freq / 1000000);
-#ifdef CONFIG_MX53
- freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
- printf("PLL4 %8d MHz\n", freq / 1000000);
-#endif
-
- printf("\n");
- printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
- printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
- printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
- printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
-#ifdef CONFIG_MXC_SPI
- printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
-#endif
- return 0;
-}
-
-/***************************************************/
-
-U_BOOT_CMD(
- clocks, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks,
- "display clocks",
- ""
-);
+++ /dev/null
-/*
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <asm/arch/imx-regs.h>
-#include <generated/asm-offsets.h>
-#include <linux/linkage.h>
-
-.section ".text.init", "x"
-
-.macro init_arm_erratum
- /* ARM erratum ID #468414 */
- mrc 15, 0, r1, c1, c0, 1
- orr r1, r1, #(1 << 5) /* enable L1NEON bit */
- mcr 15, 0, r1, c1, c0, 1
-.endm
-
-/*
- * L2CC Cache setup/invalidation/disable
- */
-.macro init_l2cc
- /* explicitly disable L2 cache */
- mrc 15, 0, r0, c1, c0, 1
- bic r0, r0, #0x2
- mcr 15, 0, r0, c1, c0, 1
-
- /* reconfigure L2 cache aux control reg */
- ldr r0, =0xC0 | /* tag RAM */ \
- 0x4 | /* data RAM */ \
- 1 << 24 | /* disable write allocate delay */ \
- 1 << 23 | /* disable write allocate combine */ \
- 1 << 22 /* disable write allocate */
-
-#if defined(CONFIG_MX51)
- ldr r3, [r4, #ROM_SI_REV]
- cmp r3, #0x10
-
- /* disable write combine for TO 2 and lower revs */
- orrls r0, r0, #1 << 25
-#endif
-
- mcr 15, 1, r0, c9, c0, 2
-
- /* enable L2 cache */
- mrc 15, 0, r0, c1, c0, 1
- orr r0, r0, #2
- mcr 15, 0, r0, c1, c0, 1
-
-.endm /* init_l2cc */
-
-/* AIPS setup - Only setup MPROTx registers.
- * The PACR default values are good.*/
-.macro init_aips
- /*
- * Set all MPROTx to be non-bufferable, trusted for R/W,
- * not forced to user-mode.
- */
- ldr r0, =AIPS1_BASE_ADDR
- ldr r1, =0x77777777
- str r1, [r0, #0x0]
- str r1, [r0, #0x4]
- ldr r0, =AIPS2_BASE_ADDR
- str r1, [r0, #0x0]
- str r1, [r0, #0x4]
- /*
- * Clear the on and off peripheral modules Supervisor Protect bit
- * for SDMA to access them. Did not change the AIPS control registers
- * (offset 0x20) access type
- */
-.endm /* init_aips */
-
-/* M4IF setup */
-.macro init_m4if
-#ifdef CONFIG_MX51
- /* VPU and IPU given higher priority (0x4)
- * IPU accesses with ID=0x1 given highest priority (=0xA)
- */
- ldr r0, =M4IF_BASE_ADDR
-
- ldr r1, =0x00000203
- str r1, [r0, #0x40]
-
- str r4, [r0, #0x44]
-
- ldr r1, =0x00120125
- str r1, [r0, #0x9C]
-
- ldr r1, =0x001901A3
- str r1, [r0, #0x48]
-
-#endif
-.endm /* init_m4if */
-
-.macro setup_pll pll, freq
- ldr r0, =\pll
- adr r2, W_DP_\freq
- bl setup_pll_func
-.endm
-
-#define W_DP_OP 0
-#define W_DP_MFD 4
-#define W_DP_MFN 8
-
-setup_pll_func:
- ldr r1, =0x00001232
- str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
- mov r1, #0x2
- str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
-
- ldr r1, [r2, #W_DP_OP]
- str r1, [r0, #PLL_DP_OP]
- str r1, [r0, #PLL_DP_HFS_OP]
-
- ldr r1, [r2, #W_DP_MFD]
- str r1, [r0, #PLL_DP_MFD]
- str r1, [r0, #PLL_DP_HFS_MFD]
-
- ldr r1, [r2, #W_DP_MFN]
- str r1, [r0, #PLL_DP_MFN]
- str r1, [r0, #PLL_DP_HFS_MFN]
-
- ldr r1, =0x00001232
- str r1, [r0, #PLL_DP_CTL]
-1: ldr r1, [r0, #PLL_DP_CTL]
- ands r1, r1, #0x1
- beq 1b
-
- /* r10 saved upper lr */
- mov pc, lr
-
-.macro setup_pll_errata pll, freq
- ldr r2, =\pll
- str r4, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
- ldr r1, =0x00001236
- str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */
-1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */
- ands r1, r1, #0x1
- beq 1b
-
- ldr r5, \freq
- str r5, [r2, #PLL_DP_MFN] /* Modify MFN value */
- str r5, [r2, #PLL_DP_HFS_MFN]
-
- mov r1, #0x1
- str r1, [r2, #PLL_DP_CONFIG] /* Reload MFN value */
-
-2: ldr r1, [r2, #PLL_DP_CONFIG]
- tst r1, #1
- bne 2b
-
- ldr r1, =100 /* Wait at least 4 us */
-3: subs r1, r1, #1
- bge 3b
-
- mov r1, #0x2
- str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
-.endm
-
-.macro init_clock
-#if defined (CONFIG_MX51)
- ldr r0, =CCM_BASE_ADDR
-
- /* Gate of clocks to the peripherals first */
- ldr r1, =0x3FFFFFFF
- str r1, [r0, #CLKCTL_CCGR0]
- str r4, [r0, #CLKCTL_CCGR1]
- str r4, [r0, #CLKCTL_CCGR2]
- str r4, [r0, #CLKCTL_CCGR3]
-
- ldr r1, =0x00030000
- str r1, [r0, #CLKCTL_CCGR4]
- ldr r1, =0x00FFF030
- str r1, [r0, #CLKCTL_CCGR5]
- ldr r1, =0x00000300
- str r1, [r0, #CLKCTL_CCGR6]
-
- /* Disable IPU and HSC dividers */
- mov r1, #0x60000
- str r1, [r0, #CLKCTL_CCDR]
-
- /* Make sure to switch the DDR away from PLL 1 */
- ldr r1, =0x19239145
- str r1, [r0, #CLKCTL_CBCDR]
- /* make sure divider effective */
-1: ldr r1, [r0, #CLKCTL_CDHIPR]
- cmp r1, #0x0
- bne 1b
-
- /* Switch ARM to step clock */
- mov r1, #0x4
- str r1, [r0, #CLKCTL_CCSR]
-
-#if defined(CONFIG_MX51_PLL_ERRATA)
- setup_pll PLL1_BASE_ADDR, 864
- setup_pll_errata PLL1_BASE_ADDR, W_DP_MFN_800_DIT
-#else
- setup_pll PLL1_BASE_ADDR, 800
-#endif
-
- setup_pll PLL3_BASE_ADDR, 665
-
- /* Switch peripheral to PLL 3 */
- ldr r0, =CCM_BASE_ADDR
- ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL
- str r1, [r0, #CLKCTL_CBCMR]
- ldr r1, =0x13239145
- str r1, [r0, #CLKCTL_CBCDR]
- setup_pll PLL2_BASE_ADDR, 665
-
- /* Switch peripheral to PLL2 */
- ldr r0, =CCM_BASE_ADDR
- ldr r1, =0x19239145
- str r1, [r0, #CLKCTL_CBCDR]
- ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
- str r1, [r0, #CLKCTL_CBCMR]
-
- setup_pll PLL3_BASE_ADDR, 216
-
- /* Set the platform clock dividers */
- ldr r0, =ARM_BASE_ADDR
- ldr r1, =0x00000725
- str r1, [r0, #0x14]
-
- ldr r0, =CCM_BASE_ADDR
-
- /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
- ldr r3, [r4, #ROM_SI_REV]
- cmp r3, #0x10
- movls r1, #0x1
- movhi r1, #0
-
- str r1, [r0, #CLKCTL_CACRR]
-
- /* Switch ARM back to PLL 1 */
- str r4, [r0, #CLKCTL_CCSR]
-
- /* setup the rest */
- /* Use lp_apm (24MHz) source for perclk */
- ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
- str r1, [r0, #CLKCTL_CBCMR]
- /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
- ldr r1, =CONFIG_SYS_CLKTL_CBCDR
- str r1, [r0, #CLKCTL_CBCDR]
-
- /* Restore the default values in the Gate registers */
- ldr r1, =0xFFFFFFFF
- str r1, [r0, #CLKCTL_CCGR0]
- str r1, [r0, #CLKCTL_CCGR1]
- str r1, [r0, #CLKCTL_CCGR2]
- str r1, [r0, #CLKCTL_CCGR3]
- str r1, [r0, #CLKCTL_CCGR4]
- str r1, [r0, #CLKCTL_CCGR5]
- str r1, [r0, #CLKCTL_CCGR6]
-
- /* Use PLL 2 for UART's, get 66.5MHz from it */
- ldr r1, =0xA5A2A020
- str r1, [r0, #CLKCTL_CSCMR1]
- ldr r1, =0x00C30321
- str r1, [r0, #CLKCTL_CSCDR1]
- /* make sure divider effective */
-1: ldr r1, [r0, #CLKCTL_CDHIPR]
- cmp r1, #0x0
- bne 1b
-
- str r4, [r0, #CLKCTL_CCDR]
-
- /* for cko - for ARM div by 8 */
- mov r1, #0x000A0000
- add r1, r1, #0x00000F0
- str r1, [r0, #CLKCTL_CCOSR]
-#else /* CONFIG_MX53 */
- ldr r0, =CCM_BASE_ADDR
-
- /* Gate of clocks to the peripherals first */
- ldr r1, =0x3FFFFFFF
- str r1, [r0, #CLKCTL_CCGR0]
- str r4, [r0, #CLKCTL_CCGR1]
- str r4, [r0, #CLKCTL_CCGR2]
- str r4, [r0, #CLKCTL_CCGR3]
- str r4, [r0, #CLKCTL_CCGR7]
- ldr r1, =0x00030000
- str r1, [r0, #CLKCTL_CCGR4]
- ldr r1, =0x00FFF030
- str r1, [r0, #CLKCTL_CCGR5]
- ldr r1, =0x0F00030F
- str r1, [r0, #CLKCTL_CCGR6]
-
- /* Switch ARM to step clock */
- mov r1, #0x4
- str r1, [r0, #CLKCTL_CCSR]
-
- setup_pll PLL1_BASE_ADDR, 800
-
- setup_pll PLL3_BASE_ADDR, 400
-
- /* Switch peripheral to PLL3 */
- ldr r0, =CCM_BASE_ADDR
- ldr r1, =0x00015154
- str r1, [r0, #CLKCTL_CBCMR]
- ldr r1, =0x02898945
- str r1, [r0, #CLKCTL_CBCDR]
- /* make sure change is effective */
-1: ldr r1, [r0, #CLKCTL_CDHIPR]
- cmp r1, #0x0
- bne 1b
-
- setup_pll PLL2_BASE_ADDR, 400
-
- /* Switch peripheral to PLL2 */
- ldr r0, =CCM_BASE_ADDR
- ldr r1, =0x00888945
- str r1, [r0, #CLKCTL_CBCDR]
-
- ldr r1, =0x00016154
- str r1, [r0, #CLKCTL_CBCMR]
-
- /*change uart clk parent to pll2*/
- ldr r1, [r0, #CLKCTL_CSCMR1]
- and r1, r1, #0xfcffffff
- orr r1, r1, #0x01000000
- str r1, [r0, #CLKCTL_CSCMR1]
-
- /* make sure change is effective */
-1: ldr r1, [r0, #CLKCTL_CDHIPR]
- cmp r1, #0x0
- bne 1b
-
- setup_pll PLL3_BASE_ADDR, 216
-
- setup_pll PLL4_BASE_ADDR, 455
-
- /* Set the platform clock dividers */
- ldr r0, =ARM_BASE_ADDR
- ldr r1, =0x00000124
- str r1, [r0, #0x14]
-
- ldr r0, =CCM_BASE_ADDR
- mov r1, #0
- str r1, [r0, #CLKCTL_CACRR]
-
- /* Switch ARM back to PLL 1. */
- mov r1, #0x0
- str r1, [r0, #CLKCTL_CCSR]
-
- /* make uart div=6 */
- ldr r1, [r0, #CLKCTL_CSCDR1]
- and r1, r1, #0xffffffc0
- orr r1, r1, #0x0a
- str r1, [r0, #CLKCTL_CSCDR1]
-
- /* Restore the default values in the Gate registers */
- ldr r1, =0xFFFFFFFF
- str r1, [r0, #CLKCTL_CCGR0]
- str r1, [r0, #CLKCTL_CCGR1]
- str r1, [r0, #CLKCTL_CCGR2]
- str r1, [r0, #CLKCTL_CCGR3]
- str r1, [r0, #CLKCTL_CCGR4]
- str r1, [r0, #CLKCTL_CCGR5]
- str r1, [r0, #CLKCTL_CCGR6]
- str r1, [r0, #CLKCTL_CCGR7]
-
- mov r1, #0x00000
- str r1, [r0, #CLKCTL_CCDR]
-
- /* for cko - for ARM div by 8 */
- mov r1, #0x000A0000
- add r1, r1, #0x00000F0
- str r1, [r0, #CLKCTL_CCOSR]
-
-#endif /* CONFIG_MX53 */
-.endm
-
-ENTRY(lowlevel_init)
- mov r10, lr
- mov r4, #0 /* Fix R4 to 0 */
-
-#if defined(CONFIG_SYS_MAIN_PWR_ON)
- ldr r0, =GPIO1_BASE_ADDR
- ldr r1, [r0, #0x0]
- orr r1, r1, #1 << 23
- str r1, [r0, #0x0]
- ldr r1, [r0, #0x4]
- orr r1, r1, #1 << 23
- str r1, [r0, #0x4]
-#endif
-
- init_arm_erratum
-
- init_l2cc
-
- init_aips
-
- init_m4if
-
- init_clock
-
- mov pc, r10
-ENDPROC(lowlevel_init)
-
-/* Board level setting value */
-#if defined(CONFIG_MX51_PLL_ERRATA)
-W_DP_864: .word DP_OP_864
- .word DP_MFD_864
- .word DP_MFN_864
-W_DP_MFN_800_DIT: .word DP_MFN_800_DIT
-#else
-W_DP_800: .word DP_OP_800
- .word DP_MFD_800
- .word DP_MFN_800
-#endif
-#if defined(CONFIG_MX51)
-W_DP_665: .word DP_OP_665
- .word DP_MFD_665
- .word DP_MFN_665
-#endif
-W_DP_216: .word DP_OP_216
- .word DP_MFD_216
- .word DP_MFN_216
-W_DP_400: .word DP_OP_400
- .word DP_MFD_400
- .word DP_MFN_400
-W_DP_455: .word DP_OP_455
- .word DP_MFD_455
- .word DP_MFN_455
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-
-#include <linux/errno.h>
-#include <asm/io.h>
-#include <asm/imx-common/boot_mode.h>
-
-#if !(defined(CONFIG_MX51) || defined(CONFIG_MX53))
-#error "CPU_TYPE not defined"
-#endif
-
-u32 get_cpu_rev(void)
-{
-#ifdef CONFIG_MX51
- int system_rev = 0x51000;
-#else
- int system_rev = 0x53000;
-#endif
- int reg = __raw_readl(ROM_SI_REV);
-
-#if defined(CONFIG_MX51)
- switch (reg) {
- case 0x02:
- system_rev |= CHIP_REV_1_1;
- break;
- case 0x10:
- if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
- system_rev |= CHIP_REV_2_5;
- else
- system_rev |= CHIP_REV_2_0;
- break;
- case 0x20:
- system_rev |= CHIP_REV_3_0;
- break;
- default:
- system_rev |= CHIP_REV_1_0;
- break;
- }
-#else
- if (reg < 0x20)
- system_rev |= CHIP_REV_1_0;
- else
- system_rev |= reg;
-#endif
- return system_rev;
-}
-
-#ifdef CONFIG_REVISION_TAG
-u32 __weak get_board_rev(void)
-{
- return get_cpu_rev();
-}
-#endif
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
-}
-#endif
-
-#if defined(CONFIG_FEC_MXC)
-void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
-{
- int i;
- struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
- struct fuse_bank *bank = &iim->bank[1];
- struct fuse_bank1_regs *fuse =
- (struct fuse_bank1_regs *)bank->fuse_regs;
-
- for (i = 0; i < 6; i++)
- mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
-}
-#endif
-
-#ifdef CONFIG_MX53
-void boot_mode_apply(unsigned cfg_val)
-{
- writel(cfg_val, &((struct srtc_regs *)SRTC_BASE_ADDR)->lpgr);
-}
-/*
- * cfg_val will be used for
- * Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
- *
- * If bit 28 of LPGR is set upon watchdog reset,
- * bits[25:0] of LPGR will move to SBMR.
- */
-const struct boot_mode soc_boot_modes[] = {
- {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
- /* usb or serial download */
- {"usb", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x13)},
- {"sata", MAKE_CFGVAL(0x28, 0x00, 0x00, 0x12)},
- {"escpi1:0", MAKE_CFGVAL(0x38, 0x20, 0x00, 0x12)},
- {"escpi1:1", MAKE_CFGVAL(0x38, 0x20, 0x04, 0x12)},
- {"escpi1:2", MAKE_CFGVAL(0x38, 0x20, 0x08, 0x12)},
- {"escpi1:3", MAKE_CFGVAL(0x38, 0x20, 0x0c, 0x12)},
- /* 4 bit bus width */
- {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
- {"esdhc2", MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
- {"esdhc3", MAKE_CFGVAL(0x40, 0x20, 0x10, 0x12)},
- {"esdhc4", MAKE_CFGVAL(0x40, 0x20, 0x18, 0x12)},
- {NULL, 0},
-};
-#endif
+++ /dev/null
-if ARCH_MX6
-
-config MX6
- bool
- default y
- select ARM_ERRATA_743622 if !MX6UL
- select ARM_ERRATA_751472 if !MX6UL
- select ARM_ERRATA_761320 if !MX6UL
- select ARM_ERRATA_794072 if !MX6UL
- imply CMD_FUSE
-
-config MX6D
- bool
-
-config MX6DL
- bool
-
-config MX6Q
- bool
-
-config MX6QDL
- bool
-
-config MX6S
- bool
-
-config MX6SL
- bool
-
-config MX6SX
- select ROM_UNIFIED_SECTIONS
- bool
-
-config MX6SLL
- select ROM_UNIFIED_SECTIONS
- bool
-
-config MX6UL
- select SYS_L2CACHE_OFF
- select ROM_UNIFIED_SECTIONS
- bool
-
-config MX6UL_LITESOM
- bool
- select MX6UL
- select DM
- select DM_THERMAL
- select SUPPORT_SPL
-
-config MX6UL_OPOS6UL
- bool
- select MX6UL
- select BOARD_LATE_INIT
- select DM
- select DM_GPIO
- select DM_MMC
- select DM_THERMAL
- select SUPPORT_SPL
-
-config MX6ULL
- bool
- select MX6UL
-
-config MX6_DDRCAL
- bool "Include dynamic DDR calibration routines"
- depends on SPL
- default n
- help
- Say "Y" if your board uses dynamic (per-boot) DDR calibration.
- If unsure, say N.
-
-choice
- prompt "MX6 board select"
- optional
-
-config TARGET_ADVANTECH_DMS_BA16
- bool "Advantech dms-ba16"
- select BOARD_LATE_INIT
- select MX6Q
- imply CMD_SATA
-
-config TARGET_APALIS_IMX6
- bool "Toradex Apalis iMX6 board"
- select BOARD_LATE_INIT
- select SUPPORT_SPL
- select DM
- select DM_SERIAL
- select DM_THERMAL
- imply CMD_SATA
-
-config TARGET_ARISTAINETOS
- bool "aristainetos"
-
-config TARGET_ARISTAINETOS2
- bool "aristainetos2"
- select BOARD_LATE_INIT
-
-config TARGET_ARISTAINETOS2B
- bool "Support aristainetos2-revB"
- select BOARD_LATE_INIT
-
-config TARGET_CGTQMX6EVAL
- bool "cgtqmx6eval"
- select BOARD_LATE_INIT
- select SUPPORT_SPL
- select DM
- select DM_THERMAL
-
-config TARGET_CM_FX6
- bool "CM-FX6"
- select SUPPORT_SPL
- select DM
- select DM_SERIAL
- select DM_GPIO
-
-config TARGET_COLIBRI_IMX6
- bool "Toradex Colibri iMX6 board"
- select BOARD_LATE_INIT
- select SUPPORT_SPL
- select DM
- select DM_SERIAL
- select DM_THERMAL
-
-config TARGET_EMBESTMX6BOARDS
- bool "embestmx6boards"
- select BOARD_LATE_INIT
-
-config TARGET_GE_B450V3
- bool "General Electric B450v3"
- select BOARD_LATE_INIT
- select MX6Q
-
-config TARGET_GE_B650V3
- bool "General Electric B650v3"
- select BOARD_LATE_INIT
- select MX6Q
-
-config TARGET_GE_B850V3
- bool "General Electric B850v3"
- select BOARD_LATE_INIT
- select MX6Q
-
-config TARGET_GW_VENTANA
- bool "gw_ventana"
- select SUPPORT_SPL
- imply CMD_SATA
-
-config TARGET_KOSAGI_NOVENA
- bool "Kosagi Novena"
- select BOARD_LATE_INIT
- select SUPPORT_SPL
-
-config TARGET_MCCMON6
- bool "mccmon6"
- select SUPPORT_SPL
-
-config TARGET_MX6CUBOXI
- bool "Solid-run mx6 boards"
- select BOARD_LATE_INIT
- select SUPPORT_SPL
-
-config TARGET_MX6LOGICPD
- bool "Logic PD i.MX6 SOM"
- select BOARD_EARLY_INIT_F
- select BOARD_LATE_INIT
- select DM
- select DM_ETH
- select DM_GPIO
- select DM_I2C
- select DM_MMC
- select DM_PMIC
- select DM_REGULATOR
- select OF_CONTROL
-
-config TARGET_MX6QARM2
- bool "mx6qarm2"
-
-config TARGET_MX6Q_ICORE
- bool "Support Engicam i.Core"
- select BOARD_LATE_INIT
- select MX6QDL
- select OF_CONTROL
- select SPL_OF_LIBFDT
- select DM
- select DM_ETH
- select DM_GPIO
- select DM_I2C
- select DM_MMC
- select DM_THERMAL
- select SUPPORT_SPL
- select SPL_LOAD_FIT
-
-config TARGET_MX6Q_ICORE_RQS
- bool "Support Engicam i.Core RQS"
- select BOARD_LATE_INIT
- select MX6QDL
- select OF_CONTROL
- select SPL_OF_LIBFDT
- select DM
- select DM_ETH
- select DM_GPIO
- select DM_I2C
- select DM_MMC
- select DM_THERMAL
- select SUPPORT_SPL
- select SPL_LOAD_FIT
-
-config TARGET_MX6QSABREAUTO
- bool "mx6qsabreauto"
- select BOARD_LATE_INIT
- select DM
- select DM_THERMAL
- select BOARD_EARLY_INIT_F
-
-config TARGET_MX6SABRESD
- bool "mx6sabresd"
- select BOARD_LATE_INIT
- select SUPPORT_SPL
- select DM
- select DM_THERMAL
- select BOARD_EARLY_INIT_F
-
-config TARGET_MX6SLEVK
- bool "mx6slevk"
- select SUPPORT_SPL
-
-config TARGET_MX6SLLEVK
- bool "mx6sll evk"
- select BOARD_LATE_INIT
- select MX6SLL
- select DM
- select DM_THERMAL
-
-config TARGET_MX6SXSABRESD
- bool "mx6sxsabresd"
- select MX6SX
- select SUPPORT_SPL
- select DM
- select DM_THERMAL
- select BOARD_EARLY_INIT_F
-
-config TARGET_MX6SXSABREAUTO
- bool "mx6sxsabreauto"
- select BOARD_LATE_INIT
- select MX6SX
- select DM
- select DM_THERMAL
- select BOARD_EARLY_INIT_F
-
-config TARGET_MX6UL_9X9_EVK
- bool "mx6ul_9x9_evk"
- select BOARD_LATE_INIT
- select MX6UL
- select DM
- select DM_THERMAL
- select SUPPORT_SPL
-
-config TARGET_MX6UL_14X14_EVK
- select BOARD_LATE_INIT
- bool "mx6ul_14x14_evk"
- select MX6UL
- select DM
- select DM_THERMAL
- select SUPPORT_SPL
-
-config TARGET_MX6UL_GEAM
- bool "Support Engicam GEAM6UL"
- select BOARD_LATE_INIT
- select MX6UL
- select OF_CONTROL
- select DM
- select DM_ETH
- select DM_GPIO
- select DM_I2C
- select DM_MMC
- select DM_THERMAL
- select SUPPORT_SPL
-config TARGET_MX6UL_ISIOT
- bool "Support Engicam Is.IoT MX6UL"
- select BOARD_LATE_INIT
- select MX6UL
- select OF_CONTROL
- select DM
- select DM_ETH
- select DM_GPIO
- select DM_I2C
- select DM_MMC
- select DM_THERMAL
- select SUPPORT_SPL
-
-config TARGET_MX6ULL_14X14_EVK
- bool "Support mx6ull_14x14_evk"
- select BOARD_LATE_INIT
- select MX6ULL
- select DM
- select DM_THERMAL
-
-config TARGET_NITROGEN6X
- bool "nitrogen6x"
-
-config TARGET_OPOS6ULDEV
- bool "Armadeus OPOS6ULDev board"
- select MX6UL_OPOS6UL
-
-config TARGET_OT1200
- bool "Bachmann OT1200"
- select SUPPORT_SPL
- imply CMD_SATA
-
-config TARGET_PICO_IMX6UL
- bool "PICO-IMX6UL-EMMC"
- select MX6UL
-
-config TARGET_LITEBOARD
- bool "Grinn liteBoard (i.MX6UL)"
- select BOARD_LATE_INIT
- select MX6UL_LITESOM
-
-config TARGET_PLATINUM_PICON
- bool "platinum-picon"
- select SUPPORT_SPL
-
-config TARGET_PLATINUM_TITANIUM
- bool "platinum-titanium"
- select SUPPORT_SPL
-
-config TARGET_PCM058
- bool "Phytec PCM058 i.MX6 Quad"
- select BOARD_LATE_INIT
- select SUPPORT_SPL
-
-config TARGET_SECOMX6
- bool "secomx6 boards"
-
-config TARGET_TBS2910
- bool "TBS2910 Matrix ARM mini PC"
-
-config TARGET_TITANIUM
- bool "titanium"
-
-config TARGET_TQMA6
- bool "TQ Systems TQMa6 board"
- select BOARD_LATE_INIT
-
-config TARGET_UDOO
- bool "udoo"
- select BOARD_LATE_INIT
- select SUPPORT_SPL
-
-config TARGET_UDOO_NEO
- bool "UDOO Neo"
- select BOARD_LATE_INIT
- select SUPPORT_SPL
- select MX6SX
- select DM
- select DM_THERMAL
-
-config TARGET_SAMTEC_VINING_2000
- bool "samtec VIN|ING 2000"
- select BOARD_LATE_INIT
- select MX6SX
- select DM
- select DM_THERMAL
-
-config TARGET_WANDBOARD
- bool "wandboard"
- select BOARD_LATE_INIT
- select SUPPORT_SPL
-
-config TARGET_WARP
- bool "WaRP"
- select BOARD_LATE_INIT
-
-config TARGET_XPRESS
- bool "CCV xPress"
- select BOARD_LATE_INIT
- select MX6UL
- select DM
- select DM_THERMAL
- select SUPPORT_SPL
-
-config TARGET_ZC5202
- bool "zc5202"
- select BOARD_LATE_INIT
- select SUPPORT_SPL
- select DM
- select DM_THERMAL
-
-config TARGET_ZC5601
- bool "zc5601"
- select BOARD_LATE_INIT
- select SUPPORT_SPL
- select DM
- select DM_THERMAL
-
-endchoice
-
-config SYS_SOC
- default "mx6"
-
-source "board/ge/bx50v3/Kconfig"
-source "board/advantech/dms-ba16/Kconfig"
-source "board/aristainetos/Kconfig"
-source "board/armadeus/opos6uldev/Kconfig"
-source "board/bachmann/ot1200/Kconfig"
-source "board/barco/platinum/Kconfig"
-source "board/barco/titanium/Kconfig"
-source "board/boundary/nitrogen6x/Kconfig"
-source "board/ccv/xpress/Kconfig"
-source "board/compulab/cm_fx6/Kconfig"
-source "board/congatec/cgtqmx6eval/Kconfig"
-source "board/el/el6x/Kconfig"
-source "board/embest/mx6boards/Kconfig"
-source "board/engicam/geam6ul/Kconfig"
-source "board/engicam/icorem6/Kconfig"
-source "board/engicam/icorem6_rqs/Kconfig"
-source "board/engicam/isiotmx6ul/Kconfig"
-source "board/freescale/mx6qarm2/Kconfig"
-source "board/freescale/mx6qsabreauto/Kconfig"
-source "board/freescale/mx6sabresd/Kconfig"
-source "board/freescale/mx6slevk/Kconfig"
-source "board/freescale/mx6sllevk/Kconfig"
-source "board/freescale/mx6sxsabresd/Kconfig"
-source "board/freescale/mx6sxsabreauto/Kconfig"
-source "board/freescale/mx6ul_14x14_evk/Kconfig"
-source "board/freescale/mx6ullevk/Kconfig"
-source "board/grinn/liteboard/Kconfig"
-source "board/phytec/pcm058/Kconfig"
-source "board/gateworks/gw_ventana/Kconfig"
-source "board/kosagi/novena/Kconfig"
-source "board/samtec/vining_2000/Kconfig"
-source "board/liebherr/mccmon6/Kconfig"
-source "board/logicpd/imx6/Kconfig"
-source "board/seco/Kconfig"
-source "board/solidrun/mx6cuboxi/Kconfig"
-source "board/technexion/pico-imx6ul/Kconfig"
-source "board/tbs/tbs2910/Kconfig"
-source "board/tqc/tqma6/Kconfig"
-source "board/toradex/apalis_imx6/Kconfig"
-source "board/toradex/colibri_imx6/Kconfig"
-source "board/udoo/Kconfig"
-source "board/udoo/neo/Kconfig"
-source "board/wandboard/Kconfig"
-source "board/warp/Kconfig"
-
-endif
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2011 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := soc.o clock.o
-obj-$(CONFIG_SPL_BUILD) += ddr.o
-obj-$(CONFIG_MP) += mp.o
-obj-$(CONFIG_MX6UL_LITESOM) += litesom.o
-obj-$(CONFIG_MX6UL_OPOS6UL) += opos6ul.o
+++ /dev/null
-/*
- * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <div64.h>
-#include <asm/io.h>
-#include <linux/errno.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-
-enum pll_clocks {
- PLL_SYS, /* System PLL */
- PLL_BUS, /* System Bus PLL*/
- PLL_USBOTG, /* OTG USB PLL */
- PLL_ENET, /* ENET PLL */
- PLL_AUDIO, /* AUDIO PLL */
- PLL_VIDEO, /* AUDIO PLL */
-};
-
-struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
-#ifdef CONFIG_MXC_OCOTP
-void enable_ocotp_clk(unsigned char enable)
-{
- u32 reg;
-
- reg = __raw_readl(&imx_ccm->CCGR2);
- if (enable)
- reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
- else
- reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
- __raw_writel(reg, &imx_ccm->CCGR2);
-}
-#endif
-
-#ifdef CONFIG_NAND_MXS
-void setup_gpmi_io_clk(u32 cfg)
-{
- /* Disable clocks per ERR007177 from MX6 errata */
- clrbits_le32(&imx_ccm->CCGR4,
- MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
- MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
-
-#if defined(CONFIG_MX6SX)
- clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
-
- clrsetbits_le32(&imx_ccm->cs2cdr,
- MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
- MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
- MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK,
- cfg);
-
- setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
-#else
- clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
-
- clrsetbits_le32(&imx_ccm->cs2cdr,
- MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
- MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
- MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
- cfg);
-
- setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
-#endif
- setbits_le32(&imx_ccm->CCGR4,
- MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
- MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
-}
-#endif
-
-void enable_usboh3_clk(unsigned char enable)
-{
- u32 reg;
-
- reg = __raw_readl(&imx_ccm->CCGR6);
- if (enable)
- reg |= MXC_CCM_CCGR6_USBOH3_MASK;
- else
- reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
- __raw_writel(reg, &imx_ccm->CCGR6);
-
-}
-
-#if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
-void enable_enet_clk(unsigned char enable)
-{
- u32 mask, *addr;
-
- if (is_mx6ull()) {
- mask = MXC_CCM_CCGR0_ENET_CLK_ENABLE_MASK;
- addr = &imx_ccm->CCGR0;
- } else if (is_mx6ul()) {
- mask = MXC_CCM_CCGR3_ENET_MASK;
- addr = &imx_ccm->CCGR3;
- } else {
- mask = MXC_CCM_CCGR1_ENET_MASK;
- addr = &imx_ccm->CCGR1;
- }
-
- if (enable)
- setbits_le32(addr, mask);
- else
- clrbits_le32(addr, mask);
-}
-#endif
-
-#ifdef CONFIG_MXC_UART
-void enable_uart_clk(unsigned char enable)
-{
- u32 mask;
-
- if (is_mx6ul() || is_mx6ull())
- mask = MXC_CCM_CCGR5_UART_MASK;
- else
- mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
-
- if (enable)
- setbits_le32(&imx_ccm->CCGR5, mask);
- else
- clrbits_le32(&imx_ccm->CCGR5, mask);
-}
-#endif
-
-#ifdef CONFIG_MMC
-int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
-{
- u32 mask;
-
- if (bus_num > 3)
- return -EINVAL;
-
- mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
- if (enable)
- setbits_le32(&imx_ccm->CCGR6, mask);
- else
- clrbits_le32(&imx_ccm->CCGR6, mask);
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_SYS_I2C_MXC
-/* i2c_num can be from 0 - 3 */
-int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
-{
- u32 reg;
- u32 mask;
- u32 *addr;
-
- if (i2c_num > 3)
- return -EINVAL;
- if (i2c_num < 3) {
- mask = MXC_CCM_CCGR_CG_MASK
- << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
- + (i2c_num << 1));
- reg = __raw_readl(&imx_ccm->CCGR2);
- if (enable)
- reg |= mask;
- else
- reg &= ~mask;
- __raw_writel(reg, &imx_ccm->CCGR2);
- } else {
- if (is_mx6sll())
- return -EINVAL;
- if (is_mx6sx() || is_mx6ul() || is_mx6ull()) {
- mask = MXC_CCM_CCGR6_I2C4_MASK;
- addr = &imx_ccm->CCGR6;
- } else {
- mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
- addr = &imx_ccm->CCGR1;
- }
- reg = __raw_readl(addr);
- if (enable)
- reg |= mask;
- else
- reg &= ~mask;
- __raw_writel(reg, addr);
- }
- return 0;
-}
-#endif
-
-/* spi_num can be from 0 - SPI_MAX_NUM */
-int enable_spi_clk(unsigned char enable, unsigned spi_num)
-{
- u32 reg;
- u32 mask;
-
- if (spi_num > SPI_MAX_NUM)
- return -EINVAL;
-
- mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
- reg = __raw_readl(&imx_ccm->CCGR1);
- if (enable)
- reg |= mask;
- else
- reg &= ~mask;
- __raw_writel(reg, &imx_ccm->CCGR1);
- return 0;
-}
-static u32 decode_pll(enum pll_clocks pll, u32 infreq)
-{
- u32 div, test_div, pll_num, pll_denom;
-
- switch (pll) {
- case PLL_SYS:
- div = __raw_readl(&imx_ccm->analog_pll_sys);
- div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
-
- return (infreq * div) >> 1;
- case PLL_BUS:
- div = __raw_readl(&imx_ccm->analog_pll_528);
- div &= BM_ANADIG_PLL_528_DIV_SELECT;
-
- return infreq * (20 + (div << 1));
- case PLL_USBOTG:
- div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
- div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
-
- return infreq * (20 + (div << 1));
- case PLL_ENET:
- div = __raw_readl(&imx_ccm->analog_pll_enet);
- div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
-
- return 25000000 * (div + (div >> 1) + 1);
- case PLL_AUDIO:
- div = __raw_readl(&imx_ccm->analog_pll_audio);
- if (!(div & BM_ANADIG_PLL_AUDIO_ENABLE))
- return 0;
- /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
- if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
- return MXC_HCLK;
- pll_num = __raw_readl(&imx_ccm->analog_pll_audio_num);
- pll_denom = __raw_readl(&imx_ccm->analog_pll_audio_denom);
- test_div = (div & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) >>
- BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT;
- div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
- if (test_div == 3) {
- debug("Error test_div\n");
- return 0;
- }
- test_div = 1 << (2 - test_div);
-
- return infreq * (div + pll_num / pll_denom) / test_div;
- case PLL_VIDEO:
- div = __raw_readl(&imx_ccm->analog_pll_video);
- if (!(div & BM_ANADIG_PLL_VIDEO_ENABLE))
- return 0;
- /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
- if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
- return MXC_HCLK;
- pll_num = __raw_readl(&imx_ccm->analog_pll_video_num);
- pll_denom = __raw_readl(&imx_ccm->analog_pll_video_denom);
- test_div = (div & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) >>
- BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
- div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
- if (test_div == 3) {
- debug("Error test_div\n");
- return 0;
- }
- test_div = 1 << (2 - test_div);
-
- return infreq * (div + pll_num / pll_denom) / test_div;
- default:
- return 0;
- }
- /* NOTREACHED */
-}
-static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
-{
- u32 div;
- u64 freq;
-
- switch (pll) {
- case PLL_BUS:
- if (!is_mx6ul() && !is_mx6ull()) {
- if (pfd_num == 3) {
- /* No PFD3 on PLL2 */
- return 0;
- }
- }
- div = __raw_readl(&imx_ccm->analog_pfd_528);
- freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
- break;
- case PLL_USBOTG:
- div = __raw_readl(&imx_ccm->analog_pfd_480);
- freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
- break;
- default:
- /* No PFD on other PLL */
- return 0;
- }
-
- return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
- ANATOP_PFD_FRAC_SHIFT(pfd_num));
-}
-
-static u32 get_mcu_main_clk(void)
-{
- u32 reg, freq;
-
- reg = __raw_readl(&imx_ccm->cacrr);
- reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
- reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
- freq = decode_pll(PLL_SYS, MXC_HCLK);
-
- return freq / (reg + 1);
-}
-
-u32 get_periph_clk(void)
-{
- u32 reg, div = 0, freq = 0;
-
- reg = __raw_readl(&imx_ccm->cbcdr);
- if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
- div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
- MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
- reg = __raw_readl(&imx_ccm->cbcmr);
- reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
- reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
-
- switch (reg) {
- case 0:
- freq = decode_pll(PLL_USBOTG, MXC_HCLK);
- break;
- case 1:
- case 2:
- freq = MXC_HCLK;
- break;
- default:
- break;
- }
- } else {
- reg = __raw_readl(&imx_ccm->cbcmr);
- reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
- reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
-
- switch (reg) {
- case 0:
- freq = decode_pll(PLL_BUS, MXC_HCLK);
- break;
- case 1:
- freq = mxc_get_pll_pfd(PLL_BUS, 2);
- break;
- case 2:
- freq = mxc_get_pll_pfd(PLL_BUS, 0);
- break;
- case 3:
- /* static / 2 divider */
- freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
- break;
- default:
- break;
- }
- }
-
- return freq / (div + 1);
-}
-
-static u32 get_ipg_clk(void)
-{
- u32 reg, ipg_podf;
-
- reg = __raw_readl(&imx_ccm->cbcdr);
- reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
- ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
-
- return get_ahb_clk() / (ipg_podf + 1);
-}
-
-static u32 get_ipg_per_clk(void)
-{
- u32 reg, perclk_podf;
-
- reg = __raw_readl(&imx_ccm->cscmr1);
- if (is_mx6sll() || is_mx6sl() || is_mx6sx() ||
- is_mx6dqp() || is_mx6ul() || is_mx6ull()) {
- if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
- return MXC_HCLK; /* OSC 24Mhz */
- }
-
- perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
-
- return get_ipg_clk() / (perclk_podf + 1);
-}
-
-static u32 get_uart_clk(void)
-{
- u32 reg, uart_podf;
- u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
- reg = __raw_readl(&imx_ccm->cscdr1);
-
- if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul() ||
- is_mx6sll() || is_mx6ull()) {
- if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
- freq = MXC_HCLK;
- }
-
- reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
- uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
-
- return freq / (uart_podf + 1);
-}
-
-static u32 get_cspi_clk(void)
-{
- u32 reg, cspi_podf;
-
- reg = __raw_readl(&imx_ccm->cscdr2);
- cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
- MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
-
- if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul() ||
- is_mx6sll() || is_mx6ull()) {
- if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
- return MXC_HCLK / (cspi_podf + 1);
- }
-
- return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
-}
-
-static u32 get_axi_clk(void)
-{
- u32 root_freq, axi_podf;
- u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
-
- axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
- axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
-
- if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
- if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
- root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
- else
- root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
- } else
- root_freq = get_periph_clk();
-
- return root_freq / (axi_podf + 1);
-}
-
-static u32 get_emi_slow_clk(void)
-{
- u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
-
- cscmr1 = __raw_readl(&imx_ccm->cscmr1);
- emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
- emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
- emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
- emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
-
- switch (emi_clk_sel) {
- case 0:
- root_freq = get_axi_clk();
- break;
- case 1:
- root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
- break;
- case 2:
- root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
- break;
- case 3:
- root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
- break;
- }
-
- return root_freq / (emi_slow_podf + 1);
-}
-
-static u32 get_mmdc_ch0_clk(void)
-{
- u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
- u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
-
- u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div;
-
- if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl() ||
- is_mx6sll()) {
- podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
- MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
- if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
- per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
- MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
- if (is_mx6sl()) {
- if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
- freq = MXC_HCLK;
- else
- freq = decode_pll(PLL_USBOTG, MXC_HCLK);
- } else {
- if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
- freq = decode_pll(PLL_BUS, MXC_HCLK);
- else
- freq = decode_pll(PLL_USBOTG, MXC_HCLK);
- }
- } else {
- per2_clk2_podf = 0;
- switch ((cbcmr &
- MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
- MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
- case 0:
- freq = decode_pll(PLL_BUS, MXC_HCLK);
- break;
- case 1:
- freq = mxc_get_pll_pfd(PLL_BUS, 2);
- break;
- case 2:
- freq = mxc_get_pll_pfd(PLL_BUS, 0);
- break;
- case 3:
- if (is_mx6sl()) {
- freq = mxc_get_pll_pfd(PLL_BUS, 2) >> 1;
- break;
- }
-
- pmu_misc2_audio_div = PMU_MISC2_AUDIO_DIV(__raw_readl(&imx_ccm->pmu_misc2));
- switch (pmu_misc2_audio_div) {
- case 0:
- case 2:
- pmu_misc2_audio_div = 1;
- break;
- case 1:
- pmu_misc2_audio_div = 2;
- break;
- case 3:
- pmu_misc2_audio_div = 4;
- break;
- }
- freq = decode_pll(PLL_AUDIO, MXC_HCLK) /
- pmu_misc2_audio_div;
- break;
- }
- }
- return freq / (podf + 1) / (per2_clk2_podf + 1);
- } else {
- podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
- MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
- return get_periph_clk() / (podf + 1);
- }
-}
-
-#if defined(CONFIG_VIDEO_MXS)
-static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom,
- u32 post_div)
-{
- u32 reg = 0;
- ulong start;
-
- debug("pll5 div = %d, num = %d, denom = %d\n",
- pll_div, pll_num, pll_denom);
-
- /* Power up PLL5 video */
- writel(BM_ANADIG_PLL_VIDEO_POWERDOWN |
- BM_ANADIG_PLL_VIDEO_BYPASS |
- BM_ANADIG_PLL_VIDEO_DIV_SELECT |
- BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
- &imx_ccm->analog_pll_video_clr);
-
- /* Set div, num and denom */
- switch (post_div) {
- case 1:
- writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
- BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x2),
- &imx_ccm->analog_pll_video_set);
- break;
- case 2:
- writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
- BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x1),
- &imx_ccm->analog_pll_video_set);
- break;
- case 4:
- writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
- BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x0),
- &imx_ccm->analog_pll_video_set);
- break;
- default:
- puts("Wrong test_div!\n");
- return -EINVAL;
- }
-
- writel(BF_ANADIG_PLL_VIDEO_NUM_A(pll_num),
- &imx_ccm->analog_pll_video_num);
- writel(BF_ANADIG_PLL_VIDEO_DENOM_B(pll_denom),
- &imx_ccm->analog_pll_video_denom);
-
- /* Wait PLL5 lock */
- start = get_timer(0); /* Get current timestamp */
-
- do {
- reg = readl(&imx_ccm->analog_pll_video);
- if (reg & BM_ANADIG_PLL_VIDEO_LOCK) {
- /* Enable PLL out */
- writel(BM_ANADIG_PLL_VIDEO_ENABLE,
- &imx_ccm->analog_pll_video_set);
- return 0;
- }
- } while (get_timer(0) < (start + 10)); /* Wait 10ms */
-
- puts("Lock PLL5 timeout\n");
-
- return -ETIME;
-}
-
-/*
- * 24M--> PLL_VIDEO -> LCDIFx_PRED -> LCDIFx_PODF -> LCD
- *
- * 'freq' using KHz as unit, see driver/video/mxsfb.c.
- */
-void mxs_set_lcdclk(u32 base_addr, u32 freq)
-{
- u32 reg = 0;
- u32 hck = MXC_HCLK / 1000;
- /* DIV_SELECT ranges from 27 to 54 */
- u32 min = hck * 27;
- u32 max = hck * 54;
- u32 temp, best = 0;
- u32 i, j, max_pred = 8, max_postd = 8, pred = 1, postd = 1;
- u32 pll_div, pll_num, pll_denom, post_div = 1;
-
- debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
-
- if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl() &&
- !is_mx6sll()) {
- debug("This chip not support lcd!\n");
- return;
- }
-
- if (!is_mx6sl()) {
- if (base_addr == LCDIF1_BASE_ADDR) {
- reg = readl(&imx_ccm->cscdr2);
- /* Can't change clocks when clock not from pre-mux */
- if ((reg & MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) != 0)
- return;
- }
- }
-
- if (is_mx6sx()) {
- reg = readl(&imx_ccm->cscdr2);
- /* Can't change clocks when clock not from pre-mux */
- if ((reg & MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK) != 0)
- return;
- }
-
- temp = freq * max_pred * max_postd;
- if (temp < min) {
- /*
- * Register: PLL_VIDEO
- * Bit Field: POST_DIV_SELECT
- * 00 — Divide by 4.
- * 01 — Divide by 2.
- * 10 — Divide by 1.
- * 11 — Reserved
- * No need to check post_div(1)
- */
- for (post_div = 2; post_div <= 4; post_div <<= 1) {
- if ((temp * post_div) > min) {
- freq *= post_div;
- break;
- }
- }
-
- if (post_div > 4) {
- printf("Fail to set rate to %dkhz", freq);
- return;
- }
- }
-
- /* Choose the best pred and postd to match freq for lcd */
- for (i = 1; i <= max_pred; i++) {
- for (j = 1; j <= max_postd; j++) {
- temp = freq * i * j;
- if (temp > max || temp < min)
- continue;
- if (best == 0 || temp < best) {
- best = temp;
- pred = i;
- postd = j;
- }
- }
- }
-
- if (best == 0) {
- printf("Fail to set rate to %dKHz", freq);
- return;
- }
-
- debug("best %d, pred = %d, postd = %d\n", best, pred, postd);
-
- pll_div = best / hck;
- pll_denom = 1000000;
- pll_num = (best - hck * pll_div) * pll_denom / hck;
-
- /*
- * pll_num
- * (24MHz * (pll_div + --------- ))
- * pll_denom
- *freq KHz = --------------------------------
- * post_div * pred * postd * 1000
- */
-
- if (base_addr == LCDIF1_BASE_ADDR) {
- if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
- return;
-
- enable_lcdif_clock(base_addr, 0);
- if (!is_mx6sl()) {
- /* Select pre-lcd clock to PLL5 and set pre divider */
- clrsetbits_le32(&imx_ccm->cscdr2,
- MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK |
- MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK,
- (0x2 << MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET) |
- ((pred - 1) <<
- MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET));
-
- /* Set the post divider */
- clrsetbits_le32(&imx_ccm->cbcmr,
- MXC_CCM_CBCMR_LCDIF1_PODF_MASK,
- ((postd - 1) <<
- MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET));
- } else {
- /* Select pre-lcd clock to PLL5 and set pre divider */
- clrsetbits_le32(&imx_ccm->cscdr2,
- MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_MASK |
- MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_MASK,
- (0x2 << MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_OFFSET) |
- ((pred - 1) <<
- MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_OFFSET));
-
- /* Set the post divider */
- clrsetbits_le32(&imx_ccm->cscmr1,
- MXC_CCM_CSCMR1_LCDIF_PIX_PODF_MASK,
- (((postd - 1)^0x6) <<
- MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET));
- }
-
- enable_lcdif_clock(base_addr, 1);
- } else if (is_mx6sx()) {
- /* Setting LCDIF2 for i.MX6SX */
- if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
- return;
-
- enable_lcdif_clock(base_addr, 0);
- /* Select pre-lcd clock to PLL5 and set pre divider */
- clrsetbits_le32(&imx_ccm->cscdr2,
- MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK |
- MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK,
- (0x2 << MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET) |
- ((pred - 1) <<
- MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET));
-
- /* Set the post divider */
- clrsetbits_le32(&imx_ccm->cscmr1,
- MXC_CCM_CSCMR1_LCDIF2_PODF_MASK,
- ((postd - 1) <<
- MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET));
-
- enable_lcdif_clock(base_addr, 1);
- }
-}
-
-int enable_lcdif_clock(u32 base_addr, bool enable)
-{
- u32 reg = 0;
- u32 lcdif_clk_sel_mask, lcdif_ccgr3_mask;
-
- if (is_mx6sx()) {
- if ((base_addr != LCDIF1_BASE_ADDR) &&
- (base_addr != LCDIF2_BASE_ADDR)) {
- puts("Wrong LCD interface!\n");
- return -EINVAL;
- }
- /* Set to pre-mux clock at default */
- lcdif_clk_sel_mask = (base_addr == LCDIF2_BASE_ADDR) ?
- MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK :
- MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
- lcdif_ccgr3_mask = (base_addr == LCDIF2_BASE_ADDR) ?
- (MXC_CCM_CCGR3_LCDIF2_PIX_MASK |
- MXC_CCM_CCGR3_DISP_AXI_MASK) :
- (MXC_CCM_CCGR3_LCDIF1_PIX_MASK |
- MXC_CCM_CCGR3_DISP_AXI_MASK);
- } else if (is_mx6ul() || is_mx6ull() || is_mx6sll()) {
- if (base_addr != LCDIF1_BASE_ADDR) {
- puts("Wrong LCD interface!\n");
- return -EINVAL;
- }
- /* Set to pre-mux clock at default */
- lcdif_clk_sel_mask = MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
- lcdif_ccgr3_mask = MXC_CCM_CCGR3_LCDIF1_PIX_MASK;
- } else if (is_mx6sl()) {
- if (base_addr != LCDIF1_BASE_ADDR) {
- puts("Wrong LCD interface!\n");
- return -EINVAL;
- }
-
- reg = readl(&imx_ccm->CCGR3);
- reg &= ~(MXC_CCM_CCGR3_LCDIF_AXI_MASK |
- MXC_CCM_CCGR3_LCDIF_PIX_MASK);
- writel(reg, &imx_ccm->CCGR3);
-
- if (enable) {
- reg = readl(&imx_ccm->cscdr3);
- reg &= ~MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK;
- reg |= 1 << MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET;
- writel(reg, &imx_ccm->cscdr3);
-
- reg = readl(&imx_ccm->CCGR3);
- reg |= MXC_CCM_CCGR3_LCDIF_AXI_MASK |
- MXC_CCM_CCGR3_LCDIF_PIX_MASK;
- writel(reg, &imx_ccm->CCGR3);
- }
-
- return 0;
- } else {
- return 0;
- }
-
- /* Gate LCDIF clock first */
- reg = readl(&imx_ccm->CCGR3);
- reg &= ~lcdif_ccgr3_mask;
- writel(reg, &imx_ccm->CCGR3);
-
- reg = readl(&imx_ccm->CCGR2);
- reg &= ~MXC_CCM_CCGR2_LCD_MASK;
- writel(reg, &imx_ccm->CCGR2);
-
- if (enable) {
- /* Select pre-mux */
- reg = readl(&imx_ccm->cscdr2);
- reg &= ~lcdif_clk_sel_mask;
- writel(reg, &imx_ccm->cscdr2);
-
- /* Enable the LCDIF pix clock */
- reg = readl(&imx_ccm->CCGR3);
- reg |= lcdif_ccgr3_mask;
- writel(reg, &imx_ccm->CCGR3);
-
- reg = readl(&imx_ccm->CCGR2);
- reg |= MXC_CCM_CCGR2_LCD_MASK;
- writel(reg, &imx_ccm->CCGR2);
- }
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_FSL_QSPI
-/* qspi_num can be from 0 - 1 */
-void enable_qspi_clk(int qspi_num)
-{
- u32 reg = 0;
- /* Enable QuadSPI clock */
- switch (qspi_num) {
- case 0:
- /* disable the clock gate */
- clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
-
- /* set 50M : (50 = 396 / 2 / 4) */
- reg = readl(&imx_ccm->cscmr1);
- reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
- MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
- reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
- (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
- writel(reg, &imx_ccm->cscmr1);
-
- /* enable the clock gate */
- setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
- break;
- case 1:
- /*
- * disable the clock gate
- * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
- * disable both of them.
- */
- clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
-
- /* set 50M : (50 = 396 / 2 / 4) */
- reg = readl(&imx_ccm->cs2cdr);
- reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
- MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
- MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
- reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
- MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
- writel(reg, &imx_ccm->cs2cdr);
-
- /*enable the clock gate*/
- setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
- break;
- default:
- break;
- }
-}
-#endif
-
-#ifdef CONFIG_FEC_MXC
-int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
-{
- u32 reg = 0;
- s32 timeout = 100000;
-
- struct anatop_regs __iomem *anatop =
- (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
-
- if (freq < ENET_25MHZ || freq > ENET_125MHZ)
- return -EINVAL;
-
- reg = readl(&anatop->pll_enet);
-
- if (fec_id == 0) {
- reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
- reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
- } else if (fec_id == 1) {
- /* Only i.MX6SX/UL support ENET2 */
- if (!(is_mx6sx() || is_mx6ul() || is_mx6ull()))
- return -EINVAL;
- reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
- reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
- } else {
- return -EINVAL;
- }
-
- if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
- (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
- reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
- writel(reg, &anatop->pll_enet);
- while (timeout--) {
- if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
- break;
- }
- if (timeout < 0)
- return -ETIMEDOUT;
- }
-
- /* Enable FEC clock */
- if (fec_id == 0)
- reg |= BM_ANADIG_PLL_ENET_ENABLE;
- else
- reg |= BM_ANADIG_PLL_ENET2_ENABLE;
- reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
- writel(reg, &anatop->pll_enet);
-
-#ifdef CONFIG_MX6SX
- /* Disable enet system clcok before switching clock parent */
- reg = readl(&imx_ccm->CCGR3);
- reg &= ~MXC_CCM_CCGR3_ENET_MASK;
- writel(reg, &imx_ccm->CCGR3);
-
- /*
- * Set enet ahb clock to 200MHz
- * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
- */
- reg = readl(&imx_ccm->chsccdr);
- reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
- | MXC_CCM_CHSCCDR_ENET_PODF_MASK
- | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
- /* PLL2 PFD2 */
- reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
- /* Div = 2*/
- reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
- reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
- writel(reg, &imx_ccm->chsccdr);
-
- /* Enable enet system clock */
- reg = readl(&imx_ccm->CCGR3);
- reg |= MXC_CCM_CCGR3_ENET_MASK;
- writel(reg, &imx_ccm->CCGR3);
-#endif
- return 0;
-}
-#endif
-
-static u32 get_usdhc_clk(u32 port)
-{
- u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
- u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
- u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
-
- if (is_mx6ul() || is_mx6ull()) {
- if (port > 1)
- return 0;
- }
-
- if (is_mx6sll()) {
- if (port > 2)
- return 0;
- }
-
- switch (port) {
- case 0:
- usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
- MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
- clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
-
- break;
- case 1:
- usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
- MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
- clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
-
- break;
- case 2:
- usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
- MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
- clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
-
- break;
- case 3:
- usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
- MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
- clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
-
- break;
- default:
- break;
- }
-
- if (clk_sel)
- root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
- else
- root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
-
- return root_freq / (usdhc_podf + 1);
-}
-
-u32 imx_get_uartclk(void)
-{
- return get_uart_clk();
-}
-
-u32 imx_get_fecclk(void)
-{
- return mxc_get_clock(MXC_IPG_CLK);
-}
-
-#if defined(CONFIG_SATA) || defined(CONFIG_PCIE_IMX)
-static int enable_enet_pll(uint32_t en)
-{
- struct mxc_ccm_reg *const imx_ccm
- = (struct mxc_ccm_reg *) CCM_BASE_ADDR;
- s32 timeout = 100000;
- u32 reg = 0;
-
- /* Enable PLLs */
- reg = readl(&imx_ccm->analog_pll_enet);
- reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
- writel(reg, &imx_ccm->analog_pll_enet);
- reg |= BM_ANADIG_PLL_SYS_ENABLE;
- while (timeout--) {
- if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
- break;
- }
- if (timeout <= 0)
- return -EIO;
- reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
- writel(reg, &imx_ccm->analog_pll_enet);
- reg |= en;
- writel(reg, &imx_ccm->analog_pll_enet);
- return 0;
-}
-#endif
-
-#ifdef CONFIG_SATA
-static void ungate_sata_clock(void)
-{
- struct mxc_ccm_reg *const imx_ccm =
- (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- /* Enable SATA clock. */
- setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
-}
-
-int enable_sata_clock(void)
-{
- ungate_sata_clock();
- return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
-}
-
-void disable_sata_clock(void)
-{
- struct mxc_ccm_reg *const imx_ccm =
- (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
-}
-#endif
-
-#ifdef CONFIG_PCIE_IMX
-static void ungate_pcie_clock(void)
-{
- struct mxc_ccm_reg *const imx_ccm =
- (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- /* Enable PCIe clock. */
- setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
-}
-
-int enable_pcie_clock(void)
-{
- struct anatop_regs *anatop_regs =
- (struct anatop_regs *)ANATOP_BASE_ADDR;
- struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- u32 lvds1_clk_sel;
-
- /*
- * Here be dragons!
- *
- * The register ANATOP_MISC1 is not documented in the Freescale
- * MX6RM. The register that is mapped in the ANATOP space and
- * marked as ANATOP_MISC1 is actually documented in the PMU section
- * of the datasheet as PMU_MISC1.
- *
- * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
- * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
- * for PCI express link that is clocked from the i.MX6.
- */
-#define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
-#define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
-#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
-#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
-#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
-
- if (is_mx6sx())
- lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
- else
- lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
-
- clrsetbits_le32(&anatop_regs->ana_misc1,
- ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
- ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
- ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
-
- /* PCIe reference clock sourced from AXI. */
- clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
-
- /* Party time! Ungate the clock to the PCIe. */
-#ifdef CONFIG_SATA
- ungate_sata_clock();
-#endif
- ungate_pcie_clock();
-
- return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
- BM_ANADIG_PLL_ENET_ENABLE_PCIE);
-}
-#endif
-
-#ifdef CONFIG_SECURE_BOOT
-void hab_caam_clock_enable(unsigned char enable)
-{
- u32 reg;
-
- if (is_mx6ull() || is_mx6sll()) {
- /* CG5, DCP clock */
- reg = __raw_readl(&imx_ccm->CCGR0);
- if (enable)
- reg |= MXC_CCM_CCGR0_DCP_CLK_MASK;
- else
- reg &= ~MXC_CCM_CCGR0_DCP_CLK_MASK;
- __raw_writel(reg, &imx_ccm->CCGR0);
- } else {
- /* CG4 ~ CG6, CAAM clocks */
- reg = __raw_readl(&imx_ccm->CCGR0);
- if (enable)
- reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
- MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
- MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
- else
- reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
- MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
- MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
- __raw_writel(reg, &imx_ccm->CCGR0);
- }
-
- /* EMI slow clk */
- reg = __raw_readl(&imx_ccm->CCGR6);
- if (enable)
- reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
- else
- reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
- __raw_writel(reg, &imx_ccm->CCGR6);
-}
-#endif
-
-static void enable_pll3(void)
-{
- struct anatop_regs __iomem *anatop =
- (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
-
- /* make sure pll3 is enabled */
- if ((readl(&anatop->usb1_pll_480_ctrl) &
- BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
- /* enable pll's power */
- writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
- &anatop->usb1_pll_480_ctrl_set);
- writel(0x80, &anatop->ana_misc2_clr);
- /* wait for pll lock */
- while ((readl(&anatop->usb1_pll_480_ctrl) &
- BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
- ;
- /* disable bypass */
- writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
- &anatop->usb1_pll_480_ctrl_clr);
- /* enable pll output */
- writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
- &anatop->usb1_pll_480_ctrl_set);
- }
-}
-
-void enable_thermal_clk(void)
-{
- enable_pll3();
-}
-
-unsigned int mxc_get_clock(enum mxc_clock clk)
-{
- switch (clk) {
- case MXC_ARM_CLK:
- return get_mcu_main_clk();
- case MXC_PER_CLK:
- return get_periph_clk();
- case MXC_AHB_CLK:
- return get_ahb_clk();
- case MXC_IPG_CLK:
- return get_ipg_clk();
- case MXC_IPG_PERCLK:
- case MXC_I2C_CLK:
- return get_ipg_per_clk();
- case MXC_UART_CLK:
- return get_uart_clk();
- case MXC_CSPI_CLK:
- return get_cspi_clk();
- case MXC_AXI_CLK:
- return get_axi_clk();
- case MXC_EMI_SLOW_CLK:
- return get_emi_slow_clk();
- case MXC_DDR_CLK:
- return get_mmdc_ch0_clk();
- case MXC_ESDHC_CLK:
- return get_usdhc_clk(0);
- case MXC_ESDHC2_CLK:
- return get_usdhc_clk(1);
- case MXC_ESDHC3_CLK:
- return get_usdhc_clk(2);
- case MXC_ESDHC4_CLK:
- return get_usdhc_clk(3);
- case MXC_SATA_CLK:
- return get_ahb_clk();
- default:
- printf("Unsupported MXC CLK: %d\n", clk);
- break;
- }
-
- return 0;
-}
-
-/*
- * Dump some core clockes.
- */
-int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- u32 freq;
- freq = decode_pll(PLL_SYS, MXC_HCLK);
- printf("PLL_SYS %8d MHz\n", freq / 1000000);
- freq = decode_pll(PLL_BUS, MXC_HCLK);
- printf("PLL_BUS %8d MHz\n", freq / 1000000);
- freq = decode_pll(PLL_USBOTG, MXC_HCLK);
- printf("PLL_OTG %8d MHz\n", freq / 1000000);
- freq = decode_pll(PLL_ENET, MXC_HCLK);
- printf("PLL_NET %8d MHz\n", freq / 1000000);
-
- printf("\n");
- printf("ARM %8d kHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000);
- printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
- printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
-#ifdef CONFIG_MXC_SPI
- printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
-#endif
- printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
- printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
- printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
- printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
- printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
- printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
- printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
- printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
- printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
-
- return 0;
-}
-
-#ifndef CONFIG_MX6SX
-void enable_ipu_clock(void)
-{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- int reg;
- reg = readl(&mxc_ccm->CCGR3);
- reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
- writel(reg, &mxc_ccm->CCGR3);
-
- if (is_mx6dqp()) {
- setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
- setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
- }
-}
-#endif
-
-#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) || defined(CONFIG_MX6DL) || \
- defined(CONFIG_MX6S)
-static void disable_ldb_di_clock_sources(void)
-{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- int reg;
-
- /* Make sure PFDs are disabled at boot. */
- reg = readl(&mxc_ccm->analog_pfd_528);
- /* Cannot disable pll2_pfd2_396M, as it is the MMDC clock in iMX6DL */
- if (is_mx6sdl())
- reg |= 0x80008080;
- else
- reg |= 0x80808080;
- writel(reg, &mxc_ccm->analog_pfd_528);
-
- /* Disable PLL3 PFDs */
- reg = readl(&mxc_ccm->analog_pfd_480);
- reg |= 0x80808080;
- writel(reg, &mxc_ccm->analog_pfd_480);
-
- /* Disable PLL5 */
- reg = readl(&mxc_ccm->analog_pll_video);
- reg &= ~(1 << 13);
- writel(reg, &mxc_ccm->analog_pll_video);
-}
-
-static void enable_ldb_di_clock_sources(void)
-{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- int reg;
-
- reg = readl(&mxc_ccm->analog_pfd_528);
- if (is_mx6sdl())
- reg &= ~(0x80008080);
- else
- reg &= ~(0x80808080);
- writel(reg, &mxc_ccm->analog_pfd_528);
-
- reg = readl(&mxc_ccm->analog_pfd_480);
- reg &= ~(0x80808080);
- writel(reg, &mxc_ccm->analog_pfd_480);
-}
-
-/*
- * Try call this function as early in the boot process as possible since the
- * function temporarily disables PLL2 PFD's, PLL3 PFD's and PLL5.
- */
-void select_ldb_di_clock_source(enum ldb_di_clock clk)
-{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- int reg;
-
- /*
- * Need to follow a strict procedure when changing the LDB
- * clock, else we can introduce a glitch. Things to keep in
- * mind:
- * 1. The current and new parent clocks must be disabled.
- * 2. The default clock for ldb_dio_clk is mmdc_ch1 which has
- * no CG bit.
- * 3. In the RTL implementation of the LDB_DI_CLK_SEL mux
- * the top four options are in one mux and the PLL3 option along
- * with another option is in the second mux. There is third mux
- * used to decide between the first and second mux.
- * The code below switches the parent to the bottom mux first
- * and then manipulates the top mux. This ensures that no glitch
- * will enter the divider.
- *
- * Need to disable MMDC_CH1 clock manually as there is no CG bit
- * for this clock. The only way to disable this clock is to move
- * it to pll3_sw_clk and then to disable pll3_sw_clk
- * Make sure periph2_clk2_sel is set to pll3_sw_clk
- */
-
- /* Disable all ldb_di clock parents */
- disable_ldb_di_clock_sources();
-
- /* Set MMDC_CH1 mask bit */
- reg = readl(&mxc_ccm->ccdr);
- reg |= MXC_CCM_CCDR_MMDC_CH1_HS_MASK;
- writel(reg, &mxc_ccm->ccdr);
-
- /* Set periph2_clk2_sel to be sourced from PLL3_sw_clk */
- reg = readl(&mxc_ccm->cbcmr);
- reg &= ~MXC_CCM_CBCMR_PERIPH2_CLK2_SEL;
- writel(reg, &mxc_ccm->cbcmr);
-
- /*
- * Set the periph2_clk_sel to the top mux so that
- * mmdc_ch1 is from pll3_sw_clk.
- */
- reg = readl(&mxc_ccm->cbcdr);
- reg |= MXC_CCM_CBCDR_PERIPH2_CLK_SEL;
- writel(reg, &mxc_ccm->cbcdr);
-
- /* Wait for the clock switch */
- while (readl(&mxc_ccm->cdhipr))
- ;
- /* Disable pll3_sw_clk by selecting bypass clock source */
- reg = readl(&mxc_ccm->ccsr);
- reg |= MXC_CCM_CCSR_PLL3_SW_CLK_SEL;
- writel(reg, &mxc_ccm->ccsr);
-
- /* Set the ldb_di0_clk and ldb_di1_clk to 111b */
- reg = readl(&mxc_ccm->cs2cdr);
- reg |= ((7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
- | (7 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
- writel(reg, &mxc_ccm->cs2cdr);
-
- /* Set the ldb_di0_clk and ldb_di1_clk to 100b */
- reg = readl(&mxc_ccm->cs2cdr);
- reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
- | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
- reg |= ((4 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
- | (4 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
- writel(reg, &mxc_ccm->cs2cdr);
-
- /* Set the ldb_di0_clk and ldb_di1_clk to desired source */
- reg = readl(&mxc_ccm->cs2cdr);
- reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
- | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
- reg |= ((clk << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
- | (clk << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
- writel(reg, &mxc_ccm->cs2cdr);
-
- /* Unbypass pll3_sw_clk */
- reg = readl(&mxc_ccm->ccsr);
- reg &= ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL;
- writel(reg, &mxc_ccm->ccsr);
-
- /*
- * Set the periph2_clk_sel back to the bottom mux so that
- * mmdc_ch1 is from its original parent.
- */
- reg = readl(&mxc_ccm->cbcdr);
- reg &= ~MXC_CCM_CBCDR_PERIPH2_CLK_SEL;
- writel(reg, &mxc_ccm->cbcdr);
-
- /* Wait for the clock switch */
- while (readl(&mxc_ccm->cdhipr))
- ;
- /* Clear MMDC_CH1 mask bit */
- reg = readl(&mxc_ccm->ccdr);
- reg &= ~MXC_CCM_CCDR_MMDC_CH1_HS_MASK;
- writel(reg, &mxc_ccm->ccdr);
-
- enable_ldb_di_clock_sources();
-}
-#endif
-
-#ifdef CONFIG_MTD_NOR_FLASH
-void enable_eim_clk(unsigned char enable)
-{
- u32 reg;
-
- reg = __raw_readl(&imx_ccm->CCGR6);
- if (enable)
- reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
- else
- reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
- __raw_writel(reg, &imx_ccm->CCGR6);
-}
-#endif
-
-/***************************************************/
-
-U_BOOT_CMD(
- clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,
- "display clocks",
- ""
-);
+++ /dev/null
-/*
- * Copyright (C) 2014 Gateworks Corporation
- * Author: Tim Harvey <tharvey@gateworks.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/types.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/mx6-ddr.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/io.h>
-#include <asm/types.h>
-#include <wait_bit.h>
-
-#if defined(CONFIG_MX6_DDRCAL)
-static void reset_read_data_fifos(void)
-{
- struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
-
- /* Reset data FIFOs twice. */
- setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
- wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
-
- setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
- wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
-}
-
-static void precharge_all(const bool cs0_enable, const bool cs1_enable)
-{
- struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
-
- /*
- * Issue the Precharge-All command to the DDR device for both
- * chip selects. Note, CON_REQ bit should also remain set. If
- * only using one chip select, then precharge only the desired
- * chip select.
- */
- if (cs0_enable) { /* CS0 */
- writel(0x04008050, &mmdc0->mdscr);
- wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 1, 100, 0);
- }
-
- if (cs1_enable) { /* CS1 */
- writel(0x04008058, &mmdc0->mdscr);
- wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 1, 100, 0);
- }
-}
-
-static void force_delay_measurement(int bus_size)
-{
- struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
- struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
-
- writel(0x800, &mmdc0->mpmur0);
- if (bus_size == 0x2)
- writel(0x800, &mmdc1->mpmur0);
-}
-
-static void modify_dg_result(u32 *reg_st0, u32 *reg_st1, u32 *reg_ctrl)
-{
- u32 dg_tmp_val, dg_dl_abs_offset, dg_hc_del, val_ctrl;
-
- /*
- * DQS gating absolute offset should be modified from reflecting
- * (HW_DG_LOWx + HW_DG_UPx)/2 to reflecting (HW_DG_UPx - 0x80)
- */
-
- val_ctrl = readl(reg_ctrl);
- val_ctrl &= 0xf0000000;
-
- dg_tmp_val = ((readl(reg_st0) & 0x07ff0000) >> 16) - 0xc0;
- dg_dl_abs_offset = dg_tmp_val & 0x7f;
- dg_hc_del = (dg_tmp_val & 0x780) << 1;
-
- val_ctrl |= dg_dl_abs_offset + dg_hc_del;
-
- dg_tmp_val = ((readl(reg_st1) & 0x07ff0000) >> 16) - 0xc0;
- dg_dl_abs_offset = dg_tmp_val & 0x7f;
- dg_hc_del = (dg_tmp_val & 0x780) << 1;
-
- val_ctrl |= (dg_dl_abs_offset + dg_hc_del) << 16;
-
- writel(val_ctrl, reg_ctrl);
-}
-
-int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo)
-{
- struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
- struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
- u32 esdmisc_val, zq_val;
- u32 errors = 0;
- u32 ldectrl[4] = {0};
- u32 ddr_mr1 = 0x4;
- u32 rwalat_max;
-
- /*
- * Stash old values in case calibration fails,
- * we need to restore them
- */
- ldectrl[0] = readl(&mmdc0->mpwldectrl0);
- ldectrl[1] = readl(&mmdc0->mpwldectrl1);
- if (sysinfo->dsize == 2) {
- ldectrl[2] = readl(&mmdc1->mpwldectrl0);
- ldectrl[3] = readl(&mmdc1->mpwldectrl1);
- }
-
- /* disable DDR logic power down timer */
- clrbits_le32(&mmdc0->mdpdc, 0xff00);
-
- /* disable Adopt power down timer */
- setbits_le32(&mmdc0->mapsr, 0x1);
-
- debug("Starting write leveling calibration.\n");
-
- /*
- * 2. disable auto refresh and ZQ calibration
- * before proceeding with Write Leveling calibration
- */
- esdmisc_val = readl(&mmdc0->mdref);
- writel(0x0000C000, &mmdc0->mdref);
- zq_val = readl(&mmdc0->mpzqhwctrl);
- writel(zq_val & ~0x3, &mmdc0->mpzqhwctrl);
-
- /* 3. increase walat and ralat to maximum */
- rwalat_max = (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17);
- setbits_le32(&mmdc0->mdmisc, rwalat_max);
- if (sysinfo->dsize == 2)
- setbits_le32(&mmdc1->mdmisc, rwalat_max);
- /*
- * 4 & 5. Configure the external DDR device to enter write-leveling
- * mode through Load Mode Register command.
- * Register setting:
- * Bits[31:16] MR1 value (0x0080 write leveling enable)
- * Bit[9] set WL_EN to enable MMDC DQS output
- * Bits[6:4] set CMD bits for Load Mode Register programming
- * Bits[2:0] set CMD_BA to 0x1 for DDR MR1 programming
- */
- writel(0x00808231, &mmdc0->mdscr);
-
- /* 6. Activate automatic calibration by setting MPWLGCR[HW_WL_EN] */
- writel(0x00000001, &mmdc0->mpwlgcr);
-
- /*
- * 7. Upon completion of this process the MMDC de-asserts
- * the MPWLGCR[HW_WL_EN]
- */
- wait_for_bit("MMDC", &mmdc0->mpwlgcr, 1 << 0, 0, 100, 0);
-
- /*
- * 8. check for any errors: check both PHYs for x64 configuration,
- * if x32, check only PHY0
- */
- if (readl(&mmdc0->mpwlgcr) & 0x00000F00)
- errors |= 1;
- if (sysinfo->dsize == 2)
- if (readl(&mmdc1->mpwlgcr) & 0x00000F00)
- errors |= 2;
-
- debug("Ending write leveling calibration. Error mask: 0x%x\n", errors);
-
- /* check to see if cal failed */
- if ((readl(&mmdc0->mpwldectrl0) == 0x001F001F) &&
- (readl(&mmdc0->mpwldectrl1) == 0x001F001F) &&
- ((sysinfo->dsize < 2) ||
- ((readl(&mmdc1->mpwldectrl0) == 0x001F001F) &&
- (readl(&mmdc1->mpwldectrl1) == 0x001F001F)))) {
- debug("Cal seems to have soft-failed due to memory not supporting write leveling on all channels. Restoring original write leveling values.\n");
- writel(ldectrl[0], &mmdc0->mpwldectrl0);
- writel(ldectrl[1], &mmdc0->mpwldectrl1);
- if (sysinfo->dsize == 2) {
- writel(ldectrl[2], &mmdc1->mpwldectrl0);
- writel(ldectrl[3], &mmdc1->mpwldectrl1);
- }
- errors |= 4;
- }
-
- /*
- * User should issue MRS command to exit write leveling mode
- * through Load Mode Register command
- * Register setting:
- * Bits[31:16] MR1 value "ddr_mr1" value from initialization
- * Bit[9] clear WL_EN to disable MMDC DQS output
- * Bits[6:4] set CMD bits for Load Mode Register programming
- * Bits[2:0] set CMD_BA to 0x1 for DDR MR1 programming
- */
- writel((ddr_mr1 << 16) + 0x8031, &mmdc0->mdscr);
-
- /* re-enable auto refresh and zq cal */
- writel(esdmisc_val, &mmdc0->mdref);
- writel(zq_val, &mmdc0->mpzqhwctrl);
-
- debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08X\n",
- readl(&mmdc0->mpwldectrl0));
- debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08X\n",
- readl(&mmdc0->mpwldectrl1));
- if (sysinfo->dsize == 2) {
- debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08X\n",
- readl(&mmdc1->mpwldectrl0));
- debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08X\n",
- readl(&mmdc1->mpwldectrl1));
- }
-
- /* We must force a readback of these values, to get them to stick */
- readl(&mmdc0->mpwldectrl0);
- readl(&mmdc0->mpwldectrl1);
- if (sysinfo->dsize == 2) {
- readl(&mmdc1->mpwldectrl0);
- readl(&mmdc1->mpwldectrl1);
- }
-
- /* enable DDR logic power down timer: */
- setbits_le32(&mmdc0->mdpdc, 0x00005500);
-
- /* Enable Adopt power down timer: */
- clrbits_le32(&mmdc0->mapsr, 0x1);
-
- /* Clear CON_REQ */
- writel(0, &mmdc0->mdscr);
-
- return errors;
-}
-
-int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
-{
- struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
- struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
- struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux =
- (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
- bool cs0_enable;
- bool cs1_enable;
- bool cs0_enable_initial;
- bool cs1_enable_initial;
- u32 esdmisc_val;
- u32 temp_ref;
- u32 pddword = 0x00ffff00; /* best so far, place into MPPDCMPR1 */
- u32 errors = 0;
- u32 initdelay = 0x40404040;
-
- /* check to see which chip selects are enabled */
- cs0_enable_initial = readl(&mmdc0->mdctl) & 0x80000000;
- cs1_enable_initial = readl(&mmdc0->mdctl) & 0x40000000;
-
- /* disable DDR logic power down timer: */
- clrbits_le32(&mmdc0->mdpdc, 0xff00);
-
- /* disable Adopt power down timer: */
- setbits_le32(&mmdc0->mapsr, 0x1);
-
- /* set DQS pull ups */
- setbits_le32(&mx6_ddr_iomux->dram_sdqs0, 0x7000);
- setbits_le32(&mx6_ddr_iomux->dram_sdqs1, 0x7000);
- setbits_le32(&mx6_ddr_iomux->dram_sdqs2, 0x7000);
- setbits_le32(&mx6_ddr_iomux->dram_sdqs3, 0x7000);
- setbits_le32(&mx6_ddr_iomux->dram_sdqs4, 0x7000);
- setbits_le32(&mx6_ddr_iomux->dram_sdqs5, 0x7000);
- setbits_le32(&mx6_ddr_iomux->dram_sdqs6, 0x7000);
- setbits_le32(&mx6_ddr_iomux->dram_sdqs7, 0x7000);
-
- /* Save old RALAT and WALAT values */
- esdmisc_val = readl(&mmdc0->mdmisc);
-
- setbits_le32(&mmdc0->mdmisc,
- (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17));
-
- /* Disable auto refresh before proceeding with calibration */
- temp_ref = readl(&mmdc0->mdref);
- writel(0x0000c000, &mmdc0->mdref);
-
- /*
- * Per the ref manual, issue one refresh cycle MDSCR[CMD]= 0x2,
- * this also sets the CON_REQ bit.
- */
- if (cs0_enable_initial)
- writel(0x00008020, &mmdc0->mdscr);
- if (cs1_enable_initial)
- writel(0x00008028, &mmdc0->mdscr);
-
- /* poll to make sure the con_ack bit was asserted */
- wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 1, 100, 0);
-
- /*
- * Check MDMISC register CALIB_PER_CS to see which CS calibration
- * is targeted to (under normal cases, it should be cleared
- * as this is the default value, indicating calibration is directed
- * to CS0).
- * Disable the other chip select not being target for calibration
- * to avoid any potential issues. This will get re-enabled at end
- * of calibration.
- */
- if ((readl(&mmdc0->mdmisc) & 0x00100000) == 0)
- clrbits_le32(&mmdc0->mdctl, 1 << 30); /* clear SDE_1 */
- else
- clrbits_le32(&mmdc0->mdctl, 1 << 31); /* clear SDE_0 */
-
- /*
- * Check to see which chip selects are now enabled for
- * the remainder of the calibration.
- */
- cs0_enable = readl(&mmdc0->mdctl) & 0x80000000;
- cs1_enable = readl(&mmdc0->mdctl) & 0x40000000;
-
- precharge_all(cs0_enable, cs1_enable);
-
- /* Write the pre-defined value into MPPDCMPR1 */
- writel(pddword, &mmdc0->mppdcmpr1);
-
- /*
- * Issue a write access to the external DDR device by setting
- * the bit SW_DUMMY_WR (bit 0) in the MPSWDAR0 and then poll
- * this bit until it clears to indicate completion of the write access.
- */
- setbits_le32(&mmdc0->mpswdar0, 1);
- wait_for_bit("MMDC", &mmdc0->mpswdar0, 1 << 0, 0, 100, 0);
-
- /* Set the RD_DL_ABS# bits to their default values
- * (will be calibrated later in the read delay-line calibration).
- * Both PHYs for x64 configuration, if x32, do only PHY0.
- */
- writel(initdelay, &mmdc0->mprddlctl);
- if (sysinfo->dsize == 0x2)
- writel(initdelay, &mmdc1->mprddlctl);
-
- /* Force a measurment, for previous delay setup to take effect. */
- force_delay_measurement(sysinfo->dsize);
-
- /*
- * ***************************
- * Read DQS Gating calibration
- * ***************************
- */
- debug("Starting Read DQS Gating calibration.\n");
-
- /*
- * Reset the read data FIFOs (two resets); only need to issue reset
- * to PHY0 since in x64 mode, the reset will also go to PHY1.
- */
- reset_read_data_fifos();
-
- /*
- * Start the automatic read DQS gating calibration process by
- * asserting MPDGCTRL0[HW_DG_EN] and MPDGCTRL0[DG_CMP_CYC]
- * and then poll MPDGCTRL0[HW_DG_EN]] until this bit clears
- * to indicate completion.
- * Also, ensure that MPDGCTRL0[HW_DG_ERR] is clear to indicate
- * no errors were seen during calibration.
- */
-
- /*
- * Set bit 30: chooses option to wait 32 cycles instead of
- * 16 before comparing read data.
- */
- setbits_le32(&mmdc0->mpdgctrl0, 1 << 30);
- if (sysinfo->dsize == 2)
- setbits_le32(&mmdc1->mpdgctrl0, 1 << 30);
-
- /* Set bit 28 to start automatic read DQS gating calibration */
- setbits_le32(&mmdc0->mpdgctrl0, 5 << 28);
-
- /* Poll for completion. MPDGCTRL0[HW_DG_EN] should be 0 */
- wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 28, 0, 100, 0);
-
- /*
- * Check to see if any errors were encountered during calibration
- * (check MPDGCTRL0[HW_DG_ERR]).
- * Check both PHYs for x64 configuration, if x32, check only PHY0.
- */
- if (readl(&mmdc0->mpdgctrl0) & 0x00001000)
- errors |= 1;
-
- if ((sysinfo->dsize == 0x2) && (readl(&mmdc1->mpdgctrl0) & 0x00001000))
- errors |= 2;
-
- /* now disable mpdgctrl0[DG_CMP_CYC] */
- clrbits_le32(&mmdc0->mpdgctrl0, 1 << 30);
- if (sysinfo->dsize == 2)
- clrbits_le32(&mmdc1->mpdgctrl0, 1 << 30);
-
- /*
- * DQS gating absolute offset should be modified from
- * reflecting (HW_DG_LOWx + HW_DG_UPx)/2 to
- * reflecting (HW_DG_UPx - 0x80)
- */
- modify_dg_result(&mmdc0->mpdghwst0, &mmdc0->mpdghwst1,
- &mmdc0->mpdgctrl0);
- modify_dg_result(&mmdc0->mpdghwst2, &mmdc0->mpdghwst3,
- &mmdc0->mpdgctrl1);
- if (sysinfo->dsize == 0x2) {
- modify_dg_result(&mmdc1->mpdghwst0, &mmdc1->mpdghwst1,
- &mmdc1->mpdgctrl0);
- modify_dg_result(&mmdc1->mpdghwst2, &mmdc1->mpdghwst3,
- &mmdc1->mpdgctrl1);
- }
- debug("Ending Read DQS Gating calibration. Error mask: 0x%x\n", errors);
-
- /*
- * **********************
- * Read Delay calibration
- * **********************
- */
- debug("Starting Read Delay calibration.\n");
-
- reset_read_data_fifos();
-
- /*
- * 4. Issue the Precharge-All command to the DDR device for both
- * chip selects. If only using one chip select, then precharge
- * only the desired chip select.
- */
- precharge_all(cs0_enable, cs1_enable);
-
- /*
- * 9. Read delay-line calibration
- * Start the automatic read calibration process by asserting
- * MPRDDLHWCTL[HW_RD_DL_EN].
- */
- writel(0x00000030, &mmdc0->mprddlhwctl);
-
- /*
- * 10. poll for completion
- * MMDC indicates that the write data calibration had finished by
- * setting MPRDDLHWCTL[HW_RD_DL_EN] = 0. Also, ensure that
- * no error bits were set.
- */
- wait_for_bit("MMDC", &mmdc0->mprddlhwctl, 1 << 4, 0, 100, 0);
-
- /* check both PHYs for x64 configuration, if x32, check only PHY0 */
- if (readl(&mmdc0->mprddlhwctl) & 0x0000000f)
- errors |= 4;
-
- if ((sysinfo->dsize == 0x2) &&
- (readl(&mmdc1->mprddlhwctl) & 0x0000000f))
- errors |= 8;
-
- debug("Ending Read Delay calibration. Error mask: 0x%x\n", errors);
-
- /*
- * ***********************
- * Write Delay Calibration
- * ***********************
- */
- debug("Starting Write Delay calibration.\n");
-
- reset_read_data_fifos();
-
- /*
- * 4. Issue the Precharge-All command to the DDR device for both
- * chip selects. If only using one chip select, then precharge
- * only the desired chip select.
- */
- precharge_all(cs0_enable, cs1_enable);
-
- /*
- * 8. Set the WR_DL_ABS# bits to their default values.
- * Both PHYs for x64 configuration, if x32, do only PHY0.
- */
- writel(initdelay, &mmdc0->mpwrdlctl);
- if (sysinfo->dsize == 0x2)
- writel(initdelay, &mmdc1->mpwrdlctl);
-
- /*
- * XXX This isn't in the manual. Force a measurement,
- * for previous delay setup to effect.
- */
- force_delay_measurement(sysinfo->dsize);
-
- /*
- * 9. 10. Start the automatic write calibration process
- * by asserting MPWRDLHWCTL0[HW_WR_DL_EN].
- */
- writel(0x00000030, &mmdc0->mpwrdlhwctl);
-
- /*
- * Poll for completion.
- * MMDC indicates that the write data calibration had finished
- * by setting MPWRDLHWCTL[HW_WR_DL_EN] = 0.
- * Also, ensure that no error bits were set.
- */
- wait_for_bit("MMDC", &mmdc0->mpwrdlhwctl, 1 << 4, 0, 100, 0);
-
- /* Check both PHYs for x64 configuration, if x32, check only PHY0 */
- if (readl(&mmdc0->mpwrdlhwctl) & 0x0000000f)
- errors |= 16;
-
- if ((sysinfo->dsize == 0x2) &&
- (readl(&mmdc1->mpwrdlhwctl) & 0x0000000f))
- errors |= 32;
-
- debug("Ending Write Delay calibration. Error mask: 0x%x\n", errors);
-
- reset_read_data_fifos();
-
- /* Enable DDR logic power down timer */
- setbits_le32(&mmdc0->mdpdc, 0x00005500);
-
- /* Enable Adopt power down timer */
- clrbits_le32(&mmdc0->mapsr, 0x1);
-
- /* Restore MDMISC value (RALAT, WALAT) to MMDCP1 */
- writel(esdmisc_val, &mmdc0->mdmisc);
-
- /* Clear DQS pull ups */
- clrbits_le32(&mx6_ddr_iomux->dram_sdqs0, 0x7000);
- clrbits_le32(&mx6_ddr_iomux->dram_sdqs1, 0x7000);
- clrbits_le32(&mx6_ddr_iomux->dram_sdqs2, 0x7000);
- clrbits_le32(&mx6_ddr_iomux->dram_sdqs3, 0x7000);
- clrbits_le32(&mx6_ddr_iomux->dram_sdqs4, 0x7000);
- clrbits_le32(&mx6_ddr_iomux->dram_sdqs5, 0x7000);
- clrbits_le32(&mx6_ddr_iomux->dram_sdqs6, 0x7000);
- clrbits_le32(&mx6_ddr_iomux->dram_sdqs7, 0x7000);
-
- /* Re-enable SDE (chip selects) if they were set initially */
- if (cs1_enable_initial)
- /* Set SDE_1 */
- setbits_le32(&mmdc0->mdctl, 1 << 30);
-
- if (cs0_enable_initial)
- /* Set SDE_0 */
- setbits_le32(&mmdc0->mdctl, 1 << 31);
-
- /* Re-enable to auto refresh */
- writel(temp_ref, &mmdc0->mdref);
-
- /* Clear the MDSCR (including the con_req bit) */
- writel(0x0, &mmdc0->mdscr); /* CS0 */
-
- /* Poll to make sure the con_ack bit is clear */
- wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 0, 100, 0);
-
- /*
- * Print out the registers that were updated as a result
- * of the calibration process.
- */
- debug("MMDC registers updated from calibration\n");
- debug("Read DQS gating calibration:\n");
- debug("\tMPDGCTRL0 PHY0 = 0x%08X\n", readl(&mmdc0->mpdgctrl0));
- debug("\tMPDGCTRL1 PHY0 = 0x%08X\n", readl(&mmdc0->mpdgctrl1));
- if (sysinfo->dsize == 2) {
- debug("\tMPDGCTRL0 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl0));
- debug("\tMPDGCTRL1 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl1));
- }
- debug("Read calibration:\n");
- debug("\tMPRDDLCTL PHY0 = 0x%08X\n", readl(&mmdc0->mprddlctl));
- if (sysinfo->dsize == 2)
- debug("\tMPRDDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mprddlctl));
- debug("Write calibration:\n");
- debug("\tMPWRDLCTL PHY0 = 0x%08X\n", readl(&mmdc0->mpwrdlctl));
- if (sysinfo->dsize == 2)
- debug("\tMPWRDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mpwrdlctl));
-
- /*
- * Registers below are for debugging purposes. These print out
- * the upper and lower boundaries captured during
- * read DQS gating calibration.
- */
- debug("Status registers bounds for read DQS gating:\n");
- debug("\tMPDGHWST0 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst0));
- debug("\tMPDGHWST1 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst1));
- debug("\tMPDGHWST2 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst2));
- debug("\tMPDGHWST3 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst3));
- if (sysinfo->dsize == 2) {
- debug("\tMPDGHWST0 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst0));
- debug("\tMPDGHWST1 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst1));
- debug("\tMPDGHWST2 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst2));
- debug("\tMPDGHWST3 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst3));
- }
-
- debug("Final do_dqs_calibration error mask: 0x%x\n", errors);
-
- return errors;
-}
-#endif
-
-#if defined(CONFIG_MX6SX)
-/* Configure MX6SX mmdc iomux */
-void mx6sx_dram_iocfg(unsigned width,
- const struct mx6sx_iomux_ddr_regs *ddr,
- const struct mx6sx_iomux_grp_regs *grp)
-{
- struct mx6sx_iomux_ddr_regs *mx6_ddr_iomux;
- struct mx6sx_iomux_grp_regs *mx6_grp_iomux;
-
- mx6_ddr_iomux = (struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE;
- mx6_grp_iomux = (struct mx6sx_iomux_grp_regs *)MX6SX_IOM_GRP_BASE;
-
- /* DDR IO TYPE */
- writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
- writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
-
- /* CLOCK */
- writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
-
- /* ADDRESS */
- writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
- writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
- writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
-
- /* Control */
- writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
- writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
- writel(ddr->dram_sdcke0, &mx6_ddr_iomux->dram_sdcke0);
- writel(ddr->dram_sdcke1, &mx6_ddr_iomux->dram_sdcke1);
- writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
- writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
- writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
-
- /* Data Strobes */
- writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
- writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
- writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
- if (width >= 32) {
- writel(ddr->dram_sdqs2, &mx6_ddr_iomux->dram_sdqs2);
- writel(ddr->dram_sdqs3, &mx6_ddr_iomux->dram_sdqs3);
- }
-
- /* Data */
- writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
- writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
- writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
- if (width >= 32) {
- writel(grp->grp_b2ds, &mx6_grp_iomux->grp_b2ds);
- writel(grp->grp_b3ds, &mx6_grp_iomux->grp_b3ds);
- }
- writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
- writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
- if (width >= 32) {
- writel(ddr->dram_dqm2, &mx6_ddr_iomux->dram_dqm2);
- writel(ddr->dram_dqm3, &mx6_ddr_iomux->dram_dqm3);
- }
-}
-#endif
-
-#ifdef CONFIG_MX6UL
-void mx6ul_dram_iocfg(unsigned width,
- const struct mx6ul_iomux_ddr_regs *ddr,
- const struct mx6ul_iomux_grp_regs *grp)
-{
- struct mx6ul_iomux_ddr_regs *mx6_ddr_iomux;
- struct mx6ul_iomux_grp_regs *mx6_grp_iomux;
-
- mx6_ddr_iomux = (struct mx6ul_iomux_ddr_regs *)MX6UL_IOM_DDR_BASE;
- mx6_grp_iomux = (struct mx6ul_iomux_grp_regs *)MX6UL_IOM_GRP_BASE;
-
- /* DDR IO TYPE */
- writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
- writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
-
- /* CLOCK */
- writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
-
- /* ADDRESS */
- writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
- writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
- writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
-
- /* Control */
- writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
- writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
- writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
- writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
- writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
-
- /* Data Strobes */
- writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
- writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
- writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
-
- /* Data */
- writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
- writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
- writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
- writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
- writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
-}
-#endif
-
-#if defined(CONFIG_MX6SL)
-void mx6sl_dram_iocfg(unsigned width,
- const struct mx6sl_iomux_ddr_regs *ddr,
- const struct mx6sl_iomux_grp_regs *grp)
-{
- struct mx6sl_iomux_ddr_regs *mx6_ddr_iomux;
- struct mx6sl_iomux_grp_regs *mx6_grp_iomux;
-
- mx6_ddr_iomux = (struct mx6sl_iomux_ddr_regs *)MX6SL_IOM_DDR_BASE;
- mx6_grp_iomux = (struct mx6sl_iomux_grp_regs *)MX6SL_IOM_GRP_BASE;
-
- /* DDR IO TYPE */
- mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
- mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
-
- /* CLOCK */
- mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
-
- /* ADDRESS */
- mx6_ddr_iomux->dram_cas = ddr->dram_cas;
- mx6_ddr_iomux->dram_ras = ddr->dram_ras;
- mx6_grp_iomux->grp_addds = grp->grp_addds;
-
- /* Control */
- mx6_ddr_iomux->dram_reset = ddr->dram_reset;
- mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
- mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
-
- /* Data Strobes */
- mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
- mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
- mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
- if (width >= 32) {
- mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
- mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
- }
-
- /* Data */
- mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
- mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
- mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
- if (width >= 32) {
- mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
- mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
- }
-
- mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
- mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
- if (width >= 32) {
- mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
- mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
- }
-}
-#endif
-
-#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
-/* Configure MX6DQ mmdc iomux */
-void mx6dq_dram_iocfg(unsigned width,
- const struct mx6dq_iomux_ddr_regs *ddr,
- const struct mx6dq_iomux_grp_regs *grp)
-{
- volatile struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux;
- volatile struct mx6dq_iomux_grp_regs *mx6_grp_iomux;
-
- mx6_ddr_iomux = (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
- mx6_grp_iomux = (struct mx6dq_iomux_grp_regs *)MX6DQ_IOM_GRP_BASE;
-
- /* DDR IO Type */
- mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
- mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
-
- /* Clock */
- mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
- mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
-
- /* Address */
- mx6_ddr_iomux->dram_cas = ddr->dram_cas;
- mx6_ddr_iomux->dram_ras = ddr->dram_ras;
- mx6_grp_iomux->grp_addds = grp->grp_addds;
-
- /* Control */
- mx6_ddr_iomux->dram_reset = ddr->dram_reset;
- mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
- mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
- mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
- mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
- mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
- mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
-
- /* Data Strobes */
- mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
- mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
- mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
- if (width >= 32) {
- mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
- mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
- }
- if (width >= 64) {
- mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
- mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
- mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
- mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
- }
-
- /* Data */
- mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
- mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
- mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
- if (width >= 32) {
- mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
- mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
- }
- if (width >= 64) {
- mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
- mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
- mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
- mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
- }
- mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
- mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
- if (width >= 32) {
- mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
- mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
- }
- if (width >= 64) {
- mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
- mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
- mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
- mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
- }
-}
-#endif
-
-#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
-/* Configure MX6SDL mmdc iomux */
-void mx6sdl_dram_iocfg(unsigned width,
- const struct mx6sdl_iomux_ddr_regs *ddr,
- const struct mx6sdl_iomux_grp_regs *grp)
-{
- volatile struct mx6sdl_iomux_ddr_regs *mx6_ddr_iomux;
- volatile struct mx6sdl_iomux_grp_regs *mx6_grp_iomux;
-
- mx6_ddr_iomux = (struct mx6sdl_iomux_ddr_regs *)MX6SDL_IOM_DDR_BASE;
- mx6_grp_iomux = (struct mx6sdl_iomux_grp_regs *)MX6SDL_IOM_GRP_BASE;
-
- /* DDR IO Type */
- mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
- mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
-
- /* Clock */
- mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
- mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
-
- /* Address */
- mx6_ddr_iomux->dram_cas = ddr->dram_cas;
- mx6_ddr_iomux->dram_ras = ddr->dram_ras;
- mx6_grp_iomux->grp_addds = grp->grp_addds;
-
- /* Control */
- mx6_ddr_iomux->dram_reset = ddr->dram_reset;
- mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
- mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
- mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
- mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
- mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
- mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
-
- /* Data Strobes */
- mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
- mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
- mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
- if (width >= 32) {
- mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
- mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
- }
- if (width >= 64) {
- mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
- mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
- mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
- mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
- }
-
- /* Data */
- mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
- mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
- mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
- if (width >= 32) {
- mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
- mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
- }
- if (width >= 64) {
- mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
- mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
- mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
- mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
- }
- mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
- mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
- if (width >= 32) {
- mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
- mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
- }
- if (width >= 64) {
- mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
- mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
- mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
- mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
- }
-}
-#endif
-
-/*
- * Configure mx6 mmdc registers based on:
- * - board-specific memory configuration
- * - board-specific calibration data
- * - ddr3/lpddr2 chip details
- *
- * The various calculations here are derived from the Freescale
- * 1. i.Mx6DQSDL DDR3 Script Aid spreadsheet (DOC-94917) designed to generate
- * MMDC configuration registers based on memory system and memory chip
- * parameters.
- *
- * 2. i.Mx6SL LPDDR2 Script Aid spreadsheet V0.04 designed to generate MMDC
- * configuration registers based on memory system and memory chip
- * parameters.
- *
- * The defaults here are those which were specified in the spreadsheet.
- * For details on each register, refer to the IMX6DQRM and/or IMX6SDLRM
- * and/or IMX6SLRM section titled MMDC initialization.
- */
-#define MR(val, ba, cmd, cs1) \
- ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
-#define MMDC1(entry, value) do { \
- if (!is_mx6sx() && !is_mx6ul() && !is_mx6sl()) \
- mmdc1->entry = value; \
- } while (0)
-
-/*
- * According JESD209-2B-LPDDR2: Table 103
- * WL: write latency
- */
-static int lpddr2_wl(uint32_t mem_speed)
-{
- switch (mem_speed) {
- case 1066:
- case 933:
- return 4;
- case 800:
- return 3;
- case 677:
- case 533:
- return 2;
- case 400:
- case 333:
- return 1;
- default:
- puts("invalid memory speed\n");
- hang();
- }
-
- return 0;
-}
-
-/*
- * According JESD209-2B-LPDDR2: Table 103
- * RL: read latency
- */
-static int lpddr2_rl(uint32_t mem_speed)
-{
- switch (mem_speed) {
- case 1066:
- return 8;
- case 933:
- return 7;
- case 800:
- return 6;
- case 677:
- return 5;
- case 533:
- return 4;
- case 400:
- case 333:
- return 3;
- default:
- puts("invalid memory speed\n");
- hang();
- }
-
- return 0;
-}
-
-void mx6_lpddr2_cfg(const struct mx6_ddr_sysinfo *sysinfo,
- const struct mx6_mmdc_calibration *calib,
- const struct mx6_lpddr2_cfg *lpddr2_cfg)
-{
- volatile struct mmdc_p_regs *mmdc0;
- u32 val;
- u8 tcke, tcksrx, tcksre, trrd;
- u8 twl, txp, tfaw, tcl;
- u16 tras, twr, tmrd, trtp, twtr, trfc, txsr;
- u16 trcd_lp, trppb_lp, trpab_lp, trc_lp;
- u16 cs0_end;
- u8 coladdr;
- int clkper; /* clock period in picoseconds */
- int clock; /* clock freq in mHz */
- int cs;
-
- /* only support 16/32 bits */
- if (sysinfo->dsize > 1)
- hang();
-
- mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
-
- clock = mxc_get_clock(MXC_DDR_CLK) / 1000000U;
- clkper = (1000 * 1000) / clock; /* pico seconds */
-
- twl = lpddr2_wl(lpddr2_cfg->mem_speed) - 1;
-
- /* LPDDR2-S2 and LPDDR2-S4 have the same tRFC value. */
- switch (lpddr2_cfg->density) {
- case 1:
- case 2:
- case 4:
- trfc = DIV_ROUND_UP(130000, clkper) - 1;
- txsr = DIV_ROUND_UP(140000, clkper) - 1;
- break;
- case 8:
- trfc = DIV_ROUND_UP(210000, clkper) - 1;
- txsr = DIV_ROUND_UP(220000, clkper) - 1;
- break;
- default:
- /*
- * 64Mb, 128Mb, 256Mb, 512Mb are not supported currently.
- */
- hang();
- break;
- }
- /*
- * txpdll, txpr, taonpd and taofpd are not relevant in LPDDR2 mode,
- * set them to 0. */
- txp = DIV_ROUND_UP(7500, clkper) - 1;
- tcke = 3;
- if (lpddr2_cfg->mem_speed == 333)
- tfaw = DIV_ROUND_UP(60000, clkper) - 1;
- else
- tfaw = DIV_ROUND_UP(50000, clkper) - 1;
- trrd = DIV_ROUND_UP(10000, clkper) - 1;
-
- /* tckesr for LPDDR2 */
- tcksre = DIV_ROUND_UP(15000, clkper);
- tcksrx = tcksre;
- twr = DIV_ROUND_UP(15000, clkper) - 1;
- /*
- * tMRR: 2, tMRW: 5
- * tMRD should be set to max(tMRR, tMRW)
- */
- tmrd = 5;
- tras = DIV_ROUND_UP(lpddr2_cfg->trasmin, clkper / 10) - 1;
- /* LPDDR2 mode use tRCD_LP filed in MDCFG3. */
- trcd_lp = DIV_ROUND_UP(lpddr2_cfg->trcd_lp, clkper / 10) - 1;
- trc_lp = DIV_ROUND_UP(lpddr2_cfg->trasmin + lpddr2_cfg->trppb_lp,
- clkper / 10) - 1;
- trppb_lp = DIV_ROUND_UP(lpddr2_cfg->trppb_lp, clkper / 10) - 1;
- trpab_lp = DIV_ROUND_UP(lpddr2_cfg->trpab_lp, clkper / 10) - 1;
- /* To LPDDR2, CL in MDCFG0 refers to RL */
- tcl = lpddr2_rl(lpddr2_cfg->mem_speed) - 3;
- twtr = DIV_ROUND_UP(7500, clkper) - 1;
- trtp = DIV_ROUND_UP(7500, clkper) - 1;
-
- cs0_end = 4 * sysinfo->cs_density - 1;
-
- debug("density:%d Gb (%d Gb per chip)\n",
- sysinfo->cs_density, lpddr2_cfg->density);
- debug("clock: %dMHz (%d ps)\n", clock, clkper);
- debug("memspd:%d\n", lpddr2_cfg->mem_speed);
- debug("trcd_lp=%d\n", trcd_lp);
- debug("trppb_lp=%d\n", trppb_lp);
- debug("trpab_lp=%d\n", trpab_lp);
- debug("trc_lp=%d\n", trc_lp);
- debug("tcke=%d\n", tcke);
- debug("tcksrx=%d\n", tcksrx);
- debug("tcksre=%d\n", tcksre);
- debug("trfc=%d\n", trfc);
- debug("txsr=%d\n", txsr);
- debug("txp=%d\n", txp);
- debug("tfaw=%d\n", tfaw);
- debug("tcl=%d\n", tcl);
- debug("tras=%d\n", tras);
- debug("twr=%d\n", twr);
- debug("tmrd=%d\n", tmrd);
- debug("twl=%d\n", twl);
- debug("trtp=%d\n", trtp);
- debug("twtr=%d\n", twtr);
- debug("trrd=%d\n", trrd);
- debug("cs0_end=%d\n", cs0_end);
- debug("ncs=%d\n", sysinfo->ncs);
-
- /*
- * board-specific configuration:
- * These values are determined empirically and vary per board layout
- */
- mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
- mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
- mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
- mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
- mmdc0->mprddlctl = calib->p0_mprddlctl;
- mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
- mmdc0->mpzqlp2ctl = calib->mpzqlp2ctl;
-
- /* Read data DQ Byte0-3 delay */
- mmdc0->mprddqby0dl = 0x33333333;
- mmdc0->mprddqby1dl = 0x33333333;
- if (sysinfo->dsize > 0) {
- mmdc0->mprddqby2dl = 0x33333333;
- mmdc0->mprddqby3dl = 0x33333333;
- }
-
- /* Write data DQ Byte0-3 delay */
- mmdc0->mpwrdqby0dl = 0xf3333333;
- mmdc0->mpwrdqby1dl = 0xf3333333;
- if (sysinfo->dsize > 0) {
- mmdc0->mpwrdqby2dl = 0xf3333333;
- mmdc0->mpwrdqby3dl = 0xf3333333;
- }
-
- /*
- * In LPDDR2 mode this register should be cleared,
- * so no termination will be activated.
- */
- mmdc0->mpodtctrl = 0;
-
- /* complete calibration */
- val = (1 << 11); /* Force measurement on delay-lines */
- mmdc0->mpmur0 = val;
-
- /* Step 1: configuration request */
- mmdc0->mdscr = (u32)(1 << 15); /* config request */
-
- /* Step 2: Timing configuration */
- mmdc0->mdcfg0 = (trfc << 24) | (txsr << 16) | (txp << 13) |
- (tfaw << 4) | tcl;
- mmdc0->mdcfg1 = (tras << 16) | (twr << 9) | (tmrd << 5) | twl;
- mmdc0->mdcfg2 = (trtp << 6) | (twtr << 3) | trrd;
- mmdc0->mdcfg3lp = (trc_lp << 16) | (trcd_lp << 8) |
- (trppb_lp << 4) | trpab_lp;
- mmdc0->mdotc = 0;
-
- mmdc0->mdasp = cs0_end; /* CS addressing */
-
- /* Step 3: Configure DDR type */
- mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
- (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
- (sysinfo->ralat << 6) | (1 << 3);
-
- /* Step 4: Configure delay while leaving reset */
- mmdc0->mdor = (sysinfo->sde_to_rst << 8) |
- (sysinfo->rst_to_cke << 0);
-
- /* Step 5: Configure DDR physical parameters (density and burst len) */
- coladdr = lpddr2_cfg->coladdr;
- if (lpddr2_cfg->coladdr == 8) /* 8-bit COL is 0x3 */
- coladdr += 4;
- else if (lpddr2_cfg->coladdr == 12) /* 12-bit COL is 0x4 */
- coladdr += 1;
- mmdc0->mdctl = (lpddr2_cfg->rowaddr - 11) << 24 | /* ROW */
- (coladdr - 9) << 20 | /* COL */
- (0 << 19) | /* Burst Length = 4 for LPDDR2 */
- (sysinfo->dsize << 16); /* DDR data bus size */
-
- /* Step 6: Perform ZQ calibration */
- val = 0xa1390003; /* one-time HW ZQ calib */
- mmdc0->mpzqhwctrl = val;
-
- /* Step 7: Enable MMDC with desired chip select */
- mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
- ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
-
- /* Step 8: Write Mode Registers to Init LPDDR2 devices */
- for (cs = 0; cs < sysinfo->ncs; cs++) {
- /* MR63: reset */
- mmdc0->mdscr = MR(63, 0, 3, cs);
- /* MR10: calibration,
- * 0xff is calibration command after intilization.
- */
- val = 0xA | (0xff << 8);
- mmdc0->mdscr = MR(val, 0, 3, cs);
- /* MR1 */
- val = 0x1 | (0x82 << 8);
- mmdc0->mdscr = MR(val, 0, 3, cs);
- /* MR2 */
- val = 0x2 | (0x04 << 8);
- mmdc0->mdscr = MR(val, 0, 3, cs);
- /* MR3 */
- val = 0x3 | (0x02 << 8);
- mmdc0->mdscr = MR(val, 0, 3, cs);
- }
-
- /* Step 10: Power down control and self-refresh */
- mmdc0->mdpdc = (tcke & 0x7) << 16 |
- 5 << 12 | /* PWDT_1: 256 cycles */
- 5 << 8 | /* PWDT_0: 256 cycles */
- 1 << 6 | /* BOTH_CS_PD */
- (tcksrx & 0x7) << 3 |
- (tcksre & 0x7);
- mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
-
- /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
- val = 0xa1310003;
- mmdc0->mpzqhwctrl = val;
-
- /* Step 12: Configure and activate periodic refresh */
- mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);
-
- /* Step 13: Deassert config request - init complete */
- mmdc0->mdscr = 0x00000000;
-
- /* wait for auto-ZQ calibration to complete */
- mdelay(1);
-}
-
-void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
- const struct mx6_mmdc_calibration *calib,
- const struct mx6_ddr3_cfg *ddr3_cfg)
-{
- volatile struct mmdc_p_regs *mmdc0;
- volatile struct mmdc_p_regs *mmdc1;
- u32 val;
- u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
- u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
- u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */
- u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
- u16 cs0_end;
- u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
- u8 coladdr;
- int clkper; /* clock period in picoseconds */
- int clock; /* clock freq in MHz */
- int cs;
- u16 mem_speed = ddr3_cfg->mem_speed;
-
- mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
- if (!is_mx6sx() && !is_mx6ul() && !is_mx6sl())
- mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
-
- /* Limit mem_speed for MX6D/MX6Q */
- if (is_mx6dq() || is_mx6dqp()) {
- if (mem_speed > 1066)
- mem_speed = 1066; /* 1066 MT/s */
-
- tcwl = 4;
- }
- /* Limit mem_speed for MX6S/MX6DL */
- else {
- if (mem_speed > 800)
- mem_speed = 800; /* 800 MT/s */
-
- tcwl = 3;
- }
-
- clock = mem_speed / 2;
- /*
- * Data rate of 1066 MT/s requires 533 MHz DDR3 clock, but MX6D/Q supports
- * up to 528 MHz, so reduce the clock to fit chip specs
- */
- if (is_mx6dq() || is_mx6dqp()) {
- if (clock > 528)
- clock = 528; /* 528 MHz */
- }
-
- clkper = (1000 * 1000) / clock; /* pico seconds */
- todtlon = tcwl;
- taxpd = tcwl;
- tanpd = tcwl;
-
- switch (ddr3_cfg->density) {
- case 1: /* 1Gb per chip */
- trfc = DIV_ROUND_UP(110000, clkper) - 1;
- txs = DIV_ROUND_UP(120000, clkper) - 1;
- break;
- case 2: /* 2Gb per chip */
- trfc = DIV_ROUND_UP(160000, clkper) - 1;
- txs = DIV_ROUND_UP(170000, clkper) - 1;
- break;
- case 4: /* 4Gb per chip */
- trfc = DIV_ROUND_UP(260000, clkper) - 1;
- txs = DIV_ROUND_UP(270000, clkper) - 1;
- break;
- case 8: /* 8Gb per chip */
- trfc = DIV_ROUND_UP(350000, clkper) - 1;
- txs = DIV_ROUND_UP(360000, clkper) - 1;
- break;
- default:
- /* invalid density */
- puts("invalid chip density\n");
- hang();
- break;
- }
- txpr = txs;
-
- switch (mem_speed) {
- case 800:
- txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
- tcke = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
- if (ddr3_cfg->pagesz == 1) {
- tfaw = DIV_ROUND_UP(40000, clkper) - 1;
- trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
- } else {
- tfaw = DIV_ROUND_UP(50000, clkper) - 1;
- trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
- }
- break;
- case 1066:
- txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
- tcke = DIV_ROUND_UP(max(3 * clkper, 5625), clkper) - 1;
- if (ddr3_cfg->pagesz == 1) {
- tfaw = DIV_ROUND_UP(37500, clkper) - 1;
- trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1;
- } else {
- tfaw = DIV_ROUND_UP(50000, clkper) - 1;
- trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
- }
- break;
- default:
- puts("invalid memory speed\n");
- hang();
- break;
- }
- txpdll = DIV_ROUND_UP(max(10 * clkper, 24000), clkper) - 1;
- tcksre = DIV_ROUND_UP(max(5 * clkper, 10000), clkper);
- taonpd = DIV_ROUND_UP(2000, clkper) - 1;
- tcksrx = tcksre;
- taofpd = taonpd;
- twr = DIV_ROUND_UP(15000, clkper) - 1;
- tmrd = DIV_ROUND_UP(max(12 * clkper, 15000), clkper) - 1;
- trc = DIV_ROUND_UP(ddr3_cfg->trcmin, clkper / 10) - 1;
- tras = DIV_ROUND_UP(ddr3_cfg->trasmin, clkper / 10) - 1;
- tcl = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 3;
- trp = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 1;
- twtr = ROUND(max(4 * clkper, 7500) / clkper, 1) - 1;
- trcd = trp;
- trtp = twtr;
- cs0_end = 4 * sysinfo->cs_density - 1;
-
- debug("density:%d Gb (%d Gb per chip)\n",
- sysinfo->cs_density, ddr3_cfg->density);
- debug("clock: %dMHz (%d ps)\n", clock, clkper);
- debug("memspd:%d\n", mem_speed);
- debug("tcke=%d\n", tcke);
- debug("tcksrx=%d\n", tcksrx);
- debug("tcksre=%d\n", tcksre);
- debug("taofpd=%d\n", taofpd);
- debug("taonpd=%d\n", taonpd);
- debug("todtlon=%d\n", todtlon);
- debug("tanpd=%d\n", tanpd);
- debug("taxpd=%d\n", taxpd);
- debug("trfc=%d\n", trfc);
- debug("txs=%d\n", txs);
- debug("txp=%d\n", txp);
- debug("txpdll=%d\n", txpdll);
- debug("tfaw=%d\n", tfaw);
- debug("tcl=%d\n", tcl);
- debug("trcd=%d\n", trcd);
- debug("trp=%d\n", trp);
- debug("trc=%d\n", trc);
- debug("tras=%d\n", tras);
- debug("twr=%d\n", twr);
- debug("tmrd=%d\n", tmrd);
- debug("tcwl=%d\n", tcwl);
- debug("tdllk=%d\n", tdllk);
- debug("trtp=%d\n", trtp);
- debug("twtr=%d\n", twtr);
- debug("trrd=%d\n", trrd);
- debug("txpr=%d\n", txpr);
- debug("cs0_end=%d\n", cs0_end);
- debug("ncs=%d\n", sysinfo->ncs);
- debug("Rtt_wr=%d\n", sysinfo->rtt_wr);
- debug("Rtt_nom=%d\n", sysinfo->rtt_nom);
- debug("SRT=%d\n", ddr3_cfg->SRT);
- debug("twr=%d\n", twr);
-
- /*
- * board-specific configuration:
- * These values are determined empirically and vary per board layout
- * see:
- * appnote, ddr3 spreadsheet
- */
- mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
- mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
- mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
- mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
- mmdc0->mprddlctl = calib->p0_mprddlctl;
- mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
- if (sysinfo->dsize > 1) {
- MMDC1(mpwldectrl0, calib->p1_mpwldectrl0);
- MMDC1(mpwldectrl1, calib->p1_mpwldectrl1);
- MMDC1(mpdgctrl0, calib->p1_mpdgctrl0);
- MMDC1(mpdgctrl1, calib->p1_mpdgctrl1);
- MMDC1(mprddlctl, calib->p1_mprddlctl);
- MMDC1(mpwrdlctl, calib->p1_mpwrdlctl);
- }
-
- /* Read data DQ Byte0-3 delay */
- mmdc0->mprddqby0dl = 0x33333333;
- mmdc0->mprddqby1dl = 0x33333333;
- if (sysinfo->dsize > 0) {
- mmdc0->mprddqby2dl = 0x33333333;
- mmdc0->mprddqby3dl = 0x33333333;
- }
-
- if (sysinfo->dsize > 1) {
- MMDC1(mprddqby0dl, 0x33333333);
- MMDC1(mprddqby1dl, 0x33333333);
- MMDC1(mprddqby2dl, 0x33333333);
- MMDC1(mprddqby3dl, 0x33333333);
- }
-
- /* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */
- val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227;
- mmdc0->mpodtctrl = val;
- if (sysinfo->dsize > 1)
- MMDC1(mpodtctrl, val);
-
- /* complete calibration */
- val = (1 << 11); /* Force measurement on delay-lines */
- mmdc0->mpmur0 = val;
- if (sysinfo->dsize > 1)
- MMDC1(mpmur0, val);
-
- /* Step 1: configuration request */
- mmdc0->mdscr = (u32)(1 << 15); /* config request */
-
- /* Step 2: Timing configuration */
- mmdc0->mdcfg0 = (trfc << 24) | (txs << 16) | (txp << 13) |
- (txpdll << 9) | (tfaw << 4) | tcl;
- mmdc0->mdcfg1 = (trcd << 29) | (trp << 26) | (trc << 21) |
- (tras << 16) | (1 << 15) /* trpa */ |
- (twr << 9) | (tmrd << 5) | tcwl;
- mmdc0->mdcfg2 = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;
- mmdc0->mdotc = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) |
- (taxpd << 16) | (todtlon << 12) | (todt_idle_off << 4);
- mmdc0->mdasp = cs0_end; /* CS addressing */
-
- /* Step 3: Configure DDR type */
- mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
- (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
- (sysinfo->ralat << 6);
-
- /* Step 4: Configure delay while leaving reset */
- mmdc0->mdor = (txpr << 16) | (sysinfo->sde_to_rst << 8) |
- (sysinfo->rst_to_cke << 0);
-
- /* Step 5: Configure DDR physical parameters (density and burst len) */
- coladdr = ddr3_cfg->coladdr;
- if (ddr3_cfg->coladdr == 8) /* 8-bit COL is 0x3 */
- coladdr += 4;
- else if (ddr3_cfg->coladdr == 12) /* 12-bit COL is 0x4 */
- coladdr += 1;
- mmdc0->mdctl = (ddr3_cfg->rowaddr - 11) << 24 | /* ROW */
- (coladdr - 9) << 20 | /* COL */
- (1 << 19) | /* Burst Length = 8 for DDR3 */
- (sysinfo->dsize << 16); /* DDR data bus size */
-
- /* Step 6: Perform ZQ calibration */
- val = 0xa1390001; /* one-time HW ZQ calib */
- mmdc0->mpzqhwctrl = val;
- if (sysinfo->dsize > 1)
- MMDC1(mpzqhwctrl, val);
-
- /* Step 7: Enable MMDC with desired chip select */
- mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
- ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
-
- /* Step 8: Write Mode Registers to Init DDR3 devices */
- for (cs = 0; cs < sysinfo->ncs; cs++) {
- /* MR2 */
- val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 |
- ((tcwl - 3) & 3) << 3;
- debug("MR2 CS%d: 0x%08x\n", cs, (u32)MR(val, 2, 3, cs));
- mmdc0->mdscr = MR(val, 2, 3, cs);
- /* MR3 */
- debug("MR3 CS%d: 0x%08x\n", cs, (u32)MR(0, 3, 3, cs));
- mmdc0->mdscr = MR(0, 3, 3, cs);
- /* MR1 */
- val = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 |
- ((sysinfo->rtt_nom & 2) ? 1 : 0) << 6;
- debug("MR1 CS%d: 0x%08x\n", cs, (u32)MR(val, 1, 3, cs));
- mmdc0->mdscr = MR(val, 1, 3, cs);
- /* MR0 */
- val = ((tcl - 1) << 4) | /* CAS */
- (1 << 8) | /* DLL Reset */
- ((twr - 3) << 9) | /* Write Recovery */
- (sysinfo->pd_fast_exit << 12); /* Precharge PD PLL on */
- debug("MR0 CS%d: 0x%08x\n", cs, (u32)MR(val, 0, 3, cs));
- mmdc0->mdscr = MR(val, 0, 3, cs);
- /* ZQ calibration */
- val = (1 << 10);
- mmdc0->mdscr = MR(val, 0, 4, cs);
- }
-
- /* Step 10: Power down control and self-refresh */
- mmdc0->mdpdc = (tcke & 0x7) << 16 |
- 5 << 12 | /* PWDT_1: 256 cycles */
- 5 << 8 | /* PWDT_0: 256 cycles */
- 1 << 6 | /* BOTH_CS_PD */
- (tcksrx & 0x7) << 3 |
- (tcksre & 0x7);
- if (!sysinfo->pd_fast_exit)
- mmdc0->mdpdc |= (1 << 7); /* SLOW_PD */
- mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
-
- /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
- val = 0xa1390003;
- mmdc0->mpzqhwctrl = val;
- if (sysinfo->dsize > 1)
- MMDC1(mpzqhwctrl, val);
-
- /* Step 12: Configure and activate periodic refresh */
- mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);
-
- /* Step 13: Deassert config request - init complete */
- mmdc0->mdscr = 0x00000000;
-
- /* wait for auto-ZQ calibration to complete */
- mdelay(1);
-}
-
-void mmdc_read_calibration(struct mx6_ddr_sysinfo const *sysinfo,
- struct mx6_mmdc_calibration *calib)
-{
- struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
- struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
-
- calib->p0_mpwldectrl0 = readl(&mmdc0->mpwldectrl0);
- calib->p0_mpwldectrl1 = readl(&mmdc0->mpwldectrl1);
- calib->p0_mpdgctrl0 = readl(&mmdc0->mpdgctrl0);
- calib->p0_mpdgctrl1 = readl(&mmdc0->mpdgctrl1);
- calib->p0_mprddlctl = readl(&mmdc0->mprddlctl);
- calib->p0_mpwrdlctl = readl(&mmdc0->mpwrdlctl);
-
- if (sysinfo->dsize == 2) {
- calib->p1_mpwldectrl0 = readl(&mmdc1->mpwldectrl0);
- calib->p1_mpwldectrl1 = readl(&mmdc1->mpwldectrl1);
- calib->p1_mpdgctrl0 = readl(&mmdc1->mpdgctrl0);
- calib->p1_mpdgctrl1 = readl(&mmdc1->mpdgctrl1);
- calib->p1_mprddlctl = readl(&mmdc1->mprddlctl);
- calib->p1_mpwrdlctl = readl(&mmdc1->mpwrdlctl);
- }
-}
-
-void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
- const struct mx6_mmdc_calibration *calib,
- const void *ddr_cfg)
-{
- if (sysinfo->ddr_type == DDR_TYPE_DDR3) {
- mx6_ddr3_cfg(sysinfo, calib, ddr_cfg);
- } else if (sysinfo->ddr_type == DDR_TYPE_LPDDR2) {
- mx6_lpddr2_cfg(sysinfo, calib, ddr_cfg);
- } else {
- puts("Unsupported ddr type\n");
- hang();
- }
-}
+++ /dev/null
-/*
- * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
- * Copyright (C) 2016 Grinn
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/arch/clock.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/mx6ul_pins.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/io.h>
-#include <common.h>
-#include <fsl_esdhc.h>
-#include <linux/sizes.h>
-#include <mmc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-int dram_init(void)
-{
- gd->ram_size = imx_ddr_size();
-
- return 0;
-}
-
-static iomux_v3_cfg_t const emmc_pads[] = {
- MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-
- /* RST_B */
- MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-#ifdef CONFIG_FSL_ESDHC
-static struct fsl_esdhc_cfg emmc_cfg = {USDHC2_BASE_ADDR, 0, 8};
-
-#define EMMC_PWR_GPIO IMX_GPIO_NR(4, 10)
-
-int litesom_mmc_init(bd_t *bis)
-{
- int ret;
-
- /* eMMC */
- imx_iomux_v3_setup_multiple_pads(emmc_pads, ARRAY_SIZE(emmc_pads));
- gpio_direction_output(EMMC_PWR_GPIO, 0);
- udelay(500);
- gpio_direction_output(EMMC_PWR_GPIO, 1);
- emmc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-
- ret = fsl_esdhc_initialize(bis, &emmc_cfg);
- if (ret) {
- printf("Warning: failed to initialize mmc dev 1 (eMMC)\n");
- return ret;
- }
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_SPL_BUILD
-#include <libfdt.h>
-#include <spl.h>
-#include <asm/arch/mx6-ddr.h>
-
-
-static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
- .grp_addds = 0x00000030,
- .grp_ddrmode_ctl = 0x00020000,
- .grp_b0ds = 0x00000030,
- .grp_ctlds = 0x00000030,
- .grp_b1ds = 0x00000030,
- .grp_ddrpke = 0x00000000,
- .grp_ddrmode = 0x00020000,
- .grp_ddr_type = 0x000c0000,
-};
-
-static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
- .dram_dqm0 = 0x00000030,
- .dram_dqm1 = 0x00000030,
- .dram_ras = 0x00000030,
- .dram_cas = 0x00000030,
- .dram_odt0 = 0x00000030,
- .dram_odt1 = 0x00000030,
- .dram_sdba2 = 0x00000000,
- .dram_sdclk_0 = 0x00000030,
- .dram_sdqs0 = 0x00000030,
- .dram_sdqs1 = 0x00000030,
- .dram_reset = 0x00000030,
-};
-
-static struct mx6_mmdc_calibration mx6_mmcd_calib = {
- .p0_mpwldectrl0 = 0x00000000,
- .p0_mpdgctrl0 = 0x41570155,
- .p0_mprddlctl = 0x4040474A,
- .p0_mpwrdlctl = 0x40405550,
-};
-
-struct mx6_ddr_sysinfo ddr_sysinfo = {
- .dsize = 0,
- .cs_density = 20,
- .ncs = 1,
- .cs1_mirror = 0,
- .rtt_wr = 2,
- .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
- .walat = 0, /* Write additional latency */
- .ralat = 5, /* Read additional latency */
- .mif3_mode = 3, /* Command prediction working mode */
- .bi_on = 1, /* Bank interleaving enabled */
- .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
- .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
- .ddr_type = DDR_TYPE_DDR3,
- .refsel = 0, /* Refresh cycles at 64KHz */
- .refr = 1, /* 2 refresh commands per refresh cycle */
-};
-
-static struct mx6_ddr3_cfg mem_ddr = {
- .mem_speed = 800,
- .density = 4,
- .width = 16,
- .banks = 8,
- .rowaddr = 15,
- .coladdr = 10,
- .pagesz = 2,
- .trcd = 1375,
- .trcmin = 4875,
- .trasmin = 3500,
-};
-
-static void ccgr_init(void)
-{
- struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- writel(0xFFFFFFFF, &ccm->CCGR0);
- writel(0xFFFFFFFF, &ccm->CCGR1);
- writel(0xFFFFFFFF, &ccm->CCGR2);
- writel(0xFFFFFFFF, &ccm->CCGR3);
- writel(0xFFFFFFFF, &ccm->CCGR4);
- writel(0xFFFFFFFF, &ccm->CCGR5);
- writel(0xFFFFFFFF, &ccm->CCGR6);
- writel(0xFFFFFFFF, &ccm->CCGR7);
-}
-
-static void spl_dram_init(void)
-{
- unsigned long ram_size;
-
- mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
- mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
-
- /*
- * Get actual RAM size, so we can adjust DDR row size for <512M
- * memories
- */
- ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_512M);
- if (ram_size < SZ_512M) {
- mem_ddr.rowaddr = 14;
- mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
- }
-}
-
-void litesom_init_f(void)
-{
- ccgr_init();
-
- /* setup AIPS and disable watchdog */
- arch_cpu_init();
-
-#ifdef CONFIG_BOARD_EARLY_INIT_F
- board_early_init_f();
-#endif
-
- /* setup GP timer */
- timer_init();
-
- /* UART clocks enabled and gd valid - init serial console */
- preloader_console_init();
-
- /* DDR initialization */
- spl_dram_init();
-}
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2014
- * Gabriel Huau <contact@huau-gabriel.fr>
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <linux/errno.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/imx-regs.h>
-
-#define MAX_CPUS 4
-static struct src *src = (struct src *)SRC_BASE_ADDR;
-
-static uint32_t cpu_reset_mask[MAX_CPUS] = {
- 0, /* We don't really want to modify the cpu0 */
- SRC_SCR_CORE_1_RESET_MASK,
- SRC_SCR_CORE_2_RESET_MASK,
- SRC_SCR_CORE_3_RESET_MASK
-};
-
-static uint32_t cpu_ctrl_mask[MAX_CPUS] = {
- 0, /* We don't really want to modify the cpu0 */
- SRC_SCR_CORE_1_ENABLE_MASK,
- SRC_SCR_CORE_2_ENABLE_MASK,
- SRC_SCR_CORE_3_ENABLE_MASK
-};
-
-int cpu_reset(int nr)
-{
- /* Software reset of the CPU N */
- src->scr |= cpu_reset_mask[nr];
- return 0;
-}
-
-int cpu_status(int nr)
-{
- printf("core %d => %d\n", nr, !!(src->scr & cpu_ctrl_mask[nr]));
- return 0;
-}
-
-int cpu_release(int nr, int argc, char *const argv[])
-{
- uint32_t boot_addr;
-
- boot_addr = simple_strtoul(argv[0], NULL, 16);
-
- switch (nr) {
- case 1:
- src->gpr3 = boot_addr;
- break;
- case 2:
- src->gpr5 = boot_addr;
- break;
- case 3:
- src->gpr7 = boot_addr;
- break;
- default:
- return 1;
- }
-
- /* CPU N is ready to start */
- src->scr |= cpu_ctrl_mask[nr];
-
- return 0;
-}
-
-int is_core_valid(unsigned int core)
-{
- uint32_t nr_cores = get_nr_cpus();
-
- if (core > nr_cores)
- return 0;
-
- return 1;
-}
-
-int cpu_disable(int nr)
-{
- /* Disable the CPU N */
- src->scr &= ~cpu_ctrl_mask[nr];
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2017 Armadeus Systems
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/arch/clock.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/arch/mx6ul_pins.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/io.h>
-#include <common.h>
-#include <environment.h>
-#include <fsl_esdhc.h>
-#include <mmc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_FEC_MXC
-#include <miiphy.h>
-
-#define MDIO_PAD_CTRL ( \
- PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm \
-)
-
-#define ENET_PAD_CTRL_PU ( \
- PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm \
-)
-
-#define ENET_PAD_CTRL_PD ( \
- PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm \
-)
-
-#define ENET_CLK_PAD_CTRL ( \
- PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST \
-)
-
-static iomux_v3_cfg_t const fec1_pads[] = {
- MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
- MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(MDIO_PAD_CTRL),
- MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
- MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
- MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
- MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
- MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
- MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
- MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
- /* PHY Int */
- MX6_PAD_NAND_DQS__GPIO4_IO16 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
- /* PHY Reset */
- MX6_PAD_NAND_DATA00__GPIO4_IO02 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
- MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
-};
-
-int board_phy_config(struct phy_device *phydev)
-{
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
-
- if (phydev->drv->config)
- phydev->drv->config(phydev);
-
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
- struct gpio_desc rst;
- int ret;
-
- /* Use 50M anatop loopback REF_CLK1 for ENET1,
- * clear gpr1[13], set gpr1[17] */
- clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
- IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
-
- ret = enable_fec_anatop_clock(0, ENET_50MHZ);
- if (ret)
- return ret;
-
- enable_enet_clk(1);
-
- imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
-
- ret = dm_gpio_lookup_name("GPIO4_2", &rst);
- if (ret) {
- printf("Cannot get GPIO4_2\n");
- return ret;
- }
-
- ret = dm_gpio_request(&rst, "phy-rst");
- if (ret) {
- printf("Cannot request GPIO4_2\n");
- return ret;
- }
-
- dm_gpio_set_dir_flags(&rst, GPIOD_IS_OUT);
- dm_gpio_set_value(&rst, 0);
- udelay(1000);
- dm_gpio_set_value(&rst, 1);
-
- return fecmxc_initialize(bis);
-}
-#endif /* CONFIG_FEC_MXC */
-
-int board_init(void)
-{
- /* Address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
- return 0;
-}
-
-int __weak opos6ul_board_late_init(void)
-{
- return 0;
-}
-
-int board_late_init(void)
-{
- struct src *psrc = (struct src *)SRC_BASE_ADDR;
- unsigned reg = readl(&psrc->sbmr2);
-
- /* In bootstrap don't use the env vars */
- if (((reg & 0x3000000) >> 24) == 0x1) {
- set_default_env(NULL);
- setenv("preboot", "");
- }
-
- return opos6ul_board_late_init();
-}
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- return cfg->esdhc_base == USDHC1_BASE_ADDR;
-}
-
-int dram_init(void)
-{
- gd->ram_size = imx_ddr_size();
-
- return 0;
-}
-
-#ifdef CONFIG_SPL_BUILD
-#include <asm/arch/mx6-ddr.h>
-#include <asm/arch/opos6ul.h>
-#include <libfdt.h>
-#include <spl.h>
-
-#define USDHC_PAD_CTRL ( \
- PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST \
-)
-
-struct fsl_esdhc_cfg usdhc_cfg[1] = {
- {USDHC1_BASE_ADDR, 0, 8},
-};
-
-static iomux_v3_cfg_t const usdhc1_pads[] = {
- MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-};
-
-static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
- .grp_addds = 0x00000030,
- .grp_ddrmode_ctl = 0x00020000,
- .grp_b0ds = 0x00000030,
- .grp_ctlds = 0x00000030,
- .grp_b1ds = 0x00000030,
- .grp_ddrpke = 0x00000000,
- .grp_ddrmode = 0x00020000,
- .grp_ddr_type = 0x000c0000,
-};
-
-static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
- .dram_dqm0 = 0x00000030,
- .dram_dqm1 = 0x00000030,
- .dram_ras = 0x00000030,
- .dram_cas = 0x00000030,
- .dram_odt0 = 0x00000030,
- .dram_odt1 = 0x00000030,
- .dram_sdba2 = 0x00000000,
- .dram_sdclk_0 = 0x00000008,
- .dram_sdqs0 = 0x00000038,
- .dram_sdqs1 = 0x00000030,
- .dram_reset = 0x00000030,
-};
-
-static struct mx6_mmdc_calibration mx6_mmcd_calib = {
- .p0_mpwldectrl0 = 0x00070007,
- .p0_mpdgctrl0 = 0x41490145,
- .p0_mprddlctl = 0x40404546,
- .p0_mpwrdlctl = 0x4040524D,
-};
-
-struct mx6_ddr_sysinfo ddr_sysinfo = {
- .dsize = 0,
- .cs_density = 20,
- .ncs = 1,
- .cs1_mirror = 0,
- .rtt_wr = 2,
- .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
- .walat = 1, /* Write additional latency */
- .ralat = 5, /* Read additional latency */
- .mif3_mode = 3, /* Command prediction working mode */
- .bi_on = 1, /* Bank interleaving enabled */
- .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
- .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
- .ddr_type = DDR_TYPE_DDR3,
-};
-
-static struct mx6_ddr3_cfg mem_ddr = {
- .mem_speed = 800,
- .density = 2,
- .width = 16,
- .banks = 8,
- .rowaddr = 14,
- .coladdr = 10,
- .pagesz = 2,
- .trcd = 1500,
- .trcmin = 5250,
- .trasmin = 3750,
-};
-
-int board_mmc_init(bd_t *bis)
-{
- imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
-}
-
-static void ccgr_init(void)
-{
- struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- writel(0xFFFFFFFF, &ccm->CCGR0);
- writel(0xFFFFFFFF, &ccm->CCGR1);
- writel(0xFFFFFFFF, &ccm->CCGR2);
- writel(0xFFFFFFFF, &ccm->CCGR3);
- writel(0xFFFFFFFF, &ccm->CCGR4);
- writel(0xFFFFFFFF, &ccm->CCGR5);
- writel(0xFFFFFFFF, &ccm->CCGR6);
- writel(0xFFFFFFFF, &ccm->CCGR7);
-}
-
-static void spl_dram_init(void)
-{
- struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
- struct fuse_bank *bank = &ocotp->bank[4];
- struct fuse_bank4_regs *fuse =
- (struct fuse_bank4_regs *)bank->fuse_regs;
- int reg = readl(&fuse->gp1);
-
- /* 512MB of RAM */
- if (reg & 0x1) {
- mem_ddr.density = 4;
- mem_ddr.rowaddr = 15;
- mem_ddr.trcd = 1375;
- mem_ddr.trcmin = 4875;
- mem_ddr.trasmin = 3500;
- }
-
- mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
- mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
-}
-
-void board_init_f(ulong dummy)
-{
- ccgr_init();
-
- /* setup AIPS and disable watchdog */
- arch_cpu_init();
-
- /* setup GP timer */
- timer_init();
-
- /* UART clocks enabled and gd valid - init serial console */
- opos6ul_setup_uart_debug();
- preloader_console_init();
-
- /* DDR initialization */
- spl_dram_init();
-}
-#endif /* CONFIG_SPL_BUILD */
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/errno.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/dma.h>
-#include <asm/imx-common/hab.h>
-#include <stdbool.h>
-#include <asm/arch/mxc_hdmi.h>
-#include <asm/arch/crm_regs.h>
-#include <dm.h>
-#include <imx_thermal.h>
-#include <mmc.h>
-
-enum ldo_reg {
- LDO_ARM,
- LDO_SOC,
- LDO_PU,
-};
-
-struct scu_regs {
- u32 ctrl;
- u32 config;
- u32 status;
- u32 invalidate;
- u32 fpga_rev;
-};
-
-#if defined(CONFIG_IMX_THERMAL)
-static const struct imx_thermal_plat imx6_thermal_plat = {
- .regs = (void *)ANATOP_BASE_ADDR,
- .fuse_bank = 1,
- .fuse_word = 6,
-};
-
-U_BOOT_DEVICE(imx6_thermal) = {
- .name = "imx_thermal",
- .platdata = &imx6_thermal_plat,
-};
-#endif
-
-#if defined(CONFIG_SECURE_BOOT)
-struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
- .bank = 0,
- .word = 6,
-};
-#endif
-
-u32 get_nr_cpus(void)
-{
- struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
- return readl(&scu->config) & 3;
-}
-
-u32 get_cpu_rev(void)
-{
- struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
- u32 reg = readl(&anatop->digprog_sololite);
- u32 type = ((reg >> 16) & 0xff);
- u32 major, cfg = 0;
-
- if (type != MXC_CPU_MX6SL) {
- reg = readl(&anatop->digprog);
- struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
- cfg = readl(&scu->config) & 3;
- type = ((reg >> 16) & 0xff);
- if (type == MXC_CPU_MX6DL) {
- if (!cfg)
- type = MXC_CPU_MX6SOLO;
- }
-
- if (type == MXC_CPU_MX6Q) {
- if (cfg == 1)
- type = MXC_CPU_MX6D;
- }
-
- }
- major = ((reg >> 8) & 0xff);
- if ((major >= 1) &&
- ((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) {
- major--;
- type = MXC_CPU_MX6QP;
- if (cfg == 1)
- type = MXC_CPU_MX6DP;
- }
- reg &= 0xff; /* mx6 silicon revision */
- return (type << 12) | (reg + (0x10 * (major + 1)));
-}
-
-/*
- * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440)
- * defines a 2-bit SPEED_GRADING
- */
-#define OCOTP_CFG3_SPEED_SHIFT 16
-#define OCOTP_CFG3_SPEED_800MHZ 0
-#define OCOTP_CFG3_SPEED_850MHZ 1
-#define OCOTP_CFG3_SPEED_1GHZ 2
-#define OCOTP_CFG3_SPEED_1P2GHZ 3
-
-/*
- * For i.MX6UL
- */
-#define OCOTP_CFG3_SPEED_528MHZ 1
-#define OCOTP_CFG3_SPEED_696MHZ 2
-
-u32 get_cpu_speed_grade_hz(void)
-{
- struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
- struct fuse_bank *bank = &ocotp->bank[0];
- struct fuse_bank0_regs *fuse =
- (struct fuse_bank0_regs *)bank->fuse_regs;
- uint32_t val;
-
- val = readl(&fuse->cfg3);
- val >>= OCOTP_CFG3_SPEED_SHIFT;
- val &= 0x3;
-
- if (is_mx6ul() || is_mx6ull()) {
- if (val == OCOTP_CFG3_SPEED_528MHZ)
- return 528000000;
- else if (val == OCOTP_CFG3_SPEED_696MHZ)
- return 69600000;
- else
- return 0;
- }
-
- switch (val) {
- /* Valid for IMX6DQ */
- case OCOTP_CFG3_SPEED_1P2GHZ:
- if (is_mx6dq() || is_mx6dqp())
- return 1200000000;
- /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
- case OCOTP_CFG3_SPEED_1GHZ:
- return 996000000;
- /* Valid for IMX6DQ */
- case OCOTP_CFG3_SPEED_850MHZ:
- if (is_mx6dq() || is_mx6dqp())
- return 852000000;
- /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
- case OCOTP_CFG3_SPEED_800MHZ:
- return 792000000;
- }
- return 0;
-}
-
-/*
- * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480)
- * defines a 2-bit Temperature Grade
- *
- * return temperature grade and min/max temperature in Celsius
- */
-#define OCOTP_MEM0_TEMP_SHIFT 6
-
-u32 get_cpu_temp_grade(int *minc, int *maxc)
-{
- struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
- struct fuse_bank *bank = &ocotp->bank[1];
- struct fuse_bank1_regs *fuse =
- (struct fuse_bank1_regs *)bank->fuse_regs;
- uint32_t val;
-
- val = readl(&fuse->mem0);
- val >>= OCOTP_MEM0_TEMP_SHIFT;
- val &= 0x3;
-
- if (minc && maxc) {
- if (val == TEMP_AUTOMOTIVE) {
- *minc = -40;
- *maxc = 125;
- } else if (val == TEMP_INDUSTRIAL) {
- *minc = -40;
- *maxc = 105;
- } else if (val == TEMP_EXTCOMMERCIAL) {
- *minc = -20;
- *maxc = 105;
- } else {
- *minc = 0;
- *maxc = 95;
- }
- }
- return val;
-}
-
-#ifdef CONFIG_REVISION_TAG
-u32 __weak get_board_rev(void)
-{
- u32 cpurev = get_cpu_rev();
- u32 type = ((cpurev >> 12) & 0xff);
- if (type == MXC_CPU_MX6SOLO)
- cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
-
- if (type == MXC_CPU_MX6D)
- cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
-
- return cpurev;
-}
-#endif
-
-static void clear_ldo_ramp(void)
-{
- struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
- int reg;
-
- /* ROM may modify LDO ramp up time according to fuse setting, so in
- * order to be in the safe side we neeed to reset these settings to
- * match the reset value: 0'b00
- */
- reg = readl(&anatop->ana_misc2);
- reg &= ~(0x3f << 24);
- writel(reg, &anatop->ana_misc2);
-}
-
-/*
- * Set the PMU_REG_CORE register
- *
- * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
- * Possible values are from 0.725V to 1.450V in steps of
- * 0.025V (25mV).
- */
-static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
-{
- struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
- u32 val, step, old, reg = readl(&anatop->reg_core);
- u8 shift;
-
- if (mv < 725)
- val = 0x00; /* Power gated off */
- else if (mv > 1450)
- val = 0x1F; /* Power FET switched full on. No regulation */
- else
- val = (mv - 700) / 25;
-
- clear_ldo_ramp();
-
- switch (ldo) {
- case LDO_SOC:
- shift = 18;
- break;
- case LDO_PU:
- shift = 9;
- break;
- case LDO_ARM:
- shift = 0;
- break;
- default:
- return -EINVAL;
- }
-
- old = (reg & (0x1F << shift)) >> shift;
- step = abs(val - old);
- if (step == 0)
- return 0;
-
- reg = (reg & ~(0x1F << shift)) | (val << shift);
- writel(reg, &anatop->reg_core);
-
- /*
- * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
- * step
- */
- udelay(3 * step);
-
- return 0;
-}
-
-static void set_ahb_rate(u32 val)
-{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- u32 reg, div;
-
- div = get_periph_clk() / val - 1;
- reg = readl(&mxc_ccm->cbcdr);
-
- writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
- (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
-}
-
-static void clear_mmdc_ch_mask(void)
-{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- u32 reg;
- reg = readl(&mxc_ccm->ccdr);
-
- /* Clear MMDC channel mask */
- if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl())
- reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
- else
- reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
- writel(reg, &mxc_ccm->ccdr);
-}
-
-#define OCOTP_MEM0_REFTOP_TRIM_SHIFT 8
-
-static void init_bandgap(void)
-{
- struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
- struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
- struct fuse_bank *bank = &ocotp->bank[1];
- struct fuse_bank1_regs *fuse =
- (struct fuse_bank1_regs *)bank->fuse_regs;
- uint32_t val;
-
- /*
- * Ensure the bandgap has stabilized.
- */
- while (!(readl(&anatop->ana_misc0) & 0x80))
- ;
- /*
- * For best noise performance of the analog blocks using the
- * outputs of the bandgap, the reftop_selfbiasoff bit should
- * be set.
- */
- writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
- /*
- * On i.MX6ULL,we need to set VBGADJ bits according to the
- * REFTOP_TRIM[3:0] in fuse table
- * 000 - set REFTOP_VBGADJ[2:0] to 3b'110,
- * 110 - set REFTOP_VBGADJ[2:0] to 3b'000,
- * 001 - set REFTOP_VBGADJ[2:0] to 3b'001,
- * 010 - set REFTOP_VBGADJ[2:0] to 3b'010,
- * 011 - set REFTOP_VBGADJ[2:0] to 3b'011,
- * 100 - set REFTOP_VBGADJ[2:0] to 3b'100,
- * 101 - set REFTOP_VBGADJ[2:0] to 3b'101,
- * 111 - set REFTOP_VBGADJ[2:0] to 3b'111,
- */
- if (is_mx6ull()) {
- val = readl(&fuse->mem0);
- val >>= OCOTP_MEM0_REFTOP_TRIM_SHIFT;
- val &= 0x7;
-
- writel(val << BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT,
- &anatop->ana_misc0_set);
- }
-}
-
-#ifdef CONFIG_MX6SL
-static void set_preclk_from_osc(void)
-{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- u32 reg;
-
- reg = readl(&mxc_ccm->cscmr1);
- reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
- writel(reg, &mxc_ccm->cscmr1);
-}
-#endif
-
-int arch_cpu_init(void)
-{
- init_aips();
-
- /* Need to clear MMDC_CHx_MASK to make warm reset work. */
- clear_mmdc_ch_mask();
-
- /*
- * Disable self-bias circuit in the analog bandap.
- * The self-bias circuit is used by the bandgap during startup.
- * This bit should be set after the bandgap has initialized.
- */
- init_bandgap();
-
- if (!is_mx6ul() && !is_mx6ull()) {
- /*
- * When low freq boot is enabled, ROM will not set AHB
- * freq, so we need to ensure AHB freq is 132MHz in such
- * scenario.
- *
- * To i.MX6UL, when power up, default ARM core and
- * AHB rate is 396M and 132M.
- */
- if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
- set_ahb_rate(132000000);
- }
-
- if (is_mx6ul()) {
- if (is_soc_rev(CHIP_REV_1_0) == 0) {
- /*
- * According to the design team's requirement on
- * i.MX6UL,the PMIC_STBY_REQ PAD should be configured
- * as open drain 100K (0x0000b8a0).
- * Only exists on TO1.0
- */
- writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c);
- } else {
- /*
- * From TO1.1, SNVS adds internal pull up control
- * for POR_B, the register filed is GPBIT[1:0],
- * after system boot up, it can be set to 2b'01
- * to disable internal pull up.It can save about
- * 30uA power in SNVS mode.
- */
- writel((readl(MX6UL_SNVS_LP_BASE_ADDR + 0x10) &
- (~0x1400)) | 0x400,
- MX6UL_SNVS_LP_BASE_ADDR + 0x10);
- }
- }
-
- if (is_mx6ull()) {
- /*
- * GPBIT[1:0] is suggested to set to 2'b11:
- * 2'b00 : always PUP100K
- * 2'b01 : PUP100K when PMIC_ON_REQ or SOC_NOT_FAIL
- * 2'b10 : always disable PUP100K
- * 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL
- * register offset is different from i.MX6UL, since
- * i.MX6UL is fixed by ECO.
- */
- writel(readl(MX6UL_SNVS_LP_BASE_ADDR) |
- 0x3, MX6UL_SNVS_LP_BASE_ADDR);
- }
-
- /* Set perclk to source from OSC 24MHz */
-#if defined(CONFIG_MX6SL)
- set_preclk_from_osc();
-#endif
-
- imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
-
-#ifdef CONFIG_APBH_DMA
- /* Start APBH DMA */
- mxs_dma_init();
-#endif
-
- init_src();
-
- return 0;
-}
-
-#ifdef CONFIG_ENV_IS_IN_MMC
-__weak int board_mmc_get_env_dev(int devno)
-{
- return CONFIG_SYS_MMC_ENV_DEV;
-}
-
-static int mmc_get_boot_dev(void)
-{
- struct src *src_regs = (struct src *)SRC_BASE_ADDR;
- u32 soc_sbmr = readl(&src_regs->sbmr1);
- u32 bootsel;
- int devno;
-
- /*
- * Refer to
- * "i.MX 6Dual/6Quad Applications Processor Reference Manual"
- * Chapter "8.5.3.1 Expansion Device eFUSE Configuration"
- * i.MX6SL/SX/UL has same layout.
- */
- bootsel = (soc_sbmr & 0x000000FF) >> 6;
-
- /* No boot from sd/mmc */
- if (bootsel != 1)
- return -1;
-
- /* BOOT_CFG2[3] and BOOT_CFG2[4] */
- devno = (soc_sbmr & 0x00001800) >> 11;
-
- return devno;
-}
-
-int mmc_get_env_dev(void)
-{
- int devno = mmc_get_boot_dev();
-
- /* If not boot from sd/mmc, use default value */
- if (devno < 0)
- return CONFIG_SYS_MMC_ENV_DEV;
-
- return board_mmc_get_env_dev(devno);
-}
-
-#ifdef CONFIG_SYS_MMC_ENV_PART
-__weak int board_mmc_get_env_part(int devno)
-{
- return CONFIG_SYS_MMC_ENV_PART;
-}
-
-uint mmc_get_env_part(struct mmc *mmc)
-{
- int devno = mmc_get_boot_dev();
-
- /* If not boot from sd/mmc, use default value */
- if (devno < 0)
- return CONFIG_SYS_MMC_ENV_PART;
-
- return board_mmc_get_env_part(devno);
-}
-#endif
-#endif
-
-int board_postclk_init(void)
-{
- set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
-
- return 0;
-}
-
-#if defined(CONFIG_FEC_MXC)
-void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
-{
- struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
- struct fuse_bank *bank = &ocotp->bank[4];
- struct fuse_bank4_regs *fuse =
- (struct fuse_bank4_regs *)bank->fuse_regs;
-
- if ((is_mx6sx() || is_mx6ul() || is_mx6ull()) && dev_id == 1) {
- u32 value = readl(&fuse->mac_addr2);
- mac[0] = value >> 24 ;
- mac[1] = value >> 16 ;
- mac[2] = value >> 8 ;
- mac[3] = value ;
-
- value = readl(&fuse->mac_addr1);
- mac[4] = value >> 24 ;
- mac[5] = value >> 16 ;
-
- } else {
- u32 value = readl(&fuse->mac_addr1);
- mac[0] = (value >> 8);
- mac[1] = value ;
-
- value = readl(&fuse->mac_addr0);
- mac[2] = value >> 24 ;
- mac[3] = value >> 16 ;
- mac[4] = value >> 8 ;
- mac[5] = value ;
- }
-
-}
-#endif
-
-/*
- * cfg_val will be used for
- * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
- * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
- * instead of SBMR1 to determine the boot device.
- */
-const struct boot_mode soc_boot_modes[] = {
- {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
- /* reserved value should start rom usb */
- {"usb", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
- {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
- {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
- {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
- {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
- {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
- /* 4 bit bus width */
- {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
- {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
- {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
- {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
- {NULL, 0},
-};
-
-void reset_misc(void)
-{
-#ifdef CONFIG_VIDEO_MXS
- lcdif_power_down();
-#endif
-}
-
-void s_init(void)
-{
- struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
- struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- u32 mask480;
- u32 mask528;
- u32 reg, periph1, periph2;
-
- if (is_mx6sx() || is_mx6ul() || is_mx6ull())
- return;
-
- /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
- * to make sure PFD is working right, otherwise, PFDs may
- * not output clock after reset, MX6DL and MX6SL have added 396M pfd
- * workaround in ROM code, as bus clock need it
- */
-
- mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
- ANATOP_PFD_CLKGATE_MASK(1) |
- ANATOP_PFD_CLKGATE_MASK(2) |
- ANATOP_PFD_CLKGATE_MASK(3);
- mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
- ANATOP_PFD_CLKGATE_MASK(3);
-
- reg = readl(&ccm->cbcmr);
- periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
- >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
- periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
- >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
-
- /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
- if ((periph2 != 0x2) && (periph1 != 0x2))
- mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
-
- if ((periph2 != 0x1) && (periph1 != 0x1) &&
- (periph2 != 0x3) && (periph1 != 0x3))
- mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
-
- writel(mask480, &anatop->pfd_480_set);
- writel(mask528, &anatop->pfd_528_set);
- writel(mask480, &anatop->pfd_480_clr);
- writel(mask528, &anatop->pfd_528_clr);
-}
-
-#ifdef CONFIG_IMX_HDMI
-void imx_enable_hdmi_phy(void)
-{
- struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
- u8 reg;
- reg = readb(&hdmi->phy_conf0);
- reg |= HDMI_PHY_CONF0_PDZ_MASK;
- writeb(reg, &hdmi->phy_conf0);
- udelay(3000);
- reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
- writeb(reg, &hdmi->phy_conf0);
- udelay(3000);
- reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
- writeb(reg, &hdmi->phy_conf0);
- writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
-}
-
-void imx_setup_hdmi(void)
-{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
- int reg, count;
- u8 val;
-
- /* Turn on HDMI PHY clock */
- reg = readl(&mxc_ccm->CCGR2);
- reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
- MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
- writel(reg, &mxc_ccm->CCGR2);
- writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
- reg = readl(&mxc_ccm->chsccdr);
- reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
- MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
- MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
- reg |= (CHSCCDR_PODF_DIVIDE_BY_3
- << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
- |(CHSCCDR_IPU_PRE_CLK_540M_PFD
- << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
- writel(reg, &mxc_ccm->chsccdr);
-
- /* Clear the overflow condition */
- if (readb(&hdmi->ih_fc_stat2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) {
- /* TMDS software reset */
- writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &hdmi->mc_swrstz);
- val = readb(&hdmi->fc_invidconf);
- /* Need minimum 3 times to write to clear the register */
- for (count = 0 ; count < 5 ; count++)
- writeb(val, &hdmi->fc_invidconf);
- }
-}
-#endif
-
-#ifdef CONFIG_IMX_BOOTAUX
-int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
-{
- struct src *src_reg;
- u32 stack, pc;
-
- if (!boot_private_data)
- return -EINVAL;
-
- stack = *(u32 *)boot_private_data;
- pc = *(u32 *)(boot_private_data + 4);
-
- /* Set the stack and pc to M4 bootROM */
- writel(stack, M4_BOOTROM_BASE_ADDR);
- writel(pc, M4_BOOTROM_BASE_ADDR + 4);
-
- /* Enable M4 */
- src_reg = (struct src *)SRC_BASE_ADDR;
- clrsetbits_le32(&src_reg->scr, SRC_SCR_M4C_NON_SCLR_RST_MASK,
- SRC_SCR_M4_ENABLE_MASK);
-
- return 0;
-}
-
-int arch_auxiliary_core_check_up(u32 core_id)
-{
- struct src *src_reg = (struct src *)SRC_BASE_ADDR;
- unsigned val;
-
- val = readl(&src_reg->scr);
-
- if (val & SRC_SCR_M4C_NON_SCLR_RST_MASK)
- return 0; /* assert in reset */
-
- return 1;
-}
-#endif
+++ /dev/null
-if ARCH_MX7
-
-config MX7
- bool
- select ROM_UNIFIED_SECTIONS
- select CPU_V7_HAS_VIRT
- select CPU_V7_HAS_NONSEC
- select ARCH_SUPPORT_PSCI
- imply CMD_FUSE
- default y
-
-config MX7D
- select ROM_UNIFIED_SECTIONS
- imply CMD_FUSE
- bool
-
-choice
- prompt "MX7 board select"
- optional
-
-config TARGET_MX7DSABRESD
- bool "mx7dsabresd"
- select BOARD_LATE_INIT
- select MX7D
- select DM
- select DM_THERMAL
-
-config TARGET_PICO_IMX7D
- bool "pico-imx7d"
- select BOARD_LATE_INIT
- select MX7D
- select DM
- select DM_THERMAL
-
-config TARGET_WARP7
- bool "warp7"
- select BOARD_LATE_INIT
- select MX7D
- select DM
- select DM_THERMAL
-
-config TARGET_COLIBRI_IMX7
- bool "Support Colibri iMX7S/iMX7D modules"
- select BOARD_LATE_INIT
- select DM
- select DM_SERIAL
- select DM_THERMAL
-
-endchoice
-
-config SYS_SOC
- default "mx7"
-
-source "board/freescale/mx7dsabresd/Kconfig"
-source "board/technexion/pico-imx7d/Kconfig"
-source "board/toradex/colibri_imx7/Kconfig"
-source "board/warp7/Kconfig"
-
-endif
+++ /dev/null
-#
-# (C) Copyright 2015 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-#
-
-obj-y := soc.o clock.o clock_slice.o
-
-ifdef CONFIG_ARMV7_PSCI
-obj-y += psci-mx7.o psci.o
-endif
+++ /dev/null
-/*
- * Copyright (C) 2015 Freescale Semiconductor, Inc.
- *
- * Author:
- * Peng Fan <Peng.Fan@freescale.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <div64.h>
-#include <asm/io.h>
-#include <linux/errno.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-
-struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
- ANATOP_BASE_ADDR;
-struct mxc_ccm_reg *ccm_reg = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
-#ifdef CONFIG_FSL_ESDHC
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
-int get_clocks(void)
-{
-#ifdef CONFIG_FSL_ESDHC
-#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
- gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
- gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-#else
- gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-#endif
-#endif
- return 0;
-}
-
-u32 get_ahb_clk(void)
-{
- return get_root_clk(AHB_CLK_ROOT);
-}
-
-static u32 get_ipg_clk(void)
-{
- /*
- * The AHB and IPG are fixed at 2:1 ratio, and synchronized to
- * each other.
- */
- return get_ahb_clk() / 2;
-}
-
-u32 imx_get_uartclk(void)
-{
- return get_root_clk(UART1_CLK_ROOT);
-}
-
-u32 imx_get_fecclk(void)
-{
- return get_root_clk(ENET_AXI_CLK_ROOT);
-}
-
-#ifdef CONFIG_MXC_OCOTP
-void enable_ocotp_clk(unsigned char enable)
-{
- clock_enable(CCGR_OCOTP, enable);
-}
-
-void enable_thermal_clk(void)
-{
- enable_ocotp_clk(1);
-}
-#endif
-
-void enable_usboh3_clk(unsigned char enable)
-{
- u32 target;
-
- if (enable) {
- /* disable the clock gate first */
- clock_enable(CCGR_USB_HSIC, 0);
-
- /* 120Mhz */
- target = CLK_ROOT_ON |
- USB_HSIC_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK |
- CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
- clock_set_target_val(USB_HSIC_CLK_ROOT, target);
-
- /* enable the clock gate */
- clock_enable(CCGR_USB_CTRL, 1);
- clock_enable(CCGR_USB_HSIC, 1);
- clock_enable(CCGR_USB_PHY1, 1);
- clock_enable(CCGR_USB_PHY2, 1);
- } else {
- clock_enable(CCGR_USB_CTRL, 0);
- clock_enable(CCGR_USB_HSIC, 0);
- clock_enable(CCGR_USB_PHY1, 0);
- clock_enable(CCGR_USB_PHY2, 0);
- }
-}
-
-static u32 decode_pll(enum pll_clocks pll, u32 infreq)
-{
- u32 reg, div_sel;
- u32 num, denom;
-
- /*
- * Alought there are four choices for the bypass src,
- * we choose OSC_24M which is the default set in ROM.
- */
- switch (pll) {
- case PLL_CORE:
- reg = readl(&ccm_anatop->pll_arm);
-
- if (reg & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK)
- return 0;
-
- if (reg & CCM_ANALOG_PLL_ARM_BYPASS_MASK)
- return MXC_HCLK;
-
- div_sel = (reg & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >>
- CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT;
-
- return (infreq * div_sel) / 2;
-
- case PLL_SYS:
- reg = readl(&ccm_anatop->pll_480);
-
- if (reg & CCM_ANALOG_PLL_480_POWERDOWN_MASK)
- return 0;
-
- if (reg & CCM_ANALOG_PLL_480_BYPASS_MASK)
- return MXC_HCLK;
-
- if (((reg & CCM_ANALOG_PLL_480_DIV_SELECT_MASK) >>
- CCM_ANALOG_PLL_480_DIV_SELECT_SHIFT) == 0)
- return 480000000u;
- else
- return 528000000u;
-
- case PLL_ENET:
- reg = readl(&ccm_anatop->pll_enet);
-
- if (reg & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK)
- return 0;
-
- if (reg & CCM_ANALOG_PLL_ENET_BYPASS_MASK)
- return MXC_HCLK;
-
- return 1000000000u;
-
- case PLL_DDR:
- reg = readl(&ccm_anatop->pll_ddr);
-
- if (reg & CCM_ANALOG_PLL_DDR_POWERDOWN_MASK)
- return 0;
-
- num = ccm_anatop->pll_ddr_num;
- denom = ccm_anatop->pll_ddr_denom;
-
- if (reg & CCM_ANALOG_PLL_DDR_BYPASS_MASK)
- return MXC_HCLK;
-
- div_sel = (reg & CCM_ANALOG_PLL_DDR_DIV_SELECT_MASK) >>
- CCM_ANALOG_PLL_DDR_DIV_SELECT_SHIFT;
-
- return infreq * (div_sel + num / denom);
-
- case PLL_USB:
- return 480000000u;
-
- default:
- printf("Unsupported pll clocks %d\n", pll);
- break;
- }
-
- return 0;
-}
-
-static u32 mxc_get_pll_sys_derive(int derive)
-{
- u32 freq, div, frac;
- u32 reg;
-
- div = 1;
- reg = readl(&ccm_anatop->pll_480);
- freq = decode_pll(PLL_SYS, MXC_HCLK);
-
- switch (derive) {
- case PLL_SYS_MAIN_480M_CLK:
- if (reg & CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_MASK)
- return 0;
- else
- return freq;
- case PLL_SYS_MAIN_240M_CLK:
- if (reg & CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_MASK)
- return 0;
- else
- return freq / 2;
- case PLL_SYS_MAIN_120M_CLK:
- if (reg & CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_MASK)
- return 0;
- else
- return freq / 4;
- case PLL_SYS_PFD0_392M_CLK:
- reg = readl(&ccm_anatop->pfd_480a);
- if (reg & CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_MASK)
- return 0;
- frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >>
- CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT;
- break;
- case PLL_SYS_PFD0_196M_CLK:
- if (reg & CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_MASK)
- return 0;
- reg = readl(&ccm_anatop->pfd_480a);
- frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >>
- CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT;
- div = 2;
- break;
- case PLL_SYS_PFD1_332M_CLK:
- reg = readl(&ccm_anatop->pfd_480a);
- if (reg & CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_MASK)
- return 0;
- frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >>
- CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT;
- break;
- case PLL_SYS_PFD1_166M_CLK:
- if (reg & CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_MASK)
- return 0;
- reg = readl(&ccm_anatop->pfd_480a);
- frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >>
- CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT;
- div = 2;
- break;
- case PLL_SYS_PFD2_270M_CLK:
- reg = readl(&ccm_anatop->pfd_480a);
- if (reg & CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_MASK)
- return 0;
- frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >>
- CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT;
- break;
- case PLL_SYS_PFD2_135M_CLK:
- if (reg & CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_MASK)
- return 0;
- reg = readl(&ccm_anatop->pfd_480a);
- frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >>
- CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT;
- div = 2;
- break;
- case PLL_SYS_PFD3_CLK:
- reg = readl(&ccm_anatop->pfd_480a);
- if (reg & CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_MASK)
- return 0;
- frac = (reg & CCM_ANALOG_PFD_480A_PFD3_FRAC_MASK) >>
- CCM_ANALOG_PFD_480A_PFD3_FRAC_SHIFT;
- break;
- case PLL_SYS_PFD4_CLK:
- reg = readl(&ccm_anatop->pfd_480b);
- if (reg & CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK)
- return 0;
- frac = (reg & CCM_ANALOG_PFD_480B_PFD4_FRAC_MASK) >>
- CCM_ANALOG_PFD_480B_PFD4_FRAC_SHIFT;
- break;
- case PLL_SYS_PFD5_CLK:
- reg = readl(&ccm_anatop->pfd_480b);
- if (reg & CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_MASK)
- return 0;
- frac = (reg & CCM_ANALOG_PFD_480B_PFD5_FRAC_MASK) >>
- CCM_ANALOG_PFD_480B_PFD5_FRAC_SHIFT;
- break;
- case PLL_SYS_PFD6_CLK:
- reg = readl(&ccm_anatop->pfd_480b);
- if (reg & CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_MASK)
- return 0;
- frac = (reg & CCM_ANALOG_PFD_480B_PFD6_FRAC_MASK) >>
- CCM_ANALOG_PFD_480B_PFD6_FRAC_SHIFT;
- break;
- case PLL_SYS_PFD7_CLK:
- reg = readl(&ccm_anatop->pfd_480b);
- if (reg & CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_MASK)
- return 0;
- frac = (reg & CCM_ANALOG_PFD_480B_PFD7_FRAC_MASK) >>
- CCM_ANALOG_PFD_480B_PFD7_FRAC_SHIFT;
- break;
- default:
- printf("Error derived pll_sys clock %d\n", derive);
- return 0;
- }
-
- return ((freq / frac) * 18) / div;
-}
-
-static u32 mxc_get_pll_enet_derive(int derive)
-{
- u32 freq, reg;
-
- freq = decode_pll(PLL_ENET, MXC_HCLK);
- reg = readl(&ccm_anatop->pll_enet);
-
- switch (derive) {
- case PLL_ENET_MAIN_500M_CLK:
- if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK)
- return freq / 2;
- break;
- case PLL_ENET_MAIN_250M_CLK:
- if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK)
- return freq / 4;
- break;
- case PLL_ENET_MAIN_125M_CLK:
- if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK)
- return freq / 8;
- break;
- case PLL_ENET_MAIN_100M_CLK:
- if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK)
- return freq / 10;
- break;
- case PLL_ENET_MAIN_50M_CLK:
- if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK)
- return freq / 20;
- break;
- case PLL_ENET_MAIN_40M_CLK:
- if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK)
- return freq / 25;
- break;
- case PLL_ENET_MAIN_25M_CLK:
- if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK)
- return freq / 40;
- break;
- default:
- printf("Error derived pll_enet clock %d\n", derive);
- break;
- }
-
- return 0;
-}
-
-static u32 mxc_get_pll_ddr_derive(int derive)
-{
- u32 freq, reg;
-
- freq = decode_pll(PLL_DDR, MXC_HCLK);
- reg = readl(&ccm_anatop->pll_ddr);
-
- switch (derive) {
- case PLL_DRAM_MAIN_1066M_CLK:
- return freq;
- case PLL_DRAM_MAIN_533M_CLK:
- if (reg & CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_MASK)
- return freq / 2;
- break;
- default:
- printf("Error derived pll_ddr clock %d\n", derive);
- break;
- }
-
- return 0;
-}
-
-static u32 mxc_get_pll_derive(enum pll_clocks pll, int derive)
-{
- switch (pll) {
- case PLL_SYS:
- return mxc_get_pll_sys_derive(derive);
- case PLL_ENET:
- return mxc_get_pll_enet_derive(derive);
- case PLL_DDR:
- return mxc_get_pll_ddr_derive(derive);
- default:
- printf("Error pll.\n");
- return 0;
- }
-}
-
-static u32 get_root_src_clk(enum clk_root_src root_src)
-{
- switch (root_src) {
- case OSC_24M_CLK:
- return 24000000u;
- case PLL_ARM_MAIN_800M_CLK:
- return decode_pll(PLL_CORE, MXC_HCLK);
-
- case PLL_SYS_MAIN_480M_CLK:
- case PLL_SYS_MAIN_240M_CLK:
- case PLL_SYS_MAIN_120M_CLK:
- case PLL_SYS_PFD0_392M_CLK:
- case PLL_SYS_PFD0_196M_CLK:
- case PLL_SYS_PFD1_332M_CLK:
- case PLL_SYS_PFD1_166M_CLK:
- case PLL_SYS_PFD2_270M_CLK:
- case PLL_SYS_PFD2_135M_CLK:
- case PLL_SYS_PFD3_CLK:
- case PLL_SYS_PFD4_CLK:
- case PLL_SYS_PFD5_CLK:
- case PLL_SYS_PFD6_CLK:
- case PLL_SYS_PFD7_CLK:
- return mxc_get_pll_derive(PLL_SYS, root_src);
-
- case PLL_ENET_MAIN_500M_CLK:
- case PLL_ENET_MAIN_250M_CLK:
- case PLL_ENET_MAIN_125M_CLK:
- case PLL_ENET_MAIN_100M_CLK:
- case PLL_ENET_MAIN_50M_CLK:
- case PLL_ENET_MAIN_40M_CLK:
- case PLL_ENET_MAIN_25M_CLK:
- return mxc_get_pll_derive(PLL_ENET, root_src);
-
- case PLL_DRAM_MAIN_1066M_CLK:
- case PLL_DRAM_MAIN_533M_CLK:
- return mxc_get_pll_derive(PLL_DDR, root_src);
-
- case PLL_AUDIO_MAIN_CLK:
- return decode_pll(PLL_AUDIO, MXC_HCLK);
- case PLL_VIDEO_MAIN_CLK:
- return decode_pll(PLL_VIDEO, MXC_HCLK);
-
- case PLL_USB_MAIN_480M_CLK:
- return decode_pll(PLL_USB, MXC_HCLK);
-
- case REF_1M_CLK:
- return 1000000;
- case OSC_32K_CLK:
- return MXC_CLK32;
-
- case EXT_CLK_1:
- case EXT_CLK_2:
- case EXT_CLK_3:
- case EXT_CLK_4:
- printf("No EXT CLK supported??\n");
- break;
- };
-
- return 0;
-}
-
-u32 get_root_clk(enum clk_root_index clock_id)
-{
- enum clk_root_src root_src;
- u32 post_podf, pre_podf, auto_podf, root_src_clk;
- int auto_en;
-
- if (clock_root_enabled(clock_id) <= 0)
- return 0;
-
- if (clock_get_prediv(clock_id, &pre_podf) < 0)
- return 0;
-
- if (clock_get_postdiv(clock_id, &post_podf) < 0)
- return 0;
-
- if (clock_get_autopostdiv(clock_id, &auto_podf, &auto_en) < 0)
- return 0;
-
- if (auto_en == 0)
- auto_podf = 0;
-
- if (clock_get_src(clock_id, &root_src) < 0)
- return 0;
-
- root_src_clk = get_root_src_clk(root_src);
-
- /*
- * bypass clk is ignored.
- */
-
- return root_src_clk / (post_podf + 1) / (pre_podf + 1) /
- (auto_podf + 1);
-}
-
-static u32 get_ddrc_clk(void)
-{
- u32 reg, freq;
- enum root_post_div post_div;
-
- reg = readl(&ccm_reg->root[DRAM_CLK_ROOT].target_root);
- if (reg & CLK_ROOT_MUX_MASK)
- /* DRAM_ALT_CLK_ROOT */
- freq = get_root_clk(DRAM_ALT_CLK_ROOT);
- else
- /* PLL_DRAM_MAIN_1066M_CLK */
- freq = mxc_get_pll_derive(PLL_DDR, PLL_DRAM_MAIN_1066M_CLK);
-
- post_div = reg & DRAM_CLK_ROOT_POST_DIV_MASK;
-
- return freq / (post_div + 1) / 2;
-}
-
-unsigned int mxc_get_clock(enum mxc_clock clk)
-{
- switch (clk) {
- case MXC_ARM_CLK:
- return get_root_clk(ARM_A7_CLK_ROOT);
- case MXC_AXI_CLK:
- return get_root_clk(MAIN_AXI_CLK_ROOT);
- case MXC_AHB_CLK:
- return get_root_clk(AHB_CLK_ROOT);
- case MXC_IPG_CLK:
- return get_ipg_clk();
- case MXC_I2C_CLK:
- return get_root_clk(I2C1_CLK_ROOT);
- case MXC_UART_CLK:
- return get_root_clk(UART1_CLK_ROOT);
- case MXC_CSPI_CLK:
- return get_root_clk(ECSPI1_CLK_ROOT);
- case MXC_DDR_CLK:
- return get_ddrc_clk();
- case MXC_ESDHC_CLK:
- return get_root_clk(USDHC1_CLK_ROOT);
- case MXC_ESDHC2_CLK:
- return get_root_clk(USDHC2_CLK_ROOT);
- case MXC_ESDHC3_CLK:
- return get_root_clk(USDHC3_CLK_ROOT);
- default:
- printf("Unsupported mxc_clock %d\n", clk);
- break;
- }
-
- return 0;
-}
-
-#ifdef CONFIG_SYS_I2C_MXC
-/* i2c_num can be 0 - 3 */
-int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
-{
- u32 target;
-
- if (i2c_num >= 4)
- return -EINVAL;
-
- if (enable) {
- clock_enable(CCGR_I2C1 + i2c_num, 0);
-
- /* Set i2c root clock to PLL_SYS_MAIN_120M_CLK */
-
- target = CLK_ROOT_ON |
- I2C1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK |
- CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
- clock_set_target_val(I2C1_CLK_ROOT + i2c_num, target);
-
- clock_enable(CCGR_I2C1 + i2c_num, 1);
- } else {
- clock_enable(CCGR_I2C1 + i2c_num, 0);
- }
-
- return 0;
-}
-#endif
-
-static void init_clk_esdhc(void)
-{
- u32 target;
-
- /* disable the clock gate first */
- clock_enable(CCGR_USDHC1, 0);
- clock_enable(CCGR_USDHC2, 0);
- clock_enable(CCGR_USDHC3, 0);
-
- /* 196: 392/2 */
- target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
- CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
- clock_set_target_val(USDHC1_CLK_ROOT, target);
-
- target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
- CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
- clock_set_target_val(USDHC2_CLK_ROOT, target);
-
- target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
- CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
- clock_set_target_val(USDHC3_CLK_ROOT, target);
-
- /* enable the clock gate */
- clock_enable(CCGR_USDHC1, 1);
- clock_enable(CCGR_USDHC2, 1);
- clock_enable(CCGR_USDHC3, 1);
-}
-
-static void init_clk_uart(void)
-{
- u32 target;
-
- /* disable the clock gate first */
- clock_enable(CCGR_UART1, 0);
- clock_enable(CCGR_UART2, 0);
- clock_enable(CCGR_UART3, 0);
- clock_enable(CCGR_UART4, 0);
- clock_enable(CCGR_UART5, 0);
- clock_enable(CCGR_UART6, 0);
- clock_enable(CCGR_UART7, 0);
-
- /* 24Mhz */
- target = CLK_ROOT_ON | UART1_CLK_ROOT_FROM_OSC_24M_CLK |
- CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
- clock_set_target_val(UART1_CLK_ROOT, target);
-
- target = CLK_ROOT_ON | UART2_CLK_ROOT_FROM_OSC_24M_CLK |
- CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
- clock_set_target_val(UART2_CLK_ROOT, target);
-
- target = CLK_ROOT_ON | UART3_CLK_ROOT_FROM_OSC_24M_CLK |
- CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
- clock_set_target_val(UART3_CLK_ROOT, target);
-
- target = CLK_ROOT_ON | UART4_CLK_ROOT_FROM_OSC_24M_CLK |
- CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
- clock_set_target_val(UART4_CLK_ROOT, target);
-
- target = CLK_ROOT_ON | UART5_CLK_ROOT_FROM_OSC_24M_CLK |
- CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
- clock_set_target_val(UART5_CLK_ROOT, target);
-
- target = CLK_ROOT_ON | UART6_CLK_ROOT_FROM_OSC_24M_CLK |
- CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
- clock_set_target_val(UART6_CLK_ROOT, target);
-
- target = CLK_ROOT_ON | UART7_CLK_ROOT_FROM_OSC_24M_CLK |
- CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
- clock_set_target_val(UART7_CLK_ROOT, target);
-
- /* enable the clock gate */
- clock_enable(CCGR_UART1, 1);
- clock_enable(CCGR_UART2, 1);
- clock_enable(CCGR_UART3, 1);
- clock_enable(CCGR_UART4, 1);
- clock_enable(CCGR_UART5, 1);
- clock_enable(CCGR_UART6, 1);
- clock_enable(CCGR_UART7, 1);
-}
-
-static void init_clk_weim(void)
-{
- u32 target;
-
- /* disable the clock gate first */
- clock_enable(CCGR_WEIM, 0);
-
- /* 120Mhz */
- target = CLK_ROOT_ON | EIM_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK |
- CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
- clock_set_target_val(EIM_CLK_ROOT, target);
-
- /* enable the clock gate */
- clock_enable(CCGR_WEIM, 1);
-}
-
-static void init_clk_ecspi(void)
-{
- u32 target;
-
- /* disable the clock gate first */
- clock_enable(CCGR_ECSPI1, 0);
- clock_enable(CCGR_ECSPI2, 0);
- clock_enable(CCGR_ECSPI3, 0);
- clock_enable(CCGR_ECSPI4, 0);
-
- /* 60Mhz: 240/4 */
- target = CLK_ROOT_ON | ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
- CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
- clock_set_target_val(ECSPI1_CLK_ROOT, target);
-
- target = CLK_ROOT_ON | ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
- CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
- clock_set_target_val(ECSPI2_CLK_ROOT, target);
-
- target = CLK_ROOT_ON | ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
- CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
- clock_set_target_val(ECSPI3_CLK_ROOT, target);
-
- target = CLK_ROOT_ON | ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
- CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
- clock_set_target_val(ECSPI4_CLK_ROOT, target);
-
- /* enable the clock gate */
- clock_enable(CCGR_ECSPI1, 1);
- clock_enable(CCGR_ECSPI2, 1);
- clock_enable(CCGR_ECSPI3, 1);
- clock_enable(CCGR_ECSPI4, 1);
-}
-
-static void init_clk_wdog(void)
-{
- u32 target;
-
- /* disable the clock gate first */
- clock_enable(CCGR_WDOG1, 0);
- clock_enable(CCGR_WDOG2, 0);
- clock_enable(CCGR_WDOG3, 0);
- clock_enable(CCGR_WDOG4, 0);
-
- /* 24Mhz */
- target = CLK_ROOT_ON | WDOG_CLK_ROOT_FROM_OSC_24M_CLK |
- CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
- clock_set_target_val(WDOG_CLK_ROOT, target);
-
- /* enable the clock gate */
- clock_enable(CCGR_WDOG1, 1);
- clock_enable(CCGR_WDOG2, 1);
- clock_enable(CCGR_WDOG3, 1);
- clock_enable(CCGR_WDOG4, 1);
-}
-
-#ifdef CONFIG_MXC_EPDC
-static void init_clk_epdc(void)
-{
- u32 target;
-
- /* disable the clock gate first */
- clock_enable(CCGR_EPDC, 0);
-
- /* 24Mhz */
- target = CLK_ROOT_ON | EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK |
- CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV12);
- clock_set_target_val(EPDC_PIXEL_CLK_ROOT, target);
-
- /* enable the clock gate */
- clock_enable(CCGR_EPDC, 1);
-}
-#endif
-
-static int enable_pll_enet(void)
-{
- u32 reg;
- s32 timeout = 100000;
-
- reg = readl(&ccm_anatop->pll_enet);
- /* If pll_enet powered up, no need to set it again */
- if (reg & ANADIG_PLL_ENET_PWDN_MASK) {
- reg &= ~ANADIG_PLL_ENET_PWDN_MASK;
- writel(reg, &ccm_anatop->pll_enet);
-
- while (timeout--) {
- if (readl(&ccm_anatop->pll_enet) & ANADIG_PLL_LOCK)
- break;
- }
-
- if (timeout <= 0) {
- /* If timeout, we set pwdn for pll_enet. */
- reg |= ANADIG_PLL_ENET_PWDN_MASK;
- return -ETIME;
- }
- }
-
- /* Clear bypass */
- writel(CCM_ANALOG_PLL_ENET_BYPASS_MASK, &ccm_anatop->pll_enet_clr);
-
- writel((CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK
- | CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK
- | CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK
- | CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK
- | CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK
- | CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK
- | CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK),
- &ccm_anatop->pll_enet_set);
-
- return 0;
-}
-static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom,
- u32 post_div)
-{
- u32 reg = 0;
- ulong start;
-
- debug("pll5 div = %d, num = %d, denom = %d\n",
- pll_div, pll_num, pll_denom);
-
- /* Power up PLL5 video and disable its output */
- writel(CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK |
- CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK |
- CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK |
- CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK |
- CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK |
- CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK,
- &ccm_anatop->pll_video_clr);
-
- /* Set div, num and denom */
- switch (post_div) {
- case 1:
- writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
- CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x1) |
- CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
- &ccm_anatop->pll_video_set);
- break;
- case 2:
- writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
- CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
- CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
- &ccm_anatop->pll_video_set);
- break;
- case 3:
- writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
- CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
- CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x1),
- &ccm_anatop->pll_video_set);
- break;
- case 4:
- writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
- CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
- CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x3),
- &ccm_anatop->pll_video_set);
- break;
- case 0:
- default:
- writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
- CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x2) |
- CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
- &ccm_anatop->pll_video_set);
- break;
- }
-
- writel(CCM_ANALOG_PLL_VIDEO_NUM_A(pll_num),
- &ccm_anatop->pll_video_num);
-
- writel(CCM_ANALOG_PLL_VIDEO_DENOM_B(pll_denom),
- &ccm_anatop->pll_video_denom);
-
- /* Wait PLL5 lock */
- start = get_timer(0); /* Get current timestamp */
-
- do {
- reg = readl(&ccm_anatop->pll_video);
- if (reg & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) {
- /* Enable PLL out */
- writel(CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK,
- &ccm_anatop->pll_video_set);
- return 0;
- }
- } while (get_timer(0) < (start + 10)); /* Wait 10ms */
-
- printf("Lock PLL5 timeout\n");
-
- return 1;
-}
-
-int set_clk_qspi(void)
-{
- u32 target;
-
- /* disable the clock gate first */
- clock_enable(CCGR_QSPI, 0);
-
- /* 49M: 392/2/4 */
- target = CLK_ROOT_ON | QSPI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK |
- CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
- clock_set_target_val(QSPI_CLK_ROOT, target);
-
- /* enable the clock gate */
- clock_enable(CCGR_QSPI, 1);
-
- return 0;
-}
-
-int set_clk_nand(void)
-{
- u32 target;
-
- /* disable the clock gate first */
- clock_enable(CCGR_RAWNAND, 0);
-
- enable_pll_enet();
- /* 100: 500/5 */
- target = CLK_ROOT_ON | NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK |
- CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV5);
- clock_set_target_val(NAND_CLK_ROOT, target);
-
- /* enable the clock gate */
- clock_enable(CCGR_RAWNAND, 1);
-
- return 0;
-}
-
-void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq)
-{
- u32 hck = MXC_HCLK/1000;
- u32 min = hck * 27;
- u32 max = hck * 54;
- u32 temp, best = 0;
- u32 i, j, pred = 1, postd = 1;
- u32 pll_div, pll_num, pll_denom, post_div = 0;
- u32 target;
-
- debug("mxs_set_lcdclk, freq = %d\n", freq);
-
- clock_enable(CCGR_LCDIF, 0);
-
- temp = (freq * 8 * 8);
- if (temp < min) {
- for (i = 1; i <= 4; i++) {
- if ((temp * (1 << i)) > min) {
- post_div = i;
- freq = (freq * (1 << i));
- break;
- }
- }
-
- if (5 == i) {
- printf("Fail to set rate to %dkhz", freq);
- return;
- }
- }
-
- for (i = 1; i <= 8; i++) {
- for (j = 1; j <= 8; j++) {
- temp = freq * i * j;
- if (temp > max || temp < min)
- continue;
-
- if (best == 0 || temp < best) {
- best = temp;
- pred = i;
- postd = j;
- }
- }
- }
-
- if (best == 0) {
- printf("Fail to set rate to %dkhz", freq);
- return;
- }
-
- debug("best %d, pred = %d, postd = %d\n", best, pred, postd);
-
- pll_div = best / hck;
- pll_denom = 1000000;
- pll_num = (best - hck * pll_div) * pll_denom / hck;
-
- if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
- return;
-
- target = CLK_ROOT_ON | LCDIF_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK |
- CLK_ROOT_PRE_DIV((pred - 1)) | CLK_ROOT_POST_DIV((postd - 1));
- clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, target);
-
- clock_enable(CCGR_LCDIF, 1);
-}
-
-#ifdef CONFIG_FEC_MXC
-int set_clk_enet(enum enet_freq type)
-{
- u32 target;
- int ret;
- u32 enet1_ref, enet2_ref;
-
- /* disable the clock first */
- clock_enable(CCGR_ENET1, 0);
- clock_enable(CCGR_ENET2, 0);
-
- switch (type) {
- case ENET_125MHz:
- enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
- enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
- break;
- case ENET_50MHz:
- enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
- enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
- break;
- case ENET_25MHz:
- enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
- enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
- break;
- default:
- return -EINVAL;
- }
-
- ret = enable_pll_enet();
- if (ret != 0)
- return ret;
-
- /* set enet axi clock 196M: 392/2 */
- target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK |
- CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
- clock_set_target_val(ENET_AXI_CLK_ROOT, target);
-
- target = CLK_ROOT_ON | enet1_ref |
- CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
- clock_set_target_val(ENET1_REF_CLK_ROOT, target);
-
- target = CLK_ROOT_ON | ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
- CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
- clock_set_target_val(ENET1_TIME_CLK_ROOT, target);
-
- target = CLK_ROOT_ON | enet2_ref |
- CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
- clock_set_target_val(ENET2_REF_CLK_ROOT, target);
-
- target = CLK_ROOT_ON | ENET2_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
- CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
- clock_set_target_val(ENET2_TIME_CLK_ROOT, target);
-
-#ifdef CONFIG_FEC_MXC_25M_REF_CLK
- target = CLK_ROOT_ON |
- ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK |
- CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
- clock_set_target_val(ENET_PHY_REF_CLK_ROOT, target);
-#endif
- /* enable clock */
- clock_enable(CCGR_ENET1, 1);
- clock_enable(CCGR_ENET2, 1);
-
- return 0;
-}
-#endif
-
-/* Configure PLL/PFD freq */
-void clock_init(void)
-{
-/* Rom has enabled PLL_ARM, PLL_DDR, PLL_SYS, PLL_ENET
- * In u-boot, we have to:
- * 1. Configure PFD3- PFD7 for freq we needed in u-boot
- * 2. Set clock root for peripherals (ip channel) used in u-boot but without set rate
- * interface. The clocks for these peripherals are enabled after this intialization.
- * 3. Other peripherals with set clock rate interface does not be set in this function.
- */
- u32 reg;
-
- /*
- * Configure PFD4 to 392M
- * 480M * 18 / 0x16 = 392M
- */
- reg = readl(&ccm_anatop->pfd_480b);
-
- reg &= ~(ANATOP_PFD480B_PFD4_FRAC_MASK |
- CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK);
- reg |= ANATOP_PFD480B_PFD4_FRAC_392M_VAL;
-
- writel(reg, &ccm_anatop->pfd_480b);
-
- init_clk_esdhc();
- init_clk_uart();
- init_clk_weim();
- init_clk_ecspi();
- init_clk_wdog();
-#ifdef CONFIG_MXC_EPDC
- init_clk_epdc();
-#endif
-
- enable_usboh3_clk(1);
-
- clock_enable(CCGR_SNVS, 1);
-
-#ifdef CONFIG_NAND_MXS
- clock_enable(CCGR_RAWNAND, 1);
-#endif
-
- if (IS_ENABLED(CONFIG_IMX_RDC)) {
- clock_enable(CCGR_RDC, 1);
- clock_enable(CCGR_SEMA1, 1);
- clock_enable(CCGR_SEMA2, 1);
- }
-}
-
-#ifdef CONFIG_SECURE_BOOT
-void hab_caam_clock_enable(unsigned char enable)
-{
- if (enable)
- clock_enable(CCGR_CAAM, 1);
- else
- clock_enable(CCGR_CAAM, 0);
-}
-#endif
-
-#ifdef CONFIG_MXC_EPDC
-void epdc_clock_enable(void)
-{
- clock_enable(CCGR_EPDC, 1);
-}
-void epdc_clock_disable(void)
-{
- clock_enable(CCGR_EPDC, 0);
-}
-#endif
-
-/*
- * Dump some core clockes.
- */
-int do_mx7_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- u32 freq;
- freq = decode_pll(PLL_CORE, MXC_HCLK);
- printf("PLL_CORE %8d MHz\n", freq / 1000000);
- freq = decode_pll(PLL_SYS, MXC_HCLK);
- printf("PLL_SYS %8d MHz\n", freq / 1000000);
- freq = decode_pll(PLL_ENET, MXC_HCLK);
- printf("PLL_NET %8d MHz\n", freq / 1000000);
-
- printf("\n");
-
- printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
- printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
-#ifdef CONFIG_MXC_SPI
- printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
-#endif
- printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
- printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
- printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
- printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
- printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
- printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
-
- return 0;
-}
-
-U_BOOT_CMD(
- clocks, CONFIG_SYS_MAXARGS, 1, do_mx7_showclocks,
- "display clocks",
- ""
-);
+++ /dev/null
-/*
- * Copyright (C) 2015 Freescale Semiconductor, Inc.
- *
- * Author:
- * Peng Fan <Peng.Fan@freescale.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <div64.h>
-#include <asm/io.h>
-#include <linux/errno.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-
-struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
-static struct clk_root_map root_array[] = {
- {ARM_A7_CLK_ROOT, CCM_CORE_CHANNEL,
- {OSC_24M_CLK, PLL_ARM_MAIN_800M_CLK, PLL_ENET_MAIN_500M_CLK,
- PLL_DRAM_MAIN_1066M_CLK, PLL_SYS_MAIN_480M_CLK,
- PLL_SYS_PFD0_392M_CLK, PLL_AUDIO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
- },
- {ARM_M4_CLK_ROOT, CCM_BUS_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_250M_CLK,
- PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK,
- PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
- },
- {ARM_M0_CLK_ROOT, CCM_BUS_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_125M_CLK,
- PLL_SYS_PFD2_135M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK,
- PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
- },
- {MAIN_AXI_CLK_ROOT, CCM_BUS_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_DRAM_MAIN_533M_CLK,
- PLL_ENET_MAIN_250M_CLK, PLL_SYS_PFD5_CLK, PLL_AUDIO_MAIN_CLK,
- PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD7_CLK}
- },
- {DISP_AXI_CLK_ROOT, CCM_BUS_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_DRAM_MAIN_533M_CLK,
- PLL_ENET_MAIN_250M_CLK, PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK,
- PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK}
- },
- {ENET_AXI_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK,
- PLL_ENET_MAIN_250M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_AUDIO_MAIN_CLK,
- PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK}
- },
- {NAND_USDHC_BUS_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK,
- PLL_SYS_MAIN_240M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_PFD6_CLK,
- PLL_ENET_MAIN_250M_CLK, PLL_AUDIO_MAIN_CLK}
- },
- {AHB_CLK_ROOT, CCM_AHB_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK,
- PLL_SYS_PFD0_392M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK,
- PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK}
- },
- {DRAM_PHYM_CLK_ROOT, CCM_DRAM_PHYM_CHANNEL,
- {PLL_DRAM_MAIN_1066M_CLK, DRAM_PHYM_ALT_CLK_ROOT}
- },
- {DRAM_CLK_ROOT, CCM_DRAM_CHANNEL,
- {PLL_DRAM_MAIN_1066M_CLK, DRAM_ALT_CLK_ROOT}
- },
- {DRAM_PHYM_ALT_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_SYS_MAIN_480M_CLK,
- PLL_ENET_MAIN_500M_CLK, PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD7_CLK,
- PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK}
- },
- {DRAM_ALT_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_SYS_MAIN_480M_CLK,
- PLL_ENET_MAIN_500M_CLK, PLL_ENET_MAIN_250M_CLK,
- PLL_SYS_PFD0_392M_CLK, PLL_AUDIO_MAIN_CLK, PLL_SYS_PFD2_270M_CLK}
- },
- {USB_HSIC_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_USB_MAIN_480M_CLK,
- PLL_SYS_PFD3_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD5_CLK,
- PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
- },
- {PCIE_CTRL_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_ENET_MAIN_250M_CLK, PLL_SYS_MAIN_240M_CLK,
- PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK,
- PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_SYS_PFD6_CLK}
- },
- {PCIE_PHY_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_ENET_MAIN_500M_CLK,
- EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
- EXT_CLK_4, PLL_SYS_PFD0_392M_CLK}
- },
- {EPDC_PIXEL_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_DRAM_MAIN_533M_CLK,
- PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD5_CLK, PLL_SYS_PFD6_CLK,
- PLL_SYS_PFD7_CLK, PLL_VIDEO_MAIN_CLK}
- },
- {LCDIF_PIXEL_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_PFD5_CLK, PLL_DRAM_MAIN_533M_CLK,
- EXT_CLK_3, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK,
- PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
- },
- {MIPI_DSI_EXTSER_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_PFD5_CLK, PLL_SYS_PFD3_CLK,
- PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD0_196M_CLK, PLL_DRAM_MAIN_533M_CLK,
- PLL_VIDEO_MAIN_CLK, PLL_AUDIO_MAIN_CLK}
- },
- {MIPI_CSI_WARP_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD3_CLK,
- PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD0_196M_CLK, PLL_DRAM_MAIN_533M_CLK,
- PLL_VIDEO_MAIN_CLK, PLL_AUDIO_MAIN_CLK}
- },
- {MIPI_DPHY_REF_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_DRAM_MAIN_533M_CLK,
- PLL_SYS_PFD5_CLK, REF_1M_CLK, EXT_CLK_2,
- PLL_VIDEO_MAIN_CLK, EXT_CLK_3}
- },
- {SAI1_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK,
- PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK,
- PLL_ENET_MAIN_125M_CLK, EXT_CLK_2}
- },
- {SAI2_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK,
- PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK,
- PLL_ENET_MAIN_125M_CLK, EXT_CLK_2}
- },
- {SAI3_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK,
- PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK,
- PLL_ENET_MAIN_125M_CLK, EXT_CLK_3}
- },
- {SPDIF_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK,
- PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK,
- PLL_ENET_MAIN_125M_CLK, EXT_CLK_3}
- },
- {ENET1_REF_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_ENET_MAIN_50M_CLK,
- PLL_ENET_MAIN_25M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_AUDIO_MAIN_CLK,
- PLL_VIDEO_MAIN_CLK, EXT_CLK_4}
- },
- {ENET1_TIME_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_AUDIO_MAIN_CLK,
- EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
- EXT_CLK_4, PLL_VIDEO_MAIN_CLK}
- },
- {ENET2_REF_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_ENET_MAIN_50M_CLK,
- PLL_ENET_MAIN_25M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_AUDIO_MAIN_CLK,
- PLL_VIDEO_MAIN_CLK, EXT_CLK_4}
- },
- {ENET2_TIME_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_AUDIO_MAIN_CLK,
- EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
- EXT_CLK_4, PLL_VIDEO_MAIN_CLK}
- },
- {ENET_PHY_REF_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_ENET_MAIN_25M_CLK, PLL_ENET_MAIN_50M_CLK,
- PLL_ENET_MAIN_125M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK,
- PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD3_CLK}
- },
- {EIM_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
- PLL_DRAM_MAIN_533M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_SYS_PFD3_CLK,
- PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK}
- },
- {NAND_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_DRAM_MAIN_533M_CLK,
- PLL_SYS_PFD0_392M_CLK, PLL_SYS_PFD3_CLK, PLL_ENET_MAIN_500M_CLK,
- PLL_ENET_MAIN_250M_CLK, PLL_VIDEO_MAIN_CLK}
- },
- {QSPI_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_PFD4_CLK, PLL_DRAM_MAIN_533M_CLK,
- PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD3_CLK, PLL_SYS_PFD2_270M_CLK,
- PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
- },
- {USDHC1_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_PFD0_392M_CLK, PLL_DRAM_MAIN_533M_CLK,
- PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK,
- PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
- },
- {USDHC2_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_PFD0_392M_CLK, PLL_DRAM_MAIN_533M_CLK,
- PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK,
- PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
- },
- {USDHC3_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_PFD0_392M_CLK, PLL_DRAM_MAIN_533M_CLK,
- PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK,
- PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
- },
- {CAN1_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_DRAM_MAIN_533M_CLK,
- PLL_SYS_MAIN_480M_CLK, PLL_ENET_MAIN_40M_CLK, PLL_USB_MAIN_480M_CLK,
- EXT_CLK_1, EXT_CLK_4}
- },
- {CAN2_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_DRAM_MAIN_533M_CLK,
- PLL_SYS_MAIN_480M_CLK, PLL_ENET_MAIN_40M_CLK, PLL_USB_MAIN_480M_CLK,
- EXT_CLK_1, EXT_CLK_3}
- },
- {I2C1_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK,
- PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK,
- PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK}
- },
- {I2C2_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK,
- PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK,
- PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK}
- },
- {I2C3_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK,
- PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK,
- PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK}
- },
- {I2C4_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK,
- PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK,
- PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK}
- },
- {UART1_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
- PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
- EXT_CLK_4, PLL_USB_MAIN_480M_CLK}
- },
- {UART2_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
- PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
- EXT_CLK_3, PLL_USB_MAIN_480M_CLK}
- },
- {UART3_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
- PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
- EXT_CLK_4, PLL_USB_MAIN_480M_CLK}
- },
- {UART4_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
- PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
- EXT_CLK_3, PLL_USB_MAIN_480M_CLK}
- },
- {UART5_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
- PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
- EXT_CLK_4, PLL_USB_MAIN_480M_CLK}
- },
- {UART6_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
- PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
- EXT_CLK_3, PLL_USB_MAIN_480M_CLK}
- },
- {UART7_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
- PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
- EXT_CLK_4, PLL_USB_MAIN_480M_CLK}
- },
- {ECSPI1_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
- PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK,
- PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK}
- },
- {ECSPI2_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
- PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK,
- PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK}
- },
- {ECSPI3_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
- PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK,
- PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK}
- },
- {ECSPI4_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
- PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK,
- PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK}
- },
- {PWM1_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
- PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_1,
- REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
- },
- {PWM2_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
- PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_1,
- REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
- },
- {PWM3_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
- PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_2,
- REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
- },
- {PWM4_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
- PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_2,
- REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
- },
- {FLEXTIMER1_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
- PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_3,
- REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
- },
- {FLEXTIMER2_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
- PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_3,
- REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
- },
- {SIM1_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
- PLL_DRAM_MAIN_533M_CLK, PLL_USB_MAIN_480M_CLK, PLL_AUDIO_MAIN_CLK,
- PLL_ENET_MAIN_125M_CLK, PLL_SYS_PFD7_CLK}
- },
- {SIM2_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
- PLL_DRAM_MAIN_533M_CLK, PLL_USB_MAIN_480M_CLK, PLL_VIDEO_MAIN_CLK,
- PLL_ENET_MAIN_125M_CLK, PLL_SYS_PFD7_CLK}
- },
- {GPT1_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK,
- PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK,
- PLL_AUDIO_MAIN_CLK, EXT_CLK_1}
- },
- {GPT2_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK,
- PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK,
- PLL_AUDIO_MAIN_CLK, EXT_CLK_2}
- },
- {GPT3_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK,
- PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK,
- PLL_AUDIO_MAIN_CLK, EXT_CLK_3}
- },
- {GPT4_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK,
- PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK,
- PLL_AUDIO_MAIN_CLK, EXT_CLK_4}
- },
- {TRACE_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
- PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK,
- EXT_CLK_1, EXT_CLK_3}
- },
- {WDOG_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
- PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK,
- REF_1M_CLK, PLL_SYS_PFD1_166M_CLK}
- },
- {CSI_MCLK_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
- PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_AUDIO_MAIN_CLK,
- PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
- },
- {AUDIO_MCLK_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
- PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_AUDIO_MAIN_CLK,
- PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
- },
- {WRCLK_CLK_ROOT, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_ENET_MAIN_40M_CLK, PLL_DRAM_MAIN_533M_CLK,
- PLL_USB_MAIN_480M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_SYS_PFD2_270M_CLK,
- PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD7_CLK}
- },
- {IPP_DO_CLKO1, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_MAIN_240M_CLK,
- PLL_SYS_PFD0_196M_CLK, PLL_SYS_PFD3_CLK, PLL_ENET_MAIN_500M_CLK,
- PLL_DRAM_MAIN_533M_CLK, REF_1M_CLK}
- },
- {IPP_DO_CLKO2, CCM_IP_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_SYS_PFD0_392M_CLK,
- PLL_SYS_PFD1_166M_CLK, PLL_SYS_PFD4_CLK, PLL_AUDIO_MAIN_CLK,
- PLL_VIDEO_MAIN_CLK, OSC_32K_CLK}
- },
-};
-
-/* select which entry of root_array */
-static int select(enum clk_root_index clock_id)
-{
- int i, size;
- struct clk_root_map *p = root_array;
-
- size = ARRAY_SIZE(root_array);
-
- for (i = 0; i < size; i++, p++) {
- if (clock_id == p->entry)
- return i;
- }
-
- return -EINVAL;
-}
-
-static int src_supported(int entry, enum clk_root_src clock_src)
-{
- int i, size;
- struct clk_root_map *p = &root_array[entry];
-
- if ((p->type == CCM_DRAM_PHYM_CHANNEL) || (p->type == CCM_DRAM_CHANNEL))
- size = 2;
- else
- size = 8;
-
- for (i = 0; i < size; i++) {
- if (p->src_mux[i] == clock_src)
- return i;
- }
-
- return -EINVAL;
-}
-
-/* Set src for clock root slice. */
-int clock_set_src(enum clk_root_index clock_id, enum clk_root_src clock_src)
-{
- int root_entry, src_entry;
- u32 reg;
-
- if (clock_id >= CLK_ROOT_MAX)
- return -EINVAL;
-
- root_entry = select(clock_id);
- if (root_entry < 0)
- return -EINVAL;
-
- src_entry = src_supported(root_entry, clock_src);
- if (src_entry < 0)
- return -EINVAL;
-
- reg = __raw_readl(&imx_ccm->root[clock_id].target_root);
- reg &= ~CLK_ROOT_MUX_MASK;
- reg |= src_entry << CLK_ROOT_MUX_SHIFT;
- __raw_writel(reg, &imx_ccm->root[clock_id].target_root);
-
- return 0;
-}
-
-/* Get src of a clock root slice. */
-int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src)
-{
- u32 val;
- int root_entry;
- struct clk_root_map *p;
-
- if (clock_id >= CLK_ROOT_MAX)
- return -EINVAL;
-
- val = __raw_readl(&imx_ccm->root[clock_id].target_root);
- val &= CLK_ROOT_MUX_MASK;
- val >>= CLK_ROOT_MUX_SHIFT;
-
- root_entry = select(clock_id);
- if (root_entry < 0)
- return -EINVAL;
-
- p = &root_array[root_entry];
- *p_clock_src = p->src_mux[val];
-
- return 0;
-}
-
-int clock_set_prediv(enum clk_root_index clock_id, enum root_pre_div pre_div)
-{
- int root_entry;
- struct clk_root_map *p;
- u32 reg;
-
- if (clock_id >= CLK_ROOT_MAX)
- return -EINVAL;
-
- root_entry = select(clock_id);
- if (root_entry < 0)
- return -EINVAL;
-
- p = &root_array[root_entry];
-
- if ((p->type == CCM_CORE_CHANNEL) ||
- (p->type == CCM_DRAM_PHYM_CHANNEL) ||
- (p->type == CCM_DRAM_CHANNEL)) {
- if (pre_div != CLK_ROOT_PRE_DIV1) {
- printf("Error pre div!\n");
- return -EINVAL;
- }
- }
-
- reg = __raw_readl(&imx_ccm->root[clock_id].target_root);
- reg &= ~CLK_ROOT_PRE_DIV_MASK;
- reg |= pre_div << CLK_ROOT_PRE_DIV_SHIFT;
- __raw_writel(reg, &imx_ccm->root[clock_id].target_root);
-
- return 0;
-}
-
-int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div)
-{
- u32 val;
- int root_entry;
- struct clk_root_map *p;
-
- if (clock_id >= CLK_ROOT_MAX)
- return -EINVAL;
-
- root_entry = select(clock_id);
- if (root_entry < 0)
- return -EINVAL;
-
- p = &root_array[root_entry];
-
- if ((p->type == CCM_CORE_CHANNEL) ||
- (p->type == CCM_DRAM_PHYM_CHANNEL) ||
- (p->type == CCM_DRAM_CHANNEL)) {
- *pre_div = 0;
- return 0;
- }
-
- val = __raw_readl(&imx_ccm->root[clock_id].target_root);
- val &= CLK_ROOT_PRE_DIV_MASK;
- val >>= CLK_ROOT_PRE_DIV_SHIFT;
-
- *pre_div = val;
-
- return 0;
-}
-
-int clock_set_postdiv(enum clk_root_index clock_id, enum root_post_div div)
-{
- u32 reg;
-
- if (clock_id >= CLK_ROOT_MAX)
- return -EINVAL;
-
- if (clock_id == DRAM_PHYM_CLK_ROOT) {
- if (div != CLK_ROOT_POST_DIV1) {
- printf("Error post div!\n");
- return -EINVAL;
- }
- }
-
- /* Only 3 bit post div. */
- if ((clock_id == DRAM_CLK_ROOT) && (div > CLK_ROOT_POST_DIV7)) {
- printf("Error post div!\n");
- return -EINVAL;
- }
-
- reg = __raw_readl(&imx_ccm->root[clock_id].target_root);
- reg &= ~CLK_ROOT_POST_DIV_MASK;
- reg |= div << CLK_ROOT_POST_DIV_SHIFT;
- __raw_writel(reg, &imx_ccm->root[clock_id].target_root);
-
- return 0;
-}
-
-int clock_get_postdiv(enum clk_root_index clock_id, enum root_post_div *div)
-{
- u32 val;
-
- if (clock_id >= CLK_ROOT_MAX)
- return -EINVAL;
-
- if (clock_id == DRAM_PHYM_CLK_ROOT) {
- *div = 0;
- return 0;
- }
-
- val = __raw_readl(&imx_ccm->root[clock_id].target_root);
- if (clock_id == DRAM_CLK_ROOT)
- val &= DRAM_CLK_ROOT_POST_DIV_MASK;
- else
- val &= CLK_ROOT_POST_DIV_MASK;
- val >>= CLK_ROOT_POST_DIV_SHIFT;
-
- *div = val;
-
- return 0;
-}
-
-int clock_set_autopostdiv(enum clk_root_index clock_id, enum root_auto_div div,
- int auto_en)
-{
- u32 val;
- int root_entry;
- struct clk_root_map *p;
-
- if (clock_id >= CLK_ROOT_MAX)
- return -EINVAL;
-
- root_entry = select(clock_id);
- if (root_entry < 0)
- return -EINVAL;
-
- p = &root_array[root_entry];
-
- if ((p->type != CCM_BUS_CHANNEL) && (p->type != CCM_AHB_CHANNEL)) {
- printf("Auto postdiv not supported.!\n");
- return -EINVAL;
- }
-
- /*
- * Each time only one filed can be changed, no use target_root_set.
- */
- val = __raw_readl(&imx_ccm->root[clock_id].target_root);
- val &= ~CLK_ROOT_AUTO_DIV_MASK;
- val |= (div << CLK_ROOT_AUTO_DIV_SHIFT);
-
- if (auto_en)
- val |= CLK_ROOT_AUTO_EN;
- else
- val &= ~CLK_ROOT_AUTO_EN;
-
- __raw_writel(val, &imx_ccm->root[clock_id].target_root);
-
- return 0;
-}
-
-int clock_get_autopostdiv(enum clk_root_index clock_id, enum root_auto_div *div,
- int *auto_en)
-{
- u32 val;
- int root_entry;
- struct clk_root_map *p;
-
- if (clock_id >= CLK_ROOT_MAX)
- return -EINVAL;
-
- root_entry = select(clock_id);
- if (root_entry < 0)
- return -EINVAL;
-
- p = &root_array[root_entry];
-
- /*
- * Only bus/ahb channel supports auto div.
- * If unsupported, just set auto_en and div with 0.
- */
- if ((p->type != CCM_BUS_CHANNEL) && (p->type != CCM_AHB_CHANNEL)) {
- *auto_en = 0;
- *div = 0;
- return 0;
- }
-
- val = __raw_readl(&imx_ccm->root[clock_id].target_root);
- if ((val & CLK_ROOT_AUTO_EN_MASK) == 0)
- *auto_en = 0;
- else
- *auto_en = 1;
-
- val &= CLK_ROOT_AUTO_DIV_MASK;
- val >>= CLK_ROOT_AUTO_DIV_SHIFT;
-
- *div = val;
-
- return 0;
-}
-
-int clock_get_target_val(enum clk_root_index clock_id, u32 *val)
-{
- if (clock_id >= CLK_ROOT_MAX)
- return -EINVAL;
-
- *val = __raw_readl(&imx_ccm->root[clock_id].target_root);
-
- return 0;
-}
-
-int clock_set_target_val(enum clk_root_index clock_id, u32 val)
-{
- if (clock_id >= CLK_ROOT_MAX)
- return -EINVAL;
-
- __raw_writel(val, &imx_ccm->root[clock_id].target_root);
-
- return 0;
-}
-
-/* Auto_div and auto_en is ignored, they are rarely used. */
-int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,
- enum root_post_div post_div, enum clk_root_src clock_src)
-{
- u32 val;
- int root_entry, src_entry;
- struct clk_root_map *p;
-
- if (clock_id >= CLK_ROOT_MAX)
- return -EINVAL;
-
- root_entry = select(clock_id);
- if (root_entry < 0)
- return -EINVAL;
-
- p = &root_array[root_entry];
-
- if ((p->type == CCM_CORE_CHANNEL) ||
- (p->type == CCM_DRAM_PHYM_CHANNEL) ||
- (p->type == CCM_DRAM_CHANNEL)) {
- if (pre_div != CLK_ROOT_PRE_DIV1) {
- printf("Error pre div!\n");
- return -EINVAL;
- }
- }
-
- /* Only 3 bit post div. */
- if (p->type == CCM_DRAM_CHANNEL) {
- if (post_div > CLK_ROOT_POST_DIV7) {
- printf("Error post div!\n");
- return -EINVAL;
- }
- }
-
- if (p->type == CCM_DRAM_PHYM_CHANNEL) {
- if (post_div != CLK_ROOT_POST_DIV1) {
- printf("Error post div!\n");
- return -EINVAL;
- }
- }
-
- src_entry = src_supported(root_entry, clock_src);
- if (src_entry < 0)
- return -EINVAL;
-
- val = CLK_ROOT_ON | pre_div << CLK_ROOT_PRE_DIV_SHIFT |
- post_div << CLK_ROOT_POST_DIV_SHIFT |
- src_entry << CLK_ROOT_MUX_SHIFT;
-
- __raw_writel(val, &imx_ccm->root[clock_id].target_root);
-
- return 0;
-}
-
-int clock_root_enabled(enum clk_root_index clock_id)
-{
- u32 val;
-
- if (clock_id >= CLK_ROOT_MAX)
- return -EINVAL;
-
- /*
- * No enable bit for DRAM controller and PHY. Just return enabled.
- */
- if ((clock_id == DRAM_PHYM_CLK_ROOT) || (clock_id == DRAM_CLK_ROOT))
- return 1;
-
- val = __raw_readl(&imx_ccm->root[clock_id].target_root);
-
- return (val & CLK_ROOT_ENABLE_MASK) ? 1 : 0;
-}
-
-/* CCGR gate operation */
-int clock_enable(enum clk_ccgr_index index, bool enable)
-{
- if (index >= CCGR_MAX)
- return -EINVAL;
-
- if (enable)
- __raw_writel(CCM_CLK_ON_MSK,
- &imx_ccm->ccgr_array[index].ccgr_set);
- else
- __raw_writel(CCM_CLK_ON_MSK,
- &imx_ccm->ccgr_array[index].ccgr_clr);
-
- return 0;
-}
+++ /dev/null
-#include <asm/io.h>
-#include <asm/psci.h>
-#include <asm/secure.h>
-#include <asm/arch/imx-regs.h>
-#include <common.h>
-
-
-#define GPC_CPU_PGC_SW_PDN_REQ 0xfc
-#define GPC_CPU_PGC_SW_PUP_REQ 0xf0
-#define GPC_PGC_C1 0x840
-
-#define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7 0x2
-
-/* below is for i.MX7D */
-#define SRC_GPR1_MX7D 0x074
-#define SRC_A7RCR0 0x004
-#define SRC_A7RCR1 0x008
-
-#define BP_SRC_A7RCR0_A7_CORE_RESET0 0
-#define BP_SRC_A7RCR1_A7_CORE1_ENABLE 1
-
-static inline void imx_gpcv2_set_m_core_pgc(bool enable, u32 offset)
-{
- writel(enable, GPC_IPS_BASE_ADDR + offset);
-}
-
-__secure void imx_gpcv2_set_core1_power(bool pdn)
-{
- u32 reg = pdn ? GPC_CPU_PGC_SW_PUP_REQ : GPC_CPU_PGC_SW_PDN_REQ;
- u32 val;
-
- imx_gpcv2_set_m_core_pgc(true, GPC_PGC_C1);
-
- val = readl(GPC_IPS_BASE_ADDR + reg);
- val |= BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7;
- writel(val, GPC_IPS_BASE_ADDR + reg);
-
- while ((readl(GPC_IPS_BASE_ADDR + reg) &
- BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7) != 0)
- ;
-
- imx_gpcv2_set_m_core_pgc(false, GPC_PGC_C1);
-}
-
-__secure void imx_enable_cpu_ca7(int cpu, bool enable)
-{
- u32 mask, val;
-
- mask = 1 << (BP_SRC_A7RCR1_A7_CORE1_ENABLE + cpu - 1);
- val = readl(SRC_BASE_ADDR + SRC_A7RCR1);
- val = enable ? val | mask : val & ~mask;
- writel(val, SRC_BASE_ADDR + SRC_A7RCR1);
-}
-
-__secure int imx_cpu_on(int fn, int cpu, int pc)
-{
- writel(pc, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D);
- imx_gpcv2_set_core1_power(true);
- imx_enable_cpu_ca7(cpu, true);
- return 0;
-}
-
-__secure int imx_cpu_off(int cpu)
-{
- imx_enable_cpu_ca7(cpu, false);
- imx_gpcv2_set_core1_power(false);
- writel(0, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D + 4);
- return 0;
-}
+++ /dev/null
-#include <config.h>
-#include <linux/linkage.h>
-
-#include <asm/armv7.h>
-#include <asm/arch-armv7/generictimer.h>
-#include <asm/psci.h>
-
- .pushsection ._secure.text, "ax"
-
- .arch_extension sec
-
-.globl psci_cpu_on
-psci_cpu_on:
- push {r4, r5, lr}
-
- mov r4, r0
- mov r5, r1
- mov r0, r1
- mov r1, r2
- bl psci_save_target_pc
-
- mov r0, r4
- mov r1, r5
- ldr r2, =psci_cpu_entry
- bl imx_cpu_on
-
- pop {r4, r5, pc}
-
-.globl psci_cpu_off
-psci_cpu_off:
-
- bl psci_cpu_off_common
- bl psci_get_cpu_id
- bl imx_cpu_off
-
-1: wfi
- b 1b
-
- .popsection
+++ /dev/null
-/*
- * Copyright (C) 2015 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/dma.h>
-#include <asm/imx-common/hab.h>
-#include <asm/imx-common/rdc-sema.h>
-#include <asm/arch/imx-rdc.h>
-#include <asm/arch/crm_regs.h>
-#include <dm.h>
-#include <imx_thermal.h>
-
-#if defined(CONFIG_IMX_THERMAL)
-static const struct imx_thermal_plat imx7_thermal_plat = {
- .regs = (void *)ANATOP_BASE_ADDR,
- .fuse_bank = 3,
- .fuse_word = 3,
-};
-
-U_BOOT_DEVICE(imx7_thermal) = {
- .name = "imx_thermal",
- .platdata = &imx7_thermal_plat,
-};
-#endif
-
-#ifdef CONFIG_IMX_RDC
-/*
- * In current design, if any peripheral was assigned to both A7 and M4,
- * it will receive ipg_stop or ipg_wait when any of the 2 platforms enter
- * low power mode. So M4 sleep will cause some peripherals fail to work
- * at A7 core side. At default, all resources are in domain 0 - 3.
- *
- * There are 26 peripherals impacted by this IC issue:
- * SIM2(sim2/emvsim2)
- * SIM1(sim1/emvsim1)
- * UART1/UART2/UART3/UART4/UART5/UART6/UART7
- * SAI1/SAI2/SAI3
- * WDOG1/WDOG2/WDOG3/WDOG4
- * GPT1/GPT2/GPT3/GPT4
- * PWM1/PWM2/PWM3/PWM4
- * ENET1/ENET2
- * Software Workaround:
- * Here we setup some resources to domain 0 where M4 codes will move
- * the M4 out of this domain. Then M4 is not able to access them any longer.
- * This is a workaround for ic issue. So the peripherals are not shared
- * by them. This way requires the uboot implemented the RDC driver and
- * set the 26 IPs above to domain 0 only. M4 code will assign resource
- * to its own domain, if it want to use the resource.
- */
-static rdc_peri_cfg_t const resources[] = {
- (RDC_PER_SIM1 | RDC_DOMAIN(0)),
- (RDC_PER_SIM2 | RDC_DOMAIN(0)),
- (RDC_PER_UART1 | RDC_DOMAIN(0)),
- (RDC_PER_UART2 | RDC_DOMAIN(0)),
- (RDC_PER_UART3 | RDC_DOMAIN(0)),
- (RDC_PER_UART4 | RDC_DOMAIN(0)),
- (RDC_PER_UART5 | RDC_DOMAIN(0)),
- (RDC_PER_UART6 | RDC_DOMAIN(0)),
- (RDC_PER_UART7 | RDC_DOMAIN(0)),
- (RDC_PER_SAI1 | RDC_DOMAIN(0)),
- (RDC_PER_SAI2 | RDC_DOMAIN(0)),
- (RDC_PER_SAI3 | RDC_DOMAIN(0)),
- (RDC_PER_WDOG1 | RDC_DOMAIN(0)),
- (RDC_PER_WDOG2 | RDC_DOMAIN(0)),
- (RDC_PER_WDOG3 | RDC_DOMAIN(0)),
- (RDC_PER_WDOG4 | RDC_DOMAIN(0)),
- (RDC_PER_GPT1 | RDC_DOMAIN(0)),
- (RDC_PER_GPT2 | RDC_DOMAIN(0)),
- (RDC_PER_GPT3 | RDC_DOMAIN(0)),
- (RDC_PER_GPT4 | RDC_DOMAIN(0)),
- (RDC_PER_PWM1 | RDC_DOMAIN(0)),
- (RDC_PER_PWM2 | RDC_DOMAIN(0)),
- (RDC_PER_PWM3 | RDC_DOMAIN(0)),
- (RDC_PER_PWM4 | RDC_DOMAIN(0)),
- (RDC_PER_ENET1 | RDC_DOMAIN(0)),
- (RDC_PER_ENET2 | RDC_DOMAIN(0)),
-};
-
-static void isolate_resource(void)
-{
- imx_rdc_setup_peripherals(resources, ARRAY_SIZE(resources));
-}
-#endif
-
-#if defined(CONFIG_SECURE_BOOT)
-struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
- .bank = 1,
- .word = 3,
-};
-#endif
-
-/*
- * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
- * defines a 2-bit SPEED_GRADING
- */
-#define OCOTP_TESTER3_SPEED_SHIFT 8
-#define OCOTP_TESTER3_SPEED_800MHZ 0
-#define OCOTP_TESTER3_SPEED_500MHZ 1
-#define OCOTP_TESTER3_SPEED_1GHZ 2
-#define OCOTP_TESTER3_SPEED_1P2GHZ 3
-
-u32 get_cpu_speed_grade_hz(void)
-{
- struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
- struct fuse_bank *bank = &ocotp->bank[1];
- struct fuse_bank1_regs *fuse =
- (struct fuse_bank1_regs *)bank->fuse_regs;
- uint32_t val;
-
- val = readl(&fuse->tester3);
- val >>= OCOTP_TESTER3_SPEED_SHIFT;
- val &= 0x3;
-
- switch(val) {
- case OCOTP_TESTER3_SPEED_800MHZ:
- return 800000000;
- case OCOTP_TESTER3_SPEED_500MHZ:
- return 500000000;
- case OCOTP_TESTER3_SPEED_1GHZ:
- return 1000000000;
- case OCOTP_TESTER3_SPEED_1P2GHZ:
- return 1200000000;
- }
- return 0;
-}
-
-/*
- * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
- * defines a 2-bit SPEED_GRADING
- */
-#define OCOTP_TESTER3_TEMP_SHIFT 6
-
-u32 get_cpu_temp_grade(int *minc, int *maxc)
-{
- struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
- struct fuse_bank *bank = &ocotp->bank[1];
- struct fuse_bank1_regs *fuse =
- (struct fuse_bank1_regs *)bank->fuse_regs;
- uint32_t val;
-
- val = readl(&fuse->tester3);
- val >>= OCOTP_TESTER3_TEMP_SHIFT;
- val &= 0x3;
-
- if (minc && maxc) {
- if (val == TEMP_AUTOMOTIVE) {
- *minc = -40;
- *maxc = 125;
- } else if (val == TEMP_INDUSTRIAL) {
- *minc = -40;
- *maxc = 105;
- } else if (val == TEMP_EXTCOMMERCIAL) {
- *minc = -20;
- *maxc = 105;
- } else {
- *minc = 0;
- *maxc = 95;
- }
- }
- return val;
-}
-
-static bool is_mx7d(void)
-{
- struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
- struct fuse_bank *bank = &ocotp->bank[1];
- struct fuse_bank1_regs *fuse =
- (struct fuse_bank1_regs *)bank->fuse_regs;
- int val;
-
- val = readl(&fuse->tester4);
- if (val & 1)
- return false;
- else
- return true;
-}
-
-u32 get_cpu_rev(void)
-{
- struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
- ANATOP_BASE_ADDR;
- u32 reg = readl(&ccm_anatop->digprog);
- u32 type = (reg >> 16) & 0xff;
-
- if (!is_mx7d())
- type = MXC_CPU_MX7S;
-
- reg &= 0xff;
- return (type << 12) | reg;
-}
-
-#ifdef CONFIG_REVISION_TAG
-u32 __weak get_board_rev(void)
-{
- return get_cpu_rev();
-}
-#endif
-
-/* enable all periherial can be accessed in nosec mode */
-static void init_csu(void)
-{
- int i = 0;
- for (i = 0; i < CSU_NUM_REGS; i++)
- writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4);
-}
-
-static void imx_enet_mdio_fixup(void)
-{
- struct iomuxc_gpr_base_regs *gpr_regs =
- (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
-
- /*
- * The management data input/output (MDIO) requires open-drain,
- * i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
- * this feature. So to TO1.1, need to enable open drain by setting
- * bits GPR0[8:7].
- */
-
- if (soc_rev() >= CHIP_REV_1_1) {
- setbits_le32(&gpr_regs->gpr[0],
- IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK);
- }
-}
-
-int arch_cpu_init(void)
-{
- init_aips();
-
- init_csu();
- /* Disable PDE bit of WMCR register */
- imx_set_wdog_powerdown(false);
-
- imx_enet_mdio_fixup();
-
-#ifdef CONFIG_APBH_DMA
- /* Start APBH DMA */
- mxs_dma_init();
-#endif
-
- if (IS_ENABLED(CONFIG_IMX_RDC))
- isolate_resource();
-
- return 0;
-}
-
-#ifdef CONFIG_ARCH_MISC_INIT
-int arch_misc_init(void)
-{
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
- if (is_mx7d())
- setenv("soc", "imx7d");
- else
- setenv("soc", "imx7s");
-#endif
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_SERIAL_TAG
-void get_board_serial(struct tag_serialnr *serialnr)
-{
- struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
- struct fuse_bank *bank = &ocotp->bank[0];
- struct fuse_bank0_regs *fuse =
- (struct fuse_bank0_regs *)bank->fuse_regs;
-
- serialnr->low = fuse->tester0;
- serialnr->high = fuse->tester1;
-}
-#endif
-
-#if defined(CONFIG_FEC_MXC)
-void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
-{
- struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
- struct fuse_bank *bank = &ocotp->bank[9];
- struct fuse_bank9_regs *fuse =
- (struct fuse_bank9_regs *)bank->fuse_regs;
-
- if (0 == dev_id) {
- u32 value = readl(&fuse->mac_addr1);
- mac[0] = (value >> 8);
- mac[1] = value;
-
- value = readl(&fuse->mac_addr0);
- mac[2] = value >> 24;
- mac[3] = value >> 16;
- mac[4] = value >> 8;
- mac[5] = value;
- } else {
- u32 value = readl(&fuse->mac_addr2);
- mac[0] = value >> 24;
- mac[1] = value >> 16;
- mac[2] = value >> 8;
- mac[3] = value;
-
- value = readl(&fuse->mac_addr1);
- mac[4] = value >> 24;
- mac[5] = value >> 16;
- }
-}
-#endif
-
-#ifdef CONFIG_IMX_BOOTAUX
-int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
-{
- u32 stack, pc;
- struct src *src_reg = (struct src *)SRC_BASE_ADDR;
-
- if (!boot_private_data)
- return 1;
-
- stack = *(u32 *)boot_private_data;
- pc = *(u32 *)(boot_private_data + 4);
-
- /* Set the stack and pc to M4 bootROM */
- writel(stack, M4_BOOTROM_BASE_ADDR);
- writel(pc, M4_BOOTROM_BASE_ADDR + 4);
-
- /* Enable M4 */
- clrsetbits_le32(&src_reg->m4rcr, SRC_M4RCR_M4C_NON_SCLR_RST_MASK,
- SRC_M4RCR_ENABLE_M4_MASK);
-
- return 0;
-}
-
-int arch_auxiliary_core_check_up(u32 core_id)
-{
- uint32_t val;
- struct src *src_reg = (struct src *)SRC_BASE_ADDR;
-
- val = readl(&src_reg->m4rcr);
- if (val & 0x00000001)
- return 0; /* assert in reset */
-
- return 1;
-}
-#endif
-
-void set_wdog_reset(struct wdog_regs *wdog)
-{
- u32 reg = readw(&wdog->wcr);
- /*
- * Output WDOG_B signal to reset external pmic or POR_B decided by
- * the board desgin. Without external reset, the peripherals/DDR/
- * PMIC are not reset, that may cause system working abnormal.
- */
- reg = readw(&wdog->wcr);
- reg |= 1 << 3;
- /*
- * WDZST bit is write-once only bit. Align this bit in kernel,
- * otherwise kernel code will have no chance to set this bit.
- */
- reg |= 1 << 0;
- writew(reg, &wdog->wcr);
-}
-
-/*
- * cfg_val will be used for
- * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
- * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
- * to SBMR1, which will determine the boot device.
- */
-const struct boot_mode soc_boot_modes[] = {
- {"ecspi1:0", MAKE_CFGVAL(0x00, 0x60, 0x00, 0x00)},
- {"ecspi1:1", MAKE_CFGVAL(0x40, 0x62, 0x00, 0x00)},
- {"ecspi1:2", MAKE_CFGVAL(0x80, 0x64, 0x00, 0x00)},
- {"ecspi1:3", MAKE_CFGVAL(0xc0, 0x66, 0x00, 0x00)},
-
- {"weim", MAKE_CFGVAL(0x00, 0x50, 0x00, 0x00)},
- {"qspi1", MAKE_CFGVAL(0x10, 0x40, 0x00, 0x00)},
- /* 4 bit bus width */
- {"usdhc1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
- {"usdhc2", MAKE_CFGVAL(0x10, 0x14, 0x00, 0x00)},
- {"usdhc3", MAKE_CFGVAL(0x10, 0x18, 0x00, 0x00)},
- {"mmc1", MAKE_CFGVAL(0x10, 0x20, 0x00, 0x00)},
- {"mmc2", MAKE_CFGVAL(0x10, 0x24, 0x00, 0x00)},
- {"mmc3", MAKE_CFGVAL(0x10, 0x28, 0x00, 0x00)},
- {NULL, 0},
-};
-
-enum boot_device get_boot_device(void)
-{
- struct bootrom_sw_info **p =
- (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
-
- enum boot_device boot_dev = SD1_BOOT;
- u8 boot_type = (*p)->boot_dev_type;
- u8 boot_instance = (*p)->boot_dev_instance;
-
- switch (boot_type) {
- case BOOT_TYPE_SD:
- boot_dev = boot_instance + SD1_BOOT;
- break;
- case BOOT_TYPE_MMC:
- boot_dev = boot_instance + MMC1_BOOT;
- break;
- case BOOT_TYPE_NAND:
- boot_dev = NAND_BOOT;
- break;
- case BOOT_TYPE_QSPI:
- boot_dev = QSPI_BOOT;
- break;
- case BOOT_TYPE_WEIM:
- boot_dev = WEIM_NOR_BOOT;
- break;
- case BOOT_TYPE_SPINOR:
- boot_dev = SPI_NOR_BOOT;
- break;
- default:
- break;
- }
-
- return boot_dev;
-}
-
-#ifdef CONFIG_ENV_IS_IN_MMC
-__weak int board_mmc_get_env_dev(int devno)
-{
- return CONFIG_SYS_MMC_ENV_DEV;
-}
-
-int mmc_get_env_dev(void)
-{
- struct bootrom_sw_info **p =
- (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
- int devno = (*p)->boot_dev_instance;
- u8 boot_type = (*p)->boot_dev_type;
-
- /* If not boot from sd/mmc, use default value */
- if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC))
- return CONFIG_SYS_MMC_ENV_DEV;
-
- return board_mmc_get_env_dev(devno);
-}
-#endif
-
-void s_init(void)
-{
-#if !defined CONFIG_SPL_BUILD
- /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
- asm volatile(
- "mrc p15, 0, r0, c1, c0, 1\n"
- "orr r0, r0, #1 << 6\n"
- "mcr p15, 0, r0, c1, c0, 1\n");
-#endif
- /* clock configuration. */
- clock_init();
-
- return;
-}
-
-void reset_misc(void)
-{
-#ifdef CONFIG_VIDEO_MXS
- lcdif_power_down();
-#endif
-}
-
+++ /dev/null
-if ARCH_MX7ULP
-
-config SYS_SOC
- default "mx7ulp"
-
-choice
- prompt "MX7ULP board select"
- optional
-
-config TARGET_MX7ULP_EVK
- bool "Support mx7ulp EVK board"
-
-endchoice
-
-source "board/freescale/mx7ulp_evk/Kconfig"
-
-endif
+++ /dev/null
-#
-# (C) Copyright 2016 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-#
-
-obj-y := soc.o clock.o iomux.o pcc.o scg.o
+++ /dev/null
-/*
- * Copyright (C) 2016 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <div64.h>
-#include <asm/io.h>
-#include <errno.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int get_clocks(void)
-{
-#ifdef CONFIG_FSL_ESDHC
-#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC0_RBASE
- gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC1_RBASE
- gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-#endif
-#endif
- return 0;
-}
-
-static u32 get_fast_plat_clk(void)
-{
- return scg_clk_get_rate(SCG_NIC0_CLK);
-}
-
-static u32 get_slow_plat_clk(void)
-{
- return scg_clk_get_rate(SCG_NIC1_CLK);
-}
-
-static u32 get_ipg_clk(void)
-{
- return scg_clk_get_rate(SCG_NIC1_BUS_CLK);
-}
-
-u32 get_lpuart_clk(void)
-{
- int index = 0;
-
- const u32 lpuart_array[] = {
- LPUART0_RBASE,
- LPUART1_RBASE,
- LPUART2_RBASE,
- LPUART3_RBASE,
- LPUART4_RBASE,
- LPUART5_RBASE,
- LPUART6_RBASE,
- LPUART7_RBASE,
- };
-
- const enum pcc_clk lpuart_pcc_clks[] = {
- PER_CLK_LPUART4,
- PER_CLK_LPUART5,
- PER_CLK_LPUART6,
- PER_CLK_LPUART7,
- };
-
- for (index = 0; index < 8; index++) {
- if (lpuart_array[index] == LPUART_BASE)
- break;
- }
-
- if (index < 4 || index > 7)
- return 0;
-
- return pcc_clock_get_rate(lpuart_pcc_clks[index - 4]);
-}
-
-#ifdef CONFIG_SYS_LPI2C_IMX
-int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
-{
- /* Set parent to FIRC DIV2 clock */
- const enum pcc_clk lpi2c_pcc_clks[] = {
- PER_CLK_LPI2C4,
- PER_CLK_LPI2C5,
- PER_CLK_LPI2C6,
- PER_CLK_LPI2C7,
- };
-
- if (i2c_num < 4 || i2c_num > 7)
- return -EINVAL;
-
- if (enable) {
- pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], false);
- pcc_clock_sel(lpi2c_pcc_clks[i2c_num - 4], SCG_FIRC_DIV2_CLK);
- pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], true);
- } else {
- pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], false);
- }
- return 0;
-}
-
-u32 imx_get_i2cclk(unsigned i2c_num)
-{
- const enum pcc_clk lpi2c_pcc_clks[] = {
- PER_CLK_LPI2C4,
- PER_CLK_LPI2C5,
- PER_CLK_LPI2C6,
- PER_CLK_LPI2C7,
- };
-
- if (i2c_num < 4 || i2c_num > 7)
- return 0;
-
- return pcc_clock_get_rate(lpi2c_pcc_clks[i2c_num - 4]);
-}
-#endif
-
-unsigned int mxc_get_clock(enum mxc_clock clk)
-{
- switch (clk) {
- case MXC_ARM_CLK:
- return scg_clk_get_rate(SCG_CORE_CLK);
- case MXC_AXI_CLK:
- return get_fast_plat_clk();
- case MXC_AHB_CLK:
- return get_slow_plat_clk();
- case MXC_IPG_CLK:
- return get_ipg_clk();
- case MXC_I2C_CLK:
- return pcc_clock_get_rate(PER_CLK_LPI2C4);
- case MXC_UART_CLK:
- return get_lpuart_clk();
- case MXC_ESDHC_CLK:
- return pcc_clock_get_rate(PER_CLK_USDHC0);
- case MXC_ESDHC2_CLK:
- return pcc_clock_get_rate(PER_CLK_USDHC1);
- case MXC_DDR_CLK:
- return scg_clk_get_rate(SCG_DDR_CLK);
- default:
- printf("Unsupported mxc_clock %d\n", clk);
- break;
- }
-
- return 0;
-}
-
-void init_clk_usdhc(u32 index)
-{
- switch (index) {
- case 0:
- /*Disable the clock before configure it */
- pcc_clock_enable(PER_CLK_USDHC0, false);
-
- /* 158MHz / 1 = 158MHz */
- pcc_clock_sel(PER_CLK_USDHC0, SCG_NIC1_CLK);
- pcc_clock_div_config(PER_CLK_USDHC0, false, 1);
- pcc_clock_enable(PER_CLK_USDHC0, true);
- break;
- case 1:
- /*Disable the clock before configure it */
- pcc_clock_enable(PER_CLK_USDHC1, false);
-
- /* 158MHz / 1 = 158MHz */
- pcc_clock_sel(PER_CLK_USDHC1, SCG_NIC1_CLK);
- pcc_clock_div_config(PER_CLK_USDHC1, false, 1);
- pcc_clock_enable(PER_CLK_USDHC1, true);
- break;
- default:
- printf("Invalid index for USDHC %d\n", index);
- break;
- }
-}
-
-#ifdef CONFIG_MXC_OCOTP
-
-#define OCOTP_CTRL_PCC1_SLOT (38)
-#define OCOTP_CTRL_HIGH4K_PCC1_SLOT (39)
-
-void enable_ocotp_clk(unsigned char enable)
-{
- u32 val;
-
- /*
- * Seems the OCOTP CLOCKs have been enabled at default,
- * check its inuse flag
- */
-
- val = readl(PCC1_RBASE + 4 * OCOTP_CTRL_PCC1_SLOT);
- if (!(val & PCC_INUSE_MASK))
- writel(PCC_CGC_MASK, (PCC1_RBASE + 4 * OCOTP_CTRL_PCC1_SLOT));
-
- val = readl(PCC1_RBASE + 4 * OCOTP_CTRL_HIGH4K_PCC1_SLOT);
- if (!(val & PCC_INUSE_MASK))
- writel(PCC_CGC_MASK,
- (PCC1_RBASE + 4 * OCOTP_CTRL_HIGH4K_PCC1_SLOT));
-}
-#endif
-
-void enable_usboh3_clk(unsigned char enable)
-{
- if (enable) {
- pcc_clock_enable(PER_CLK_USB0, false);
- pcc_clock_sel(PER_CLK_USB0, SCG_NIC1_BUS_CLK);
- pcc_clock_enable(PER_CLK_USB0, true);
-
-#ifdef CONFIG_USB_MAX_CONTROLLER_COUNT
- if (CONFIG_USB_MAX_CONTROLLER_COUNT > 1) {
- pcc_clock_enable(PER_CLK_USB1, false);
- pcc_clock_sel(PER_CLK_USB1, SCG_NIC1_BUS_CLK);
- pcc_clock_enable(PER_CLK_USB1, true);
- }
-#endif
-
- pcc_clock_enable(PER_CLK_USB_PHY, true);
- pcc_clock_enable(PER_CLK_USB_PL301, true);
- } else {
- pcc_clock_enable(PER_CLK_USB0, false);
- pcc_clock_enable(PER_CLK_USB1, false);
- pcc_clock_enable(PER_CLK_USB_PHY, false);
- pcc_clock_enable(PER_CLK_USB_PL301, false);
- }
-}
-
-static void lpuart_set_clk(uint32_t index, enum scg_clk clk)
-{
- const enum pcc_clk lpuart_pcc_clks[] = {
- PER_CLK_LPUART4,
- PER_CLK_LPUART5,
- PER_CLK_LPUART6,
- PER_CLK_LPUART7,
- };
-
- if (index < 4 || index > 7)
- return;
-
-#ifndef CONFIG_CLK_DEBUG
- pcc_clock_enable(lpuart_pcc_clks[index - 4], false);
-#endif
- pcc_clock_sel(lpuart_pcc_clks[index - 4], clk);
- pcc_clock_enable(lpuart_pcc_clks[index - 4], true);
-}
-
-static void init_clk_lpuart(void)
-{
- u32 index = 0, i;
-
- const u32 lpuart_array[] = {
- LPUART0_RBASE,
- LPUART1_RBASE,
- LPUART2_RBASE,
- LPUART3_RBASE,
- LPUART4_RBASE,
- LPUART5_RBASE,
- LPUART6_RBASE,
- LPUART7_RBASE,
- };
-
- for (i = 0; i < 8; i++) {
- if (lpuart_array[i] == LPUART_BASE) {
- index = i;
- break;
- }
- }
-
- lpuart_set_clk(index, SCG_SOSC_DIV2_CLK);
-}
-
-static void init_clk_rgpio2p(void)
-{
- /*Enable RGPIO2P1 clock */
- pcc_clock_enable(PER_CLK_RGPIO2P1, true);
-
- /*
- * Hard code to enable RGPIO2P0 clock since it is not
- * in clock frame for A7 domain
- */
- writel(PCC_CGC_MASK, (PCC0_RBASE + 0x3C));
-}
-
-/* Configure PLL/PFD freq */
-void clock_init(void)
-{
- /*
- * ROM has enabled clocks:
- * A4 side: SIRC 16Mhz (DIV1-3 off), FIRC 48Mhz (DIV1-2 on),
- * Non-LP-boot: SOSC, SPLL PFD0 (scs selected)
- * A7 side: SPLL PFD0 (scs selected, 413Mhz),
- * APLL PFD0 (352Mhz), DDRCLK, all NIC clocks
- * A7 Plat0 (NIC0) = 176Mhz, Plat1 (NIC1) = 176Mhz,
- * IP BUS (NIC1_BUS) = 58.6Mhz
- *
- * In u-boot:
- * 1. Enable PFD1-3 of APLL for A7 side. Enable FIRC and DIVs.
- * 2. Enable USB PLL
- * 3. Init the clocks of peripherals used in u-boot bu
- * without set rate interface.The clocks for these
- * peripherals are enabled in this intialization.
- * 4.Other peripherals with set clock rate interface
- * does not be set in this function.
- */
-
- scg_a7_firc_init();
-
- scg_a7_soscdiv_init();
-
- /* APLL PFD1 = 270Mhz, PFD2=480Mhz, PFD3=800Mhz */
- scg_enable_pll_pfd(SCG_APLL_PFD1_CLK, 35);
- scg_enable_pll_pfd(SCG_APLL_PFD2_CLK, 20);
- scg_enable_pll_pfd(SCG_APLL_PFD3_CLK, 12);
-
- init_clk_lpuart();
-
- init_clk_rgpio2p();
-
- enable_usboh3_clk(1);
-}
-
-#ifdef CONFIG_SECURE_BOOT
-void hab_caam_clock_enable(unsigned char enable)
-{
- if (enable)
- pcc_clock_enable(PER_CLK_CAAM, true);
- else
- pcc_clock_enable(PER_CLK_CAAM, false);
-}
-#endif
-
-/*
- * Dump some core clockes.
- */
-int do_mx7_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- u32 addr = 0;
- u32 freq;
- freq = decode_pll(PLL_A7_SPLL);
- printf("PLL_A7_SPLL %8d MHz\n", freq / 1000000);
-
- freq = decode_pll(PLL_A7_APLL);
- printf("PLL_A7_APLL %8d MHz\n", freq / 1000000);
-
- freq = decode_pll(PLL_USB);
- printf("PLL_USB %8d MHz\n", freq / 1000000);
-
- printf("\n");
-
- printf("CORE %8d kHz\n", scg_clk_get_rate(SCG_CORE_CLK) / 1000);
- printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
- printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
- printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
- printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
- printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
- printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
- printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
- printf("I2C4 %8d kHz\n", mxc_get_clock(MXC_I2C_CLK) / 1000);
-
- addr = (u32) clock_init;
- printf("[%s] addr = 0x%08X\r\n", __func__, addr);
- scg_a7_info();
-
- return 0;
-}
-
-U_BOOT_CMD(
- clocks, CONFIG_SYS_MAXARGS, 1, do_mx7_showclocks,
- "display clocks",
- ""
-);
+++ /dev/null
-/*
- * Copyright (C) 2016 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-
-static void *base = (void *)IOMUXC_BASE_ADDR;
-
-/*
- * iomuxc0 base address. In imx7ulp-pins.h,
- * the offsets of pins in iomuxc0 are from 0xD000,
- * so we set the base address to (0x4103D000 - 0xD000 = 0x41030000)
- */
-static void *base_mports = (void *)(AIPS0_BASE + 0x30000);
-
-/*
- * configures a single pad in the iomuxer
- */
-void mx7ulp_iomux_setup_pad(iomux_cfg_t pad)
-{
- u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
- u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
- u32 sel_input_ofs =
- (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
- u32 sel_input =
- (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
- u32 pad_ctrl_ofs = mux_ctrl_ofs;
- u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
-
- debug("[PAD CFG] = 0x%16llX \r\n\tmux_ctl = 0x%X(0x%X) sel_input = 0x%X(0x%X) pad_ctrl = 0x%X(0x%X)\r\n",
- pad, mux_ctrl_ofs, mux_mode, sel_input_ofs, sel_input,
- pad_ctrl_ofs, pad_ctrl);
-
- if (mux_mode & IOMUX_CONFIG_MPORTS) {
- mux_mode &= ~IOMUX_CONFIG_MPORTS;
- base = base_mports;
- } else {
- base = (void *)IOMUXC_BASE_ADDR;
- }
-
- __raw_writel(((mux_mode << IOMUXC_PCR_MUX_ALT_SHIFT) &
- IOMUXC_PCR_MUX_ALT_MASK), base + mux_ctrl_ofs);
-
- if (sel_input_ofs)
- __raw_writel((sel_input << IOMUXC_PSMI_IMUX_ALT_SHIFT),
- base + sel_input_ofs);
-
- if (!(pad_ctrl & NO_PAD_CTRL))
- __raw_writel(((mux_mode << IOMUXC_PCR_MUX_ALT_SHIFT) &
- IOMUXC_PCR_MUX_ALT_MASK) |
- (pad_ctrl & (~IOMUXC_PCR_MUX_ALT_MASK)),
- base + pad_ctrl_ofs);
-}
-
-/* configures a list of pads within declared with IOMUX_PADS macro */
-void mx7ulp_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list,
- unsigned count)
-{
- iomux_cfg_t const *p = pad_list;
- int i;
-
- for (i = 0; i < count; i++) {
- mx7ulp_iomux_setup_pad(*p);
- p++;
- }
-}
+++ /dev/null
-/*
- * Copyright (C) 2016 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <div64.h>
-#include <asm/io.h>
-#include <errno.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/pcc.h>
-#include <asm/arch/sys_proto.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define PCC_CLKSRC_TYPES 2
-#define PCC_CLKSRC_NUM 7
-
-static enum scg_clk pcc_clksrc[PCC_CLKSRC_TYPES][PCC_CLKSRC_NUM] = {
- { SCG_NIC1_BUS_CLK,
- SCG_NIC1_CLK,
- SCG_DDR_CLK,
- SCG_APLL_PFD2_CLK,
- SCG_APLL_PFD1_CLK,
- SCG_APLL_PFD0_CLK,
- USB_PLL_OUT,
- },
- { SCG_SOSC_DIV2_CLK, /* SOSC BUS clock */
- MIPI_PLL_OUT,
- SCG_FIRC_DIV2_CLK, /* FIRC BUS clock */
- SCG_ROSC_CLK,
- SCG_NIC1_BUS_CLK,
- SCG_NIC1_CLK,
- SCG_APLL_PFD3_CLK,
- },
-};
-
-static struct pcc_entry pcc_arrays[] = {
- {PCC2_RBASE, DMA1_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
- {PCC2_RBASE, RGPIO1_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
- {PCC2_RBASE, FLEXBUS0_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
- {PCC2_RBASE, SEMA42_1_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
- {PCC2_RBASE, DMA1_CH_MUX0_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
- {PCC2_RBASE, SNVS_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
- {PCC2_RBASE, CAAM_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
- {PCC2_RBASE, LPTPM4_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
- {PCC2_RBASE, LPTPM5_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
- {PCC2_RBASE, LPIT1_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
- {PCC2_RBASE, LPSPI2_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
- {PCC2_RBASE, LPSPI3_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
- {PCC2_RBASE, LPI2C4_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
- {PCC2_RBASE, LPI2C5_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
- {PCC2_RBASE, LPUART4_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
- {PCC2_RBASE, LPUART5_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
- {PCC2_RBASE, FLEXIO1_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
- {PCC2_RBASE, USBOTG0_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
- {PCC2_RBASE, USBOTG1_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
- {PCC2_RBASE, USBPHY_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
- {PCC2_RBASE, USB_PL301_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
- {PCC2_RBASE, USDHC0_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
- {PCC2_RBASE, USDHC1_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
- {PCC2_RBASE, WDG1_PCC2_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV},
- {PCC2_RBASE, WDG2_PCC2_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV},
-
- {PCC3_RBASE, LPTPM6_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
- {PCC3_RBASE, LPTPM7_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
- {PCC3_RBASE, LPI2C6_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
- {PCC3_RBASE, LPI2C7_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
- {PCC3_RBASE, LPUART6_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
- {PCC3_RBASE, LPUART7_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
- {PCC3_RBASE, VIU0_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
- {PCC3_RBASE, DSI0_PCC3_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV},
- {PCC3_RBASE, LCDIF0_PCC3_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
- {PCC3_RBASE, MMDC0_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
- {PCC3_RBASE, PORTC_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
- {PCC3_RBASE, PORTD_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
- {PCC3_RBASE, PORTE_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
- {PCC3_RBASE, PORTF_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
- {PCC3_RBASE, GPU3D_PCC3_SLOT, CLKSRC_PER_PLAT, PCC_NO_DIV},
- {PCC3_RBASE, GPU2D_PCC3_SLOT, CLKSRC_PER_PLAT, PCC_NO_DIV},
-};
-
-int pcc_clock_enable(enum pcc_clk clk, bool enable)
-{
- u32 reg, val;
-
- if (clk >= ARRAY_SIZE(pcc_arrays))
- return -EINVAL;
-
- reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
-
- val = readl(reg);
-
- clk_debug("pcc_clock_enable: clk %d, reg 0x%x, val 0x%x, enable %d\n",
- clk, reg, val, enable);
-
- if (!(val & PCC_PR_MASK) || (val & PCC_INUSE_MASK))
- return -EPERM;
-
- if (enable)
- val |= PCC_CGC_MASK;
- else
- val &= ~PCC_CGC_MASK;
-
- writel(val, reg);
-
- clk_debug("pcc_clock_enable: val 0x%x\n", val);
-
- return 0;
-}
-
-/* The clock source select needs clock is disabled */
-int pcc_clock_sel(enum pcc_clk clk, enum scg_clk src)
-{
- u32 reg, val, i, clksrc_type;
-
- if (clk >= ARRAY_SIZE(pcc_arrays))
- return -EINVAL;
-
- clksrc_type = pcc_arrays[clk].clksrc;
- if (clksrc_type >= CLKSRC_NO_PCS) {
- printf("No PCS field for the PCC %d, clksrc type %d\n",
- clk, clksrc_type);
- return -EPERM;
- }
-
- for (i = 0; i < PCC_CLKSRC_NUM; i++) {
- if (pcc_clksrc[clksrc_type][i] == src) {
- /* Find the clock src, then set it to PCS */
- break;
- }
- }
-
- if (i == PCC_CLKSRC_NUM) {
- printf("Not find the parent scg_clk in PCS of PCC %d, invalid scg_clk %d\n", clk, src);
- return -EINVAL;
- }
-
- reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
-
- val = readl(reg);
-
- clk_debug("pcc_clock_sel: clk %d, reg 0x%x, val 0x%x, clksrc_type %d\n",
- clk, reg, val, clksrc_type);
-
- if (!(val & PCC_PR_MASK) || (val & PCC_INUSE_MASK) ||
- (val & PCC_CGC_MASK)) {
- printf("Not permit to select clock source val = 0x%x\n", val);
- return -EPERM;
- }
-
- val &= ~PCC_PCS_MASK;
- val |= ((i + 1) << PCC_PCS_OFFSET);
-
- writel(val, reg);
-
- clk_debug("pcc_clock_sel: val 0x%x\n", val);
-
- return 0;
-}
-
-int pcc_clock_div_config(enum pcc_clk clk, bool frac, u8 div)
-{
- u32 reg, val;
-
- if (clk >= ARRAY_SIZE(pcc_arrays) || div > 8 ||
- (div == 1 && frac != 0))
- return -EINVAL;
-
- if (pcc_arrays[clk].div >= PCC_NO_DIV) {
- printf("No DIV/FRAC field for the PCC %d\n", clk);
- return -EPERM;
- }
-
- reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
-
- val = readl(reg);
-
- if (!(val & PCC_PR_MASK) || (val & PCC_INUSE_MASK) ||
- (val & PCC_CGC_MASK)) {
- printf("Not permit to set div/frac val = 0x%x\n", val);
- return -EPERM;
- }
-
- if (frac)
- val |= PCC_FRAC_MASK;
- else
- val &= ~PCC_FRAC_MASK;
-
- val &= ~PCC_PCD_MASK;
- val |= (div - 1) & PCC_PCD_MASK;
-
- writel(val, reg);
-
- return 0;
-}
-
-bool pcc_clock_is_enable(enum pcc_clk clk)
-{
- u32 reg, val;
-
- if (clk >= ARRAY_SIZE(pcc_arrays))
- return -EINVAL;
-
- reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
- val = readl(reg);
-
- if ((val & PCC_INUSE_MASK) || (val & PCC_CGC_MASK))
- return true;
-
- return false;
-}
-
-int pcc_clock_get_clksrc(enum pcc_clk clk, enum scg_clk *src)
-{
- u32 reg, val, clksrc_type;
-
- if (clk >= ARRAY_SIZE(pcc_arrays))
- return -EINVAL;
-
- clksrc_type = pcc_arrays[clk].clksrc;
- if (clksrc_type >= CLKSRC_NO_PCS) {
- printf("No PCS field for the PCC %d, clksrc type %d\n",
- clk, clksrc_type);
- return -EPERM;
- }
-
- reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
-
- val = readl(reg);
-
- clk_debug("pcc_clock_get_clksrc: clk %d, reg 0x%x, val 0x%x, type %d\n",
- clk, reg, val, clksrc_type);
-
- if (!(val & PCC_PR_MASK)) {
- printf("This pcc slot is not present = 0x%x\n", val);
- return -EPERM;
- }
-
- val &= PCC_PCS_MASK;
- val = (val >> PCC_PCS_OFFSET);
-
- if (!val) {
- printf("Clock source is off\n");
- return -EIO;
- }
-
- *src = pcc_clksrc[clksrc_type][val - 1];
-
- clk_debug("pcc_clock_get_clksrc: parent scg clk %d\n", *src);
-
- return 0;
-}
-
-u32 pcc_clock_get_rate(enum pcc_clk clk)
-{
- u32 reg, val, rate, frac, div;
- enum scg_clk parent;
- int ret;
-
- ret = pcc_clock_get_clksrc(clk, &parent);
- if (ret)
- return 0;
-
- rate = scg_clk_get_rate(parent);
-
- clk_debug("pcc_clock_get_rate: parent rate %u\n", rate);
-
- if (pcc_arrays[clk].div == PCC_HAS_DIV) {
- reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
- val = readl(reg);
-
- frac = (val & PCC_FRAC_MASK) >> PCC_FRAC_OFFSET;
- div = (val & PCC_PCD_MASK) >> PCC_PCD_OFFSET;
-
- /*
- * Theoretically don't have overflow in the calc,
- * the rate won't exceed 2G
- */
- rate = rate * (frac + 1) / (div + 1);
- }
-
- clk_debug("pcc_clock_get_rate: rate %u\n", rate);
- return rate;
-}
+++ /dev/null
-/*
- * Copyright (C) 2016 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <div64.h>
-#include <asm/io.h>
-#include <errno.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/pcc.h>
-#include <asm/arch/sys_proto.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-scg_p scg1_regs = (scg_p)SCG1_RBASE;
-
-static u32 scg_src_get_rate(enum scg_clk clksrc)
-{
- u32 reg;
-
- switch (clksrc) {
- case SCG_SOSC_CLK:
- reg = readl(&scg1_regs->sosccsr);
- if (!(reg & SCG_SOSC_CSR_SOSCVLD_MASK))
- return 0;
-
- return 24000000;
- case SCG_FIRC_CLK:
- reg = readl(&scg1_regs->firccsr);
- if (!(reg & SCG_FIRC_CSR_FIRCVLD_MASK))
- return 0;
-
- return 48000000;
- case SCG_SIRC_CLK:
- reg = readl(&scg1_regs->sirccsr);
- if (!(reg & SCG_SIRC_CSR_SIRCVLD_MASK))
- return 0;
-
- return 16000000;
- case SCG_ROSC_CLK:
- reg = readl(&scg1_regs->rtccsr);
- if (!(reg & SCG_ROSC_CSR_ROSCVLD_MASK))
- return 0;
-
- return 32768;
- default:
- break;
- }
-
- return 0;
-}
-
-static u32 scg_sircdiv_get_rate(enum scg_clk clk)
-{
- u32 reg, val, rate;
- u32 shift, mask;
-
- switch (clk) {
- case SCG_SIRC_DIV1_CLK:
- mask = SCG_SIRCDIV_DIV1_MASK;
- shift = SCG_SIRCDIV_DIV1_SHIFT;
- break;
- case SCG_SIRC_DIV2_CLK:
- mask = SCG_SIRCDIV_DIV2_MASK;
- shift = SCG_SIRCDIV_DIV2_SHIFT;
- break;
- case SCG_SIRC_DIV3_CLK:
- mask = SCG_SIRCDIV_DIV3_MASK;
- shift = SCG_SIRCDIV_DIV3_SHIFT;
- break;
- default:
- return 0;
- }
-
- reg = readl(&scg1_regs->sirccsr);
- if (!(reg & SCG_SIRC_CSR_SIRCVLD_MASK))
- return 0;
-
- reg = readl(&scg1_regs->sircdiv);
- val = (reg & mask) >> shift;
-
- if (!val) /*clock disabled*/
- return 0;
-
- rate = scg_src_get_rate(SCG_SIRC_CLK);
- rate = rate / (1 << (val - 1));
-
- return rate;
-}
-
-static u32 scg_fircdiv_get_rate(enum scg_clk clk)
-{
- u32 reg, val, rate;
- u32 shift, mask;
-
- switch (clk) {
- case SCG_FIRC_DIV1_CLK:
- mask = SCG_FIRCDIV_DIV1_MASK;
- shift = SCG_FIRCDIV_DIV1_SHIFT;
- break;
- case SCG_FIRC_DIV2_CLK:
- mask = SCG_FIRCDIV_DIV2_MASK;
- shift = SCG_FIRCDIV_DIV2_SHIFT;
- break;
- case SCG_FIRC_DIV3_CLK:
- mask = SCG_FIRCDIV_DIV3_MASK;
- shift = SCG_FIRCDIV_DIV3_SHIFT;
- break;
- default:
- return 0;
- }
-
- reg = readl(&scg1_regs->firccsr);
- if (!(reg & SCG_FIRC_CSR_FIRCVLD_MASK))
- return 0;
-
- reg = readl(&scg1_regs->fircdiv);
- val = (reg & mask) >> shift;
-
- if (!val) /*clock disabled*/
- return 0;
-
- rate = scg_src_get_rate(SCG_FIRC_CLK);
- rate = rate / (1 << (val - 1));
-
- return rate;
-}
-
-static u32 scg_soscdiv_get_rate(enum scg_clk clk)
-{
- u32 reg, val, rate;
- u32 shift, mask;
-
- switch (clk) {
- case SCG_SOSC_DIV1_CLK:
- mask = SCG_SOSCDIV_DIV1_MASK;
- shift = SCG_SOSCDIV_DIV1_SHIFT;
- break;
- case SCG_SOSC_DIV2_CLK:
- mask = SCG_SOSCDIV_DIV2_MASK;
- shift = SCG_SOSCDIV_DIV2_SHIFT;
- break;
- case SCG_SOSC_DIV3_CLK:
- mask = SCG_SOSCDIV_DIV3_MASK;
- shift = SCG_SOSCDIV_DIV3_SHIFT;
- break;
- default:
- return 0;
- }
-
- reg = readl(&scg1_regs->sosccsr);
- if (!(reg & SCG_SOSC_CSR_SOSCVLD_MASK))
- return 0;
-
- reg = readl(&scg1_regs->soscdiv);
- val = (reg & mask) >> shift;
-
- if (!val) /*clock disabled*/
- return 0;
-
- rate = scg_src_get_rate(SCG_SOSC_CLK);
- rate = rate / (1 << (val - 1));
-
- return rate;
-}
-
-static u32 scg_apll_pfd_get_rate(enum scg_clk clk)
-{
- u32 reg, val, rate;
- u32 shift, mask, gate, valid;
-
- switch (clk) {
- case SCG_APLL_PFD0_CLK:
- gate = SCG_PLL_PFD0_GATE_MASK;
- valid = SCG_PLL_PFD0_VALID_MASK;
- mask = SCG_PLL_PFD0_FRAC_MASK;
- shift = SCG_PLL_PFD0_FRAC_SHIFT;
- break;
- case SCG_APLL_PFD1_CLK:
- gate = SCG_PLL_PFD1_GATE_MASK;
- valid = SCG_PLL_PFD1_VALID_MASK;
- mask = SCG_PLL_PFD1_FRAC_MASK;
- shift = SCG_PLL_PFD1_FRAC_SHIFT;
- break;
- case SCG_APLL_PFD2_CLK:
- gate = SCG_PLL_PFD2_GATE_MASK;
- valid = SCG_PLL_PFD2_VALID_MASK;
- mask = SCG_PLL_PFD2_FRAC_MASK;
- shift = SCG_PLL_PFD2_FRAC_SHIFT;
- break;
- case SCG_APLL_PFD3_CLK:
- gate = SCG_PLL_PFD3_GATE_MASK;
- valid = SCG_PLL_PFD3_VALID_MASK;
- mask = SCG_PLL_PFD3_FRAC_MASK;
- shift = SCG_PLL_PFD3_FRAC_SHIFT;
- break;
- default:
- return 0;
- }
-
- reg = readl(&scg1_regs->apllpfd);
- if (reg & gate || !(reg & valid))
- return 0;
-
- clk_debug("scg_apll_pfd_get_rate reg 0x%x\n", reg);
-
- val = (reg & mask) >> shift;
- rate = decode_pll(PLL_A7_APLL);
-
- rate = rate / val * 18;
-
- clk_debug("scg_apll_pfd_get_rate rate %u\n", rate);
-
- return rate;
-}
-
-static u32 scg_spll_pfd_get_rate(enum scg_clk clk)
-{
- u32 reg, val, rate;
- u32 shift, mask, gate, valid;
-
- switch (clk) {
- case SCG_SPLL_PFD0_CLK:
- gate = SCG_PLL_PFD0_GATE_MASK;
- valid = SCG_PLL_PFD0_VALID_MASK;
- mask = SCG_PLL_PFD0_FRAC_MASK;
- shift = SCG_PLL_PFD0_FRAC_SHIFT;
- break;
- case SCG_SPLL_PFD1_CLK:
- gate = SCG_PLL_PFD1_GATE_MASK;
- valid = SCG_PLL_PFD1_VALID_MASK;
- mask = SCG_PLL_PFD1_FRAC_MASK;
- shift = SCG_PLL_PFD1_FRAC_SHIFT;
- break;
- case SCG_SPLL_PFD2_CLK:
- gate = SCG_PLL_PFD2_GATE_MASK;
- valid = SCG_PLL_PFD2_VALID_MASK;
- mask = SCG_PLL_PFD2_FRAC_MASK;
- shift = SCG_PLL_PFD2_FRAC_SHIFT;
- break;
- case SCG_SPLL_PFD3_CLK:
- gate = SCG_PLL_PFD3_GATE_MASK;
- valid = SCG_PLL_PFD3_VALID_MASK;
- mask = SCG_PLL_PFD3_FRAC_MASK;
- shift = SCG_PLL_PFD3_FRAC_SHIFT;
- break;
- default:
- return 0;
- }
-
- reg = readl(&scg1_regs->spllpfd);
- if (reg & gate || !(reg & valid))
- return 0;
-
- clk_debug("scg_spll_pfd_get_rate reg 0x%x\n", reg);
-
- val = (reg & mask) >> shift;
- rate = decode_pll(PLL_A7_SPLL);
-
- rate = rate / val * 18;
-
- clk_debug("scg_spll_pfd_get_rate rate %u\n", rate);
-
- return rate;
-}
-
-static u32 scg_apll_get_rate(void)
-{
- u32 reg, val, rate;
-
- reg = readl(&scg1_regs->apllcfg);
- val = (reg & SCG_PLL_CFG_PLLSEL_MASK) >> SCG_PLL_CFG_PLLSEL_SHIFT;
-
- if (!val) {
- /* APLL clock after two dividers */
- rate = decode_pll(PLL_A7_APLL);
-
- val = (reg & SCG_PLL_CFG_POSTDIV1_MASK) >>
- SCG_PLL_CFG_POSTDIV1_SHIFT;
- rate = rate / (val + 1);
-
- val = (reg & SCG_PLL_CFG_POSTDIV2_MASK) >>
- SCG_PLL_CFG_POSTDIV2_SHIFT;
- rate = rate / (val + 1);
- } else {
- /* APLL PFD clock */
- val = (reg & SCG_PLL_CFG_PFDSEL_MASK) >>
- SCG_PLL_CFG_PFDSEL_SHIFT;
- rate = scg_apll_pfd_get_rate(SCG_APLL_PFD0_CLK + val);
- }
-
- return rate;
-}
-
-static u32 scg_spll_get_rate(void)
-{
- u32 reg, val, rate;
-
- reg = readl(&scg1_regs->spllcfg);
- val = (reg & SCG_PLL_CFG_PLLSEL_MASK) >> SCG_PLL_CFG_PLLSEL_SHIFT;
-
- clk_debug("scg_spll_get_rate reg 0x%x\n", reg);
-
- if (!val) {
- /* APLL clock after two dividers */
- rate = decode_pll(PLL_A7_SPLL);
-
- val = (reg & SCG_PLL_CFG_POSTDIV1_MASK) >>
- SCG_PLL_CFG_POSTDIV1_SHIFT;
- rate = rate / (val + 1);
-
- val = (reg & SCG_PLL_CFG_POSTDIV2_MASK) >>
- SCG_PLL_CFG_POSTDIV2_SHIFT;
- rate = rate / (val + 1);
-
- clk_debug("scg_spll_get_rate SPLL %u\n", rate);
-
- } else {
- /* APLL PFD clock */
- val = (reg & SCG_PLL_CFG_PFDSEL_MASK) >>
- SCG_PLL_CFG_PFDSEL_SHIFT;
- rate = scg_spll_pfd_get_rate(SCG_SPLL_PFD0_CLK + val);
-
- clk_debug("scg_spll_get_rate PFD %u\n", rate);
- }
-
- return rate;
-}
-
-static u32 scg_ddr_get_rate(void)
-{
- u32 reg, val, rate, div;
-
- reg = readl(&scg1_regs->ddrccr);
- val = (reg & SCG_DDRCCR_DDRCS_MASK) >> SCG_DDRCCR_DDRCS_SHIFT;
- div = (reg & SCG_DDRCCR_DDRDIV_MASK) >> SCG_DDRCCR_DDRDIV_SHIFT;
-
- if (!div)
- return 0;
-
- if (!val) {
- reg = readl(&scg1_regs->apllcfg);
- val = (reg & SCG_PLL_CFG_PFDSEL_MASK) >>
- SCG_PLL_CFG_PFDSEL_SHIFT;
- rate = scg_apll_pfd_get_rate(SCG_APLL_PFD0_CLK + val);
- } else {
- rate = decode_pll(PLL_USB);
- }
-
- rate = rate / (1 << (div - 1));
- return rate;
-}
-
-static u32 scg_nic_get_rate(enum scg_clk clk)
-{
- u32 reg, val, rate;
- u32 shift, mask;
-
- reg = readl(&scg1_regs->niccsr);
- val = (reg & SCG_NICCSR_NICCS_MASK) >> SCG_NICCSR_NICCS_SHIFT;
-
- clk_debug("scg_nic_get_rate niccsr 0x%x\n", reg);
-
- if (!val)
- rate = scg_src_get_rate(SCG_FIRC_CLK);
- else
- rate = scg_ddr_get_rate();
-
- clk_debug("scg_nic_get_rate parent rate %u\n", rate);
-
- val = (reg & SCG_NICCSR_NIC0DIV_MASK) >> SCG_NICCSR_NIC0DIV_SHIFT;
-
- rate = rate / (val + 1);
-
- clk_debug("scg_nic_get_rate NIC0 rate %u\n", rate);
-
- switch (clk) {
- case SCG_NIC0_CLK:
- return rate;
- case SCG_GPU_CLK:
- mask = SCG_NICCSR_GPUDIV_MASK;
- shift = SCG_NICCSR_GPUDIV_SHIFT;
- break;
- case SCG_NIC1_EXT_CLK:
- case SCG_NIC1_BUS_CLK:
- case SCG_NIC1_CLK:
- mask = SCG_NICCSR_NIC1DIV_MASK;
- shift = SCG_NICCSR_NIC1DIV_SHIFT;
- break;
- default:
- return 0;
- }
-
- val = (reg & mask) >> shift;
- rate = rate / (val + 1);
-
- clk_debug("scg_nic_get_rate NIC1 rate %u\n", rate);
-
- switch (clk) {
- case SCG_GPU_CLK:
- case SCG_NIC1_CLK:
- return rate;
- case SCG_NIC1_EXT_CLK:
- mask = SCG_NICCSR_NIC1EXTDIV_MASK;
- shift = SCG_NICCSR_NIC1EXTDIV_SHIFT;
- break;
- case SCG_NIC1_BUS_CLK:
- mask = SCG_NICCSR_NIC1BUSDIV_MASK;
- shift = SCG_NICCSR_NIC1BUSDIV_SHIFT;
- break;
- default:
- return 0;
- }
-
- val = (reg & mask) >> shift;
- rate = rate / (val + 1);
-
- clk_debug("scg_nic_get_rate NIC1 bus rate %u\n", rate);
- return rate;
-}
-
-
-static enum scg_clk scg_scs_array[4] = {
- SCG_SOSC_CLK, SCG_SIRC_CLK, SCG_FIRC_CLK, SCG_ROSC_CLK,
-};
-
-static u32 scg_sys_get_rate(enum scg_clk clk)
-{
- u32 reg, val, rate;
-
- if (clk != SCG_CORE_CLK && clk != SCG_BUS_CLK)
- return 0;
-
- reg = readl(&scg1_regs->csr);
- val = (reg & SCG_CCR_SCS_MASK) >> SCG_CCR_SCS_SHIFT;
-
- clk_debug("scg_sys_get_rate reg 0x%x\n", reg);
-
- switch (val) {
- case SCG_SCS_SYS_OSC:
- case SCG_SCS_SLOW_IRC:
- case SCG_SCS_FAST_IRC:
- case SCG_SCS_RTC_OSC:
- rate = scg_src_get_rate(scg_scs_array[val]);
- break;
- case 5:
- rate = scg_apll_get_rate();
- break;
- case 6:
- rate = scg_spll_get_rate();
- break;
- default:
- return 0;
- }
-
- clk_debug("scg_sys_get_rate parent rate %u\n", rate);
-
- val = (reg & SCG_CCR_DIVCORE_MASK) >> SCG_CCR_DIVCORE_SHIFT;
-
- rate = rate / (val + 1);
-
- if (clk == SCG_BUS_CLK) {
- val = (reg & SCG_CCR_DIVBUS_MASK) >> SCG_CCR_DIVBUS_SHIFT;
- rate = rate / (val + 1);
- }
-
- return rate;
-}
-
-u32 decode_pll(enum pll_clocks pll)
-{
- u32 reg, pre_div, infreq, mult;
- u32 num, denom;
-
- /*
- * Alought there are four choices for the bypass src,
- * we choose OSC_24M which is the default set in ROM.
- */
- switch (pll) {
- case PLL_A7_SPLL:
- reg = readl(&scg1_regs->spllcsr);
-
- if (!(reg & SCG_SPLL_CSR_SPLLVLD_MASK))
- return 0;
-
- reg = readl(&scg1_regs->spllcfg);
-
- pre_div = (reg & SCG_PLL_CFG_PREDIV_MASK) >>
- SCG_PLL_CFG_PREDIV_SHIFT;
- pre_div += 1;
-
- mult = (reg & SCG1_SPLL_CFG_MULT_MASK) >>
- SCG_PLL_CFG_MULT_SHIFT;
-
- infreq = (reg & SCG_PLL_CFG_CLKSRC_MASK) >>
- SCG_PLL_CFG_CLKSRC_SHIFT;
- if (!infreq)
- infreq = scg_src_get_rate(SCG_SOSC_CLK);
- else
- infreq = scg_src_get_rate(SCG_FIRC_CLK);
-
- num = readl(&scg1_regs->spllnum);
- denom = readl(&scg1_regs->splldenom);
-
- infreq = infreq / pre_div;
-
- return infreq * mult + infreq * num / denom;
-
- case PLL_A7_APLL:
- reg = readl(&scg1_regs->apllcsr);
-
- if (!(reg & SCG_APLL_CSR_APLLVLD_MASK))
- return 0;
-
- reg = readl(&scg1_regs->apllcfg);
-
- pre_div = (reg & SCG_PLL_CFG_PREDIV_MASK) >>
- SCG_PLL_CFG_PREDIV_SHIFT;
- pre_div += 1;
-
- mult = (reg & SCG_APLL_CFG_MULT_MASK) >>
- SCG_PLL_CFG_MULT_SHIFT;
-
- infreq = (reg & SCG_PLL_CFG_CLKSRC_MASK) >>
- SCG_PLL_CFG_CLKSRC_SHIFT;
- if (!infreq)
- infreq = scg_src_get_rate(SCG_SOSC_CLK);
- else
- infreq = scg_src_get_rate(SCG_FIRC_CLK);
-
- num = readl(&scg1_regs->apllnum);
- denom = readl(&scg1_regs->aplldenom);
-
- infreq = infreq / pre_div;
-
- return infreq * mult + infreq * num / denom;
-
- case PLL_USB:
- reg = readl(&scg1_regs->upllcsr);
-
- if (!(reg & SCG_UPLL_CSR_UPLLVLD_MASK))
- return 0;
-
- return 480000000u;
-
- case PLL_MIPI:
- return 480000000u;
- default:
- printf("Unsupported pll clocks %d\n", pll);
- break;
- }
-
- return 0;
-}
-
-u32 scg_clk_get_rate(enum scg_clk clk)
-{
- switch (clk) {
- case SCG_SIRC_DIV1_CLK:
- case SCG_SIRC_DIV2_CLK:
- case SCG_SIRC_DIV3_CLK:
- return scg_sircdiv_get_rate(clk);
-
- case SCG_FIRC_DIV1_CLK:
- case SCG_FIRC_DIV2_CLK:
- case SCG_FIRC_DIV3_CLK:
- return scg_fircdiv_get_rate(clk);
-
- case SCG_SOSC_DIV1_CLK:
- case SCG_SOSC_DIV2_CLK:
- case SCG_SOSC_DIV3_CLK:
- return scg_soscdiv_get_rate(clk);
-
- case SCG_CORE_CLK:
- case SCG_BUS_CLK:
- return scg_sys_get_rate(clk);
-
- case SCG_SPLL_PFD0_CLK:
- case SCG_SPLL_PFD1_CLK:
- case SCG_SPLL_PFD2_CLK:
- case SCG_SPLL_PFD3_CLK:
- return scg_spll_pfd_get_rate(clk);
-
- case SCG_APLL_PFD0_CLK:
- case SCG_APLL_PFD1_CLK:
- case SCG_APLL_PFD2_CLK:
- case SCG_APLL_PFD3_CLK:
- return scg_apll_pfd_get_rate(clk);
-
- case SCG_DDR_CLK:
- return scg_ddr_get_rate();
-
- case SCG_NIC0_CLK:
- case SCG_GPU_CLK:
- case SCG_NIC1_CLK:
- case SCG_NIC1_BUS_CLK:
- case SCG_NIC1_EXT_CLK:
- return scg_nic_get_rate(clk);
-
- case USB_PLL_OUT:
- return decode_pll(PLL_USB);
-
- case MIPI_PLL_OUT:
- return decode_pll(PLL_MIPI);
-
- case SCG_SOSC_CLK:
- case SCG_FIRC_CLK:
- case SCG_SIRC_CLK:
- case SCG_ROSC_CLK:
- return scg_src_get_rate(clk);
- default:
- return 0;
- }
-}
-
-int scg_enable_pll_pfd(enum scg_clk clk, u32 frac)
-{
- u32 reg;
- u32 shift, mask, gate, valid;
- u32 addr;
-
- if (frac < 12 || frac > 35)
- return -EINVAL;
-
- switch (clk) {
- case SCG_SPLL_PFD0_CLK:
- case SCG_APLL_PFD0_CLK:
- gate = SCG_PLL_PFD0_GATE_MASK;
- valid = SCG_PLL_PFD0_VALID_MASK;
- mask = SCG_PLL_PFD0_FRAC_MASK;
- shift = SCG_PLL_PFD0_FRAC_SHIFT;
-
- if (clk == SCG_SPLL_PFD0_CLK)
- addr = (u32)(&scg1_regs->spllpfd);
- else
- addr = (u32)(&scg1_regs->apllpfd);
- break;
- case SCG_SPLL_PFD1_CLK:
- case SCG_APLL_PFD1_CLK:
- gate = SCG_PLL_PFD1_GATE_MASK;
- valid = SCG_PLL_PFD1_VALID_MASK;
- mask = SCG_PLL_PFD1_FRAC_MASK;
- shift = SCG_PLL_PFD1_FRAC_SHIFT;
-
- if (clk == SCG_SPLL_PFD1_CLK)
- addr = (u32)(&scg1_regs->spllpfd);
- else
- addr = (u32)(&scg1_regs->apllpfd);
- break;
- case SCG_SPLL_PFD2_CLK:
- case SCG_APLL_PFD2_CLK:
- gate = SCG_PLL_PFD2_GATE_MASK;
- valid = SCG_PLL_PFD2_VALID_MASK;
- mask = SCG_PLL_PFD2_FRAC_MASK;
- shift = SCG_PLL_PFD2_FRAC_SHIFT;
-
- if (clk == SCG_SPLL_PFD2_CLK)
- addr = (u32)(&scg1_regs->spllpfd);
- else
- addr = (u32)(&scg1_regs->apllpfd);
- break;
- case SCG_SPLL_PFD3_CLK:
- case SCG_APLL_PFD3_CLK:
- gate = SCG_PLL_PFD3_GATE_MASK;
- valid = SCG_PLL_PFD3_VALID_MASK;
- mask = SCG_PLL_PFD3_FRAC_MASK;
- shift = SCG_PLL_PFD3_FRAC_SHIFT;
-
- if (clk == SCG_SPLL_PFD3_CLK)
- addr = (u32)(&scg1_regs->spllpfd);
- else
- addr = (u32)(&scg1_regs->apllpfd);
- break;
- default:
- return -EINVAL;
- }
-
- /* Gate the PFD */
- reg = readl(addr);
- reg |= gate;
- writel(reg, addr);
-
- /* Write Frac divider */
- reg &= ~mask;
- reg |= (frac << shift) & mask;
- writel(reg, addr);
-
- /*
- * Un-gate the PFD
- * (Need un-gate before checking valid, not align with RM)
- */
- reg &= ~gate;
- writel(reg, addr);
-
- /* Wait for PFD clock being valid */
- do {
- reg = readl(addr);
- } while (!(reg & valid));
-
- return 0;
-}
-
-#define SIM_MISC_CTRL0_USB_PLL_EN_MASK (0x1 << 2)
-int scg_enable_usb_pll(bool usb_control)
-{
- u32 sosc_rate;
- s32 timeout = 1000000;
- u32 reg;
-
- struct usbphy_regs *usbphy =
- (struct usbphy_regs *)USBPHY_RBASE;
-
- sosc_rate = scg_src_get_rate(SCG_SOSC_CLK);
- if (!sosc_rate)
- return -EPERM;
-
- reg = readl(SIM0_RBASE + 0x3C);
- if (usb_control)
- reg &= ~SIM_MISC_CTRL0_USB_PLL_EN_MASK;
- else
- reg |= SIM_MISC_CTRL0_USB_PLL_EN_MASK;
- writel(reg, SIM0_RBASE + 0x3C);
-
- if (!(readl(&usbphy->usb1_pll_480_ctrl) & PLL_USB_LOCK_MASK)) {
- writel(0x1c00000, &usbphy->usb1_pll_480_ctrl_clr);
-
- switch (sosc_rate) {
- case 24000000:
- writel(0xc00000, &usbphy->usb1_pll_480_ctrl_set);
- break;
-
- case 30000000:
- writel(0x800000, &usbphy->usb1_pll_480_ctrl_set);
- break;
-
- case 19200000:
- writel(0x1400000, &usbphy->usb1_pll_480_ctrl_set);
- break;
-
- default:
- writel(0xc00000, &usbphy->usb1_pll_480_ctrl_set);
- break;
- }
-
- /* Enable the regulator first */
- writel(PLL_USB_REG_ENABLE_MASK,
- &usbphy->usb1_pll_480_ctrl_set);
-
- /* Wait at least 15us */
- udelay(15);
-
- /* Enable the power */
- writel(PLL_USB_PWR_MASK, &usbphy->usb1_pll_480_ctrl_set);
-
- /* Wait lock */
- while (timeout--) {
- if (readl(&usbphy->usb1_pll_480_ctrl) &
- PLL_USB_LOCK_MASK)
- break;
- }
-
- if (timeout <= 0) {
- /* If timeout, we power down the pll */
- writel(PLL_USB_PWR_MASK,
- &usbphy->usb1_pll_480_ctrl_clr);
- return -ETIME;
- }
- }
-
- /* Clear the bypass */
- writel(PLL_USB_BYPASS_MASK, &usbphy->usb1_pll_480_ctrl_clr);
-
- /* Enable the PLL clock out to USB */
- writel((PLL_USB_EN_USB_CLKS_MASK | PLL_USB_ENABLE_MASK),
- &usbphy->usb1_pll_480_ctrl_set);
-
- if (!usb_control) {
- while (timeout--) {
- if (readl(&scg1_regs->upllcsr) &
- SCG_UPLL_CSR_UPLLVLD_MASK)
- break;
- }
-
- if (timeout <= 0) {
- reg = readl(SIM0_RBASE + 0x3C);
- reg &= ~SIM_MISC_CTRL0_USB_PLL_EN_MASK;
- writel(reg, SIM0_RBASE + 0x3C);
- return -ETIME;
- }
- }
-
- return 0;
-}
-
-
-/* A7 domain system clock source is SPLL */
-#define SCG1_RCCR_SCS_NUM ((SCG_SCS_SYS_PLL) << SCG_CCR_SCS_SHIFT)
-
-/* A7 Core clck = SPLL PFD0 / 1 = 500MHz / 1 = 500MHz */
-#define SCG1_RCCR_DIVCORE_NUM ((0x0) << SCG_CCR_DIVCORE_SHIFT)
-#define SCG1_RCCR_CFG_MASK (SCG_CCR_SCS_MASK | SCG_CCR_DIVBUS_MASK)
-
-/* A7 Plat clck = A7 Core Clock / 2 = 250MHz / 1 = 250MHz */
-#define SCG1_RCCR_DIVBUS_NUM ((0x1) << SCG_CCR_DIVBUS_SHIFT)
-#define SCG1_RCCR_CFG_NUM (SCG1_RCCR_SCS_NUM | SCG1_RCCR_DIVBUS_NUM)
-
-void scg_a7_rccr_init(void)
-{
- u32 rccr_reg_val = 0;
-
- rccr_reg_val = readl(&scg1_regs->rccr);
-
- rccr_reg_val &= (~SCG1_RCCR_CFG_MASK);
- rccr_reg_val |= (SCG1_RCCR_CFG_NUM);
-
- writel(rccr_reg_val, &scg1_regs->rccr);
-}
-
-/* POSTDIV2 = 1 */
-#define SCG1_SPLL_CFG_POSTDIV2_NUM ((0x0) << SCG_PLL_CFG_POSTDIV2_SHIFT)
-/* POSTDIV1 = 1 */
-#define SCG1_SPLL_CFG_POSTDIV1_NUM ((0x0) << SCG_PLL_CFG_POSTDIV1_SHIFT)
-
-/* MULT = 22 */
-#define SCG1_SPLL_CFG_MULT_NUM ((22) << SCG_PLL_CFG_MULT_SHIFT)
-
-/* PFD0 output clock selected */
-#define SCG1_SPLL_CFG_PFDSEL_NUM ((0) << SCG_PLL_CFG_PFDSEL_SHIFT)
-/* PREDIV = 1 */
-#define SCG1_SPLL_CFG_PREDIV_NUM ((0x0) << SCG_PLL_CFG_PREDIV_SHIFT)
-/* SPLL output clocks (including PFD outputs) selected */
-#define SCG1_SPLL_CFG_BYPASS_NUM ((0x0) << SCG_PLL_CFG_BYPASS_SHIFT)
-/* SPLL PFD output clock selected */
-#define SCG1_SPLL_CFG_PLLSEL_NUM ((0x1) << SCG_PLL_CFG_PLLSEL_SHIFT)
-/* Clock source is System OSC */
-#define SCG1_SPLL_CFG_CLKSRC_NUM ((0x0) << SCG_PLL_CFG_CLKSRC_SHIFT)
-#define SCG1_SPLL_CFG_NUM_24M_OSC (SCG1_SPLL_CFG_POSTDIV2_NUM | \
- SCG1_SPLL_CFG_POSTDIV1_NUM | \
- (22 << SCG_PLL_CFG_MULT_SHIFT) | \
- SCG1_SPLL_CFG_PFDSEL_NUM | \
- SCG1_SPLL_CFG_PREDIV_NUM | \
- SCG1_SPLL_CFG_BYPASS_NUM | \
- SCG1_SPLL_CFG_PLLSEL_NUM | \
- SCG1_SPLL_CFG_CLKSRC_NUM)
-/*413Mhz = A7 SPLL(528MHz) * 18/23 */
-#define SCG1_SPLL_PFD0_FRAC_NUM ((23) << SCG_PLL_PFD0_FRAC_SHIFT)
-
-void scg_a7_spll_init(void)
-{
- u32 val = 0;
-
- /* Disable A7 System PLL */
- val = readl(&scg1_regs->spllcsr);
- val &= ~SCG_SPLL_CSR_SPLLEN_MASK;
- writel(val, &scg1_regs->spllcsr);
-
- /*
- * Per block guide,
- * "When changing PFD values, it is recommneded PFDx clock
- * gets gated first by writing a value of 1 to PFDx_CLKGATE register,
- * then program the new PFD value, then poll the PFDx_VALID
- * flag to set before writing a value of 0 to PFDx_CLKGATE
- * to ungate the PFDx clock and allow PFDx clock to run"
- */
-
- /* Gate off A7 SPLL PFD0 ~ PDF4 */
- val = readl(&scg1_regs->spllpfd);
- val |= (SCG_PLL_PFD3_GATE_MASK |
- SCG_PLL_PFD2_GATE_MASK |
- SCG_PLL_PFD1_GATE_MASK |
- SCG_PLL_PFD0_GATE_MASK);
- writel(val, &scg1_regs->spllpfd);
-
- /* ================ A7 SPLL Configuration Start ============== */
-
- /* Configure A7 System PLL */
- writel(SCG1_SPLL_CFG_NUM_24M_OSC, &scg1_regs->spllcfg);
-
- /* Enable A7 System PLL */
- val = readl(&scg1_regs->spllcsr);
- val |= SCG_SPLL_CSR_SPLLEN_MASK;
- writel(val, &scg1_regs->spllcsr);
-
- /* Wait for A7 SPLL clock ready */
- while (!(readl(&scg1_regs->spllcsr) & SCG_SPLL_CSR_SPLLVLD_MASK))
- ;
-
- /* Configure A7 SPLL PFD0 */
- val = readl(&scg1_regs->spllpfd);
- val &= ~SCG_PLL_PFD0_FRAC_MASK;
- val |= SCG1_SPLL_PFD0_FRAC_NUM;
- writel(val, &scg1_regs->spllpfd);
-
- /* Un-gate A7 SPLL PFD0 */
- val = readl(&scg1_regs->spllpfd);
- val &= ~SCG_PLL_PFD0_GATE_MASK;
- writel(val, &scg1_regs->spllpfd);
-
- /* Wait for A7 SPLL PFD0 clock being valid */
- while (!(readl(&scg1_regs->spllpfd) & SCG_PLL_PFD0_VALID_MASK))
- ;
-
- /* ================ A7 SPLL Configuration End ============== */
-}
-
-/* DDR clock source is APLL PFD0 (396MHz) */
-#define SCG1_DDRCCR_DDRCS_NUM ((0x0) << SCG_DDRCCR_DDRCS_SHIFT)
-/* DDR clock = APLL PFD0 / 1 = 396MHz / 1 = 396MHz */
-#define SCG1_DDRCCR_DDRDIV_NUM ((0x1) << SCG_DDRCCR_DDRDIV_SHIFT)
-/* DDR clock = APLL PFD0 / 2 = 396MHz / 2 = 198MHz */
-#define SCG1_DDRCCR_DDRDIV_LF_NUM ((0x2) << SCG_DDRCCR_DDRDIV_SHIFT)
-#define SCG1_DDRCCR_CFG_NUM (SCG1_DDRCCR_DDRCS_NUM | \
- SCG1_DDRCCR_DDRDIV_NUM)
-#define SCG1_DDRCCR_CFG_LF_NUM (SCG1_DDRCCR_DDRCS_NUM | \
- SCG1_DDRCCR_DDRDIV_LF_NUM)
-void scg_a7_ddrclk_init(void)
-{
- writel(SCG1_DDRCCR_CFG_NUM, &scg1_regs->ddrccr);
-}
-
-/* SCG1(A7) APLLCFG configurations */
-/* divide by 1 <<28 */
-#define SCG1_APLL_CFG_POSTDIV2_NUM ((0x0) << SCG_PLL_CFG_POSTDIV2_SHIFT)
-/* divide by 1 <<24 */
-#define SCG1_APLL_CFG_POSTDIV1_NUM ((0x0) << SCG_PLL_CFG_POSTDIV1_SHIFT)
-/* MULT is 22 <<16 */
-#define SCG1_APLL_CFG_MULT_NUM ((22) << SCG_PLL_CFG_MULT_SHIFT)
-/* PFD0 output clock selected <<14 */
-#define SCG1_APLL_CFG_PFDSEL_NUM ((0) << SCG_PLL_CFG_PFDSEL_SHIFT)
-/* PREDIV = 1 <<8 */
-#define SCG1_APLL_CFG_PREDIV_NUM ((0x0) << SCG_PLL_CFG_PREDIV_SHIFT)
-/* APLL output clocks (including PFD outputs) selected <<2 */
-#define SCG1_APLL_CFG_BYPASS_NUM ((0x0) << SCG_PLL_CFG_BYPASS_SHIFT)
-/* APLL PFD output clock selected <<1 */
-#define SCG1_APLL_CFG_PLLSEL_NUM ((0x0) << SCG_PLL_CFG_PLLSEL_SHIFT)
-/* Clock source is System OSC <<0 */
-#define SCG1_APLL_CFG_CLKSRC_NUM ((0x0) << SCG_PLL_CFG_CLKSRC_SHIFT)
-
-/*
- * A7 APLL = 24MHz / 1 * 22 / 1 / 1 = 528MHz,
- * system PLL is sourced from APLL,
- * APLL clock source is system OSC (24MHz)
- */
-#define SCG1_APLL_CFG_NUM_24M_OSC (SCG1_APLL_CFG_POSTDIV2_NUM | \
- SCG1_APLL_CFG_POSTDIV1_NUM | \
- (22 << SCG_PLL_CFG_MULT_SHIFT) | \
- SCG1_APLL_CFG_PFDSEL_NUM | \
- SCG1_APLL_CFG_PREDIV_NUM | \
- SCG1_APLL_CFG_BYPASS_NUM | \
- SCG1_APLL_CFG_PLLSEL_NUM | \
- SCG1_APLL_CFG_CLKSRC_NUM)
-
-/* PFD0 Freq = A7 APLL(528MHz) * 18 / 27 = 352MHz */
-#define SCG1_APLL_PFD0_FRAC_NUM (27)
-
-
-void scg_a7_apll_init(void)
-{
- u32 val = 0;
-
- /* Disable A7 Auxiliary PLL */
- val = readl(&scg1_regs->apllcsr);
- val &= ~SCG_APLL_CSR_APLLEN_MASK;
- writel(val, &scg1_regs->apllcsr);
-
- /* Gate off A7 APLL PFD0 ~ PDF4 */
- val = readl(&scg1_regs->apllpfd);
- val |= 0x80808080;
- writel(val, &scg1_regs->apllpfd);
-
- /* ================ A7 APLL Configuration Start ============== */
- /* Configure A7 Auxiliary PLL */
- writel(SCG1_APLL_CFG_NUM_24M_OSC, &scg1_regs->apllcfg);
-
- /* Enable A7 Auxiliary PLL */
- val = readl(&scg1_regs->apllcsr);
- val |= SCG_APLL_CSR_APLLEN_MASK;
- writel(val, &scg1_regs->apllcsr);
-
- /* Wait for A7 APLL clock ready */
- while (!(readl(&scg1_regs->apllcsr) & SCG_APLL_CSR_APLLVLD_MASK))
- ;
-
- /* Configure A7 APLL PFD0 */
- val = readl(&scg1_regs->apllpfd);
- val &= ~SCG_PLL_PFD0_FRAC_MASK;
- val |= SCG1_APLL_PFD0_FRAC_NUM;
- writel(val, &scg1_regs->apllpfd);
-
- /* Un-gate A7 APLL PFD0 */
- val = readl(&scg1_regs->apllpfd);
- val &= ~SCG_PLL_PFD0_GATE_MASK;
- writel(val, &scg1_regs->apllpfd);
-
- /* Wait for A7 APLL PFD0 clock being valid */
- while (!(readl(&scg1_regs->apllpfd) & SCG_PLL_PFD0_VALID_MASK))
- ;
-}
-
-/* SCG1(A7) FIRC DIV configurations */
-/* Disable FIRC DIV3 */
-#define SCG1_FIRCDIV_DIV3_NUM ((0x0) << SCG_FIRCDIV_DIV3_SHIFT)
-/* FIRC DIV2 = 48MHz / 1 = 48MHz */
-#define SCG1_FIRCDIV_DIV2_NUM ((0x1) << SCG_FIRCDIV_DIV2_SHIFT)
-/* Disable FIRC DIV1 */
-#define SCG1_FIRCDIV_DIV1_NUM ((0x0) << SCG_FIRCDIV_DIV1_SHIFT)
-
-void scg_a7_firc_init(void)
-{
- /* Wait for FIRC clock ready */
- while (!(readl(&scg1_regs->firccsr) & SCG_FIRC_CSR_FIRCVLD_MASK))
- ;
-
- /* Configure A7 FIRC DIV1 ~ DIV3 */
- writel((SCG1_FIRCDIV_DIV3_NUM |
- SCG1_FIRCDIV_DIV2_NUM |
- SCG1_FIRCDIV_DIV1_NUM), &scg1_regs->fircdiv);
-}
-
-/* SCG1(A7) NICCCR configurations */
-/* NIC clock source is DDR clock (396/198MHz) */
-#define SCG1_NICCCR_NICCS_NUM ((0x1) << SCG_NICCCR_NICCS_SHIFT)
-
-/* NIC0 clock = DDR Clock / 2 = 396MHz / 2 = 198MHz */
-#define SCG1_NICCCR_NIC0_DIV_NUM ((0x1) << SCG_NICCCR_NIC0_DIV_SHIFT)
-/* NIC0 clock = DDR Clock / 1 = 198MHz / 1 = 198MHz */
-#define SCG1_NICCCR_NIC0_DIV_LF_NUM ((0x0) << SCG_NICCCR_NIC0_DIV_SHIFT)
-/* NIC1 clock = NIC0 Clock / 1 = 198MHz / 2 = 198MHz */
-#define SCG1_NICCCR_NIC1_DIV_NUM ((0x0) << SCG_NICCCR_NIC1_DIV_SHIFT)
-/* NIC1 bus clock = NIC1 Clock / 3 = 198MHz / 3 = 66MHz */
-#define SCG1_NICCCR_NIC1_DIVBUS_NUM ((0x2) << SCG_NICCCR_NIC1_DIVBUS_SHIFT)
-#define SCG1_NICCCR_CFG_NUM (SCG1_NICCCR_NICCS_NUM | \
- SCG1_NICCCR_NIC0_DIV_NUM | \
- SCG1_NICCCR_NIC1_DIV_NUM | \
- SCG1_NICCCR_NIC1_DIVBUS_NUM)
-
-void scg_a7_nicclk_init(void)
-{
- writel(SCG1_NICCCR_CFG_NUM, &scg1_regs->nicccr);
-}
-
-/* SCG1(A7) FIRC DIV configurations */
-/* Enable FIRC DIV3 */
-#define SCG1_SOSCDIV_DIV3_NUM ((0x1) << SCG_SOSCDIV_DIV3_SHIFT)
-/* FIRC DIV2 = 48MHz / 1 = 48MHz */
-#define SCG1_SOSCDIV_DIV2_NUM ((0x1) << SCG_SOSCDIV_DIV2_SHIFT)
-/* Enable FIRC DIV1 */
-#define SCG1_SOSCDIV_DIV1_NUM ((0x1) << SCG_SOSCDIV_DIV1_SHIFT)
-
-void scg_a7_soscdiv_init(void)
-{
- /* Wait for FIRC clock ready */
- while (!(readl(&scg1_regs->sosccsr) & SCG_SOSC_CSR_SOSCVLD_MASK))
- ;
-
- /* Configure A7 FIRC DIV1 ~ DIV3 */
- writel((SCG1_SOSCDIV_DIV3_NUM | SCG1_SOSCDIV_DIV2_NUM |
- SCG1_SOSCDIV_DIV1_NUM), &scg1_regs->soscdiv);
-}
-
-void scg_a7_sys_clk_sel(enum scg_sys_src clk)
-{
- u32 rccr_reg_val = 0;
-
- clk_debug("%s: system clock selected as %s\n", "[SCG]",
- clk == SCG_SCS_SYS_OSC ? "SYS_OSC" :
- clk == SCG_SCS_SLOW_IRC ? "SLOW_IRC" :
- clk == SCG_SCS_FAST_IRC ? "FAST_IRC" :
- clk == SCG_SCS_RTC_OSC ? "RTC_OSC" :
- clk == SCG_SCS_AUX_PLL ? "AUX_PLL" :
- clk == SCG_SCS_SYS_PLL ? "SYS_PLL" :
- clk == SCG_SCS_USBPHY_PLL ? "USBPHY_PLL" :
- "Invalid source"
- );
-
- rccr_reg_val = readl(&scg1_regs->rccr);
- rccr_reg_val &= ~SCG_CCR_SCS_MASK;
- rccr_reg_val |= (clk << SCG_CCR_SCS_SHIFT);
- writel(rccr_reg_val, &scg1_regs->rccr);
-}
-
-void scg_a7_info(void)
-{
- debug("SCG Version: 0x%x\n", readl(&scg1_regs->verid));
- debug("SCG Parameter: 0x%x\n", readl(&scg1_regs->param));
- debug("SCG RCCR Value: 0x%x\n", readl(&scg1_regs->rccr));
- debug("SCG Clock Status: 0x%x\n", readl(&scg1_regs->csr));
-}
+++ /dev/null
-/*
- * Copyright (C) 2016 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/hab.h>
-
-static char *get_reset_cause(char *);
-
-#if defined(CONFIG_SECURE_BOOT)
-struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
- .bank = 29,
- .word = 6,
-};
-#endif
-
-u32 get_cpu_rev(void)
-{
- /* Temporally hard code the CPU rev to 0x73, rev 1.0. Fix it later */
- return (MXC_CPU_MX7ULP << 12) | (1 << 4);
-}
-
-#ifdef CONFIG_REVISION_TAG
-u32 __weak get_board_rev(void)
-{
- return get_cpu_rev();
-}
-#endif
-
-enum bt_mode get_boot_mode(void)
-{
- u32 bt0_cfg = 0;
-
- bt0_cfg = readl(CMC0_RBASE + 0x40);
- bt0_cfg &= (BT0CFG_LPBOOT_MASK | BT0CFG_DUALBOOT_MASK);
-
- if (!(bt0_cfg & BT0CFG_LPBOOT_MASK)) {
- /* No low power boot */
- if (bt0_cfg & BT0CFG_DUALBOOT_MASK)
- return DUAL_BOOT;
- else
- return SINGLE_BOOT;
- }
-
- return LOW_POWER_BOOT;
-}
-
-int arch_cpu_init(void)
-{
- return 0;
-}
-
-#ifdef CONFIG_BOARD_POSTCLK_INIT
-int board_postclk_init(void)
-{
- return 0;
-}
-#endif
-
-#define UNLOCK_WORD0 0xC520 /* 1st unlock word */
-#define UNLOCK_WORD1 0xD928 /* 2nd unlock word */
-#define REFRESH_WORD0 0xA602 /* 1st refresh word */
-#define REFRESH_WORD1 0xB480 /* 2nd refresh word */
-
-static void disable_wdog(u32 wdog_base)
-{
- writel(UNLOCK_WORD0, (wdog_base + 0x04));
- writel(UNLOCK_WORD1, (wdog_base + 0x04));
- writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */
- writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */
- writel(0x120, (wdog_base + 0x00)); /* Disable it and set update */
-
- writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */
- writel(REFRESH_WORD1, (wdog_base + 0x04));
-}
-
-void init_wdog(void)
-{
- /*
- * ROM will configure WDOG1, disable it or enable it
- * depending on FUSE. The update bit is set for reconfigurable.
- * We have to use unlock sequence to reconfigure it.
- * WDOG2 is not touched by ROM, so it will have default value
- * which is enabled. We can directly configure it.
- * To simplify the codes, we still use same reconfigure
- * process as WDOG1. Because the update bit is not set for
- * WDOG2, the unlock sequence won't take effect really.
- * It actually directly configure the wdog.
- * In this function, we will disable both WDOG1 and WDOG2,
- * and set update bit for both. So that kernel can reconfigure them.
- */
- disable_wdog(WDG1_RBASE);
- disable_wdog(WDG2_RBASE);
-}
-
-
-void s_init(void)
-{
- /* Disable wdog */
- init_wdog();
-
- /* clock configuration. */
- clock_init();
-
- return;
-}
-
-#ifndef CONFIG_ULP_WATCHDOG
-void reset_cpu(ulong addr)
-{
- setbits_le32(SIM0_RBASE, SIM_SOPT1_A7_SW_RESET);
- while (1)
- ;
-}
-#endif
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-const char *get_imx_type(u32 imxtype)
-{
- return "7ULP";
-}
-
-int print_cpuinfo(void)
-{
- u32 cpurev;
- char cause[18];
-
- cpurev = get_cpu_rev();
-
- printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
- get_imx_type((cpurev & 0xFF000) >> 12),
- (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0,
- mxc_get_clock(MXC_ARM_CLK) / 1000000);
-
- printf("Reset cause: %s\n", get_reset_cause(cause));
-
- printf("Boot mode: ");
- switch (get_boot_mode()) {
- case LOW_POWER_BOOT:
- printf("Low power boot\n");
- break;
- case DUAL_BOOT:
- printf("Dual boot\n");
- break;
- case SINGLE_BOOT:
- default:
- printf("Single boot\n");
- break;
- }
-
- return 0;
-}
-#endif
-
-#define CMC_SRS_TAMPER (1 << 31)
-#define CMC_SRS_SECURITY (1 << 30)
-#define CMC_SRS_TZWDG (1 << 29)
-#define CMC_SRS_JTAG_RST (1 << 28)
-#define CMC_SRS_CORE1 (1 << 16)
-#define CMC_SRS_LOCKUP (1 << 15)
-#define CMC_SRS_SW (1 << 14)
-#define CMC_SRS_WDG (1 << 13)
-#define CMC_SRS_PIN_RESET (1 << 8)
-#define CMC_SRS_WARM (1 << 4)
-#define CMC_SRS_HVD (1 << 3)
-#define CMC_SRS_LVD (1 << 2)
-#define CMC_SRS_POR (1 << 1)
-#define CMC_SRS_WUP (1 << 0)
-
-static u32 reset_cause = -1;
-
-static char *get_reset_cause(char *ret)
-{
- u32 cause1, cause = 0, srs = 0;
- u32 *reg_ssrs = (u32 *)(SRC_BASE_ADDR + 0x28);
- u32 *reg_srs = (u32 *)(SRC_BASE_ADDR + 0x20);
-
- if (!ret)
- return "null";
-
- srs = readl(reg_srs);
- cause1 = readl(reg_ssrs);
- writel(cause1, reg_ssrs);
-
- reset_cause = cause1;
-
- cause = cause1 & (CMC_SRS_POR | CMC_SRS_WUP | CMC_SRS_WARM);
-
- switch (cause) {
- case CMC_SRS_POR:
- sprintf(ret, "%s", "POR");
- break;
- case CMC_SRS_WUP:
- sprintf(ret, "%s", "WUP");
- break;
- case CMC_SRS_WARM:
- cause = cause1 & (CMC_SRS_WDG | CMC_SRS_SW |
- CMC_SRS_JTAG_RST);
- switch (cause) {
- case CMC_SRS_WDG:
- sprintf(ret, "%s", "WARM-WDG");
- break;
- case CMC_SRS_SW:
- sprintf(ret, "%s", "WARM-SW");
- break;
- case CMC_SRS_JTAG_RST:
- sprintf(ret, "%s", "WARM-JTAG");
- break;
- default:
- sprintf(ret, "%s", "WARM-UNKN");
- break;
- }
- break;
- default:
- sprintf(ret, "%s-%X", "UNKN", cause1);
- break;
- }
-
- debug("[%X] SRS[%X] %X - ", cause1, srs, srs^cause1);
- return ret;
-}
-
-#ifdef CONFIG_ENV_IS_IN_MMC
-__weak int board_mmc_get_env_dev(int devno)
-{
- return CONFIG_SYS_MMC_ENV_DEV;
-}
-
-int mmc_get_env_dev(void)
-{
- int devno = 0;
- u32 bt1_cfg = 0;
-
- /* If not boot from sd/mmc, use default value */
- if (get_boot_mode() == LOW_POWER_BOOT)
- return CONFIG_SYS_MMC_ENV_DEV;
-
- bt1_cfg = readl(CMC1_RBASE + 0x40);
- devno = (bt1_cfg >> 9) & 0x7;
-
- return board_mmc_get_env_dev(devno);
-}
-#endif
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
-#include <asm/imx-common/sys_proto.h>
+#include <asm/mach-imx/sys_proto.h>
#include <netdev.h>
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
debug("%s: PPA image load from NAND\n", __func__);
nand_init();
- ret = nand_read(nand_info[0], (loff_t)CONFIG_SYS_LS_PPA_FW_ADDR,
- &fdt_header_len, (u_char *)&fit);
+ ret = nand_read(get_nand_dev_by_index(0),
+ (loff_t)CONFIG_SYS_LS_PPA_FW_ADDR,
+ &fdt_header_len, (u_char *)&fit);
if (ret == -EUCLEAN) {
printf("NAND read of PPA FIT header at offset 0x%x failed\n",
CONFIG_SYS_LS_PPA_FW_ADDR);
fw_length = CONFIG_LS_PPA_ESBC_HDR_SIZE;
- ret = nand_read(nand_info[0], (loff_t)CONFIG_SYS_LS_PPA_ESBC_ADDR,
- &fw_length, (u_char *)ppa_hdr_ddr);
+ ret = nand_read(get_nand_dev_by_index(0),
+ (loff_t)CONFIG_SYS_LS_PPA_ESBC_ADDR,
+ &fw_length, (u_char *)ppa_hdr_ddr);
if (ret == -EUCLEAN) {
free(ppa_hdr_ddr);
printf("NAND read of PPA firmware at offset 0x%x failed\n",
return -ENOMEM;
}
- ret = nand_read(nand_info[0], (loff_t)CONFIG_SYS_LS_PPA_FW_ADDR,
- &fw_length, (u_char *)ppa_fit_addr);
+ ret = nand_read(get_nand_dev_by_index(0),
+ (loff_t)CONFIG_SYS_LS_PPA_FW_ADDR,
+ &fw_length, (u_char *)ppa_fit_addr);
if (ret == -EUCLEAN) {
free(ppa_fit_addr);
printf("NAND read of PPA firmware at offset 0x%x failed\n",
--- /dev/null
+/*
+ * Copyright (C) 2017 Marek Behun <marek.behun@nic.cz>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/ {
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2cmux;
+ spi0 = &spi0;
+ };
+};
+
+&i2c0 {
+ u-boot,dm-pre-reloc;
+
+ i2cmux: i2cmux@70 {
+ u-boot,dm-pre-reloc;
+
+ i2c@0 {
+ u-boot,dm-pre-reloc;
+ };
+
+ i2c@1 {
+ u-boot,dm-pre-reloc;
+ };
+
+ i2c@5 {
+ u-boot,dm-pre-reloc;
+
+ /* ATSHA204A at address 0x64 */
+ atsha204a@64 {
+ u-boot,dm-pre-reloc;
+ compatible = "atmel,atsha204a";
+ reg = <0x64>;
+ };
+ };
+ };
+};
+
+&spi0 {
+ u-boot,dm-pre-reloc;
+
+ spi-flash@0 {
+ compatible = "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+};
--- /dev/null
+/*
+ * Device Tree file for the Turris Omnia
+ *
+ * Copyright (C) 2016 Uwe Kleine-König <uwe@kleine-koenig.org>
+ * Copyright (C) 2016 Tomas Hlavacek <tmshlvkc@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Schematic available at https://www.turris.cz/doc/_media/rtrom01-schema.pdf
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "armada-385.dtsi"
+
+/ {
+ model = "Turris Omnia";
+ compatible = "cznic,turris-omnia", "marvell,armada385", "marvell,armada380";
+
+ chosen {
+ stdout-path = &uart0;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x40000000>; /* 1024 MB */
+ };
+
+ soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+ MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
+ MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
+ MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
+
+ internal-regs {
+
+ /* USB part of the PCIe2/USB 2.0 port */
+ usb@58000 {
+ status = "okay";
+ };
+
+ sata@a8000 {
+ status = "okay";
+ };
+
+ sdhci@d8000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhci_pins>;
+ status = "okay";
+
+ bus-width = <8>;
+ no-1-8-v;
+ non-removable;
+ };
+
+ usb3@f0000 {
+ status = "okay";
+ };
+
+ usb3@f8000 {
+ status = "okay";
+ };
+ };
+
+ pcie-controller {
+ status = "okay";
+
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+
+ pcie@2,0 {
+ /* Port 1, Lane 0 */
+ status = "okay";
+ };
+
+ pcie@3,0 {
+ /* Port 2, Lane 0 */
+ status = "okay";
+ };
+ };
+ };
+};
+
+/* Connected to 88E6176 switch, port 6 */
+ð0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ge0_rgmii_pins>;
+ status = "okay";
+ phy-mode = "rgmii";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
+/* Connected to 88E6176 switch, port 5 */
+ð1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ge1_rgmii_pins>;
+ status = "okay";
+ phy-mode = "rgmii";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
+/* WAN port */
+ð2 {
+ status = "okay";
+ phy-mode = "sgmii";
+ phy = <&phy1>;
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ status = "okay";
+
+ i2cmux@70 {
+ compatible = "nxp,pca9547";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x70>;
+ status = "okay";
+
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ /* STM32F0 command interface at address 0x2a */
+ /* leds device (in STM32F0) at address 0x2b */
+
+ eeprom@54 {
+ compatible = "at,24c64";
+ reg = <0x54>;
+
+ /* The EEPROM contains data for bootloader.
+ * Contents:
+ * struct omnia_eeprom {
+ * u32 magic; (=0x0341a034 in LE)
+ * u32 ramsize; (in GiB)
+ * char regdomain[4];
+ * u32 crc32;
+ * };
+ */
+ };
+ };
+
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ /* routed to PCIe0/mSATA connector (CN7A) */
+ };
+
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+
+ /* routed to PCIe1/USB2 connector (CN61A) */
+ };
+
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+
+ /* routed to PCIe2 connector (CN62A) */
+ };
+
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+
+ /* routed to SFP+ */
+ };
+
+ i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+
+ /* ATSHA204A at address 0x64 */
+ };
+
+ i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+
+ /* exposed on pin header */
+ };
+
+ i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+
+ pcawan: gpio@71 {
+ /*
+ * GPIO expander for SFP+ signals and
+ * and phy irq
+ */
+ compatible = "nxp,pca9538";
+ reg = <0x71>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcawan_pins>;
+
+ interrupt-parent = <&gpio1>;
+ interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+ };
+};
+
+&mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio_pins>;
+ status = "okay";
+
+ phy1: phy@1 {
+ status = "okay";
+ compatible = "ethernet-phy-id0141.0DD1", "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+
+ /* irq is connected to &pcawan pin 7 */
+ };
+
+ /* Switch MV88E6176 at address 0x10 */
+ switch@10 {
+ compatible = "marvell,mv88e6085";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dsa,member = <0 0>;
+
+ reg = <0x10>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports@0 {
+ reg = <0>;
+ label = "lan0";
+ };
+
+ ports@1 {
+ reg = <1>;
+ label = "lan1";
+ };
+
+ ports@2 {
+ reg = <2>;
+ label = "lan2";
+ };
+
+ ports@3 {
+ reg = <3>;
+ label = "lan3";
+ };
+
+ ports@4 {
+ reg = <4>;
+ label = "lan4";
+ };
+
+ ports@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <ð1>;
+ phy-mode = "rgmii-id";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ /* port 6 is connected to eth0 */
+ };
+ };
+};
+
+&pinctrl {
+ pcawan_pins: pcawan-pins {
+ marvell,pins = "mpp46";
+ marvell,function = "gpio";
+ };
+
+ spi0cs0_pins: spi0cs0-pins {
+ marvell,pins = "mpp25";
+ marvell,function = "spi0";
+ };
+
+ spi0cs1_pins: spi0cs1-pins {
+ marvell,pins = "mpp26";
+ marvell,function = "spi0";
+ };
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins &spi0cs0_pins>;
+ status = "okay";
+
+ spi-nor@0 {
+ compatible = "spansion,s25fl164k", "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ reg = <0x0 0x00100000>;
+ label = "U-Boot";
+ };
+
+ partition@100000 {
+ reg = <0x00100000 0x00700000>;
+ label = "Rescue system";
+ };
+ };
+ };
+
+ /* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */
+};
+
+&uart0 {
+ /* Pin header CN10 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
+&uart1 {
+ /* Pin header CN11 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ status = "okay";
+};
reg = <0x0 0x10000000 0x0 0x200000>;
no-map;
};
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0xbc00000>;
+ alignment = <0x0 0x400000>;
+ linux,cma-default;
+ };
};
cpus {
};
i2c_A: i2c@8500 {
- compatible = "amlogic,meson-gxbb-i2c";
+ compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
reg = <0x0 0x08500 0x0 0x20>;
interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
status = "disabled";
};
+ saradc: adc@8680 {
+ compatible = "amlogic,meson-saradc";
+ reg = <0x0 0x8680 0x0 0x34>;
+ #io-channel-cells = <1>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ };
+
pwm_ef: pwm@86c0 {
compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
reg = <0x0 0x086c0 0x0 0x10>;
};
i2c_B: i2c@87c0 {
- compatible = "amlogic,meson-gxbb-i2c";
+ compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
reg = <0x0 0x087c0 0x0 0x20>;
interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
};
i2c_C: i2c@87e0 {
- compatible = "amlogic,meson-gxbb-i2c";
+ compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
reg = <0x0 0x087e0 0x0 0x20>;
interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
status = "disabled";
};
+ spifc: spi@8c80 {
+ compatible = "amlogic,meson-gx-spifc", "amlogic,meson-gxbb-spifc";
+ reg = <0x0 0x08c80 0x0 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
watchdog@98d0 {
compatible = "amlogic,meson-gx-wdt", "amlogic,meson-gxbb-wdt";
reg = <0x0 0x098d0 0x0 0x10>;
};
sram: sram@c8000000 {
- compatible = "amlogic,meson-gxbb-sram", "mmio-sram";
+ compatible = "amlogic,meson-gx-sram", "amlogic,meson-gxbb-sram", "mmio-sram";
reg = <0x0 0xc8000000 0x0 0x14000>;
#address-cells = <1>;
ranges = <0 0x0 0xc8000000 0x14000>;
cpu_scp_lpri: scp-shmem@0 {
- compatible = "amlogic,meson-gxbb-scp-shmem";
+ compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
reg = <0x13000 0x400>;
};
cpu_scp_hpri: scp-shmem@200 {
- compatible = "amlogic,meson-gxbb-scp-shmem";
+ compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
reg = <0x13400 0x400>;
};
};
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
+ clkc_AO: clock-controller@040 {
+ compatible = "amlogic,gx-aoclkc", "amlogic,gxbb-aoclkc";
+ reg = <0x0 0x00040 0x0 0x4>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
uart_AO: serial@4c0 {
compatible = "amlogic,meson-uart";
reg = <0x0 0x004c0 0x0 0x14>;
status = "disabled";
};
+ i2c_AO: i2c@500 {
+ compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
+ reg = <0x0 0x500 0x0 0x20>;
+ interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ pwm_AO_ab: pwm@550 {
+ compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
+ reg = <0x0 0x00550 0x0 0x10>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
ir: ir@580 {
- compatible = "amlogic,meson-gxbb-ir";
+ compatible = "amlogic,meson-gx-ir", "amlogic,meson-gxbb-ir";
reg = <0x0 0x00580 0x0 0x40>;
interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
- rng {
+ hwrng: rng {
compatible = "amlogic,meson-rng";
reg = <0x0 0x0 0x0 0x4>;
};
};
-
hiubus: hiubus@c883c000 {
compatible = "simple-bus";
reg = <0x0 0xc883c000 0x0 0x2000>;
0x0 0xc8834540 0x0 0x4>;
interrupts = <0 8 1>;
interrupt-names = "macirq";
- phy-mode = "rgmii";
status = "disabled";
};
cvbs_vdac_port: port@0 {
reg = <0>;
};
+
+ /* HDMI-TX output port */
+ hdmi_tx_port: port@1 {
+ reg = <1>;
+
+ hdmi_tx_out: endpoint {
+ remote-endpoint = <&hdmi_tx_in>;
+ };
+ };
+ };
+
+ hdmi_tx: hdmi-tx@c883a000 {
+ compatible = "amlogic,meson-gx-dw-hdmi";
+ reg = <0x0 0xc883a000 0x0 0x1c>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ /* VPU VENC Input */
+ hdmi_tx_venc_port: port@0 {
+ reg = <0>;
+
+ hdmi_tx_in: endpoint {
+ remote-endpoint = <&hdmi_tx_out>;
+ };
+ };
+
+ /* TMDS Output */
+ hdmi_tx_tmds_port: port@1 {
+ reg = <1>;
+ };
};
};
};
/ {
compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
model = "Hardkernel ODROID-C2";
-
+
aliases {
serial0 = &uart_AO;
};
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- gpio = <&gpio_ao GPIOAO_12 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio GPIOY_12 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
pinctrl-0 = <ð_rgmii_pins>;
pinctrl-names = "default";
phy-handle = <ð_phy0>;
+ phy-mode = "rgmii";
+
+ snps,reset-gpio = <&gpio GPIOZ_14 0>;
+ snps,reset-delays-us = <0 10000 1000000>;
+ snps,reset-active-low;
+
+ amlogic,tx-delay-ns = <2>;
mdio {
compatible = "snps,dwmac-mdio";
};
};
+&pinctrl_aobus {
+ gpio-line-names = "UART TX", "UART RX", "VCCK En", "TF 3V3/1V8 En",
+ "USB HUB nRESET", "USB OTG Power En",
+ "J7 Header Pin2", "IR In", "J7 Header Pin4",
+ "J7 Header Pin6", "J7 Header Pin5", "J7 Header Pin7",
+ "HDMI CEC", "SYS LED";
+};
+
+&pinctrl_periphs {
+ gpio-line-names = /* Bank GPIOZ */
+ "Eth MDIO", "Eth MDC", "Eth RGMII RX Clk",
+ "Eth RX DV", "Eth RX D0", "Eth RX D1", "Eth RX D2",
+ "Eth RX D3", "Eth RGMII TX Clk", "Eth TX En",
+ "Eth TX D0", "Eth TX D1", "Eth TX D2", "Eth TX D3",
+ "Eth PHY nRESET", "Eth PHY Intc",
+ /* Bank GPIOH */
+ "HDMI HPD", "HDMI DDC SDA", "HDMI DDC SCL", "",
+ /* Bank BOOT */
+ "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", "eMMC D4",
+ "eMMC D5", "eMMC D6", "eMMC D7", "eMMC Clk",
+ "eMMC Reset", "eMMC CMD",
+ "", "", "", "", "", "", "",
+ /* Bank CARD */
+ "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD",
+ "SDCard D3", "SDCard D2", "SDCard Det",
+ /* Bank GPIODV */
+ "", "", "", "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "", "",
+ "I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK",
+ "PWM D", "PWM B",
+ /* Bank GPIOY */
+ "Revision Bit0", "Revision Bit1", "",
+ "J2 Header Pin35", "", "", "", "J2 Header Pin36",
+ "J2 Header Pin31", "", "", "", "TF VDD En",
+ "J2 Header Pin32", "J2 Header Pin26", "", "",
+ /* Bank GPIOX */
+ "J2 Header Pin29", "J2 Header Pin24",
+ "J2 Header Pin23", "J2 Header Pin22",
+ "J2 Header Pin21", "J2 Header Pin18",
+ "J2 Header Pin33", "J2 Header Pin19",
+ "J2 Header Pin16", "J2 Header Pin15",
+ "J2 Header Pin12", "J2 Header Pin13",
+ "J2 Header Pin8", "J2 Header Pin10",
+ "", "", "", "", "",
+ "J2 Header Pin11", "", "J2 Header Pin7",
+ /* Bank GPIOCLK */
+ "", "", "", "",
+ /* GPIO_TEST_N */
+ "";
+};
+
&ir {
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
pinctrl-names = "default";
};
+&gpio_ao {
+ /*
+ * WARNING: The USB Hub on the Odroid-C2 needs a reset signal
+ * to be turned high in order to be detected by the USB Controller
+ * This signal should be handled by a USB specific power sequence
+ * in order to reset the Hub when USB bus is powered down.
+ */
+ usb-hub {
+ gpio-hog;
+ gpios = <GPIOAO_4 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "usb-hub-reset";
+ };
+};
+
&usb0_phy {
status = "okay";
phy-supply = <&usb_otg_pwr>;
status = "okay";
};
+&saradc {
+ status = "okay";
+ vref-supply = <&vcc1v8>;
+};
+
/* SD */
&sd_emmc_b {
status = "okay";
};
};
-&cbus {
- spifc: spi@8c80 {
- compatible = "amlogic,meson-gxbb-spifc";
- reg = <0x0 0x08c80 0x0 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clkc CLKID_SPI>;
- status = "disabled";
- };
-};
-
ðmac {
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_FCLK_DIV2>,
reg-names = "mux", "pull", "gpio";
gpio-controller;
#gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_aobus 0 0 14>;
};
uart_ao_a_pins: uart_ao_a {
function = "pwm_ao_b";
};
};
- };
- clkc_AO: clock-controller@040 {
- compatible = "amlogic,gxbb-aoclkc";
- reg = <0x0 0x00040 0x0 0x4>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
+ i2s_am_clk_pins: i2s_am_clk {
+ mux {
+ groups = "i2s_am_clk";
+ function = "i2s_out_ao";
+ };
+ };
- pwm_ab_AO: pwm@550 {
- compatible = "amlogic,meson-gxbb-pwm";
- reg = <0x0 0x0550 0x0 0x10>;
- #pwm-cells = <3>;
- status = "disabled";
- };
+ i2s_out_ao_clk_pins: i2s_out_ao_clk {
+ mux {
+ groups = "i2s_out_ao_clk";
+ function = "i2s_out_ao";
+ };
+ };
+
+ i2s_out_lr_clk_pins: i2s_out_lr_clk {
+ mux {
+ groups = "i2s_out_lr_clk";
+ function = "i2s_out_ao";
+ };
+ };
+
+ i2s_out_ch01_ao_pins: i2s_out_ch01_ao {
+ mux {
+ groups = "i2s_out_ch01_ao";
+ function = "i2s_out_ao";
+ };
+ };
+
+ i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
+ mux {
+ groups = "i2s_out_ch23_ao";
+ function = "i2s_out_ao";
+ };
+ };
+
+ i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
+ mux {
+ groups = "i2s_out_ch45_ao";
+ function = "i2s_out_ao";
+ };
+ };
+
+ spdif_out_ao_6_pins: spdif_out_ao_6 {
+ mux {
+ groups = "spdif_out_ao_6";
+ function = "spdif_out_ao";
+ };
+ };
- i2c_AO: i2c@500 {
- compatible = "amlogic,meson-gxbb-i2c";
- reg = <0x0 0x500 0x0 0x20>;
- interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc CLKID_AO_I2C>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
+ spdif_out_ao_13_pins: spdif_out_ao_13 {
+ mux {
+ groups = "spdif_out_ao_13";
+ function = "spdif_out_ao";
+ };
+ };
};
};
reg-names = "mux", "pull", "pull-enable", "gpio";
gpio-controller;
#gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_periphs 0 14 120>;
};
emmc_pins: emmc {
function = "hdmi_i2c";
};
};
+
+ i2sout_ch23_y_pins: i2sout_ch23_y {
+ mux {
+ groups = "i2sout_ch23_y";
+ function = "i2s_out";
+ };
+ };
+
+ i2sout_ch45_y_pins: i2sout_ch45_y {
+ mux {
+ groups = "i2sout_ch45_y";
+ function = "i2s_out";
+ };
+ };
+
+ i2sout_ch67_y_pins: i2sout_ch67_y {
+ mux {
+ groups = "i2sout_ch67_y";
+ function = "i2s_out";
+ };
+ };
+
+ spdif_out_y_pins: spdif_out_y {
+ mux {
+ groups = "spdif_out_y";
+ function = "spdif_out";
+ };
+ };
};
};
};
};
+&apb {
+ mali: gpu@c0000 {
+ compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
+ reg = <0x0 0xc0000 0x0 0x40000>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp", "gpmmu", "pp", "pmu",
+ "pp0", "ppmmu0", "pp1", "ppmmu1",
+ "pp2", "ppmmu2";
+ clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
+ clock-names = "bus", "core";
+
+ /*
+ * Mali clocking is provided by two identical clock paths
+ * MALI_0 and MALI_1 muxed to a single clock by a glitch
+ * free mux to safely change frequency while running.
+ */
+ assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
+ <&clkc CLKID_MALI_0>,
+ <&clkc CLKID_MALI>; /* Glitch free mux */
+ assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
+ <0>, /* Do Nothing */
+ <&clkc CLKID_MALI_0>;
+ assigned-clock-rates = <0>, /* Do Nothing */
+ <666666666>,
+ <0>; /* Do Nothing */
+ };
+};
+
&i2c_A {
clocks = <&clkc CLKID_I2C>;
};
+&i2c_AO {
+ clocks = <&clkc CLKID_AO_I2C>;
+};
+
&i2c_B {
clocks = <&clkc CLKID_I2C>;
};
clocks = <&clkc CLKID_I2C>;
};
+&saradc {
+ compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
+ clocks = <&xtal>,
+ <&clkc CLKID_SAR_ADC>,
+ <&clkc CLKID_SANA>,
+ <&clkc CLKID_SAR_ADC_CLK>,
+ <&clkc CLKID_SAR_ADC_SEL>;
+ clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+};
+
&sd_emmc_a {
clocks = <&clkc CLKID_SD_EMMC_A>,
<&xtal>,
clock-names = "core", "clkin0", "clkin1";
};
+&spifc {
+ clocks = <&clkc CLKID_SPI>;
+};
+
&vpu {
compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
};
+
+&hwrng {
+ clocks = <&clkc CLKID_RNG0>;
+ clock-names = "core";
+};
+
+&hdmi_tx {
+ compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
+ resets = <&reset RESET_HDMITX_CAPB3>,
+ <&reset RESET_HDMI_SYSTEM_RESET>,
+ <&reset RESET_HDMI_TX>;
+ reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
+ clocks = <&clkc CLKID_HDMI_PCLK>,
+ <&clkc CLKID_CLK81>,
+ <&clkc CLKID_GCLK_VENCI_INT0>;
+ clock-names = "isfr", "iahb", "venci";
+};
--- /dev/null
+&uart2 {
+ u-boot,dm-pre-reloc;
+};
+
+&grf {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
&uart2 {
status = "okay";
};
+
+&usb20_otg {
+ status = "okay";
+};
status = "disabled";
};
+ usb20_otg: usb@30040000 {
+ compatible = "rockchip,rk3229-usb", "rockchip,rk3288-usb",
+ "snps,dwc2";
+ reg = <0x30040000 0x40000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ hnp-srp-disable;
+ dr_mode = "otg";
+ status = "disabled";
+ };
+
gmac: ethernet@30200000 {
compatible = "rockchip,rk3228-gmac";
reg = <0x30200000 0x10000>;
aliases {
rtc0 = &i2c_rtc;
rtc1 = &rk818;
+ eeprom0 = &i2c_eeprom_id;
};
ext_gmac: external-gmac-clock {
pagesize = <32>;
};
+ /* M24C32-D Identification page */
+ i2c_eeprom_id: eeprom@58 {
+ compatible = "atmel,24c32";
+ reg = <0x58>;
+ pagesize = <32>;
+ };
+
vdd_cpu: regulator@60 {
compatible = "fcs,fan53555";
reg = <0x60>;
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3399.dtsi"
-#include "rk3399-sdram-ddr3-1333.dtsi"
+#include "rk3399-sdram-ddr3-1600.dtsi"
/ {
model = "Firefly-RK3399 Board";
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
- regulator-min-microvolt = <800000>;
+ regulator-min-microvolt = <430000>;
regulator-max-microvolt = <1400000>;
+ regulator-init-microvolt = <950000>;
};
vccadc_ref: vccadc-ref {
compatible = "tsd,rk3399-q7", "tsd,puma", "rockchip,rk3399";
config {
- u-boot,spl-payload-offset = <0x40000>; /* 256kbyte */
+ u-boot,spl-payload-offset = <0x40000>; /* @ 256KB */
+ u-boot,mmc-env-offset = <0x4000>; /* @ 16KB */
+ u-boot,efi-partition-entries-offset = <0x200000>; /* 2MB */
u-boot,boot-led = "module_led";
};
pinctrl-names = "default";
status = "okay";
- mr-nbanks = <1>;
/* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */
bank1: bank@0 {
st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_4
#include "armv7-m.dtsi"
#include <dt-bindings/pinctrl/stm32f746-pinfunc.h>
+#include <dt-bindings/clock/stm32fx-clock.h>
+#include <dt-bindings/mfd/stm32f7-rcc.h>
/ {
clocks {
fmc: fmc@A0000000 {
compatible = "st,stm32-fmc";
reg = <0xA0000000 0x1000>;
- clocks = <&rcc 0 64>;
+ clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
u-boot,dm-pre-reloc;
};
reg-names = "QuadSPI", "QuadSPI-memory";
interrupts = <92>;
spi-max-frequency = <108000000>;
- clocks = <&rcc 0 65>;
+ clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>;
status = "disabled";
};
usart1: serial@40011000 {
compatible = "st,stm32f7-usart", "st,stm32f7-uart";
reg = <0x40011000 0x400>;
interrupts = <37>;
- clocks = <&rcc 0 164>;
+ clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>;
status = "disabled";
u-boot,dm-pre-reloc;
};
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x0 0x400>;
- clocks = <&rcc 0 0>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
st,bank-name = "GPIOA";
u-boot,dm-pre-reloc;
};
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x400 0x400>;
- clocks = <&rcc 0 1>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
st,bank-name = "GPIOB";
u-boot,dm-pre-reloc;
};
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x800 0x400>;
- clocks = <&rcc 0 2>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
st,bank-name = "GPIOC";
u-boot,dm-pre-reloc;
};
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0xc00 0x400>;
- clocks = <&rcc 0 3>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
st,bank-name = "GPIOD";
u-boot,dm-pre-reloc;
};
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x1000 0x400>;
- clocks = <&rcc 0 4>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
st,bank-name = "GPIOE";
u-boot,dm-pre-reloc;
};
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x1400 0x400>;
- clocks = <&rcc 0 5>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
st,bank-name = "GPIOF";
u-boot,dm-pre-reloc;
};
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x1800 0x400>;
- clocks = <&rcc 0 6>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
st,bank-name = "GPIOG";
u-boot,dm-pre-reloc;
};
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x1c00 0x400>;
- clocks = <&rcc 0 7>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
st,bank-name = "GPIOH";
u-boot,dm-pre-reloc;
};
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x2000 0x400>;
- clocks = <&rcc 0 8>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
st,bank-name = "GPIOI";
u-boot,dm-pre-reloc;
};
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x2400 0x400>;
- clocks = <&rcc 0 9>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
st,bank-name = "GPIOJ";
u-boot,dm-pre-reloc;
};
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x2800 0x400>;
- clocks = <&rcc 0 10>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
st,bank-name = "GPIOK";
u-boot,dm-pre-reloc;
};
pinctrl-names = "default";
status = "okay";
- mr-nbanks = <1>;
/* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */
bank1: bank@0 {
st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_32 BANKS_4
aliases {
console = &uarta;
- stdout-path = &uarta;
i2c0 = "/i2c@7000d000";
i2c1 = "/i2c@7000c000";
i2c2 = "/i2c@7000c400";
usb2 = "/usb@7d004000";
};
+ chosen {
+ stdout-path = &uarta;
+ };
+
host1x@50000000 {
dc@54200000 {
display-timings {
&usb2 {
status = "okay";
};
-
-/* for U-Boot only */
-&serial0 {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart0 {
- u-boot,dm-pre-reloc;
-};
&usb2 {
status = "okay";
};
-
-/* for U-Boot only */
-&serial0 {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart0 {
- u-boot,dm-pre-reloc;
-};
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
- u-boot,dm-pre-reloc;
serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
compatible = "socionext,uniphier-ld11-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
- u-boot,dm-pre-reloc;
pinctrl: pinctrl {
compatible = "socionext,uniphier-ld11-pinctrl";
- u-boot,dm-pre-reloc;
};
};
&i2c0 {
status = "okay";
};
-
-/* for U-Boot only */
-&serial0 {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart0 {
- u-boot,dm-pre-reloc;
-};
&i2c0 {
status = "okay";
};
-
-/* for U-Boot only */
-&serial0 {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart0 {
- u-boot,dm-pre-reloc;
-};
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
- u-boot,dm-pre-reloc;
serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
compatible = "socionext,uniphier-ld20-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
- u-boot,dm-pre-reloc;
pinctrl: pinctrl {
compatible = "socionext,uniphier-ld20-pinctrl";
- u-boot,dm-pre-reloc;
};
};
+++ /dev/null
-config IMX_CONFIG
- string
-
-config ROM_UNIFIED_SECTIONS
- bool
-
-config IMX_RDC
- bool "i.MX Resource domain controller driver"
- depends on ARCH_MX6 || ARCH_MX7
- help
- i.MX Resource domain controller is used to assign masters
- and peripherals to differet domains. This can be used to
- isolate resources.
-
-config IMX_BOOTAUX
- bool "Support boot auxiliary core"
- depends on ARCH_MX7 || ARCH_MX6
- help
- bootaux [addr] to boot auxiliary core.
-
-config USE_IMXIMG_PLUGIN
- bool "Use imximage plugin code"
- depends on ARCH_MX7 || ARCH_MX6
- help
- i.MX6/7 supports DCD and Plugin. Enable this configuration
- to use Plugin, otherwise DCD will be used.
-
-config SECURE_BOOT
- bool "Support i.MX HAB features"
- depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5
- select FSL_CAAM
- imply CMD_DEKBLOB
- help
- This option enables the support for secure boot (HAB).
- See doc/README.mxc_hab for more details.
-
-config CMD_BMODE
- bool "Support the 'bmode' command"
- default y
- depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5
- help
- This enables the 'bmode' (bootmode) command for forcing
- a boot from specific media.
-
- This is useful for forcing the ROM's usb downloader to
- activate upon a watchdog reset which is nice when iterating
- on U-Boot. Using the reset button or running bmode normal
- will set it back to normal. This command currently
- supports i.MX53 and i.MX6.
-
-config CMD_DEKBLOB
- bool "Support the 'dek_blob' command"
- help
- This enables the 'dek_blob' command which is used with the
- Freescale secure boot mechanism. This command encapsulates and
- creates a blob of data. See also CMD_BLOB and doc/README.mxc_hab for
- more information.
-
-config CMD_HDMIDETECT
- bool "Support the 'hdmidet' command"
- help
- This enables the 'hdmidet' command which detects if an HDMI monitor
- is connected.
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2011 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 vf610))
-obj-y = iomux-v3.o
-endif
-ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
-obj-y += timer.o cpu.o speed.o
-obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
-endif
-ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs))
-obj-y += misc.o
-obj-$(CONFIG_SPL_BUILD) += spl.o
-endif
-ifeq ($(SOC),$(filter $(SOC),mx7))
-obj-y += cpu.o
-obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
-obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o
-endif
-ifeq ($(SOC),$(filter $(SOC),mx6 mx7))
-obj-y += cache.o init.o
-obj-$(CONFIG_SATA) += sata.o
-obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
-obj-$(CONFIG_IMX_RDC) += rdc-sema.o
-obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
-obj-$(CONFIG_SECURE_BOOT) += hab.o
-endif
-ifeq ($(SOC),$(filter $(SOC),mx7ulp))
-obj-y += cache.o
-obj-$(CONFIG_SECURE_BOOT) += hab.o
-endif
-ifeq ($(SOC),$(filter $(SOC),vf610))
-obj-y += ddrmc-vf610.o
-endif
-ifneq ($(CONFIG_SPL_BUILD),y)
-obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o
-obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
-obj-$(CONFIG_CMD_DEKBLOB) += cmd_dek.o
-endif
-
-PLUGIN = board/$(BOARDDIR)/plugin
-
-ifeq ($(CONFIG_USE_IMXIMG_PLUGIN),y)
-
-$(PLUGIN).o: $(PLUGIN).S FORCE
- $(Q)mkdir -p $(dir $@)
- $(call if_changed_dep,as_o_S)
-
-$(PLUGIN).bin: $(PLUGIN).o FORCE
- $(Q)mkdir -p $(dir $@)
- $(OBJCOPY) -O binary --gap-fill 0xff $< $@
-else
-
-$(PLUGIN).bin:
-
-endif
-
-quiet_cmd_cpp_cfg = CFGS $@
- cmd_cpp_cfg = $(CPP) $(cpp_flags) -x c -o $@ $<
-
-IMX_CONFIG = $(CONFIG_IMX_CONFIG:"%"=%).cfgtmp
-
-$(IMX_CONFIG): %.cfgtmp: % FORCE
- $(Q)mkdir -p $(dir $@)
- $(call if_changed_dep,cpp_cfg)
-
-MKIMAGEFLAGS_u-boot.imx = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) -T imximage \
- -e $(CONFIG_SYS_TEXT_BASE)
-u-boot.imx: MKIMAGEOUTPUT = u-boot.imx.log
-
-u-boot.imx: u-boot.bin $(IMX_CONFIG) $(PLUGIN).bin FORCE
- $(call if_changed,mkimage)
-
-ifeq ($(CONFIG_OF_SEPARATE),y)
-MKIMAGEFLAGS_u-boot-dtb.imx = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) -T imximage \
- -e $(CONFIG_SYS_TEXT_BASE)
-u-boot-dtb.imx: MKIMAGEOUTPUT = u-boot-dtb.imx.log
-
-u-boot-dtb.imx: u-boot-dtb.bin $(IMX_CONFIG) $(PLUGIN).bin FORCE
- $(call if_changed,mkimage)
-endif
-
-MKIMAGEFLAGS_SPL = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) -T imximage \
- -e $(CONFIG_SPL_TEXT_BASE)
-
-SPL: MKIMAGEOUTPUT = SPL.log
-
-SPL: spl/u-boot-spl.bin $(IMX_CONFIG) $(PLUGIN).bin FORCE
- $(call if_changed,mkimage)
-
-MKIMAGEFLAGS_u-boot.uim = -A arm -O U-Boot -a $(CONFIG_SYS_TEXT_BASE) \
- -e $(CONFIG_SYS_TEXT_BASE) -C none -T firmware
-
-u-boot.uim: u-boot.bin FORCE
- $(call if_changed,mkimage)
-
-OBJCOPYFLAGS += -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO)
-append = cat $(filter-out $< $(PHONY), $^) >> $@
-
-quiet_cmd_pad_cat = CAT $@
-cmd_pad_cat = $(cmd_objcopy) && $(append) || rm -f $@
-
-u-boot-with-spl.imx: SPL u-boot.uim FORCE
- $(call if_changed,pad_cat)
-
-u-boot-with-nand-spl.imx: spl/u-boot-nand-spl.imx u-boot.uim FORCE
- $(call if_changed,pad_cat)
-
-quiet_cmd_u-boot-nand-spl_imx = GEN $@
-cmd_u-boot-nand-spl_imx = (printf '\000\000\000\000\106\103\102\040\001' && \
- dd bs=1015 count=1 if=/dev/zero 2>/dev/null) | cat - $< > $@
-
-spl/u-boot-nand-spl.imx: SPL FORCE
- $(call if_changed,u-boot-nand-spl_imx)
-
-targets += $(addprefix ../../../,$(IMX_CONFIG) SPL u-boot.uim spl/u-boot-nand-spl.imx)
+++ /dev/null
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/armv7.h>
-#include <asm/pl310.h>
-#include <asm/io.h>
-#include <asm/imx-common/sys_proto.h>
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
-#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
- enum dcache_option option = DCACHE_WRITETHROUGH;
-#else
- enum dcache_option option = DCACHE_WRITEBACK;
-#endif
- /* Avoid random hang when download by usb */
- invalidate_dcache_all();
-
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
-
- /* Enable caching on OCRAM and ROM */
- mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
- ROMCP_ARB_END_ADDR,
- option);
- mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
- IRAM_SIZE,
- option);
-}
-#endif
-
-#ifndef CONFIG_SYS_L2CACHE_OFF
-#ifdef CONFIG_SYS_L2_PL310
-#define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
-void v7_outer_cache_enable(void)
-{
- struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
- struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
- unsigned int val;
-
-
- /*
- * Must disable the L2 before changing the latency parameters
- * and auxiliary control register.
- */
- clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-
- /*
- * Set bit 22 in the auxiliary control register. If this bit
- * is cleared, PL310 treats Normal Shared Non-cacheable
- * accesses as Cacheable no-allocate.
- */
- setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
-
- if (is_mx6sl() || is_mx6sll()) {
- val = readl(&iomux->gpr[11]);
- if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
- /* L2 cache configured as OCRAM, reset it */
- val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
- writel(val, &iomux->gpr[11]);
- }
- }
-
- writel(0x132, &pl310->pl310_tag_latency_ctrl);
- writel(0x132, &pl310->pl310_data_latency_ctrl);
-
- val = readl(&pl310->pl310_prefetch_ctrl);
-
- /* Turn on the L2 I/D prefetch */
- val |= 0x30000000;
-
- /*
- * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
- * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
- * But according to ARM PL310 errata: 752271
- * ID: 752271: Double linefill feature can cause data corruption
- * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
- * Workaround: The only workaround to this erratum is to disable the
- * double linefill feature. This is the default behavior.
- */
-
-#ifndef CONFIG_MX6Q
- val |= 0x40800000;
-#endif
- writel(val, &pl310->pl310_prefetch_ctrl);
-
- val = readl(&pl310->pl310_power_ctrl);
- val |= L2X0_DYNAMIC_CLK_GATING_EN;
- val |= L2X0_STNDBY_MODE_EN;
- writel(val, &pl310->pl310_power_ctrl);
-
- setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-}
-
-void v7_outer_cache_disable(void)
-{
- struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
-
- clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-}
-#endif /* !CONFIG_SYS_L2_PL310 */
-#endif /* !CONFIG_SYS_L2CACHE_OFF */
+++ /dev/null
-/*
- * Copyright (C) 2012 Boundary Devices Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <linux/errno.h>
-#include <asm/io.h>
-#include <asm/imx-common/boot_mode.h>
-#include <malloc.h>
-#include <command.h>
-
-static const struct boot_mode *modes[2];
-
-static const struct boot_mode *search_modes(char *arg)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(modes); i++) {
- const struct boot_mode *p = modes[i];
- if (p) {
- while (p->name) {
- if (!strcmp(p->name, arg))
- return p;
- p++;
- }
- }
- }
- return NULL;
-}
-
-static int create_usage(char *dest)
-{
- int i;
- int size = 0;
-
- for (i = 0; i < ARRAY_SIZE(modes); i++) {
- const struct boot_mode *p = modes[i];
- if (p) {
- while (p->name) {
- int len = strlen(p->name);
- if (dest) {
- memcpy(dest, p->name, len);
- dest += len;
- *dest++ = '|';
- }
- size += len + 1;
- p++;
- }
- }
- }
- if (dest)
- memcpy(dest - 1, " [noreset]", 11); /* include trailing 0 */
- size += 10;
- return size;
-}
-
-static int do_boot_mode(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- const struct boot_mode *p;
- int reset_requested = 1;
-
- if (argc < 2)
- return CMD_RET_USAGE;
- p = search_modes(argv[1]);
- if (!p)
- return CMD_RET_USAGE;
- if (argc == 3) {
- if (strcmp(argv[2], "noreset"))
- return CMD_RET_USAGE;
- reset_requested = 0;
- }
-
- boot_mode_apply(p->cfg_val);
- if (reset_requested && p->cfg_val)
- do_reset(NULL, 0, 0, NULL);
- return 0;
-}
-
-U_BOOT_CMD(
- bmode, 3, 0, do_boot_mode,
- NULL,
- "");
-
-void add_board_boot_modes(const struct boot_mode *p)
-{
- int size;
- char *dest;
-
- cmd_tbl_t *entry = ll_entry_get(cmd_tbl_t, bmode, cmd);
-
- if (entry->usage) {
- free(entry->usage);
- entry->usage = NULL;
- }
-
- modes[0] = p;
- modes[1] = soc_boot_modes;
- size = create_usage(NULL);
- dest = malloc(size);
- if (dest) {
- create_usage(dest);
- entry->usage = dest;
- }
-}
+++ /dev/null
-/*
- * Copyright 2008-2015 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Command for encapsulating DEK blob
- */
-
-#include <common.h>
-#include <command.h>
-#include <environment.h>
-#include <malloc.h>
-#include <asm/byteorder.h>
-#include <linux/compiler.h>
-#include <fsl_sec.h>
-#include <asm/arch/clock.h>
-#include <mapmem.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/**
-* blob_dek() - Encapsulate the DEK as a blob using CAM's Key
-* @src: - Address of data to be encapsulated
-* @dst: - Desination address of encapsulated data
-* @len: - Size of data to be encapsulated
-*
-* Returns zero on success,and negative on error.
-*/
-static int blob_encap_dek(const u8 *src, u8 *dst, u32 len)
-{
- int ret = 0;
- u32 jr_size = 4;
-
- u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR + 0x102c);
- if (out_jr_size != jr_size) {
- hab_caam_clock_enable(1);
- sec_init();
- }
-
- if (!((len == 128) | (len == 192) | (len == 256))) {
- debug("Invalid DEK size. Valid sizes are 128, 192 and 256b\n");
- return -1;
- }
-
- len /= 8;
- ret = blob_dek(src, dst, len);
-
- return ret;
-}
-
-/**
- * do_dek_blob() - Handle the "dek_blob" command-line command
- * @cmdtp: Command data struct pointer
- * @flag: Command flag
- * @argc: Command-line argument count
- * @argv: Array of command-line arguments
- *
- * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
- * on error.
- */
-static int do_dek_blob(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
-{
- uint32_t src_addr, dst_addr, len;
- uint8_t *src_ptr, *dst_ptr;
- int ret = 0;
-
- if (argc != 4)
- return CMD_RET_USAGE;
-
- src_addr = simple_strtoul(argv[1], NULL, 16);
- dst_addr = simple_strtoul(argv[2], NULL, 16);
- len = simple_strtoul(argv[3], NULL, 10);
-
- src_ptr = map_sysmem(src_addr, len/8);
- dst_ptr = map_sysmem(dst_addr, BLOB_SIZE(len/8));
-
- ret = blob_encap_dek(src_ptr, dst_ptr, len);
-
- return ret;
-}
-
-/***************************************************/
-static char dek_blob_help_text[] =
- "src dst len - Encapsulate and create blob of data\n"
- " $len bits long at address $src and\n"
- " store the result at address $dst.\n";
-
-U_BOOT_CMD(
- dek_blob, 4, 1, do_dek_blob,
- "Data Encryption Key blob encapsulation",
- dek_blob_help_text
-);
+++ /dev/null
-/*
- * Copyright (C) 2012 Boundary Devices Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/mxc_hdmi.h>
-#include <asm/io.h>
-
-static int do_hdmidet(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
- return (readb(&hdmi->phy_stat0) & HDMI_DVI_STAT) ? 0 : 1;
-}
-
-U_BOOT_CMD(hdmidet, 1, 1, do_hdmidet,
- "detect HDMI monitor",
- ""
-);
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <bootm.h>
-#include <common.h>
-#include <netdev.h>
-#include <linux/errno.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/crm_regs.h>
-#include <imx_thermal.h>
-#include <ipu_pixfmt.h>
-#include <thermal.h>
-#include <sata.h>
-
-#ifdef CONFIG_FSL_ESDHC
-#include <fsl_esdhc.h>
-#endif
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-static u32 reset_cause = -1;
-
-static char *get_reset_cause(void)
-{
- u32 cause;
- struct src *src_regs = (struct src *)SRC_BASE_ADDR;
-
- cause = readl(&src_regs->srsr);
- writel(cause, &src_regs->srsr);
- reset_cause = cause;
-
- switch (cause) {
- case 0x00001:
- case 0x00011:
- return "POR";
- case 0x00004:
- return "CSU";
- case 0x00008:
- return "IPP USER";
- case 0x00010:
-#ifdef CONFIG_MX7
- return "WDOG1";
-#else
- return "WDOG";
-#endif
- case 0x00020:
- return "JTAG HIGH-Z";
- case 0x00040:
- return "JTAG SW";
- case 0x00080:
- return "WDOG3";
-#ifdef CONFIG_MX7
- case 0x00100:
- return "WDOG4";
- case 0x00200:
- return "TEMPSENSE";
-#else
- case 0x00100:
- return "TEMPSENSE";
- case 0x10000:
- return "WARM BOOT";
-#endif
- default:
- return "unknown reset";
- }
-}
-
-u32 get_imx_reset_cause(void)
-{
- return reset_cause;
-}
-#endif
-
-#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
-#if defined(CONFIG_MX53)
-#define MEMCTL_BASE ESDCTL_BASE_ADDR
-#else
-#define MEMCTL_BASE MMDC_P0_BASE_ADDR
-#endif
-static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
-static const unsigned char bank_lookup[] = {3, 2};
-
-/* these MMDC registers are common to the IMX53 and IMX6 */
-struct esd_mmdc_regs {
- uint32_t ctl;
- uint32_t pdc;
- uint32_t otc;
- uint32_t cfg0;
- uint32_t cfg1;
- uint32_t cfg2;
- uint32_t misc;
-};
-
-#define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7)
-#define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7)
-#define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3)
-#define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1)
-#define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1)
-
-/*
- * imx_ddr_size - return size in bytes of DRAM according MMDC config
- * The MMDC MDCTL register holds the number of bits for row, col, and data
- * width and the MMDC MDMISC register holds the number of banks. Combine
- * all these bits to determine the meme size the MMDC has been configured for
- */
-unsigned imx_ddr_size(void)
-{
- struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
- unsigned ctl = readl(&mem->ctl);
- unsigned misc = readl(&mem->misc);
- int bits = 11 + 0 + 0 + 1; /* row + col + bank + width */
-
- bits += ESD_MMDC_CTL_GET_ROW(ctl);
- bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
- bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
- bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
- bits += ESD_MMDC_CTL_GET_CS1(ctl);
-
- /* The MX6 can do only 3840 MiB of DRAM */
- if (bits == 32)
- return 0xf0000000;
-
- return 1 << bits;
-}
-#endif
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-
-const char *get_imx_type(u32 imxtype)
-{
- switch (imxtype) {
- case MXC_CPU_MX7S:
- return "7S"; /* Single-core version of the mx7 */
- case MXC_CPU_MX7D:
- return "7D"; /* Dual-core version of the mx7 */
- case MXC_CPU_MX6QP:
- return "6QP"; /* Quad-Plus version of the mx6 */
- case MXC_CPU_MX6DP:
- return "6DP"; /* Dual-Plus version of the mx6 */
- case MXC_CPU_MX6Q:
- return "6Q"; /* Quad-core version of the mx6 */
- case MXC_CPU_MX6D:
- return "6D"; /* Dual-core version of the mx6 */
- case MXC_CPU_MX6DL:
- return "6DL"; /* Dual Lite version of the mx6 */
- case MXC_CPU_MX6SOLO:
- return "6SOLO"; /* Solo version of the mx6 */
- case MXC_CPU_MX6SL:
- return "6SL"; /* Solo-Lite version of the mx6 */
- case MXC_CPU_MX6SLL:
- return "6SLL"; /* SLL version of the mx6 */
- case MXC_CPU_MX6SX:
- return "6SX"; /* SoloX version of the mx6 */
- case MXC_CPU_MX6UL:
- return "6UL"; /* Ultra-Lite version of the mx6 */
- case MXC_CPU_MX6ULL:
- return "6ULL"; /* ULL version of the mx6 */
- case MXC_CPU_MX51:
- return "51";
- case MXC_CPU_MX53:
- return "53";
- default:
- return "??";
- }
-}
-
-int print_cpuinfo(void)
-{
- u32 cpurev;
- __maybe_unused u32 max_freq;
-
- cpurev = get_cpu_rev();
-
-#if defined(CONFIG_IMX_THERMAL)
- struct udevice *thermal_dev;
- int cpu_tmp, minc, maxc, ret;
-
- printf("CPU: Freescale i.MX%s rev%d.%d",
- get_imx_type((cpurev & 0xFF000) >> 12),
- (cpurev & 0x000F0) >> 4,
- (cpurev & 0x0000F) >> 0);
- max_freq = get_cpu_speed_grade_hz();
- if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) {
- printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
- } else {
- printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
- mxc_get_clock(MXC_ARM_CLK) / 1000000);
- }
-#else
- printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
- get_imx_type((cpurev & 0xFF000) >> 12),
- (cpurev & 0x000F0) >> 4,
- (cpurev & 0x0000F) >> 0,
- mxc_get_clock(MXC_ARM_CLK) / 1000000);
-#endif
-
-#if defined(CONFIG_IMX_THERMAL)
- puts("CPU: ");
- switch (get_cpu_temp_grade(&minc, &maxc)) {
- case TEMP_AUTOMOTIVE:
- puts("Automotive temperature grade ");
- break;
- case TEMP_INDUSTRIAL:
- puts("Industrial temperature grade ");
- break;
- case TEMP_EXTCOMMERCIAL:
- puts("Extended Commercial temperature grade ");
- break;
- default:
- puts("Commercial temperature grade ");
- break;
- }
- printf("(%dC to %dC)", minc, maxc);
- ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
- if (!ret) {
- ret = thermal_get_temp(thermal_dev, &cpu_tmp);
-
- if (!ret)
- printf(" at %dC\n", cpu_tmp);
- else
- debug(" - invalid sensor data\n");
- } else {
- debug(" - invalid sensor device\n");
- }
-#endif
-
- printf("Reset cause: %s\n", get_reset_cause());
- return 0;
-}
-#endif
-
-int cpu_eth_init(bd_t *bis)
-{
- int rc = -ENODEV;
-
-#if defined(CONFIG_FEC_MXC)
- rc = fecmxc_initialize(bis);
-#endif
-
- return rc;
-}
-
-#ifdef CONFIG_FSL_ESDHC
-/*
- * Initializes on-chip MMC controllers.
- * to override, implement board_mmc_init()
- */
-int cpu_mmc_init(bd_t *bis)
-{
- return fsl_esdhc_mmc_init(bis);
-}
-#endif
-
-#ifndef CONFIG_MX7
-u32 get_ahb_clk(void)
-{
- struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- u32 reg, ahb_podf;
-
- reg = __raw_readl(&imx_ccm->cbcdr);
- reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
- ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
-
- return get_periph_clk() / (ahb_podf + 1);
-}
-#endif
-
-void arch_preboot_os(void)
-{
-#if defined(CONFIG_PCIE_IMX)
- imx_pcie_remove();
-#endif
-#if defined(CONFIG_SATA)
- sata_stop();
-#if defined(CONFIG_MX6)
- disable_sata_clock();
-#endif
-#endif
-#if defined(CONFIG_VIDEO_IPUV3)
- /* disable video before launching O/S */
- ipuv3_fb_shutdown();
-#endif
-#if defined(CONFIG_VIDEO_MXS)
- lcdif_power_down();
-#endif
-}
-
-void set_chipselect_size(int const cs_size)
-{
- unsigned int reg;
- struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
- reg = readl(&iomuxc_regs->gpr[1]);
-
- switch (cs_size) {
- case CS0_128:
- reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
- reg |= 0x5;
- break;
- case CS0_64M_CS1_64M:
- reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
- reg |= 0x1B;
- break;
- case CS0_64M_CS1_32M_CS2_32M:
- reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
- reg |= 0x4B;
- break;
- case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
- reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
- reg |= 0x249;
- break;
- default:
- printf("Unknown chip select size: %d\n", cs_size);
- break;
- }
-
- writel(reg, &iomuxc_regs->gpr[1]);
-}
+++ /dev/null
-/*
- * Copyright 2015 Toradex, Inc.
- *
- * Based on vf610twr:
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux-vf610.h>
-#include <asm/arch/ddrmc-vf610.h>
-
-void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count)
-{
- static const iomux_v3_cfg_t default_pads[] = {
- VF610_PAD_DDR_A15__DDR_A_15,
- VF610_PAD_DDR_A14__DDR_A_14,
- VF610_PAD_DDR_A13__DDR_A_13,
- VF610_PAD_DDR_A12__DDR_A_12,
- VF610_PAD_DDR_A11__DDR_A_11,
- VF610_PAD_DDR_A10__DDR_A_10,
- VF610_PAD_DDR_A9__DDR_A_9,
- VF610_PAD_DDR_A8__DDR_A_8,
- VF610_PAD_DDR_A7__DDR_A_7,
- VF610_PAD_DDR_A6__DDR_A_6,
- VF610_PAD_DDR_A5__DDR_A_5,
- VF610_PAD_DDR_A4__DDR_A_4,
- VF610_PAD_DDR_A3__DDR_A_3,
- VF610_PAD_DDR_A2__DDR_A_2,
- VF610_PAD_DDR_A1__DDR_A_1,
- VF610_PAD_DDR_A0__DDR_A_0,
- VF610_PAD_DDR_BA2__DDR_BA_2,
- VF610_PAD_DDR_BA1__DDR_BA_1,
- VF610_PAD_DDR_BA0__DDR_BA_0,
- VF610_PAD_DDR_CAS__DDR_CAS_B,
- VF610_PAD_DDR_CKE__DDR_CKE_0,
- VF610_PAD_DDR_CLK__DDR_CLK_0,
- VF610_PAD_DDR_CS__DDR_CS_B_0,
- VF610_PAD_DDR_D15__DDR_D_15,
- VF610_PAD_DDR_D14__DDR_D_14,
- VF610_PAD_DDR_D13__DDR_D_13,
- VF610_PAD_DDR_D12__DDR_D_12,
- VF610_PAD_DDR_D11__DDR_D_11,
- VF610_PAD_DDR_D10__DDR_D_10,
- VF610_PAD_DDR_D9__DDR_D_9,
- VF610_PAD_DDR_D8__DDR_D_8,
- VF610_PAD_DDR_D7__DDR_D_7,
- VF610_PAD_DDR_D6__DDR_D_6,
- VF610_PAD_DDR_D5__DDR_D_5,
- VF610_PAD_DDR_D4__DDR_D_4,
- VF610_PAD_DDR_D3__DDR_D_3,
- VF610_PAD_DDR_D2__DDR_D_2,
- VF610_PAD_DDR_D1__DDR_D_1,
- VF610_PAD_DDR_D0__DDR_D_0,
- VF610_PAD_DDR_DQM1__DDR_DQM_1,
- VF610_PAD_DDR_DQM0__DDR_DQM_0,
- VF610_PAD_DDR_DQS1__DDR_DQS_1,
- VF610_PAD_DDR_DQS0__DDR_DQS_0,
- VF610_PAD_DDR_RAS__DDR_RAS_B,
- VF610_PAD_DDR_WE__DDR_WE_B,
- VF610_PAD_DDR_ODT1__DDR_ODT_0,
- VF610_PAD_DDR_ODT0__DDR_ODT_1,
- VF610_PAD_DDR_RESETB,
- };
-
- if ((pads == NULL) || (pads_count == 0)) {
- pads = default_pads;
- pads_count = ARRAY_SIZE(default_pads);
- }
-
- imx_iomux_v3_setup_multiple_pads(pads, pads_count);
-}
-
-static struct ddrmc_phy_setting default_phy_settings[] = {
- { DDRMC_PHY_DQ_TIMING, 0 },
- { DDRMC_PHY_DQ_TIMING, 16 },
- { DDRMC_PHY_DQ_TIMING, 32 },
-
- { DDRMC_PHY_DQS_TIMING, 1 },
- { DDRMC_PHY_DQS_TIMING, 17 },
-
- { DDRMC_PHY_CTRL, 2 },
- { DDRMC_PHY_CTRL, 18 },
- { DDRMC_PHY_CTRL, 34 },
-
- { DDRMC_PHY_MASTER_CTRL, 3 },
- { DDRMC_PHY_MASTER_CTRL, 19 },
- { DDRMC_PHY_MASTER_CTRL, 35 },
-
- { DDRMC_PHY_SLAVE_CTRL, 4 },
- { DDRMC_PHY_SLAVE_CTRL, 20 },
- { DDRMC_PHY_SLAVE_CTRL, 36 },
-
- /* LPDDR2 only parameter */
- { DDRMC_PHY_OFF, 49 },
-
- { DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, 50 },
-
- /* Processor Pad ODT settings */
- { DDRMC_PHY_PROC_PAD_ODT, 52 },
-
- /* end marker */
- { 0, -1 }
-};
-
-void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
- struct ddrmc_cr_setting *board_cr_settings,
- struct ddrmc_phy_setting *board_phy_settings,
- int col_diff, int row_diff)
-{
- struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
- struct ddrmc_cr_setting *cr_setting;
- struct ddrmc_phy_setting *phy_setting;
-
- writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]);
- writel(DDRMC_CR02_DRAM_TINIT(timings->tinit), &ddrmr->cr[2]);
- writel(DDRMC_CR10_TRST_PWRON(timings->trst_pwron), &ddrmr->cr[10]);
-
- writel(DDRMC_CR11_CKE_INACTIVE(timings->cke_inactive), &ddrmr->cr[11]);
- writel(DDRMC_CR12_WRLAT(timings->wrlat) |
- DDRMC_CR12_CASLAT_LIN(timings->caslat_lin), &ddrmr->cr[12]);
- writel(DDRMC_CR13_TRC(timings->trc) | DDRMC_CR13_TRRD(timings->trrd) |
- DDRMC_CR13_TCCD(timings->tccd) |
- DDRMC_CR13_TBST_INT_INTERVAL(timings->tbst_int_interval),
- &ddrmr->cr[13]);
- writel(DDRMC_CR14_TFAW(timings->tfaw) | DDRMC_CR14_TRP(timings->trp) |
- DDRMC_CR14_TWTR(timings->twtr) |
- DDRMC_CR14_TRAS_MIN(timings->tras_min), &ddrmr->cr[14]);
- writel(DDRMC_CR16_TMRD(timings->tmrd) |
- DDRMC_CR16_TRTP(timings->trtp), &ddrmr->cr[16]);
- writel(DDRMC_CR17_TRAS_MAX(timings->tras_max) |
- DDRMC_CR17_TMOD(timings->tmod), &ddrmr->cr[17]);
- writel(DDRMC_CR18_TCKESR(timings->tckesr) |
- DDRMC_CR18_TCKE(timings->tcke), &ddrmr->cr[18]);
-
- writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]);
- writel(DDRMC_CR21_TRCD_INT(timings->trcd_int) | DDRMC_CR21_CCMAP_EN |
- DDRMC_CR21_TRAS_LOCKOUT(timings->tras_lockout),
- &ddrmr->cr[21]);
-
- writel(DDRMC_CR22_TDAL(timings->tdal), &ddrmr->cr[22]);
- writel(DDRMC_CR23_BSTLEN(timings->bstlen) |
- DDRMC_CR23_TDLL(timings->tdll), &ddrmr->cr[23]);
- writel(DDRMC_CR24_TRP_AB(timings->trp_ab), &ddrmr->cr[24]);
-
- writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]);
- writel(DDRMC_CR26_TREF(timings->tref) |
- DDRMC_CR26_TRFC(timings->trfc), &ddrmr->cr[26]);
- writel(DDRMC_CR28_TREF_INT(timings->tref_int), &ddrmr->cr[28]);
- writel(DDRMC_CR29_TPDEX(timings->tpdex), &ddrmr->cr[29]);
-
- writel(DDRMC_CR30_TXPDLL(timings->txpdll), &ddrmr->cr[30]);
- writel(DDRMC_CR31_TXSNR(timings->txsnr) |
- DDRMC_CR31_TXSR(timings->txsr), &ddrmr->cr[31]);
- writel(DDRMC_CR33_EN_QK_SREF, &ddrmr->cr[33]);
- writel(DDRMC_CR34_CKSRX(timings->cksrx) |
- DDRMC_CR34_CKSRE(timings->cksre), &ddrmr->cr[34]);
-
- writel(DDRMC_CR38_FREQ_CHG_EN(timings->freq_chg_en), &ddrmr->cr[38]);
- writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) |
- DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]);
-
- writel(DDRMC_CR41_PHY_INI_STRT_INI_DIS, &ddrmr->cr[41]);
- writel(DDRMC_CR48_MR1_DA_0(70) |
- DDRMC_CR48_MR0_DA_0(1056), &ddrmr->cr[48]);
-
- writel(DDRMC_CR66_ZQCL(timings->zqcl) |
- DDRMC_CR66_ZQINIT(timings->zqinit), &ddrmr->cr[66]);
- writel(DDRMC_CR67_ZQCS(timings->zqcs), &ddrmr->cr[67]);
- writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]);
-
- writel(DDRMC_CR70_REF_PER_ZQ(timings->ref_per_zq), &ddrmr->cr[70]);
- writel(DDRMC_CR72_ZQCS_ROTATE(timings->zqcs_rotate), &ddrmr->cr[72]);
-
- writel(DDRMC_CR73_APREBIT(timings->aprebit) |
- DDRMC_CR73_COL_DIFF(col_diff) |
- DDRMC_CR73_ROW_DIFF(row_diff), &ddrmr->cr[73]);
- writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN |
- DDRMC_CR74_CMD_AGE_CNT(timings->cmd_age_cnt) |
- DDRMC_CR74_AGE_CNT(timings->age_cnt),
- &ddrmr->cr[74]);
- writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN |
- DDRMC_CR75_PLEN, &ddrmr->cr[75]);
- writel(DDRMC_CR76_NQENT_ACTDIS(3) | DDRMC_CR76_D_RW_G_BKCN(3) |
- DDRMC_CR76_W2R_SPLT_EN, &ddrmr->cr[76]);
- writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE |
- DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]);
- writel(DDRMC_CR78_Q_FULLNESS(timings->q_fullness) |
- DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]);
- writel(DDRMC_CR79_CTLUPD_AREF(0), &ddrmr->cr[79]);
-
- writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
-
- writel(DDRMC_CR87_ODT_RD_MAPCS0(timings->odt_rd_mapcs0) |
- DDRMC_CR87_ODT_WR_MAPCS0(timings->odt_wr_mapcs0),
- &ddrmr->cr[87]);
- writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]);
- writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]);
-
- writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr->cr[91]);
- writel(DDRMC_CR96_WLMRD(timings->wlmrd) |
- DDRMC_CR96_WLDQSEN(timings->wldqsen), &ddrmr->cr[96]);
-
- /* execute custom CR setting sequence (may be NULL) */
- cr_setting = board_cr_settings;
- if (cr_setting != NULL)
- while (cr_setting->cr_rnum >= 0) {
- writel(cr_setting->setting,
- &ddrmr->cr[cr_setting->cr_rnum]);
- cr_setting++;
- }
-
- /* perform default PHY settings (may be overridden by custom settings */
- phy_setting = default_phy_settings;
- while (phy_setting->phy_rnum >= 0) {
- writel(phy_setting->setting,
- &ddrmr->phy[phy_setting->phy_rnum]);
- phy_setting++;
- }
-
- /* execute custom PHY setting sequence (may be NULL) */
- phy_setting = board_phy_settings;
- if (phy_setting != NULL)
- while (phy_setting->phy_rnum >= 0) {
- writel(phy_setting->setting,
- &ddrmr->phy[phy_setting->phy_rnum]);
- phy_setting++;
- }
-
- /* all inits done, start the DDR controller */
- writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]);
-
- while (!(readl(&ddrmr->cr[80]) && 0x100))
- udelay(10);
-}
+++ /dev/null
-/*
- * Copyright (C) 2010-2015 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <fuse.h>
-#include <asm/io.h>
-#include <asm/system.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/hab.h>
-
-/* -------- start of HAB API updates ------------*/
-
-#define hab_rvt_report_event_p \
-( \
- (is_mx6dqp()) ? \
- ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \
- (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \
- ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \
- (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
- ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \
- ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT) \
-)
-
-#define hab_rvt_report_status_p \
-( \
- (is_mx6dqp()) ? \
- ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
- (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \
- ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
- (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
- ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
- ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS) \
-)
-
-#define hab_rvt_authenticate_image_p \
-( \
- (is_mx6dqp()) ? \
- ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
- (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \
- ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
- (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
- ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
- ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE) \
-)
-
-#define hab_rvt_entry_p \
-( \
- (is_mx6dqp()) ? \
- ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \
- (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \
- ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \
- (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
- ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \
- ((hab_rvt_entry_t *)HAB_RVT_ENTRY) \
-)
-
-#define hab_rvt_exit_p \
-( \
- (is_mx6dqp()) ? \
- ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \
- (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \
- ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \
- (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
- ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \
- ((hab_rvt_exit_t *)HAB_RVT_EXIT) \
-)
-
-#define IVT_SIZE 0x20
-#define ALIGN_SIZE 0x1000
-#define CSF_PAD_SIZE 0x2000
-#define MX6DQ_PU_IROM_MMU_EN_VAR 0x009024a8
-#define MX6DLS_PU_IROM_MMU_EN_VAR 0x00901dd0
-#define MX6SL_PU_IROM_MMU_EN_VAR 0x00900a18
-#define IS_HAB_ENABLED_BIT \
- (is_soc_type(MXC_SOC_MX7ULP) ? 0x80000000 : \
- (is_soc_type(MXC_SOC_MX7) ? 0x2000000 : 0x2))
-
-/*
- * +------------+ 0x0 (DDR_UIMAGE_START) -
- * | Header | |
- * +------------+ 0x40 |
- * | | |
- * | | |
- * | | |
- * | | |
- * | Image Data | |
- * . | |
- * . | > Stuff to be authenticated ----+
- * . | | |
- * | | | |
- * | | | |
- * +------------+ | |
- * | | | |
- * | Fill Data | | |
- * | | | |
- * +------------+ Align to ALIGN_SIZE | |
- * | IVT | | |
- * +------------+ + IVT_SIZE - |
- * | | |
- * | CSF DATA | <---------------------------------------------------------+
- * | |
- * +------------+
- * | |
- * | Fill Data |
- * | |
- * +------------+ + CSF_PAD_SIZE
- */
-
-static bool is_hab_enabled(void);
-
-#if !defined(CONFIG_SPL_BUILD)
-
-#define MAX_RECORD_BYTES (8*1024) /* 4 kbytes */
-
-struct record {
- uint8_t tag; /* Tag */
- uint8_t len[2]; /* Length */
- uint8_t par; /* Version */
- uint8_t contents[MAX_RECORD_BYTES];/* Record Data */
- bool any_rec_flag;
-};
-
-char *rsn_str[] = {"RSN = HAB_RSN_ANY (0x00)\n",
- "RSN = HAB_ENG_FAIL (0x30)\n",
- "RSN = HAB_INV_ADDRESS (0x22)\n",
- "RSN = HAB_INV_ASSERTION (0x0C)\n",
- "RSN = HAB_INV_CALL (0x28)\n",
- "RSN = HAB_INV_CERTIFICATE (0x21)\n",
- "RSN = HAB_INV_COMMAND (0x06)\n",
- "RSN = HAB_INV_CSF (0x11)\n",
- "RSN = HAB_INV_DCD (0x27)\n",
- "RSN = HAB_INV_INDEX (0x0F)\n",
- "RSN = HAB_INV_IVT (0x05)\n",
- "RSN = HAB_INV_KEY (0x1D)\n",
- "RSN = HAB_INV_RETURN (0x1E)\n",
- "RSN = HAB_INV_SIGNATURE (0x18)\n",
- "RSN = HAB_INV_SIZE (0x17)\n",
- "RSN = HAB_MEM_FAIL (0x2E)\n",
- "RSN = HAB_OVR_COUNT (0x2B)\n",
- "RSN = HAB_OVR_STORAGE (0x2D)\n",
- "RSN = HAB_UNS_ALGORITHM (0x12)\n",
- "RSN = HAB_UNS_COMMAND (0x03)\n",
- "RSN = HAB_UNS_ENGINE (0x0A)\n",
- "RSN = HAB_UNS_ITEM (0x24)\n",
- "RSN = HAB_UNS_KEY (0x1B)\n",
- "RSN = HAB_UNS_PROTOCOL (0x14)\n",
- "RSN = HAB_UNS_STATE (0x09)\n",
- "RSN = INVALID\n",
- NULL};
-
-char *sts_str[] = {"STS = HAB_SUCCESS (0xF0)\n",
- "STS = HAB_FAILURE (0x33)\n",
- "STS = HAB_WARNING (0x69)\n",
- "STS = INVALID\n",
- NULL};
-
-char *eng_str[] = {"ENG = HAB_ENG_ANY (0x00)\n",
- "ENG = HAB_ENG_SCC (0x03)\n",
- "ENG = HAB_ENG_RTIC (0x05)\n",
- "ENG = HAB_ENG_SAHARA (0x06)\n",
- "ENG = HAB_ENG_CSU (0x0A)\n",
- "ENG = HAB_ENG_SRTC (0x0C)\n",
- "ENG = HAB_ENG_DCP (0x1B)\n",
- "ENG = HAB_ENG_CAAM (0x1D)\n",
- "ENG = HAB_ENG_SNVS (0x1E)\n",
- "ENG = HAB_ENG_OCOTP (0x21)\n",
- "ENG = HAB_ENG_DTCP (0x22)\n",
- "ENG = HAB_ENG_ROM (0x36)\n",
- "ENG = HAB_ENG_HDCP (0x24)\n",
- "ENG = HAB_ENG_RTL (0x77)\n",
- "ENG = HAB_ENG_SW (0xFF)\n",
- "ENG = INVALID\n",
- NULL};
-
-char *ctx_str[] = {"CTX = HAB_CTX_ANY(0x00)\n",
- "CTX = HAB_CTX_FAB (0xFF)\n",
- "CTX = HAB_CTX_ENTRY (0xE1)\n",
- "CTX = HAB_CTX_TARGET (0x33)\n",
- "CTX = HAB_CTX_AUTHENTICATE (0x0A)\n",
- "CTX = HAB_CTX_DCD (0xDD)\n",
- "CTX = HAB_CTX_CSF (0xCF)\n",
- "CTX = HAB_CTX_COMMAND (0xC0)\n",
- "CTX = HAB_CTX_AUT_DAT (0xDB)\n",
- "CTX = HAB_CTX_ASSERT (0xA0)\n",
- "CTX = HAB_CTX_EXIT (0xEE)\n",
- "CTX = INVALID\n",
- NULL};
-
-uint8_t hab_statuses[5] = {
- HAB_STS_ANY,
- HAB_FAILURE,
- HAB_WARNING,
- HAB_SUCCESS,
- -1
-};
-
-uint8_t hab_reasons[26] = {
- HAB_RSN_ANY,
- HAB_ENG_FAIL,
- HAB_INV_ADDRESS,
- HAB_INV_ASSERTION,
- HAB_INV_CALL,
- HAB_INV_CERTIFICATE,
- HAB_INV_COMMAND,
- HAB_INV_CSF,
- HAB_INV_DCD,
- HAB_INV_INDEX,
- HAB_INV_IVT,
- HAB_INV_KEY,
- HAB_INV_RETURN,
- HAB_INV_SIGNATURE,
- HAB_INV_SIZE,
- HAB_MEM_FAIL,
- HAB_OVR_COUNT,
- HAB_OVR_STORAGE,
- HAB_UNS_ALGORITHM,
- HAB_UNS_COMMAND,
- HAB_UNS_ENGINE,
- HAB_UNS_ITEM,
- HAB_UNS_KEY,
- HAB_UNS_PROTOCOL,
- HAB_UNS_STATE,
- -1
-};
-
-uint8_t hab_contexts[12] = {
- HAB_CTX_ANY,
- HAB_CTX_FAB,
- HAB_CTX_ENTRY,
- HAB_CTX_TARGET,
- HAB_CTX_AUTHENTICATE,
- HAB_CTX_DCD,
- HAB_CTX_CSF,
- HAB_CTX_COMMAND,
- HAB_CTX_AUT_DAT,
- HAB_CTX_ASSERT,
- HAB_CTX_EXIT,
- -1
-};
-
-uint8_t hab_engines[16] = {
- HAB_ENG_ANY,
- HAB_ENG_SCC,
- HAB_ENG_RTIC,
- HAB_ENG_SAHARA,
- HAB_ENG_CSU,
- HAB_ENG_SRTC,
- HAB_ENG_DCP,
- HAB_ENG_CAAM,
- HAB_ENG_SNVS,
- HAB_ENG_OCOTP,
- HAB_ENG_DTCP,
- HAB_ENG_ROM,
- HAB_ENG_HDCP,
- HAB_ENG_RTL,
- HAB_ENG_SW,
- -1
-};
-
-static inline uint8_t get_idx(uint8_t *list, uint8_t tgt)
-{
- uint8_t idx = 0;
- uint8_t element = list[idx];
- while (element != -1) {
- if (element == tgt)
- return idx;
- element = list[++idx];
- }
- return -1;
-}
-
-void process_event_record(uint8_t *event_data, size_t bytes)
-{
- struct record *rec = (struct record *)event_data;
-
- printf("\n\n%s", sts_str[get_idx(hab_statuses, rec->contents[0])]);
- printf("%s", rsn_str[get_idx(hab_reasons, rec->contents[1])]);
- printf("%s", ctx_str[get_idx(hab_contexts, rec->contents[2])]);
- printf("%s", eng_str[get_idx(hab_engines, rec->contents[3])]);
-}
-
-void display_event(uint8_t *event_data, size_t bytes)
-{
- uint32_t i;
-
- if (!(event_data && bytes > 0))
- return;
-
- for (i = 0; i < bytes; i++) {
- if (i == 0)
- printf("\t0x%02x", event_data[i]);
- else if ((i % 8) == 0)
- printf("\n\t0x%02x", event_data[i]);
- else
- printf(" 0x%02x", event_data[i]);
- }
-
- process_event_record(event_data, bytes);
-}
-
-int get_hab_status(void)
-{
- uint32_t index = 0; /* Loop index */
- uint8_t event_data[128]; /* Event data buffer */
- size_t bytes = sizeof(event_data); /* Event size in bytes */
- enum hab_config config = 0;
- enum hab_state state = 0;
- hab_rvt_report_event_t *hab_rvt_report_event;
- hab_rvt_report_status_t *hab_rvt_report_status;
-
- hab_rvt_report_event = hab_rvt_report_event_p;
- hab_rvt_report_status = hab_rvt_report_status_p;
-
- if (is_hab_enabled())
- puts("\nSecure boot enabled\n");
- else
- puts("\nSecure boot disabled\n");
-
- /* Check HAB status */
- if (hab_rvt_report_status(&config, &state) != HAB_SUCCESS) {
- printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n",
- config, state);
-
- /* Display HAB Error events */
- while (hab_rvt_report_event(HAB_FAILURE, index, event_data,
- &bytes) == HAB_SUCCESS) {
- puts("\n");
- printf("--------- HAB Event %d -----------------\n",
- index + 1);
- puts("event data:\n");
- display_event(event_data, bytes);
- puts("\n");
- bytes = sizeof(event_data);
- index++;
- }
- }
- /* Display message if no HAB events are found */
- else {
- printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n",
- config, state);
- puts("No HAB Events Found!\n\n");
- }
- return 0;
-}
-
-int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- if ((argc != 1)) {
- cmd_usage(cmdtp);
- return 1;
- }
-
- get_hab_status();
-
- return 0;
-}
-
-static int do_authenticate_image(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- ulong addr, ivt_offset;
- int rcode = 0;
-
- if (argc < 3)
- return CMD_RET_USAGE;
-
- addr = simple_strtoul(argv[1], NULL, 16);
- ivt_offset = simple_strtoul(argv[2], NULL, 16);
-
- rcode = authenticate_image(addr, ivt_offset);
-
- return rcode;
-}
-
-U_BOOT_CMD(
- hab_status, CONFIG_SYS_MAXARGS, 1, do_hab_status,
- "display HAB status",
- ""
- );
-
-U_BOOT_CMD(
- hab_auth_img, 3, 0, do_authenticate_image,
- "authenticate image via HAB",
- "addr ivt_offset\n"
- "addr - image hex address\n"
- "ivt_offset - hex offset of IVT in the image"
- );
-
-
-#endif /* !defined(CONFIG_SPL_BUILD) */
-
-static bool is_hab_enabled(void)
-{
- struct imx_sec_config_fuse_t *fuse =
- (struct imx_sec_config_fuse_t *)&imx_sec_config_fuse;
- uint32_t reg;
- int ret;
-
- ret = fuse_read(fuse->bank, fuse->word, ®);
- if (ret) {
- puts("\nSecure boot fuse read error\n");
- return ret;
- }
-
- return (reg & IS_HAB_ENABLED_BIT) == IS_HAB_ENABLED_BIT;
-}
-
-uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size)
-{
- uint32_t load_addr = 0;
- size_t bytes;
- ptrdiff_t ivt_offset = 0;
- int result = 0;
- ulong start;
- hab_rvt_authenticate_image_t *hab_rvt_authenticate_image;
- hab_rvt_entry_t *hab_rvt_entry;
- hab_rvt_exit_t *hab_rvt_exit;
-
- hab_rvt_authenticate_image = hab_rvt_authenticate_image_p;
- hab_rvt_entry = hab_rvt_entry_p;
- hab_rvt_exit = hab_rvt_exit_p;
-
- if (is_hab_enabled()) {
- printf("\nAuthenticate image from DDR location 0x%x...\n",
- ddr_start);
-
- hab_caam_clock_enable(1);
-
- if (hab_rvt_entry() == HAB_SUCCESS) {
- /* If not already aligned, Align to ALIGN_SIZE */
- ivt_offset = (image_size + ALIGN_SIZE - 1) &
- ~(ALIGN_SIZE - 1);
-
- start = ddr_start;
- bytes = ivt_offset + IVT_SIZE + CSF_PAD_SIZE;
-#ifdef DEBUG
- printf("\nivt_offset = 0x%x, ivt addr = 0x%x\n",
- ivt_offset, ddr_start + ivt_offset);
- puts("Dumping IVT\n");
- print_buffer(ddr_start + ivt_offset,
- (void *)(ddr_start + ivt_offset),
- 4, 0x8, 0);
-
- puts("Dumping CSF Header\n");
- print_buffer(ddr_start + ivt_offset+IVT_SIZE,
- (void *)(ddr_start + ivt_offset+IVT_SIZE),
- 4, 0x10, 0);
-
-#if !defined(CONFIG_SPL_BUILD)
- get_hab_status();
-#endif
-
- puts("\nCalling authenticate_image in ROM\n");
- printf("\tivt_offset = 0x%x\n", ivt_offset);
- printf("\tstart = 0x%08lx\n", start);
- printf("\tbytes = 0x%x\n", bytes);
-#endif
- /*
- * If the MMU is enabled, we have to notify the ROM
- * code, or it won't flush the caches when needed.
- * This is done, by setting the "pu_irom_mmu_enabled"
- * word to 1. You can find its address by looking in
- * the ROM map. This is critical for
- * authenticate_image(). If MMU is enabled, without
- * setting this bit, authentication will fail and may
- * crash.
- */
- /* Check MMU enabled */
- if (is_soc_type(MXC_SOC_MX6) && get_cr() & CR_M) {
- if (is_mx6dq()) {
- /*
- * This won't work on Rev 1.0.0 of
- * i.MX6Q/D, since their ROM doesn't
- * do cache flushes. don't think any
- * exist, so we ignore them.
- */
- if (!is_mx6dqp())
- writel(1, MX6DQ_PU_IROM_MMU_EN_VAR);
- } else if (is_mx6sdl()) {
- writel(1, MX6DLS_PU_IROM_MMU_EN_VAR);
- } else if (is_mx6sl()) {
- writel(1, MX6SL_PU_IROM_MMU_EN_VAR);
- }
- }
-
- load_addr = (uint32_t)hab_rvt_authenticate_image(
- HAB_CID_UBOOT,
- ivt_offset, (void **)&start,
- (size_t *)&bytes, NULL);
- if (hab_rvt_exit() != HAB_SUCCESS) {
- puts("hab exit function fail\n");
- load_addr = 0;
- }
- } else {
- puts("hab entry function fail\n");
- }
-
- hab_caam_clock_enable(0);
-
-#if !defined(CONFIG_SPL_BUILD)
- get_hab_status();
-#endif
- } else {
- puts("hab fuse not enabled\n");
- }
-
- if ((!is_hab_enabled()) || (load_addr != 0))
- result = 1;
-
- return result;
-}
+++ /dev/null
-/*
- * Copyright (C) 2012 Boundary Devices Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <malloc.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <linux/errno.h>
-#include <asm/gpio.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <watchdog.h>
-
-int force_idle_bus(void *priv)
-{
- int i;
- int sda, scl;
- ulong elapsed, start_time;
- struct i2c_pads_info *p = (struct i2c_pads_info *)priv;
- int ret = 0;
-
- gpio_direction_input(p->sda.gp);
- gpio_direction_input(p->scl.gp);
-
- imx_iomux_v3_setup_pad(p->sda.gpio_mode);
- imx_iomux_v3_setup_pad(p->scl.gpio_mode);
-
- sda = gpio_get_value(p->sda.gp);
- scl = gpio_get_value(p->scl.gp);
- if ((sda & scl) == 1)
- goto exit; /* Bus is idle already */
-
- printf("%s: sda=%d scl=%d sda.gp=0x%x scl.gp=0x%x\n", __func__,
- sda, scl, p->sda.gp, p->scl.gp);
- /* Send high and low on the SCL line */
- for (i = 0; i < 9; i++) {
- gpio_direction_output(p->scl.gp, 0);
- udelay(50);
- gpio_direction_input(p->scl.gp);
- udelay(50);
- }
- start_time = get_timer(0);
- for (;;) {
- sda = gpio_get_value(p->sda.gp);
- scl = gpio_get_value(p->scl.gp);
- if ((sda & scl) == 1)
- break;
- WATCHDOG_RESET();
- elapsed = get_timer(start_time);
- if (elapsed > (CONFIG_SYS_HZ / 5)) { /* .2 seconds */
- ret = -EBUSY;
- printf("%s: failed to clear bus, sda=%d scl=%d\n",
- __func__, sda, scl);
- break;
- }
- }
-exit:
- imx_iomux_v3_setup_pad(p->sda.i2c_mode);
- imx_iomux_v3_setup_pad(p->scl.i2c_mode);
- return ret;
-}
-
-static void * const i2c_bases[] = {
- (void *)I2C1_BASE_ADDR,
- (void *)I2C2_BASE_ADDR,
-#ifdef I2C3_BASE_ADDR
- (void *)I2C3_BASE_ADDR,
-#endif
-#ifdef I2C4_BASE_ADDR
- (void *)I2C4_BASE_ADDR,
-#endif
-};
-
-/* i2c_index can be from 0 - 3 */
-int setup_i2c(unsigned i2c_index, int speed, int slave_addr,
- struct i2c_pads_info *p)
-{
- char name[9];
- int ret;
-
- if (i2c_index >= ARRAY_SIZE(i2c_bases))
- return -EINVAL;
-
- snprintf(name, sizeof(name), "i2c_sda%01d", i2c_index);
- ret = gpio_request(p->sda.gp, name);
- if (ret)
- return ret;
-
- snprintf(name, sizeof(name), "i2c_scl%01d", i2c_index);
- ret = gpio_request(p->scl.gp, name);
- if (ret)
- goto err_req;
-
- /* Enable i2c clock */
- ret = enable_i2c_clk(1, i2c_index);
- if (ret)
- goto err_clk;
-
- /* Make sure bus is idle */
- ret = force_idle_bus(p);
- if (ret)
- goto err_idle;
-
-#ifndef CONFIG_DM_I2C
- bus_i2c_init(i2c_index, speed, slave_addr, force_idle_bus, p);
-#endif
-
- return 0;
-
-err_idle:
-err_clk:
- gpio_free(p->scl.gp);
-err_req:
- gpio_free(p->sda.gp);
-
- return ret;
-}
+++ /dev/null
-/*
- * Copyright (C) 2016 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-
-/* Allow for arch specific config before we boot */
-static int __arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
-{
- /* please define platform specific arch_auxiliary_core_up() */
- return CMD_RET_FAILURE;
-}
-
-int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
- __attribute__((weak, alias("__arch_auxiliary_core_up")));
-
-/* Allow for arch specific config before we boot */
-static int __arch_auxiliary_core_check_up(u32 core_id)
-{
- /* please define platform specific arch_auxiliary_core_check_up() */
- return 0;
-}
-
-int arch_auxiliary_core_check_up(u32 core_id)
- __attribute__((weak, alias("__arch_auxiliary_core_check_up")));
-
-/*
- * To i.MX6SX and i.MX7D, the image supported by bootaux needs
- * the reset vector at the head for the image, with SP and PC
- * as the first two words.
- *
- * Per the cortex-M reference manual, the reset vector of M4 needs
- * to exist at 0x0 (TCMUL). The PC and SP are the first two addresses
- * of that vector. So to boot M4, the A core must build the M4's reset
- * vector with getting the PC and SP from image and filling them to
- * TCMUL. When M4 is kicked, it will load the PC and SP by itself.
- * The TCMUL is mapped to (M4_BOOTROM_BASE_ADDR) at A core side for
- * accessing the M4 TCMUL.
- */
-int do_bootaux(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- ulong addr;
- int ret, up;
-
- if (argc < 2)
- return CMD_RET_USAGE;
-
- up = arch_auxiliary_core_check_up(0);
- if (up) {
- printf("## Auxiliary core is already up\n");
- return CMD_RET_SUCCESS;
- }
-
- addr = simple_strtoul(argv[1], NULL, 16);
-
- printf("## Starting auxiliary core at 0x%08lX ...\n", addr);
-
- ret = arch_auxiliary_core_up(0, addr);
- if (ret)
- return CMD_RET_FAILURE;
-
- return CMD_RET_SUCCESS;
-}
-
-U_BOOT_CMD(
- bootaux, CONFIG_SYS_MAXARGS, 1, do_bootaux,
- "Start auxiliary core",
- ""
-);
+++ /dev/null
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/arch/crm_regs.h>
-
-void init_aips(void)
-{
- struct aipstz_regs *aips1, *aips2, *aips3;
-
- aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
- aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
- aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
-
- /*
- * Set all MPROTx to be non-bufferable, trusted for R/W,
- * not forced to user-mode.
- */
- writel(0x77777777, &aips1->mprot0);
- writel(0x77777777, &aips1->mprot1);
- writel(0x77777777, &aips2->mprot0);
- writel(0x77777777, &aips2->mprot1);
-
- /*
- * Set all OPACRx to be non-bufferable, not require
- * supervisor privilege level for access,allow for
- * write access and untrusted master access.
- */
- writel(0x00000000, &aips1->opacr0);
- writel(0x00000000, &aips1->opacr1);
- writel(0x00000000, &aips1->opacr2);
- writel(0x00000000, &aips1->opacr3);
- writel(0x00000000, &aips1->opacr4);
- writel(0x00000000, &aips2->opacr0);
- writel(0x00000000, &aips2->opacr1);
- writel(0x00000000, &aips2->opacr2);
- writel(0x00000000, &aips2->opacr3);
- writel(0x00000000, &aips2->opacr4);
-
- if (is_mx6ull() || is_mx6sx() || is_mx7()) {
- /*
- * Set all MPROTx to be non-bufferable, trusted for R/W,
- * not forced to user-mode.
- */
- writel(0x77777777, &aips3->mprot0);
- writel(0x77777777, &aips3->mprot1);
-
- /*
- * Set all OPACRx to be non-bufferable, not require
- * supervisor privilege level for access,allow for
- * write access and untrusted master access.
- */
- writel(0x00000000, &aips3->opacr0);
- writel(0x00000000, &aips3->opacr1);
- writel(0x00000000, &aips3->opacr2);
- writel(0x00000000, &aips3->opacr3);
- writel(0x00000000, &aips3->opacr4);
- }
-}
-
-void imx_set_wdog_powerdown(bool enable)
-{
- struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
- struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
- struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
-#ifdef CONFIG_MX7D
- struct wdog_regs *wdog4 = (struct wdog_regs *)WDOG4_BASE_ADDR;
-#endif
-
- /* Write to the PDE (Power Down Enable) bit */
- writew(enable, &wdog1->wmcr);
- writew(enable, &wdog2->wmcr);
-
- if (is_mx6sx() || is_mx6ul() || is_mx7())
- writew(enable, &wdog3->wmcr);
-#ifdef CONFIG_MX7D
- writew(enable, &wdog4->wmcr);
-#endif
-}
-
-#define SRC_SCR_WARM_RESET_ENABLE 0
-
-void init_src(void)
-{
- struct src *src_regs = (struct src *)SRC_BASE_ADDR;
- u32 val;
-
- /*
- * force warm reset sources to generate cold reset
- * for a more reliable restart
- */
- val = readl(&src_regs->scr);
- val &= ~(1 << SRC_SCR_WARM_RESET_ENABLE);
- writel(val, &src_regs->scr);
-}
-
-#ifdef CONFIG_CMD_BMODE
-void boot_mode_apply(unsigned cfg_val)
-{
- unsigned reg;
- struct src *psrc = (struct src *)SRC_BASE_ADDR;
- writel(cfg_val, &psrc->gpr9);
- reg = readl(&psrc->gpr10);
- if (cfg_val)
- reg |= 1 << 28;
- else
- reg &= ~(1 << 28);
- writel(reg, &psrc->gpr10);
-}
-#endif
-
-#if defined(CONFIG_MX6)
-u32 imx6_src_get_boot_mode(void)
-{
- if (imx6_is_bmode_from_gpr9())
- return readl(&src_base->gpr9);
- else
- return readl(&src_base->sbmr1);
-}
-#endif
+++ /dev/null
-/*
- * Based on the iomux-v3.c from Linux kernel:
- * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
- * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
- * <armlinux@phytec.de>
- *
- * Copyright (C) 2004-2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/sys_proto.h>
-
-static void *base = (void *)IOMUXC_BASE_ADDR;
-
-/*
- * configures a single pad in the iomuxer
- */
-void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
-{
- u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
- u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
- u32 sel_input_ofs =
- (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
- u32 sel_input =
- (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
- u32 pad_ctrl_ofs =
- (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
- u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
-
-#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
- /* Check whether LVE bit needs to be set */
- if (pad_ctrl & PAD_CTL_LVE) {
- pad_ctrl &= ~PAD_CTL_LVE;
- pad_ctrl |= PAD_CTL_LVE_BIT;
- }
-#endif
-
-#ifdef CONFIG_IOMUX_LPSR
- u32 lpsr = (pad & MUX_MODE_LPSR) >> MUX_MODE_SHIFT;
-
-#ifdef CONFIG_MX7
- if (lpsr == IOMUX_CONFIG_LPSR) {
- base = (void *)IOMUXC_LPSR_BASE_ADDR;
- mux_mode &= ~IOMUX_CONFIG_LPSR;
- /* set daisy chain sel_input */
- if (sel_input_ofs)
- sel_input_ofs += IOMUX_LPSR_SEL_INPUT_OFS;
- }
-#else
- if (is_mx6ull() || is_mx6sll()) {
- if (lpsr == IOMUX_CONFIG_LPSR) {
- base = (void *)IOMUXC_SNVS_BASE_ADDR;
- mux_mode &= ~IOMUX_CONFIG_LPSR;
- }
- }
-#endif
-#endif
-
- if (is_mx7() || is_mx6ull() || is_mx6sll() || mux_ctrl_ofs)
- __raw_writel(mux_mode, base + mux_ctrl_ofs);
-
- if (sel_input_ofs)
- __raw_writel(sel_input, base + sel_input_ofs);
-
-#ifdef CONFIG_IOMUX_SHARE_CONF_REG
- if (!(pad_ctrl & NO_PAD_CTRL))
- __raw_writel((mux_mode << PAD_MUX_MODE_SHIFT) | pad_ctrl,
- base + pad_ctrl_ofs);
-#else
- if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
- __raw_writel(pad_ctrl, base + pad_ctrl_ofs);
-#if defined(CONFIG_MX6SLL)
- else if ((pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
- clrbits_le32(base + pad_ctrl_ofs, PAD_CTL_IPD_BIT);
-#endif
-#endif
-
-#ifdef CONFIG_IOMUX_LPSR
- if (lpsr == IOMUX_CONFIG_LPSR)
- base = (void *)IOMUXC_BASE_ADDR;
-#endif
-
-}
-
-/* configures a list of pads within declared with IOMUX_PADS macro */
-void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
- unsigned count)
-{
- iomux_v3_cfg_t const *p = pad_list;
- int stride;
- int i;
-
-#if defined(CONFIG_MX6QDL)
- stride = 2;
- if (!is_mx6dq() && !is_mx6dqp())
- p += 1;
-#else
- stride = 1;
-#endif
- for (i = 0; i < count; i++) {
- imx_iomux_v3_setup_pad(*p);
- p += stride;
- }
-}
-
-void imx_iomux_set_gpr_register(int group, int start_bit,
- int num_bits, int value)
-{
- int i = 0;
- u32 reg;
- reg = readl(base + group * 4);
- while (num_bits) {
- reg &= ~(1<<(start_bit + i));
- i++;
- num_bits--;
- }
- reg |= (value << start_bit);
- writel(reg, base + group * 4);
-}
-
-#ifdef CONFIG_IOMUX_SHARE_CONF_REG
-void imx_iomux_gpio_set_direction(unsigned int gpio,
- unsigned int direction)
-{
- u32 reg;
- /*
- * Only on Vybrid the input/output buffer enable flags
- * are part of the shared mux/conf register.
- */
- reg = readl(base + (gpio << 2));
-
- if (direction)
- reg |= 0x2;
- else
- reg &= ~0x2;
-
- writel(reg, base + (gpio << 2));
-}
-
-void imx_iomux_gpio_get_function(unsigned int gpio, u32 *gpio_state)
-{
- *gpio_state = readl(base + (gpio << 2)) &
- ((0X07 << PAD_MUX_MODE_SHIFT) | PAD_CTL_OBE_IBE_ENABLE);
-}
-#endif
+++ /dev/null
-/*
- * Copyright 2013 Stefan Roese <sr@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-#include <linux/errno.h>
-#include <asm/io.h>
-#include <asm/imx-common/regs-common.h>
-
-/* 1 second delay should be plenty of time for block reset. */
-#define RESET_MAX_TIMEOUT 1000000
-
-#define MXS_BLOCK_SFTRST (1 << 31)
-#define MXS_BLOCK_CLKGATE (1 << 30)
-
-int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned
- int timeout)
-{
- while (--timeout) {
- if ((readl(®->reg) & mask) == mask)
- break;
- udelay(1);
- }
-
- return !timeout;
-}
-
-int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned
- int timeout)
-{
- while (--timeout) {
- if ((readl(®->reg) & mask) == 0)
- break;
- udelay(1);
- }
-
- return !timeout;
-}
-
-int mxs_reset_block(struct mxs_register_32 *reg)
-{
- /* Clear SFTRST */
- writel(MXS_BLOCK_SFTRST, ®->reg_clr);
-
- if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
- return 1;
-
- /* Clear CLKGATE */
- writel(MXS_BLOCK_CLKGATE, ®->reg_clr);
-
- /* Set SFTRST */
- writel(MXS_BLOCK_SFTRST, ®->reg_set);
-
- /* Wait for CLKGATE being set */
- if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
- return 1;
-
- /* Clear SFTRST */
- writel(MXS_BLOCK_SFTRST, ®->reg_clr);
-
- if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
- return 1;
-
- /* Clear CLKGATE */
- writel(MXS_BLOCK_CLKGATE, ®->reg_clr);
-
- if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
- return 1;
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2016 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/rdc-sema.h>
-#include <asm/arch/imx-rdc.h>
-#include <linux/errno.h>
-
-/*
- * Check if the RDC Semaphore is required for this peripheral.
- */
-static inline int imx_rdc_check_sema_required(int per_id)
-{
- struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
- u32 reg;
-
- reg = readl(&imx_rdc->pdap[per_id]);
- /*
- * No semaphore:
- * Intial value or this peripheral is assigned to only one domain
- */
- if (!(reg & RDC_PDAP_SREQ_MASK))
- return -ENOENT;
-
- return 0;
-}
-
-/*
- * Check the peripheral read / write access permission on Domain [dom_id].
- */
-int imx_rdc_check_permission(int per_id, int dom_id)
-{
- struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
- u32 reg;
-
- reg = readl(&imx_rdc->pdap[per_id]);
- if (!(reg & RDC_PDAP_DRW_MASK(dom_id)))
- return -EACCES; /*No access*/
-
- return 0;
-}
-
-/*
- * Lock up the RDC semaphore for this peripheral if semaphore is required.
- */
-int imx_rdc_sema_lock(int per_id)
-{
- struct rdc_sema_regs *imx_rdc_sema;
- int ret;
- u8 reg;
-
- ret = imx_rdc_check_sema_required(per_id);
- if (ret)
- return ret;
-
- if (per_id < SEMA_GATES_NUM)
- imx_rdc_sema = (struct rdc_sema_regs *)SEMAPHORE1_BASE_ADDR;
- else
- imx_rdc_sema = (struct rdc_sema_regs *)SEMAPHORE2_BASE_ADDR;
-
- do {
- writeb(RDC_SEMA_PROC_ID,
- &imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
- reg = readb(&imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
- if ((reg & RDC_SEMA_GATE_GTFSM_MASK) == RDC_SEMA_PROC_ID)
- break; /* Get the Semaphore*/
- } while (1);
-
- return 0;
-}
-
-/*
- * Unlock the RDC semaphore for this peripheral if main CPU is the
- * semaphore owner.
- */
-int imx_rdc_sema_unlock(int per_id)
-{
- struct rdc_sema_regs *imx_rdc_sema;
- int ret;
- u8 reg;
-
- ret = imx_rdc_check_sema_required(per_id);
- if (ret)
- return ret;
-
- if (per_id < SEMA_GATES_NUM)
- imx_rdc_sema = (struct rdc_sema_regs *)SEMAPHORE1_BASE_ADDR;
- else
- imx_rdc_sema = (struct rdc_sema_regs *)SEMAPHORE2_BASE_ADDR;
-
- reg = readb(&imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
- if ((reg & RDC_SEMA_GATE_GTFSM_MASK) != RDC_SEMA_PROC_ID)
- return -EACCES; /*Not the semaphore owner */
-
- writeb(0x0, &imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
-
- return 0;
-}
-
-/*
- * Setup RDC setting for one peripheral
- */
-int imx_rdc_setup_peri(rdc_peri_cfg_t p)
-{
- struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
- u32 reg = 0;
- u32 share_count = 0;
- u32 peri_id = p & RDC_PERI_MASK;
- u32 domain = (p & RDC_DOMAIN_MASK) >> RDC_DOMAIN_SHIFT_BASE;
-
- /* No domain assigned */
- if (domain == 0)
- return -EINVAL;
-
- reg |= domain;
-
- share_count = (domain & 0x3)
- + ((domain >> 2) & 0x3)
- + ((domain >> 4) & 0x3)
- + ((domain >> 6) & 0x3);
-
- if (share_count > 0x3)
- reg |= RDC_PDAP_SREQ_MASK;
-
- writel(reg, &imx_rdc->pdap[peri_id]);
-
- return 0;
-}
-
-/*
- * Setup RDC settings for multiple peripherals
- */
-int imx_rdc_setup_peripherals(rdc_peri_cfg_t const *peripherals_list,
- unsigned count)
-{
- rdc_peri_cfg_t const *p = peripherals_list;
- int i, ret;
-
- for (i = 0; i < count; i++) {
- ret = imx_rdc_setup_peri(*p);
- if (ret)
- return ret;
- p++;
- }
-
- return 0;
-}
-
-/*
- * Setup RDC setting for one master
- */
-int imx_rdc_setup_ma(rdc_ma_cfg_t p)
-{
- struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
- u32 master_id = (p & RDC_MASTER_MASK) >> RDC_MASTER_SHIFT;
- u32 domain = (p & RDC_DOMAIN_MASK) >> RDC_DOMAIN_SHIFT_BASE;
-
- writel((domain & RDC_MDA_DID_MASK), &imx_rdc->mda[master_id]);
-
- return 0;
-}
-
-/*
- * Setup RDC settings for multiple masters
- */
-int imx_rdc_setup_masters(rdc_ma_cfg_t const *masters_list, unsigned count)
-{
- rdc_ma_cfg_t const *p = masters_list;
- int i, ret;
-
- for (i = 0; i < count; i++) {
- ret = imx_rdc_setup_ma(*p);
- if (ret)
- return ret;
- p++;
- }
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/arch/iomux.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-
-int setup_sata(void)
-{
- struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
- int ret;
-
- if (!is_mx6dq() && !is_mx6dqp())
- return 1;
-
- ret = enable_sata_clock();
- if (ret)
- return ret;
-
- clrsetbits_le32(&iomuxc_regs->gpr[13],
- IOMUXC_GPR13_SATA_MASK,
- IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
- |IOMUXC_GPR13_SATA_PHY_7_SATA2M
- |IOMUXC_GPR13_SATA_SPEED_3G
- |(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
- |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
- |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
- |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
- |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
- |IOMUXC_GPR13_SATA_PHY_1_SLOW);
-
- return 0;
-}
+++ /dev/null
-/*
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/clock.h>
-
-#ifdef CONFIG_FSL_ESDHC
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
-int get_clocks(void)
-{
-#ifdef CONFIG_FSL_ESDHC
-#ifdef CONFIG_FSL_USDHC
-#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
- gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
- gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC4_BASE_ADDR
- gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
-#else
- gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-#endif
-#else
-#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
- gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
- gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC4_BASE_ADDR
- gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
-#else
- gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-#endif
-#endif
-#endif
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2014 Gateworks Corporation
- * Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
- *
- * Author: Tim Harvey <tharvey@gateworks.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/spl.h>
-#include <spl.h>
-#include <asm/imx-common/hab.h>
-
-#if defined(CONFIG_MX6)
-/* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 register */
-u32 spl_boot_device(void)
-{
- unsigned int bmode = readl(&src_base->sbmr2);
- u32 reg = imx6_src_get_boot_mode();
-
- /*
- * Check for BMODE if serial downloader is enabled
- * BOOT_MODE - see IMX6DQRM Table 8-1
- */
- if (((bmode >> 24) & 0x03) == 0x01) /* Serial Downloader */
- return BOOT_DEVICE_UART;
-
- /* BOOT_CFG1[7:4] - see IMX6DQRM Table 8-8 */
- switch ((reg & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
- /* EIM: See 8.5.1, Table 8-9 */
- case IMX6_BMODE_EMI:
- /* BOOT_CFG1[3]: NOR/OneNAND Selection */
- switch ((reg & IMX6_BMODE_EMI_MASK) >> IMX6_BMODE_EMI_SHIFT) {
- case IMX6_BMODE_ONENAND:
- return BOOT_DEVICE_ONENAND;
- case IMX6_BMODE_NOR:
- return BOOT_DEVICE_NOR;
- break;
- }
- /* Reserved: Used to force Serial Downloader */
- case IMX6_BMODE_UART:
- return BOOT_DEVICE_UART;
- /* SATA: See 8.5.4, Table 8-20 */
- case IMX6_BMODE_SATA:
- return BOOT_DEVICE_SATA;
- /* Serial ROM: See 8.5.5.1, Table 8-22 */
- case IMX6_BMODE_SERIAL_ROM:
- /* BOOT_CFG4[2:0] */
- switch ((reg & IMX6_BMODE_SERIAL_ROM_MASK) >>
- IMX6_BMODE_SERIAL_ROM_SHIFT) {
- case IMX6_BMODE_ECSPI1:
- case IMX6_BMODE_ECSPI2:
- case IMX6_BMODE_ECSPI3:
- case IMX6_BMODE_ECSPI4:
- case IMX6_BMODE_ECSPI5:
- return BOOT_DEVICE_SPI;
- case IMX6_BMODE_I2C1:
- case IMX6_BMODE_I2C2:
- case IMX6_BMODE_I2C3:
- return BOOT_DEVICE_I2C;
- }
- break;
- /* SD/eSD: 8.5.3, Table 8-15 */
- case IMX6_BMODE_SD:
- case IMX6_BMODE_ESD:
- return BOOT_DEVICE_MMC1;
- /* MMC/eMMC: 8.5.3 */
- case IMX6_BMODE_MMC:
- case IMX6_BMODE_EMMC:
- return BOOT_DEVICE_MMC1;
- /* NAND Flash: 8.5.2, Table 8-10 */
- case IMX6_BMODE_NAND:
- return BOOT_DEVICE_NAND;
- }
- return BOOT_DEVICE_NONE;
-}
-#endif
-
-#if defined(CONFIG_SPL_MMC_SUPPORT)
-/* called from spl_mmc to see type of boot mode for storage (RAW or FAT) */
-u32 spl_boot_mode(const u32 boot_device)
-{
- switch (spl_boot_device()) {
- /* for MMC return either RAW or FAT mode */
- case BOOT_DEVICE_MMC1:
- case BOOT_DEVICE_MMC2:
-#if defined(CONFIG_SPL_FAT_SUPPORT)
- return MMCSD_MODE_FS;
-#elif defined(CONFIG_SUPPORT_EMMC_BOOT)
- return MMCSD_MODE_EMMCBOOT;
-#else
- return MMCSD_MODE_RAW;
-#endif
- break;
- default:
- puts("spl: ERROR: unsupported device\n");
- hang();
- }
-}
-#endif
-
-#if defined(CONFIG_SECURE_BOOT)
-
-__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
-{
- typedef void __noreturn (*image_entry_noargs_t)(void);
-
- image_entry_noargs_t image_entry =
- (image_entry_noargs_t)(unsigned long)spl_image->entry_point;
-
- debug("image entry point: 0x%lX\n", spl_image->entry_point);
-
- /* HAB looks for the CSF at the end of the authenticated data therefore,
- * we need to subtract the size of the CSF from the actual filesize */
- if (authenticate_image(spl_image->load_addr,
- spl_image->size - CONFIG_CSF_SIZE)) {
- image_entry();
- } else {
- puts("spl: ERROR: image authentication unsuccessful\n");
- hang();
- }
-}
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#define __ASSEMBLY__
-#include <config.h>
-
-IMAGE_VERSION 2
-BOOT_FROM sd
-
-/*
- * Secure boot support
- */
-#ifdef CONFIG_SECURE_BOOT
-CSF CONFIG_CSF_SIZE
-#endif
\ No newline at end of file
+++ /dev/null
-/*
- * Copyright (C) 2015 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * The file use ls102xa/timer.c as a reference.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <div64.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/syscounter.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * This function is intended for SHORT delays only.
- * It will overflow at around 10 seconds @ 400MHz,
- * or 20 seconds @ 200MHz.
- */
-unsigned long usec2ticks(unsigned long usec)
-{
- ulong ticks;
-
- if (usec < 1000)
- ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000;
- else
- ticks = ((usec / 10) * (get_tbclk() / 100000));
-
- return ticks;
-}
-
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
- unsigned long freq;
-
- asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
-
- tick *= CONFIG_SYS_HZ;
- do_div(tick, freq);
-
- return tick;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long usec)
-{
- unsigned long freq;
-
- asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
-
- usec = usec * freq + 999999;
- do_div(usec, 1000000);
-
- return usec;
-}
-
-int timer_init(void)
-{
- struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR;
- unsigned long val, freq;
-
- freq = CONFIG_SC_TIMER_CLK;
- asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
-
- writel(freq, &sctr->cntfid0);
-
- /* Enable system counter */
- val = readl(&sctr->cntcr);
- val &= ~(SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1);
- val |= SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG;
- writel(val, &sctr->cntcr);
-
- gd->arch.tbl = 0;
- gd->arch.tbu = 0;
-
- return 0;
-}
-
-unsigned long long get_ticks(void)
-{
- unsigned long long now;
-
- asm("mrrc p15, 0, %Q0, %R0, c14" : "=r" (now));
-
- gd->arch.tbl = (unsigned long)(now & 0xffffffff);
- gd->arch.tbu = (unsigned long)(now >> 32);
-
- return now;
-}
-
-ulong get_timer_masked(void)
-{
- return tick_to_time(get_ticks());
-}
-
-ulong get_timer(ulong base)
-{
- return get_timer_masked() - base;
-}
-
-void __udelay(unsigned long usec)
-{
- unsigned long long tmp;
- ulong tmo;
-
- tmo = us_to_tick(usec);
- tmp = get_ticks() + tmo; /* get current timestamp */
-
- while (get_ticks() < tmp) /* loop till event */
- /*NOP*/;
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- unsigned long freq;
-
- asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
-
- return freq;
-}
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <div64.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-
-/* General purpose timers registers */
-struct mxc_gpt {
- unsigned int control;
- unsigned int prescaler;
- unsigned int status;
- unsigned int nouse[6];
- unsigned int counter;
-};
-
-static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
-
-/* General purpose timers bitfields */
-#define GPTCR_SWR (1 << 15) /* Software reset */
-#define GPTCR_24MEN (1 << 10) /* Enable 24MHz clock input */
-#define GPTCR_FRR (1 << 9) /* Freerun / restart */
-#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source 32khz */
-#define GPTCR_CLKSOURCE_OSC (5 << 6) /* Clock source OSC */
-#define GPTCR_CLKSOURCE_PRE (1 << 6) /* Clock source PRECLK */
-#define GPTCR_CLKSOURCE_MASK (0x7 << 6)
-#define GPTCR_TEN 1 /* Timer enable */
-
-#define GPTPR_PRESCALER24M_SHIFT 12
-#define GPTPR_PRESCALER24M_MASK (0xF << GPTPR_PRESCALER24M_SHIFT)
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static inline int gpt_has_clk_source_osc(void)
-{
-#if defined(CONFIG_MX6)
- if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) ||
- is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul() ||
- is_mx6ull() || is_mx6sll())
- return 1;
-
- return 0;
-#else
- return 0;
-#endif
-}
-
-static inline ulong gpt_get_clk(void)
-{
-#ifdef CONFIG_MXC_GPT_HCLK
- if (gpt_has_clk_source_osc())
- return MXC_HCLK >> 3;
- else
- return mxc_get_clock(MXC_IPG_PERCLK);
-#else
- return MXC_CLK32;
-#endif
-}
-
-int timer_init(void)
-{
- int i;
-
- /* setup GP Timer 1 */
- __raw_writel(GPTCR_SWR, &cur_gpt->control);
-
- /* We have no udelay by now */
- for (i = 0; i < 100; i++)
- __raw_writel(0, &cur_gpt->control);
-
- i = __raw_readl(&cur_gpt->control);
- i &= ~GPTCR_CLKSOURCE_MASK;
-
-#ifdef CONFIG_MXC_GPT_HCLK
- if (gpt_has_clk_source_osc()) {
- i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
-
- /*
- * For DL/S, SX, UL, ULL, SLL set 24Mhz OSC
- * Enable bit and prescaler
- */
- if (is_mx6sdl() || is_mx6sx() || is_mx6ul() || is_mx6ull() ||
- is_mx6sll()) {
- i |= GPTCR_24MEN;
-
- /* Produce 3Mhz clock */
- __raw_writel((7 << GPTPR_PRESCALER24M_SHIFT),
- &cur_gpt->prescaler);
- }
- } else {
- i |= GPTCR_CLKSOURCE_PRE | GPTCR_TEN;
- }
-#else
- __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */
- i |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
-#endif
- __raw_writel(i, &cur_gpt->control);
-
- return 0;
-}
-
-unsigned long timer_read_counter(void)
-{
- return __raw_readl(&cur_gpt->counter); /* current tick value */
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- return gpt_get_clk();
-}
-
-/*
- * This function is intended for SHORT delays only.
- * It will overflow at around 10 seconds @ 400MHz,
- * or 20 seconds @ 200MHz.
- */
-unsigned long usec2ticks(unsigned long _usec)
-{
- unsigned long long usec = _usec;
-
- usec *= get_tbclk();
- usec += 999999;
- do_div(usec, 1000000);
-
- return usec;
-}
+++ /dev/null
-/*
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/errno.h>
-#include <asm/imx-common/video.h>
-
-int board_video_skip(void)
-{
- int i;
- int ret;
- char const *panel = getenv("panel");
-
- if (!panel) {
- for (i = 0; i < display_count; i++) {
- struct display_info_t const *dev = displays+i;
- if (dev->detect && dev->detect(dev)) {
- panel = dev->mode.name;
- printf("auto-detected panel %s\n", panel);
- break;
- }
- }
- if (!panel) {
- panel = displays[0].mode.name;
- printf("No panel detected: default to %s\n", panel);
- i = 0;
- }
- } else {
- for (i = 0; i < display_count; i++) {
- if (!strcmp(panel, displays[i].mode.name))
- break;
- }
- }
-
- if (i < display_count) {
- ret = ipuv3_fb_init(&displays[i].mode, displays[i].di ? 1 : 0,
- displays[i].pixfmt);
- if (!ret) {
- if (displays[i].enable)
- displays[i].enable(displays + i);
-
- printf("Display: %s (%ux%u)\n",
- displays[i].mode.name,
- displays[i].mode.xres,
- displays[i].mode.yres);
- } else
- printf("LCD %s cannot be configured: %d\n",
- displays[i].mode.name, ret);
- } else {
- printf("unsupported panel %s\n", panel);
- return -EINVAL;
- }
-
- return 0;
-}
-
-#ifdef CONFIG_IMX_HDMI
-#include <asm/arch/mxc_hdmi.h>
-#include <asm/io.h>
-int detect_hdmi(struct display_info_t const *dev)
-{
- struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
- return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT;
-}
-#endif
--- /dev/null
+/*
+ * (C) Copyright 2017 - Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MESON_GPIO_H
+#define __ASM_ARCH_MESON_GPIO_H
+
+
+#endif /* __ASM_ARCH_MESON_GPIO_H */
#ifndef __ASM_ARCH_MX25_GPIO_H
#define __ASM_ARCH_MX25_GPIO_H
-#include <asm/imx-common/gpio.h>
+#include <asm/mach-imx/gpio.h>
#endif
#ifndef __IOMUX_MX25_H__
#define __IOMUX_MX25_H__
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
/* Pad control groupings */
#define MX25_KPP_ROW_PAD_CTRL PAD_CTL_PUS_100K_UP
#ifndef __ASM_ARCH_MX31_GPIO_H
#define __ASM_ARCH_MX31_GPIO_H
-#include <asm/imx-common/gpio.h>
+#include <asm/mach-imx/gpio.h>
#endif
#ifndef _MX31_SYS_PROTO_H_
#define _MX31_SYS_PROTO_H_
-#include <asm/imx-common/sys_proto.h>
+#include <asm/mach-imx/sys_proto.h>
struct mxc_weimcs {
u32 upper;
#ifndef __ASM_ARCH_MX35_GPIO_H
#define __ASM_ARCH_MX35_GPIO_H
-#include <asm/imx-common/gpio.h>
+#include <asm/mach-imx/gpio.h>
#endif
#ifndef __IOMUX_MX35_H__
#define __IOMUX_MX35_H__
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
/*
* The naming convention for the pad modes is MX35_PAD_<padname>__<padmode>
#ifndef _MX35_SYS_PROTO_H_
#define _MX35_SYS_PROTO_H_
-#include <asm/imx-common/sys_proto.h>
+#include <asm/mach-imx/sys_proto.h>
void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config, u32 row,
u32 col, u32 dsize, u32 refresh);
#ifndef __ASM_ARCH_MX5_GPIO_H
#define __ASM_ARCH_MX5_GPIO_H
-#include <asm/imx-common/gpio.h>
+#include <asm/mach-imx/gpio.h>
#endif
#ifndef __IOMUX_MX51_H__
#define __IOMUX_MX51_H__
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
/* Pad control groupings */
#define MX51_UART_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH | \
#ifndef __IOMUX_MX53_H__
#define __IOMUX_MX53_H__
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
/* Pad control groupings */
#define MX53_UART_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH | \
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <asm/imx-common/sys_proto.h>
+#include <asm/mach-imx/sys_proto.h>
#ifndef __ASM_ARCH_MX6_GPIO_H
#define __ASM_ARCH_MX6_GPIO_H
-#include <asm/imx-common/gpio.h>
+#include <asm/mach-imx/gpio.h>
#endif /* __ASM_ARCH_MX6_GPIO_H */
#endif
#define FEC_QUIRK_ENET_MAC
-#include <asm/imx-common/regs-lcdif.h>
+#include <asm/mach-imx/regs-lcdif.h>
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
#ifndef __ASM_ARCH_MX6_PINS_H__
#define __ASM_ARCH_MX6_PINS_H__
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
#define MX6_PAD_DECLARE(prefix, name, pco, mc, mm, sio, si, pc) \
prefix##name = IOMUX_PAD(pco, mc, mm, sio, si, pc)
#ifndef __ASM_ARCH_MX6_MX6SL_PINS_H__
#define __ASM_ARCH_MX6_MX6SL_PINS_H__
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
enum {
MX6_PAD_ECSPI1_MISO__ECSPI_MISO = IOMUX_PAD(0x0358, 0x0068, 0, 0x0684, 0, 0),
#ifndef __ASM_ARCH_IMX6SLL_PINS_H__
#define __ASM_ARCH_IMX6SLL_PINS_H__
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
enum {
MX6_PAD_WDOG_B__WDOG1_B = IOMUX_PAD(0x02DC, 0x0014, 0, 0x0000, 0, 0),
#ifndef __ASM_ARCH_MX6_MX6_PINS_H__
#define __ASM_ARCH_MX6_MX6_PINS_H__
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
enum {
MX6_PAD_GPIO1_IO00__I2C1_SCL = IOMUX_PAD(0x035C, 0x0014, IOMUX_CONFIG_SION | 0, 0x07A8, 1, 0),
#ifndef __ASM_ARCH_IMX6UL_PINS_H__
#define __ASM_ARCH_IMX6UL_PINS_H__
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
enum {
#ifndef __ASM_ARCH_IMX6ULL_PINS_H__
#define __ASM_ARCH_IMX6ULL_PINS_H__
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
enum {
MX6_PAD_BOOT_MODE0__GPIO5_IO10 = IOMUX_PAD(0x0044, 0x0000, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <asm/imx-common/sys_proto.h>
+#include <asm/mach-imx/sys_proto.h>
#ifndef __ASM_ARCH_MX7_GPIO_H
#define __ASM_ARCH_MX7_GPIO_H
-#include <asm/imx-common/gpio.h>
+#include <asm/mach-imx/gpio.h>
#endif /* __ASM_ARCH_MX7_GPIO_H */
CONFIG_SYS_FSL_JR0_OFFSET)
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
-#include <asm/imx-common/regs-lcdif.h>
+#include <asm/mach-imx/regs-lcdif.h>
#include <asm/types.h>
extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
#ifndef __ASM_ARCH_MX7_PINS_H__
#define __ASM_ARCH_MX7_PINS_H__
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
#if defined(CONFIG_MX7D)
#include "mx7d_pins.h"
#ifndef __ASM_ARCH_IMX7D_PINS_H__
#define __ASM_ARCH_IMX7D_PINS_H__
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
enum {
MX7D_PAD_GPIO1_IO00__GPIO1_IO0 = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0),
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <asm/imx-common/sys_proto.h>
+#include <asm/mach-imx/sys_proto.h>
void set_wdog_reset(struct wdog_regs *wdog);
#ifndef _SYS_PROTO_MX7ULP_H_
#define _SYS_PROTO_MX7ULP_H_
-#include <asm/imx-common/sys_proto.h>
+#include <asm/mach-imx/sys_proto.h>
#define BT0CFG_LPBOOT_MASK 0x1
#define BT0CFG_DUALBOOT_MASK 0x2
#ifndef __IMX_REGS_H__
#define __IMX_REGS_H__
-#include <asm/imx-common/regs-apbh.h>
+#include <asm/mach-imx/regs-apbh.h>
#include <asm/arch/regs-base.h>
-#include <asm/imx-common/regs-bch.h>
+#include <asm/mach-imx/regs-bch.h>
#include <asm/arch/regs-digctl.h>
-#include <asm/imx-common/regs-gpmi.h>
-#include <asm/imx-common/regs-lcdif.h>
+#include <asm/mach-imx/regs-gpmi.h>
+#include <asm/mach-imx/regs-lcdif.h>
#include <asm/arch/regs-i2c.h>
#include <asm/arch/regs-lradc.h>
#include <asm/arch/regs-ocotp.h>
#ifndef __MX23_REGS_CLKCTRL_H__
#define __MX23_REGS_CLKCTRL_H__
-#include <asm/imx-common/regs-common.h>
+#include <asm/mach-imx/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_clkctrl_regs {
#ifndef __MX28_REGS_CLKCTRL_H__
#define __MX28_REGS_CLKCTRL_H__
-#include <asm/imx-common/regs-common.h>
+#include <asm/mach-imx/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_clkctrl_regs {
#ifndef __MX28_REGS_DIGCTL_H__
#define __MX28_REGS_DIGCTL_H__
-#include <asm/imx-common/regs-common.h>
+#include <asm/mach-imx/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_digctl_regs {
#ifndef __MX28_REGS_I2C_H__
#define __MX28_REGS_I2C_H__
-#include <asm/imx-common/regs-common.h>
+#include <asm/mach-imx/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_i2c_regs {
#ifndef __MX28_REGS_LRADC_H__
#define __MX28_REGS_LRADC_H__
-#include <asm/imx-common/regs-common.h>
+#include <asm/mach-imx/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_lradc_regs {
#ifndef __MX28_REGS_OCOTP_H__
#define __MX28_REGS_OCOTP_H__
-#include <asm/imx-common/regs-common.h>
+#include <asm/mach-imx/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_ocotp_regs {
#ifndef __MX28_REGS_PINCTRL_H__
#define __MX28_REGS_PINCTRL_H__
-#include <asm/imx-common/regs-common.h>
+#include <asm/mach-imx/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_pinctrl_regs {
#ifndef __MX23_REGS_POWER_H__
#define __MX23_REGS_POWER_H__
-#include <asm/imx-common/regs-common.h>
+#include <asm/mach-imx/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_power_regs {
#ifndef __MX28_REGS_POWER_H__
#define __MX28_REGS_POWER_H__
-#include <asm/imx-common/regs-common.h>
+#include <asm/mach-imx/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_power_regs {
#ifndef __MX28_REGS_RTC_H__
#define __MX28_REGS_RTC_H__
-#include <asm/imx-common/regs-common.h>
+#include <asm/mach-imx/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_rtc_regs {
#ifndef __MX28_REGS_SSP_H__
#define __MX28_REGS_SSP_H__
-#include <asm/imx-common/regs-common.h>
+#include <asm/mach-imx/regs-common.h>
#ifndef __ASSEMBLY__
#if defined(CONFIG_MX23)
#ifndef __MX28_REGS_TIMROT_H__
#define __MX28_REGS_TIMROT_H__
-#include <asm/imx-common/regs-common.h>
+#include <asm/mach-imx/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_timrot_regs {
#ifndef __ARCH_ARM___MXS_UARTAPP_H
#define __ARCH_ARM___MXS_UARTAPP_H
-#include <asm/imx-common/regs-common.h>
+#include <asm/mach-imx/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_uartapp_regs {
#ifndef __MXS_SYS_PROTO_H__
#define __MXS_SYS_PROTO_H__
-#include <asm/imx-common/sys_proto.h>
+#include <asm/mach-imx/sys_proto.h>
int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int));
+
/*
* Copyright 2017 Theobroma Systems Design und Consulting GmbH
*
*/
#ifdef CONFIG_SPL_BUILD
- .space 0x4 /* space for the 'RK33' */
+ /*
+ * We need to add 4 bytes of space for the 'RK33' at the
+ * beginning of the executable. However, as we want to keep
+ * this generic and make it applicable to builds that are like
+ * the RK3368 (TPL needs this, SPL doesn't) or the RK3399 (no
+ * TPL, but extra space needed in the SPL), we simply repeat
+ * the 'b reset' with the expectation that the first one will
+ * be overwritten, if this is the first stage contained in the
+ * final image created with mkimage)...
+ */
+ b reset /* may be overwritten --- should be 'nop' or a 'b reset' */
#endif
b reset
struct rk3368_clk_priv {
struct rk3368_cru *cru;
- ulong rate;
- bool has_bwadj;
};
enum {
/* Private data for the clock driver - used by rockchip_get_cru() */
struct rk3399_clk_priv {
struct rk3399_cru *cru;
- ulong rate;
};
struct rk3399_pmuclk_priv {
struct rk3399_pmucru *pmucru;
- ulong rate;
};
struct rk3399_pmucru {
#define PWM_DUTY_POSTIVE (1 << 3)
#define PWM_DUTY_NEGATIVE (0 << 3)
+#define PWM_DUTY_MASK (1 << 3)
#define PWM_INACTIVE_POSTIVE (1 << 4)
#define PWM_INACTIVE_NEGATIVE (0 << 4)
+#define PWM_INACTIVE_MASK (1 << 4)
#define PWM_OUTPUT_LEFT (0 << 5)
#define PWM_OUTPUT_CENTER (1 << 5)
#define __ASM_ARCH_TIMER_H
struct rk_timer {
- unsigned int timer_load_count0;
- unsigned int timer_load_count1;
- unsigned int timer_curr_value0;
- unsigned int timer_curr_value1;
- unsigned int timer_ctrl_reg;
- unsigned int timer_int_status;
+ u32 timer_load_count0;
+ u32 timer_load_count1;
+ u32 timer_curr_value0;
+ u32 timer_curr_value1;
+ u32 timer_ctrl_reg;
+ u32 timer_int_status;
};
void rockchip_timer_init(void);
+++ /dev/null
-/*
- * (C) Copyright 2013
- * Pavel Boldin, Emcraft Systems, paboldin@emcraft.com
- *
- * (C) Copyright 2015
- * Kamil Lulko, <kamil.lulko@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _MACH_FMC_H_
-#define _MACH_FMC_H_
-
-struct stm32_fmc_regs {
- u32 sdcr1; /* Control register 1 */
- u32 sdcr2; /* Control register 2 */
- u32 sdtr1; /* Timing register 1 */
- u32 sdtr2; /* Timing register 2 */
- u32 sdcmr; /* Mode register */
- u32 sdrtr; /* Refresh timing register */
- u32 sdsr; /* Status register */
-};
-
-/*
- * FMC registers base
- */
-#define STM32_SDRAM_FMC ((struct stm32_fmc_regs *)SDRAM_FMC_BASE)
-
-/* Control register SDCR */
-#define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */
-#define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */
-#define FMC_SDCR_SDCLK_SHIFT 10 /* SDRAM clock divisor shift */
-#define FMC_SDCR_WP_SHIFT 9 /* Write protection shift */
-#define FMC_SDCR_CAS_SHIFT 7 /* CAS latency shift */
-#define FMC_SDCR_NB_SHIFT 6 /* Number of banks shift */
-#define FMC_SDCR_MWID_SHIFT 4 /* Memory width shift */
-#define FMC_SDCR_NR_SHIFT 2 /* Number of row address bits shift */
-#define FMC_SDCR_NC_SHIFT 0 /* Number of col address bits shift */
-
-/* Timings register SDTR */
-#define FMC_SDTR_TMRD_SHIFT 0 /* Load mode register to active */
-#define FMC_SDTR_TXSR_SHIFT 4 /* Exit self-refresh time */
-#define FMC_SDTR_TRAS_SHIFT 8 /* Self-refresh time */
-#define FMC_SDTR_TRC_SHIFT 12 /* Row cycle delay */
-#define FMC_SDTR_TWR_SHIFT 16 /* Recovery delay */
-#define FMC_SDTR_TRP_SHIFT 20 /* Row precharge delay */
-#define FMC_SDTR_TRCD_SHIFT 24 /* Row-to-column delay */
-
-
-#define FMC_SDCMR_NRFS_SHIFT 5
-
-#define FMC_SDCMR_MODE_NORMAL 0
-#define FMC_SDCMR_MODE_START_CLOCK 1
-#define FMC_SDCMR_MODE_PRECHARGE 2
-#define FMC_SDCMR_MODE_AUTOREFRESH 3
-#define FMC_SDCMR_MODE_WRITE_MODE 4
-#define FMC_SDCMR_MODE_SELFREFRESH 5
-#define FMC_SDCMR_MODE_POWERDOWN 6
-
-#define FMC_SDCMR_BANK_1 BIT(4)
-#define FMC_SDCMR_BANK_2 BIT(3)
-
-#define FMC_SDCMR_MODE_REGISTER_SHIFT 9
-
-#define FMC_SDSR_BUSY BIT(5)
-
-#define FMC_BUSY_WAIT() do { \
- __asm__ __volatile__ ("dsb" : : : "memory"); \
- while (STM32_SDRAM_FMC->sdsr & FMC_SDSR_BUSY) \
- ; \
- } while (0)
-
-
-#endif /* _MACH_FMC_H_ */
#ifndef _STM32_RCC_H
#define _STM32_RCC_H
+#include <dt-bindings/mfd/stm32f7-rcc.h>
+
/*
* RCC AHB1ENR specific definitions
*/
-#define RCC_AHB1ENR_GPIO_A_EN BIT(0)
-#define RCC_AHB1ENR_GPIO_B_EN BIT(1)
-#define RCC_AHB1ENR_GPIO_C_EN BIT(2)
-#define RCC_AHB1ENR_GPIO_D_EN BIT(3)
-#define RCC_AHB1ENR_GPIO_E_EN BIT(4)
-#define RCC_AHB1ENR_GPIO_F_EN BIT(5)
-#define RCC_AHB1ENR_GPIO_G_EN BIT(6)
-#define RCC_AHB1ENR_GPIO_H_EN BIT(7)
-#define RCC_AHB1ENR_GPIO_I_EN BIT(8)
-#define RCC_AHB1ENR_GPIO_J_EN BIT(9)
-#define RCC_AHB1ENR_GPIO_K_EN BIT(10)
#define RCC_AHB1ENR_ETHMAC_EN BIT(25)
#define RCC_AHB1ENR_ETHMAC_TX_EN BIT(26)
#define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27)
-#define RCC_AHB1ENR_ETHMAC_PTP_EN BIT(28)
-
-/*
- * RCC AHB3ENR specific definitions
- */
-#define RCC_AHB3ENR_FMC_EN BIT(0)
-#define RCC_AHB3ENR_QSPI_EN BIT(1)
/*
* RCC APB1ENR specific definitions
*/
#define RCC_APB1ENR_TIM2EN BIT(0)
-#define RCC_APB1ENR_USART2EN BIT(17)
-#define RCC_APB1ENR_USART3EN BIT(18)
#define RCC_APB1ENR_PWREN BIT(28)
/*
* RCC APB2ENR specific definitions
*/
-#define RCC_APB2ENR_USART1EN BIT(4)
-#define RCC_APB2ENR_USART6EN BIT(5)
#define RCC_APB2ENR_SYSCFGEN BIT(14)
#endif
[5 ... 7] = 256 * 1024
};
-enum clock {
- CLOCK_CORE,
- CLOCK_AHB,
- CLOCK_APB1,
- CLOCK_APB2
-};
#define STM32_BUS_MASK GENMASK(31, 16)
struct stm32_rcc_regs {
};
#define STM32_RCC ((struct stm32_rcc_regs *)RCC_BASE)
-struct stm32_rcc_ext_f7_regs {
- u32 dckcfgr2; /* dedicated clocks configuration register */
-};
-#define STM32_RCC_EXT_F7 ((struct stm32_rcc_ext_f7_regs *) (RCC_BASE + sizeof(struct stm32_rcc_regs)))
-
struct stm32_pwr_regs {
u32 cr1; /* power control register 1 */
u32 csr1; /* power control/status register 2 */
};
#define STM32_PWR ((struct stm32_pwr_regs *)PWR_BASE)
-int configure_clocks(void);
-unsigned long clock_get(enum clock clck);
void stm32_flash_latency_cfg(int latency);
#endif /* _ASM_ARCH_HARDWARE_H */
};
enum periph_clock {
- USART1_CLOCK_CFG = 0,
- USART2_CLOCK_CFG,
- GPIO_A_CLOCK_CFG,
- GPIO_B_CLOCK_CFG,
- GPIO_C_CLOCK_CFG,
- GPIO_D_CLOCK_CFG,
- GPIO_E_CLOCK_CFG,
- GPIO_F_CLOCK_CFG,
- GPIO_G_CLOCK_CFG,
- GPIO_H_CLOCK_CFG,
- GPIO_I_CLOCK_CFG,
- GPIO_J_CLOCK_CFG,
- GPIO_K_CLOCK_CFG,
SYSCFG_CLOCK_CFG,
TIMER2_CLOCK_CFG,
- FMC_CLOCK_CFG,
STMMAC_CLOCK_CFG,
- QSPI_CLOCK_CFG,
};
#endif /* __ASM_ARM_ARCH_PERIPH_H */
* @param node Node to look at
* @return peripheral ID, or PERIPH_ID_NONE if none
*/
-enum periph_id clock_decode_periph_id(const void *blob, int node);
+int clock_decode_periph_id(struct udevice *dev);
/**
* Checks if the oscillator bypass is enabled (XOBP bit)
TEGRA_SOC_UNKNOWN = -1,
};
+/* Tegra system controller (SYSCON) devices */
+enum {
+ TEGRA_SYSCON_PMC,
+};
+
#else /* __ASSEMBLY__ */
#define PRM_RSTCTRL NV_PA_PMC_BASE
#endif
*/
struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type);
-void tegra_xusb_padctl_init(const void *fdt);
+void tegra_xusb_padctl_init(void);
int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy);
int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy);
int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy);
#ifndef __IOMUX_VF610_H__
#define __IOMUX_VF610_H__
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
/* Pad control groupings */
#define VF610_UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_25ohm | \
OMAP_EHCI_PORT_MODE_HSIC,
};
-#ifdef CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS
-#define OMAP_HS_USB_PORTS CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS
-#else
#define OMAP_HS_USB_PORTS 3
-#endif
#define is_ehci_phy_mode(x) ((x) == OMAP_EHCI_PORT_MODE_PHY)
#define is_ehci_tll_mode(x) ((x) == OMAP_EHCI_PORT_MODE_TLL)
+++ /dev/null
-/*
- * Copyright (C) 2012 Boundary Devices Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ASM_BOOT_MODE_H
-#define _ASM_BOOT_MODE_H
-#define MAKE_CFGVAL(cfg1, cfg2, cfg3, cfg4) \
- ((cfg4) << 24) | ((cfg3) << 16) | ((cfg2) << 8) | (cfg1)
-
-enum boot_device {
- WEIM_NOR_BOOT,
- ONE_NAND_BOOT,
- PATA_BOOT,
- SATA_BOOT,
- I2C_BOOT,
- SPI_NOR_BOOT,
- SD1_BOOT,
- SD2_BOOT,
- SD3_BOOT,
- SD4_BOOT,
- MMC1_BOOT,
- MMC2_BOOT,
- MMC3_BOOT,
- MMC4_BOOT,
- NAND_BOOT,
- QSPI_BOOT,
- UNKNOWN_BOOT,
- BOOT_DEV_NUM = UNKNOWN_BOOT,
-};
-
-struct boot_mode {
- const char *name;
- unsigned cfg_val;
-};
-
-void add_board_boot_modes(const struct boot_mode *p);
-void boot_mode_apply(unsigned cfg_val);
-extern const struct boot_mode soc_boot_modes[];
-#endif
+++ /dev/null
-/*
- * Freescale i.MX28 APBH DMA
- *
- * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
- * on behalf of DENX Software Engineering GmbH
- *
- * Based on code from LTIB:
- * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __DMA_H__
-#define __DMA_H__
-
-#include <linux/list.h>
-#include <linux/compiler.h>
-
-#define DMA_PIO_WORDS 15
-#define MXS_DMA_ALIGNMENT ARCH_DMA_MINALIGN
-
-/*
- * MXS DMA channels
- */
-#if defined(CONFIG_MX23)
-enum {
- MXS_DMA_CHANNEL_AHB_APBH_LCDIF = 0,
- MXS_DMA_CHANNEL_AHB_APBH_SSP0,
- MXS_DMA_CHANNEL_AHB_APBH_SSP1,
- MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
- MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
- MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
- MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
- MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
- MXS_MAX_DMA_CHANNELS,
-};
-#elif defined(CONFIG_MX28)
-enum {
- MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0,
- MXS_DMA_CHANNEL_AHB_APBH_SSP1,
- MXS_DMA_CHANNEL_AHB_APBH_SSP2,
- MXS_DMA_CHANNEL_AHB_APBH_SSP3,
- MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
- MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
- MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
- MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
- MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
- MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
- MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
- MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
- MXS_DMA_CHANNEL_AHB_APBH_HSADC,
- MXS_DMA_CHANNEL_AHB_APBH_LCDIF,
- MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
- MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
- MXS_MAX_DMA_CHANNELS,
-};
-#elif defined(CONFIG_MX6) || defined(CONFIG_MX7)
-enum {
- MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0,
- MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
- MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
- MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
- MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
- MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
- MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
- MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
- MXS_MAX_DMA_CHANNELS,
-};
-#endif
-
-/*
- * MXS DMA hardware command.
- *
- * This structure describes the in-memory layout of an entire DMA command,
- * including space for the maximum number of PIO accesses. See the appropriate
- * reference manual for a detailed description of what these fields mean to the
- * DMA hardware.
- */
-#define MXS_DMA_DESC_COMMAND_MASK 0x3
-#define MXS_DMA_DESC_COMMAND_OFFSET 0
-#define MXS_DMA_DESC_COMMAND_NO_DMAXFER 0x0
-#define MXS_DMA_DESC_COMMAND_DMA_WRITE 0x1
-#define MXS_DMA_DESC_COMMAND_DMA_READ 0x2
-#define MXS_DMA_DESC_COMMAND_DMA_SENSE 0x3
-#define MXS_DMA_DESC_CHAIN (1 << 2)
-#define MXS_DMA_DESC_IRQ (1 << 3)
-#define MXS_DMA_DESC_NAND_LOCK (1 << 4)
-#define MXS_DMA_DESC_NAND_WAIT_4_READY (1 << 5)
-#define MXS_DMA_DESC_DEC_SEM (1 << 6)
-#define MXS_DMA_DESC_WAIT4END (1 << 7)
-#define MXS_DMA_DESC_HALT_ON_TERMINATE (1 << 8)
-#define MXS_DMA_DESC_TERMINATE_FLUSH (1 << 9)
-#define MXS_DMA_DESC_PIO_WORDS_MASK (0xf << 12)
-#define MXS_DMA_DESC_PIO_WORDS_OFFSET 12
-#define MXS_DMA_DESC_BYTES_MASK (0xffff << 16)
-#define MXS_DMA_DESC_BYTES_OFFSET 16
-
-struct mxs_dma_cmd {
- unsigned long next;
- unsigned long data;
- union {
- dma_addr_t address;
- unsigned long alternate;
- };
- unsigned long pio_words[DMA_PIO_WORDS];
-};
-
-/*
- * MXS DMA command descriptor.
- *
- * This structure incorporates an MXS DMA hardware command structure, along
- * with metadata.
- */
-#define MXS_DMA_DESC_FIRST (1 << 0)
-#define MXS_DMA_DESC_LAST (1 << 1)
-#define MXS_DMA_DESC_READY (1 << 31)
-
-struct mxs_dma_desc {
- struct mxs_dma_cmd cmd;
- unsigned int flags;
- dma_addr_t address;
- void *buffer;
- struct list_head node;
-} __aligned(MXS_DMA_ALIGNMENT);
-
-/**
- * MXS DMA channel
- *
- * This structure represents a single DMA channel. The MXS platform code
- * maintains an array of these structures to represent every DMA channel in the
- * system (see mxs_dma_channels).
- */
-#define MXS_DMA_FLAGS_IDLE 0
-#define MXS_DMA_FLAGS_BUSY (1 << 0)
-#define MXS_DMA_FLAGS_FREE 0
-#define MXS_DMA_FLAGS_ALLOCATED (1 << 16)
-#define MXS_DMA_FLAGS_VALID (1 << 31)
-
-struct mxs_dma_chan {
- const char *name;
- unsigned long dev;
- struct mxs_dma_device *dma;
- unsigned int flags;
- unsigned int active_num;
- unsigned int pending_num;
- struct list_head active;
- struct list_head done;
-};
-
-struct mxs_dma_desc *mxs_dma_desc_alloc(void);
-void mxs_dma_desc_free(struct mxs_dma_desc *);
-int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc);
-
-int mxs_dma_go(int chan);
-void mxs_dma_init(void);
-int mxs_dma_init_channel(int chan);
-int mxs_dma_release(int chan);
-
-void mxs_dma_circ_start(int chan, struct mxs_dma_desc *pdesc);
-
-#endif /* __DMA_H__ */
+++ /dev/null
-/*
- * Copyright (C) 2011
- * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-#ifndef __ASM_ARCH_IMX_GPIO_H
-#define __ASM_ARCH_IMX_GPIO_H
-
-#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
-/* GPIO registers */
-struct gpio_regs {
- u32 gpio_dr; /* data */
- u32 gpio_dir; /* direction */
- u32 gpio_psr; /* pad satus */
-};
-#endif
-
-#define IMX_GPIO_NR(port, index) ((((port)-1)*32)+((index)&31))
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
-*/
-
-#ifndef __SECURE_MX6Q_H__
-#define __SECURE_MX6Q_H__
-
-#include <linux/types.h>
-
-/* -------- start of HAB API updates ------------*/
-/* The following are taken from HAB4 SIS */
-
-/* Status definitions */
-enum hab_status {
- HAB_STS_ANY = 0x00,
- HAB_FAILURE = 0x33,
- HAB_WARNING = 0x69,
- HAB_SUCCESS = 0xf0
-};
-
-/* Security Configuration definitions */
-enum hab_config {
- HAB_CFG_RETURN = 0x33, /* < Field Return IC */
- HAB_CFG_OPEN = 0xf0, /* < Non-secure IC */
- HAB_CFG_CLOSED = 0xcc /* < Secure IC */
-};
-
-/* State definitions */
-enum hab_state {
- HAB_STATE_INITIAL = 0x33, /* Initialising state (transitory) */
- HAB_STATE_CHECK = 0x55, /* Check state (non-secure) */
- HAB_STATE_NONSECURE = 0x66, /* Non-secure state */
- HAB_STATE_TRUSTED = 0x99, /* Trusted state */
- HAB_STATE_SECURE = 0xaa, /* Secure state */
- HAB_STATE_FAIL_SOFT = 0xcc, /* Soft fail state */
- HAB_STATE_FAIL_HARD = 0xff, /* Hard fail state (terminal) */
- HAB_STATE_NONE = 0xf0, /* No security state machine */
- HAB_STATE_MAX
-};
-
-enum hab_reason {
- HAB_RSN_ANY = 0x00, /* Match any reason */
- HAB_ENG_FAIL = 0x30, /* Engine failure */
- HAB_INV_ADDRESS = 0x22, /* Invalid address: access denied */
- HAB_INV_ASSERTION = 0x0c, /* Invalid assertion */
- HAB_INV_CALL = 0x28, /* Function called out of sequence */
- HAB_INV_CERTIFICATE = 0x21, /* Invalid certificate */
- HAB_INV_COMMAND = 0x06, /* Invalid command: command malformed */
- HAB_INV_CSF = 0x11, /* Invalid csf */
- HAB_INV_DCD = 0x27, /* Invalid dcd */
- HAB_INV_INDEX = 0x0f, /* Invalid index: access denied */
- HAB_INV_IVT = 0x05, /* Invalid ivt */
- HAB_INV_KEY = 0x1d, /* Invalid key */
- HAB_INV_RETURN = 0x1e, /* Failed callback function */
- HAB_INV_SIGNATURE = 0x18, /* Invalid signature */
- HAB_INV_SIZE = 0x17, /* Invalid data size */
- HAB_MEM_FAIL = 0x2e, /* Memory failure */
- HAB_OVR_COUNT = 0x2b, /* Expired poll count */
- HAB_OVR_STORAGE = 0x2d, /* Exhausted storage region */
- HAB_UNS_ALGORITHM = 0x12, /* Unsupported algorithm */
- HAB_UNS_COMMAND = 0x03, /* Unsupported command */
- HAB_UNS_ENGINE = 0x0a, /* Unsupported engine */
- HAB_UNS_ITEM = 0x24, /* Unsupported configuration item */
- HAB_UNS_KEY = 0x1b, /* Unsupported key type/parameters */
- HAB_UNS_PROTOCOL = 0x14, /* Unsupported protocol */
- HAB_UNS_STATE = 0x09, /* Unsuitable state */
- HAB_RSN_MAX
-};
-
-enum hab_context {
- HAB_CTX_ANY = 0x00, /* Match any context */
- HAB_CTX_FAB = 0xff, /* Event logged in hab_fab_test() */
- HAB_CTX_ENTRY = 0xe1, /* Event logged in hab_rvt.entry() */
- HAB_CTX_TARGET = 0x33, /* Event logged in hab_rvt.check_target() */
- HAB_CTX_AUTHENTICATE = 0x0a,/* Logged in hab_rvt.authenticate_image() */
- HAB_CTX_DCD = 0xdd, /* Event logged in hab_rvt.run_dcd() */
- HAB_CTX_CSF = 0xcf, /* Event logged in hab_rvt.run_csf() */
- HAB_CTX_COMMAND = 0xc0, /* Event logged executing csf/dcd command */
- HAB_CTX_AUT_DAT = 0xdb, /* Authenticated data block */
- HAB_CTX_ASSERT = 0xa0, /* Event logged in hab_rvt.assert() */
- HAB_CTX_EXIT = 0xee, /* Event logged in hab_rvt.exit() */
- HAB_CTX_MAX
-};
-
-struct imx_sec_config_fuse_t {
- int bank;
- int word;
-};
-
-#if defined(CONFIG_SECURE_BOOT)
-extern struct imx_sec_config_fuse_t const imx_sec_config_fuse;
-#endif
-
-/*Function prototype description*/
-typedef enum hab_status hab_rvt_report_event_t(enum hab_status, uint32_t,
- uint8_t* , size_t*);
-typedef enum hab_status hab_rvt_report_status_t(enum hab_config *,
- enum hab_state *);
-typedef enum hab_status hab_loader_callback_f_t(void**, size_t*, const void*);
-typedef enum hab_status hab_rvt_entry_t(void);
-typedef enum hab_status hab_rvt_exit_t(void);
-typedef void *hab_rvt_authenticate_image_t(uint8_t, ptrdiff_t,
- void **, size_t *, hab_loader_callback_f_t);
-typedef void hapi_clock_init_t(void);
-
-#define HAB_ENG_ANY 0x00 /* Select first compatible engine */
-#define HAB_ENG_SCC 0x03 /* Security controller */
-#define HAB_ENG_RTIC 0x05 /* Run-time integrity checker */
-#define HAB_ENG_SAHARA 0x06 /* Crypto accelerator */
-#define HAB_ENG_CSU 0x0a /* Central Security Unit */
-#define HAB_ENG_SRTC 0x0c /* Secure clock */
-#define HAB_ENG_DCP 0x1b /* Data Co-Processor */
-#define HAB_ENG_CAAM 0x1d /* CAAM */
-#define HAB_ENG_SNVS 0x1e /* Secure Non-Volatile Storage */
-#define HAB_ENG_OCOTP 0x21 /* Fuse controller */
-#define HAB_ENG_DTCP 0x22 /* DTCP co-processor */
-#define HAB_ENG_ROM 0x36 /* Protected ROM area */
-#define HAB_ENG_HDCP 0x24 /* HDCP co-processor */
-#define HAB_ENG_RTL 0x77 /* RTL simulation engine */
-#define HAB_ENG_SW 0xff /* Software engine */
-
-#ifdef CONFIG_ROM_UNIFIED_SECTIONS
-#define HAB_RVT_BASE 0x00000100
-#else
-#define HAB_RVT_BASE 0x00000094
-#endif
-
-#define HAB_RVT_ENTRY (*(uint32_t *)(HAB_RVT_BASE + 0x04))
-#define HAB_RVT_EXIT (*(uint32_t *)(HAB_RVT_BASE + 0x08))
-#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)(HAB_RVT_BASE + 0x10))
-#define HAB_RVT_REPORT_EVENT (*(uint32_t *)(HAB_RVT_BASE + 0x20))
-#define HAB_RVT_REPORT_STATUS (*(uint32_t *)(HAB_RVT_BASE + 0x24))
-
-#define HAB_RVT_REPORT_EVENT_NEW (*(uint32_t *)0x000000B8)
-#define HAB_RVT_REPORT_STATUS_NEW (*(uint32_t *)0x000000BC)
-#define HAB_RVT_AUTHENTICATE_IMAGE_NEW (*(uint32_t *)0x000000A8)
-#define HAB_RVT_ENTRY_NEW (*(uint32_t *)0x0000009C)
-#define HAB_RVT_EXIT_NEW (*(uint32_t *)0x000000A0)
-
-#define HAB_CID_ROM 0 /**< ROM Caller ID */
-#define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/
-
-/* ----------- end of HAB API updates ------------*/
-
-uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size);
-
-#endif
+++ /dev/null
-/*
- * i.MX image header offset values
- * Copyright (C) 2013 Marek Vasut <marex@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * NOTE: This file must be kept in sync with tools/imximage.h because
- * tools/imximage.c can not cross-include headers from arch/arm/
- * and vice-versa.
- */
-
-#ifndef __ASM_IMX_COMMON_IMXIMAGE_CFG__
-#define __ASM_IMX_COMMON_IMXIMAGE_CFG__
-
-/* Standard image header offset for NAND, SATA, SD, SPI flash. */
-#define FLASH_OFFSET_STANDARD 0x400
-/* Specific image header offset for booting from OneNAND. */
-#define FLASH_OFFSET_ONENAND 0x100
-/* Specific image header offset for booting from memory-mapped NOR. */
-#define FLASH_OFFSET_NOR 0x1000
-
-#endif /* __ASM_IMX_COMMON_IMXIMAGE_CFG__ */
+++ /dev/null
-/*
- * Based on Linux i.MX iomux-v3.h file:
- * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
- * <armlinux@phytec.de>
- *
- * Copyright (C) 2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __MACH_IOMUX_V3_H__
-#define __MACH_IOMUX_V3_H__
-
-#include <common.h>
-
-/*
- * build IOMUX_PAD structure
- *
- * This iomux scheme is based around pads, which are the physical balls
- * on the processor.
- *
- * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls
- * things like driving strength and pullup/pulldown.
- * - Each pad can have but not necessarily does have an output routing register
- * (IOMUXC_SW_MUX_CTL_PAD_x).
- * - Each pad can have but not necessarily does have an input routing register
- * (IOMUXC_x_SELECT_INPUT)
- *
- * The three register sets do not have a fixed offset to each other,
- * hence we order this table by pad control registers (which all pads
- * have) and put the optional i/o routing registers into additional
- * fields.
- *
- * The naming convention for the pad modes is SOC_PAD_<padname>__<padmode>
- * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
- *
- * IOMUX/PAD Bit field definitions
- *
- * MUX_CTRL_OFS: 0..11 (12)
- * PAD_CTRL_OFS: 12..23 (12)
- * SEL_INPUT_OFS: 24..35 (12)
- * MUX_MODE + SION + LPSR: 36..41 (6)
- * PAD_CTRL + NO_PAD_CTRL: 42..59 (18)
- * SEL_INP: 60..63 (4)
-*/
-
-typedef u64 iomux_v3_cfg_t;
-
-#define MUX_CTRL_OFS_SHIFT 0
-#define MUX_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT)
-#define MUX_PAD_CTRL_OFS_SHIFT 12
-#define MUX_PAD_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << \
- MUX_PAD_CTRL_OFS_SHIFT)
-#define MUX_SEL_INPUT_OFS_SHIFT 24
-#define MUX_SEL_INPUT_OFS_MASK ((iomux_v3_cfg_t)0xfff << \
- MUX_SEL_INPUT_OFS_SHIFT)
-
-#define MUX_MODE_SHIFT 36
-#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x3f << MUX_MODE_SHIFT)
-#define MUX_PAD_CTRL_SHIFT 42
-#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT)
-#define MUX_SEL_INPUT_SHIFT 60
-#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
-
-#define MUX_MODE_SION ((iomux_v3_cfg_t)IOMUX_CONFIG_SION << \
- MUX_MODE_SHIFT)
-#define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
-
-#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \
- sel_input, pad_ctrl) \
- (((iomux_v3_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \
- ((iomux_v3_cfg_t)(mux_mode) << MUX_MODE_SHIFT) | \
- ((iomux_v3_cfg_t)(pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) | \
- ((iomux_v3_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \
- ((iomux_v3_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)| \
- ((iomux_v3_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT))
-
-#define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | \
- MUX_PAD_CTRL(pad))
-
-#define __NA_ 0x000
-#define NO_MUX_I 0
-#define NO_PAD_I 0
-
-#define NO_PAD_CTRL (1 << 17)
-
-#define IOMUX_CONFIG_LPSR 0x20
-#define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \
- MUX_MODE_SHIFT)
-#ifdef CONFIG_MX7
-
-#define IOMUX_LPSR_SEL_INPUT_OFS 0x70000
-
-#define PAD_CTL_DSE_1P8V_140OHM (0x0<<0)
-#define PAD_CTL_DSE_1P8V_35OHM (0x1<<0)
-#define PAD_CTL_DSE_1P8V_70OHM (0x2<<0)
-#define PAD_CTL_DSE_1P8V_23OHM (0x3<<0)
-
-#define PAD_CTL_DSE_3P3V_196OHM (0x0<<0)
-#define PAD_CTL_DSE_3P3V_49OHM (0x1<<0)
-#define PAD_CTL_DSE_3P3V_98OHM (0x2<<0)
-#define PAD_CTL_DSE_3P3V_32OHM (0x3<<0)
-
-#define PAD_CTL_SRE_FAST (0 << 2)
-#define PAD_CTL_SRE_SLOW (0x1 << 2)
-
-#define PAD_CTL_HYS (0x1 << 3)
-#define PAD_CTL_PUE (0x1 << 4)
-
-#define PAD_CTL_PUS_PD100KOHM ((0x0 << 5) | PAD_CTL_PUE)
-#define PAD_CTL_PUS_PU5KOHM ((0x1 << 5) | PAD_CTL_PUE)
-#define PAD_CTL_PUS_PU47KOHM ((0x2 << 5) | PAD_CTL_PUE)
-#define PAD_CTL_PUS_PU100KOHM ((0x3 << 5) | PAD_CTL_PUE)
-
-#else
-
-#ifdef CONFIG_MX6
-
-#define PAD_CTL_HYS (1 << 16)
-
-#define PAD_CTL_PUS_100K_DOWN (0 << 14 | PAD_CTL_PUE)
-#define PAD_CTL_PUS_47K_UP (1 << 14 | PAD_CTL_PUE)
-#define PAD_CTL_PUS_100K_UP (2 << 14 | PAD_CTL_PUE)
-#define PAD_CTL_PUS_22K_UP (3 << 14 | PAD_CTL_PUE)
-#define PAD_CTL_PUE (1 << 13 | PAD_CTL_PKE)
-#define PAD_CTL_PKE (1 << 12)
-
-#define PAD_CTL_ODE (1 << 11)
-
-#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)
-#define PAD_CTL_SPEED_LOW (0 << 6)
-#else
-#define PAD_CTL_SPEED_LOW (1 << 6)
-#endif
-#define PAD_CTL_SPEED_MED (2 << 6)
-#define PAD_CTL_SPEED_HIGH (3 << 6)
-
-#define PAD_CTL_DSE_DISABLE (0 << 3)
-#define PAD_CTL_DSE_240ohm (1 << 3)
-#define PAD_CTL_DSE_120ohm (2 << 3)
-#define PAD_CTL_DSE_80ohm (3 << 3)
-#define PAD_CTL_DSE_60ohm (4 << 3)
-#define PAD_CTL_DSE_48ohm (5 << 3)
-#define PAD_CTL_DSE_40ohm (6 << 3)
-#define PAD_CTL_DSE_34ohm (7 << 3)
-
-/* i.MX6SL/SLL */
-#define PAD_CTL_LVE (1 << 1)
-#define PAD_CTL_LVE_BIT (1 << 22)
-
-/* i.MX6SLL */
-#define PAD_CTL_IPD_BIT (1 << 27)
-
-#elif defined(CONFIG_VF610)
-
-#define PAD_MUX_MODE_SHIFT 20
-
-#define PAD_CTL_INPUT_DIFFERENTIAL (1 << 16)
-
-#define PAD_CTL_SPEED_MED (1 << 12)
-#define PAD_CTL_SPEED_HIGH (3 << 12)
-
-#define PAD_CTL_SRE (1 << 11)
-
-#define PAD_CTL_ODE (1 << 10)
-
-#define PAD_CTL_DSE_150ohm (1 << 6)
-#define PAD_CTL_DSE_75ohm (2 << 6)
-#define PAD_CTL_DSE_50ohm (3 << 6)
-#define PAD_CTL_DSE_37ohm (4 << 6)
-#define PAD_CTL_DSE_30ohm (5 << 6)
-#define PAD_CTL_DSE_25ohm (6 << 6)
-#define PAD_CTL_DSE_20ohm (7 << 6)
-
-#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE)
-#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE)
-#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE)
-#define PAD_CTL_PKE (1 << 3)
-#define PAD_CTL_PUE (1 << 2 | PAD_CTL_PKE)
-
-#define PAD_CTL_OBE_IBE_ENABLE (3 << 0)
-#define PAD_CTL_OBE_ENABLE (1 << 1)
-#define PAD_CTL_IBE_ENABLE (1 << 0)
-
-#else
-
-#define PAD_CTL_DVS (1 << 13)
-#define PAD_CTL_INPUT_DDR (1 << 9)
-#define PAD_CTL_HYS (1 << 8)
-
-#define PAD_CTL_PKE (1 << 7)
-#define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE)
-#define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE)
-#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE)
-#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE)
-#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE)
-
-#define PAD_CTL_ODE (1 << 3)
-
-#define PAD_CTL_DSE_LOW (0 << 1)
-#define PAD_CTL_DSE_MED (1 << 1)
-#define PAD_CTL_DSE_HIGH (2 << 1)
-#define PAD_CTL_DSE_MAX (3 << 1)
-
-#endif
-
-#define PAD_CTL_SRE_SLOW (0 << 0)
-#define PAD_CTL_SRE_FAST (1 << 0)
-
-#endif
-
-#define IOMUX_CONFIG_SION 0x10
-
-#define GPIO_PIN_MASK 0x1f
-#define GPIO_PORT_SHIFT 5
-#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
-#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
-#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
-#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
-#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
-#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
-#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
-
-void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
-void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
- unsigned count);
-/*
-* Set bits for general purpose registers
-*/
-void imx_iomux_set_gpr_register(int group, int start_bit,
- int num_bits, int value);
-#ifdef CONFIG_IOMUX_SHARE_CONF_REG
-void imx_iomux_gpio_set_direction(unsigned int gpio,
- unsigned int direction);
-void imx_iomux_gpio_get_function(unsigned int gpio,
- u32 *gpio_state);
-#endif
-
-/* macros for declaring and using pinmux array */
-#if defined(CONFIG_MX6QDL)
-#define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x)
-#define SETUP_IOMUX_PAD(def) \
-if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) { \
- imx_iomux_v3_setup_pad(MX6Q_##def); \
-} else { \
- imx_iomux_v3_setup_pad(MX6DL_##def); \
-}
-#define SETUP_IOMUX_PADS(x) \
- imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)/2)
-#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
-#define IOMUX_PADS(x) MX6Q_##x
-#define SETUP_IOMUX_PAD(def) \
- imx_iomux_v3_setup_pad(MX6Q_##def);
-#define SETUP_IOMUX_PADS(x) \
- imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
-#elif defined(CONFIG_MX6UL)
-#define IOMUX_PADS(x) MX6_##x
-#define SETUP_IOMUX_PAD(def) \
- imx_iomux_v3_setup_pad(MX6_##def);
-#define SETUP_IOMUX_PADS(x) \
- imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
-#else
-#define IOMUX_PADS(x) MX6DL_##x
-#define SETUP_IOMUX_PAD(def) \
- imx_iomux_v3_setup_pad(MX6DL_##def);
-#define SETUP_IOMUX_PADS(x) \
- imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
-#endif
-
-#endif /* __MACH_IOMUX_V3_H__*/
+++ /dev/null
-/*
- * Copyright (C) 2012
- * Anatolij Gustschin, DENX Software Engineering, <agust@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __MX5_VIDEO_H
-#define __MX5_VIDEO_H
-
-#ifdef CONFIG_VIDEO
-void lcd_enable(void);
-void setup_iomux_lcd(void);
-#else
-static inline void lcd_enable(void) { }
-static inline void setup_iomux_lcd(void) { }
-#endif
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __ASM_ARCH_MXC_MXC_I2C_H__
-#define __ASM_ARCH_MXC_MXC_I2C_H__
-#include <asm-generic/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-
-struct i2c_pin_ctrl {
- iomux_v3_cfg_t i2c_mode;
- iomux_v3_cfg_t gpio_mode;
- unsigned char gp;
- unsigned char spare;
-};
-
-struct i2c_pads_info {
- struct i2c_pin_ctrl scl;
- struct i2c_pin_ctrl sda;
-};
-
-/*
- * Information about i2c controller
- * struct mxc_i2c_bus - information about the i2c[x] bus
- * @index: i2c bus index
- * @base: Address of I2C bus controller
- * @driver_data: Flags for different platforms, such as I2C_QUIRK_FLAG.
- * @speed: Speed of I2C bus
- * @pads_info: pinctrl info for this i2c bus, will be used when pinctrl is ok.
- * The following two is only to be compatible with non-DM part.
- * @idle_bus_fn: function to force bus idle
- * @idle_bus_data: parameter for idle_bus_fun
- * For DM:
- * bus: The device structure for i2c bus controller
- * scl-gpio: specify the gpio related to SCL pin
- * sda-gpio: specify the gpio related to SDA pin
- */
-struct mxc_i2c_bus {
- /*
- * board file can use this index to locate which i2c_pads_info is for
- * i2c_idle_bus. When pinmux is implement, this entry can be
- * discarded. Here we do not use dev->seq, because we do not want to
- * export device to board file.
- */
- int index;
- ulong base;
- ulong driver_data;
- int speed;
- struct i2c_pads_info *pads_info;
-#ifndef CONFIG_DM_I2C
- int (*idle_bus_fn)(void *p);
- void *idle_bus_data;
-#else
- struct udevice *bus;
- /* Use gpio to force bus idle when bus state is abnormal */
- struct gpio_desc scl_gpio;
- struct gpio_desc sda_gpio;
-#endif
-};
-
-#if defined(CONFIG_MX6QDL)
-#define I2C_PADS(name, scl_i2c, scl_gpio, scl_gp, sda_i2c, sda_gpio, sda_gp) \
- struct i2c_pads_info mx6q_##name = { \
- .scl = { \
- .i2c_mode = MX6Q_##scl_i2c, \
- .gpio_mode = MX6Q_##scl_gpio, \
- .gp = scl_gp, \
- }, \
- .sda = { \
- .i2c_mode = MX6Q_##sda_i2c, \
- .gpio_mode = MX6Q_##sda_gpio, \
- .gp = sda_gp, \
- } \
- }; \
- struct i2c_pads_info mx6s_##name = { \
- .scl = { \
- .i2c_mode = MX6DL_##scl_i2c, \
- .gpio_mode = MX6DL_##scl_gpio, \
- .gp = scl_gp, \
- }, \
- .sda = { \
- .i2c_mode = MX6DL_##sda_i2c, \
- .gpio_mode = MX6DL_##sda_gpio, \
- .gp = sda_gp, \
- } \
- };
-
-
-#define I2C_PADS_INFO(name) \
- (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) ? \
- &mx6q_##name : &mx6s_##name
-#endif
-
-int setup_i2c(unsigned i2c_index, int speed, int slave_addr,
- struct i2c_pads_info *p);
-void bus_i2c_init(int index, int speed, int slave_addr,
- int (*idle_bus_fn)(void *p), void *p);
-int force_idle_bus(void *priv);
-int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus);
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2016 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __RDC_SEMA_H__
-#define __RDC_SEMA_H__
-
-/*
- * rdc_peri_cfg_t and rdc_ma_cft_t use the same layout.
- *
- * [ 23 22 | 21 20 | 19 18 | 17 16 ] | [ 15 - 8 ] | [ 7 - 0 ]
- * d3 d2 d1 d0 | master id | peri id
- * d[x] means domain[x], x can be [3 - 0].
- */
-typedef u32 rdc_peri_cfg_t;
-typedef u32 rdc_ma_cfg_t;
-
-#define RDC_PERI_SHIFT 0
-#define RDC_PERI_MASK 0xFF
-
-#define RDC_DOMAIN_SHIFT_BASE 16
-#define RDC_DOMAIN_MASK 0xFF0000
-#define RDC_DOMAIN_SHIFT(x) (RDC_DOMAIN_SHIFT_BASE + ((x << 1)))
-#define RDC_DOMAIN(x) ((rdc_peri_cfg_t)(0x3 << RDC_DOMAIN_SHIFT(x)))
-
-#define RDC_MASTER_SHIFT 8
-#define RDC_MASTER_MASK 0xFF00
-#define RDC_MASTER_CFG(master_id, domain_id) (rdc_ma_cfg_t)((master_id << 8) | \
- (domain_id << RDC_DOMAIN_SHIFT_BASE))
-
-/* The Following macro definitions are common to i.MX6SX and i.MX7D */
-#define SEMA_GATES_NUM 64
-
-#define RDC_MDA_DID_SHIFT 0
-#define RDC_MDA_DID_MASK (0x3 << RDC_MDA_DID_SHIFT)
-#define RDC_MDA_LCK_SHIFT 31
-#define RDC_MDA_LCK_MASK (0x1 << RDC_MDA_LCK_SHIFT)
-
-#define RDC_PDAP_DW_SHIFT(domain) ((domain) << 1)
-#define RDC_PDAP_DR_SHIFT(domain) (1 + RDC_PDAP_DW_SHIFT(domain))
-#define RDC_PDAP_DW_MASK(domain) (1 << RDC_PDAP_DW_SHIFT(domain))
-#define RDC_PDAP_DR_MASK(domain) (1 << RDC_PDAP_DR_SHIFT(domain))
-#define RDC_PDAP_DRW_MASK(domain) (RDC_PDAP_DW_MASK(domain) | \
- RDC_PDAP_DR_MASK(domain))
-
-#define RDC_PDAP_SREQ_SHIFT 30
-#define RDC_PDAP_SREQ_MASK (0x1 << RDC_PDAP_SREQ_SHIFT)
-#define RDC_PDAP_LCK_SHIFT 31
-#define RDC_PDAP_LCK_MASK (0x1 << RDC_PDAP_LCK_SHIFT)
-
-#define RDC_MRSA_SADR_SHIFT 7
-#define RDC_MRSA_SADR_MASK (0x1ffffff << RDC_MRSA_SADR_SHIFT)
-
-#define RDC_MREA_EADR_SHIFT 7
-#define RDC_MREA_EADR_MASK (0x1ffffff << RDC_MREA_EADR_SHIFT)
-
-#define RDC_MRC_DW_SHIFT(domain) (domain)
-#define RDC_MRC_DR_SHIFT(domain) (1 + RDC_MRC_DW_SHIFT(domain))
-#define RDC_MRC_DW_MASK(domain) (1 << RDC_MRC_DW_SHIFT(domain))
-#define RDC_MRC_DR_MASK(domain) (1 << RDC_MRC_DR_SHIFT(domain))
-#define RDC_MRC_DRW_MASK(domain) (RDC_MRC_DW_MASK(domain) | \
- RDC_MRC_DR_MASK(domain))
-#define RDC_MRC_ENA_SHIFT 30
-#define RDC_MRC_ENA_MASK (0x1 << RDC_MRC_ENA_SHIFT)
-#define RDC_MRC_LCK_SHIFT 31
-#define RDC_MRC_LCK_MASK (0x1 << RDC_MRC_LCK_SHIFT)
-
-#define RDC_MRVS_VDID_SHIFT 0
-#define RDC_MRVS_VDID_MASK (0x3 << RDC_MRVS_VDID_SHIFT)
-#define RDC_MRVS_AD_SHIFT 4
-#define RDC_MRVS_AD_MASK (0x1 << RDC_MRVS_AD_SHIFT)
-#define RDC_MRVS_VADDR_SHIFT 5
-#define RDC_MRVS_VADDR_MASK (0x7ffffff << RDC_MRVS_VADDR_SHIFT)
-
-#define RDC_SEMA_GATE_GTFSM_SHIFT 0
-#define RDC_SEMA_GATE_GTFSM_MASK (0xf << RDC_SEMA_GATE_GTFSM_SHIFT)
-#define RDC_SEMA_GATE_LDOM_SHIFT 5
-#define RDC_SEMA_GATE_LDOM_MASK (0x3 << RDC_SEMA_GATE_LDOM_SHIFT)
-
-#define RDC_SEMA_RSTGT_RSTGDP_SHIFT 0
-#define RDC_SEMA_RSTGT_RSTGDP_MASK (0xff << RDC_SEMA_RSTGT_RSTGDP_SHIFT)
-#define RDC_SEMA_RSTGT_RSTGSM_SHIFT 2
-#define RDC_SEMA_RSTGT_RSTGSM_MASK (0x3 << RDC_SEMA_RSTGT_RSTGSM_SHIFT)
-#define RDC_SEMA_RSTGT_RSTGMS_SHIFT 4
-#define RDC_SEMA_RSTGT_RSTGMS_MASK (0xf << RDC_SEMA_RSTGT_RSTGMS_SHIFT)
-#define RDC_SEMA_RSTGT_RSTGTN_SHIFT 8
-#define RDC_SEMA_RSTGT_RSTGTN_MASK (0xff << RDC_SEMA_RSTGT_RSTGTN_SHIFT)
-
-int imx_rdc_check_permission(int per_id, int dom_id);
-int imx_rdc_sema_lock(int per_id);
-int imx_rdc_sema_unlock(int per_id);
-int imx_rdc_setup_peri(rdc_peri_cfg_t p);
-int imx_rdc_setup_peripherals(rdc_peri_cfg_t const *peripherals_list,
- unsigned count);
-int imx_rdc_setup_ma(rdc_ma_cfg_t p);
-int imx_rdc_setup_masters(rdc_ma_cfg_t const *masters_list, unsigned count);
-
-#endif /* __RDC_SEMA_H__*/
+++ /dev/null
-/*
- * Freescale i.MX28 APBH Register Definitions
- *
- * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
- * on behalf of DENX Software Engineering GmbH
- *
- * Based on code from LTIB:
- * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __REGS_APBH_H__
-#define __REGS_APBH_H__
-
-#include <asm/imx-common/regs-common.h>
-
-#ifndef __ASSEMBLY__
-
-#if defined(CONFIG_MX23)
-struct mxs_apbh_regs {
- mxs_reg_32(hw_apbh_ctrl0)
- mxs_reg_32(hw_apbh_ctrl1)
- mxs_reg_32(hw_apbh_ctrl2)
- mxs_reg_32(hw_apbh_channel_ctrl)
-
- union {
- struct {
- mxs_reg_32(hw_apbh_ch_curcmdar)
- mxs_reg_32(hw_apbh_ch_nxtcmdar)
- mxs_reg_32(hw_apbh_ch_cmd)
- mxs_reg_32(hw_apbh_ch_bar)
- mxs_reg_32(hw_apbh_ch_sema)
- mxs_reg_32(hw_apbh_ch_debug1)
- mxs_reg_32(hw_apbh_ch_debug2)
- } ch[8];
- struct {
- mxs_reg_32(hw_apbh_ch0_curcmdar)
- mxs_reg_32(hw_apbh_ch0_nxtcmdar)
- mxs_reg_32(hw_apbh_ch0_cmd)
- mxs_reg_32(hw_apbh_ch0_bar)
- mxs_reg_32(hw_apbh_ch0_sema)
- mxs_reg_32(hw_apbh_ch0_debug1)
- mxs_reg_32(hw_apbh_ch0_debug2)
- mxs_reg_32(hw_apbh_ch1_curcmdar)
- mxs_reg_32(hw_apbh_ch1_nxtcmdar)
- mxs_reg_32(hw_apbh_ch1_cmd)
- mxs_reg_32(hw_apbh_ch1_bar)
- mxs_reg_32(hw_apbh_ch1_sema)
- mxs_reg_32(hw_apbh_ch1_debug1)
- mxs_reg_32(hw_apbh_ch1_debug2)
- mxs_reg_32(hw_apbh_ch2_curcmdar)
- mxs_reg_32(hw_apbh_ch2_nxtcmdar)
- mxs_reg_32(hw_apbh_ch2_cmd)
- mxs_reg_32(hw_apbh_ch2_bar)
- mxs_reg_32(hw_apbh_ch2_sema)
- mxs_reg_32(hw_apbh_ch2_debug1)
- mxs_reg_32(hw_apbh_ch2_debug2)
- mxs_reg_32(hw_apbh_ch3_curcmdar)
- mxs_reg_32(hw_apbh_ch3_nxtcmdar)
- mxs_reg_32(hw_apbh_ch3_cmd)
- mxs_reg_32(hw_apbh_ch3_bar)
- mxs_reg_32(hw_apbh_ch3_sema)
- mxs_reg_32(hw_apbh_ch3_debug1)
- mxs_reg_32(hw_apbh_ch3_debug2)
- mxs_reg_32(hw_apbh_ch4_curcmdar)
- mxs_reg_32(hw_apbh_ch4_nxtcmdar)
- mxs_reg_32(hw_apbh_ch4_cmd)
- mxs_reg_32(hw_apbh_ch4_bar)
- mxs_reg_32(hw_apbh_ch4_sema)
- mxs_reg_32(hw_apbh_ch4_debug1)
- mxs_reg_32(hw_apbh_ch4_debug2)
- mxs_reg_32(hw_apbh_ch5_curcmdar)
- mxs_reg_32(hw_apbh_ch5_nxtcmdar)
- mxs_reg_32(hw_apbh_ch5_cmd)
- mxs_reg_32(hw_apbh_ch5_bar)
- mxs_reg_32(hw_apbh_ch5_sema)
- mxs_reg_32(hw_apbh_ch5_debug1)
- mxs_reg_32(hw_apbh_ch5_debug2)
- mxs_reg_32(hw_apbh_ch6_curcmdar)
- mxs_reg_32(hw_apbh_ch6_nxtcmdar)
- mxs_reg_32(hw_apbh_ch6_cmd)
- mxs_reg_32(hw_apbh_ch6_bar)
- mxs_reg_32(hw_apbh_ch6_sema)
- mxs_reg_32(hw_apbh_ch6_debug1)
- mxs_reg_32(hw_apbh_ch6_debug2)
- mxs_reg_32(hw_apbh_ch7_curcmdar)
- mxs_reg_32(hw_apbh_ch7_nxtcmdar)
- mxs_reg_32(hw_apbh_ch7_cmd)
- mxs_reg_32(hw_apbh_ch7_bar)
- mxs_reg_32(hw_apbh_ch7_sema)
- mxs_reg_32(hw_apbh_ch7_debug1)
- mxs_reg_32(hw_apbh_ch7_debug2)
- };
- };
- mxs_reg_32(hw_apbh_version)
-};
-
-#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7))
-struct mxs_apbh_regs {
- mxs_reg_32(hw_apbh_ctrl0)
- mxs_reg_32(hw_apbh_ctrl1)
- mxs_reg_32(hw_apbh_ctrl2)
- mxs_reg_32(hw_apbh_channel_ctrl)
- mxs_reg_32(hw_apbh_devsel)
- mxs_reg_32(hw_apbh_dma_burst_size)
- mxs_reg_32(hw_apbh_debug)
-
- uint32_t reserved[36];
-
- union {
- struct {
- mxs_reg_32(hw_apbh_ch_curcmdar)
- mxs_reg_32(hw_apbh_ch_nxtcmdar)
- mxs_reg_32(hw_apbh_ch_cmd)
- mxs_reg_32(hw_apbh_ch_bar)
- mxs_reg_32(hw_apbh_ch_sema)
- mxs_reg_32(hw_apbh_ch_debug1)
- mxs_reg_32(hw_apbh_ch_debug2)
- } ch[16];
- struct {
- mxs_reg_32(hw_apbh_ch0_curcmdar)
- mxs_reg_32(hw_apbh_ch0_nxtcmdar)
- mxs_reg_32(hw_apbh_ch0_cmd)
- mxs_reg_32(hw_apbh_ch0_bar)
- mxs_reg_32(hw_apbh_ch0_sema)
- mxs_reg_32(hw_apbh_ch0_debug1)
- mxs_reg_32(hw_apbh_ch0_debug2)
- mxs_reg_32(hw_apbh_ch1_curcmdar)
- mxs_reg_32(hw_apbh_ch1_nxtcmdar)
- mxs_reg_32(hw_apbh_ch1_cmd)
- mxs_reg_32(hw_apbh_ch1_bar)
- mxs_reg_32(hw_apbh_ch1_sema)
- mxs_reg_32(hw_apbh_ch1_debug1)
- mxs_reg_32(hw_apbh_ch1_debug2)
- mxs_reg_32(hw_apbh_ch2_curcmdar)
- mxs_reg_32(hw_apbh_ch2_nxtcmdar)
- mxs_reg_32(hw_apbh_ch2_cmd)
- mxs_reg_32(hw_apbh_ch2_bar)
- mxs_reg_32(hw_apbh_ch2_sema)
- mxs_reg_32(hw_apbh_ch2_debug1)
- mxs_reg_32(hw_apbh_ch2_debug2)
- mxs_reg_32(hw_apbh_ch3_curcmdar)
- mxs_reg_32(hw_apbh_ch3_nxtcmdar)
- mxs_reg_32(hw_apbh_ch3_cmd)
- mxs_reg_32(hw_apbh_ch3_bar)
- mxs_reg_32(hw_apbh_ch3_sema)
- mxs_reg_32(hw_apbh_ch3_debug1)
- mxs_reg_32(hw_apbh_ch3_debug2)
- mxs_reg_32(hw_apbh_ch4_curcmdar)
- mxs_reg_32(hw_apbh_ch4_nxtcmdar)
- mxs_reg_32(hw_apbh_ch4_cmd)
- mxs_reg_32(hw_apbh_ch4_bar)
- mxs_reg_32(hw_apbh_ch4_sema)
- mxs_reg_32(hw_apbh_ch4_debug1)
- mxs_reg_32(hw_apbh_ch4_debug2)
- mxs_reg_32(hw_apbh_ch5_curcmdar)
- mxs_reg_32(hw_apbh_ch5_nxtcmdar)
- mxs_reg_32(hw_apbh_ch5_cmd)
- mxs_reg_32(hw_apbh_ch5_bar)
- mxs_reg_32(hw_apbh_ch5_sema)
- mxs_reg_32(hw_apbh_ch5_debug1)
- mxs_reg_32(hw_apbh_ch5_debug2)
- mxs_reg_32(hw_apbh_ch6_curcmdar)
- mxs_reg_32(hw_apbh_ch6_nxtcmdar)
- mxs_reg_32(hw_apbh_ch6_cmd)
- mxs_reg_32(hw_apbh_ch6_bar)
- mxs_reg_32(hw_apbh_ch6_sema)
- mxs_reg_32(hw_apbh_ch6_debug1)
- mxs_reg_32(hw_apbh_ch6_debug2)
- mxs_reg_32(hw_apbh_ch7_curcmdar)
- mxs_reg_32(hw_apbh_ch7_nxtcmdar)
- mxs_reg_32(hw_apbh_ch7_cmd)
- mxs_reg_32(hw_apbh_ch7_bar)
- mxs_reg_32(hw_apbh_ch7_sema)
- mxs_reg_32(hw_apbh_ch7_debug1)
- mxs_reg_32(hw_apbh_ch7_debug2)
- mxs_reg_32(hw_apbh_ch8_curcmdar)
- mxs_reg_32(hw_apbh_ch8_nxtcmdar)
- mxs_reg_32(hw_apbh_ch8_cmd)
- mxs_reg_32(hw_apbh_ch8_bar)
- mxs_reg_32(hw_apbh_ch8_sema)
- mxs_reg_32(hw_apbh_ch8_debug1)
- mxs_reg_32(hw_apbh_ch8_debug2)
- mxs_reg_32(hw_apbh_ch9_curcmdar)
- mxs_reg_32(hw_apbh_ch9_nxtcmdar)
- mxs_reg_32(hw_apbh_ch9_cmd)
- mxs_reg_32(hw_apbh_ch9_bar)
- mxs_reg_32(hw_apbh_ch9_sema)
- mxs_reg_32(hw_apbh_ch9_debug1)
- mxs_reg_32(hw_apbh_ch9_debug2)
- mxs_reg_32(hw_apbh_ch10_curcmdar)
- mxs_reg_32(hw_apbh_ch10_nxtcmdar)
- mxs_reg_32(hw_apbh_ch10_cmd)
- mxs_reg_32(hw_apbh_ch10_bar)
- mxs_reg_32(hw_apbh_ch10_sema)
- mxs_reg_32(hw_apbh_ch10_debug1)
- mxs_reg_32(hw_apbh_ch10_debug2)
- mxs_reg_32(hw_apbh_ch11_curcmdar)
- mxs_reg_32(hw_apbh_ch11_nxtcmdar)
- mxs_reg_32(hw_apbh_ch11_cmd)
- mxs_reg_32(hw_apbh_ch11_bar)
- mxs_reg_32(hw_apbh_ch11_sema)
- mxs_reg_32(hw_apbh_ch11_debug1)
- mxs_reg_32(hw_apbh_ch11_debug2)
- mxs_reg_32(hw_apbh_ch12_curcmdar)
- mxs_reg_32(hw_apbh_ch12_nxtcmdar)
- mxs_reg_32(hw_apbh_ch12_cmd)
- mxs_reg_32(hw_apbh_ch12_bar)
- mxs_reg_32(hw_apbh_ch12_sema)
- mxs_reg_32(hw_apbh_ch12_debug1)
- mxs_reg_32(hw_apbh_ch12_debug2)
- mxs_reg_32(hw_apbh_ch13_curcmdar)
- mxs_reg_32(hw_apbh_ch13_nxtcmdar)
- mxs_reg_32(hw_apbh_ch13_cmd)
- mxs_reg_32(hw_apbh_ch13_bar)
- mxs_reg_32(hw_apbh_ch13_sema)
- mxs_reg_32(hw_apbh_ch13_debug1)
- mxs_reg_32(hw_apbh_ch13_debug2)
- mxs_reg_32(hw_apbh_ch14_curcmdar)
- mxs_reg_32(hw_apbh_ch14_nxtcmdar)
- mxs_reg_32(hw_apbh_ch14_cmd)
- mxs_reg_32(hw_apbh_ch14_bar)
- mxs_reg_32(hw_apbh_ch14_sema)
- mxs_reg_32(hw_apbh_ch14_debug1)
- mxs_reg_32(hw_apbh_ch14_debug2)
- mxs_reg_32(hw_apbh_ch15_curcmdar)
- mxs_reg_32(hw_apbh_ch15_nxtcmdar)
- mxs_reg_32(hw_apbh_ch15_cmd)
- mxs_reg_32(hw_apbh_ch15_bar)
- mxs_reg_32(hw_apbh_ch15_sema)
- mxs_reg_32(hw_apbh_ch15_debug1)
- mxs_reg_32(hw_apbh_ch15_debug2)
- };
- };
- mxs_reg_32(hw_apbh_version)
-};
-#endif
-
-#endif
-
-#define APBH_CTRL0_SFTRST (1 << 31)
-#define APBH_CTRL0_CLKGATE (1 << 30)
-#define APBH_CTRL0_AHB_BURST8_EN (1 << 29)
-#define APBH_CTRL0_APB_BURST_EN (1 << 28)
-#if defined(CONFIG_MX23)
-#define APBH_CTRL0_RSVD0_MASK (0xf << 24)
-#define APBH_CTRL0_RSVD0_OFFSET 24
-#define APBH_CTRL0_RESET_CHANNEL_MASK (0xff << 16)
-#define APBH_CTRL0_RESET_CHANNEL_OFFSET 16
-#define APBH_CTRL0_CLKGATE_CHANNEL_MASK (0xff << 8)
-#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 8
-#define APBH_CTRL0_CLKGATE_CHANNEL_SSP0 0x02
-#define APBH_CTRL0_CLKGATE_CHANNEL_SSP1 0x04
-#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x10
-#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x20
-#define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x40
-#define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x80
-#elif defined(CONFIG_MX28)
-#define APBH_CTRL0_RSVD0_MASK (0xfff << 16)
-#define APBH_CTRL0_RSVD0_OFFSET 16
-#define APBH_CTRL0_CLKGATE_CHANNEL_MASK 0xffff
-#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0
-#define APBH_CTRL0_CLKGATE_CHANNEL_SSP0 0x0001
-#define APBH_CTRL0_CLKGATE_CHANNEL_SSP1 0x0002
-#define APBH_CTRL0_CLKGATE_CHANNEL_SSP2 0x0004
-#define APBH_CTRL0_CLKGATE_CHANNEL_SSP3 0x0008
-#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0010
-#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0020
-#define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x0040
-#define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x0080
-#define APBH_CTRL0_CLKGATE_CHANNEL_NAND4 0x0100
-#define APBH_CTRL0_CLKGATE_CHANNEL_NAND5 0x0200
-#define APBH_CTRL0_CLKGATE_CHANNEL_NAND6 0x0400
-#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800
-#define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000
-#define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000
-#elif (defined(CONFIG_MX6) || defined(CONFIG_MX7))
-#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0
-#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0001
-#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0002
-#define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x0004
-#define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x0008
-#define APBH_CTRL0_CLKGATE_CHANNEL_NAND4 0x0010
-#define APBH_CTRL0_CLKGATE_CHANNEL_NAND5 0x0020
-#define APBH_CTRL0_CLKGATE_CHANNEL_NAND6 0x0040
-#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0080
-#define APBH_CTRL0_CLKGATE_CHANNEL_SSP 0x0100
-#endif
-
-#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN (1 << 31)
-#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN (1 << 30)
-#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN (1 << 29)
-#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN (1 << 28)
-#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN (1 << 27)
-#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN (1 << 26)
-#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN (1 << 25)
-#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN (1 << 24)
-#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN (1 << 23)
-#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN (1 << 22)
-#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN (1 << 21)
-#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN (1 << 20)
-#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN (1 << 19)
-#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN (1 << 18)
-#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN (1 << 17)
-#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN (1 << 16)
-#define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET 16
-#define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_MASK (0xffff << 16)
-#define APBH_CTRL1_CH15_CMDCMPLT_IRQ (1 << 15)
-#define APBH_CTRL1_CH14_CMDCMPLT_IRQ (1 << 14)
-#define APBH_CTRL1_CH13_CMDCMPLT_IRQ (1 << 13)
-#define APBH_CTRL1_CH12_CMDCMPLT_IRQ (1 << 12)
-#define APBH_CTRL1_CH11_CMDCMPLT_IRQ (1 << 11)
-#define APBH_CTRL1_CH10_CMDCMPLT_IRQ (1 << 10)
-#define APBH_CTRL1_CH9_CMDCMPLT_IRQ (1 << 9)
-#define APBH_CTRL1_CH8_CMDCMPLT_IRQ (1 << 8)
-#define APBH_CTRL1_CH7_CMDCMPLT_IRQ (1 << 7)
-#define APBH_CTRL1_CH6_CMDCMPLT_IRQ (1 << 6)
-#define APBH_CTRL1_CH5_CMDCMPLT_IRQ (1 << 5)
-#define APBH_CTRL1_CH4_CMDCMPLT_IRQ (1 << 4)
-#define APBH_CTRL1_CH3_CMDCMPLT_IRQ (1 << 3)
-#define APBH_CTRL1_CH2_CMDCMPLT_IRQ (1 << 2)
-#define APBH_CTRL1_CH1_CMDCMPLT_IRQ (1 << 1)
-#define APBH_CTRL1_CH0_CMDCMPLT_IRQ (1 << 0)
-
-#define APBH_CTRL2_CH15_ERROR_STATUS (1 << 31)
-#define APBH_CTRL2_CH14_ERROR_STATUS (1 << 30)
-#define APBH_CTRL2_CH13_ERROR_STATUS (1 << 29)
-#define APBH_CTRL2_CH12_ERROR_STATUS (1 << 28)
-#define APBH_CTRL2_CH11_ERROR_STATUS (1 << 27)
-#define APBH_CTRL2_CH10_ERROR_STATUS (1 << 26)
-#define APBH_CTRL2_CH9_ERROR_STATUS (1 << 25)
-#define APBH_CTRL2_CH8_ERROR_STATUS (1 << 24)
-#define APBH_CTRL2_CH7_ERROR_STATUS (1 << 23)
-#define APBH_CTRL2_CH6_ERROR_STATUS (1 << 22)
-#define APBH_CTRL2_CH5_ERROR_STATUS (1 << 21)
-#define APBH_CTRL2_CH4_ERROR_STATUS (1 << 20)
-#define APBH_CTRL2_CH3_ERROR_STATUS (1 << 19)
-#define APBH_CTRL2_CH2_ERROR_STATUS (1 << 18)
-#define APBH_CTRL2_CH1_ERROR_STATUS (1 << 17)
-#define APBH_CTRL2_CH0_ERROR_STATUS (1 << 16)
-#define APBH_CTRL2_CH15_ERROR_IRQ (1 << 15)
-#define APBH_CTRL2_CH14_ERROR_IRQ (1 << 14)
-#define APBH_CTRL2_CH13_ERROR_IRQ (1 << 13)
-#define APBH_CTRL2_CH12_ERROR_IRQ (1 << 12)
-#define APBH_CTRL2_CH11_ERROR_IRQ (1 << 11)
-#define APBH_CTRL2_CH10_ERROR_IRQ (1 << 10)
-#define APBH_CTRL2_CH9_ERROR_IRQ (1 << 9)
-#define APBH_CTRL2_CH8_ERROR_IRQ (1 << 8)
-#define APBH_CTRL2_CH7_ERROR_IRQ (1 << 7)
-#define APBH_CTRL2_CH6_ERROR_IRQ (1 << 6)
-#define APBH_CTRL2_CH5_ERROR_IRQ (1 << 5)
-#define APBH_CTRL2_CH4_ERROR_IRQ (1 << 4)
-#define APBH_CTRL2_CH3_ERROR_IRQ (1 << 3)
-#define APBH_CTRL2_CH2_ERROR_IRQ (1 << 2)
-#define APBH_CTRL2_CH1_ERROR_IRQ (1 << 1)
-#define APBH_CTRL2_CH0_ERROR_IRQ (1 << 0)
-
-#if defined(CONFIG_MX28)
-#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xffff << 16)
-#define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16
-#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP0 (0x0001 << 16)
-#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP1 (0x0002 << 16)
-#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP2 (0x0004 << 16)
-#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP3 (0x0008 << 16)
-#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND0 (0x0010 << 16)
-#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND1 (0x0020 << 16)
-#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND2 (0x0040 << 16)
-#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND3 (0x0080 << 16)
-#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND4 (0x0100 << 16)
-#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND5 (0x0200 << 16)
-#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND6 (0x0400 << 16)
-#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND7 (0x0800 << 16)
-#define APBH_CHANNEL_CTRL_RESET_CHANNEL_HSADC (0x1000 << 16)
-#define APBH_CHANNEL_CTRL_RESET_CHANNEL_LCDIF (0x2000 << 16)
-#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK 0xffff
-#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_OFFSET 0
-#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP0 0x0001
-#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP1 0x0002
-#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP2 0x0004
-#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP3 0x0008
-#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND0 0x0010
-#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND1 0x0020
-#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND2 0x0040
-#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND3 0x0080
-#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND4 0x0100
-#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND5 0x0200
-#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND6 0x0400
-#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND7 0x0800
-#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_HSADC 0x1000
-#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000
-#endif
-
-#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
-#define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16
-#endif
-
-#if defined(CONFIG_MX23)
-#define APBH_DEVSEL_CH7_MASK (0xf << 28)
-#define APBH_DEVSEL_CH7_OFFSET 28
-#define APBH_DEVSEL_CH6_MASK (0xf << 24)
-#define APBH_DEVSEL_CH6_OFFSET 24
-#define APBH_DEVSEL_CH5_MASK (0xf << 20)
-#define APBH_DEVSEL_CH5_OFFSET 20
-#define APBH_DEVSEL_CH4_MASK (0xf << 16)
-#define APBH_DEVSEL_CH4_OFFSET 16
-#define APBH_DEVSEL_CH3_MASK (0xf << 12)
-#define APBH_DEVSEL_CH3_OFFSET 12
-#define APBH_DEVSEL_CH2_MASK (0xf << 8)
-#define APBH_DEVSEL_CH2_OFFSET 8
-#define APBH_DEVSEL_CH1_MASK (0xf << 4)
-#define APBH_DEVSEL_CH1_OFFSET 4
-#define APBH_DEVSEL_CH0_MASK (0xf << 0)
-#define APBH_DEVSEL_CH0_OFFSET 0
-#elif defined(CONFIG_MX28)
-#define APBH_DEVSEL_CH15_MASK (0x3 << 30)
-#define APBH_DEVSEL_CH15_OFFSET 30
-#define APBH_DEVSEL_CH14_MASK (0x3 << 28)
-#define APBH_DEVSEL_CH14_OFFSET 28
-#define APBH_DEVSEL_CH13_MASK (0x3 << 26)
-#define APBH_DEVSEL_CH13_OFFSET 26
-#define APBH_DEVSEL_CH12_MASK (0x3 << 24)
-#define APBH_DEVSEL_CH12_OFFSET 24
-#define APBH_DEVSEL_CH11_MASK (0x3 << 22)
-#define APBH_DEVSEL_CH11_OFFSET 22
-#define APBH_DEVSEL_CH10_MASK (0x3 << 20)
-#define APBH_DEVSEL_CH10_OFFSET 20
-#define APBH_DEVSEL_CH9_MASK (0x3 << 18)
-#define APBH_DEVSEL_CH9_OFFSET 18
-#define APBH_DEVSEL_CH8_MASK (0x3 << 16)
-#define APBH_DEVSEL_CH8_OFFSET 16
-#define APBH_DEVSEL_CH7_MASK (0x3 << 14)
-#define APBH_DEVSEL_CH7_OFFSET 14
-#define APBH_DEVSEL_CH6_MASK (0x3 << 12)
-#define APBH_DEVSEL_CH6_OFFSET 12
-#define APBH_DEVSEL_CH5_MASK (0x3 << 10)
-#define APBH_DEVSEL_CH5_OFFSET 10
-#define APBH_DEVSEL_CH4_MASK (0x3 << 8)
-#define APBH_DEVSEL_CH4_OFFSET 8
-#define APBH_DEVSEL_CH3_MASK (0x3 << 6)
-#define APBH_DEVSEL_CH3_OFFSET 6
-#define APBH_DEVSEL_CH2_MASK (0x3 << 4)
-#define APBH_DEVSEL_CH2_OFFSET 4
-#define APBH_DEVSEL_CH1_MASK (0x3 << 2)
-#define APBH_DEVSEL_CH1_OFFSET 2
-#define APBH_DEVSEL_CH0_MASK (0x3 << 0)
-#define APBH_DEVSEL_CH0_OFFSET 0
-#endif
-
-#if defined(CONFIG_MX28)
-#define APBH_DMA_BURST_SIZE_CH15_MASK (0x3 << 30)
-#define APBH_DMA_BURST_SIZE_CH15_OFFSET 30
-#define APBH_DMA_BURST_SIZE_CH14_MASK (0x3 << 28)
-#define APBH_DMA_BURST_SIZE_CH14_OFFSET 28
-#define APBH_DMA_BURST_SIZE_CH13_MASK (0x3 << 26)
-#define APBH_DMA_BURST_SIZE_CH13_OFFSET 26
-#define APBH_DMA_BURST_SIZE_CH12_MASK (0x3 << 24)
-#define APBH_DMA_BURST_SIZE_CH12_OFFSET 24
-#define APBH_DMA_BURST_SIZE_CH11_MASK (0x3 << 22)
-#define APBH_DMA_BURST_SIZE_CH11_OFFSET 22
-#define APBH_DMA_BURST_SIZE_CH10_MASK (0x3 << 20)
-#define APBH_DMA_BURST_SIZE_CH10_OFFSET 20
-#define APBH_DMA_BURST_SIZE_CH9_MASK (0x3 << 18)
-#define APBH_DMA_BURST_SIZE_CH9_OFFSET 18
-#define APBH_DMA_BURST_SIZE_CH8_MASK (0x3 << 16)
-#define APBH_DMA_BURST_SIZE_CH8_OFFSET 16
-#define APBH_DMA_BURST_SIZE_CH8_BURST0 (0x0 << 16)
-#define APBH_DMA_BURST_SIZE_CH8_BURST4 (0x1 << 16)
-#define APBH_DMA_BURST_SIZE_CH8_BURST8 (0x2 << 16)
-#define APBH_DMA_BURST_SIZE_CH7_MASK (0x3 << 14)
-#define APBH_DMA_BURST_SIZE_CH7_OFFSET 14
-#define APBH_DMA_BURST_SIZE_CH6_MASK (0x3 << 12)
-#define APBH_DMA_BURST_SIZE_CH6_OFFSET 12
-#define APBH_DMA_BURST_SIZE_CH5_MASK (0x3 << 10)
-#define APBH_DMA_BURST_SIZE_CH5_OFFSET 10
-#define APBH_DMA_BURST_SIZE_CH4_MASK (0x3 << 8)
-#define APBH_DMA_BURST_SIZE_CH4_OFFSET 8
-#define APBH_DMA_BURST_SIZE_CH3_MASK (0x3 << 6)
-#define APBH_DMA_BURST_SIZE_CH3_OFFSET 6
-#define APBH_DMA_BURST_SIZE_CH3_BURST0 (0x0 << 6)
-#define APBH_DMA_BURST_SIZE_CH3_BURST4 (0x1 << 6)
-#define APBH_DMA_BURST_SIZE_CH3_BURST8 (0x2 << 6)
-
-#define APBH_DMA_BURST_SIZE_CH2_MASK (0x3 << 4)
-#define APBH_DMA_BURST_SIZE_CH2_OFFSET 4
-#define APBH_DMA_BURST_SIZE_CH2_BURST0 (0x0 << 4)
-#define APBH_DMA_BURST_SIZE_CH2_BURST4 (0x1 << 4)
-#define APBH_DMA_BURST_SIZE_CH2_BURST8 (0x2 << 4)
-#define APBH_DMA_BURST_SIZE_CH1_MASK (0x3 << 2)
-#define APBH_DMA_BURST_SIZE_CH1_OFFSET 2
-#define APBH_DMA_BURST_SIZE_CH1_BURST0 (0x0 << 2)
-#define APBH_DMA_BURST_SIZE_CH1_BURST4 (0x1 << 2)
-#define APBH_DMA_BURST_SIZE_CH1_BURST8 (0x2 << 2)
-
-#define APBH_DMA_BURST_SIZE_CH0_MASK 0x3
-#define APBH_DMA_BURST_SIZE_CH0_OFFSET 0
-#define APBH_DMA_BURST_SIZE_CH0_BURST0 0x0
-#define APBH_DMA_BURST_SIZE_CH0_BURST4 0x1
-#define APBH_DMA_BURST_SIZE_CH0_BURST8 0x2
-
-#define APBH_DEBUG_GPMI_ONE_FIFO (1 << 0)
-#endif
-
-#define APBH_CHn_CURCMDAR_CMD_ADDR_MASK 0xffffffff
-#define APBH_CHn_CURCMDAR_CMD_ADDR_OFFSET 0
-
-#define APBH_CHn_NXTCMDAR_CMD_ADDR_MASK 0xffffffff
-#define APBH_CHn_NXTCMDAR_CMD_ADDR_OFFSET 0
-
-#define APBH_CHn_CMD_XFER_COUNT_MASK (0xffff << 16)
-#define APBH_CHn_CMD_XFER_COUNT_OFFSET 16
-#define APBH_CHn_CMD_CMDWORDS_MASK (0xf << 12)
-#define APBH_CHn_CMD_CMDWORDS_OFFSET 12
-#define APBH_CHn_CMD_HALTONTERMINATE (1 << 8)
-#define APBH_CHn_CMD_WAIT4ENDCMD (1 << 7)
-#define APBH_CHn_CMD_SEMAPHORE (1 << 6)
-#define APBH_CHn_CMD_NANDWAIT4READY (1 << 5)
-#define APBH_CHn_CMD_NANDLOCK (1 << 4)
-#define APBH_CHn_CMD_IRQONCMPLT (1 << 3)
-#define APBH_CHn_CMD_CHAIN (1 << 2)
-#define APBH_CHn_CMD_COMMAND_MASK 0x3
-#define APBH_CHn_CMD_COMMAND_OFFSET 0
-#define APBH_CHn_CMD_COMMAND_NO_DMA_XFER 0x0
-#define APBH_CHn_CMD_COMMAND_DMA_WRITE 0x1
-#define APBH_CHn_CMD_COMMAND_DMA_READ 0x2
-#define APBH_CHn_CMD_COMMAND_DMA_SENSE 0x3
-
-#define APBH_CHn_BAR_ADDRESS_MASK 0xffffffff
-#define APBH_CHn_BAR_ADDRESS_OFFSET 0
-
-#define APBH_CHn_SEMA_RSVD2_MASK (0xff << 24)
-#define APBH_CHn_SEMA_RSVD2_OFFSET 24
-#define APBH_CHn_SEMA_PHORE_MASK (0xff << 16)
-#define APBH_CHn_SEMA_PHORE_OFFSET 16
-#define APBH_CHn_SEMA_RSVD1_MASK (0xff << 8)
-#define APBH_CHn_SEMA_RSVD1_OFFSET 8
-#define APBH_CHn_SEMA_INCREMENT_SEMA_MASK (0xff << 0)
-#define APBH_CHn_SEMA_INCREMENT_SEMA_OFFSET 0
-
-#define APBH_CHn_DEBUG1_REQ (1 << 31)
-#define APBH_CHn_DEBUG1_BURST (1 << 30)
-#define APBH_CHn_DEBUG1_KICK (1 << 29)
-#define APBH_CHn_DEBUG1_END (1 << 28)
-#define APBH_CHn_DEBUG1_SENSE (1 << 27)
-#define APBH_CHn_DEBUG1_READY (1 << 26)
-#define APBH_CHn_DEBUG1_LOCK (1 << 25)
-#define APBH_CHn_DEBUG1_NEXTCMDADDRVALID (1 << 24)
-#define APBH_CHn_DEBUG1_RD_FIFO_EMPTY (1 << 23)
-#define APBH_CHn_DEBUG1_RD_FIFO_FULL (1 << 22)
-#define APBH_CHn_DEBUG1_WR_FIFO_EMPTY (1 << 21)
-#define APBH_CHn_DEBUG1_WR_FIFO_FULL (1 << 20)
-#define APBH_CHn_DEBUG1_RSVD1_MASK (0x7fff << 5)
-#define APBH_CHn_DEBUG1_RSVD1_OFFSET 5
-#define APBH_CHn_DEBUG1_STATEMACHINE_MASK 0x1f
-#define APBH_CHn_DEBUG1_STATEMACHINE_OFFSET 0
-#define APBH_CHn_DEBUG1_STATEMACHINE_IDLE 0x00
-#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD1 0x01
-#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD3 0x02
-#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD2 0x03
-#define APBH_CHn_DEBUG1_STATEMACHINE_XFER_DECODE 0x04
-#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_WAIT 0x05
-#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD4 0x06
-#define APBH_CHn_DEBUG1_STATEMACHINE_PIO_REQ 0x07
-#define APBH_CHn_DEBUG1_STATEMACHINE_READ_FLUSH 0x08
-#define APBH_CHn_DEBUG1_STATEMACHINE_READ_WAIT 0x09
-#define APBH_CHn_DEBUG1_STATEMACHINE_WRITE 0x0c
-#define APBH_CHn_DEBUG1_STATEMACHINE_READ_REQ 0x0d
-#define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_CHAIN 0x0e
-#define APBH_CHn_DEBUG1_STATEMACHINE_XFER_COMPLETE 0x0f
-#define APBH_CHn_DEBUG1_STATEMACHINE_TERMINATE 0x14
-#define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_END 0x15
-#define APBH_CHn_DEBUG1_STATEMACHINE_WRITE_WAIT 0x1c
-#define APBH_CHn_DEBUG1_STATEMACHINE_HALT_AFTER_TERM 0x1d
-#define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_WAIT 0x1e
-#define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_READY 0x1f
-
-#define APBH_CHn_DEBUG2_APB_BYTES_MASK (0xffff << 16)
-#define APBH_CHn_DEBUG2_APB_BYTES_OFFSET 16
-#define APBH_CHn_DEBUG2_AHB_BYTES_MASK 0xffff
-#define APBH_CHn_DEBUG2_AHB_BYTES_OFFSET 0
-
-#define APBH_VERSION_MAJOR_MASK (0xff << 24)
-#define APBH_VERSION_MAJOR_OFFSET 24
-#define APBH_VERSION_MINOR_MASK (0xff << 16)
-#define APBH_VERSION_MINOR_OFFSET 16
-#define APBH_VERSION_STEP_MASK 0xffff
-#define APBH_VERSION_STEP_OFFSET 0
-
-#endif /* __REGS_APBH_H__ */
+++ /dev/null
-/*
- * Freescale i.MX28 BCH Register Definitions
- *
- * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
- * on behalf of DENX Software Engineering GmbH
- *
- * Based on code from LTIB:
- * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __MX28_REGS_BCH_H__
-#define __MX28_REGS_BCH_H__
-
-#include <asm/imx-common/regs-common.h>
-
-#ifndef __ASSEMBLY__
-struct mxs_bch_regs {
- mxs_reg_32(hw_bch_ctrl)
- mxs_reg_32(hw_bch_status0)
- mxs_reg_32(hw_bch_mode)
- mxs_reg_32(hw_bch_encodeptr)
- mxs_reg_32(hw_bch_dataptr)
- mxs_reg_32(hw_bch_metaptr)
-
- uint32_t reserved[4];
-
- mxs_reg_32(hw_bch_layoutselect)
- mxs_reg_32(hw_bch_flash0layout0)
- mxs_reg_32(hw_bch_flash0layout1)
- mxs_reg_32(hw_bch_flash1layout0)
- mxs_reg_32(hw_bch_flash1layout1)
- mxs_reg_32(hw_bch_flash2layout0)
- mxs_reg_32(hw_bch_flash2layout1)
- mxs_reg_32(hw_bch_flash3layout0)
- mxs_reg_32(hw_bch_flash3layout1)
- mxs_reg_32(hw_bch_dbgkesread)
- mxs_reg_32(hw_bch_dbgcsferead)
- mxs_reg_32(hw_bch_dbgsyndegread)
- mxs_reg_32(hw_bch_dbgahbmread)
- mxs_reg_32(hw_bch_blockname)
- mxs_reg_32(hw_bch_version)
-};
-#endif
-
-#define BCH_CTRL_SFTRST (1 << 31)
-#define BCH_CTRL_CLKGATE (1 << 30)
-#define BCH_CTRL_DEBUGSYNDROME (1 << 22)
-#define BCH_CTRL_M2M_LAYOUT_MASK (0x3 << 18)
-#define BCH_CTRL_M2M_LAYOUT_OFFSET 18
-#define BCH_CTRL_M2M_ENCODE (1 << 17)
-#define BCH_CTRL_M2M_ENABLE (1 << 16)
-#define BCH_CTRL_DEBUG_STALL_IRQ_EN (1 << 10)
-#define BCH_CTRL_COMPLETE_IRQ_EN (1 << 8)
-#define BCH_CTRL_BM_ERROR_IRQ (1 << 3)
-#define BCH_CTRL_DEBUG_STALL_IRQ (1 << 2)
-#define BCH_CTRL_COMPLETE_IRQ (1 << 0)
-
-#define BCH_STATUS0_HANDLE_MASK (0xfff << 20)
-#define BCH_STATUS0_HANDLE_OFFSET 20
-#define BCH_STATUS0_COMPLETED_CE_MASK (0xf << 16)
-#define BCH_STATUS0_COMPLETED_CE_OFFSET 16
-#define BCH_STATUS0_STATUS_BLK0_MASK (0xff << 8)
-#define BCH_STATUS0_STATUS_BLK0_OFFSET 8
-#define BCH_STATUS0_STATUS_BLK0_ZERO (0x00 << 8)
-#define BCH_STATUS0_STATUS_BLK0_ERROR1 (0x01 << 8)
-#define BCH_STATUS0_STATUS_BLK0_ERROR2 (0x02 << 8)
-#define BCH_STATUS0_STATUS_BLK0_ERROR3 (0x03 << 8)
-#define BCH_STATUS0_STATUS_BLK0_ERROR4 (0x04 << 8)
-#define BCH_STATUS0_STATUS_BLK0_UNCORRECTABLE (0xfe << 8)
-#define BCH_STATUS0_STATUS_BLK0_ERASED (0xff << 8)
-#define BCH_STATUS0_ALLONES (1 << 4)
-#define BCH_STATUS0_CORRECTED (1 << 3)
-#define BCH_STATUS0_UNCORRECTABLE (1 << 2)
-
-#define BCH_MODE_ERASE_THRESHOLD_MASK 0xff
-#define BCH_MODE_ERASE_THRESHOLD_OFFSET 0
-
-#define BCH_ENCODEPTR_ADDR_MASK 0xffffffff
-#define BCH_ENCODEPTR_ADDR_OFFSET 0
-
-#define BCH_DATAPTR_ADDR_MASK 0xffffffff
-#define BCH_DATAPTR_ADDR_OFFSET 0
-
-#define BCH_METAPTR_ADDR_MASK 0xffffffff
-#define BCH_METAPTR_ADDR_OFFSET 0
-
-#define BCH_LAYOUTSELECT_CS15_SELECT_MASK (0x3 << 30)
-#define BCH_LAYOUTSELECT_CS15_SELECT_OFFSET 30
-#define BCH_LAYOUTSELECT_CS14_SELECT_MASK (0x3 << 28)
-#define BCH_LAYOUTSELECT_CS14_SELECT_OFFSET 28
-#define BCH_LAYOUTSELECT_CS13_SELECT_MASK (0x3 << 26)
-#define BCH_LAYOUTSELECT_CS13_SELECT_OFFSET 26
-#define BCH_LAYOUTSELECT_CS12_SELECT_MASK (0x3 << 24)
-#define BCH_LAYOUTSELECT_CS12_SELECT_OFFSET 24
-#define BCH_LAYOUTSELECT_CS11_SELECT_MASK (0x3 << 22)
-#define BCH_LAYOUTSELECT_CS11_SELECT_OFFSET 22
-#define BCH_LAYOUTSELECT_CS10_SELECT_MASK (0x3 << 20)
-#define BCH_LAYOUTSELECT_CS10_SELECT_OFFSET 20
-#define BCH_LAYOUTSELECT_CS9_SELECT_MASK (0x3 << 18)
-#define BCH_LAYOUTSELECT_CS9_SELECT_OFFSET 18
-#define BCH_LAYOUTSELECT_CS8_SELECT_MASK (0x3 << 16)
-#define BCH_LAYOUTSELECT_CS8_SELECT_OFFSET 16
-#define BCH_LAYOUTSELECT_CS7_SELECT_MASK (0x3 << 14)
-#define BCH_LAYOUTSELECT_CS7_SELECT_OFFSET 14
-#define BCH_LAYOUTSELECT_CS6_SELECT_MASK (0x3 << 12)
-#define BCH_LAYOUTSELECT_CS6_SELECT_OFFSET 12
-#define BCH_LAYOUTSELECT_CS5_SELECT_MASK (0x3 << 10)
-#define BCH_LAYOUTSELECT_CS5_SELECT_OFFSET 10
-#define BCH_LAYOUTSELECT_CS4_SELECT_MASK (0x3 << 8)
-#define BCH_LAYOUTSELECT_CS4_SELECT_OFFSET 8
-#define BCH_LAYOUTSELECT_CS3_SELECT_MASK (0x3 << 6)
-#define BCH_LAYOUTSELECT_CS3_SELECT_OFFSET 6
-#define BCH_LAYOUTSELECT_CS2_SELECT_MASK (0x3 << 4)
-#define BCH_LAYOUTSELECT_CS2_SELECT_OFFSET 4
-#define BCH_LAYOUTSELECT_CS1_SELECT_MASK (0x3 << 2)
-#define BCH_LAYOUTSELECT_CS1_SELECT_OFFSET 2
-#define BCH_LAYOUTSELECT_CS0_SELECT_MASK (0x3 << 0)
-#define BCH_LAYOUTSELECT_CS0_SELECT_OFFSET 0
-
-#define BCH_FLASHLAYOUT0_NBLOCKS_MASK (0xff << 24)
-#define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24
-#define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << 16)
-#define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16
-#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
-#define BCH_FLASHLAYOUT0_ECC0_MASK (0x1f << 11)
-#define BCH_FLASHLAYOUT0_ECC0_OFFSET 11
-#else
-#define BCH_FLASHLAYOUT0_ECC0_MASK (0xf << 12)
-#define BCH_FLASHLAYOUT0_ECC0_OFFSET 12
-#endif
-#define BCH_FLASHLAYOUT0_ECC0_NONE (0x0 << 12)
-#define BCH_FLASHLAYOUT0_ECC0_ECC2 (0x1 << 12)
-#define BCH_FLASHLAYOUT0_ECC0_ECC4 (0x2 << 12)
-#define BCH_FLASHLAYOUT0_ECC0_ECC6 (0x3 << 12)
-#define BCH_FLASHLAYOUT0_ECC0_ECC8 (0x4 << 12)
-#define BCH_FLASHLAYOUT0_ECC0_ECC10 (0x5 << 12)
-#define BCH_FLASHLAYOUT0_ECC0_ECC12 (0x6 << 12)
-#define BCH_FLASHLAYOUT0_ECC0_ECC14 (0x7 << 12)
-#define BCH_FLASHLAYOUT0_ECC0_ECC16 (0x8 << 12)
-#define BCH_FLASHLAYOUT0_ECC0_ECC18 (0x9 << 12)
-#define BCH_FLASHLAYOUT0_ECC0_ECC20 (0xa << 12)
-#define BCH_FLASHLAYOUT0_ECC0_ECC22 (0xb << 12)
-#define BCH_FLASHLAYOUT0_ECC0_ECC24 (0xc << 12)
-#define BCH_FLASHLAYOUT0_ECC0_ECC26 (0xd << 12)
-#define BCH_FLASHLAYOUT0_ECC0_ECC28 (0xe << 12)
-#define BCH_FLASHLAYOUT0_ECC0_ECC30 (0xf << 12)
-#define BCH_FLASHLAYOUT0_ECC0_ECC32 (0x10 << 12)
-#define BCH_FLASHLAYOUT0_GF13_0_GF14_1 (1 << 10)
-#define BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET 10
-#define BCH_FLASHLAYOUT0_DATA0_SIZE_MASK 0xfff
-#define BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET 0
-
-#define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16)
-#define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16
-#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
-#define BCH_FLASHLAYOUT1_ECCN_MASK (0x1f << 11)
-#define BCH_FLASHLAYOUT1_ECCN_OFFSET 11
-#else
-#define BCH_FLASHLAYOUT1_ECCN_MASK (0xf << 12)
-#define BCH_FLASHLAYOUT1_ECCN_OFFSET 12
-#endif
-#define BCH_FLASHLAYOUT1_ECCN_NONE (0x0 << 12)
-#define BCH_FLASHLAYOUT1_ECCN_ECC2 (0x1 << 12)
-#define BCH_FLASHLAYOUT1_ECCN_ECC4 (0x2 << 12)
-#define BCH_FLASHLAYOUT1_ECCN_ECC6 (0x3 << 12)
-#define BCH_FLASHLAYOUT1_ECCN_ECC8 (0x4 << 12)
-#define BCH_FLASHLAYOUT1_ECCN_ECC10 (0x5 << 12)
-#define BCH_FLASHLAYOUT1_ECCN_ECC12 (0x6 << 12)
-#define BCH_FLASHLAYOUT1_ECCN_ECC14 (0x7 << 12)
-#define BCH_FLASHLAYOUT1_ECCN_ECC16 (0x8 << 12)
-#define BCH_FLASHLAYOUT1_ECCN_ECC18 (0x9 << 12)
-#define BCH_FLASHLAYOUT1_ECCN_ECC20 (0xa << 12)
-#define BCH_FLASHLAYOUT1_ECCN_ECC22 (0xb << 12)
-#define BCH_FLASHLAYOUT1_ECCN_ECC24 (0xc << 12)
-#define BCH_FLASHLAYOUT1_ECCN_ECC26 (0xd << 12)
-#define BCH_FLASHLAYOUT1_ECCN_ECC28 (0xe << 12)
-#define BCH_FLASHLAYOUT1_ECCN_ECC30 (0xf << 12)
-#define BCH_FLASHLAYOUT1_ECCN_ECC32 (0x10 << 12)
-#define BCH_FLASHLAYOUT1_GF13_0_GF14_1 (1 << 10)
-#define BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET 10
-#define BCH_FLASHLAYOUT1_DATAN_SIZE_MASK 0xfff
-#define BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET 0
-
-#define BCH_DEBUG0_RSVD1_MASK (0x1f << 27)
-#define BCH_DEBUG0_RSVD1_OFFSET 27
-#define BCH_DEBUG0_ROM_BIST_ENABLE (1 << 26)
-#define BCH_DEBUG0_ROM_BIST_COMPLETE (1 << 25)
-#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1ff << 16)
-#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_OFFSET 16
-#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_NORMAL (0x0 << 16)
-#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_TEST_MODE (0x1 << 16)
-#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND (1 << 15)
-#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG (1 << 14)
-#define BCH_DEBUG0_KES_DEBUG_MODE4K (1 << 13)
-#define BCH_DEBUG0_KES_DEBUG_KICK (1 << 12)
-#define BCH_DEBUG0_KES_STANDALONE (1 << 11)
-#define BCH_DEBUG0_KES_DEBUG_STEP (1 << 10)
-#define BCH_DEBUG0_KES_DEBUG_STALL (1 << 9)
-#define BCH_DEBUG0_BM_KES_TEST_BYPASS (1 << 8)
-#define BCH_DEBUG0_RSVD0_MASK (0x3 << 6)
-#define BCH_DEBUG0_RSVD0_OFFSET 6
-#define BCH_DEBUG0_DEBUG_REG_SELECT_MASK 0x3f
-#define BCH_DEBUG0_DEBUG_REG_SELECT_OFFSET 0
-
-#define BCH_DBGKESREAD_VALUES_MASK 0xffffffff
-#define BCH_DBGKESREAD_VALUES_OFFSET 0
-
-#define BCH_DBGCSFEREAD_VALUES_MASK 0xffffffff
-#define BCH_DBGCSFEREAD_VALUES_OFFSET 0
-
-#define BCH_DBGSYNDGENREAD_VALUES_MASK 0xffffffff
-#define BCH_DBGSYNDGENREAD_VALUES_OFFSET 0
-
-#define BCH_DBGAHBMREAD_VALUES_MASK 0xffffffff
-#define BCH_DBGAHBMREAD_VALUES_OFFSET 0
-
-#define BCH_BLOCKNAME_NAME_MASK 0xffffffff
-#define BCH_BLOCKNAME_NAME_OFFSET 0
-
-#define BCH_VERSION_MAJOR_MASK (0xff << 24)
-#define BCH_VERSION_MAJOR_OFFSET 24
-#define BCH_VERSION_MINOR_MASK (0xff << 16)
-#define BCH_VERSION_MINOR_OFFSET 16
-#define BCH_VERSION_STEP_MASK 0xffff
-#define BCH_VERSION_STEP_OFFSET 0
-
-#endif /* __MX28_REGS_BCH_H__ */
+++ /dev/null
-/*
- * Freescale i.MXS Register Accessors
- *
- * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
- * on behalf of DENX Software Engineering GmbH
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __MXS_REGS_COMMON_H__
-#define __MXS_REGS_COMMON_H__
-
-#include <linux/types.h>
-
-/*
- * The i.MXS has interesting feature when it comes to register access. There
- * are four kinds of access to one particular register. Those are:
- *
- * 1) Common read/write access. To use this mode, just write to the address of
- * the register.
- * 2) Set bits only access. To set bits, write which bits you want to set to the
- * address of the register + 0x4.
- * 3) Clear bits only access. To clear bits, write which bits you want to clear
- * to the address of the register + 0x8.
- * 4) Toggle bits only access. To toggle bits, write which bits you want to
- * toggle to the address of the register + 0xc.
- *
- * IMPORTANT NOTE: Not all registers support accesses 2-4! Also, not all bits
- * can be set/cleared by pure write as in access type 1, some need to be
- * explicitly set/cleared by using access type 2-3.
- *
- * The following macros and structures allow the user to either access the
- * register in all aforementioned modes (by accessing reg_name, reg_name_set,
- * reg_name_clr, reg_name_tog) or pass the register structure further into
- * various functions with correct type information (by accessing reg_name_reg).
- *
- */
-
-#define __mxs_reg_8(name) \
- uint8_t name[4]; \
- uint8_t name##_set[4]; \
- uint8_t name##_clr[4]; \
- uint8_t name##_tog[4]; \
-
-#define __mxs_reg_32(name) \
- uint32_t name; \
- uint32_t name##_set; \
- uint32_t name##_clr; \
- uint32_t name##_tog;
-
-struct mxs_register_8 {
- __mxs_reg_8(reg)
-};
-
-struct mxs_register_32 {
- __mxs_reg_32(reg)
-};
-
-#define mxs_reg_8(name) \
- union { \
- struct { __mxs_reg_8(name) }; \
- struct mxs_register_8 name##_reg; \
- };
-
-#define mxs_reg_32(name) \
- union { \
- struct { __mxs_reg_32(name) }; \
- struct mxs_register_32 name##_reg; \
- };
-
-#endif /* __MXS_REGS_COMMON_H__ */
+++ /dev/null
-/*
- * Freescale i.MX28 GPMI Register Definitions
- *
- * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
- * on behalf of DENX Software Engineering GmbH
- *
- * Based on code from LTIB:
- * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __MX28_REGS_GPMI_H__
-#define __MX28_REGS_GPMI_H__
-
-#include <asm/imx-common/regs-common.h>
-
-#ifndef __ASSEMBLY__
-struct mxs_gpmi_regs {
- mxs_reg_32(hw_gpmi_ctrl0)
- mxs_reg_32(hw_gpmi_compare)
- mxs_reg_32(hw_gpmi_eccctrl)
- mxs_reg_32(hw_gpmi_ecccount)
- mxs_reg_32(hw_gpmi_payload)
- mxs_reg_32(hw_gpmi_auxiliary)
- mxs_reg_32(hw_gpmi_ctrl1)
- mxs_reg_32(hw_gpmi_timing0)
- mxs_reg_32(hw_gpmi_timing1)
-
- uint32_t reserved[4];
-
- mxs_reg_32(hw_gpmi_data)
- mxs_reg_32(hw_gpmi_stat)
- mxs_reg_32(hw_gpmi_debug)
- mxs_reg_32(hw_gpmi_version)
-};
-#endif
-
-#define GPMI_CTRL0_SFTRST (1 << 31)
-#define GPMI_CTRL0_CLKGATE (1 << 30)
-#define GPMI_CTRL0_RUN (1 << 29)
-#define GPMI_CTRL0_DEV_IRQ_EN (1 << 28)
-#define GPMI_CTRL0_LOCK_CS (1 << 27)
-#define GPMI_CTRL0_UDMA (1 << 26)
-#define GPMI_CTRL0_COMMAND_MODE_MASK (0x3 << 24)
-#define GPMI_CTRL0_COMMAND_MODE_OFFSET 24
-#define GPMI_CTRL0_COMMAND_MODE_WRITE (0x0 << 24)
-#define GPMI_CTRL0_COMMAND_MODE_READ (0x1 << 24)
-#define GPMI_CTRL0_COMMAND_MODE_READ_AND_COMPARE (0x2 << 24)
-#define GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY (0x3 << 24)
-#define GPMI_CTRL0_WORD_LENGTH (1 << 23)
-#define GPMI_CTRL0_CS_MASK (0x7 << 20)
-#define GPMI_CTRL0_CS_OFFSET 20
-#define GPMI_CTRL0_ADDRESS_MASK (0x7 << 17)
-#define GPMI_CTRL0_ADDRESS_OFFSET 17
-#define GPMI_CTRL0_ADDRESS_NAND_DATA (0x0 << 17)
-#define GPMI_CTRL0_ADDRESS_NAND_CLE (0x1 << 17)
-#define GPMI_CTRL0_ADDRESS_NAND_ALE (0x2 << 17)
-#define GPMI_CTRL0_ADDRESS_INCREMENT (1 << 16)
-#define GPMI_CTRL0_XFER_COUNT_MASK 0xffff
-#define GPMI_CTRL0_XFER_COUNT_OFFSET 0
-
-#define GPMI_COMPARE_MASK_MASK (0xffff << 16)
-#define GPMI_COMPARE_MASK_OFFSET 16
-#define GPMI_COMPARE_REFERENCE_MASK 0xffff
-#define GPMI_COMPARE_REFERENCE_OFFSET 0
-
-#define GPMI_ECCCTRL_HANDLE_MASK (0xffff << 16)
-#define GPMI_ECCCTRL_HANDLE_OFFSET 16
-#define GPMI_ECCCTRL_ECC_CMD_MASK (0x3 << 13)
-#define GPMI_ECCCTRL_ECC_CMD_OFFSET 13
-#define GPMI_ECCCTRL_ECC_CMD_DECODE (0x0 << 13)
-#define GPMI_ECCCTRL_ECC_CMD_ENCODE (0x1 << 13)
-#define GPMI_ECCCTRL_ENABLE_ECC (1 << 12)
-#define GPMI_ECCCTRL_BUFFER_MASK_MASK 0x1ff
-#define GPMI_ECCCTRL_BUFFER_MASK_OFFSET 0
-#define GPMI_ECCCTRL_BUFFER_MASK_BCH_AUXONLY 0x100
-#define GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE 0x1ff
-
-#define GPMI_ECCCOUNT_COUNT_MASK 0xffff
-#define GPMI_ECCCOUNT_COUNT_OFFSET 0
-
-#define GPMI_PAYLOAD_ADDRESS_MASK (0x3fffffff << 2)
-#define GPMI_PAYLOAD_ADDRESS_OFFSET 2
-
-#define GPMI_AUXILIARY_ADDRESS_MASK (0x3fffffff << 2)
-#define GPMI_AUXILIARY_ADDRESS_OFFSET 2
-
-#define GPMI_CTRL1_DECOUPLE_CS (1 << 24)
-#define GPMI_CTRL1_WRN_DLY_SEL_MASK (0x3 << 22)
-#define GPMI_CTRL1_WRN_DLY_SEL_OFFSET 22
-#define GPMI_CTRL1_TIMEOUT_IRQ_EN (1 << 20)
-#define GPMI_CTRL1_GANGED_RDYBUSY (1 << 19)
-#define GPMI_CTRL1_BCH_MODE (1 << 18)
-#define GPMI_CTRL1_DLL_ENABLE (1 << 17)
-#define GPMI_CTRL1_HALF_PERIOD (1 << 16)
-#define GPMI_CTRL1_RDN_DELAY_MASK (0xf << 12)
-#define GPMI_CTRL1_RDN_DELAY_OFFSET 12
-#define GPMI_CTRL1_DMA2ECC_MODE (1 << 11)
-#define GPMI_CTRL1_DEV_IRQ (1 << 10)
-#define GPMI_CTRL1_TIMEOUT_IRQ (1 << 9)
-#define GPMI_CTRL1_BURST_EN (1 << 8)
-#define GPMI_CTRL1_ABORT_WAIT_REQUEST (1 << 7)
-#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x7 << 4)
-#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_OFFSET 4
-#define GPMI_CTRL1_DEV_RESET (1 << 3)
-#define GPMI_CTRL1_ATA_IRQRDY_POLARITY (1 << 2)
-#define GPMI_CTRL1_CAMERA_MODE (1 << 1)
-#define GPMI_CTRL1_GPMI_MODE (1 << 0)
-
-#define GPMI_TIMING0_ADDRESS_SETUP_MASK (0xff << 16)
-#define GPMI_TIMING0_ADDRESS_SETUP_OFFSET 16
-#define GPMI_TIMING0_DATA_HOLD_MASK (0xff << 8)
-#define GPMI_TIMING0_DATA_HOLD_OFFSET 8
-#define GPMI_TIMING0_DATA_SETUP_MASK 0xff
-#define GPMI_TIMING0_DATA_SETUP_OFFSET 0
-
-#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK (0xffff << 16)
-#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_OFFSET 16
-
-#define GPMI_TIMING2_UDMA_TRP_MASK (0xff << 24)
-#define GPMI_TIMING2_UDMA_TRP_OFFSET 24
-#define GPMI_TIMING2_UDMA_ENV_MASK (0xff << 16)
-#define GPMI_TIMING2_UDMA_ENV_OFFSET 16
-#define GPMI_TIMING2_UDMA_HOLD_MASK (0xff << 8)
-#define GPMI_TIMING2_UDMA_HOLD_OFFSET 8
-#define GPMI_TIMING2_UDMA_SETUP_MASK 0xff
-#define GPMI_TIMING2_UDMA_SETUP_OFFSET 0
-
-#define GPMI_DATA_DATA_MASK 0xffffffff
-#define GPMI_DATA_DATA_OFFSET 0
-
-#define GPMI_STAT_READY_BUSY_MASK (0xff << 24)
-#define GPMI_STAT_READY_BUSY_OFFSET 24
-#define GPMI_STAT_RDY_TIMEOUT_MASK (0xff << 16)
-#define GPMI_STAT_RDY_TIMEOUT_OFFSET 16
-#define GPMI_STAT_DEV7_ERROR (1 << 15)
-#define GPMI_STAT_DEV6_ERROR (1 << 14)
-#define GPMI_STAT_DEV5_ERROR (1 << 13)
-#define GPMI_STAT_DEV4_ERROR (1 << 12)
-#define GPMI_STAT_DEV3_ERROR (1 << 11)
-#define GPMI_STAT_DEV2_ERROR (1 << 10)
-#define GPMI_STAT_DEV1_ERROR (1 << 9)
-#define GPMI_STAT_DEV0_ERROR (1 << 8)
-#define GPMI_STAT_ATA_IRQ (1 << 4)
-#define GPMI_STAT_INVALID_BUFFER_MASK (1 << 3)
-#define GPMI_STAT_FIFO_EMPTY (1 << 2)
-#define GPMI_STAT_FIFO_FULL (1 << 1)
-#define GPMI_STAT_PRESENT (1 << 0)
-
-#define GPMI_DEBUG_WAIT_FOR_READY_END_MASK (0xff << 24)
-#define GPMI_DEBUG_WAIT_FOR_READY_END_OFFSET 24
-#define GPMI_DEBUG_DMA_SENSE_MASK (0xff << 16)
-#define GPMI_DEBUG_DMA_SENSE_OFFSET 16
-#define GPMI_DEBUG_DMAREQ_MASK (0xff << 8)
-#define GPMI_DEBUG_DMAREQ_OFFSET 8
-#define GPMI_DEBUG_CMD_END_MASK 0xff
-#define GPMI_DEBUG_CMD_END_OFFSET 0
-
-#define GPMI_VERSION_MAJOR_MASK (0xff << 24)
-#define GPMI_VERSION_MAJOR_OFFSET 24
-#define GPMI_VERSION_MINOR_MASK (0xff << 16)
-#define GPMI_VERSION_MINOR_OFFSET 16
-#define GPMI_VERSION_STEP_MASK 0xffff
-#define GPMI_VERSION_STEP_OFFSET 0
-
-#define GPMI_DEBUG2_UDMA_STATE_MASK (0xf << 24)
-#define GPMI_DEBUG2_UDMA_STATE_OFFSET 24
-#define GPMI_DEBUG2_BUSY (1 << 23)
-#define GPMI_DEBUG2_PIN_STATE_MASK (0x7 << 20)
-#define GPMI_DEBUG2_PIN_STATE_OFFSET 20
-#define GPMI_DEBUG2_PIN_STATE_PSM_IDLE (0x0 << 20)
-#define GPMI_DEBUG2_PIN_STATE_PSM_BYTCNT (0x1 << 20)
-#define GPMI_DEBUG2_PIN_STATE_PSM_ADDR (0x2 << 20)
-#define GPMI_DEBUG2_PIN_STATE_PSM_STALL (0x3 << 20)
-#define GPMI_DEBUG2_PIN_STATE_PSM_STROBE (0x4 << 20)
-#define GPMI_DEBUG2_PIN_STATE_PSM_ATARDY (0x5 << 20)
-#define GPMI_DEBUG2_PIN_STATE_PSM_DHOLD (0x6 << 20)
-#define GPMI_DEBUG2_PIN_STATE_PSM_DONE (0x7 << 20)
-#define GPMI_DEBUG2_MAIN_STATE_MASK (0xf << 16)
-#define GPMI_DEBUG2_MAIN_STATE_OFFSET 16
-#define GPMI_DEBUG2_MAIN_STATE_MSM_IDLE (0x0 << 16)
-#define GPMI_DEBUG2_MAIN_STATE_MSM_BYTCNT (0x1 << 16)
-#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFE (0x2 << 16)
-#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFR (0x3 << 16)
-#define GPMI_DEBUG2_MAIN_STATE_MSM_DMAREQ (0x4 << 16)
-#define GPMI_DEBUG2_MAIN_STATE_MSM_DMAACK (0x5 << 16)
-#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFF (0x6 << 16)
-#define GPMI_DEBUG2_MAIN_STATE_MSM_LDFIFO (0x7 << 16)
-#define GPMI_DEBUG2_MAIN_STATE_MSM_LDDMAR (0x8 << 16)
-#define GPMI_DEBUG2_MAIN_STATE_MSM_RDCMP (0x9 << 16)
-#define GPMI_DEBUG2_MAIN_STATE_MSM_DONE (0xa << 16)
-#define GPMI_DEBUG2_SYND2GPMI_BE_MASK (0xf << 12)
-#define GPMI_DEBUG2_SYND2GPMI_BE_OFFSET 12
-#define GPMI_DEBUG2_GPMI2SYND_VALID (1 << 11)
-#define GPMI_DEBUG2_GPMI2SYND_READY (1 << 10)
-#define GPMI_DEBUG2_SYND2GPMI_VALID (1 << 9)
-#define GPMI_DEBUG2_SYND2GPMI_READY (1 << 8)
-#define GPMI_DEBUG2_VIEW_DELAYED_RDN (1 << 7)
-#define GPMI_DEBUG2_UPDATE_WINDOW (1 << 6)
-#define GPMI_DEBUG2_RDN_TAP_MASK 0x3f
-#define GPMI_DEBUG2_RDN_TAP_OFFSET 0
-
-#define GPMI_DEBUG3_APB_WORD_CNTR_MASK (0xffff << 16)
-#define GPMI_DEBUG3_APB_WORD_CNTR_OFFSET 16
-#define GPMI_DEBUG3_DEV_WORD_CNTR_MASK 0xffff
-#define GPMI_DEBUG3_DEV_WORD_CNTR_OFFSET 0
-
-#endif /* __MX28_REGS_GPMI_H__ */
+++ /dev/null
-/*
- * Freescale i.MX28/6SX/6UL/7D LCDIF Register Definitions
- *
- * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
- * on behalf of DENX Software Engineering GmbH
- *
- * Based on code from LTIB:
- * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __IMX_REGS_LCDIF_H__
-#define __IMX_REGS_LCDIF_H__
-
-#ifndef __ASSEMBLY__
-#include <asm/imx-common/regs-common.h>
-
-struct mxs_lcdif_regs {
- mxs_reg_32(hw_lcdif_ctrl) /* 0x00 */
- mxs_reg_32(hw_lcdif_ctrl1) /* 0x10 */
-#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
- defined(CONFIG_MX7) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
- mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */
-#endif
- mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */
- mxs_reg_32(hw_lcdif_cur_buf) /* 0x30/0x40 */
- mxs_reg_32(hw_lcdif_next_buf) /* 0x40/0x50 */
-
-#if defined(CONFIG_MX23)
- uint32_t reserved1[4];
-#endif
-
- mxs_reg_32(hw_lcdif_timing) /* 0x60 */
- mxs_reg_32(hw_lcdif_vdctrl0) /* 0x70 */
- mxs_reg_32(hw_lcdif_vdctrl1) /* 0x80 */
- mxs_reg_32(hw_lcdif_vdctrl2) /* 0x90 */
- mxs_reg_32(hw_lcdif_vdctrl3) /* 0xa0 */
- mxs_reg_32(hw_lcdif_vdctrl4) /* 0xb0 */
- mxs_reg_32(hw_lcdif_dvictrl0) /* 0xc0 */
- mxs_reg_32(hw_lcdif_dvictrl1) /* 0xd0 */
- mxs_reg_32(hw_lcdif_dvictrl2) /* 0xe0 */
- mxs_reg_32(hw_lcdif_dvictrl3) /* 0xf0 */
- mxs_reg_32(hw_lcdif_dvictrl4) /* 0x100 */
- mxs_reg_32(hw_lcdif_csc_coeffctrl0) /* 0x110 */
- mxs_reg_32(hw_lcdif_csc_coeffctrl1) /* 0x120 */
- mxs_reg_32(hw_lcdif_csc_coeffctrl2) /* 0x130 */
- mxs_reg_32(hw_lcdif_csc_coeffctrl3) /* 0x140 */
- mxs_reg_32(hw_lcdif_csc_coeffctrl4) /* 0x150 */
- mxs_reg_32(hw_lcdif_csc_offset) /* 0x160 */
- mxs_reg_32(hw_lcdif_csc_limit) /* 0x170 */
-
-#if defined(CONFIG_MX23)
- uint32_t reserved2[12];
-#endif
- mxs_reg_32(hw_lcdif_data) /* 0x1b0/0x180 */
- mxs_reg_32(hw_lcdif_bm_error_stat) /* 0x1c0/0x190 */
-#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
- defined(CONFIG_MX7) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
- mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */
-#endif
- mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */
- mxs_reg_32(hw_lcdif_version) /* 0x1e0/0x1c0 */
- mxs_reg_32(hw_lcdif_debug0) /* 0x1f0/0x1d0 */
- mxs_reg_32(hw_lcdif_debug1) /* 0x200/0x1e0 */
- mxs_reg_32(hw_lcdif_debug2) /* 0x1f0 */
-#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX7) || \
- defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
- mxs_reg_32(hw_lcdif_thres)
- mxs_reg_32(hw_lcdif_as_ctrl)
- mxs_reg_32(hw_lcdif_as_buf)
- mxs_reg_32(hw_lcdif_as_next_buf)
- mxs_reg_32(hw_lcdif_as_clrkeylow)
- mxs_reg_32(hw_lcdif_as_clrkeyhigh)
- mxs_reg_32(hw_lcdif_as_sync_delay)
- mxs_reg_32(hw_lcdif_as_debug3)
- mxs_reg_32(hw_lcdif_as_debug4)
- mxs_reg_32(hw_lcdif_as_debug5)
-#endif
-};
-#endif
-
-#define LCDIF_CTRL_SFTRST (1 << 31)
-#define LCDIF_CTRL_CLKGATE (1 << 30)
-#define LCDIF_CTRL_YCBCR422_INPUT (1 << 29)
-#define LCDIF_CTRL_READ_WRITEB (1 << 28)
-#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE (1 << 27)
-#define LCDIF_CTRL_DATA_SHIFT_DIR (1 << 26)
-#define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x1f << 21)
-#define LCDIF_CTRL_SHIFT_NUM_BITS_OFFSET 21
-#define LCDIF_CTRL_DVI_MODE (1 << 20)
-#define LCDIF_CTRL_BYPASS_COUNT (1 << 19)
-#define LCDIF_CTRL_VSYNC_MODE (1 << 18)
-#define LCDIF_CTRL_DOTCLK_MODE (1 << 17)
-#define LCDIF_CTRL_DATA_SELECT (1 << 16)
-#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0x3 << 14)
-#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET 14
-#define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3 << 12)
-#define LCDIF_CTRL_CSC_DATA_SWIZZLE_OFFSET 12
-#define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0x3 << 10)
-#define LCDIF_CTRL_LCD_DATABUS_WIDTH_OFFSET 10
-#define LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT (0 << 10)
-#define LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT (1 << 10)
-#define LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT (2 << 10)
-#define LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT (3 << 10)
-#define LCDIF_CTRL_WORD_LENGTH_MASK (0x3 << 8)
-#define LCDIF_CTRL_WORD_LENGTH_OFFSET 8
-#define LCDIF_CTRL_WORD_LENGTH_16BIT (0 << 8)
-#define LCDIF_CTRL_WORD_LENGTH_8BIT (1 << 8)
-#define LCDIF_CTRL_WORD_LENGTH_18BIT (2 << 8)
-#define LCDIF_CTRL_WORD_LENGTH_24BIT (3 << 8)
-#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC (1 << 7)
-#define LCDIF_CTRL_LCDIF_MASTER (1 << 5)
-#define LCDIF_CTRL_DATA_FORMAT_16_BIT (1 << 3)
-#define LCDIF_CTRL_DATA_FORMAT_18_BIT (1 << 2)
-#define LCDIF_CTRL_DATA_FORMAT_24_BIT (1 << 1)
-#define LCDIF_CTRL_RUN (1 << 0)
-
-#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB (1 << 27)
-#define LCDIF_CTRL1_BM_ERROR_IRQ_EN (1 << 26)
-#define LCDIF_CTRL1_BM_ERROR_IRQ (1 << 25)
-#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW (1 << 24)
-#define LCDIF_CTRL1_INTERLACE_FIELDS (1 << 23)
-#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD (1 << 22)
-#define LCDIF_CTRL1_FIFO_CLEAR (1 << 21)
-#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS (1 << 20)
-#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xf << 16)
-#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET 16
-#define LCDIF_CTRL1_OVERFLOW_IRQ_EN (1 << 15)
-#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN (1 << 14)
-#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN (1 << 13)
-#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN (1 << 12)
-#define LCDIF_CTRL1_OVERFLOW_IRQ (1 << 11)
-#define LCDIF_CTRL1_UNDERFLOW_IRQ (1 << 10)
-#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ (1 << 9)
-#define LCDIF_CTRL1_VSYNC_EDGE_IRQ (1 << 8)
-#define LCDIF_CTRL1_BUSY_ENABLE (1 << 2)
-#define LCDIF_CTRL1_MODE86 (1 << 1)
-#define LCDIF_CTRL1_RESET (1 << 0)
-
-#define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0x7 << 21)
-#define LCDIF_CTRL2_OUTSTANDING_REQS_OFFSET 21
-#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_1 (0x0 << 21)
-#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2 (0x1 << 21)
-#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_4 (0x2 << 21)
-#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_8 (0x3 << 21)
-#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16 (0x4 << 21)
-#define LCDIF_CTRL2_BURST_LEN_8 (1 << 20)
-#define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x7 << 16)
-#define LCDIF_CTRL2_ODD_LINE_PATTERN_OFFSET 16
-#define LCDIF_CTRL2_ODD_LINE_PATTERN_RGB (0x0 << 16)
-#define LCDIF_CTRL2_ODD_LINE_PATTERN_RBG (0x1 << 16)
-#define LCDIF_CTRL2_ODD_LINE_PATTERN_GBR (0x2 << 16)
-#define LCDIF_CTRL2_ODD_LINE_PATTERN_GRB (0x3 << 16)
-#define LCDIF_CTRL2_ODD_LINE_PATTERN_BRG (0x4 << 16)
-#define LCDIF_CTRL2_ODD_LINE_PATTERN_BGR (0x5 << 16)
-#define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7 << 12)
-#define LCDIF_CTRL2_EVEN_LINE_PATTERN_OFFSET 12
-#define LCDIF_CTRL2_EVEN_LINE_PATTERN_RGB (0x0 << 12)
-#define LCDIF_CTRL2_EVEN_LINE_PATTERN_RBG (0x1 << 12)
-#define LCDIF_CTRL2_EVEN_LINE_PATTERN_GBR (0x2 << 12)
-#define LCDIF_CTRL2_EVEN_LINE_PATTERN_GRB (0x3 << 12)
-#define LCDIF_CTRL2_EVEN_LINE_PATTERN_BRG (0x4 << 12)
-#define LCDIF_CTRL2_EVEN_LINE_PATTERN_BGR (0x5 << 12)
-#define LCDIF_CTRL2_READ_PACK_DIR (1 << 10)
-#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT (1 << 9)
-#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT (1 << 8)
-#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x7 << 4)
-#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_OFFSET 4
-#define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0x7 << 1)
-#define LCDIF_CTRL2_INITIAL_DUMMY_READ_OFFSET 1
-
-#define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xffff << 16)
-#define LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET 16
-#define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xffff << 0)
-#define LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET 0
-
-#define LCDIF_CUR_BUF_ADDR_MASK 0xffffffff
-#define LCDIF_CUR_BUF_ADDR_OFFSET 0
-
-#define LCDIF_NEXT_BUF_ADDR_MASK 0xffffffff
-#define LCDIF_NEXT_BUF_ADDR_OFFSET 0
-
-#define LCDIF_TIMING_CMD_HOLD_MASK (0xff << 24)
-#define LCDIF_TIMING_CMD_HOLD_OFFSET 24
-#define LCDIF_TIMING_CMD_SETUP_MASK (0xff << 16)
-#define LCDIF_TIMING_CMD_SETUP_OFFSET 16
-#define LCDIF_TIMING_DATA_HOLD_MASK (0xff << 8)
-#define LCDIF_TIMING_DATA_HOLD_OFFSET 8
-#define LCDIF_TIMING_DATA_SETUP_MASK (0xff << 0)
-#define LCDIF_TIMING_DATA_SETUP_OFFSET 0
-
-#define LCDIF_VDCTRL0_VSYNC_OEB (1 << 29)
-#define LCDIF_VDCTRL0_ENABLE_PRESENT (1 << 28)
-#define LCDIF_VDCTRL0_VSYNC_POL (1 << 27)
-#define LCDIF_VDCTRL0_HSYNC_POL (1 << 26)
-#define LCDIF_VDCTRL0_DOTCLK_POL (1 << 25)
-#define LCDIF_VDCTRL0_ENABLE_POL (1 << 24)
-#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21)
-#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20)
-#define LCDIF_VDCTRL0_HALF_LINE (1 << 19)
-#define LCDIF_VDCTRL0_HALF_LINE_MODE (1 << 18)
-#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK 0x3ffff
-#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET 0
-
-#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK 0xffffffff
-#define LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET 0
-
-#if defined(CONFIG_MX23)
-#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xff << 24)
-#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 24
-#else
-#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18)
-#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18
-#endif
-#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK 0x3ffff
-#define LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET 0
-
-#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS (1 << 29)
-#define LCDIF_VDCTRL3_VSYNC_ONLY (1 << 28)
-#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xfff << 16)
-#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET 16
-#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xffff << 0)
-#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET 0
-
-#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0x7 << 29)
-#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET 29
-#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON (1 << 18)
-#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff
-#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0
-
-#endif /* __IMX_REGS_LCDIF_H__ */
+++ /dev/null
-/*
- * Freescale USB PHY Register Definitions
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- */
-
-#ifndef __REGS_USBPHY_H__
-#define __REGS_USBPHY_H__
-
-#define USBPHY_CTRL 0x00000030
-#define USBPHY_CTRL_SET 0x00000034
-#define USBPHY_CTRL_CLR 0x00000038
-#define USBPHY_CTRL_TOG 0x0000003C
-#define USBPHY_PWD 0x00000000
-#define USBPHY_TX 0x00000010
-#define USBPHY_RX 0x00000020
-#define USBPHY_DEBUG 0x00000050
-
-#define USBPHY_CTRL_ENUTMILEVEL2 (1 << 14)
-#define USBPHY_CTRL_ENUTMILEVEL3 (1 << 15)
-#define USBPHY_CTRL_OTG_ID (1 << 27)
-#define USBPHY_CTRL_CLKGATE (1 << 30)
-#define USBPHY_CTRL_SFTRST (1 << 31)
-
-#endif /* __REGS_USBPHY_H__ */
+++ /dev/null
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __IMX_SATA_H_
-#define __IMX_SATA_H_
-
-/*
- * SATA setup for i.mx6 quad based platform
- */
-
-int setup_sata(void);
-
-#endif
+++ /dev/null
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __MXC_SPI_H_
-#define __MXC_SPI_H_
-
-/*
- * Board-level chip-select callback
- * Should return GPIO # to be used for chip-select
- */
-
-int board_spi_cs_gpio(unsigned bus, unsigned cs);
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _SYS_PROTO_H_
-#define _SYS_PROTO_H_
-
-#include <asm/io.h>
-#include <asm/imx-common/regs-common.h>
-#include <common.h>
-#include "../arch-imx/cpu.h"
-
-#define soc_rev() (get_cpu_rev() & 0xFF)
-#define is_soc_rev(rev) (soc_rev() == rev)
-
-/* returns MXC_CPU_ value */
-#define cpu_type(rev) (((rev) >> 12) & 0xff)
-#define soc_type(rev) (((rev) >> 12) & 0xf0)
-/* both macros return/take MXC_CPU_ constants */
-#define get_cpu_type() (cpu_type(get_cpu_rev()))
-#define get_soc_type() (soc_type(get_cpu_rev()))
-#define is_cpu_type(cpu) (get_cpu_type() == cpu)
-#define is_soc_type(soc) (get_soc_type() == soc)
-
-#define is_mx6() (is_soc_type(MXC_SOC_MX6))
-#define is_mx7() (is_soc_type(MXC_SOC_MX7))
-
-#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
-#define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
-#define is_mx6sdl() (is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6DL))
-#define is_mx6dl() (is_cpu_type(MXC_CPU_MX6DL))
-#define is_mx6sx() (is_cpu_type(MXC_CPU_MX6SX))
-#define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL))
-#define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO))
-#define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL))
-#define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL))
-#define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL))
-
-#define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP))
-
-#ifdef CONFIG_MX6
-#define IMX6_SRC_GPR10_BMODE BIT(28)
-
-#define IMX6_BMODE_MASK GENMASK(7, 0)
-#define IMX6_BMODE_SHIFT 4
-#define IMX6_BMODE_EMI_MASK BIT(3)
-#define IMX6_BMODE_EMI_SHIFT 3
-#define IMX6_BMODE_SERIAL_ROM_MASK GENMASK(26, 24)
-#define IMX6_BMODE_SERIAL_ROM_SHIFT 24
-
-enum imx6_bmode_serial_rom {
- IMX6_BMODE_ECSPI1,
- IMX6_BMODE_ECSPI2,
- IMX6_BMODE_ECSPI3,
- IMX6_BMODE_ECSPI4,
- IMX6_BMODE_ECSPI5,
- IMX6_BMODE_I2C1,
- IMX6_BMODE_I2C2,
- IMX6_BMODE_I2C3,
-};
-
-enum imx6_bmode_emi {
- IMX6_BMODE_ONENAND,
- IMX6_BMODE_NOR,
-};
-
-enum imx6_bmode {
- IMX6_BMODE_EMI,
- IMX6_BMODE_UART,
- IMX6_BMODE_SATA,
- IMX6_BMODE_SERIAL_ROM,
- IMX6_BMODE_SD,
- IMX6_BMODE_ESD,
- IMX6_BMODE_MMC,
- IMX6_BMODE_EMMC,
- IMX6_BMODE_NAND,
-};
-
-static inline u8 imx6_is_bmode_from_gpr9(void)
-{
- return readl(&src_base->gpr10) & IMX6_SRC_GPR10_BMODE;
-}
-
-u32 imx6_src_get_boot_mode(void);
-#endif /* CONFIG_MX6 */
-
-u32 get_nr_cpus(void);
-u32 get_cpu_rev(void);
-u32 get_cpu_speed_grade_hz(void);
-u32 get_cpu_temp_grade(int *minc, int *maxc);
-const char *get_imx_type(u32 imxtype);
-u32 imx_ddr_size(void);
-void sdelay(unsigned long);
-void set_chipselect_size(int const);
-
-void init_aips(void);
-void init_src(void);
-void imx_set_wdog_powerdown(bool enable);
-
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-int fecmxc_initialize(bd_t *bis);
-u32 get_ahb_clk(void);
-u32 get_periph_clk(void);
-
-void lcdif_power_down(void);
-
-int mxs_reset_block(struct mxs_register_32 *reg);
-int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
-int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2015 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ASM_ARCH_SYSTEM_COUNTER_H
-#define _ASM_ARCH_SYSTEM_COUNTER_H
-
-/* System Counter */
-struct sctr_regs {
- u32 cntcr;
- u32 cntsr;
- u32 cntcv1;
- u32 cntcv2;
- u32 resv1[4];
- u32 cntfid0;
- u32 cntfid1;
- u32 cntfid2;
- u32 resv2[1001];
- u32 counterid[1];
-};
-
-#define SC_CNTCR_ENABLE (1 << 0)
-#define SC_CNTCR_HDBG (1 << 1)
-#define SC_CNTCR_FREQ0 (1 << 8)
-#define SC_CNTCR_FREQ1 (1 << 9)
-
-#endif
+++ /dev/null
-/*
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __IMX_VIDEO_H_
-#define __IMX_VIDEO_H_
-
-#include <linux/fb.h>
-#include <ipu_pixfmt.h>
-
-struct display_info_t {
- int bus;
- int addr;
- int pixfmt;
- int di;
- int (*detect)(struct display_info_t const *dev);
- void (*enable)(struct display_info_t const *dev);
- struct fb_videomode mode;
-};
-
-#ifdef CONFIG_IMX_HDMI
-extern int detect_hdmi(struct display_info_t const *dev);
-#endif
-
-#ifdef CONFIG_IMX_VIDEO_SKIP
-extern struct display_info_t const displays[];
-extern size_t display_count;
-#endif
-
-int ipu_set_ldb_clock(int rate);
-#endif
--- /dev/null
+/*
+ * Copyright (C) 2012 Boundary Devices Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_BOOT_MODE_H
+#define _ASM_BOOT_MODE_H
+#define MAKE_CFGVAL(cfg1, cfg2, cfg3, cfg4) \
+ ((cfg4) << 24) | ((cfg3) << 16) | ((cfg2) << 8) | (cfg1)
+
+enum boot_device {
+ WEIM_NOR_BOOT,
+ ONE_NAND_BOOT,
+ PATA_BOOT,
+ SATA_BOOT,
+ I2C_BOOT,
+ SPI_NOR_BOOT,
+ SD1_BOOT,
+ SD2_BOOT,
+ SD3_BOOT,
+ SD4_BOOT,
+ MMC1_BOOT,
+ MMC2_BOOT,
+ MMC3_BOOT,
+ MMC4_BOOT,
+ NAND_BOOT,
+ QSPI_BOOT,
+ UNKNOWN_BOOT,
+ BOOT_DEV_NUM = UNKNOWN_BOOT,
+};
+
+struct boot_mode {
+ const char *name;
+ unsigned cfg_val;
+};
+
+void add_board_boot_modes(const struct boot_mode *p);
+void boot_mode_apply(unsigned cfg_val);
+extern const struct boot_mode soc_boot_modes[];
+#endif
--- /dev/null
+/*
+ * Freescale i.MX28 APBH DMA
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DMA_H__
+#define __DMA_H__
+
+#include <linux/list.h>
+#include <linux/compiler.h>
+
+#define DMA_PIO_WORDS 15
+#define MXS_DMA_ALIGNMENT ARCH_DMA_MINALIGN
+
+/*
+ * MXS DMA channels
+ */
+#if defined(CONFIG_MX23)
+enum {
+ MXS_DMA_CHANNEL_AHB_APBH_LCDIF = 0,
+ MXS_DMA_CHANNEL_AHB_APBH_SSP0,
+ MXS_DMA_CHANNEL_AHB_APBH_SSP1,
+ MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
+ MXS_MAX_DMA_CHANNELS,
+};
+#elif defined(CONFIG_MX28)
+enum {
+ MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0,
+ MXS_DMA_CHANNEL_AHB_APBH_SSP1,
+ MXS_DMA_CHANNEL_AHB_APBH_SSP2,
+ MXS_DMA_CHANNEL_AHB_APBH_SSP3,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
+ MXS_DMA_CHANNEL_AHB_APBH_HSADC,
+ MXS_DMA_CHANNEL_AHB_APBH_LCDIF,
+ MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
+ MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
+ MXS_MAX_DMA_CHANNELS,
+};
+#elif defined(CONFIG_MX6) || defined(CONFIG_MX7)
+enum {
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
+ MXS_MAX_DMA_CHANNELS,
+};
+#endif
+
+/*
+ * MXS DMA hardware command.
+ *
+ * This structure describes the in-memory layout of an entire DMA command,
+ * including space for the maximum number of PIO accesses. See the appropriate
+ * reference manual for a detailed description of what these fields mean to the
+ * DMA hardware.
+ */
+#define MXS_DMA_DESC_COMMAND_MASK 0x3
+#define MXS_DMA_DESC_COMMAND_OFFSET 0
+#define MXS_DMA_DESC_COMMAND_NO_DMAXFER 0x0
+#define MXS_DMA_DESC_COMMAND_DMA_WRITE 0x1
+#define MXS_DMA_DESC_COMMAND_DMA_READ 0x2
+#define MXS_DMA_DESC_COMMAND_DMA_SENSE 0x3
+#define MXS_DMA_DESC_CHAIN (1 << 2)
+#define MXS_DMA_DESC_IRQ (1 << 3)
+#define MXS_DMA_DESC_NAND_LOCK (1 << 4)
+#define MXS_DMA_DESC_NAND_WAIT_4_READY (1 << 5)
+#define MXS_DMA_DESC_DEC_SEM (1 << 6)
+#define MXS_DMA_DESC_WAIT4END (1 << 7)
+#define MXS_DMA_DESC_HALT_ON_TERMINATE (1 << 8)
+#define MXS_DMA_DESC_TERMINATE_FLUSH (1 << 9)
+#define MXS_DMA_DESC_PIO_WORDS_MASK (0xf << 12)
+#define MXS_DMA_DESC_PIO_WORDS_OFFSET 12
+#define MXS_DMA_DESC_BYTES_MASK (0xffff << 16)
+#define MXS_DMA_DESC_BYTES_OFFSET 16
+
+struct mxs_dma_cmd {
+ unsigned long next;
+ unsigned long data;
+ union {
+ dma_addr_t address;
+ unsigned long alternate;
+ };
+ unsigned long pio_words[DMA_PIO_WORDS];
+};
+
+/*
+ * MXS DMA command descriptor.
+ *
+ * This structure incorporates an MXS DMA hardware command structure, along
+ * with metadata.
+ */
+#define MXS_DMA_DESC_FIRST (1 << 0)
+#define MXS_DMA_DESC_LAST (1 << 1)
+#define MXS_DMA_DESC_READY (1 << 31)
+
+struct mxs_dma_desc {
+ struct mxs_dma_cmd cmd;
+ unsigned int flags;
+ dma_addr_t address;
+ void *buffer;
+ struct list_head node;
+} __aligned(MXS_DMA_ALIGNMENT);
+
+/**
+ * MXS DMA channel
+ *
+ * This structure represents a single DMA channel. The MXS platform code
+ * maintains an array of these structures to represent every DMA channel in the
+ * system (see mxs_dma_channels).
+ */
+#define MXS_DMA_FLAGS_IDLE 0
+#define MXS_DMA_FLAGS_BUSY (1 << 0)
+#define MXS_DMA_FLAGS_FREE 0
+#define MXS_DMA_FLAGS_ALLOCATED (1 << 16)
+#define MXS_DMA_FLAGS_VALID (1 << 31)
+
+struct mxs_dma_chan {
+ const char *name;
+ unsigned long dev;
+ struct mxs_dma_device *dma;
+ unsigned int flags;
+ unsigned int active_num;
+ unsigned int pending_num;
+ struct list_head active;
+ struct list_head done;
+};
+
+struct mxs_dma_desc *mxs_dma_desc_alloc(void);
+void mxs_dma_desc_free(struct mxs_dma_desc *);
+int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc);
+
+int mxs_dma_go(int chan);
+void mxs_dma_init(void);
+int mxs_dma_init_channel(int chan);
+int mxs_dma_release(int chan);
+
+void mxs_dma_circ_start(int chan, struct mxs_dma_desc *pdesc);
+
+#endif /* __DMA_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2011
+ * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+
+#ifndef __ASM_ARCH_IMX_GPIO_H
+#define __ASM_ARCH_IMX_GPIO_H
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+/* GPIO registers */
+struct gpio_regs {
+ u32 gpio_dr; /* data */
+ u32 gpio_dir; /* direction */
+ u32 gpio_psr; /* pad satus */
+};
+#endif
+
+#define IMX_GPIO_NR(port, index) ((((port)-1)*32)+((index)&31))
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+*/
+
+#ifndef __SECURE_MX6Q_H__
+#define __SECURE_MX6Q_H__
+
+#include <linux/types.h>
+
+/* -------- start of HAB API updates ------------*/
+/* The following are taken from HAB4 SIS */
+
+/* Status definitions */
+enum hab_status {
+ HAB_STS_ANY = 0x00,
+ HAB_FAILURE = 0x33,
+ HAB_WARNING = 0x69,
+ HAB_SUCCESS = 0xf0
+};
+
+/* Security Configuration definitions */
+enum hab_config {
+ HAB_CFG_RETURN = 0x33, /* < Field Return IC */
+ HAB_CFG_OPEN = 0xf0, /* < Non-secure IC */
+ HAB_CFG_CLOSED = 0xcc /* < Secure IC */
+};
+
+/* State definitions */
+enum hab_state {
+ HAB_STATE_INITIAL = 0x33, /* Initialising state (transitory) */
+ HAB_STATE_CHECK = 0x55, /* Check state (non-secure) */
+ HAB_STATE_NONSECURE = 0x66, /* Non-secure state */
+ HAB_STATE_TRUSTED = 0x99, /* Trusted state */
+ HAB_STATE_SECURE = 0xaa, /* Secure state */
+ HAB_STATE_FAIL_SOFT = 0xcc, /* Soft fail state */
+ HAB_STATE_FAIL_HARD = 0xff, /* Hard fail state (terminal) */
+ HAB_STATE_NONE = 0xf0, /* No security state machine */
+ HAB_STATE_MAX
+};
+
+enum hab_reason {
+ HAB_RSN_ANY = 0x00, /* Match any reason */
+ HAB_ENG_FAIL = 0x30, /* Engine failure */
+ HAB_INV_ADDRESS = 0x22, /* Invalid address: access denied */
+ HAB_INV_ASSERTION = 0x0c, /* Invalid assertion */
+ HAB_INV_CALL = 0x28, /* Function called out of sequence */
+ HAB_INV_CERTIFICATE = 0x21, /* Invalid certificate */
+ HAB_INV_COMMAND = 0x06, /* Invalid command: command malformed */
+ HAB_INV_CSF = 0x11, /* Invalid csf */
+ HAB_INV_DCD = 0x27, /* Invalid dcd */
+ HAB_INV_INDEX = 0x0f, /* Invalid index: access denied */
+ HAB_INV_IVT = 0x05, /* Invalid ivt */
+ HAB_INV_KEY = 0x1d, /* Invalid key */
+ HAB_INV_RETURN = 0x1e, /* Failed callback function */
+ HAB_INV_SIGNATURE = 0x18, /* Invalid signature */
+ HAB_INV_SIZE = 0x17, /* Invalid data size */
+ HAB_MEM_FAIL = 0x2e, /* Memory failure */
+ HAB_OVR_COUNT = 0x2b, /* Expired poll count */
+ HAB_OVR_STORAGE = 0x2d, /* Exhausted storage region */
+ HAB_UNS_ALGORITHM = 0x12, /* Unsupported algorithm */
+ HAB_UNS_COMMAND = 0x03, /* Unsupported command */
+ HAB_UNS_ENGINE = 0x0a, /* Unsupported engine */
+ HAB_UNS_ITEM = 0x24, /* Unsupported configuration item */
+ HAB_UNS_KEY = 0x1b, /* Unsupported key type/parameters */
+ HAB_UNS_PROTOCOL = 0x14, /* Unsupported protocol */
+ HAB_UNS_STATE = 0x09, /* Unsuitable state */
+ HAB_RSN_MAX
+};
+
+enum hab_context {
+ HAB_CTX_ANY = 0x00, /* Match any context */
+ HAB_CTX_FAB = 0xff, /* Event logged in hab_fab_test() */
+ HAB_CTX_ENTRY = 0xe1, /* Event logged in hab_rvt.entry() */
+ HAB_CTX_TARGET = 0x33, /* Event logged in hab_rvt.check_target() */
+ HAB_CTX_AUTHENTICATE = 0x0a,/* Logged in hab_rvt.authenticate_image() */
+ HAB_CTX_DCD = 0xdd, /* Event logged in hab_rvt.run_dcd() */
+ HAB_CTX_CSF = 0xcf, /* Event logged in hab_rvt.run_csf() */
+ HAB_CTX_COMMAND = 0xc0, /* Event logged executing csf/dcd command */
+ HAB_CTX_AUT_DAT = 0xdb, /* Authenticated data block */
+ HAB_CTX_ASSERT = 0xa0, /* Event logged in hab_rvt.assert() */
+ HAB_CTX_EXIT = 0xee, /* Event logged in hab_rvt.exit() */
+ HAB_CTX_MAX
+};
+
+struct imx_sec_config_fuse_t {
+ int bank;
+ int word;
+};
+
+#if defined(CONFIG_SECURE_BOOT)
+extern struct imx_sec_config_fuse_t const imx_sec_config_fuse;
+#endif
+
+/*Function prototype description*/
+typedef enum hab_status hab_rvt_report_event_t(enum hab_status, uint32_t,
+ uint8_t* , size_t*);
+typedef enum hab_status hab_rvt_report_status_t(enum hab_config *,
+ enum hab_state *);
+typedef enum hab_status hab_loader_callback_f_t(void**, size_t*, const void*);
+typedef enum hab_status hab_rvt_entry_t(void);
+typedef enum hab_status hab_rvt_exit_t(void);
+typedef void *hab_rvt_authenticate_image_t(uint8_t, ptrdiff_t,
+ void **, size_t *, hab_loader_callback_f_t);
+typedef void hapi_clock_init_t(void);
+
+#define HAB_ENG_ANY 0x00 /* Select first compatible engine */
+#define HAB_ENG_SCC 0x03 /* Security controller */
+#define HAB_ENG_RTIC 0x05 /* Run-time integrity checker */
+#define HAB_ENG_SAHARA 0x06 /* Crypto accelerator */
+#define HAB_ENG_CSU 0x0a /* Central Security Unit */
+#define HAB_ENG_SRTC 0x0c /* Secure clock */
+#define HAB_ENG_DCP 0x1b /* Data Co-Processor */
+#define HAB_ENG_CAAM 0x1d /* CAAM */
+#define HAB_ENG_SNVS 0x1e /* Secure Non-Volatile Storage */
+#define HAB_ENG_OCOTP 0x21 /* Fuse controller */
+#define HAB_ENG_DTCP 0x22 /* DTCP co-processor */
+#define HAB_ENG_ROM 0x36 /* Protected ROM area */
+#define HAB_ENG_HDCP 0x24 /* HDCP co-processor */
+#define HAB_ENG_RTL 0x77 /* RTL simulation engine */
+#define HAB_ENG_SW 0xff /* Software engine */
+
+#ifdef CONFIG_ROM_UNIFIED_SECTIONS
+#define HAB_RVT_BASE 0x00000100
+#else
+#define HAB_RVT_BASE 0x00000094
+#endif
+
+#define HAB_RVT_ENTRY (*(uint32_t *)(HAB_RVT_BASE + 0x04))
+#define HAB_RVT_EXIT (*(uint32_t *)(HAB_RVT_BASE + 0x08))
+#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)(HAB_RVT_BASE + 0x10))
+#define HAB_RVT_REPORT_EVENT (*(uint32_t *)(HAB_RVT_BASE + 0x20))
+#define HAB_RVT_REPORT_STATUS (*(uint32_t *)(HAB_RVT_BASE + 0x24))
+
+#define HAB_RVT_REPORT_EVENT_NEW (*(uint32_t *)0x000000B8)
+#define HAB_RVT_REPORT_STATUS_NEW (*(uint32_t *)0x000000BC)
+#define HAB_RVT_AUTHENTICATE_IMAGE_NEW (*(uint32_t *)0x000000A8)
+#define HAB_RVT_ENTRY_NEW (*(uint32_t *)0x0000009C)
+#define HAB_RVT_EXIT_NEW (*(uint32_t *)0x000000A0)
+
+#define HAB_CID_ROM 0 /**< ROM Caller ID */
+#define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/
+
+/* ----------- end of HAB API updates ------------*/
+
+uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size);
+
+#endif
--- /dev/null
+/*
+ * i.MX image header offset values
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * NOTE: This file must be kept in sync with tools/imximage.h because
+ * tools/imximage.c can not cross-include headers from arch/arm/
+ * and vice-versa.
+ */
+
+#ifndef __ASM_IMX_COMMON_IMXIMAGE_CFG__
+#define __ASM_IMX_COMMON_IMXIMAGE_CFG__
+
+/* Standard image header offset for NAND, SATA, SD, SPI flash. */
+#define FLASH_OFFSET_STANDARD 0x400
+/* Specific image header offset for booting from OneNAND. */
+#define FLASH_OFFSET_ONENAND 0x100
+/* Specific image header offset for booting from memory-mapped NOR. */
+#define FLASH_OFFSET_NOR 0x1000
+
+#endif /* __ASM_IMX_COMMON_IMXIMAGE_CFG__ */
--- /dev/null
+/*
+ * Based on Linux i.MX iomux-v3.h file:
+ * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
+ * <armlinux@phytec.de>
+ *
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __MACH_IOMUX_V3_H__
+#define __MACH_IOMUX_V3_H__
+
+#include <common.h>
+
+/*
+ * build IOMUX_PAD structure
+ *
+ * This iomux scheme is based around pads, which are the physical balls
+ * on the processor.
+ *
+ * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls
+ * things like driving strength and pullup/pulldown.
+ * - Each pad can have but not necessarily does have an output routing register
+ * (IOMUXC_SW_MUX_CTL_PAD_x).
+ * - Each pad can have but not necessarily does have an input routing register
+ * (IOMUXC_x_SELECT_INPUT)
+ *
+ * The three register sets do not have a fixed offset to each other,
+ * hence we order this table by pad control registers (which all pads
+ * have) and put the optional i/o routing registers into additional
+ * fields.
+ *
+ * The naming convention for the pad modes is SOC_PAD_<padname>__<padmode>
+ * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
+ *
+ * IOMUX/PAD Bit field definitions
+ *
+ * MUX_CTRL_OFS: 0..11 (12)
+ * PAD_CTRL_OFS: 12..23 (12)
+ * SEL_INPUT_OFS: 24..35 (12)
+ * MUX_MODE + SION + LPSR: 36..41 (6)
+ * PAD_CTRL + NO_PAD_CTRL: 42..59 (18)
+ * SEL_INP: 60..63 (4)
+*/
+
+typedef u64 iomux_v3_cfg_t;
+
+#define MUX_CTRL_OFS_SHIFT 0
+#define MUX_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT)
+#define MUX_PAD_CTRL_OFS_SHIFT 12
+#define MUX_PAD_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << \
+ MUX_PAD_CTRL_OFS_SHIFT)
+#define MUX_SEL_INPUT_OFS_SHIFT 24
+#define MUX_SEL_INPUT_OFS_MASK ((iomux_v3_cfg_t)0xfff << \
+ MUX_SEL_INPUT_OFS_SHIFT)
+
+#define MUX_MODE_SHIFT 36
+#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x3f << MUX_MODE_SHIFT)
+#define MUX_PAD_CTRL_SHIFT 42
+#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT)
+#define MUX_SEL_INPUT_SHIFT 60
+#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
+
+#define MUX_MODE_SION ((iomux_v3_cfg_t)IOMUX_CONFIG_SION << \
+ MUX_MODE_SHIFT)
+#define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
+
+#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \
+ sel_input, pad_ctrl) \
+ (((iomux_v3_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \
+ ((iomux_v3_cfg_t)(mux_mode) << MUX_MODE_SHIFT) | \
+ ((iomux_v3_cfg_t)(pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) | \
+ ((iomux_v3_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \
+ ((iomux_v3_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)| \
+ ((iomux_v3_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT))
+
+#define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | \
+ MUX_PAD_CTRL(pad))
+
+#define __NA_ 0x000
+#define NO_MUX_I 0
+#define NO_PAD_I 0
+
+#define NO_PAD_CTRL (1 << 17)
+
+#define IOMUX_CONFIG_LPSR 0x20
+#define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \
+ MUX_MODE_SHIFT)
+#ifdef CONFIG_MX7
+
+#define IOMUX_LPSR_SEL_INPUT_OFS 0x70000
+
+#define PAD_CTL_DSE_1P8V_140OHM (0x0<<0)
+#define PAD_CTL_DSE_1P8V_35OHM (0x1<<0)
+#define PAD_CTL_DSE_1P8V_70OHM (0x2<<0)
+#define PAD_CTL_DSE_1P8V_23OHM (0x3<<0)
+
+#define PAD_CTL_DSE_3P3V_196OHM (0x0<<0)
+#define PAD_CTL_DSE_3P3V_49OHM (0x1<<0)
+#define PAD_CTL_DSE_3P3V_98OHM (0x2<<0)
+#define PAD_CTL_DSE_3P3V_32OHM (0x3<<0)
+
+#define PAD_CTL_SRE_FAST (0 << 2)
+#define PAD_CTL_SRE_SLOW (0x1 << 2)
+
+#define PAD_CTL_HYS (0x1 << 3)
+#define PAD_CTL_PUE (0x1 << 4)
+
+#define PAD_CTL_PUS_PD100KOHM ((0x0 << 5) | PAD_CTL_PUE)
+#define PAD_CTL_PUS_PU5KOHM ((0x1 << 5) | PAD_CTL_PUE)
+#define PAD_CTL_PUS_PU47KOHM ((0x2 << 5) | PAD_CTL_PUE)
+#define PAD_CTL_PUS_PU100KOHM ((0x3 << 5) | PAD_CTL_PUE)
+
+#else
+
+#ifdef CONFIG_MX6
+
+#define PAD_CTL_HYS (1 << 16)
+
+#define PAD_CTL_PUS_100K_DOWN (0 << 14 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_47K_UP (1 << 14 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_100K_UP (2 << 14 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_22K_UP (3 << 14 | PAD_CTL_PUE)
+#define PAD_CTL_PUE (1 << 13 | PAD_CTL_PKE)
+#define PAD_CTL_PKE (1 << 12)
+
+#define PAD_CTL_ODE (1 << 11)
+
+#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)
+#define PAD_CTL_SPEED_LOW (0 << 6)
+#else
+#define PAD_CTL_SPEED_LOW (1 << 6)
+#endif
+#define PAD_CTL_SPEED_MED (2 << 6)
+#define PAD_CTL_SPEED_HIGH (3 << 6)
+
+#define PAD_CTL_DSE_DISABLE (0 << 3)
+#define PAD_CTL_DSE_240ohm (1 << 3)
+#define PAD_CTL_DSE_120ohm (2 << 3)
+#define PAD_CTL_DSE_80ohm (3 << 3)
+#define PAD_CTL_DSE_60ohm (4 << 3)
+#define PAD_CTL_DSE_48ohm (5 << 3)
+#define PAD_CTL_DSE_40ohm (6 << 3)
+#define PAD_CTL_DSE_34ohm (7 << 3)
+
+/* i.MX6SL/SLL */
+#define PAD_CTL_LVE (1 << 1)
+#define PAD_CTL_LVE_BIT (1 << 22)
+
+/* i.MX6SLL */
+#define PAD_CTL_IPD_BIT (1 << 27)
+
+#elif defined(CONFIG_VF610)
+
+#define PAD_MUX_MODE_SHIFT 20
+
+#define PAD_CTL_INPUT_DIFFERENTIAL (1 << 16)
+
+#define PAD_CTL_SPEED_MED (1 << 12)
+#define PAD_CTL_SPEED_HIGH (3 << 12)
+
+#define PAD_CTL_SRE (1 << 11)
+
+#define PAD_CTL_ODE (1 << 10)
+
+#define PAD_CTL_DSE_150ohm (1 << 6)
+#define PAD_CTL_DSE_75ohm (2 << 6)
+#define PAD_CTL_DSE_50ohm (3 << 6)
+#define PAD_CTL_DSE_37ohm (4 << 6)
+#define PAD_CTL_DSE_30ohm (5 << 6)
+#define PAD_CTL_DSE_25ohm (6 << 6)
+#define PAD_CTL_DSE_20ohm (7 << 6)
+
+#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PKE (1 << 3)
+#define PAD_CTL_PUE (1 << 2 | PAD_CTL_PKE)
+
+#define PAD_CTL_OBE_IBE_ENABLE (3 << 0)
+#define PAD_CTL_OBE_ENABLE (1 << 1)
+#define PAD_CTL_IBE_ENABLE (1 << 0)
+
+#else
+
+#define PAD_CTL_DVS (1 << 13)
+#define PAD_CTL_INPUT_DDR (1 << 9)
+#define PAD_CTL_HYS (1 << 8)
+
+#define PAD_CTL_PKE (1 << 7)
+#define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE)
+#define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE)
+
+#define PAD_CTL_ODE (1 << 3)
+
+#define PAD_CTL_DSE_LOW (0 << 1)
+#define PAD_CTL_DSE_MED (1 << 1)
+#define PAD_CTL_DSE_HIGH (2 << 1)
+#define PAD_CTL_DSE_MAX (3 << 1)
+
+#endif
+
+#define PAD_CTL_SRE_SLOW (0 << 0)
+#define PAD_CTL_SRE_FAST (1 << 0)
+
+#endif
+
+#define IOMUX_CONFIG_SION 0x10
+
+#define GPIO_PIN_MASK 0x1f
+#define GPIO_PORT_SHIFT 5
+#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
+#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
+#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
+#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
+#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
+#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
+#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
+
+void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
+void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
+ unsigned count);
+/*
+* Set bits for general purpose registers
+*/
+void imx_iomux_set_gpr_register(int group, int start_bit,
+ int num_bits, int value);
+#ifdef CONFIG_IOMUX_SHARE_CONF_REG
+void imx_iomux_gpio_set_direction(unsigned int gpio,
+ unsigned int direction);
+void imx_iomux_gpio_get_function(unsigned int gpio,
+ u32 *gpio_state);
+#endif
+
+/* macros for declaring and using pinmux array */
+#if defined(CONFIG_MX6QDL)
+#define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x)
+#define SETUP_IOMUX_PAD(def) \
+if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) { \
+ imx_iomux_v3_setup_pad(MX6Q_##def); \
+} else { \
+ imx_iomux_v3_setup_pad(MX6DL_##def); \
+}
+#define SETUP_IOMUX_PADS(x) \
+ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)/2)
+#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
+#define IOMUX_PADS(x) MX6Q_##x
+#define SETUP_IOMUX_PAD(def) \
+ imx_iomux_v3_setup_pad(MX6Q_##def);
+#define SETUP_IOMUX_PADS(x) \
+ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
+#elif defined(CONFIG_MX6UL)
+#define IOMUX_PADS(x) MX6_##x
+#define SETUP_IOMUX_PAD(def) \
+ imx_iomux_v3_setup_pad(MX6_##def);
+#define SETUP_IOMUX_PADS(x) \
+ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
+#else
+#define IOMUX_PADS(x) MX6DL_##x
+#define SETUP_IOMUX_PAD(def) \
+ imx_iomux_v3_setup_pad(MX6DL_##def);
+#define SETUP_IOMUX_PADS(x) \
+ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
+#endif
+
+#endif /* __MACH_IOMUX_V3_H__*/
--- /dev/null
+/*
+ * Copyright (C) 2012
+ * Anatolij Gustschin, DENX Software Engineering, <agust@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __MX5_VIDEO_H
+#define __MX5_VIDEO_H
+
+#ifdef CONFIG_VIDEO
+void lcd_enable(void);
+void setup_iomux_lcd(void);
+#else
+static inline void lcd_enable(void) { }
+static inline void setup_iomux_lcd(void) { }
+#endif
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __ASM_ARCH_MXC_MXC_I2C_H__
+#define __ASM_ARCH_MXC_MXC_I2C_H__
+#include <asm-generic/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+
+struct i2c_pin_ctrl {
+ iomux_v3_cfg_t i2c_mode;
+ iomux_v3_cfg_t gpio_mode;
+ unsigned char gp;
+ unsigned char spare;
+};
+
+struct i2c_pads_info {
+ struct i2c_pin_ctrl scl;
+ struct i2c_pin_ctrl sda;
+};
+
+/*
+ * Information about i2c controller
+ * struct mxc_i2c_bus - information about the i2c[x] bus
+ * @index: i2c bus index
+ * @base: Address of I2C bus controller
+ * @driver_data: Flags for different platforms, such as I2C_QUIRK_FLAG.
+ * @speed: Speed of I2C bus
+ * @pads_info: pinctrl info for this i2c bus, will be used when pinctrl is ok.
+ * The following two is only to be compatible with non-DM part.
+ * @idle_bus_fn: function to force bus idle
+ * @idle_bus_data: parameter for idle_bus_fun
+ * For DM:
+ * bus: The device structure for i2c bus controller
+ * scl-gpio: specify the gpio related to SCL pin
+ * sda-gpio: specify the gpio related to SDA pin
+ */
+struct mxc_i2c_bus {
+ /*
+ * board file can use this index to locate which i2c_pads_info is for
+ * i2c_idle_bus. When pinmux is implement, this entry can be
+ * discarded. Here we do not use dev->seq, because we do not want to
+ * export device to board file.
+ */
+ int index;
+ ulong base;
+ ulong driver_data;
+ int speed;
+ struct i2c_pads_info *pads_info;
+#ifndef CONFIG_DM_I2C
+ int (*idle_bus_fn)(void *p);
+ void *idle_bus_data;
+#else
+ struct udevice *bus;
+ /* Use gpio to force bus idle when bus state is abnormal */
+ struct gpio_desc scl_gpio;
+ struct gpio_desc sda_gpio;
+#endif
+};
+
+#if defined(CONFIG_MX6QDL)
+#define I2C_PADS(name, scl_i2c, scl_gpio, scl_gp, sda_i2c, sda_gpio, sda_gp) \
+ struct i2c_pads_info mx6q_##name = { \
+ .scl = { \
+ .i2c_mode = MX6Q_##scl_i2c, \
+ .gpio_mode = MX6Q_##scl_gpio, \
+ .gp = scl_gp, \
+ }, \
+ .sda = { \
+ .i2c_mode = MX6Q_##sda_i2c, \
+ .gpio_mode = MX6Q_##sda_gpio, \
+ .gp = sda_gp, \
+ } \
+ }; \
+ struct i2c_pads_info mx6s_##name = { \
+ .scl = { \
+ .i2c_mode = MX6DL_##scl_i2c, \
+ .gpio_mode = MX6DL_##scl_gpio, \
+ .gp = scl_gp, \
+ }, \
+ .sda = { \
+ .i2c_mode = MX6DL_##sda_i2c, \
+ .gpio_mode = MX6DL_##sda_gpio, \
+ .gp = sda_gp, \
+ } \
+ };
+
+
+#define I2C_PADS_INFO(name) \
+ (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) ? \
+ &mx6q_##name : &mx6s_##name
+#endif
+
+int setup_i2c(unsigned i2c_index, int speed, int slave_addr,
+ struct i2c_pads_info *p);
+void bus_i2c_init(int index, int speed, int slave_addr,
+ int (*idle_bus_fn)(void *p), void *p);
+int force_idle_bus(void *priv);
+int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus);
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __RDC_SEMA_H__
+#define __RDC_SEMA_H__
+
+/*
+ * rdc_peri_cfg_t and rdc_ma_cft_t use the same layout.
+ *
+ * [ 23 22 | 21 20 | 19 18 | 17 16 ] | [ 15 - 8 ] | [ 7 - 0 ]
+ * d3 d2 d1 d0 | master id | peri id
+ * d[x] means domain[x], x can be [3 - 0].
+ */
+typedef u32 rdc_peri_cfg_t;
+typedef u32 rdc_ma_cfg_t;
+
+#define RDC_PERI_SHIFT 0
+#define RDC_PERI_MASK 0xFF
+
+#define RDC_DOMAIN_SHIFT_BASE 16
+#define RDC_DOMAIN_MASK 0xFF0000
+#define RDC_DOMAIN_SHIFT(x) (RDC_DOMAIN_SHIFT_BASE + ((x << 1)))
+#define RDC_DOMAIN(x) ((rdc_peri_cfg_t)(0x3 << RDC_DOMAIN_SHIFT(x)))
+
+#define RDC_MASTER_SHIFT 8
+#define RDC_MASTER_MASK 0xFF00
+#define RDC_MASTER_CFG(master_id, domain_id) (rdc_ma_cfg_t)((master_id << 8) | \
+ (domain_id << RDC_DOMAIN_SHIFT_BASE))
+
+/* The Following macro definitions are common to i.MX6SX and i.MX7D */
+#define SEMA_GATES_NUM 64
+
+#define RDC_MDA_DID_SHIFT 0
+#define RDC_MDA_DID_MASK (0x3 << RDC_MDA_DID_SHIFT)
+#define RDC_MDA_LCK_SHIFT 31
+#define RDC_MDA_LCK_MASK (0x1 << RDC_MDA_LCK_SHIFT)
+
+#define RDC_PDAP_DW_SHIFT(domain) ((domain) << 1)
+#define RDC_PDAP_DR_SHIFT(domain) (1 + RDC_PDAP_DW_SHIFT(domain))
+#define RDC_PDAP_DW_MASK(domain) (1 << RDC_PDAP_DW_SHIFT(domain))
+#define RDC_PDAP_DR_MASK(domain) (1 << RDC_PDAP_DR_SHIFT(domain))
+#define RDC_PDAP_DRW_MASK(domain) (RDC_PDAP_DW_MASK(domain) | \
+ RDC_PDAP_DR_MASK(domain))
+
+#define RDC_PDAP_SREQ_SHIFT 30
+#define RDC_PDAP_SREQ_MASK (0x1 << RDC_PDAP_SREQ_SHIFT)
+#define RDC_PDAP_LCK_SHIFT 31
+#define RDC_PDAP_LCK_MASK (0x1 << RDC_PDAP_LCK_SHIFT)
+
+#define RDC_MRSA_SADR_SHIFT 7
+#define RDC_MRSA_SADR_MASK (0x1ffffff << RDC_MRSA_SADR_SHIFT)
+
+#define RDC_MREA_EADR_SHIFT 7
+#define RDC_MREA_EADR_MASK (0x1ffffff << RDC_MREA_EADR_SHIFT)
+
+#define RDC_MRC_DW_SHIFT(domain) (domain)
+#define RDC_MRC_DR_SHIFT(domain) (1 + RDC_MRC_DW_SHIFT(domain))
+#define RDC_MRC_DW_MASK(domain) (1 << RDC_MRC_DW_SHIFT(domain))
+#define RDC_MRC_DR_MASK(domain) (1 << RDC_MRC_DR_SHIFT(domain))
+#define RDC_MRC_DRW_MASK(domain) (RDC_MRC_DW_MASK(domain) | \
+ RDC_MRC_DR_MASK(domain))
+#define RDC_MRC_ENA_SHIFT 30
+#define RDC_MRC_ENA_MASK (0x1 << RDC_MRC_ENA_SHIFT)
+#define RDC_MRC_LCK_SHIFT 31
+#define RDC_MRC_LCK_MASK (0x1 << RDC_MRC_LCK_SHIFT)
+
+#define RDC_MRVS_VDID_SHIFT 0
+#define RDC_MRVS_VDID_MASK (0x3 << RDC_MRVS_VDID_SHIFT)
+#define RDC_MRVS_AD_SHIFT 4
+#define RDC_MRVS_AD_MASK (0x1 << RDC_MRVS_AD_SHIFT)
+#define RDC_MRVS_VADDR_SHIFT 5
+#define RDC_MRVS_VADDR_MASK (0x7ffffff << RDC_MRVS_VADDR_SHIFT)
+
+#define RDC_SEMA_GATE_GTFSM_SHIFT 0
+#define RDC_SEMA_GATE_GTFSM_MASK (0xf << RDC_SEMA_GATE_GTFSM_SHIFT)
+#define RDC_SEMA_GATE_LDOM_SHIFT 5
+#define RDC_SEMA_GATE_LDOM_MASK (0x3 << RDC_SEMA_GATE_LDOM_SHIFT)
+
+#define RDC_SEMA_RSTGT_RSTGDP_SHIFT 0
+#define RDC_SEMA_RSTGT_RSTGDP_MASK (0xff << RDC_SEMA_RSTGT_RSTGDP_SHIFT)
+#define RDC_SEMA_RSTGT_RSTGSM_SHIFT 2
+#define RDC_SEMA_RSTGT_RSTGSM_MASK (0x3 << RDC_SEMA_RSTGT_RSTGSM_SHIFT)
+#define RDC_SEMA_RSTGT_RSTGMS_SHIFT 4
+#define RDC_SEMA_RSTGT_RSTGMS_MASK (0xf << RDC_SEMA_RSTGT_RSTGMS_SHIFT)
+#define RDC_SEMA_RSTGT_RSTGTN_SHIFT 8
+#define RDC_SEMA_RSTGT_RSTGTN_MASK (0xff << RDC_SEMA_RSTGT_RSTGTN_SHIFT)
+
+int imx_rdc_check_permission(int per_id, int dom_id);
+int imx_rdc_sema_lock(int per_id);
+int imx_rdc_sema_unlock(int per_id);
+int imx_rdc_setup_peri(rdc_peri_cfg_t p);
+int imx_rdc_setup_peripherals(rdc_peri_cfg_t const *peripherals_list,
+ unsigned count);
+int imx_rdc_setup_ma(rdc_ma_cfg_t p);
+int imx_rdc_setup_masters(rdc_ma_cfg_t const *masters_list, unsigned count);
+
+#endif /* __RDC_SEMA_H__*/
--- /dev/null
+/*
+ * Freescale i.MX28 APBH Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __REGS_APBH_H__
+#define __REGS_APBH_H__
+
+#include <asm/mach-imx/regs-common.h>
+
+#ifndef __ASSEMBLY__
+
+#if defined(CONFIG_MX23)
+struct mxs_apbh_regs {
+ mxs_reg_32(hw_apbh_ctrl0)
+ mxs_reg_32(hw_apbh_ctrl1)
+ mxs_reg_32(hw_apbh_ctrl2)
+ mxs_reg_32(hw_apbh_channel_ctrl)
+
+ union {
+ struct {
+ mxs_reg_32(hw_apbh_ch_curcmdar)
+ mxs_reg_32(hw_apbh_ch_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch_cmd)
+ mxs_reg_32(hw_apbh_ch_bar)
+ mxs_reg_32(hw_apbh_ch_sema)
+ mxs_reg_32(hw_apbh_ch_debug1)
+ mxs_reg_32(hw_apbh_ch_debug2)
+ } ch[8];
+ struct {
+ mxs_reg_32(hw_apbh_ch0_curcmdar)
+ mxs_reg_32(hw_apbh_ch0_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch0_cmd)
+ mxs_reg_32(hw_apbh_ch0_bar)
+ mxs_reg_32(hw_apbh_ch0_sema)
+ mxs_reg_32(hw_apbh_ch0_debug1)
+ mxs_reg_32(hw_apbh_ch0_debug2)
+ mxs_reg_32(hw_apbh_ch1_curcmdar)
+ mxs_reg_32(hw_apbh_ch1_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch1_cmd)
+ mxs_reg_32(hw_apbh_ch1_bar)
+ mxs_reg_32(hw_apbh_ch1_sema)
+ mxs_reg_32(hw_apbh_ch1_debug1)
+ mxs_reg_32(hw_apbh_ch1_debug2)
+ mxs_reg_32(hw_apbh_ch2_curcmdar)
+ mxs_reg_32(hw_apbh_ch2_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch2_cmd)
+ mxs_reg_32(hw_apbh_ch2_bar)
+ mxs_reg_32(hw_apbh_ch2_sema)
+ mxs_reg_32(hw_apbh_ch2_debug1)
+ mxs_reg_32(hw_apbh_ch2_debug2)
+ mxs_reg_32(hw_apbh_ch3_curcmdar)
+ mxs_reg_32(hw_apbh_ch3_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch3_cmd)
+ mxs_reg_32(hw_apbh_ch3_bar)
+ mxs_reg_32(hw_apbh_ch3_sema)
+ mxs_reg_32(hw_apbh_ch3_debug1)
+ mxs_reg_32(hw_apbh_ch3_debug2)
+ mxs_reg_32(hw_apbh_ch4_curcmdar)
+ mxs_reg_32(hw_apbh_ch4_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch4_cmd)
+ mxs_reg_32(hw_apbh_ch4_bar)
+ mxs_reg_32(hw_apbh_ch4_sema)
+ mxs_reg_32(hw_apbh_ch4_debug1)
+ mxs_reg_32(hw_apbh_ch4_debug2)
+ mxs_reg_32(hw_apbh_ch5_curcmdar)
+ mxs_reg_32(hw_apbh_ch5_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch5_cmd)
+ mxs_reg_32(hw_apbh_ch5_bar)
+ mxs_reg_32(hw_apbh_ch5_sema)
+ mxs_reg_32(hw_apbh_ch5_debug1)
+ mxs_reg_32(hw_apbh_ch5_debug2)
+ mxs_reg_32(hw_apbh_ch6_curcmdar)
+ mxs_reg_32(hw_apbh_ch6_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch6_cmd)
+ mxs_reg_32(hw_apbh_ch6_bar)
+ mxs_reg_32(hw_apbh_ch6_sema)
+ mxs_reg_32(hw_apbh_ch6_debug1)
+ mxs_reg_32(hw_apbh_ch6_debug2)
+ mxs_reg_32(hw_apbh_ch7_curcmdar)
+ mxs_reg_32(hw_apbh_ch7_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch7_cmd)
+ mxs_reg_32(hw_apbh_ch7_bar)
+ mxs_reg_32(hw_apbh_ch7_sema)
+ mxs_reg_32(hw_apbh_ch7_debug1)
+ mxs_reg_32(hw_apbh_ch7_debug2)
+ };
+ };
+ mxs_reg_32(hw_apbh_version)
+};
+
+#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7))
+struct mxs_apbh_regs {
+ mxs_reg_32(hw_apbh_ctrl0)
+ mxs_reg_32(hw_apbh_ctrl1)
+ mxs_reg_32(hw_apbh_ctrl2)
+ mxs_reg_32(hw_apbh_channel_ctrl)
+ mxs_reg_32(hw_apbh_devsel)
+ mxs_reg_32(hw_apbh_dma_burst_size)
+ mxs_reg_32(hw_apbh_debug)
+
+ uint32_t reserved[36];
+
+ union {
+ struct {
+ mxs_reg_32(hw_apbh_ch_curcmdar)
+ mxs_reg_32(hw_apbh_ch_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch_cmd)
+ mxs_reg_32(hw_apbh_ch_bar)
+ mxs_reg_32(hw_apbh_ch_sema)
+ mxs_reg_32(hw_apbh_ch_debug1)
+ mxs_reg_32(hw_apbh_ch_debug2)
+ } ch[16];
+ struct {
+ mxs_reg_32(hw_apbh_ch0_curcmdar)
+ mxs_reg_32(hw_apbh_ch0_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch0_cmd)
+ mxs_reg_32(hw_apbh_ch0_bar)
+ mxs_reg_32(hw_apbh_ch0_sema)
+ mxs_reg_32(hw_apbh_ch0_debug1)
+ mxs_reg_32(hw_apbh_ch0_debug2)
+ mxs_reg_32(hw_apbh_ch1_curcmdar)
+ mxs_reg_32(hw_apbh_ch1_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch1_cmd)
+ mxs_reg_32(hw_apbh_ch1_bar)
+ mxs_reg_32(hw_apbh_ch1_sema)
+ mxs_reg_32(hw_apbh_ch1_debug1)
+ mxs_reg_32(hw_apbh_ch1_debug2)
+ mxs_reg_32(hw_apbh_ch2_curcmdar)
+ mxs_reg_32(hw_apbh_ch2_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch2_cmd)
+ mxs_reg_32(hw_apbh_ch2_bar)
+ mxs_reg_32(hw_apbh_ch2_sema)
+ mxs_reg_32(hw_apbh_ch2_debug1)
+ mxs_reg_32(hw_apbh_ch2_debug2)
+ mxs_reg_32(hw_apbh_ch3_curcmdar)
+ mxs_reg_32(hw_apbh_ch3_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch3_cmd)
+ mxs_reg_32(hw_apbh_ch3_bar)
+ mxs_reg_32(hw_apbh_ch3_sema)
+ mxs_reg_32(hw_apbh_ch3_debug1)
+ mxs_reg_32(hw_apbh_ch3_debug2)
+ mxs_reg_32(hw_apbh_ch4_curcmdar)
+ mxs_reg_32(hw_apbh_ch4_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch4_cmd)
+ mxs_reg_32(hw_apbh_ch4_bar)
+ mxs_reg_32(hw_apbh_ch4_sema)
+ mxs_reg_32(hw_apbh_ch4_debug1)
+ mxs_reg_32(hw_apbh_ch4_debug2)
+ mxs_reg_32(hw_apbh_ch5_curcmdar)
+ mxs_reg_32(hw_apbh_ch5_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch5_cmd)
+ mxs_reg_32(hw_apbh_ch5_bar)
+ mxs_reg_32(hw_apbh_ch5_sema)
+ mxs_reg_32(hw_apbh_ch5_debug1)
+ mxs_reg_32(hw_apbh_ch5_debug2)
+ mxs_reg_32(hw_apbh_ch6_curcmdar)
+ mxs_reg_32(hw_apbh_ch6_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch6_cmd)
+ mxs_reg_32(hw_apbh_ch6_bar)
+ mxs_reg_32(hw_apbh_ch6_sema)
+ mxs_reg_32(hw_apbh_ch6_debug1)
+ mxs_reg_32(hw_apbh_ch6_debug2)
+ mxs_reg_32(hw_apbh_ch7_curcmdar)
+ mxs_reg_32(hw_apbh_ch7_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch7_cmd)
+ mxs_reg_32(hw_apbh_ch7_bar)
+ mxs_reg_32(hw_apbh_ch7_sema)
+ mxs_reg_32(hw_apbh_ch7_debug1)
+ mxs_reg_32(hw_apbh_ch7_debug2)
+ mxs_reg_32(hw_apbh_ch8_curcmdar)
+ mxs_reg_32(hw_apbh_ch8_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch8_cmd)
+ mxs_reg_32(hw_apbh_ch8_bar)
+ mxs_reg_32(hw_apbh_ch8_sema)
+ mxs_reg_32(hw_apbh_ch8_debug1)
+ mxs_reg_32(hw_apbh_ch8_debug2)
+ mxs_reg_32(hw_apbh_ch9_curcmdar)
+ mxs_reg_32(hw_apbh_ch9_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch9_cmd)
+ mxs_reg_32(hw_apbh_ch9_bar)
+ mxs_reg_32(hw_apbh_ch9_sema)
+ mxs_reg_32(hw_apbh_ch9_debug1)
+ mxs_reg_32(hw_apbh_ch9_debug2)
+ mxs_reg_32(hw_apbh_ch10_curcmdar)
+ mxs_reg_32(hw_apbh_ch10_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch10_cmd)
+ mxs_reg_32(hw_apbh_ch10_bar)
+ mxs_reg_32(hw_apbh_ch10_sema)
+ mxs_reg_32(hw_apbh_ch10_debug1)
+ mxs_reg_32(hw_apbh_ch10_debug2)
+ mxs_reg_32(hw_apbh_ch11_curcmdar)
+ mxs_reg_32(hw_apbh_ch11_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch11_cmd)
+ mxs_reg_32(hw_apbh_ch11_bar)
+ mxs_reg_32(hw_apbh_ch11_sema)
+ mxs_reg_32(hw_apbh_ch11_debug1)
+ mxs_reg_32(hw_apbh_ch11_debug2)
+ mxs_reg_32(hw_apbh_ch12_curcmdar)
+ mxs_reg_32(hw_apbh_ch12_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch12_cmd)
+ mxs_reg_32(hw_apbh_ch12_bar)
+ mxs_reg_32(hw_apbh_ch12_sema)
+ mxs_reg_32(hw_apbh_ch12_debug1)
+ mxs_reg_32(hw_apbh_ch12_debug2)
+ mxs_reg_32(hw_apbh_ch13_curcmdar)
+ mxs_reg_32(hw_apbh_ch13_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch13_cmd)
+ mxs_reg_32(hw_apbh_ch13_bar)
+ mxs_reg_32(hw_apbh_ch13_sema)
+ mxs_reg_32(hw_apbh_ch13_debug1)
+ mxs_reg_32(hw_apbh_ch13_debug2)
+ mxs_reg_32(hw_apbh_ch14_curcmdar)
+ mxs_reg_32(hw_apbh_ch14_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch14_cmd)
+ mxs_reg_32(hw_apbh_ch14_bar)
+ mxs_reg_32(hw_apbh_ch14_sema)
+ mxs_reg_32(hw_apbh_ch14_debug1)
+ mxs_reg_32(hw_apbh_ch14_debug2)
+ mxs_reg_32(hw_apbh_ch15_curcmdar)
+ mxs_reg_32(hw_apbh_ch15_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch15_cmd)
+ mxs_reg_32(hw_apbh_ch15_bar)
+ mxs_reg_32(hw_apbh_ch15_sema)
+ mxs_reg_32(hw_apbh_ch15_debug1)
+ mxs_reg_32(hw_apbh_ch15_debug2)
+ };
+ };
+ mxs_reg_32(hw_apbh_version)
+};
+#endif
+
+#endif
+
+#define APBH_CTRL0_SFTRST (1 << 31)
+#define APBH_CTRL0_CLKGATE (1 << 30)
+#define APBH_CTRL0_AHB_BURST8_EN (1 << 29)
+#define APBH_CTRL0_APB_BURST_EN (1 << 28)
+#if defined(CONFIG_MX23)
+#define APBH_CTRL0_RSVD0_MASK (0xf << 24)
+#define APBH_CTRL0_RSVD0_OFFSET 24
+#define APBH_CTRL0_RESET_CHANNEL_MASK (0xff << 16)
+#define APBH_CTRL0_RESET_CHANNEL_OFFSET 16
+#define APBH_CTRL0_CLKGATE_CHANNEL_MASK (0xff << 8)
+#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 8
+#define APBH_CTRL0_CLKGATE_CHANNEL_SSP0 0x02
+#define APBH_CTRL0_CLKGATE_CHANNEL_SSP1 0x04
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x10
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x20
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x40
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x80
+#elif defined(CONFIG_MX28)
+#define APBH_CTRL0_RSVD0_MASK (0xfff << 16)
+#define APBH_CTRL0_RSVD0_OFFSET 16
+#define APBH_CTRL0_CLKGATE_CHANNEL_MASK 0xffff
+#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0
+#define APBH_CTRL0_CLKGATE_CHANNEL_SSP0 0x0001
+#define APBH_CTRL0_CLKGATE_CHANNEL_SSP1 0x0002
+#define APBH_CTRL0_CLKGATE_CHANNEL_SSP2 0x0004
+#define APBH_CTRL0_CLKGATE_CHANNEL_SSP3 0x0008
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0010
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0020
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x0040
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x0080
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND4 0x0100
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND5 0x0200
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND6 0x0400
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800
+#define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000
+#define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000
+#elif (defined(CONFIG_MX6) || defined(CONFIG_MX7))
+#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0001
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0002
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x0004
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x0008
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND4 0x0010
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND5 0x0020
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND6 0x0040
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0080
+#define APBH_CTRL0_CLKGATE_CHANNEL_SSP 0x0100
+#endif
+
+#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN (1 << 31)
+#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN (1 << 30)
+#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN (1 << 29)
+#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN (1 << 28)
+#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN (1 << 27)
+#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN (1 << 26)
+#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN (1 << 25)
+#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN (1 << 24)
+#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN (1 << 23)
+#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN (1 << 22)
+#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN (1 << 21)
+#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN (1 << 20)
+#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN (1 << 19)
+#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN (1 << 18)
+#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN (1 << 17)
+#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN (1 << 16)
+#define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET 16
+#define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_MASK (0xffff << 16)
+#define APBH_CTRL1_CH15_CMDCMPLT_IRQ (1 << 15)
+#define APBH_CTRL1_CH14_CMDCMPLT_IRQ (1 << 14)
+#define APBH_CTRL1_CH13_CMDCMPLT_IRQ (1 << 13)
+#define APBH_CTRL1_CH12_CMDCMPLT_IRQ (1 << 12)
+#define APBH_CTRL1_CH11_CMDCMPLT_IRQ (1 << 11)
+#define APBH_CTRL1_CH10_CMDCMPLT_IRQ (1 << 10)
+#define APBH_CTRL1_CH9_CMDCMPLT_IRQ (1 << 9)
+#define APBH_CTRL1_CH8_CMDCMPLT_IRQ (1 << 8)
+#define APBH_CTRL1_CH7_CMDCMPLT_IRQ (1 << 7)
+#define APBH_CTRL1_CH6_CMDCMPLT_IRQ (1 << 6)
+#define APBH_CTRL1_CH5_CMDCMPLT_IRQ (1 << 5)
+#define APBH_CTRL1_CH4_CMDCMPLT_IRQ (1 << 4)
+#define APBH_CTRL1_CH3_CMDCMPLT_IRQ (1 << 3)
+#define APBH_CTRL1_CH2_CMDCMPLT_IRQ (1 << 2)
+#define APBH_CTRL1_CH1_CMDCMPLT_IRQ (1 << 1)
+#define APBH_CTRL1_CH0_CMDCMPLT_IRQ (1 << 0)
+
+#define APBH_CTRL2_CH15_ERROR_STATUS (1 << 31)
+#define APBH_CTRL2_CH14_ERROR_STATUS (1 << 30)
+#define APBH_CTRL2_CH13_ERROR_STATUS (1 << 29)
+#define APBH_CTRL2_CH12_ERROR_STATUS (1 << 28)
+#define APBH_CTRL2_CH11_ERROR_STATUS (1 << 27)
+#define APBH_CTRL2_CH10_ERROR_STATUS (1 << 26)
+#define APBH_CTRL2_CH9_ERROR_STATUS (1 << 25)
+#define APBH_CTRL2_CH8_ERROR_STATUS (1 << 24)
+#define APBH_CTRL2_CH7_ERROR_STATUS (1 << 23)
+#define APBH_CTRL2_CH6_ERROR_STATUS (1 << 22)
+#define APBH_CTRL2_CH5_ERROR_STATUS (1 << 21)
+#define APBH_CTRL2_CH4_ERROR_STATUS (1 << 20)
+#define APBH_CTRL2_CH3_ERROR_STATUS (1 << 19)
+#define APBH_CTRL2_CH2_ERROR_STATUS (1 << 18)
+#define APBH_CTRL2_CH1_ERROR_STATUS (1 << 17)
+#define APBH_CTRL2_CH0_ERROR_STATUS (1 << 16)
+#define APBH_CTRL2_CH15_ERROR_IRQ (1 << 15)
+#define APBH_CTRL2_CH14_ERROR_IRQ (1 << 14)
+#define APBH_CTRL2_CH13_ERROR_IRQ (1 << 13)
+#define APBH_CTRL2_CH12_ERROR_IRQ (1 << 12)
+#define APBH_CTRL2_CH11_ERROR_IRQ (1 << 11)
+#define APBH_CTRL2_CH10_ERROR_IRQ (1 << 10)
+#define APBH_CTRL2_CH9_ERROR_IRQ (1 << 9)
+#define APBH_CTRL2_CH8_ERROR_IRQ (1 << 8)
+#define APBH_CTRL2_CH7_ERROR_IRQ (1 << 7)
+#define APBH_CTRL2_CH6_ERROR_IRQ (1 << 6)
+#define APBH_CTRL2_CH5_ERROR_IRQ (1 << 5)
+#define APBH_CTRL2_CH4_ERROR_IRQ (1 << 4)
+#define APBH_CTRL2_CH3_ERROR_IRQ (1 << 3)
+#define APBH_CTRL2_CH2_ERROR_IRQ (1 << 2)
+#define APBH_CTRL2_CH1_ERROR_IRQ (1 << 1)
+#define APBH_CTRL2_CH0_ERROR_IRQ (1 << 0)
+
+#if defined(CONFIG_MX28)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xffff << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP0 (0x0001 << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP1 (0x0002 << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP2 (0x0004 << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP3 (0x0008 << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND0 (0x0010 << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND1 (0x0020 << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND2 (0x0040 << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND3 (0x0080 << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND4 (0x0100 << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND5 (0x0200 << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND6 (0x0400 << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND7 (0x0800 << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_HSADC (0x1000 << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_LCDIF (0x2000 << 16)
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK 0xffff
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_OFFSET 0
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP0 0x0001
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP1 0x0002
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP2 0x0004
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP3 0x0008
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND0 0x0010
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND1 0x0020
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND2 0x0040
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND3 0x0080
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND4 0x0100
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND5 0x0200
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND6 0x0400
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND7 0x0800
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_HSADC 0x1000
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000
+#endif
+
+#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16
+#endif
+
+#if defined(CONFIG_MX23)
+#define APBH_DEVSEL_CH7_MASK (0xf << 28)
+#define APBH_DEVSEL_CH7_OFFSET 28
+#define APBH_DEVSEL_CH6_MASK (0xf << 24)
+#define APBH_DEVSEL_CH6_OFFSET 24
+#define APBH_DEVSEL_CH5_MASK (0xf << 20)
+#define APBH_DEVSEL_CH5_OFFSET 20
+#define APBH_DEVSEL_CH4_MASK (0xf << 16)
+#define APBH_DEVSEL_CH4_OFFSET 16
+#define APBH_DEVSEL_CH3_MASK (0xf << 12)
+#define APBH_DEVSEL_CH3_OFFSET 12
+#define APBH_DEVSEL_CH2_MASK (0xf << 8)
+#define APBH_DEVSEL_CH2_OFFSET 8
+#define APBH_DEVSEL_CH1_MASK (0xf << 4)
+#define APBH_DEVSEL_CH1_OFFSET 4
+#define APBH_DEVSEL_CH0_MASK (0xf << 0)
+#define APBH_DEVSEL_CH0_OFFSET 0
+#elif defined(CONFIG_MX28)
+#define APBH_DEVSEL_CH15_MASK (0x3 << 30)
+#define APBH_DEVSEL_CH15_OFFSET 30
+#define APBH_DEVSEL_CH14_MASK (0x3 << 28)
+#define APBH_DEVSEL_CH14_OFFSET 28
+#define APBH_DEVSEL_CH13_MASK (0x3 << 26)
+#define APBH_DEVSEL_CH13_OFFSET 26
+#define APBH_DEVSEL_CH12_MASK (0x3 << 24)
+#define APBH_DEVSEL_CH12_OFFSET 24
+#define APBH_DEVSEL_CH11_MASK (0x3 << 22)
+#define APBH_DEVSEL_CH11_OFFSET 22
+#define APBH_DEVSEL_CH10_MASK (0x3 << 20)
+#define APBH_DEVSEL_CH10_OFFSET 20
+#define APBH_DEVSEL_CH9_MASK (0x3 << 18)
+#define APBH_DEVSEL_CH9_OFFSET 18
+#define APBH_DEVSEL_CH8_MASK (0x3 << 16)
+#define APBH_DEVSEL_CH8_OFFSET 16
+#define APBH_DEVSEL_CH7_MASK (0x3 << 14)
+#define APBH_DEVSEL_CH7_OFFSET 14
+#define APBH_DEVSEL_CH6_MASK (0x3 << 12)
+#define APBH_DEVSEL_CH6_OFFSET 12
+#define APBH_DEVSEL_CH5_MASK (0x3 << 10)
+#define APBH_DEVSEL_CH5_OFFSET 10
+#define APBH_DEVSEL_CH4_MASK (0x3 << 8)
+#define APBH_DEVSEL_CH4_OFFSET 8
+#define APBH_DEVSEL_CH3_MASK (0x3 << 6)
+#define APBH_DEVSEL_CH3_OFFSET 6
+#define APBH_DEVSEL_CH2_MASK (0x3 << 4)
+#define APBH_DEVSEL_CH2_OFFSET 4
+#define APBH_DEVSEL_CH1_MASK (0x3 << 2)
+#define APBH_DEVSEL_CH1_OFFSET 2
+#define APBH_DEVSEL_CH0_MASK (0x3 << 0)
+#define APBH_DEVSEL_CH0_OFFSET 0
+#endif
+
+#if defined(CONFIG_MX28)
+#define APBH_DMA_BURST_SIZE_CH15_MASK (0x3 << 30)
+#define APBH_DMA_BURST_SIZE_CH15_OFFSET 30
+#define APBH_DMA_BURST_SIZE_CH14_MASK (0x3 << 28)
+#define APBH_DMA_BURST_SIZE_CH14_OFFSET 28
+#define APBH_DMA_BURST_SIZE_CH13_MASK (0x3 << 26)
+#define APBH_DMA_BURST_SIZE_CH13_OFFSET 26
+#define APBH_DMA_BURST_SIZE_CH12_MASK (0x3 << 24)
+#define APBH_DMA_BURST_SIZE_CH12_OFFSET 24
+#define APBH_DMA_BURST_SIZE_CH11_MASK (0x3 << 22)
+#define APBH_DMA_BURST_SIZE_CH11_OFFSET 22
+#define APBH_DMA_BURST_SIZE_CH10_MASK (0x3 << 20)
+#define APBH_DMA_BURST_SIZE_CH10_OFFSET 20
+#define APBH_DMA_BURST_SIZE_CH9_MASK (0x3 << 18)
+#define APBH_DMA_BURST_SIZE_CH9_OFFSET 18
+#define APBH_DMA_BURST_SIZE_CH8_MASK (0x3 << 16)
+#define APBH_DMA_BURST_SIZE_CH8_OFFSET 16
+#define APBH_DMA_BURST_SIZE_CH8_BURST0 (0x0 << 16)
+#define APBH_DMA_BURST_SIZE_CH8_BURST4 (0x1 << 16)
+#define APBH_DMA_BURST_SIZE_CH8_BURST8 (0x2 << 16)
+#define APBH_DMA_BURST_SIZE_CH7_MASK (0x3 << 14)
+#define APBH_DMA_BURST_SIZE_CH7_OFFSET 14
+#define APBH_DMA_BURST_SIZE_CH6_MASK (0x3 << 12)
+#define APBH_DMA_BURST_SIZE_CH6_OFFSET 12
+#define APBH_DMA_BURST_SIZE_CH5_MASK (0x3 << 10)
+#define APBH_DMA_BURST_SIZE_CH5_OFFSET 10
+#define APBH_DMA_BURST_SIZE_CH4_MASK (0x3 << 8)
+#define APBH_DMA_BURST_SIZE_CH4_OFFSET 8
+#define APBH_DMA_BURST_SIZE_CH3_MASK (0x3 << 6)
+#define APBH_DMA_BURST_SIZE_CH3_OFFSET 6
+#define APBH_DMA_BURST_SIZE_CH3_BURST0 (0x0 << 6)
+#define APBH_DMA_BURST_SIZE_CH3_BURST4 (0x1 << 6)
+#define APBH_DMA_BURST_SIZE_CH3_BURST8 (0x2 << 6)
+
+#define APBH_DMA_BURST_SIZE_CH2_MASK (0x3 << 4)
+#define APBH_DMA_BURST_SIZE_CH2_OFFSET 4
+#define APBH_DMA_BURST_SIZE_CH2_BURST0 (0x0 << 4)
+#define APBH_DMA_BURST_SIZE_CH2_BURST4 (0x1 << 4)
+#define APBH_DMA_BURST_SIZE_CH2_BURST8 (0x2 << 4)
+#define APBH_DMA_BURST_SIZE_CH1_MASK (0x3 << 2)
+#define APBH_DMA_BURST_SIZE_CH1_OFFSET 2
+#define APBH_DMA_BURST_SIZE_CH1_BURST0 (0x0 << 2)
+#define APBH_DMA_BURST_SIZE_CH1_BURST4 (0x1 << 2)
+#define APBH_DMA_BURST_SIZE_CH1_BURST8 (0x2 << 2)
+
+#define APBH_DMA_BURST_SIZE_CH0_MASK 0x3
+#define APBH_DMA_BURST_SIZE_CH0_OFFSET 0
+#define APBH_DMA_BURST_SIZE_CH0_BURST0 0x0
+#define APBH_DMA_BURST_SIZE_CH0_BURST4 0x1
+#define APBH_DMA_BURST_SIZE_CH0_BURST8 0x2
+
+#define APBH_DEBUG_GPMI_ONE_FIFO (1 << 0)
+#endif
+
+#define APBH_CHn_CURCMDAR_CMD_ADDR_MASK 0xffffffff
+#define APBH_CHn_CURCMDAR_CMD_ADDR_OFFSET 0
+
+#define APBH_CHn_NXTCMDAR_CMD_ADDR_MASK 0xffffffff
+#define APBH_CHn_NXTCMDAR_CMD_ADDR_OFFSET 0
+
+#define APBH_CHn_CMD_XFER_COUNT_MASK (0xffff << 16)
+#define APBH_CHn_CMD_XFER_COUNT_OFFSET 16
+#define APBH_CHn_CMD_CMDWORDS_MASK (0xf << 12)
+#define APBH_CHn_CMD_CMDWORDS_OFFSET 12
+#define APBH_CHn_CMD_HALTONTERMINATE (1 << 8)
+#define APBH_CHn_CMD_WAIT4ENDCMD (1 << 7)
+#define APBH_CHn_CMD_SEMAPHORE (1 << 6)
+#define APBH_CHn_CMD_NANDWAIT4READY (1 << 5)
+#define APBH_CHn_CMD_NANDLOCK (1 << 4)
+#define APBH_CHn_CMD_IRQONCMPLT (1 << 3)
+#define APBH_CHn_CMD_CHAIN (1 << 2)
+#define APBH_CHn_CMD_COMMAND_MASK 0x3
+#define APBH_CHn_CMD_COMMAND_OFFSET 0
+#define APBH_CHn_CMD_COMMAND_NO_DMA_XFER 0x0
+#define APBH_CHn_CMD_COMMAND_DMA_WRITE 0x1
+#define APBH_CHn_CMD_COMMAND_DMA_READ 0x2
+#define APBH_CHn_CMD_COMMAND_DMA_SENSE 0x3
+
+#define APBH_CHn_BAR_ADDRESS_MASK 0xffffffff
+#define APBH_CHn_BAR_ADDRESS_OFFSET 0
+
+#define APBH_CHn_SEMA_RSVD2_MASK (0xff << 24)
+#define APBH_CHn_SEMA_RSVD2_OFFSET 24
+#define APBH_CHn_SEMA_PHORE_MASK (0xff << 16)
+#define APBH_CHn_SEMA_PHORE_OFFSET 16
+#define APBH_CHn_SEMA_RSVD1_MASK (0xff << 8)
+#define APBH_CHn_SEMA_RSVD1_OFFSET 8
+#define APBH_CHn_SEMA_INCREMENT_SEMA_MASK (0xff << 0)
+#define APBH_CHn_SEMA_INCREMENT_SEMA_OFFSET 0
+
+#define APBH_CHn_DEBUG1_REQ (1 << 31)
+#define APBH_CHn_DEBUG1_BURST (1 << 30)
+#define APBH_CHn_DEBUG1_KICK (1 << 29)
+#define APBH_CHn_DEBUG1_END (1 << 28)
+#define APBH_CHn_DEBUG1_SENSE (1 << 27)
+#define APBH_CHn_DEBUG1_READY (1 << 26)
+#define APBH_CHn_DEBUG1_LOCK (1 << 25)
+#define APBH_CHn_DEBUG1_NEXTCMDADDRVALID (1 << 24)
+#define APBH_CHn_DEBUG1_RD_FIFO_EMPTY (1 << 23)
+#define APBH_CHn_DEBUG1_RD_FIFO_FULL (1 << 22)
+#define APBH_CHn_DEBUG1_WR_FIFO_EMPTY (1 << 21)
+#define APBH_CHn_DEBUG1_WR_FIFO_FULL (1 << 20)
+#define APBH_CHn_DEBUG1_RSVD1_MASK (0x7fff << 5)
+#define APBH_CHn_DEBUG1_RSVD1_OFFSET 5
+#define APBH_CHn_DEBUG1_STATEMACHINE_MASK 0x1f
+#define APBH_CHn_DEBUG1_STATEMACHINE_OFFSET 0
+#define APBH_CHn_DEBUG1_STATEMACHINE_IDLE 0x00
+#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD1 0x01
+#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD3 0x02
+#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD2 0x03
+#define APBH_CHn_DEBUG1_STATEMACHINE_XFER_DECODE 0x04
+#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_WAIT 0x05
+#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD4 0x06
+#define APBH_CHn_DEBUG1_STATEMACHINE_PIO_REQ 0x07
+#define APBH_CHn_DEBUG1_STATEMACHINE_READ_FLUSH 0x08
+#define APBH_CHn_DEBUG1_STATEMACHINE_READ_WAIT 0x09
+#define APBH_CHn_DEBUG1_STATEMACHINE_WRITE 0x0c
+#define APBH_CHn_DEBUG1_STATEMACHINE_READ_REQ 0x0d
+#define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_CHAIN 0x0e
+#define APBH_CHn_DEBUG1_STATEMACHINE_XFER_COMPLETE 0x0f
+#define APBH_CHn_DEBUG1_STATEMACHINE_TERMINATE 0x14
+#define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_END 0x15
+#define APBH_CHn_DEBUG1_STATEMACHINE_WRITE_WAIT 0x1c
+#define APBH_CHn_DEBUG1_STATEMACHINE_HALT_AFTER_TERM 0x1d
+#define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_WAIT 0x1e
+#define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_READY 0x1f
+
+#define APBH_CHn_DEBUG2_APB_BYTES_MASK (0xffff << 16)
+#define APBH_CHn_DEBUG2_APB_BYTES_OFFSET 16
+#define APBH_CHn_DEBUG2_AHB_BYTES_MASK 0xffff
+#define APBH_CHn_DEBUG2_AHB_BYTES_OFFSET 0
+
+#define APBH_VERSION_MAJOR_MASK (0xff << 24)
+#define APBH_VERSION_MAJOR_OFFSET 24
+#define APBH_VERSION_MINOR_MASK (0xff << 16)
+#define APBH_VERSION_MINOR_OFFSET 16
+#define APBH_VERSION_STEP_MASK 0xffff
+#define APBH_VERSION_STEP_OFFSET 0
+
+#endif /* __REGS_APBH_H__ */
--- /dev/null
+/*
+ * Freescale i.MX28 BCH Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __MX28_REGS_BCH_H__
+#define __MX28_REGS_BCH_H__
+
+#include <asm/mach-imx/regs-common.h>
+
+#ifndef __ASSEMBLY__
+struct mxs_bch_regs {
+ mxs_reg_32(hw_bch_ctrl)
+ mxs_reg_32(hw_bch_status0)
+ mxs_reg_32(hw_bch_mode)
+ mxs_reg_32(hw_bch_encodeptr)
+ mxs_reg_32(hw_bch_dataptr)
+ mxs_reg_32(hw_bch_metaptr)
+
+ uint32_t reserved[4];
+
+ mxs_reg_32(hw_bch_layoutselect)
+ mxs_reg_32(hw_bch_flash0layout0)
+ mxs_reg_32(hw_bch_flash0layout1)
+ mxs_reg_32(hw_bch_flash1layout0)
+ mxs_reg_32(hw_bch_flash1layout1)
+ mxs_reg_32(hw_bch_flash2layout0)
+ mxs_reg_32(hw_bch_flash2layout1)
+ mxs_reg_32(hw_bch_flash3layout0)
+ mxs_reg_32(hw_bch_flash3layout1)
+ mxs_reg_32(hw_bch_dbgkesread)
+ mxs_reg_32(hw_bch_dbgcsferead)
+ mxs_reg_32(hw_bch_dbgsyndegread)
+ mxs_reg_32(hw_bch_dbgahbmread)
+ mxs_reg_32(hw_bch_blockname)
+ mxs_reg_32(hw_bch_version)
+};
+#endif
+
+#define BCH_CTRL_SFTRST (1 << 31)
+#define BCH_CTRL_CLKGATE (1 << 30)
+#define BCH_CTRL_DEBUGSYNDROME (1 << 22)
+#define BCH_CTRL_M2M_LAYOUT_MASK (0x3 << 18)
+#define BCH_CTRL_M2M_LAYOUT_OFFSET 18
+#define BCH_CTRL_M2M_ENCODE (1 << 17)
+#define BCH_CTRL_M2M_ENABLE (1 << 16)
+#define BCH_CTRL_DEBUG_STALL_IRQ_EN (1 << 10)
+#define BCH_CTRL_COMPLETE_IRQ_EN (1 << 8)
+#define BCH_CTRL_BM_ERROR_IRQ (1 << 3)
+#define BCH_CTRL_DEBUG_STALL_IRQ (1 << 2)
+#define BCH_CTRL_COMPLETE_IRQ (1 << 0)
+
+#define BCH_STATUS0_HANDLE_MASK (0xfff << 20)
+#define BCH_STATUS0_HANDLE_OFFSET 20
+#define BCH_STATUS0_COMPLETED_CE_MASK (0xf << 16)
+#define BCH_STATUS0_COMPLETED_CE_OFFSET 16
+#define BCH_STATUS0_STATUS_BLK0_MASK (0xff << 8)
+#define BCH_STATUS0_STATUS_BLK0_OFFSET 8
+#define BCH_STATUS0_STATUS_BLK0_ZERO (0x00 << 8)
+#define BCH_STATUS0_STATUS_BLK0_ERROR1 (0x01 << 8)
+#define BCH_STATUS0_STATUS_BLK0_ERROR2 (0x02 << 8)
+#define BCH_STATUS0_STATUS_BLK0_ERROR3 (0x03 << 8)
+#define BCH_STATUS0_STATUS_BLK0_ERROR4 (0x04 << 8)
+#define BCH_STATUS0_STATUS_BLK0_UNCORRECTABLE (0xfe << 8)
+#define BCH_STATUS0_STATUS_BLK0_ERASED (0xff << 8)
+#define BCH_STATUS0_ALLONES (1 << 4)
+#define BCH_STATUS0_CORRECTED (1 << 3)
+#define BCH_STATUS0_UNCORRECTABLE (1 << 2)
+
+#define BCH_MODE_ERASE_THRESHOLD_MASK 0xff
+#define BCH_MODE_ERASE_THRESHOLD_OFFSET 0
+
+#define BCH_ENCODEPTR_ADDR_MASK 0xffffffff
+#define BCH_ENCODEPTR_ADDR_OFFSET 0
+
+#define BCH_DATAPTR_ADDR_MASK 0xffffffff
+#define BCH_DATAPTR_ADDR_OFFSET 0
+
+#define BCH_METAPTR_ADDR_MASK 0xffffffff
+#define BCH_METAPTR_ADDR_OFFSET 0
+
+#define BCH_LAYOUTSELECT_CS15_SELECT_MASK (0x3 << 30)
+#define BCH_LAYOUTSELECT_CS15_SELECT_OFFSET 30
+#define BCH_LAYOUTSELECT_CS14_SELECT_MASK (0x3 << 28)
+#define BCH_LAYOUTSELECT_CS14_SELECT_OFFSET 28
+#define BCH_LAYOUTSELECT_CS13_SELECT_MASK (0x3 << 26)
+#define BCH_LAYOUTSELECT_CS13_SELECT_OFFSET 26
+#define BCH_LAYOUTSELECT_CS12_SELECT_MASK (0x3 << 24)
+#define BCH_LAYOUTSELECT_CS12_SELECT_OFFSET 24
+#define BCH_LAYOUTSELECT_CS11_SELECT_MASK (0x3 << 22)
+#define BCH_LAYOUTSELECT_CS11_SELECT_OFFSET 22
+#define BCH_LAYOUTSELECT_CS10_SELECT_MASK (0x3 << 20)
+#define BCH_LAYOUTSELECT_CS10_SELECT_OFFSET 20
+#define BCH_LAYOUTSELECT_CS9_SELECT_MASK (0x3 << 18)
+#define BCH_LAYOUTSELECT_CS9_SELECT_OFFSET 18
+#define BCH_LAYOUTSELECT_CS8_SELECT_MASK (0x3 << 16)
+#define BCH_LAYOUTSELECT_CS8_SELECT_OFFSET 16
+#define BCH_LAYOUTSELECT_CS7_SELECT_MASK (0x3 << 14)
+#define BCH_LAYOUTSELECT_CS7_SELECT_OFFSET 14
+#define BCH_LAYOUTSELECT_CS6_SELECT_MASK (0x3 << 12)
+#define BCH_LAYOUTSELECT_CS6_SELECT_OFFSET 12
+#define BCH_LAYOUTSELECT_CS5_SELECT_MASK (0x3 << 10)
+#define BCH_LAYOUTSELECT_CS5_SELECT_OFFSET 10
+#define BCH_LAYOUTSELECT_CS4_SELECT_MASK (0x3 << 8)
+#define BCH_LAYOUTSELECT_CS4_SELECT_OFFSET 8
+#define BCH_LAYOUTSELECT_CS3_SELECT_MASK (0x3 << 6)
+#define BCH_LAYOUTSELECT_CS3_SELECT_OFFSET 6
+#define BCH_LAYOUTSELECT_CS2_SELECT_MASK (0x3 << 4)
+#define BCH_LAYOUTSELECT_CS2_SELECT_OFFSET 4
+#define BCH_LAYOUTSELECT_CS1_SELECT_MASK (0x3 << 2)
+#define BCH_LAYOUTSELECT_CS1_SELECT_OFFSET 2
+#define BCH_LAYOUTSELECT_CS0_SELECT_MASK (0x3 << 0)
+#define BCH_LAYOUTSELECT_CS0_SELECT_OFFSET 0
+
+#define BCH_FLASHLAYOUT0_NBLOCKS_MASK (0xff << 24)
+#define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24
+#define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << 16)
+#define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16
+#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
+#define BCH_FLASHLAYOUT0_ECC0_MASK (0x1f << 11)
+#define BCH_FLASHLAYOUT0_ECC0_OFFSET 11
+#else
+#define BCH_FLASHLAYOUT0_ECC0_MASK (0xf << 12)
+#define BCH_FLASHLAYOUT0_ECC0_OFFSET 12
+#endif
+#define BCH_FLASHLAYOUT0_ECC0_NONE (0x0 << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC2 (0x1 << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC4 (0x2 << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC6 (0x3 << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC8 (0x4 << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC10 (0x5 << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC12 (0x6 << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC14 (0x7 << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC16 (0x8 << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC18 (0x9 << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC20 (0xa << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC22 (0xb << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC24 (0xc << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC26 (0xd << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC28 (0xe << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC30 (0xf << 12)
+#define BCH_FLASHLAYOUT0_ECC0_ECC32 (0x10 << 12)
+#define BCH_FLASHLAYOUT0_GF13_0_GF14_1 (1 << 10)
+#define BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET 10
+#define BCH_FLASHLAYOUT0_DATA0_SIZE_MASK 0xfff
+#define BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET 0
+
+#define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16)
+#define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16
+#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
+#define BCH_FLASHLAYOUT1_ECCN_MASK (0x1f << 11)
+#define BCH_FLASHLAYOUT1_ECCN_OFFSET 11
+#else
+#define BCH_FLASHLAYOUT1_ECCN_MASK (0xf << 12)
+#define BCH_FLASHLAYOUT1_ECCN_OFFSET 12
+#endif
+#define BCH_FLASHLAYOUT1_ECCN_NONE (0x0 << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC2 (0x1 << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC4 (0x2 << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC6 (0x3 << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC8 (0x4 << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC10 (0x5 << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC12 (0x6 << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC14 (0x7 << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC16 (0x8 << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC18 (0x9 << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC20 (0xa << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC22 (0xb << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC24 (0xc << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC26 (0xd << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC28 (0xe << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC30 (0xf << 12)
+#define BCH_FLASHLAYOUT1_ECCN_ECC32 (0x10 << 12)
+#define BCH_FLASHLAYOUT1_GF13_0_GF14_1 (1 << 10)
+#define BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET 10
+#define BCH_FLASHLAYOUT1_DATAN_SIZE_MASK 0xfff
+#define BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET 0
+
+#define BCH_DEBUG0_RSVD1_MASK (0x1f << 27)
+#define BCH_DEBUG0_RSVD1_OFFSET 27
+#define BCH_DEBUG0_ROM_BIST_ENABLE (1 << 26)
+#define BCH_DEBUG0_ROM_BIST_COMPLETE (1 << 25)
+#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1ff << 16)
+#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_OFFSET 16
+#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_NORMAL (0x0 << 16)
+#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_TEST_MODE (0x1 << 16)
+#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND (1 << 15)
+#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG (1 << 14)
+#define BCH_DEBUG0_KES_DEBUG_MODE4K (1 << 13)
+#define BCH_DEBUG0_KES_DEBUG_KICK (1 << 12)
+#define BCH_DEBUG0_KES_STANDALONE (1 << 11)
+#define BCH_DEBUG0_KES_DEBUG_STEP (1 << 10)
+#define BCH_DEBUG0_KES_DEBUG_STALL (1 << 9)
+#define BCH_DEBUG0_BM_KES_TEST_BYPASS (1 << 8)
+#define BCH_DEBUG0_RSVD0_MASK (0x3 << 6)
+#define BCH_DEBUG0_RSVD0_OFFSET 6
+#define BCH_DEBUG0_DEBUG_REG_SELECT_MASK 0x3f
+#define BCH_DEBUG0_DEBUG_REG_SELECT_OFFSET 0
+
+#define BCH_DBGKESREAD_VALUES_MASK 0xffffffff
+#define BCH_DBGKESREAD_VALUES_OFFSET 0
+
+#define BCH_DBGCSFEREAD_VALUES_MASK 0xffffffff
+#define BCH_DBGCSFEREAD_VALUES_OFFSET 0
+
+#define BCH_DBGSYNDGENREAD_VALUES_MASK 0xffffffff
+#define BCH_DBGSYNDGENREAD_VALUES_OFFSET 0
+
+#define BCH_DBGAHBMREAD_VALUES_MASK 0xffffffff
+#define BCH_DBGAHBMREAD_VALUES_OFFSET 0
+
+#define BCH_BLOCKNAME_NAME_MASK 0xffffffff
+#define BCH_BLOCKNAME_NAME_OFFSET 0
+
+#define BCH_VERSION_MAJOR_MASK (0xff << 24)
+#define BCH_VERSION_MAJOR_OFFSET 24
+#define BCH_VERSION_MINOR_MASK (0xff << 16)
+#define BCH_VERSION_MINOR_OFFSET 16
+#define BCH_VERSION_STEP_MASK 0xffff
+#define BCH_VERSION_STEP_OFFSET 0
+
+#endif /* __MX28_REGS_BCH_H__ */
--- /dev/null
+/*
+ * Freescale i.MXS Register Accessors
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __MXS_REGS_COMMON_H__
+#define __MXS_REGS_COMMON_H__
+
+#include <linux/types.h>
+
+/*
+ * The i.MXS has interesting feature when it comes to register access. There
+ * are four kinds of access to one particular register. Those are:
+ *
+ * 1) Common read/write access. To use this mode, just write to the address of
+ * the register.
+ * 2) Set bits only access. To set bits, write which bits you want to set to the
+ * address of the register + 0x4.
+ * 3) Clear bits only access. To clear bits, write which bits you want to clear
+ * to the address of the register + 0x8.
+ * 4) Toggle bits only access. To toggle bits, write which bits you want to
+ * toggle to the address of the register + 0xc.
+ *
+ * IMPORTANT NOTE: Not all registers support accesses 2-4! Also, not all bits
+ * can be set/cleared by pure write as in access type 1, some need to be
+ * explicitly set/cleared by using access type 2-3.
+ *
+ * The following macros and structures allow the user to either access the
+ * register in all aforementioned modes (by accessing reg_name, reg_name_set,
+ * reg_name_clr, reg_name_tog) or pass the register structure further into
+ * various functions with correct type information (by accessing reg_name_reg).
+ *
+ */
+
+#define __mxs_reg_8(name) \
+ uint8_t name[4]; \
+ uint8_t name##_set[4]; \
+ uint8_t name##_clr[4]; \
+ uint8_t name##_tog[4]; \
+
+#define __mxs_reg_32(name) \
+ uint32_t name; \
+ uint32_t name##_set; \
+ uint32_t name##_clr; \
+ uint32_t name##_tog;
+
+struct mxs_register_8 {
+ __mxs_reg_8(reg)
+};
+
+struct mxs_register_32 {
+ __mxs_reg_32(reg)
+};
+
+#define mxs_reg_8(name) \
+ union { \
+ struct { __mxs_reg_8(name) }; \
+ struct mxs_register_8 name##_reg; \
+ };
+
+#define mxs_reg_32(name) \
+ union { \
+ struct { __mxs_reg_32(name) }; \
+ struct mxs_register_32 name##_reg; \
+ };
+
+#endif /* __MXS_REGS_COMMON_H__ */
--- /dev/null
+/*
+ * Freescale i.MX28 GPMI Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __MX28_REGS_GPMI_H__
+#define __MX28_REGS_GPMI_H__
+
+#include <asm/mach-imx/regs-common.h>
+
+#ifndef __ASSEMBLY__
+struct mxs_gpmi_regs {
+ mxs_reg_32(hw_gpmi_ctrl0)
+ mxs_reg_32(hw_gpmi_compare)
+ mxs_reg_32(hw_gpmi_eccctrl)
+ mxs_reg_32(hw_gpmi_ecccount)
+ mxs_reg_32(hw_gpmi_payload)
+ mxs_reg_32(hw_gpmi_auxiliary)
+ mxs_reg_32(hw_gpmi_ctrl1)
+ mxs_reg_32(hw_gpmi_timing0)
+ mxs_reg_32(hw_gpmi_timing1)
+
+ uint32_t reserved[4];
+
+ mxs_reg_32(hw_gpmi_data)
+ mxs_reg_32(hw_gpmi_stat)
+ mxs_reg_32(hw_gpmi_debug)
+ mxs_reg_32(hw_gpmi_version)
+};
+#endif
+
+#define GPMI_CTRL0_SFTRST (1 << 31)
+#define GPMI_CTRL0_CLKGATE (1 << 30)
+#define GPMI_CTRL0_RUN (1 << 29)
+#define GPMI_CTRL0_DEV_IRQ_EN (1 << 28)
+#define GPMI_CTRL0_LOCK_CS (1 << 27)
+#define GPMI_CTRL0_UDMA (1 << 26)
+#define GPMI_CTRL0_COMMAND_MODE_MASK (0x3 << 24)
+#define GPMI_CTRL0_COMMAND_MODE_OFFSET 24
+#define GPMI_CTRL0_COMMAND_MODE_WRITE (0x0 << 24)
+#define GPMI_CTRL0_COMMAND_MODE_READ (0x1 << 24)
+#define GPMI_CTRL0_COMMAND_MODE_READ_AND_COMPARE (0x2 << 24)
+#define GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY (0x3 << 24)
+#define GPMI_CTRL0_WORD_LENGTH (1 << 23)
+#define GPMI_CTRL0_CS_MASK (0x7 << 20)
+#define GPMI_CTRL0_CS_OFFSET 20
+#define GPMI_CTRL0_ADDRESS_MASK (0x7 << 17)
+#define GPMI_CTRL0_ADDRESS_OFFSET 17
+#define GPMI_CTRL0_ADDRESS_NAND_DATA (0x0 << 17)
+#define GPMI_CTRL0_ADDRESS_NAND_CLE (0x1 << 17)
+#define GPMI_CTRL0_ADDRESS_NAND_ALE (0x2 << 17)
+#define GPMI_CTRL0_ADDRESS_INCREMENT (1 << 16)
+#define GPMI_CTRL0_XFER_COUNT_MASK 0xffff
+#define GPMI_CTRL0_XFER_COUNT_OFFSET 0
+
+#define GPMI_COMPARE_MASK_MASK (0xffff << 16)
+#define GPMI_COMPARE_MASK_OFFSET 16
+#define GPMI_COMPARE_REFERENCE_MASK 0xffff
+#define GPMI_COMPARE_REFERENCE_OFFSET 0
+
+#define GPMI_ECCCTRL_HANDLE_MASK (0xffff << 16)
+#define GPMI_ECCCTRL_HANDLE_OFFSET 16
+#define GPMI_ECCCTRL_ECC_CMD_MASK (0x3 << 13)
+#define GPMI_ECCCTRL_ECC_CMD_OFFSET 13
+#define GPMI_ECCCTRL_ECC_CMD_DECODE (0x0 << 13)
+#define GPMI_ECCCTRL_ECC_CMD_ENCODE (0x1 << 13)
+#define GPMI_ECCCTRL_ENABLE_ECC (1 << 12)
+#define GPMI_ECCCTRL_BUFFER_MASK_MASK 0x1ff
+#define GPMI_ECCCTRL_BUFFER_MASK_OFFSET 0
+#define GPMI_ECCCTRL_BUFFER_MASK_BCH_AUXONLY 0x100
+#define GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE 0x1ff
+
+#define GPMI_ECCCOUNT_COUNT_MASK 0xffff
+#define GPMI_ECCCOUNT_COUNT_OFFSET 0
+
+#define GPMI_PAYLOAD_ADDRESS_MASK (0x3fffffff << 2)
+#define GPMI_PAYLOAD_ADDRESS_OFFSET 2
+
+#define GPMI_AUXILIARY_ADDRESS_MASK (0x3fffffff << 2)
+#define GPMI_AUXILIARY_ADDRESS_OFFSET 2
+
+#define GPMI_CTRL1_DECOUPLE_CS (1 << 24)
+#define GPMI_CTRL1_WRN_DLY_SEL_MASK (0x3 << 22)
+#define GPMI_CTRL1_WRN_DLY_SEL_OFFSET 22
+#define GPMI_CTRL1_TIMEOUT_IRQ_EN (1 << 20)
+#define GPMI_CTRL1_GANGED_RDYBUSY (1 << 19)
+#define GPMI_CTRL1_BCH_MODE (1 << 18)
+#define GPMI_CTRL1_DLL_ENABLE (1 << 17)
+#define GPMI_CTRL1_HALF_PERIOD (1 << 16)
+#define GPMI_CTRL1_RDN_DELAY_MASK (0xf << 12)
+#define GPMI_CTRL1_RDN_DELAY_OFFSET 12
+#define GPMI_CTRL1_DMA2ECC_MODE (1 << 11)
+#define GPMI_CTRL1_DEV_IRQ (1 << 10)
+#define GPMI_CTRL1_TIMEOUT_IRQ (1 << 9)
+#define GPMI_CTRL1_BURST_EN (1 << 8)
+#define GPMI_CTRL1_ABORT_WAIT_REQUEST (1 << 7)
+#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x7 << 4)
+#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_OFFSET 4
+#define GPMI_CTRL1_DEV_RESET (1 << 3)
+#define GPMI_CTRL1_ATA_IRQRDY_POLARITY (1 << 2)
+#define GPMI_CTRL1_CAMERA_MODE (1 << 1)
+#define GPMI_CTRL1_GPMI_MODE (1 << 0)
+
+#define GPMI_TIMING0_ADDRESS_SETUP_MASK (0xff << 16)
+#define GPMI_TIMING0_ADDRESS_SETUP_OFFSET 16
+#define GPMI_TIMING0_DATA_HOLD_MASK (0xff << 8)
+#define GPMI_TIMING0_DATA_HOLD_OFFSET 8
+#define GPMI_TIMING0_DATA_SETUP_MASK 0xff
+#define GPMI_TIMING0_DATA_SETUP_OFFSET 0
+
+#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK (0xffff << 16)
+#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_OFFSET 16
+
+#define GPMI_TIMING2_UDMA_TRP_MASK (0xff << 24)
+#define GPMI_TIMING2_UDMA_TRP_OFFSET 24
+#define GPMI_TIMING2_UDMA_ENV_MASK (0xff << 16)
+#define GPMI_TIMING2_UDMA_ENV_OFFSET 16
+#define GPMI_TIMING2_UDMA_HOLD_MASK (0xff << 8)
+#define GPMI_TIMING2_UDMA_HOLD_OFFSET 8
+#define GPMI_TIMING2_UDMA_SETUP_MASK 0xff
+#define GPMI_TIMING2_UDMA_SETUP_OFFSET 0
+
+#define GPMI_DATA_DATA_MASK 0xffffffff
+#define GPMI_DATA_DATA_OFFSET 0
+
+#define GPMI_STAT_READY_BUSY_MASK (0xff << 24)
+#define GPMI_STAT_READY_BUSY_OFFSET 24
+#define GPMI_STAT_RDY_TIMEOUT_MASK (0xff << 16)
+#define GPMI_STAT_RDY_TIMEOUT_OFFSET 16
+#define GPMI_STAT_DEV7_ERROR (1 << 15)
+#define GPMI_STAT_DEV6_ERROR (1 << 14)
+#define GPMI_STAT_DEV5_ERROR (1 << 13)
+#define GPMI_STAT_DEV4_ERROR (1 << 12)
+#define GPMI_STAT_DEV3_ERROR (1 << 11)
+#define GPMI_STAT_DEV2_ERROR (1 << 10)
+#define GPMI_STAT_DEV1_ERROR (1 << 9)
+#define GPMI_STAT_DEV0_ERROR (1 << 8)
+#define GPMI_STAT_ATA_IRQ (1 << 4)
+#define GPMI_STAT_INVALID_BUFFER_MASK (1 << 3)
+#define GPMI_STAT_FIFO_EMPTY (1 << 2)
+#define GPMI_STAT_FIFO_FULL (1 << 1)
+#define GPMI_STAT_PRESENT (1 << 0)
+
+#define GPMI_DEBUG_WAIT_FOR_READY_END_MASK (0xff << 24)
+#define GPMI_DEBUG_WAIT_FOR_READY_END_OFFSET 24
+#define GPMI_DEBUG_DMA_SENSE_MASK (0xff << 16)
+#define GPMI_DEBUG_DMA_SENSE_OFFSET 16
+#define GPMI_DEBUG_DMAREQ_MASK (0xff << 8)
+#define GPMI_DEBUG_DMAREQ_OFFSET 8
+#define GPMI_DEBUG_CMD_END_MASK 0xff
+#define GPMI_DEBUG_CMD_END_OFFSET 0
+
+#define GPMI_VERSION_MAJOR_MASK (0xff << 24)
+#define GPMI_VERSION_MAJOR_OFFSET 24
+#define GPMI_VERSION_MINOR_MASK (0xff << 16)
+#define GPMI_VERSION_MINOR_OFFSET 16
+#define GPMI_VERSION_STEP_MASK 0xffff
+#define GPMI_VERSION_STEP_OFFSET 0
+
+#define GPMI_DEBUG2_UDMA_STATE_MASK (0xf << 24)
+#define GPMI_DEBUG2_UDMA_STATE_OFFSET 24
+#define GPMI_DEBUG2_BUSY (1 << 23)
+#define GPMI_DEBUG2_PIN_STATE_MASK (0x7 << 20)
+#define GPMI_DEBUG2_PIN_STATE_OFFSET 20
+#define GPMI_DEBUG2_PIN_STATE_PSM_IDLE (0x0 << 20)
+#define GPMI_DEBUG2_PIN_STATE_PSM_BYTCNT (0x1 << 20)
+#define GPMI_DEBUG2_PIN_STATE_PSM_ADDR (0x2 << 20)
+#define GPMI_DEBUG2_PIN_STATE_PSM_STALL (0x3 << 20)
+#define GPMI_DEBUG2_PIN_STATE_PSM_STROBE (0x4 << 20)
+#define GPMI_DEBUG2_PIN_STATE_PSM_ATARDY (0x5 << 20)
+#define GPMI_DEBUG2_PIN_STATE_PSM_DHOLD (0x6 << 20)
+#define GPMI_DEBUG2_PIN_STATE_PSM_DONE (0x7 << 20)
+#define GPMI_DEBUG2_MAIN_STATE_MASK (0xf << 16)
+#define GPMI_DEBUG2_MAIN_STATE_OFFSET 16
+#define GPMI_DEBUG2_MAIN_STATE_MSM_IDLE (0x0 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_BYTCNT (0x1 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFE (0x2 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFR (0x3 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_DMAREQ (0x4 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_DMAACK (0x5 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFF (0x6 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_LDFIFO (0x7 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_LDDMAR (0x8 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_RDCMP (0x9 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_DONE (0xa << 16)
+#define GPMI_DEBUG2_SYND2GPMI_BE_MASK (0xf << 12)
+#define GPMI_DEBUG2_SYND2GPMI_BE_OFFSET 12
+#define GPMI_DEBUG2_GPMI2SYND_VALID (1 << 11)
+#define GPMI_DEBUG2_GPMI2SYND_READY (1 << 10)
+#define GPMI_DEBUG2_SYND2GPMI_VALID (1 << 9)
+#define GPMI_DEBUG2_SYND2GPMI_READY (1 << 8)
+#define GPMI_DEBUG2_VIEW_DELAYED_RDN (1 << 7)
+#define GPMI_DEBUG2_UPDATE_WINDOW (1 << 6)
+#define GPMI_DEBUG2_RDN_TAP_MASK 0x3f
+#define GPMI_DEBUG2_RDN_TAP_OFFSET 0
+
+#define GPMI_DEBUG3_APB_WORD_CNTR_MASK (0xffff << 16)
+#define GPMI_DEBUG3_APB_WORD_CNTR_OFFSET 16
+#define GPMI_DEBUG3_DEV_WORD_CNTR_MASK 0xffff
+#define GPMI_DEBUG3_DEV_WORD_CNTR_OFFSET 0
+
+#endif /* __MX28_REGS_GPMI_H__ */
--- /dev/null
+/*
+ * Freescale i.MX28/6SX/6UL/7D LCDIF Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __IMX_REGS_LCDIF_H__
+#define __IMX_REGS_LCDIF_H__
+
+#ifndef __ASSEMBLY__
+#include <asm/mach-imx/regs-common.h>
+
+struct mxs_lcdif_regs {
+ mxs_reg_32(hw_lcdif_ctrl) /* 0x00 */
+ mxs_reg_32(hw_lcdif_ctrl1) /* 0x10 */
+#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
+ defined(CONFIG_MX7) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
+ mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */
+#endif
+ mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */
+ mxs_reg_32(hw_lcdif_cur_buf) /* 0x30/0x40 */
+ mxs_reg_32(hw_lcdif_next_buf) /* 0x40/0x50 */
+
+#if defined(CONFIG_MX23)
+ uint32_t reserved1[4];
+#endif
+
+ mxs_reg_32(hw_lcdif_timing) /* 0x60 */
+ mxs_reg_32(hw_lcdif_vdctrl0) /* 0x70 */
+ mxs_reg_32(hw_lcdif_vdctrl1) /* 0x80 */
+ mxs_reg_32(hw_lcdif_vdctrl2) /* 0x90 */
+ mxs_reg_32(hw_lcdif_vdctrl3) /* 0xa0 */
+ mxs_reg_32(hw_lcdif_vdctrl4) /* 0xb0 */
+ mxs_reg_32(hw_lcdif_dvictrl0) /* 0xc0 */
+ mxs_reg_32(hw_lcdif_dvictrl1) /* 0xd0 */
+ mxs_reg_32(hw_lcdif_dvictrl2) /* 0xe0 */
+ mxs_reg_32(hw_lcdif_dvictrl3) /* 0xf0 */
+ mxs_reg_32(hw_lcdif_dvictrl4) /* 0x100 */
+ mxs_reg_32(hw_lcdif_csc_coeffctrl0) /* 0x110 */
+ mxs_reg_32(hw_lcdif_csc_coeffctrl1) /* 0x120 */
+ mxs_reg_32(hw_lcdif_csc_coeffctrl2) /* 0x130 */
+ mxs_reg_32(hw_lcdif_csc_coeffctrl3) /* 0x140 */
+ mxs_reg_32(hw_lcdif_csc_coeffctrl4) /* 0x150 */
+ mxs_reg_32(hw_lcdif_csc_offset) /* 0x160 */
+ mxs_reg_32(hw_lcdif_csc_limit) /* 0x170 */
+
+#if defined(CONFIG_MX23)
+ uint32_t reserved2[12];
+#endif
+ mxs_reg_32(hw_lcdif_data) /* 0x1b0/0x180 */
+ mxs_reg_32(hw_lcdif_bm_error_stat) /* 0x1c0/0x190 */
+#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
+ defined(CONFIG_MX7) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
+ mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */
+#endif
+ mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */
+ mxs_reg_32(hw_lcdif_version) /* 0x1e0/0x1c0 */
+ mxs_reg_32(hw_lcdif_debug0) /* 0x1f0/0x1d0 */
+ mxs_reg_32(hw_lcdif_debug1) /* 0x200/0x1e0 */
+ mxs_reg_32(hw_lcdif_debug2) /* 0x1f0 */
+#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX7) || \
+ defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
+ mxs_reg_32(hw_lcdif_thres)
+ mxs_reg_32(hw_lcdif_as_ctrl)
+ mxs_reg_32(hw_lcdif_as_buf)
+ mxs_reg_32(hw_lcdif_as_next_buf)
+ mxs_reg_32(hw_lcdif_as_clrkeylow)
+ mxs_reg_32(hw_lcdif_as_clrkeyhigh)
+ mxs_reg_32(hw_lcdif_as_sync_delay)
+ mxs_reg_32(hw_lcdif_as_debug3)
+ mxs_reg_32(hw_lcdif_as_debug4)
+ mxs_reg_32(hw_lcdif_as_debug5)
+#endif
+};
+#endif
+
+#define LCDIF_CTRL_SFTRST (1 << 31)
+#define LCDIF_CTRL_CLKGATE (1 << 30)
+#define LCDIF_CTRL_YCBCR422_INPUT (1 << 29)
+#define LCDIF_CTRL_READ_WRITEB (1 << 28)
+#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE (1 << 27)
+#define LCDIF_CTRL_DATA_SHIFT_DIR (1 << 26)
+#define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x1f << 21)
+#define LCDIF_CTRL_SHIFT_NUM_BITS_OFFSET 21
+#define LCDIF_CTRL_DVI_MODE (1 << 20)
+#define LCDIF_CTRL_BYPASS_COUNT (1 << 19)
+#define LCDIF_CTRL_VSYNC_MODE (1 << 18)
+#define LCDIF_CTRL_DOTCLK_MODE (1 << 17)
+#define LCDIF_CTRL_DATA_SELECT (1 << 16)
+#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0x3 << 14)
+#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET 14
+#define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3 << 12)
+#define LCDIF_CTRL_CSC_DATA_SWIZZLE_OFFSET 12
+#define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0x3 << 10)
+#define LCDIF_CTRL_LCD_DATABUS_WIDTH_OFFSET 10
+#define LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT (0 << 10)
+#define LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT (1 << 10)
+#define LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT (2 << 10)
+#define LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT (3 << 10)
+#define LCDIF_CTRL_WORD_LENGTH_MASK (0x3 << 8)
+#define LCDIF_CTRL_WORD_LENGTH_OFFSET 8
+#define LCDIF_CTRL_WORD_LENGTH_16BIT (0 << 8)
+#define LCDIF_CTRL_WORD_LENGTH_8BIT (1 << 8)
+#define LCDIF_CTRL_WORD_LENGTH_18BIT (2 << 8)
+#define LCDIF_CTRL_WORD_LENGTH_24BIT (3 << 8)
+#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC (1 << 7)
+#define LCDIF_CTRL_LCDIF_MASTER (1 << 5)
+#define LCDIF_CTRL_DATA_FORMAT_16_BIT (1 << 3)
+#define LCDIF_CTRL_DATA_FORMAT_18_BIT (1 << 2)
+#define LCDIF_CTRL_DATA_FORMAT_24_BIT (1 << 1)
+#define LCDIF_CTRL_RUN (1 << 0)
+
+#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB (1 << 27)
+#define LCDIF_CTRL1_BM_ERROR_IRQ_EN (1 << 26)
+#define LCDIF_CTRL1_BM_ERROR_IRQ (1 << 25)
+#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW (1 << 24)
+#define LCDIF_CTRL1_INTERLACE_FIELDS (1 << 23)
+#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD (1 << 22)
+#define LCDIF_CTRL1_FIFO_CLEAR (1 << 21)
+#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS (1 << 20)
+#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xf << 16)
+#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET 16
+#define LCDIF_CTRL1_OVERFLOW_IRQ_EN (1 << 15)
+#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN (1 << 14)
+#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN (1 << 13)
+#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN (1 << 12)
+#define LCDIF_CTRL1_OVERFLOW_IRQ (1 << 11)
+#define LCDIF_CTRL1_UNDERFLOW_IRQ (1 << 10)
+#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ (1 << 9)
+#define LCDIF_CTRL1_VSYNC_EDGE_IRQ (1 << 8)
+#define LCDIF_CTRL1_BUSY_ENABLE (1 << 2)
+#define LCDIF_CTRL1_MODE86 (1 << 1)
+#define LCDIF_CTRL1_RESET (1 << 0)
+
+#define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0x7 << 21)
+#define LCDIF_CTRL2_OUTSTANDING_REQS_OFFSET 21
+#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_1 (0x0 << 21)
+#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2 (0x1 << 21)
+#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_4 (0x2 << 21)
+#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_8 (0x3 << 21)
+#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16 (0x4 << 21)
+#define LCDIF_CTRL2_BURST_LEN_8 (1 << 20)
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x7 << 16)
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_OFFSET 16
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_RGB (0x0 << 16)
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_RBG (0x1 << 16)
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_GBR (0x2 << 16)
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_GRB (0x3 << 16)
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_BRG (0x4 << 16)
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_BGR (0x5 << 16)
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7 << 12)
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_OFFSET 12
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_RGB (0x0 << 12)
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_RBG (0x1 << 12)
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_GBR (0x2 << 12)
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_GRB (0x3 << 12)
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_BRG (0x4 << 12)
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_BGR (0x5 << 12)
+#define LCDIF_CTRL2_READ_PACK_DIR (1 << 10)
+#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT (1 << 9)
+#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT (1 << 8)
+#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x7 << 4)
+#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_OFFSET 4
+#define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0x7 << 1)
+#define LCDIF_CTRL2_INITIAL_DUMMY_READ_OFFSET 1
+
+#define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xffff << 16)
+#define LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET 16
+#define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xffff << 0)
+#define LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET 0
+
+#define LCDIF_CUR_BUF_ADDR_MASK 0xffffffff
+#define LCDIF_CUR_BUF_ADDR_OFFSET 0
+
+#define LCDIF_NEXT_BUF_ADDR_MASK 0xffffffff
+#define LCDIF_NEXT_BUF_ADDR_OFFSET 0
+
+#define LCDIF_TIMING_CMD_HOLD_MASK (0xff << 24)
+#define LCDIF_TIMING_CMD_HOLD_OFFSET 24
+#define LCDIF_TIMING_CMD_SETUP_MASK (0xff << 16)
+#define LCDIF_TIMING_CMD_SETUP_OFFSET 16
+#define LCDIF_TIMING_DATA_HOLD_MASK (0xff << 8)
+#define LCDIF_TIMING_DATA_HOLD_OFFSET 8
+#define LCDIF_TIMING_DATA_SETUP_MASK (0xff << 0)
+#define LCDIF_TIMING_DATA_SETUP_OFFSET 0
+
+#define LCDIF_VDCTRL0_VSYNC_OEB (1 << 29)
+#define LCDIF_VDCTRL0_ENABLE_PRESENT (1 << 28)
+#define LCDIF_VDCTRL0_VSYNC_POL (1 << 27)
+#define LCDIF_VDCTRL0_HSYNC_POL (1 << 26)
+#define LCDIF_VDCTRL0_DOTCLK_POL (1 << 25)
+#define LCDIF_VDCTRL0_ENABLE_POL (1 << 24)
+#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21)
+#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20)
+#define LCDIF_VDCTRL0_HALF_LINE (1 << 19)
+#define LCDIF_VDCTRL0_HALF_LINE_MODE (1 << 18)
+#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK 0x3ffff
+#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET 0
+
+#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK 0xffffffff
+#define LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET 0
+
+#if defined(CONFIG_MX23)
+#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xff << 24)
+#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 24
+#else
+#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18)
+#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18
+#endif
+#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK 0x3ffff
+#define LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET 0
+
+#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS (1 << 29)
+#define LCDIF_VDCTRL3_VSYNC_ONLY (1 << 28)
+#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xfff << 16)
+#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET 16
+#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xffff << 0)
+#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET 0
+
+#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0x7 << 29)
+#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET 29
+#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON (1 << 18)
+#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff
+#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0
+
+#endif /* __IMX_REGS_LCDIF_H__ */
--- /dev/null
+/*
+ * Freescale USB PHY Register Definitions
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#ifndef __REGS_USBPHY_H__
+#define __REGS_USBPHY_H__
+
+#define USBPHY_CTRL 0x00000030
+#define USBPHY_CTRL_SET 0x00000034
+#define USBPHY_CTRL_CLR 0x00000038
+#define USBPHY_CTRL_TOG 0x0000003C
+#define USBPHY_PWD 0x00000000
+#define USBPHY_TX 0x00000010
+#define USBPHY_RX 0x00000020
+#define USBPHY_DEBUG 0x00000050
+
+#define USBPHY_CTRL_ENUTMILEVEL2 (1 << 14)
+#define USBPHY_CTRL_ENUTMILEVEL3 (1 << 15)
+#define USBPHY_CTRL_OTG_ID (1 << 27)
+#define USBPHY_CTRL_CLKGATE (1 << 30)
+#define USBPHY_CTRL_SFTRST (1 << 31)
+
+#endif /* __REGS_USBPHY_H__ */
--- /dev/null
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __IMX_SATA_H_
+#define __IMX_SATA_H_
+
+/*
+ * SATA setup for i.mx6 quad based platform
+ */
+
+int setup_sata(void);
+
+#endif
--- /dev/null
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __MXC_SPI_H_
+#define __MXC_SPI_H_
+
+/*
+ * Board-level chip-select callback
+ * Should return GPIO # to be used for chip-select
+ */
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs);
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+#include <asm/io.h>
+#include <asm/mach-imx/regs-common.h>
+#include <common.h>
+#include "../arch-imx/cpu.h"
+
+#define soc_rev() (get_cpu_rev() & 0xFF)
+#define is_soc_rev(rev) (soc_rev() == rev)
+
+/* returns MXC_CPU_ value */
+#define cpu_type(rev) (((rev) >> 12) & 0xff)
+#define soc_type(rev) (((rev) >> 12) & 0xf0)
+/* both macros return/take MXC_CPU_ constants */
+#define get_cpu_type() (cpu_type(get_cpu_rev()))
+#define get_soc_type() (soc_type(get_cpu_rev()))
+#define is_cpu_type(cpu) (get_cpu_type() == cpu)
+#define is_soc_type(soc) (get_soc_type() == soc)
+
+#define is_mx6() (is_soc_type(MXC_SOC_MX6))
+#define is_mx7() (is_soc_type(MXC_SOC_MX7))
+
+#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
+#define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+#define is_mx6sdl() (is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6DL))
+#define is_mx6dl() (is_cpu_type(MXC_CPU_MX6DL))
+#define is_mx6sx() (is_cpu_type(MXC_CPU_MX6SX))
+#define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL))
+#define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO))
+#define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL))
+#define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL))
+#define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL))
+
+#define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP))
+
+#ifdef CONFIG_MX6
+#define IMX6_SRC_GPR10_BMODE BIT(28)
+
+#define IMX6_BMODE_MASK GENMASK(7, 0)
+#define IMX6_BMODE_SHIFT 4
+#define IMX6_BMODE_EMI_MASK BIT(3)
+#define IMX6_BMODE_EMI_SHIFT 3
+#define IMX6_BMODE_SERIAL_ROM_MASK GENMASK(26, 24)
+#define IMX6_BMODE_SERIAL_ROM_SHIFT 24
+
+enum imx6_bmode_serial_rom {
+ IMX6_BMODE_ECSPI1,
+ IMX6_BMODE_ECSPI2,
+ IMX6_BMODE_ECSPI3,
+ IMX6_BMODE_ECSPI4,
+ IMX6_BMODE_ECSPI5,
+ IMX6_BMODE_I2C1,
+ IMX6_BMODE_I2C2,
+ IMX6_BMODE_I2C3,
+};
+
+enum imx6_bmode_emi {
+ IMX6_BMODE_ONENAND,
+ IMX6_BMODE_NOR,
+};
+
+enum imx6_bmode {
+ IMX6_BMODE_EMI,
+ IMX6_BMODE_UART,
+ IMX6_BMODE_SATA,
+ IMX6_BMODE_SERIAL_ROM,
+ IMX6_BMODE_SD,
+ IMX6_BMODE_ESD,
+ IMX6_BMODE_MMC,
+ IMX6_BMODE_EMMC,
+ IMX6_BMODE_NAND,
+};
+
+static inline u8 imx6_is_bmode_from_gpr9(void)
+{
+ return readl(&src_base->gpr10) & IMX6_SRC_GPR10_BMODE;
+}
+
+u32 imx6_src_get_boot_mode(void);
+#endif /* CONFIG_MX6 */
+
+u32 get_nr_cpus(void);
+u32 get_cpu_rev(void);
+u32 get_cpu_speed_grade_hz(void);
+u32 get_cpu_temp_grade(int *minc, int *maxc);
+const char *get_imx_type(u32 imxtype);
+u32 imx_ddr_size(void);
+void sdelay(unsigned long);
+void set_chipselect_size(int const);
+
+void init_aips(void);
+void init_src(void);
+void imx_set_wdog_powerdown(bool enable);
+
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
+int fecmxc_initialize(bd_t *bis);
+u32 get_ahb_clk(void);
+u32 get_periph_clk(void);
+
+void lcdif_power_down(void);
+
+int mxs_reset_block(struct mxs_register_32 *reg);
+int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
+int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_SYSTEM_COUNTER_H
+#define _ASM_ARCH_SYSTEM_COUNTER_H
+
+/* System Counter */
+struct sctr_regs {
+ u32 cntcr;
+ u32 cntsr;
+ u32 cntcv1;
+ u32 cntcv2;
+ u32 resv1[4];
+ u32 cntfid0;
+ u32 cntfid1;
+ u32 cntfid2;
+ u32 resv2[1001];
+ u32 counterid[1];
+};
+
+#define SC_CNTCR_ENABLE (1 << 0)
+#define SC_CNTCR_HDBG (1 << 1)
+#define SC_CNTCR_FREQ0 (1 << 8)
+#define SC_CNTCR_FREQ1 (1 << 9)
+
+#endif
--- /dev/null
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __IMX_VIDEO_H_
+#define __IMX_VIDEO_H_
+
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+
+struct display_info_t {
+ int bus;
+ int addr;
+ int pixfmt;
+ int di;
+ int (*detect)(struct display_info_t const *dev);
+ void (*enable)(struct display_info_t const *dev);
+ struct fb_videomode mode;
+};
+
+#ifdef CONFIG_IMX_HDMI
+extern int detect_hdmi(struct display_info_t const *dev);
+#endif
+
+#ifdef CONFIG_IMX_VIDEO_SKIP
+extern struct display_info_t const displays[];
+extern size_t display_count;
+#endif
+
+int ipu_set_ldb_clock(int rate);
+#endif
/* Initialize general purpose I2C(0) on the SoC */
void gpi2c_init(void);
+/* Common FDT Fixups */
+int ft_hs_disable_rng(void *fdt, bd_t *bd);
+int ft_hs_fixup_dram(void *fdt, bd_t *bd);
+int ft_hs_add_tee(void *fdt, bd_t *bd);
+
/* ABB */
#define OMAP_ABB_NOMINAL_OPP 0
#define OMAP_ABB_FAST_OPP 1
*/
int secure_boot_verify_image(void **p_image, size_t *p_size);
+/*
+ * Return the start of secure reserved RAM, if a default start address has
+ * not been configured then return a region at the end of the external DRAM.
+ */
+u32 get_sec_mem_start(void);
+
/*
* Invoke a secure HAL API that allows configuration of the external memory
* firewall regions.
bool "Exynos4 SoC family"
select CPU_V7
select BOARD_EARLY_INIT_F
+ imply ENV_IS_IN_MMC
help
Samsung Exynos4 SoC family are based on ARM Cortex-A9 CPU. There
are multiple SoCs in this family including Exynos4210, Exynos4412,
--- /dev/null
+config IMX_CONFIG
+ string
+
+config ROM_UNIFIED_SECTIONS
+ bool
+
+config IMX_RDC
+ bool "i.MX Resource domain controller driver"
+ depends on ARCH_MX6 || ARCH_MX7
+ help
+ i.MX Resource domain controller is used to assign masters
+ and peripherals to differet domains. This can be used to
+ isolate resources.
+
+config IMX_BOOTAUX
+ bool "Support boot auxiliary core"
+ depends on ARCH_MX7 || ARCH_MX6
+ help
+ bootaux [addr] to boot auxiliary core.
+
+config USE_IMXIMG_PLUGIN
+ bool "Use imximage plugin code"
+ depends on ARCH_MX7 || ARCH_MX6
+ help
+ i.MX6/7 supports DCD and Plugin. Enable this configuration
+ to use Plugin, otherwise DCD will be used.
+
+config SECURE_BOOT
+ bool "Support i.MX HAB features"
+ depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5
+ select FSL_CAAM
+ imply CMD_DEKBLOB
+ help
+ This option enables the support for secure boot (HAB).
+ See doc/README.mxc_hab for more details.
+
+config CMD_BMODE
+ bool "Support the 'bmode' command"
+ default y
+ depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5
+ help
+ This enables the 'bmode' (bootmode) command for forcing
+ a boot from specific media.
+
+ This is useful for forcing the ROM's usb downloader to
+ activate upon a watchdog reset which is nice when iterating
+ on U-Boot. Using the reset button or running bmode normal
+ will set it back to normal. This command currently
+ supports i.MX53 and i.MX6.
+
+config CMD_DEKBLOB
+ bool "Support the 'dek_blob' command"
+ help
+ This enables the 'dek_blob' command which is used with the
+ Freescale secure boot mechanism. This command encapsulates and
+ creates a blob of data. See also CMD_BLOB and doc/README.mxc_hab for
+ more information.
+
+config CMD_HDMIDETECT
+ bool "Support the 'hdmidet' command"
+ help
+ This enables the 'hdmidet' command which detects if an HDMI monitor
+ is connected.
--- /dev/null
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 vf610))
+obj-y = iomux-v3.o
+endif
+ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
+obj-y += timer.o cpu.o speed.o
+obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
+endif
+ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs))
+obj-y += misc.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
+endif
+ifeq ($(SOC),$(filter $(SOC),mx7))
+obj-y += cpu.o
+obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
+obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o
+endif
+ifeq ($(SOC),$(filter $(SOC),mx6 mx7))
+obj-y += cache.o init.o
+obj-$(CONFIG_SATA) += sata.o
+obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
+obj-$(CONFIG_IMX_RDC) += rdc-sema.o
+obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
+obj-$(CONFIG_SECURE_BOOT) += hab.o
+endif
+ifeq ($(SOC),$(filter $(SOC),mx7ulp))
+obj-y += cache.o
+obj-$(CONFIG_SECURE_BOOT) += hab.o
+endif
+ifeq ($(SOC),$(filter $(SOC),vf610))
+obj-y += ddrmc-vf610.o
+endif
+ifneq ($(CONFIG_SPL_BUILD),y)
+obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o
+obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
+obj-$(CONFIG_CMD_DEKBLOB) += cmd_dek.o
+endif
+
+PLUGIN = board/$(BOARDDIR)/plugin
+
+ifeq ($(CONFIG_USE_IMXIMG_PLUGIN),y)
+
+$(PLUGIN).o: $(PLUGIN).S FORCE
+ $(Q)mkdir -p $(dir $@)
+ $(call if_changed_dep,as_o_S)
+
+$(PLUGIN).bin: $(PLUGIN).o FORCE
+ $(Q)mkdir -p $(dir $@)
+ $(OBJCOPY) -O binary --gap-fill 0xff $< $@
+else
+
+$(PLUGIN).bin:
+
+endif
+
+quiet_cmd_cpp_cfg = CFGS $@
+ cmd_cpp_cfg = $(CPP) $(cpp_flags) -x c -o $@ $<
+
+IMX_CONFIG = $(CONFIG_IMX_CONFIG:"%"=%).cfgtmp
+
+$(IMX_CONFIG): %.cfgtmp: % FORCE
+ $(Q)mkdir -p $(dir $@)
+ $(call if_changed_dep,cpp_cfg)
+
+MKIMAGEFLAGS_u-boot.imx = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) -T imximage \
+ -e $(CONFIG_SYS_TEXT_BASE)
+u-boot.imx: MKIMAGEOUTPUT = u-boot.imx.log
+
+u-boot.imx: u-boot.bin $(IMX_CONFIG) $(PLUGIN).bin FORCE
+ $(call if_changed,mkimage)
+
+ifeq ($(CONFIG_OF_SEPARATE),y)
+MKIMAGEFLAGS_u-boot-dtb.imx = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) -T imximage \
+ -e $(CONFIG_SYS_TEXT_BASE)
+u-boot-dtb.imx: MKIMAGEOUTPUT = u-boot-dtb.imx.log
+
+u-boot-dtb.imx: u-boot-dtb.bin $(IMX_CONFIG) $(PLUGIN).bin FORCE
+ $(call if_changed,mkimage)
+endif
+
+MKIMAGEFLAGS_SPL = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) -T imximage \
+ -e $(CONFIG_SPL_TEXT_BASE)
+
+SPL: MKIMAGEOUTPUT = SPL.log
+
+SPL: spl/u-boot-spl.bin $(IMX_CONFIG) $(PLUGIN).bin FORCE
+ $(call if_changed,mkimage)
+
+MKIMAGEFLAGS_u-boot.uim = -A arm -O U-Boot -a $(CONFIG_SYS_TEXT_BASE) \
+ -e $(CONFIG_SYS_TEXT_BASE) -C none -T firmware
+
+u-boot.uim: u-boot.bin FORCE
+ $(call if_changed,mkimage)
+
+OBJCOPYFLAGS += -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO)
+append = cat $(filter-out $< $(PHONY), $^) >> $@
+
+quiet_cmd_pad_cat = CAT $@
+cmd_pad_cat = $(cmd_objcopy) && $(append) || rm -f $@
+
+u-boot-with-spl.imx: SPL u-boot.uim FORCE
+ $(call if_changed,pad_cat)
+
+u-boot-with-nand-spl.imx: spl/u-boot-nand-spl.imx u-boot.uim FORCE
+ $(call if_changed,pad_cat)
+
+quiet_cmd_u-boot-nand-spl_imx = GEN $@
+cmd_u-boot-nand-spl_imx = (printf '\000\000\000\000\106\103\102\040\001' && \
+ dd bs=1015 count=1 if=/dev/zero 2>/dev/null) | cat - $< > $@
+
+spl/u-boot-nand-spl.imx: SPL FORCE
+ $(call if_changed,u-boot-nand-spl_imx)
+
+targets += $(addprefix ../../../,$(IMX_CONFIG) SPL u-boot.uim spl/u-boot-nand-spl.imx)
+
+obj-$(CONFIG_MX5) += mx5/
+obj-$(CONFIG_MX6) += mx6/
+obj-$(CONFIG_MX7) += mx7/
+obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/
+
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/armv7.h>
+#include <asm/pl310.h>
+#include <asm/io.h>
+#include <asm/mach-imx/sys_proto.h>
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+ enum dcache_option option = DCACHE_WRITETHROUGH;
+#else
+ enum dcache_option option = DCACHE_WRITEBACK;
+#endif
+ /* Avoid random hang when download by usb */
+ invalidate_dcache_all();
+
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+
+ /* Enable caching on OCRAM and ROM */
+ mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
+ ROMCP_ARB_END_ADDR,
+ option);
+ mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
+ IRAM_SIZE,
+ option);
+}
+#endif
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+#ifdef CONFIG_SYS_L2_PL310
+#define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
+void v7_outer_cache_enable(void)
+{
+ struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ unsigned int val;
+
+
+ /*
+ * Must disable the L2 before changing the latency parameters
+ * and auxiliary control register.
+ */
+ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+
+ /*
+ * Set bit 22 in the auxiliary control register. If this bit
+ * is cleared, PL310 treats Normal Shared Non-cacheable
+ * accesses as Cacheable no-allocate.
+ */
+ setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
+
+ if (is_mx6sl() || is_mx6sll()) {
+ val = readl(&iomux->gpr[11]);
+ if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
+ /* L2 cache configured as OCRAM, reset it */
+ val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
+ writel(val, &iomux->gpr[11]);
+ }
+ }
+
+ writel(0x132, &pl310->pl310_tag_latency_ctrl);
+ writel(0x132, &pl310->pl310_data_latency_ctrl);
+
+ val = readl(&pl310->pl310_prefetch_ctrl);
+
+ /* Turn on the L2 I/D prefetch */
+ val |= 0x30000000;
+
+ /*
+ * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
+ * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
+ * But according to ARM PL310 errata: 752271
+ * ID: 752271: Double linefill feature can cause data corruption
+ * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
+ * Workaround: The only workaround to this erratum is to disable the
+ * double linefill feature. This is the default behavior.
+ */
+
+#ifndef CONFIG_MX6Q
+ val |= 0x40800000;
+#endif
+ writel(val, &pl310->pl310_prefetch_ctrl);
+
+ val = readl(&pl310->pl310_power_ctrl);
+ val |= L2X0_DYNAMIC_CLK_GATING_EN;
+ val |= L2X0_STNDBY_MODE_EN;
+ writel(val, &pl310->pl310_power_ctrl);
+
+ setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+}
+
+void v7_outer_cache_disable(void)
+{
+ struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
+
+ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+}
+#endif /* !CONFIG_SYS_L2_PL310 */
+#endif /* !CONFIG_SYS_L2CACHE_OFF */
--- /dev/null
+/*
+ * Copyright (C) 2012 Boundary Devices Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <linux/errno.h>
+#include <asm/io.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <malloc.h>
+#include <command.h>
+
+static const struct boot_mode *modes[2];
+
+static const struct boot_mode *search_modes(char *arg)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(modes); i++) {
+ const struct boot_mode *p = modes[i];
+ if (p) {
+ while (p->name) {
+ if (!strcmp(p->name, arg))
+ return p;
+ p++;
+ }
+ }
+ }
+ return NULL;
+}
+
+static int create_usage(char *dest)
+{
+ int i;
+ int size = 0;
+
+ for (i = 0; i < ARRAY_SIZE(modes); i++) {
+ const struct boot_mode *p = modes[i];
+ if (p) {
+ while (p->name) {
+ int len = strlen(p->name);
+ if (dest) {
+ memcpy(dest, p->name, len);
+ dest += len;
+ *dest++ = '|';
+ }
+ size += len + 1;
+ p++;
+ }
+ }
+ }
+ if (dest)
+ memcpy(dest - 1, " [noreset]", 11); /* include trailing 0 */
+ size += 10;
+ return size;
+}
+
+static int do_boot_mode(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ const struct boot_mode *p;
+ int reset_requested = 1;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+ p = search_modes(argv[1]);
+ if (!p)
+ return CMD_RET_USAGE;
+ if (argc == 3) {
+ if (strcmp(argv[2], "noreset"))
+ return CMD_RET_USAGE;
+ reset_requested = 0;
+ }
+
+ boot_mode_apply(p->cfg_val);
+ if (reset_requested && p->cfg_val)
+ do_reset(NULL, 0, 0, NULL);
+ return 0;
+}
+
+U_BOOT_CMD(
+ bmode, 3, 0, do_boot_mode,
+ NULL,
+ "");
+
+void add_board_boot_modes(const struct boot_mode *p)
+{
+ int size;
+ char *dest;
+
+ cmd_tbl_t *entry = ll_entry_get(cmd_tbl_t, bmode, cmd);
+
+ if (entry->usage) {
+ free(entry->usage);
+ entry->usage = NULL;
+ }
+
+ modes[0] = p;
+ modes[1] = soc_boot_modes;
+ size = create_usage(NULL);
+ dest = malloc(size);
+ if (dest) {
+ create_usage(dest);
+ entry->usage = dest;
+ }
+}
--- /dev/null
+/*
+ * Copyright 2008-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Command for encapsulating DEK blob
+ */
+
+#include <common.h>
+#include <command.h>
+#include <environment.h>
+#include <malloc.h>
+#include <asm/byteorder.h>
+#include <linux/compiler.h>
+#include <fsl_sec.h>
+#include <asm/arch/clock.h>
+#include <mapmem.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+* blob_dek() - Encapsulate the DEK as a blob using CAM's Key
+* @src: - Address of data to be encapsulated
+* @dst: - Desination address of encapsulated data
+* @len: - Size of data to be encapsulated
+*
+* Returns zero on success,and negative on error.
+*/
+static int blob_encap_dek(const u8 *src, u8 *dst, u32 len)
+{
+ int ret = 0;
+ u32 jr_size = 4;
+
+ u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR + 0x102c);
+ if (out_jr_size != jr_size) {
+ hab_caam_clock_enable(1);
+ sec_init();
+ }
+
+ if (!((len == 128) | (len == 192) | (len == 256))) {
+ debug("Invalid DEK size. Valid sizes are 128, 192 and 256b\n");
+ return -1;
+ }
+
+ len /= 8;
+ ret = blob_dek(src, dst, len);
+
+ return ret;
+}
+
+/**
+ * do_dek_blob() - Handle the "dek_blob" command-line command
+ * @cmdtp: Command data struct pointer
+ * @flag: Command flag
+ * @argc: Command-line argument count
+ * @argv: Array of command-line arguments
+ *
+ * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
+ * on error.
+ */
+static int do_dek_blob(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ uint32_t src_addr, dst_addr, len;
+ uint8_t *src_ptr, *dst_ptr;
+ int ret = 0;
+
+ if (argc != 4)
+ return CMD_RET_USAGE;
+
+ src_addr = simple_strtoul(argv[1], NULL, 16);
+ dst_addr = simple_strtoul(argv[2], NULL, 16);
+ len = simple_strtoul(argv[3], NULL, 10);
+
+ src_ptr = map_sysmem(src_addr, len/8);
+ dst_ptr = map_sysmem(dst_addr, BLOB_SIZE(len/8));
+
+ ret = blob_encap_dek(src_ptr, dst_ptr, len);
+
+ return ret;
+}
+
+/***************************************************/
+static char dek_blob_help_text[] =
+ "src dst len - Encapsulate and create blob of data\n"
+ " $len bits long at address $src and\n"
+ " store the result at address $dst.\n";
+
+U_BOOT_CMD(
+ dek_blob, 4, 1, do_dek_blob,
+ "Data Encryption Key blob encapsulation",
+ dek_blob_help_text
+);
--- /dev/null
+/*
+ * Copyright (C) 2012 Boundary Devices Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/io.h>
+
+static int do_hdmidet(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
+ return (readb(&hdmi->phy_stat0) & HDMI_DVI_STAT) ? 0 : 1;
+}
+
+U_BOOT_CMD(hdmidet, 1, 1, do_hdmidet,
+ "detect HDMI monitor",
+ ""
+);
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <bootm.h>
+#include <common.h>
+#include <netdev.h>
+#include <linux/errno.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <imx_thermal.h>
+#include <ipu_pixfmt.h>
+#include <thermal.h>
+#include <sata.h>
+
+#ifdef CONFIG_FSL_ESDHC
+#include <fsl_esdhc.h>
+#endif
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+static u32 reset_cause = -1;
+
+static char *get_reset_cause(void)
+{
+ u32 cause;
+ struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+
+ cause = readl(&src_regs->srsr);
+ writel(cause, &src_regs->srsr);
+ reset_cause = cause;
+
+ switch (cause) {
+ case 0x00001:
+ case 0x00011:
+ return "POR";
+ case 0x00004:
+ return "CSU";
+ case 0x00008:
+ return "IPP USER";
+ case 0x00010:
+#ifdef CONFIG_MX7
+ return "WDOG1";
+#else
+ return "WDOG";
+#endif
+ case 0x00020:
+ return "JTAG HIGH-Z";
+ case 0x00040:
+ return "JTAG SW";
+ case 0x00080:
+ return "WDOG3";
+#ifdef CONFIG_MX7
+ case 0x00100:
+ return "WDOG4";
+ case 0x00200:
+ return "TEMPSENSE";
+#else
+ case 0x00100:
+ return "TEMPSENSE";
+ case 0x10000:
+ return "WARM BOOT";
+#endif
+ default:
+ return "unknown reset";
+ }
+}
+
+u32 get_imx_reset_cause(void)
+{
+ return reset_cause;
+}
+#endif
+
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_MX53)
+#define MEMCTL_BASE ESDCTL_BASE_ADDR
+#else
+#define MEMCTL_BASE MMDC_P0_BASE_ADDR
+#endif
+static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
+static const unsigned char bank_lookup[] = {3, 2};
+
+/* these MMDC registers are common to the IMX53 and IMX6 */
+struct esd_mmdc_regs {
+ uint32_t ctl;
+ uint32_t pdc;
+ uint32_t otc;
+ uint32_t cfg0;
+ uint32_t cfg1;
+ uint32_t cfg2;
+ uint32_t misc;
+};
+
+#define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7)
+#define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7)
+#define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3)
+#define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1)
+#define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1)
+
+/*
+ * imx_ddr_size - return size in bytes of DRAM according MMDC config
+ * The MMDC MDCTL register holds the number of bits for row, col, and data
+ * width and the MMDC MDMISC register holds the number of banks. Combine
+ * all these bits to determine the meme size the MMDC has been configured for
+ */
+unsigned imx_ddr_size(void)
+{
+ struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
+ unsigned ctl = readl(&mem->ctl);
+ unsigned misc = readl(&mem->misc);
+ int bits = 11 + 0 + 0 + 1; /* row + col + bank + width */
+
+ bits += ESD_MMDC_CTL_GET_ROW(ctl);
+ bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
+ bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
+ bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
+ bits += ESD_MMDC_CTL_GET_CS1(ctl);
+
+ /* The MX6 can do only 3840 MiB of DRAM */
+ if (bits == 32)
+ return 0xf0000000;
+
+ return 1 << bits;
+}
+#endif
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+
+const char *get_imx_type(u32 imxtype)
+{
+ switch (imxtype) {
+ case MXC_CPU_MX7S:
+ return "7S"; /* Single-core version of the mx7 */
+ case MXC_CPU_MX7D:
+ return "7D"; /* Dual-core version of the mx7 */
+ case MXC_CPU_MX6QP:
+ return "6QP"; /* Quad-Plus version of the mx6 */
+ case MXC_CPU_MX6DP:
+ return "6DP"; /* Dual-Plus version of the mx6 */
+ case MXC_CPU_MX6Q:
+ return "6Q"; /* Quad-core version of the mx6 */
+ case MXC_CPU_MX6D:
+ return "6D"; /* Dual-core version of the mx6 */
+ case MXC_CPU_MX6DL:
+ return "6DL"; /* Dual Lite version of the mx6 */
+ case MXC_CPU_MX6SOLO:
+ return "6SOLO"; /* Solo version of the mx6 */
+ case MXC_CPU_MX6SL:
+ return "6SL"; /* Solo-Lite version of the mx6 */
+ case MXC_CPU_MX6SLL:
+ return "6SLL"; /* SLL version of the mx6 */
+ case MXC_CPU_MX6SX:
+ return "6SX"; /* SoloX version of the mx6 */
+ case MXC_CPU_MX6UL:
+ return "6UL"; /* Ultra-Lite version of the mx6 */
+ case MXC_CPU_MX6ULL:
+ return "6ULL"; /* ULL version of the mx6 */
+ case MXC_CPU_MX51:
+ return "51";
+ case MXC_CPU_MX53:
+ return "53";
+ default:
+ return "??";
+ }
+}
+
+int print_cpuinfo(void)
+{
+ u32 cpurev;
+ __maybe_unused u32 max_freq;
+
+ cpurev = get_cpu_rev();
+
+#if defined(CONFIG_IMX_THERMAL)
+ struct udevice *thermal_dev;
+ int cpu_tmp, minc, maxc, ret;
+
+ printf("CPU: Freescale i.MX%s rev%d.%d",
+ get_imx_type((cpurev & 0xFF000) >> 12),
+ (cpurev & 0x000F0) >> 4,
+ (cpurev & 0x0000F) >> 0);
+ max_freq = get_cpu_speed_grade_hz();
+ if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) {
+ printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
+ } else {
+ printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
+ mxc_get_clock(MXC_ARM_CLK) / 1000000);
+ }
+#else
+ printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
+ get_imx_type((cpurev & 0xFF000) >> 12),
+ (cpurev & 0x000F0) >> 4,
+ (cpurev & 0x0000F) >> 0,
+ mxc_get_clock(MXC_ARM_CLK) / 1000000);
+#endif
+
+#if defined(CONFIG_IMX_THERMAL)
+ puts("CPU: ");
+ switch (get_cpu_temp_grade(&minc, &maxc)) {
+ case TEMP_AUTOMOTIVE:
+ puts("Automotive temperature grade ");
+ break;
+ case TEMP_INDUSTRIAL:
+ puts("Industrial temperature grade ");
+ break;
+ case TEMP_EXTCOMMERCIAL:
+ puts("Extended Commercial temperature grade ");
+ break;
+ default:
+ puts("Commercial temperature grade ");
+ break;
+ }
+ printf("(%dC to %dC)", minc, maxc);
+ ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
+ if (!ret) {
+ ret = thermal_get_temp(thermal_dev, &cpu_tmp);
+
+ if (!ret)
+ printf(" at %dC\n", cpu_tmp);
+ else
+ debug(" - invalid sensor data\n");
+ } else {
+ debug(" - invalid sensor device\n");
+ }
+#endif
+
+ printf("Reset cause: %s\n", get_reset_cause());
+ return 0;
+}
+#endif
+
+int cpu_eth_init(bd_t *bis)
+{
+ int rc = -ENODEV;
+
+#if defined(CONFIG_FEC_MXC)
+ rc = fecmxc_initialize(bis);
+#endif
+
+ return rc;
+}
+
+#ifdef CONFIG_FSL_ESDHC
+/*
+ * Initializes on-chip MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(bd_t *bis)
+{
+ return fsl_esdhc_mmc_init(bis);
+}
+#endif
+
+#ifndef CONFIG_MX7
+u32 get_ahb_clk(void)
+{
+ struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ u32 reg, ahb_podf;
+
+ reg = __raw_readl(&imx_ccm->cbcdr);
+ reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
+ ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
+
+ return get_periph_clk() / (ahb_podf + 1);
+}
+#endif
+
+void arch_preboot_os(void)
+{
+#if defined(CONFIG_PCIE_IMX)
+ imx_pcie_remove();
+#endif
+#if defined(CONFIG_SATA)
+ sata_stop();
+#if defined(CONFIG_MX6)
+ disable_sata_clock();
+#endif
+#endif
+#if defined(CONFIG_VIDEO_IPUV3)
+ /* disable video before launching O/S */
+ ipuv3_fb_shutdown();
+#endif
+#if defined(CONFIG_VIDEO_MXS)
+ lcdif_power_down();
+#endif
+}
+
+void set_chipselect_size(int const cs_size)
+{
+ unsigned int reg;
+ struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ reg = readl(&iomuxc_regs->gpr[1]);
+
+ switch (cs_size) {
+ case CS0_128:
+ reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
+ reg |= 0x5;
+ break;
+ case CS0_64M_CS1_64M:
+ reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
+ reg |= 0x1B;
+ break;
+ case CS0_64M_CS1_32M_CS2_32M:
+ reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
+ reg |= 0x4B;
+ break;
+ case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
+ reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
+ reg |= 0x249;
+ break;
+ default:
+ printf("Unknown chip select size: %d\n", cs_size);
+ break;
+ }
+
+ writel(reg, &iomuxc_regs->gpr[1]);
+}
--- /dev/null
+/*
+ * Copyright 2015 Toradex, Inc.
+ *
+ * Based on vf610twr:
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-vf610.h>
+#include <asm/arch/ddrmc-vf610.h>
+
+void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count)
+{
+ static const iomux_v3_cfg_t default_pads[] = {
+ VF610_PAD_DDR_A15__DDR_A_15,
+ VF610_PAD_DDR_A14__DDR_A_14,
+ VF610_PAD_DDR_A13__DDR_A_13,
+ VF610_PAD_DDR_A12__DDR_A_12,
+ VF610_PAD_DDR_A11__DDR_A_11,
+ VF610_PAD_DDR_A10__DDR_A_10,
+ VF610_PAD_DDR_A9__DDR_A_9,
+ VF610_PAD_DDR_A8__DDR_A_8,
+ VF610_PAD_DDR_A7__DDR_A_7,
+ VF610_PAD_DDR_A6__DDR_A_6,
+ VF610_PAD_DDR_A5__DDR_A_5,
+ VF610_PAD_DDR_A4__DDR_A_4,
+ VF610_PAD_DDR_A3__DDR_A_3,
+ VF610_PAD_DDR_A2__DDR_A_2,
+ VF610_PAD_DDR_A1__DDR_A_1,
+ VF610_PAD_DDR_A0__DDR_A_0,
+ VF610_PAD_DDR_BA2__DDR_BA_2,
+ VF610_PAD_DDR_BA1__DDR_BA_1,
+ VF610_PAD_DDR_BA0__DDR_BA_0,
+ VF610_PAD_DDR_CAS__DDR_CAS_B,
+ VF610_PAD_DDR_CKE__DDR_CKE_0,
+ VF610_PAD_DDR_CLK__DDR_CLK_0,
+ VF610_PAD_DDR_CS__DDR_CS_B_0,
+ VF610_PAD_DDR_D15__DDR_D_15,
+ VF610_PAD_DDR_D14__DDR_D_14,
+ VF610_PAD_DDR_D13__DDR_D_13,
+ VF610_PAD_DDR_D12__DDR_D_12,
+ VF610_PAD_DDR_D11__DDR_D_11,
+ VF610_PAD_DDR_D10__DDR_D_10,
+ VF610_PAD_DDR_D9__DDR_D_9,
+ VF610_PAD_DDR_D8__DDR_D_8,
+ VF610_PAD_DDR_D7__DDR_D_7,
+ VF610_PAD_DDR_D6__DDR_D_6,
+ VF610_PAD_DDR_D5__DDR_D_5,
+ VF610_PAD_DDR_D4__DDR_D_4,
+ VF610_PAD_DDR_D3__DDR_D_3,
+ VF610_PAD_DDR_D2__DDR_D_2,
+ VF610_PAD_DDR_D1__DDR_D_1,
+ VF610_PAD_DDR_D0__DDR_D_0,
+ VF610_PAD_DDR_DQM1__DDR_DQM_1,
+ VF610_PAD_DDR_DQM0__DDR_DQM_0,
+ VF610_PAD_DDR_DQS1__DDR_DQS_1,
+ VF610_PAD_DDR_DQS0__DDR_DQS_0,
+ VF610_PAD_DDR_RAS__DDR_RAS_B,
+ VF610_PAD_DDR_WE__DDR_WE_B,
+ VF610_PAD_DDR_ODT1__DDR_ODT_0,
+ VF610_PAD_DDR_ODT0__DDR_ODT_1,
+ VF610_PAD_DDR_RESETB,
+ };
+
+ if ((pads == NULL) || (pads_count == 0)) {
+ pads = default_pads;
+ pads_count = ARRAY_SIZE(default_pads);
+ }
+
+ imx_iomux_v3_setup_multiple_pads(pads, pads_count);
+}
+
+static struct ddrmc_phy_setting default_phy_settings[] = {
+ { DDRMC_PHY_DQ_TIMING, 0 },
+ { DDRMC_PHY_DQ_TIMING, 16 },
+ { DDRMC_PHY_DQ_TIMING, 32 },
+
+ { DDRMC_PHY_DQS_TIMING, 1 },
+ { DDRMC_PHY_DQS_TIMING, 17 },
+
+ { DDRMC_PHY_CTRL, 2 },
+ { DDRMC_PHY_CTRL, 18 },
+ { DDRMC_PHY_CTRL, 34 },
+
+ { DDRMC_PHY_MASTER_CTRL, 3 },
+ { DDRMC_PHY_MASTER_CTRL, 19 },
+ { DDRMC_PHY_MASTER_CTRL, 35 },
+
+ { DDRMC_PHY_SLAVE_CTRL, 4 },
+ { DDRMC_PHY_SLAVE_CTRL, 20 },
+ { DDRMC_PHY_SLAVE_CTRL, 36 },
+
+ /* LPDDR2 only parameter */
+ { DDRMC_PHY_OFF, 49 },
+
+ { DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, 50 },
+
+ /* Processor Pad ODT settings */
+ { DDRMC_PHY_PROC_PAD_ODT, 52 },
+
+ /* end marker */
+ { 0, -1 }
+};
+
+void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
+ struct ddrmc_cr_setting *board_cr_settings,
+ struct ddrmc_phy_setting *board_phy_settings,
+ int col_diff, int row_diff)
+{
+ struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
+ struct ddrmc_cr_setting *cr_setting;
+ struct ddrmc_phy_setting *phy_setting;
+
+ writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]);
+ writel(DDRMC_CR02_DRAM_TINIT(timings->tinit), &ddrmr->cr[2]);
+ writel(DDRMC_CR10_TRST_PWRON(timings->trst_pwron), &ddrmr->cr[10]);
+
+ writel(DDRMC_CR11_CKE_INACTIVE(timings->cke_inactive), &ddrmr->cr[11]);
+ writel(DDRMC_CR12_WRLAT(timings->wrlat) |
+ DDRMC_CR12_CASLAT_LIN(timings->caslat_lin), &ddrmr->cr[12]);
+ writel(DDRMC_CR13_TRC(timings->trc) | DDRMC_CR13_TRRD(timings->trrd) |
+ DDRMC_CR13_TCCD(timings->tccd) |
+ DDRMC_CR13_TBST_INT_INTERVAL(timings->tbst_int_interval),
+ &ddrmr->cr[13]);
+ writel(DDRMC_CR14_TFAW(timings->tfaw) | DDRMC_CR14_TRP(timings->trp) |
+ DDRMC_CR14_TWTR(timings->twtr) |
+ DDRMC_CR14_TRAS_MIN(timings->tras_min), &ddrmr->cr[14]);
+ writel(DDRMC_CR16_TMRD(timings->tmrd) |
+ DDRMC_CR16_TRTP(timings->trtp), &ddrmr->cr[16]);
+ writel(DDRMC_CR17_TRAS_MAX(timings->tras_max) |
+ DDRMC_CR17_TMOD(timings->tmod), &ddrmr->cr[17]);
+ writel(DDRMC_CR18_TCKESR(timings->tckesr) |
+ DDRMC_CR18_TCKE(timings->tcke), &ddrmr->cr[18]);
+
+ writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]);
+ writel(DDRMC_CR21_TRCD_INT(timings->trcd_int) | DDRMC_CR21_CCMAP_EN |
+ DDRMC_CR21_TRAS_LOCKOUT(timings->tras_lockout),
+ &ddrmr->cr[21]);
+
+ writel(DDRMC_CR22_TDAL(timings->tdal), &ddrmr->cr[22]);
+ writel(DDRMC_CR23_BSTLEN(timings->bstlen) |
+ DDRMC_CR23_TDLL(timings->tdll), &ddrmr->cr[23]);
+ writel(DDRMC_CR24_TRP_AB(timings->trp_ab), &ddrmr->cr[24]);
+
+ writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]);
+ writel(DDRMC_CR26_TREF(timings->tref) |
+ DDRMC_CR26_TRFC(timings->trfc), &ddrmr->cr[26]);
+ writel(DDRMC_CR28_TREF_INT(timings->tref_int), &ddrmr->cr[28]);
+ writel(DDRMC_CR29_TPDEX(timings->tpdex), &ddrmr->cr[29]);
+
+ writel(DDRMC_CR30_TXPDLL(timings->txpdll), &ddrmr->cr[30]);
+ writel(DDRMC_CR31_TXSNR(timings->txsnr) |
+ DDRMC_CR31_TXSR(timings->txsr), &ddrmr->cr[31]);
+ writel(DDRMC_CR33_EN_QK_SREF, &ddrmr->cr[33]);
+ writel(DDRMC_CR34_CKSRX(timings->cksrx) |
+ DDRMC_CR34_CKSRE(timings->cksre), &ddrmr->cr[34]);
+
+ writel(DDRMC_CR38_FREQ_CHG_EN(timings->freq_chg_en), &ddrmr->cr[38]);
+ writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) |
+ DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]);
+
+ writel(DDRMC_CR41_PHY_INI_STRT_INI_DIS, &ddrmr->cr[41]);
+ writel(DDRMC_CR48_MR1_DA_0(70) |
+ DDRMC_CR48_MR0_DA_0(1056), &ddrmr->cr[48]);
+
+ writel(DDRMC_CR66_ZQCL(timings->zqcl) |
+ DDRMC_CR66_ZQINIT(timings->zqinit), &ddrmr->cr[66]);
+ writel(DDRMC_CR67_ZQCS(timings->zqcs), &ddrmr->cr[67]);
+ writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]);
+
+ writel(DDRMC_CR70_REF_PER_ZQ(timings->ref_per_zq), &ddrmr->cr[70]);
+ writel(DDRMC_CR72_ZQCS_ROTATE(timings->zqcs_rotate), &ddrmr->cr[72]);
+
+ writel(DDRMC_CR73_APREBIT(timings->aprebit) |
+ DDRMC_CR73_COL_DIFF(col_diff) |
+ DDRMC_CR73_ROW_DIFF(row_diff), &ddrmr->cr[73]);
+ writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN |
+ DDRMC_CR74_CMD_AGE_CNT(timings->cmd_age_cnt) |
+ DDRMC_CR74_AGE_CNT(timings->age_cnt),
+ &ddrmr->cr[74]);
+ writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN |
+ DDRMC_CR75_PLEN, &ddrmr->cr[75]);
+ writel(DDRMC_CR76_NQENT_ACTDIS(3) | DDRMC_CR76_D_RW_G_BKCN(3) |
+ DDRMC_CR76_W2R_SPLT_EN, &ddrmr->cr[76]);
+ writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE |
+ DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]);
+ writel(DDRMC_CR78_Q_FULLNESS(timings->q_fullness) |
+ DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]);
+ writel(DDRMC_CR79_CTLUPD_AREF(0), &ddrmr->cr[79]);
+
+ writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
+
+ writel(DDRMC_CR87_ODT_RD_MAPCS0(timings->odt_rd_mapcs0) |
+ DDRMC_CR87_ODT_WR_MAPCS0(timings->odt_wr_mapcs0),
+ &ddrmr->cr[87]);
+ writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]);
+ writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]);
+
+ writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr->cr[91]);
+ writel(DDRMC_CR96_WLMRD(timings->wlmrd) |
+ DDRMC_CR96_WLDQSEN(timings->wldqsen), &ddrmr->cr[96]);
+
+ /* execute custom CR setting sequence (may be NULL) */
+ cr_setting = board_cr_settings;
+ if (cr_setting != NULL)
+ while (cr_setting->cr_rnum >= 0) {
+ writel(cr_setting->setting,
+ &ddrmr->cr[cr_setting->cr_rnum]);
+ cr_setting++;
+ }
+
+ /* perform default PHY settings (may be overridden by custom settings */
+ phy_setting = default_phy_settings;
+ while (phy_setting->phy_rnum >= 0) {
+ writel(phy_setting->setting,
+ &ddrmr->phy[phy_setting->phy_rnum]);
+ phy_setting++;
+ }
+
+ /* execute custom PHY setting sequence (may be NULL) */
+ phy_setting = board_phy_settings;
+ if (phy_setting != NULL)
+ while (phy_setting->phy_rnum >= 0) {
+ writel(phy_setting->setting,
+ &ddrmr->phy[phy_setting->phy_rnum]);
+ phy_setting++;
+ }
+
+ /* all inits done, start the DDR controller */
+ writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]);
+
+ while (!(readl(&ddrmr->cr[80]) && 0x100))
+ udelay(10);
+}
--- /dev/null
+/*
+ * Copyright (C) 2010-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <fuse.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/hab.h>
+
+/* -------- start of HAB API updates ------------*/
+
+#define hab_rvt_report_event_p \
+( \
+ (is_mx6dqp()) ? \
+ ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \
+ (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \
+ ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \
+ (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
+ ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \
+ ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT) \
+)
+
+#define hab_rvt_report_status_p \
+( \
+ (is_mx6dqp()) ? \
+ ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
+ (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \
+ ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
+ (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
+ ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
+ ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS) \
+)
+
+#define hab_rvt_authenticate_image_p \
+( \
+ (is_mx6dqp()) ? \
+ ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
+ (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \
+ ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
+ (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
+ ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
+ ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE) \
+)
+
+#define hab_rvt_entry_p \
+( \
+ (is_mx6dqp()) ? \
+ ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \
+ (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \
+ ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \
+ (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
+ ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \
+ ((hab_rvt_entry_t *)HAB_RVT_ENTRY) \
+)
+
+#define hab_rvt_exit_p \
+( \
+ (is_mx6dqp()) ? \
+ ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \
+ (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \
+ ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \
+ (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
+ ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \
+ ((hab_rvt_exit_t *)HAB_RVT_EXIT) \
+)
+
+#define IVT_SIZE 0x20
+#define ALIGN_SIZE 0x1000
+#define CSF_PAD_SIZE 0x2000
+#define MX6DQ_PU_IROM_MMU_EN_VAR 0x009024a8
+#define MX6DLS_PU_IROM_MMU_EN_VAR 0x00901dd0
+#define MX6SL_PU_IROM_MMU_EN_VAR 0x00900a18
+#define IS_HAB_ENABLED_BIT \
+ (is_soc_type(MXC_SOC_MX7ULP) ? 0x80000000 : \
+ (is_soc_type(MXC_SOC_MX7) ? 0x2000000 : 0x2))
+
+/*
+ * +------------+ 0x0 (DDR_UIMAGE_START) -
+ * | Header | |
+ * +------------+ 0x40 |
+ * | | |
+ * | | |
+ * | | |
+ * | | |
+ * | Image Data | |
+ * . | |
+ * . | > Stuff to be authenticated ----+
+ * . | | |
+ * | | | |
+ * | | | |
+ * +------------+ | |
+ * | | | |
+ * | Fill Data | | |
+ * | | | |
+ * +------------+ Align to ALIGN_SIZE | |
+ * | IVT | | |
+ * +------------+ + IVT_SIZE - |
+ * | | |
+ * | CSF DATA | <---------------------------------------------------------+
+ * | |
+ * +------------+
+ * | |
+ * | Fill Data |
+ * | |
+ * +------------+ + CSF_PAD_SIZE
+ */
+
+static bool is_hab_enabled(void);
+
+#if !defined(CONFIG_SPL_BUILD)
+
+#define MAX_RECORD_BYTES (8*1024) /* 4 kbytes */
+
+struct record {
+ uint8_t tag; /* Tag */
+ uint8_t len[2]; /* Length */
+ uint8_t par; /* Version */
+ uint8_t contents[MAX_RECORD_BYTES];/* Record Data */
+ bool any_rec_flag;
+};
+
+char *rsn_str[] = {"RSN = HAB_RSN_ANY (0x00)\n",
+ "RSN = HAB_ENG_FAIL (0x30)\n",
+ "RSN = HAB_INV_ADDRESS (0x22)\n",
+ "RSN = HAB_INV_ASSERTION (0x0C)\n",
+ "RSN = HAB_INV_CALL (0x28)\n",
+ "RSN = HAB_INV_CERTIFICATE (0x21)\n",
+ "RSN = HAB_INV_COMMAND (0x06)\n",
+ "RSN = HAB_INV_CSF (0x11)\n",
+ "RSN = HAB_INV_DCD (0x27)\n",
+ "RSN = HAB_INV_INDEX (0x0F)\n",
+ "RSN = HAB_INV_IVT (0x05)\n",
+ "RSN = HAB_INV_KEY (0x1D)\n",
+ "RSN = HAB_INV_RETURN (0x1E)\n",
+ "RSN = HAB_INV_SIGNATURE (0x18)\n",
+ "RSN = HAB_INV_SIZE (0x17)\n",
+ "RSN = HAB_MEM_FAIL (0x2E)\n",
+ "RSN = HAB_OVR_COUNT (0x2B)\n",
+ "RSN = HAB_OVR_STORAGE (0x2D)\n",
+ "RSN = HAB_UNS_ALGORITHM (0x12)\n",
+ "RSN = HAB_UNS_COMMAND (0x03)\n",
+ "RSN = HAB_UNS_ENGINE (0x0A)\n",
+ "RSN = HAB_UNS_ITEM (0x24)\n",
+ "RSN = HAB_UNS_KEY (0x1B)\n",
+ "RSN = HAB_UNS_PROTOCOL (0x14)\n",
+ "RSN = HAB_UNS_STATE (0x09)\n",
+ "RSN = INVALID\n",
+ NULL};
+
+char *sts_str[] = {"STS = HAB_SUCCESS (0xF0)\n",
+ "STS = HAB_FAILURE (0x33)\n",
+ "STS = HAB_WARNING (0x69)\n",
+ "STS = INVALID\n",
+ NULL};
+
+char *eng_str[] = {"ENG = HAB_ENG_ANY (0x00)\n",
+ "ENG = HAB_ENG_SCC (0x03)\n",
+ "ENG = HAB_ENG_RTIC (0x05)\n",
+ "ENG = HAB_ENG_SAHARA (0x06)\n",
+ "ENG = HAB_ENG_CSU (0x0A)\n",
+ "ENG = HAB_ENG_SRTC (0x0C)\n",
+ "ENG = HAB_ENG_DCP (0x1B)\n",
+ "ENG = HAB_ENG_CAAM (0x1D)\n",
+ "ENG = HAB_ENG_SNVS (0x1E)\n",
+ "ENG = HAB_ENG_OCOTP (0x21)\n",
+ "ENG = HAB_ENG_DTCP (0x22)\n",
+ "ENG = HAB_ENG_ROM (0x36)\n",
+ "ENG = HAB_ENG_HDCP (0x24)\n",
+ "ENG = HAB_ENG_RTL (0x77)\n",
+ "ENG = HAB_ENG_SW (0xFF)\n",
+ "ENG = INVALID\n",
+ NULL};
+
+char *ctx_str[] = {"CTX = HAB_CTX_ANY(0x00)\n",
+ "CTX = HAB_CTX_FAB (0xFF)\n",
+ "CTX = HAB_CTX_ENTRY (0xE1)\n",
+ "CTX = HAB_CTX_TARGET (0x33)\n",
+ "CTX = HAB_CTX_AUTHENTICATE (0x0A)\n",
+ "CTX = HAB_CTX_DCD (0xDD)\n",
+ "CTX = HAB_CTX_CSF (0xCF)\n",
+ "CTX = HAB_CTX_COMMAND (0xC0)\n",
+ "CTX = HAB_CTX_AUT_DAT (0xDB)\n",
+ "CTX = HAB_CTX_ASSERT (0xA0)\n",
+ "CTX = HAB_CTX_EXIT (0xEE)\n",
+ "CTX = INVALID\n",
+ NULL};
+
+uint8_t hab_statuses[5] = {
+ HAB_STS_ANY,
+ HAB_FAILURE,
+ HAB_WARNING,
+ HAB_SUCCESS,
+ -1
+};
+
+uint8_t hab_reasons[26] = {
+ HAB_RSN_ANY,
+ HAB_ENG_FAIL,
+ HAB_INV_ADDRESS,
+ HAB_INV_ASSERTION,
+ HAB_INV_CALL,
+ HAB_INV_CERTIFICATE,
+ HAB_INV_COMMAND,
+ HAB_INV_CSF,
+ HAB_INV_DCD,
+ HAB_INV_INDEX,
+ HAB_INV_IVT,
+ HAB_INV_KEY,
+ HAB_INV_RETURN,
+ HAB_INV_SIGNATURE,
+ HAB_INV_SIZE,
+ HAB_MEM_FAIL,
+ HAB_OVR_COUNT,
+ HAB_OVR_STORAGE,
+ HAB_UNS_ALGORITHM,
+ HAB_UNS_COMMAND,
+ HAB_UNS_ENGINE,
+ HAB_UNS_ITEM,
+ HAB_UNS_KEY,
+ HAB_UNS_PROTOCOL,
+ HAB_UNS_STATE,
+ -1
+};
+
+uint8_t hab_contexts[12] = {
+ HAB_CTX_ANY,
+ HAB_CTX_FAB,
+ HAB_CTX_ENTRY,
+ HAB_CTX_TARGET,
+ HAB_CTX_AUTHENTICATE,
+ HAB_CTX_DCD,
+ HAB_CTX_CSF,
+ HAB_CTX_COMMAND,
+ HAB_CTX_AUT_DAT,
+ HAB_CTX_ASSERT,
+ HAB_CTX_EXIT,
+ -1
+};
+
+uint8_t hab_engines[16] = {
+ HAB_ENG_ANY,
+ HAB_ENG_SCC,
+ HAB_ENG_RTIC,
+ HAB_ENG_SAHARA,
+ HAB_ENG_CSU,
+ HAB_ENG_SRTC,
+ HAB_ENG_DCP,
+ HAB_ENG_CAAM,
+ HAB_ENG_SNVS,
+ HAB_ENG_OCOTP,
+ HAB_ENG_DTCP,
+ HAB_ENG_ROM,
+ HAB_ENG_HDCP,
+ HAB_ENG_RTL,
+ HAB_ENG_SW,
+ -1
+};
+
+static inline uint8_t get_idx(uint8_t *list, uint8_t tgt)
+{
+ uint8_t idx = 0;
+ uint8_t element = list[idx];
+ while (element != -1) {
+ if (element == tgt)
+ return idx;
+ element = list[++idx];
+ }
+ return -1;
+}
+
+void process_event_record(uint8_t *event_data, size_t bytes)
+{
+ struct record *rec = (struct record *)event_data;
+
+ printf("\n\n%s", sts_str[get_idx(hab_statuses, rec->contents[0])]);
+ printf("%s", rsn_str[get_idx(hab_reasons, rec->contents[1])]);
+ printf("%s", ctx_str[get_idx(hab_contexts, rec->contents[2])]);
+ printf("%s", eng_str[get_idx(hab_engines, rec->contents[3])]);
+}
+
+void display_event(uint8_t *event_data, size_t bytes)
+{
+ uint32_t i;
+
+ if (!(event_data && bytes > 0))
+ return;
+
+ for (i = 0; i < bytes; i++) {
+ if (i == 0)
+ printf("\t0x%02x", event_data[i]);
+ else if ((i % 8) == 0)
+ printf("\n\t0x%02x", event_data[i]);
+ else
+ printf(" 0x%02x", event_data[i]);
+ }
+
+ process_event_record(event_data, bytes);
+}
+
+int get_hab_status(void)
+{
+ uint32_t index = 0; /* Loop index */
+ uint8_t event_data[128]; /* Event data buffer */
+ size_t bytes = sizeof(event_data); /* Event size in bytes */
+ enum hab_config config = 0;
+ enum hab_state state = 0;
+ hab_rvt_report_event_t *hab_rvt_report_event;
+ hab_rvt_report_status_t *hab_rvt_report_status;
+
+ hab_rvt_report_event = hab_rvt_report_event_p;
+ hab_rvt_report_status = hab_rvt_report_status_p;
+
+ if (is_hab_enabled())
+ puts("\nSecure boot enabled\n");
+ else
+ puts("\nSecure boot disabled\n");
+
+ /* Check HAB status */
+ if (hab_rvt_report_status(&config, &state) != HAB_SUCCESS) {
+ printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n",
+ config, state);
+
+ /* Display HAB Error events */
+ while (hab_rvt_report_event(HAB_FAILURE, index, event_data,
+ &bytes) == HAB_SUCCESS) {
+ puts("\n");
+ printf("--------- HAB Event %d -----------------\n",
+ index + 1);
+ puts("event data:\n");
+ display_event(event_data, bytes);
+ puts("\n");
+ bytes = sizeof(event_data);
+ index++;
+ }
+ }
+ /* Display message if no HAB events are found */
+ else {
+ printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n",
+ config, state);
+ puts("No HAB Events Found!\n\n");
+ }
+ return 0;
+}
+
+int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ if ((argc != 1)) {
+ cmd_usage(cmdtp);
+ return 1;
+ }
+
+ get_hab_status();
+
+ return 0;
+}
+
+static int do_authenticate_image(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ ulong addr, ivt_offset;
+ int rcode = 0;
+
+ if (argc < 3)
+ return CMD_RET_USAGE;
+
+ addr = simple_strtoul(argv[1], NULL, 16);
+ ivt_offset = simple_strtoul(argv[2], NULL, 16);
+
+ rcode = authenticate_image(addr, ivt_offset);
+
+ return rcode;
+}
+
+U_BOOT_CMD(
+ hab_status, CONFIG_SYS_MAXARGS, 1, do_hab_status,
+ "display HAB status",
+ ""
+ );
+
+U_BOOT_CMD(
+ hab_auth_img, 3, 0, do_authenticate_image,
+ "authenticate image via HAB",
+ "addr ivt_offset\n"
+ "addr - image hex address\n"
+ "ivt_offset - hex offset of IVT in the image"
+ );
+
+
+#endif /* !defined(CONFIG_SPL_BUILD) */
+
+static bool is_hab_enabled(void)
+{
+ struct imx_sec_config_fuse_t *fuse =
+ (struct imx_sec_config_fuse_t *)&imx_sec_config_fuse;
+ uint32_t reg;
+ int ret;
+
+ ret = fuse_read(fuse->bank, fuse->word, ®);
+ if (ret) {
+ puts("\nSecure boot fuse read error\n");
+ return ret;
+ }
+
+ return (reg & IS_HAB_ENABLED_BIT) == IS_HAB_ENABLED_BIT;
+}
+
+uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size)
+{
+ uint32_t load_addr = 0;
+ size_t bytes;
+ ptrdiff_t ivt_offset = 0;
+ int result = 0;
+ ulong start;
+ hab_rvt_authenticate_image_t *hab_rvt_authenticate_image;
+ hab_rvt_entry_t *hab_rvt_entry;
+ hab_rvt_exit_t *hab_rvt_exit;
+
+ hab_rvt_authenticate_image = hab_rvt_authenticate_image_p;
+ hab_rvt_entry = hab_rvt_entry_p;
+ hab_rvt_exit = hab_rvt_exit_p;
+
+ if (is_hab_enabled()) {
+ printf("\nAuthenticate image from DDR location 0x%x...\n",
+ ddr_start);
+
+ hab_caam_clock_enable(1);
+
+ if (hab_rvt_entry() == HAB_SUCCESS) {
+ /* If not already aligned, Align to ALIGN_SIZE */
+ ivt_offset = (image_size + ALIGN_SIZE - 1) &
+ ~(ALIGN_SIZE - 1);
+
+ start = ddr_start;
+ bytes = ivt_offset + IVT_SIZE + CSF_PAD_SIZE;
+#ifdef DEBUG
+ printf("\nivt_offset = 0x%x, ivt addr = 0x%x\n",
+ ivt_offset, ddr_start + ivt_offset);
+ puts("Dumping IVT\n");
+ print_buffer(ddr_start + ivt_offset,
+ (void *)(ddr_start + ivt_offset),
+ 4, 0x8, 0);
+
+ puts("Dumping CSF Header\n");
+ print_buffer(ddr_start + ivt_offset+IVT_SIZE,
+ (void *)(ddr_start + ivt_offset+IVT_SIZE),
+ 4, 0x10, 0);
+
+#if !defined(CONFIG_SPL_BUILD)
+ get_hab_status();
+#endif
+
+ puts("\nCalling authenticate_image in ROM\n");
+ printf("\tivt_offset = 0x%x\n", ivt_offset);
+ printf("\tstart = 0x%08lx\n", start);
+ printf("\tbytes = 0x%x\n", bytes);
+#endif
+ /*
+ * If the MMU is enabled, we have to notify the ROM
+ * code, or it won't flush the caches when needed.
+ * This is done, by setting the "pu_irom_mmu_enabled"
+ * word to 1. You can find its address by looking in
+ * the ROM map. This is critical for
+ * authenticate_image(). If MMU is enabled, without
+ * setting this bit, authentication will fail and may
+ * crash.
+ */
+ /* Check MMU enabled */
+ if (is_soc_type(MXC_SOC_MX6) && get_cr() & CR_M) {
+ if (is_mx6dq()) {
+ /*
+ * This won't work on Rev 1.0.0 of
+ * i.MX6Q/D, since their ROM doesn't
+ * do cache flushes. don't think any
+ * exist, so we ignore them.
+ */
+ if (!is_mx6dqp())
+ writel(1, MX6DQ_PU_IROM_MMU_EN_VAR);
+ } else if (is_mx6sdl()) {
+ writel(1, MX6DLS_PU_IROM_MMU_EN_VAR);
+ } else if (is_mx6sl()) {
+ writel(1, MX6SL_PU_IROM_MMU_EN_VAR);
+ }
+ }
+
+ load_addr = (uint32_t)hab_rvt_authenticate_image(
+ HAB_CID_UBOOT,
+ ivt_offset, (void **)&start,
+ (size_t *)&bytes, NULL);
+ if (hab_rvt_exit() != HAB_SUCCESS) {
+ puts("hab exit function fail\n");
+ load_addr = 0;
+ }
+ } else {
+ puts("hab entry function fail\n");
+ }
+
+ hab_caam_clock_enable(0);
+
+#if !defined(CONFIG_SPL_BUILD)
+ get_hab_status();
+#endif
+ } else {
+ puts("hab fuse not enabled\n");
+ }
+
+ if ((!is_hab_enabled()) || (load_addr != 0))
+ result = 1;
+
+ return result;
+}
--- /dev/null
+/*
+ * Copyright (C) 2012 Boundary Devices Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <malloc.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <linux/errno.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <watchdog.h>
+
+int force_idle_bus(void *priv)
+{
+ int i;
+ int sda, scl;
+ ulong elapsed, start_time;
+ struct i2c_pads_info *p = (struct i2c_pads_info *)priv;
+ int ret = 0;
+
+ gpio_direction_input(p->sda.gp);
+ gpio_direction_input(p->scl.gp);
+
+ imx_iomux_v3_setup_pad(p->sda.gpio_mode);
+ imx_iomux_v3_setup_pad(p->scl.gpio_mode);
+
+ sda = gpio_get_value(p->sda.gp);
+ scl = gpio_get_value(p->scl.gp);
+ if ((sda & scl) == 1)
+ goto exit; /* Bus is idle already */
+
+ printf("%s: sda=%d scl=%d sda.gp=0x%x scl.gp=0x%x\n", __func__,
+ sda, scl, p->sda.gp, p->scl.gp);
+ /* Send high and low on the SCL line */
+ for (i = 0; i < 9; i++) {
+ gpio_direction_output(p->scl.gp, 0);
+ udelay(50);
+ gpio_direction_input(p->scl.gp);
+ udelay(50);
+ }
+ start_time = get_timer(0);
+ for (;;) {
+ sda = gpio_get_value(p->sda.gp);
+ scl = gpio_get_value(p->scl.gp);
+ if ((sda & scl) == 1)
+ break;
+ WATCHDOG_RESET();
+ elapsed = get_timer(start_time);
+ if (elapsed > (CONFIG_SYS_HZ / 5)) { /* .2 seconds */
+ ret = -EBUSY;
+ printf("%s: failed to clear bus, sda=%d scl=%d\n",
+ __func__, sda, scl);
+ break;
+ }
+ }
+exit:
+ imx_iomux_v3_setup_pad(p->sda.i2c_mode);
+ imx_iomux_v3_setup_pad(p->scl.i2c_mode);
+ return ret;
+}
+
+static void * const i2c_bases[] = {
+ (void *)I2C1_BASE_ADDR,
+ (void *)I2C2_BASE_ADDR,
+#ifdef I2C3_BASE_ADDR
+ (void *)I2C3_BASE_ADDR,
+#endif
+#ifdef I2C4_BASE_ADDR
+ (void *)I2C4_BASE_ADDR,
+#endif
+};
+
+/* i2c_index can be from 0 - 3 */
+int setup_i2c(unsigned i2c_index, int speed, int slave_addr,
+ struct i2c_pads_info *p)
+{
+ char name[9];
+ int ret;
+
+ if (i2c_index >= ARRAY_SIZE(i2c_bases))
+ return -EINVAL;
+
+ snprintf(name, sizeof(name), "i2c_sda%01d", i2c_index);
+ ret = gpio_request(p->sda.gp, name);
+ if (ret)
+ return ret;
+
+ snprintf(name, sizeof(name), "i2c_scl%01d", i2c_index);
+ ret = gpio_request(p->scl.gp, name);
+ if (ret)
+ goto err_req;
+
+ /* Enable i2c clock */
+ ret = enable_i2c_clk(1, i2c_index);
+ if (ret)
+ goto err_clk;
+
+ /* Make sure bus is idle */
+ ret = force_idle_bus(p);
+ if (ret)
+ goto err_idle;
+
+#ifndef CONFIG_DM_I2C
+ bus_i2c_init(i2c_index, speed, slave_addr, force_idle_bus, p);
+#endif
+
+ return 0;
+
+err_idle:
+err_clk:
+ gpio_free(p->scl.gp);
+err_req:
+ gpio_free(p->sda.gp);
+
+ return ret;
+}
--- /dev/null
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+
+/* Allow for arch specific config before we boot */
+static int __arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
+{
+ /* please define platform specific arch_auxiliary_core_up() */
+ return CMD_RET_FAILURE;
+}
+
+int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
+ __attribute__((weak, alias("__arch_auxiliary_core_up")));
+
+/* Allow for arch specific config before we boot */
+static int __arch_auxiliary_core_check_up(u32 core_id)
+{
+ /* please define platform specific arch_auxiliary_core_check_up() */
+ return 0;
+}
+
+int arch_auxiliary_core_check_up(u32 core_id)
+ __attribute__((weak, alias("__arch_auxiliary_core_check_up")));
+
+/*
+ * To i.MX6SX and i.MX7D, the image supported by bootaux needs
+ * the reset vector at the head for the image, with SP and PC
+ * as the first two words.
+ *
+ * Per the cortex-M reference manual, the reset vector of M4 needs
+ * to exist at 0x0 (TCMUL). The PC and SP are the first two addresses
+ * of that vector. So to boot M4, the A core must build the M4's reset
+ * vector with getting the PC and SP from image and filling them to
+ * TCMUL. When M4 is kicked, it will load the PC and SP by itself.
+ * The TCMUL is mapped to (M4_BOOTROM_BASE_ADDR) at A core side for
+ * accessing the M4 TCMUL.
+ */
+int do_bootaux(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ ulong addr;
+ int ret, up;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ up = arch_auxiliary_core_check_up(0);
+ if (up) {
+ printf("## Auxiliary core is already up\n");
+ return CMD_RET_SUCCESS;
+ }
+
+ addr = simple_strtoul(argv[1], NULL, 16);
+
+ printf("## Starting auxiliary core at 0x%08lX ...\n", addr);
+
+ ret = arch_auxiliary_core_up(0, addr);
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+ bootaux, CONFIG_SYS_MAXARGS, 1, do_bootaux,
+ "Start auxiliary core",
+ ""
+);
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/arch/crm_regs.h>
+
+void init_aips(void)
+{
+ struct aipstz_regs *aips1, *aips2, *aips3;
+
+ aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
+ aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
+ aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
+
+ /*
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+ writel(0x77777777, &aips1->mprot0);
+ writel(0x77777777, &aips1->mprot1);
+ writel(0x77777777, &aips2->mprot0);
+ writel(0x77777777, &aips2->mprot1);
+
+ /*
+ * Set all OPACRx to be non-bufferable, not require
+ * supervisor privilege level for access,allow for
+ * write access and untrusted master access.
+ */
+ writel(0x00000000, &aips1->opacr0);
+ writel(0x00000000, &aips1->opacr1);
+ writel(0x00000000, &aips1->opacr2);
+ writel(0x00000000, &aips1->opacr3);
+ writel(0x00000000, &aips1->opacr4);
+ writel(0x00000000, &aips2->opacr0);
+ writel(0x00000000, &aips2->opacr1);
+ writel(0x00000000, &aips2->opacr2);
+ writel(0x00000000, &aips2->opacr3);
+ writel(0x00000000, &aips2->opacr4);
+
+ if (is_mx6ull() || is_mx6sx() || is_mx7()) {
+ /*
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+ writel(0x77777777, &aips3->mprot0);
+ writel(0x77777777, &aips3->mprot1);
+
+ /*
+ * Set all OPACRx to be non-bufferable, not require
+ * supervisor privilege level for access,allow for
+ * write access and untrusted master access.
+ */
+ writel(0x00000000, &aips3->opacr0);
+ writel(0x00000000, &aips3->opacr1);
+ writel(0x00000000, &aips3->opacr2);
+ writel(0x00000000, &aips3->opacr3);
+ writel(0x00000000, &aips3->opacr4);
+ }
+}
+
+void imx_set_wdog_powerdown(bool enable)
+{
+ struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
+ struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
+ struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
+#ifdef CONFIG_MX7D
+ struct wdog_regs *wdog4 = (struct wdog_regs *)WDOG4_BASE_ADDR;
+#endif
+
+ /* Write to the PDE (Power Down Enable) bit */
+ writew(enable, &wdog1->wmcr);
+ writew(enable, &wdog2->wmcr);
+
+ if (is_mx6sx() || is_mx6ul() || is_mx7())
+ writew(enable, &wdog3->wmcr);
+#ifdef CONFIG_MX7D
+ writew(enable, &wdog4->wmcr);
+#endif
+}
+
+#define SRC_SCR_WARM_RESET_ENABLE 0
+
+void init_src(void)
+{
+ struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+ u32 val;
+
+ /*
+ * force warm reset sources to generate cold reset
+ * for a more reliable restart
+ */
+ val = readl(&src_regs->scr);
+ val &= ~(1 << SRC_SCR_WARM_RESET_ENABLE);
+ writel(val, &src_regs->scr);
+}
+
+#ifdef CONFIG_CMD_BMODE
+void boot_mode_apply(unsigned cfg_val)
+{
+ unsigned reg;
+ struct src *psrc = (struct src *)SRC_BASE_ADDR;
+ writel(cfg_val, &psrc->gpr9);
+ reg = readl(&psrc->gpr10);
+ if (cfg_val)
+ reg |= 1 << 28;
+ else
+ reg &= ~(1 << 28);
+ writel(reg, &psrc->gpr10);
+}
+#endif
+
+#if defined(CONFIG_MX6)
+u32 imx6_src_get_boot_mode(void)
+{
+ if (imx6_is_bmode_from_gpr9())
+ return readl(&src_base->gpr9);
+ else
+ return readl(&src_base->sbmr1);
+}
+#endif
--- /dev/null
+/*
+ * Based on the iomux-v3.c from Linux kernel:
+ * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
+ * <armlinux@phytec.de>
+ *
+ * Copyright (C) 2004-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/sys_proto.h>
+
+static void *base = (void *)IOMUXC_BASE_ADDR;
+
+/*
+ * configures a single pad in the iomuxer
+ */
+void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
+{
+ u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
+ u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
+ u32 sel_input_ofs =
+ (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
+ u32 sel_input =
+ (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
+ u32 pad_ctrl_ofs =
+ (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
+ u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
+
+#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
+ /* Check whether LVE bit needs to be set */
+ if (pad_ctrl & PAD_CTL_LVE) {
+ pad_ctrl &= ~PAD_CTL_LVE;
+ pad_ctrl |= PAD_CTL_LVE_BIT;
+ }
+#endif
+
+#ifdef CONFIG_IOMUX_LPSR
+ u32 lpsr = (pad & MUX_MODE_LPSR) >> MUX_MODE_SHIFT;
+
+#ifdef CONFIG_MX7
+ if (lpsr == IOMUX_CONFIG_LPSR) {
+ base = (void *)IOMUXC_LPSR_BASE_ADDR;
+ mux_mode &= ~IOMUX_CONFIG_LPSR;
+ /* set daisy chain sel_input */
+ if (sel_input_ofs)
+ sel_input_ofs += IOMUX_LPSR_SEL_INPUT_OFS;
+ }
+#else
+ if (is_mx6ull() || is_mx6sll()) {
+ if (lpsr == IOMUX_CONFIG_LPSR) {
+ base = (void *)IOMUXC_SNVS_BASE_ADDR;
+ mux_mode &= ~IOMUX_CONFIG_LPSR;
+ }
+ }
+#endif
+#endif
+
+ if (is_mx7() || is_mx6ull() || is_mx6sll() || mux_ctrl_ofs)
+ __raw_writel(mux_mode, base + mux_ctrl_ofs);
+
+ if (sel_input_ofs)
+ __raw_writel(sel_input, base + sel_input_ofs);
+
+#ifdef CONFIG_IOMUX_SHARE_CONF_REG
+ if (!(pad_ctrl & NO_PAD_CTRL))
+ __raw_writel((mux_mode << PAD_MUX_MODE_SHIFT) | pad_ctrl,
+ base + pad_ctrl_ofs);
+#else
+ if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
+ __raw_writel(pad_ctrl, base + pad_ctrl_ofs);
+#if defined(CONFIG_MX6SLL)
+ else if ((pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
+ clrbits_le32(base + pad_ctrl_ofs, PAD_CTL_IPD_BIT);
+#endif
+#endif
+
+#ifdef CONFIG_IOMUX_LPSR
+ if (lpsr == IOMUX_CONFIG_LPSR)
+ base = (void *)IOMUXC_BASE_ADDR;
+#endif
+
+}
+
+/* configures a list of pads within declared with IOMUX_PADS macro */
+void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
+ unsigned count)
+{
+ iomux_v3_cfg_t const *p = pad_list;
+ int stride;
+ int i;
+
+#if defined(CONFIG_MX6QDL)
+ stride = 2;
+ if (!is_mx6dq() && !is_mx6dqp())
+ p += 1;
+#else
+ stride = 1;
+#endif
+ for (i = 0; i < count; i++) {
+ imx_iomux_v3_setup_pad(*p);
+ p += stride;
+ }
+}
+
+void imx_iomux_set_gpr_register(int group, int start_bit,
+ int num_bits, int value)
+{
+ int i = 0;
+ u32 reg;
+ reg = readl(base + group * 4);
+ while (num_bits) {
+ reg &= ~(1<<(start_bit + i));
+ i++;
+ num_bits--;
+ }
+ reg |= (value << start_bit);
+ writel(reg, base + group * 4);
+}
+
+#ifdef CONFIG_IOMUX_SHARE_CONF_REG
+void imx_iomux_gpio_set_direction(unsigned int gpio,
+ unsigned int direction)
+{
+ u32 reg;
+ /*
+ * Only on Vybrid the input/output buffer enable flags
+ * are part of the shared mux/conf register.
+ */
+ reg = readl(base + (gpio << 2));
+
+ if (direction)
+ reg |= 0x2;
+ else
+ reg &= ~0x2;
+
+ writel(reg, base + (gpio << 2));
+}
+
+void imx_iomux_gpio_get_function(unsigned int gpio, u32 *gpio_state)
+{
+ *gpio_state = readl(base + (gpio << 2)) &
+ ((0X07 << PAD_MUX_MODE_SHIFT) | PAD_CTL_OBE_IBE_ENABLE);
+}
+#endif
--- /dev/null
+/*
+ * Copyright 2013 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/errno.h>
+#include <asm/io.h>
+#include <asm/mach-imx/regs-common.h>
+
+/* 1 second delay should be plenty of time for block reset. */
+#define RESET_MAX_TIMEOUT 1000000
+
+#define MXS_BLOCK_SFTRST (1 << 31)
+#define MXS_BLOCK_CLKGATE (1 << 30)
+
+int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned
+ int timeout)
+{
+ while (--timeout) {
+ if ((readl(®->reg) & mask) == mask)
+ break;
+ udelay(1);
+ }
+
+ return !timeout;
+}
+
+int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned
+ int timeout)
+{
+ while (--timeout) {
+ if ((readl(®->reg) & mask) == 0)
+ break;
+ udelay(1);
+ }
+
+ return !timeout;
+}
+
+int mxs_reset_block(struct mxs_register_32 *reg)
+{
+ /* Clear SFTRST */
+ writel(MXS_BLOCK_SFTRST, ®->reg_clr);
+
+ if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
+ return 1;
+
+ /* Clear CLKGATE */
+ writel(MXS_BLOCK_CLKGATE, ®->reg_clr);
+
+ /* Set SFTRST */
+ writel(MXS_BLOCK_SFTRST, ®->reg_set);
+
+ /* Wait for CLKGATE being set */
+ if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
+ return 1;
+
+ /* Clear SFTRST */
+ writel(MXS_BLOCK_SFTRST, ®->reg_clr);
+
+ if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
+ return 1;
+
+ /* Clear CLKGATE */
+ writel(MXS_BLOCK_CLKGATE, ®->reg_clr);
+
+ if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
+ return 1;
+
+ return 0;
+}
--- /dev/null
+if ARCH_MX5
+
+config MX5
+ bool
+ default y
+
+config MX51
+ bool
+
+config MX53
+ bool
+
+choice
+ prompt "MX5 board select"
+ optional
+
+config TARGET_M53EVK
+ bool "Support m53evk"
+ select MX53
+ select SUPPORT_SPL
+
+config TARGET_MX51EVK
+ bool "Support mx51evk"
+ select BOARD_LATE_INIT
+ select MX51
+
+config TARGET_MX53ARD
+ bool "Support mx53ard"
+ select MX53
+
+config TARGET_MX53CX9020
+ bool "Support CX9020"
+ select BOARD_LATE_INIT
+ select MX53
+ select DM
+ select DM_SERIAL
+
+config TARGET_MX53EVK
+ bool "Support mx53evk"
+ select BOARD_LATE_INIT
+ select MX53
+
+config TARGET_MX53LOCO
+ bool "Support mx53loco"
+ select BOARD_LATE_INIT
+ select MX53
+
+config TARGET_MX53SMD
+ bool "Support mx53smd"
+ select MX53
+
+config TARGET_TS4800
+ bool "Support TS4800"
+ select MX51
+ select SYS_FSL_ERRATUM_ESDHC_A001
+
+config TARGET_USBARMORY
+ bool "Support USB armory"
+ select MX53
+
+endchoice
+
+config SYS_SOC
+ default "mx5"
+
+source "board/aries/m53evk/Kconfig"
+source "board/beckhoff/mx53cx9020/Kconfig"
+source "board/freescale/mx51evk/Kconfig"
+source "board/freescale/mx53ard/Kconfig"
+source "board/freescale/mx53evk/Kconfig"
+source "board/freescale/mx53loco/Kconfig"
+source "board/freescale/mx53smd/Kconfig"
+source "board/inversepath/usbarmory/Kconfig"
+source "board/technologic/ts4800/Kconfig"
+
+endif
--- /dev/null
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2009 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := soc.o clock.o
+obj-y += lowlevel_init.o
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <div64.h>
+#include <asm/arch/sys_proto.h>
+
+enum pll_clocks {
+ PLL1_CLOCK = 0,
+ PLL2_CLOCK,
+ PLL3_CLOCK,
+#ifdef CONFIG_MX53
+ PLL4_CLOCK,
+#endif
+ PLL_CLOCKS,
+};
+
+struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
+ [PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR,
+ [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
+ [PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,
+#ifdef CONFIG_MX53
+ [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
+#endif
+};
+
+#define AHB_CLK_ROOT 133333333
+#define SZ_DEC_1M 1000000
+#define PLL_PD_MAX 16 /* Actual pd+1 */
+#define PLL_MFI_MAX 15
+#define PLL_MFI_MIN 5
+#define ARM_DIV_MAX 8
+#define IPG_DIV_MAX 4
+#define AHB_DIV_MAX 8
+#define EMI_DIV_MAX 8
+#define NFC_DIV_MAX 8
+
+#define MX5_CBCMR 0x00015154
+#define MX5_CBCDR 0x02888945
+
+struct fixed_pll_mfd {
+ u32 ref_clk_hz;
+ u32 mfd;
+};
+
+const struct fixed_pll_mfd fixed_mfd[] = {
+ {MXC_HCLK, 24 * 16},
+};
+
+struct pll_param {
+ u32 pd;
+ u32 mfi;
+ u32 mfn;
+ u32 mfd;
+};
+
+#define PLL_FREQ_MAX(ref_clk) (4 * (ref_clk) * PLL_MFI_MAX)
+#define PLL_FREQ_MIN(ref_clk) \
+ ((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
+#define MAX_DDR_CLK 420000000
+#define NFC_CLK_MAX 34000000
+
+struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
+
+void set_usboh3_clk(void)
+{
+ clrsetbits_le32(&mxc_ccm->cscmr1,
+ MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK,
+ MXC_CCM_CSCMR1_USBOH3_CLK_SEL(1));
+ clrsetbits_le32(&mxc_ccm->cscdr1,
+ MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK |
+ MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK,
+ MXC_CCM_CSCDR1_USBOH3_CLK_PRED(4) |
+ MXC_CCM_CSCDR1_USBOH3_CLK_PODF(1));
+}
+
+void enable_usboh3_clk(bool enable)
+{
+ unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
+
+ clrsetbits_le32(&mxc_ccm->CCGR2,
+ MXC_CCM_CCGR2_USBOH3_60M(MXC_CCM_CCGR_CG_MASK),
+ MXC_CCM_CCGR2_USBOH3_60M(cg));
+}
+
+#ifdef CONFIG_SYS_I2C_MXC
+/* i2c_num can be from 0, to 1 for i.MX51 and 2 for i.MX53 */
+int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
+{
+ u32 mask;
+
+#if defined(CONFIG_MX51)
+ if (i2c_num > 1)
+#elif defined(CONFIG_MX53)
+ if (i2c_num > 2)
+#endif
+ return -EINVAL;
+ mask = MXC_CCM_CCGR_CG_MASK <<
+ (MXC_CCM_CCGR1_I2C1_OFFSET + (i2c_num << 1));
+ if (enable)
+ setbits_le32(&mxc_ccm->CCGR1, mask);
+ else
+ clrbits_le32(&mxc_ccm->CCGR1, mask);
+ return 0;
+}
+#endif
+
+void set_usb_phy_clk(void)
+{
+ clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
+}
+
+#if defined(CONFIG_MX51)
+void enable_usb_phy1_clk(bool enable)
+{
+ unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
+
+ clrsetbits_le32(&mxc_ccm->CCGR2,
+ MXC_CCM_CCGR2_USB_PHY(MXC_CCM_CCGR_CG_MASK),
+ MXC_CCM_CCGR2_USB_PHY(cg));
+}
+
+void enable_usb_phy2_clk(bool enable)
+{
+ /* i.MX51 has a single USB PHY clock, so do nothing here. */
+}
+#elif defined(CONFIG_MX53)
+void enable_usb_phy1_clk(bool enable)
+{
+ unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
+
+ clrsetbits_le32(&mxc_ccm->CCGR4,
+ MXC_CCM_CCGR4_USB_PHY1(MXC_CCM_CCGR_CG_MASK),
+ MXC_CCM_CCGR4_USB_PHY1(cg));
+}
+
+void enable_usb_phy2_clk(bool enable)
+{
+ unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
+
+ clrsetbits_le32(&mxc_ccm->CCGR4,
+ MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK),
+ MXC_CCM_CCGR4_USB_PHY2(cg));
+}
+#endif
+
+/*
+ * Calculate the frequency of PLLn.
+ */
+static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)
+{
+ uint32_t ctrl, op, mfd, mfn, mfi, pdf, ret;
+ uint64_t refclk, temp;
+ int32_t mfn_abs;
+
+ ctrl = readl(&pll->ctrl);
+
+ if (ctrl & MXC_DPLLC_CTL_HFSM) {
+ mfn = readl(&pll->hfs_mfn);
+ mfd = readl(&pll->hfs_mfd);
+ op = readl(&pll->hfs_op);
+ } else {
+ mfn = readl(&pll->mfn);
+ mfd = readl(&pll->mfd);
+ op = readl(&pll->op);
+ }
+
+ mfd &= MXC_DPLLC_MFD_MFD_MASK;
+ mfn &= MXC_DPLLC_MFN_MFN_MASK;
+ pdf = op & MXC_DPLLC_OP_PDF_MASK;
+ mfi = MXC_DPLLC_OP_MFI_RD(op);
+
+ /* 21.2.3 */
+ if (mfi < 5)
+ mfi = 5;
+
+ /* Sign extend */
+ if (mfn >= 0x04000000) {
+ mfn |= 0xfc000000;
+ mfn_abs = -mfn;
+ } else
+ mfn_abs = mfn;
+
+ refclk = infreq * 2;
+ if (ctrl & MXC_DPLLC_CTL_DPDCK0_2_EN)
+ refclk *= 2;
+
+ do_div(refclk, pdf + 1);
+ temp = refclk * mfn_abs;
+ do_div(temp, mfd + 1);
+ ret = refclk * mfi;
+
+ if ((int)mfn < 0)
+ ret -= temp;
+ else
+ ret += temp;
+
+ return ret;
+}
+
+#ifdef CONFIG_MX51
+/*
+ * This function returns the Frequency Pre-Multiplier clock.
+ */
+static u32 get_fpm(void)
+{
+ u32 mult;
+ u32 ccr = readl(&mxc_ccm->ccr);
+
+ if (ccr & MXC_CCM_CCR_FPM_MULT)
+ mult = 1024;
+ else
+ mult = 512;
+
+ return MXC_CLK32 * mult;
+}
+#endif
+
+/*
+ * This function returns the low power audio clock.
+ */
+static u32 get_lp_apm(void)
+{
+ u32 ret_val = 0;
+ u32 ccsr = readl(&mxc_ccm->ccsr);
+
+ if (ccsr & MXC_CCM_CCSR_LP_APM)
+#if defined(CONFIG_MX51)
+ ret_val = get_fpm();
+#elif defined(CONFIG_MX53)
+ ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
+#endif
+ else
+ ret_val = MXC_HCLK;
+
+ return ret_val;
+}
+
+/*
+ * Get mcu main rate
+ */
+u32 get_mcu_main_clk(void)
+{
+ u32 reg, freq;
+
+ reg = MXC_CCM_CACRR_ARM_PODF_RD(readl(&mxc_ccm->cacrr));
+ freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
+ return freq / (reg + 1);
+}
+
+/*
+ * Get the rate of peripheral's root clock.
+ */
+u32 get_periph_clk(void)
+{
+ u32 reg;
+
+ reg = readl(&mxc_ccm->cbcdr);
+ if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
+ return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
+ reg = readl(&mxc_ccm->cbcmr);
+ switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(reg)) {
+ case 0:
+ return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
+ case 1:
+ return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
+ case 2:
+ return get_lp_apm();
+ default:
+ return 0;
+ }
+ /* NOTREACHED */
+}
+
+/*
+ * Get the rate of ipg clock.
+ */
+static u32 get_ipg_clk(void)
+{
+ uint32_t freq, reg, div;
+
+ freq = get_ahb_clk();
+
+ reg = readl(&mxc_ccm->cbcdr);
+ div = MXC_CCM_CBCDR_IPG_PODF_RD(reg) + 1;
+
+ return freq / div;
+}
+
+/*
+ * Get the rate of ipg_per clock.
+ */
+static u32 get_ipg_per_clk(void)
+{
+ u32 freq, pred1, pred2, podf;
+
+ if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
+ return get_ipg_clk();
+
+ if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL)
+ freq = get_lp_apm();
+ else
+ freq = get_periph_clk();
+ podf = readl(&mxc_ccm->cbcdr);
+ pred1 = MXC_CCM_CBCDR_PERCLK_PRED1_RD(podf);
+ pred2 = MXC_CCM_CBCDR_PERCLK_PRED2_RD(podf);
+ podf = MXC_CCM_CBCDR_PERCLK_PODF_RD(podf);
+ return freq / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
+}
+
+/* Get the output clock rate of a standard PLL MUX for peripherals. */
+static u32 get_standard_pll_sel_clk(u32 clk_sel)
+{
+ u32 freq = 0;
+
+ switch (clk_sel & 0x3) {
+ case 0:
+ freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
+ break;
+ case 1:
+ freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
+ break;
+ case 2:
+ freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
+ break;
+ case 3:
+ freq = get_lp_apm();
+ break;
+ }
+
+ return freq;
+}
+
+/*
+ * Get the rate of uart clk.
+ */
+static u32 get_uart_clk(void)
+{
+ unsigned int clk_sel, freq, reg, pred, podf;
+
+ reg = readl(&mxc_ccm->cscmr1);
+ clk_sel = MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg);
+ freq = get_standard_pll_sel_clk(clk_sel);
+
+ reg = readl(&mxc_ccm->cscdr1);
+ pred = MXC_CCM_CSCDR1_UART_CLK_PRED_RD(reg);
+ podf = MXC_CCM_CSCDR1_UART_CLK_PODF_RD(reg);
+ freq /= (pred + 1) * (podf + 1);
+
+ return freq;
+}
+
+/*
+ * get cspi clock rate.
+ */
+static u32 imx_get_cspiclk(void)
+{
+ u32 ret_val = 0, pdf, pre_pdf, clk_sel, freq;
+ u32 cscmr1 = readl(&mxc_ccm->cscmr1);
+ u32 cscdr2 = readl(&mxc_ccm->cscdr2);
+
+ pre_pdf = MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(cscdr2);
+ pdf = MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(cscdr2);
+ clk_sel = MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(cscmr1);
+ freq = get_standard_pll_sel_clk(clk_sel);
+ ret_val = freq / ((pre_pdf + 1) * (pdf + 1));
+ return ret_val;
+}
+
+/*
+ * get esdhc clock rate.
+ */
+static u32 get_esdhc_clk(u32 port)
+{
+ u32 clk_sel = 0, pred = 0, podf = 0, freq = 0;
+ u32 cscmr1 = readl(&mxc_ccm->cscmr1);
+ u32 cscdr1 = readl(&mxc_ccm->cscdr1);
+
+ switch (port) {
+ case 0:
+ clk_sel = MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(cscmr1);
+ pred = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(cscdr1);
+ podf = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(cscdr1);
+ break;
+ case 1:
+ clk_sel = MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(cscmr1);
+ pred = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(cscdr1);
+ podf = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(cscdr1);
+ break;
+ case 2:
+ if (cscmr1 & MXC_CCM_CSCMR1_ESDHC3_CLK_SEL)
+ return get_esdhc_clk(1);
+ else
+ return get_esdhc_clk(0);
+ case 3:
+ if (cscmr1 & MXC_CCM_CSCMR1_ESDHC4_CLK_SEL)
+ return get_esdhc_clk(1);
+ else
+ return get_esdhc_clk(0);
+ default:
+ break;
+ }
+
+ freq = get_standard_pll_sel_clk(clk_sel) / ((pred + 1) * (podf + 1));
+ return freq;
+}
+
+static u32 get_axi_a_clk(void)
+{
+ u32 cbcdr = readl(&mxc_ccm->cbcdr);
+ u32 pdf = MXC_CCM_CBCDR_AXI_A_PODF_RD(cbcdr);
+
+ return get_periph_clk() / (pdf + 1);
+}
+
+static u32 get_axi_b_clk(void)
+{
+ u32 cbcdr = readl(&mxc_ccm->cbcdr);
+ u32 pdf = MXC_CCM_CBCDR_AXI_B_PODF_RD(cbcdr);
+
+ return get_periph_clk() / (pdf + 1);
+}
+
+static u32 get_emi_slow_clk(void)
+{
+ u32 cbcdr = readl(&mxc_ccm->cbcdr);
+ u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL;
+ u32 pdf = MXC_CCM_CBCDR_EMI_PODF_RD(cbcdr);
+
+ if (emi_clk_sel)
+ return get_ahb_clk() / (pdf + 1);
+
+ return get_periph_clk() / (pdf + 1);
+}
+
+static u32 get_ddr_clk(void)
+{
+ u32 ret_val = 0;
+ u32 cbcmr = readl(&mxc_ccm->cbcmr);
+ u32 ddr_clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
+#ifdef CONFIG_MX51
+ u32 cbcdr = readl(&mxc_ccm->cbcdr);
+ if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) {
+ u32 ddr_clk_podf = MXC_CCM_CBCDR_DDR_PODF_RD(cbcdr);
+
+ ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
+ ret_val /= ddr_clk_podf + 1;
+
+ return ret_val;
+ }
+#endif
+ switch (ddr_clk_sel) {
+ case 0:
+ ret_val = get_axi_a_clk();
+ break;
+ case 1:
+ ret_val = get_axi_b_clk();
+ break;
+ case 2:
+ ret_val = get_emi_slow_clk();
+ break;
+ case 3:
+ ret_val = get_ahb_clk();
+ break;
+ default:
+ break;
+ }
+
+ return ret_val;
+}
+
+/*
+ * The API of get mxc clocks.
+ */
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+ switch (clk) {
+ case MXC_ARM_CLK:
+ return get_mcu_main_clk();
+ case MXC_AHB_CLK:
+ return get_ahb_clk();
+ case MXC_IPG_CLK:
+ return get_ipg_clk();
+ case MXC_IPG_PERCLK:
+ case MXC_I2C_CLK:
+ return get_ipg_per_clk();
+ case MXC_UART_CLK:
+ return get_uart_clk();
+ case MXC_CSPI_CLK:
+ return imx_get_cspiclk();
+ case MXC_ESDHC_CLK:
+ return get_esdhc_clk(0);
+ case MXC_ESDHC2_CLK:
+ return get_esdhc_clk(1);
+ case MXC_ESDHC3_CLK:
+ return get_esdhc_clk(2);
+ case MXC_ESDHC4_CLK:
+ return get_esdhc_clk(3);
+ case MXC_FEC_CLK:
+ return get_ipg_clk();
+ case MXC_SATA_CLK:
+ return get_ahb_clk();
+ case MXC_DDR_CLK:
+ return get_ddr_clk();
+ default:
+ break;
+ }
+ return -EINVAL;
+}
+
+u32 imx_get_uartclk(void)
+{
+ return get_uart_clk();
+}
+
+u32 imx_get_fecclk(void)
+{
+ return get_ipg_clk();
+}
+
+static int gcd(int m, int n)
+{
+ int t;
+ while (m > 0) {
+ if (n > m) {
+ t = m;
+ m = n;
+ n = t;
+ } /* swap */
+ m -= n;
+ }
+ return n;
+}
+
+/*
+ * This is to calculate various parameters based on reference clock and
+ * targeted clock based on the equation:
+ * t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1)
+ * This calculation is based on a fixed MFD value for simplicity.
+ */
+static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll)
+{
+ u64 pd, mfi = 1, mfn, mfd, t1;
+ u32 n_target = target;
+ u32 n_ref = ref, i;
+
+ /*
+ * Make sure targeted freq is in the valid range.
+ * Otherwise the following calculation might be wrong!!!
+ */
+ if (n_target < PLL_FREQ_MIN(ref) ||
+ n_target > PLL_FREQ_MAX(ref)) {
+ printf("Targeted peripheral clock should be"
+ "within [%d - %d]\n",
+ PLL_FREQ_MIN(ref) / SZ_DEC_1M,
+ PLL_FREQ_MAX(ref) / SZ_DEC_1M);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(fixed_mfd); i++) {
+ if (fixed_mfd[i].ref_clk_hz == ref) {
+ mfd = fixed_mfd[i].mfd;
+ break;
+ }
+ }
+
+ if (i == ARRAY_SIZE(fixed_mfd))
+ return -EINVAL;
+
+ /* Use n_target and n_ref to avoid overflow */
+ for (pd = 1; pd <= PLL_PD_MAX; pd++) {
+ t1 = n_target * pd;
+ do_div(t1, (4 * n_ref));
+ mfi = t1;
+ if (mfi > PLL_MFI_MAX)
+ return -EINVAL;
+ else if (mfi < 5)
+ continue;
+ break;
+ }
+ /*
+ * Now got pd and mfi already
+ *
+ * mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref;
+ */
+ t1 = n_target * pd;
+ do_div(t1, 4);
+ t1 -= n_ref * mfi;
+ t1 *= mfd;
+ do_div(t1, n_ref);
+ mfn = t1;
+ debug("ref=%d, target=%d, pd=%d," "mfi=%d,mfn=%d, mfd=%d\n",
+ ref, n_target, (u32)pd, (u32)mfi, (u32)mfn, (u32)mfd);
+ i = 1;
+ if (mfn != 0)
+ i = gcd(mfd, mfn);
+ pll->pd = (u32)pd;
+ pll->mfi = (u32)mfi;
+ do_div(mfn, i);
+ pll->mfn = (u32)mfn;
+ do_div(mfd, i);
+ pll->mfd = (u32)mfd;
+
+ return 0;
+}
+
+#define calc_div(tgt_clk, src_clk, limit) ({ \
+ u32 v = 0; \
+ if (((src_clk) % (tgt_clk)) <= 100) \
+ v = (src_clk) / (tgt_clk); \
+ else \
+ v = ((src_clk) / (tgt_clk)) + 1;\
+ if (v > limit) \
+ v = limit; \
+ (v - 1); \
+ })
+
+#define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \
+ { \
+ writel(0x1232, &pll->ctrl); \
+ writel(0x2, &pll->config); \
+ writel((((pd) - 1) << 0) | ((fi) << 4), \
+ &pll->op); \
+ writel(fn, &(pll->mfn)); \
+ writel((fd) - 1, &pll->mfd); \
+ writel((((pd) - 1) << 0) | ((fi) << 4), \
+ &pll->hfs_op); \
+ writel(fn, &pll->hfs_mfn); \
+ writel((fd) - 1, &pll->hfs_mfd); \
+ writel(0x1232, &pll->ctrl); \
+ while (!readl(&pll->ctrl) & 0x1) \
+ ;\
+ }
+
+static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param)
+{
+ u32 ccsr = readl(&mxc_ccm->ccsr);
+ struct mxc_pll_reg *pll = mxc_plls[index];
+
+ switch (index) {
+ case PLL1_CLOCK:
+ /* Switch ARM to PLL2 clock */
+ writel(ccsr | MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
+ &mxc_ccm->ccsr);
+ CHANGE_PLL_SETTINGS(pll, pll_param->pd,
+ pll_param->mfi, pll_param->mfn,
+ pll_param->mfd);
+ /* Switch back */
+ writel(ccsr & ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
+ &mxc_ccm->ccsr);
+ break;
+ case PLL2_CLOCK:
+ /* Switch to pll2 bypass clock */
+ writel(ccsr | MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
+ &mxc_ccm->ccsr);
+ CHANGE_PLL_SETTINGS(pll, pll_param->pd,
+ pll_param->mfi, pll_param->mfn,
+ pll_param->mfd);
+ /* Switch back */
+ writel(ccsr & ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
+ &mxc_ccm->ccsr);
+ break;
+ case PLL3_CLOCK:
+ /* Switch to pll3 bypass clock */
+ writel(ccsr | MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
+ &mxc_ccm->ccsr);
+ CHANGE_PLL_SETTINGS(pll, pll_param->pd,
+ pll_param->mfi, pll_param->mfn,
+ pll_param->mfd);
+ /* Switch back */
+ writel(ccsr & ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
+ &mxc_ccm->ccsr);
+ break;
+#ifdef CONFIG_MX53
+ case PLL4_CLOCK:
+ /* Switch to pll4 bypass clock */
+ writel(ccsr | MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
+ &mxc_ccm->ccsr);
+ CHANGE_PLL_SETTINGS(pll, pll_param->pd,
+ pll_param->mfi, pll_param->mfn,
+ pll_param->mfd);
+ /* Switch back */
+ writel(ccsr & ~MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
+ &mxc_ccm->ccsr);
+ break;
+#endif
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/* Config CPU clock */
+static int config_core_clk(u32 ref, u32 freq)
+{
+ int ret = 0;
+ struct pll_param pll_param;
+
+ memset(&pll_param, 0, sizeof(struct pll_param));
+
+ /* The case that periph uses PLL1 is not considered here */
+ ret = calc_pll_params(ref, freq, &pll_param);
+ if (ret != 0) {
+ printf("Error:Can't find pll parameters: %d\n", ret);
+ return ret;
+ }
+
+ return config_pll_clk(PLL1_CLOCK, &pll_param);
+}
+
+static int config_nfc_clk(u32 nfc_clk)
+{
+ u32 parent_rate = get_emi_slow_clk();
+ u32 div;
+
+ if (nfc_clk == 0)
+ return -EINVAL;
+ div = parent_rate / nfc_clk;
+ if (div == 0)
+ div++;
+ if (parent_rate / div > NFC_CLK_MAX)
+ div++;
+ clrsetbits_le32(&mxc_ccm->cbcdr,
+ MXC_CCM_CBCDR_NFC_PODF_MASK,
+ MXC_CCM_CBCDR_NFC_PODF(div - 1));
+ while (readl(&mxc_ccm->cdhipr) != 0)
+ ;
+ return 0;
+}
+
+void enable_nfc_clk(unsigned char enable)
+{
+ unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
+
+ clrsetbits_le32(&mxc_ccm->CCGR5,
+ MXC_CCM_CCGR5_EMI_ENFC(MXC_CCM_CCGR_CG_MASK),
+ MXC_CCM_CCGR5_EMI_ENFC(cg));
+}
+
+#ifdef CONFIG_FSL_IIM
+void enable_efuse_prog_supply(bool enable)
+{
+ if (enable)
+ setbits_le32(&mxc_ccm->cgpr,
+ MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
+ else
+ clrbits_le32(&mxc_ccm->cgpr,
+ MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
+}
+#endif
+
+/* Config main_bus_clock for periphs */
+static int config_periph_clk(u32 ref, u32 freq)
+{
+ int ret = 0;
+ struct pll_param pll_param;
+
+ memset(&pll_param, 0, sizeof(struct pll_param));
+
+ if (readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
+ ret = calc_pll_params(ref, freq, &pll_param);
+ if (ret != 0) {
+ printf("Error:Can't find pll parameters: %d\n",
+ ret);
+ return ret;
+ }
+ switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(
+ readl(&mxc_ccm->cbcmr))) {
+ case 0:
+ return config_pll_clk(PLL1_CLOCK, &pll_param);
+ break;
+ case 1:
+ return config_pll_clk(PLL3_CLOCK, &pll_param);
+ break;
+ default:
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
+
+static int config_ddr_clk(u32 emi_clk)
+{
+ u32 clk_src;
+ s32 shift = 0, clk_sel, div = 1;
+ u32 cbcmr = readl(&mxc_ccm->cbcmr);
+
+ if (emi_clk > MAX_DDR_CLK) {
+ printf("Warning:DDR clock should not exceed %d MHz\n",
+ MAX_DDR_CLK / SZ_DEC_1M);
+ emi_clk = MAX_DDR_CLK;
+ }
+
+ clk_src = get_periph_clk();
+ /* Find DDR clock input */
+ clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
+ switch (clk_sel) {
+ case 0:
+ shift = 16;
+ break;
+ case 1:
+ shift = 19;
+ break;
+ case 2:
+ shift = 22;
+ break;
+ case 3:
+ shift = 10;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if ((clk_src % emi_clk) < 10000000)
+ div = clk_src / emi_clk;
+ else
+ div = (clk_src / emi_clk) + 1;
+ if (div > 8)
+ div = 8;
+
+ clrsetbits_le32(&mxc_ccm->cbcdr, 0x7 << shift, (div - 1) << shift);
+ while (readl(&mxc_ccm->cdhipr) != 0)
+ ;
+ writel(0x0, &mxc_ccm->ccdr);
+
+ return 0;
+}
+
+/*
+ * This function assumes the expected core clock has to be changed by
+ * modifying the PLL. This is NOT true always but for most of the times,
+ * it is. So it assumes the PLL output freq is the same as the expected
+ * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
+ * In the latter case, it will try to increase the presc value until
+ * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
+ * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
+ * on the targeted PLL and reference input clock to the PLL. Lastly,
+ * it sets the register based on these values along with the dividers.
+ * Note 1) There is no value checking for the passed-in divider values
+ * so the caller has to make sure those values are sensible.
+ * 2) Also adjust the NFC divider such that the NFC clock doesn't
+ * exceed NFC_CLK_MAX.
+ * 3) IPU HSP clock is independent of AHB clock. Even it can go up to
+ * 177MHz for higher voltage, this function fixes the max to 133MHz.
+ * 4) This function should not have allowed diag_printf() calls since
+ * the serial driver has been stoped. But leave then here to allow
+ * easy debugging by NOT calling the cyg_hal_plf_serial_stop().
+ */
+int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
+{
+ freq *= SZ_DEC_1M;
+
+ switch (clk) {
+ case MXC_ARM_CLK:
+ if (config_core_clk(ref, freq))
+ return -EINVAL;
+ break;
+ case MXC_PERIPH_CLK:
+ if (config_periph_clk(ref, freq))
+ return -EINVAL;
+ break;
+ case MXC_DDR_CLK:
+ if (config_ddr_clk(freq))
+ return -EINVAL;
+ break;
+ case MXC_NFC_CLK:
+ if (config_nfc_clk(freq))
+ return -EINVAL;
+ break;
+ default:
+ printf("Warning:Unsupported or invalid clock type\n");
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_MX53
+/*
+ * The clock for the external interface can be set to use internal clock
+ * if fuse bank 4, row 3, bit 2 is set.
+ * This is an undocumented feature and it was confirmed by Freescale's support:
+ * Fuses (but not pins) may be used to configure SATA clocks.
+ * Particularly the i.MX53 Fuse_Map contains the next information
+ * about configuring SATA clocks : SATA_ALT_REF_CLK[1:0] (offset 0x180C)
+ * '00' - 100MHz (External)
+ * '01' - 50MHz (External)
+ * '10' - 120MHz, internal (USB PHY)
+ * '11' - Reserved
+*/
+void mxc_set_sata_internal_clock(void)
+{
+ u32 *tmp_base =
+ (u32 *)(IIM_BASE_ADDR + 0x180c);
+
+ set_usb_phy_clk();
+
+ clrsetbits_le32(tmp_base, 0x6, 0x4);
+}
+#endif
+
+/*
+ * Dump some core clockes.
+ */
+int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ u32 freq;
+
+ freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
+ printf("PLL1 %8d MHz\n", freq / 1000000);
+ freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
+ printf("PLL2 %8d MHz\n", freq / 1000000);
+ freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
+ printf("PLL3 %8d MHz\n", freq / 1000000);
+#ifdef CONFIG_MX53
+ freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
+ printf("PLL4 %8d MHz\n", freq / 1000000);
+#endif
+
+ printf("\n");
+ printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
+ printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
+ printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
+ printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
+#ifdef CONFIG_MXC_SPI
+ printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
+#endif
+ return 0;
+}
+
+/***************************************************/
+
+U_BOOT_CMD(
+ clocks, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks,
+ "display clocks",
+ ""
+);
--- /dev/null
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/arch/imx-regs.h>
+#include <generated/asm-offsets.h>
+#include <linux/linkage.h>
+
+.section ".text.init", "x"
+
+.macro init_arm_erratum
+ /* ARM erratum ID #468414 */
+ mrc 15, 0, r1, c1, c0, 1
+ orr r1, r1, #(1 << 5) /* enable L1NEON bit */
+ mcr 15, 0, r1, c1, c0, 1
+.endm
+
+/*
+ * L2CC Cache setup/invalidation/disable
+ */
+.macro init_l2cc
+ /* explicitly disable L2 cache */
+ mrc 15, 0, r0, c1, c0, 1
+ bic r0, r0, #0x2
+ mcr 15, 0, r0, c1, c0, 1
+
+ /* reconfigure L2 cache aux control reg */
+ ldr r0, =0xC0 | /* tag RAM */ \
+ 0x4 | /* data RAM */ \
+ 1 << 24 | /* disable write allocate delay */ \
+ 1 << 23 | /* disable write allocate combine */ \
+ 1 << 22 /* disable write allocate */
+
+#if defined(CONFIG_MX51)
+ ldr r3, [r4, #ROM_SI_REV]
+ cmp r3, #0x10
+
+ /* disable write combine for TO 2 and lower revs */
+ orrls r0, r0, #1 << 25
+#endif
+
+ mcr 15, 1, r0, c9, c0, 2
+
+ /* enable L2 cache */
+ mrc 15, 0, r0, c1, c0, 1
+ orr r0, r0, #2
+ mcr 15, 0, r0, c1, c0, 1
+
+.endm /* init_l2cc */
+
+/* AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.*/
+.macro init_aips
+ /*
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+ ldr r0, =AIPS1_BASE_ADDR
+ ldr r1, =0x77777777
+ str r1, [r0, #0x0]
+ str r1, [r0, #0x4]
+ ldr r0, =AIPS2_BASE_ADDR
+ str r1, [r0, #0x0]
+ str r1, [r0, #0x4]
+ /*
+ * Clear the on and off peripheral modules Supervisor Protect bit
+ * for SDMA to access them. Did not change the AIPS control registers
+ * (offset 0x20) access type
+ */
+.endm /* init_aips */
+
+/* M4IF setup */
+.macro init_m4if
+#ifdef CONFIG_MX51
+ /* VPU and IPU given higher priority (0x4)
+ * IPU accesses with ID=0x1 given highest priority (=0xA)
+ */
+ ldr r0, =M4IF_BASE_ADDR
+
+ ldr r1, =0x00000203
+ str r1, [r0, #0x40]
+
+ str r4, [r0, #0x44]
+
+ ldr r1, =0x00120125
+ str r1, [r0, #0x9C]
+
+ ldr r1, =0x001901A3
+ str r1, [r0, #0x48]
+
+#endif
+.endm /* init_m4if */
+
+.macro setup_pll pll, freq
+ ldr r0, =\pll
+ adr r2, W_DP_\freq
+ bl setup_pll_func
+.endm
+
+#define W_DP_OP 0
+#define W_DP_MFD 4
+#define W_DP_MFN 8
+
+setup_pll_func:
+ ldr r1, =0x00001232
+ str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
+ mov r1, #0x2
+ str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
+
+ ldr r1, [r2, #W_DP_OP]
+ str r1, [r0, #PLL_DP_OP]
+ str r1, [r0, #PLL_DP_HFS_OP]
+
+ ldr r1, [r2, #W_DP_MFD]
+ str r1, [r0, #PLL_DP_MFD]
+ str r1, [r0, #PLL_DP_HFS_MFD]
+
+ ldr r1, [r2, #W_DP_MFN]
+ str r1, [r0, #PLL_DP_MFN]
+ str r1, [r0, #PLL_DP_HFS_MFN]
+
+ ldr r1, =0x00001232
+ str r1, [r0, #PLL_DP_CTL]
+1: ldr r1, [r0, #PLL_DP_CTL]
+ ands r1, r1, #0x1
+ beq 1b
+
+ /* r10 saved upper lr */
+ mov pc, lr
+
+.macro setup_pll_errata pll, freq
+ ldr r2, =\pll
+ str r4, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
+ ldr r1, =0x00001236
+ str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */
+1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */
+ ands r1, r1, #0x1
+ beq 1b
+
+ ldr r5, \freq
+ str r5, [r2, #PLL_DP_MFN] /* Modify MFN value */
+ str r5, [r2, #PLL_DP_HFS_MFN]
+
+ mov r1, #0x1
+ str r1, [r2, #PLL_DP_CONFIG] /* Reload MFN value */
+
+2: ldr r1, [r2, #PLL_DP_CONFIG]
+ tst r1, #1
+ bne 2b
+
+ ldr r1, =100 /* Wait at least 4 us */
+3: subs r1, r1, #1
+ bge 3b
+
+ mov r1, #0x2
+ str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
+.endm
+
+.macro init_clock
+#if defined (CONFIG_MX51)
+ ldr r0, =CCM_BASE_ADDR
+
+ /* Gate of clocks to the peripherals first */
+ ldr r1, =0x3FFFFFFF
+ str r1, [r0, #CLKCTL_CCGR0]
+ str r4, [r0, #CLKCTL_CCGR1]
+ str r4, [r0, #CLKCTL_CCGR2]
+ str r4, [r0, #CLKCTL_CCGR3]
+
+ ldr r1, =0x00030000
+ str r1, [r0, #CLKCTL_CCGR4]
+ ldr r1, =0x00FFF030
+ str r1, [r0, #CLKCTL_CCGR5]
+ ldr r1, =0x00000300
+ str r1, [r0, #CLKCTL_CCGR6]
+
+ /* Disable IPU and HSC dividers */
+ mov r1, #0x60000
+ str r1, [r0, #CLKCTL_CCDR]
+
+ /* Make sure to switch the DDR away from PLL 1 */
+ ldr r1, =0x19239145
+ str r1, [r0, #CLKCTL_CBCDR]
+ /* make sure divider effective */
+1: ldr r1, [r0, #CLKCTL_CDHIPR]
+ cmp r1, #0x0
+ bne 1b
+
+ /* Switch ARM to step clock */
+ mov r1, #0x4
+ str r1, [r0, #CLKCTL_CCSR]
+
+#if defined(CONFIG_MX51_PLL_ERRATA)
+ setup_pll PLL1_BASE_ADDR, 864
+ setup_pll_errata PLL1_BASE_ADDR, W_DP_MFN_800_DIT
+#else
+ setup_pll PLL1_BASE_ADDR, 800
+#endif
+
+ setup_pll PLL3_BASE_ADDR, 665
+
+ /* Switch peripheral to PLL 3 */
+ ldr r0, =CCM_BASE_ADDR
+ ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL
+ str r1, [r0, #CLKCTL_CBCMR]
+ ldr r1, =0x13239145
+ str r1, [r0, #CLKCTL_CBCDR]
+ setup_pll PLL2_BASE_ADDR, 665
+
+ /* Switch peripheral to PLL2 */
+ ldr r0, =CCM_BASE_ADDR
+ ldr r1, =0x19239145
+ str r1, [r0, #CLKCTL_CBCDR]
+ ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
+ str r1, [r0, #CLKCTL_CBCMR]
+
+ setup_pll PLL3_BASE_ADDR, 216
+
+ /* Set the platform clock dividers */
+ ldr r0, =ARM_BASE_ADDR
+ ldr r1, =0x00000725
+ str r1, [r0, #0x14]
+
+ ldr r0, =CCM_BASE_ADDR
+
+ /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
+ ldr r3, [r4, #ROM_SI_REV]
+ cmp r3, #0x10
+ movls r1, #0x1
+ movhi r1, #0
+
+ str r1, [r0, #CLKCTL_CACRR]
+
+ /* Switch ARM back to PLL 1 */
+ str r4, [r0, #CLKCTL_CCSR]
+
+ /* setup the rest */
+ /* Use lp_apm (24MHz) source for perclk */
+ ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
+ str r1, [r0, #CLKCTL_CBCMR]
+ /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
+ ldr r1, =CONFIG_SYS_CLKTL_CBCDR
+ str r1, [r0, #CLKCTL_CBCDR]
+
+ /* Restore the default values in the Gate registers */
+ ldr r1, =0xFFFFFFFF
+ str r1, [r0, #CLKCTL_CCGR0]
+ str r1, [r0, #CLKCTL_CCGR1]
+ str r1, [r0, #CLKCTL_CCGR2]
+ str r1, [r0, #CLKCTL_CCGR3]
+ str r1, [r0, #CLKCTL_CCGR4]
+ str r1, [r0, #CLKCTL_CCGR5]
+ str r1, [r0, #CLKCTL_CCGR6]
+
+ /* Use PLL 2 for UART's, get 66.5MHz from it */
+ ldr r1, =0xA5A2A020
+ str r1, [r0, #CLKCTL_CSCMR1]
+ ldr r1, =0x00C30321
+ str r1, [r0, #CLKCTL_CSCDR1]
+ /* make sure divider effective */
+1: ldr r1, [r0, #CLKCTL_CDHIPR]
+ cmp r1, #0x0
+ bne 1b
+
+ str r4, [r0, #CLKCTL_CCDR]
+
+ /* for cko - for ARM div by 8 */
+ mov r1, #0x000A0000
+ add r1, r1, #0x00000F0
+ str r1, [r0, #CLKCTL_CCOSR]
+#else /* CONFIG_MX53 */
+ ldr r0, =CCM_BASE_ADDR
+
+ /* Gate of clocks to the peripherals first */
+ ldr r1, =0x3FFFFFFF
+ str r1, [r0, #CLKCTL_CCGR0]
+ str r4, [r0, #CLKCTL_CCGR1]
+ str r4, [r0, #CLKCTL_CCGR2]
+ str r4, [r0, #CLKCTL_CCGR3]
+ str r4, [r0, #CLKCTL_CCGR7]
+ ldr r1, =0x00030000
+ str r1, [r0, #CLKCTL_CCGR4]
+ ldr r1, =0x00FFF030
+ str r1, [r0, #CLKCTL_CCGR5]
+ ldr r1, =0x0F00030F
+ str r1, [r0, #CLKCTL_CCGR6]
+
+ /* Switch ARM to step clock */
+ mov r1, #0x4
+ str r1, [r0, #CLKCTL_CCSR]
+
+ setup_pll PLL1_BASE_ADDR, 800
+
+ setup_pll PLL3_BASE_ADDR, 400
+
+ /* Switch peripheral to PLL3 */
+ ldr r0, =CCM_BASE_ADDR
+ ldr r1, =0x00015154
+ str r1, [r0, #CLKCTL_CBCMR]
+ ldr r1, =0x02898945
+ str r1, [r0, #CLKCTL_CBCDR]
+ /* make sure change is effective */
+1: ldr r1, [r0, #CLKCTL_CDHIPR]
+ cmp r1, #0x0
+ bne 1b
+
+ setup_pll PLL2_BASE_ADDR, 400
+
+ /* Switch peripheral to PLL2 */
+ ldr r0, =CCM_BASE_ADDR
+ ldr r1, =0x00888945
+ str r1, [r0, #CLKCTL_CBCDR]
+
+ ldr r1, =0x00016154
+ str r1, [r0, #CLKCTL_CBCMR]
+
+ /*change uart clk parent to pll2*/
+ ldr r1, [r0, #CLKCTL_CSCMR1]
+ and r1, r1, #0xfcffffff
+ orr r1, r1, #0x01000000
+ str r1, [r0, #CLKCTL_CSCMR1]
+
+ /* make sure change is effective */
+1: ldr r1, [r0, #CLKCTL_CDHIPR]
+ cmp r1, #0x0
+ bne 1b
+
+ setup_pll PLL3_BASE_ADDR, 216
+
+ setup_pll PLL4_BASE_ADDR, 455
+
+ /* Set the platform clock dividers */
+ ldr r0, =ARM_BASE_ADDR
+ ldr r1, =0x00000124
+ str r1, [r0, #0x14]
+
+ ldr r0, =CCM_BASE_ADDR
+ mov r1, #0
+ str r1, [r0, #CLKCTL_CACRR]
+
+ /* Switch ARM back to PLL 1. */
+ mov r1, #0x0
+ str r1, [r0, #CLKCTL_CCSR]
+
+ /* make uart div=6 */
+ ldr r1, [r0, #CLKCTL_CSCDR1]
+ and r1, r1, #0xffffffc0
+ orr r1, r1, #0x0a
+ str r1, [r0, #CLKCTL_CSCDR1]
+
+ /* Restore the default values in the Gate registers */
+ ldr r1, =0xFFFFFFFF
+ str r1, [r0, #CLKCTL_CCGR0]
+ str r1, [r0, #CLKCTL_CCGR1]
+ str r1, [r0, #CLKCTL_CCGR2]
+ str r1, [r0, #CLKCTL_CCGR3]
+ str r1, [r0, #CLKCTL_CCGR4]
+ str r1, [r0, #CLKCTL_CCGR5]
+ str r1, [r0, #CLKCTL_CCGR6]
+ str r1, [r0, #CLKCTL_CCGR7]
+
+ mov r1, #0x00000
+ str r1, [r0, #CLKCTL_CCDR]
+
+ /* for cko - for ARM div by 8 */
+ mov r1, #0x000A0000
+ add r1, r1, #0x00000F0
+ str r1, [r0, #CLKCTL_CCOSR]
+
+#endif /* CONFIG_MX53 */
+.endm
+
+ENTRY(lowlevel_init)
+ mov r10, lr
+ mov r4, #0 /* Fix R4 to 0 */
+
+#if defined(CONFIG_SYS_MAIN_PWR_ON)
+ ldr r0, =GPIO1_BASE_ADDR
+ ldr r1, [r0, #0x0]
+ orr r1, r1, #1 << 23
+ str r1, [r0, #0x0]
+ ldr r1, [r0, #0x4]
+ orr r1, r1, #1 << 23
+ str r1, [r0, #0x4]
+#endif
+
+ init_arm_erratum
+
+ init_l2cc
+
+ init_aips
+
+ init_m4if
+
+ init_clock
+
+ mov pc, r10
+ENDPROC(lowlevel_init)
+
+/* Board level setting value */
+#if defined(CONFIG_MX51_PLL_ERRATA)
+W_DP_864: .word DP_OP_864
+ .word DP_MFD_864
+ .word DP_MFN_864
+W_DP_MFN_800_DIT: .word DP_MFN_800_DIT
+#else
+W_DP_800: .word DP_OP_800
+ .word DP_MFD_800
+ .word DP_MFN_800
+#endif
+#if defined(CONFIG_MX51)
+W_DP_665: .word DP_OP_665
+ .word DP_MFD_665
+ .word DP_MFN_665
+#endif
+W_DP_216: .word DP_OP_216
+ .word DP_MFD_216
+ .word DP_MFN_216
+W_DP_400: .word DP_OP_400
+ .word DP_MFD_400
+ .word DP_MFN_400
+W_DP_455: .word DP_OP_455
+ .word DP_MFD_455
+ .word DP_MFN_455
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+
+#include <linux/errno.h>
+#include <asm/io.h>
+#include <asm/mach-imx/boot_mode.h>
+
+#if !(defined(CONFIG_MX51) || defined(CONFIG_MX53))
+#error "CPU_TYPE not defined"
+#endif
+
+u32 get_cpu_rev(void)
+{
+#ifdef CONFIG_MX51
+ int system_rev = 0x51000;
+#else
+ int system_rev = 0x53000;
+#endif
+ int reg = __raw_readl(ROM_SI_REV);
+
+#if defined(CONFIG_MX51)
+ switch (reg) {
+ case 0x02:
+ system_rev |= CHIP_REV_1_1;
+ break;
+ case 0x10:
+ if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
+ system_rev |= CHIP_REV_2_5;
+ else
+ system_rev |= CHIP_REV_2_0;
+ break;
+ case 0x20:
+ system_rev |= CHIP_REV_3_0;
+ break;
+ default:
+ system_rev |= CHIP_REV_1_0;
+ break;
+ }
+#else
+ if (reg < 0x20)
+ system_rev |= CHIP_REV_1_0;
+ else
+ system_rev |= reg;
+#endif
+ return system_rev;
+}
+
+#ifdef CONFIG_REVISION_TAG
+u32 __weak get_board_rev(void)
+{
+ return get_cpu_rev();
+}
+#endif
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+}
+#endif
+
+#if defined(CONFIG_FEC_MXC)
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+ int i;
+ struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+ struct fuse_bank *bank = &iim->bank[1];
+ struct fuse_bank1_regs *fuse =
+ (struct fuse_bank1_regs *)bank->fuse_regs;
+
+ for (i = 0; i < 6; i++)
+ mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
+}
+#endif
+
+#ifdef CONFIG_MX53
+void boot_mode_apply(unsigned cfg_val)
+{
+ writel(cfg_val, &((struct srtc_regs *)SRTC_BASE_ADDR)->lpgr);
+}
+/*
+ * cfg_val will be used for
+ * Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
+ *
+ * If bit 28 of LPGR is set upon watchdog reset,
+ * bits[25:0] of LPGR will move to SBMR.
+ */
+const struct boot_mode soc_boot_modes[] = {
+ {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
+ /* usb or serial download */
+ {"usb", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x13)},
+ {"sata", MAKE_CFGVAL(0x28, 0x00, 0x00, 0x12)},
+ {"escpi1:0", MAKE_CFGVAL(0x38, 0x20, 0x00, 0x12)},
+ {"escpi1:1", MAKE_CFGVAL(0x38, 0x20, 0x04, 0x12)},
+ {"escpi1:2", MAKE_CFGVAL(0x38, 0x20, 0x08, 0x12)},
+ {"escpi1:3", MAKE_CFGVAL(0x38, 0x20, 0x0c, 0x12)},
+ /* 4 bit bus width */
+ {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
+ {"esdhc2", MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
+ {"esdhc3", MAKE_CFGVAL(0x40, 0x20, 0x10, 0x12)},
+ {"esdhc4", MAKE_CFGVAL(0x40, 0x20, 0x18, 0x12)},
+ {NULL, 0},
+};
+#endif
--- /dev/null
+if ARCH_MX6
+
+config MX6
+ bool
+ default y
+ select ARM_ERRATA_743622 if !MX6UL
+ select ARM_ERRATA_751472 if !MX6UL
+ select ARM_ERRATA_761320 if !MX6UL
+ select ARM_ERRATA_794072 if !MX6UL
+ imply CMD_FUSE
+
+config MX6D
+ bool
+
+config MX6DL
+ bool
+
+config MX6Q
+ bool
+
+config MX6QDL
+ bool
+
+config MX6S
+ bool
+
+config MX6SL
+ bool
+
+config MX6SX
+ select ROM_UNIFIED_SECTIONS
+ bool
+ imply ENV_IS_IN_MMC
+
+config MX6SLL
+ select ROM_UNIFIED_SECTIONS
+ bool
+
+config MX6UL
+ select SYS_L2CACHE_OFF
+ select ROM_UNIFIED_SECTIONS
+ bool
+
+config MX6UL_LITESOM
+ bool
+ select MX6UL
+ select DM
+ select DM_THERMAL
+ select SUPPORT_SPL
+
+config MX6UL_OPOS6UL
+ bool
+ select MX6UL
+ select BOARD_LATE_INIT
+ select DM
+ select DM_GPIO
+ select DM_MMC
+ select DM_THERMAL
+ select SUPPORT_SPL
+
+config MX6ULL
+ bool
+ select MX6UL
+
+config MX6_DDRCAL
+ bool "Include dynamic DDR calibration routines"
+ depends on SPL
+ default n
+ help
+ Say "Y" if your board uses dynamic (per-boot) DDR calibration.
+ If unsure, say N.
+
+choice
+ prompt "MX6 board select"
+ optional
+
+config TARGET_ADVANTECH_DMS_BA16
+ bool "Advantech dms-ba16"
+ select BOARD_LATE_INIT
+ select MX6Q
+ imply CMD_SATA
+
+config TARGET_APALIS_IMX6
+ bool "Toradex Apalis iMX6 board"
+ select BOARD_LATE_INIT
+ select SUPPORT_SPL
+ select DM
+ select DM_SERIAL
+ select DM_THERMAL
+ imply CMD_SATA
+
+config TARGET_ARISTAINETOS
+ bool "aristainetos"
+
+config TARGET_ARISTAINETOS2
+ bool "aristainetos2"
+ select BOARD_LATE_INIT
+
+config TARGET_ARISTAINETOS2B
+ bool "Support aristainetos2-revB"
+ select BOARD_LATE_INIT
+
+config TARGET_CGTQMX6EVAL
+ bool "cgtqmx6eval"
+ select BOARD_LATE_INIT
+ select SUPPORT_SPL
+ select DM
+ select DM_THERMAL
+
+config TARGET_CM_FX6
+ bool "CM-FX6"
+ select SUPPORT_SPL
+ select DM
+ select DM_SERIAL
+ select DM_GPIO
+
+config TARGET_COLIBRI_IMX6
+ bool "Toradex Colibri iMX6 board"
+ select BOARD_LATE_INIT
+ select SUPPORT_SPL
+ select DM
+ select DM_SERIAL
+ select DM_THERMAL
+
+config TARGET_EMBESTMX6BOARDS
+ bool "embestmx6boards"
+ select BOARD_LATE_INIT
+
+config TARGET_GE_B450V3
+ bool "General Electric B450v3"
+ select BOARD_LATE_INIT
+ select MX6Q
+
+config TARGET_GE_B650V3
+ bool "General Electric B650v3"
+ select BOARD_LATE_INIT
+ select MX6Q
+
+config TARGET_GE_B850V3
+ bool "General Electric B850v3"
+ select BOARD_LATE_INIT
+ select MX6Q
+
+config TARGET_GW_VENTANA
+ bool "gw_ventana"
+ select SUPPORT_SPL
+ imply CMD_SATA
+
+config TARGET_KOSAGI_NOVENA
+ bool "Kosagi Novena"
+ select BOARD_LATE_INIT
+ select SUPPORT_SPL
+
+config TARGET_MCCMON6
+ bool "mccmon6"
+ select SUPPORT_SPL
+
+config TARGET_MX6CUBOXI
+ bool "Solid-run mx6 boards"
+ select BOARD_LATE_INIT
+ select SUPPORT_SPL
+
+config TARGET_MX6LOGICPD
+ bool "Logic PD i.MX6 SOM"
+ select BOARD_EARLY_INIT_F
+ select BOARD_LATE_INIT
+ select DM
+ select DM_ETH
+ select DM_GPIO
+ select DM_I2C
+ select DM_MMC
+ select DM_PMIC
+ select DM_REGULATOR
+ select OF_CONTROL
+
+config TARGET_MX6QARM2
+ bool "mx6qarm2"
+
+config TARGET_MX6Q_ICORE
+ bool "Support Engicam i.Core"
+ select BOARD_LATE_INIT
+ select MX6QDL
+ select OF_CONTROL
+ select SPL_OF_LIBFDT
+ select DM
+ select DM_ETH
+ select DM_GPIO
+ select DM_I2C
+ select DM_MMC
+ select DM_THERMAL
+ select SUPPORT_SPL
+ select SPL_LOAD_FIT
+
+config TARGET_MX6Q_ICORE_RQS
+ bool "Support Engicam i.Core RQS"
+ select BOARD_LATE_INIT
+ select MX6QDL
+ select OF_CONTROL
+ select SPL_OF_LIBFDT
+ select DM
+ select DM_ETH
+ select DM_GPIO
+ select DM_I2C
+ select DM_MMC
+ select DM_THERMAL
+ select SUPPORT_SPL
+ select SPL_LOAD_FIT
+
+config TARGET_MX6SABREAUTO
+ bool "mx6sabreauto"
+ select BOARD_LATE_INIT
+ select SUPPORT_SPL
+ select DM
+ select DM_THERMAL
+ select BOARD_EARLY_INIT_F
+
+config TARGET_MX6SABRESD
+ bool "mx6sabresd"
+ select BOARD_LATE_INIT
+ select SUPPORT_SPL
+ select DM
+ select DM_THERMAL
+ select BOARD_EARLY_INIT_F
+
+config TARGET_MX6SLEVK
+ bool "mx6slevk"
+ select SUPPORT_SPL
+
+config TARGET_MX6SLLEVK
+ bool "mx6sll evk"
+ select BOARD_LATE_INIT
+ select MX6SLL
+ select DM
+ select DM_THERMAL
+
+config TARGET_MX6SXSABRESD
+ bool "mx6sxsabresd"
+ select MX6SX
+ select SUPPORT_SPL
+ select DM
+ select DM_THERMAL
+ select BOARD_EARLY_INIT_F
+
+config TARGET_MX6SXSABREAUTO
+ bool "mx6sxsabreauto"
+ select BOARD_LATE_INIT
+ select MX6SX
+ select DM
+ select DM_THERMAL
+ select BOARD_EARLY_INIT_F
+
+config TARGET_MX6UL_9X9_EVK
+ bool "mx6ul_9x9_evk"
+ select BOARD_LATE_INIT
+ select MX6UL
+ select DM
+ select DM_THERMAL
+ select SUPPORT_SPL
+
+config TARGET_MX6UL_14X14_EVK
+ select BOARD_LATE_INIT
+ bool "mx6ul_14x14_evk"
+ select MX6UL
+ select DM
+ select DM_THERMAL
+ select SUPPORT_SPL
+
+config TARGET_MX6UL_GEAM
+ bool "Support Engicam GEAM6UL"
+ select BOARD_LATE_INIT
+ select MX6UL
+ select OF_CONTROL
+ select DM
+ select DM_ETH
+ select DM_GPIO
+ select DM_I2C
+ select DM_MMC
+ select DM_THERMAL
+ select SUPPORT_SPL
+config TARGET_MX6UL_ISIOT
+ bool "Support Engicam Is.IoT MX6UL"
+ select BOARD_LATE_INIT
+ select MX6UL
+ select OF_CONTROL
+ select DM
+ select DM_ETH
+ select DM_GPIO
+ select DM_I2C
+ select DM_MMC
+ select DM_THERMAL
+ select SUPPORT_SPL
+
+config TARGET_MX6ULL_14X14_EVK
+ bool "Support mx6ull_14x14_evk"
+ select BOARD_LATE_INIT
+ select MX6ULL
+ select DM
+ select DM_THERMAL
+
+config TARGET_NITROGEN6X
+ bool "nitrogen6x"
+
+config TARGET_OPOS6ULDEV
+ bool "Armadeus OPOS6ULDev board"
+ select MX6UL_OPOS6UL
+
+config TARGET_OT1200
+ bool "Bachmann OT1200"
+ select SUPPORT_SPL
+ imply CMD_SATA
+
+config TARGET_PICO_IMX6UL
+ bool "PICO-IMX6UL-EMMC"
+ select MX6UL
+
+config TARGET_LITEBOARD
+ bool "Grinn liteBoard (i.MX6UL)"
+ select BOARD_LATE_INIT
+ select MX6UL_LITESOM
+
+config TARGET_PLATINUM_PICON
+ bool "platinum-picon"
+ select SUPPORT_SPL
+
+config TARGET_PLATINUM_TITANIUM
+ bool "platinum-titanium"
+ select SUPPORT_SPL
+
+config TARGET_PCM058
+ bool "Phytec PCM058 i.MX6 Quad"
+ select BOARD_LATE_INIT
+ select SUPPORT_SPL
+
+config TARGET_SECOMX6
+ bool "secomx6 boards"
+
+config TARGET_TBS2910
+ bool "TBS2910 Matrix ARM mini PC"
+
+config TARGET_TITANIUM
+ bool "titanium"
+
+config TARGET_TQMA6
+ bool "TQ Systems TQMa6 board"
+ select BOARD_LATE_INIT
+
+config TARGET_UDOO
+ bool "udoo"
+ select BOARD_LATE_INIT
+ select SUPPORT_SPL
+
+config TARGET_UDOO_NEO
+ bool "UDOO Neo"
+ select BOARD_LATE_INIT
+ select SUPPORT_SPL
+ select MX6SX
+ select DM
+ select DM_THERMAL
+
+config TARGET_SAMTEC_VINING_2000
+ bool "samtec VIN|ING 2000"
+ select BOARD_LATE_INIT
+ select MX6SX
+ select DM
+ select DM_THERMAL
+
+config TARGET_WANDBOARD
+ bool "wandboard"
+ select BOARD_LATE_INIT
+ select SUPPORT_SPL
+
+config TARGET_WARP
+ bool "WaRP"
+ select BOARD_LATE_INIT
+
+config TARGET_XPRESS
+ bool "CCV xPress"
+ select BOARD_LATE_INIT
+ select MX6UL
+ select DM
+ select DM_THERMAL
+ select SUPPORT_SPL
+
+config TARGET_ZC5202
+ bool "zc5202"
+ select BOARD_LATE_INIT
+ select SUPPORT_SPL
+ select DM
+ select DM_THERMAL
+
+config TARGET_ZC5601
+ bool "zc5601"
+ select BOARD_LATE_INIT
+ select SUPPORT_SPL
+ select DM
+ select DM_THERMAL
+
+endchoice
+
+config SYS_SOC
+ default "mx6"
+
+source "board/ge/bx50v3/Kconfig"
+source "board/advantech/dms-ba16/Kconfig"
+source "board/aristainetos/Kconfig"
+source "board/armadeus/opos6uldev/Kconfig"
+source "board/bachmann/ot1200/Kconfig"
+source "board/barco/platinum/Kconfig"
+source "board/barco/titanium/Kconfig"
+source "board/boundary/nitrogen6x/Kconfig"
+source "board/ccv/xpress/Kconfig"
+source "board/compulab/cm_fx6/Kconfig"
+source "board/congatec/cgtqmx6eval/Kconfig"
+source "board/el/el6x/Kconfig"
+source "board/embest/mx6boards/Kconfig"
+source "board/engicam/geam6ul/Kconfig"
+source "board/engicam/icorem6/Kconfig"
+source "board/engicam/icorem6_rqs/Kconfig"
+source "board/engicam/isiotmx6ul/Kconfig"
+source "board/freescale/mx6qarm2/Kconfig"
+source "board/freescale/mx6sabreauto/Kconfig"
+source "board/freescale/mx6sabresd/Kconfig"
+source "board/freescale/mx6slevk/Kconfig"
+source "board/freescale/mx6sllevk/Kconfig"
+source "board/freescale/mx6sxsabresd/Kconfig"
+source "board/freescale/mx6sxsabreauto/Kconfig"
+source "board/freescale/mx6ul_14x14_evk/Kconfig"
+source "board/freescale/mx6ullevk/Kconfig"
+source "board/grinn/liteboard/Kconfig"
+source "board/phytec/pcm058/Kconfig"
+source "board/gateworks/gw_ventana/Kconfig"
+source "board/kosagi/novena/Kconfig"
+source "board/samtec/vining_2000/Kconfig"
+source "board/liebherr/mccmon6/Kconfig"
+source "board/logicpd/imx6/Kconfig"
+source "board/seco/Kconfig"
+source "board/solidrun/mx6cuboxi/Kconfig"
+source "board/technexion/pico-imx6ul/Kconfig"
+source "board/tbs/tbs2910/Kconfig"
+source "board/tqc/tqma6/Kconfig"
+source "board/toradex/apalis_imx6/Kconfig"
+source "board/toradex/colibri_imx6/Kconfig"
+source "board/udoo/Kconfig"
+source "board/udoo/neo/Kconfig"
+source "board/wandboard/Kconfig"
+source "board/warp/Kconfig"
+
+endif
--- /dev/null
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := soc.o clock.o
+obj-$(CONFIG_SPL_BUILD) += ddr.o
+obj-$(CONFIG_MP) += mp.o
+obj-$(CONFIG_MX6UL_LITESOM) += litesom.o
+obj-$(CONFIG_MX6UL_OPOS6UL) += opos6ul.o
--- /dev/null
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+
+enum pll_clocks {
+ PLL_SYS, /* System PLL */
+ PLL_BUS, /* System Bus PLL*/
+ PLL_USBOTG, /* OTG USB PLL */
+ PLL_ENET, /* ENET PLL */
+ PLL_AUDIO, /* AUDIO PLL */
+ PLL_VIDEO, /* AUDIO PLL */
+};
+
+struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+#ifdef CONFIG_MXC_OCOTP
+void enable_ocotp_clk(unsigned char enable)
+{
+ u32 reg;
+
+ reg = __raw_readl(&imx_ccm->CCGR2);
+ if (enable)
+ reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
+ else
+ reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
+ __raw_writel(reg, &imx_ccm->CCGR2);
+}
+#endif
+
+#ifdef CONFIG_NAND_MXS
+void setup_gpmi_io_clk(u32 cfg)
+{
+ /* Disable clocks per ERR007177 from MX6 errata */
+ clrbits_le32(&imx_ccm->CCGR4,
+ MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+ MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
+
+#if defined(CONFIG_MX6SX)
+ clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
+
+ clrsetbits_le32(&imx_ccm->cs2cdr,
+ MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
+ MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
+ MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK,
+ cfg);
+
+ setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
+#else
+ clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+
+ clrsetbits_le32(&imx_ccm->cs2cdr,
+ MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
+ MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
+ cfg);
+
+ setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+#endif
+ setbits_le32(&imx_ccm->CCGR4,
+ MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+ MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
+}
+#endif
+
+void enable_usboh3_clk(unsigned char enable)
+{
+ u32 reg;
+
+ reg = __raw_readl(&imx_ccm->CCGR6);
+ if (enable)
+ reg |= MXC_CCM_CCGR6_USBOH3_MASK;
+ else
+ reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
+ __raw_writel(reg, &imx_ccm->CCGR6);
+
+}
+
+#if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
+void enable_enet_clk(unsigned char enable)
+{
+ u32 mask, *addr;
+
+ if (is_mx6ull()) {
+ mask = MXC_CCM_CCGR0_ENET_CLK_ENABLE_MASK;
+ addr = &imx_ccm->CCGR0;
+ } else if (is_mx6ul()) {
+ mask = MXC_CCM_CCGR3_ENET_MASK;
+ addr = &imx_ccm->CCGR3;
+ } else {
+ mask = MXC_CCM_CCGR1_ENET_MASK;
+ addr = &imx_ccm->CCGR1;
+ }
+
+ if (enable)
+ setbits_le32(addr, mask);
+ else
+ clrbits_le32(addr, mask);
+}
+#endif
+
+#ifdef CONFIG_MXC_UART
+void enable_uart_clk(unsigned char enable)
+{
+ u32 mask;
+
+ if (is_mx6ul() || is_mx6ull())
+ mask = MXC_CCM_CCGR5_UART_MASK;
+ else
+ mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
+
+ if (enable)
+ setbits_le32(&imx_ccm->CCGR5, mask);
+ else
+ clrbits_le32(&imx_ccm->CCGR5, mask);
+}
+#endif
+
+#ifdef CONFIG_MMC
+int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
+{
+ u32 mask;
+
+ if (bus_num > 3)
+ return -EINVAL;
+
+ mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
+ if (enable)
+ setbits_le32(&imx_ccm->CCGR6, mask);
+ else
+ clrbits_le32(&imx_ccm->CCGR6, mask);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SYS_I2C_MXC
+/* i2c_num can be from 0 - 3 */
+int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
+{
+ u32 reg;
+ u32 mask;
+ u32 *addr;
+
+ if (i2c_num > 3)
+ return -EINVAL;
+ if (i2c_num < 3) {
+ mask = MXC_CCM_CCGR_CG_MASK
+ << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
+ + (i2c_num << 1));
+ reg = __raw_readl(&imx_ccm->CCGR2);
+ if (enable)
+ reg |= mask;
+ else
+ reg &= ~mask;
+ __raw_writel(reg, &imx_ccm->CCGR2);
+ } else {
+ if (is_mx6sll())
+ return -EINVAL;
+ if (is_mx6sx() || is_mx6ul() || is_mx6ull()) {
+ mask = MXC_CCM_CCGR6_I2C4_MASK;
+ addr = &imx_ccm->CCGR6;
+ } else {
+ mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
+ addr = &imx_ccm->CCGR1;
+ }
+ reg = __raw_readl(addr);
+ if (enable)
+ reg |= mask;
+ else
+ reg &= ~mask;
+ __raw_writel(reg, addr);
+ }
+ return 0;
+}
+#endif
+
+/* spi_num can be from 0 - SPI_MAX_NUM */
+int enable_spi_clk(unsigned char enable, unsigned spi_num)
+{
+ u32 reg;
+ u32 mask;
+
+ if (spi_num > SPI_MAX_NUM)
+ return -EINVAL;
+
+ mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
+ reg = __raw_readl(&imx_ccm->CCGR1);
+ if (enable)
+ reg |= mask;
+ else
+ reg &= ~mask;
+ __raw_writel(reg, &imx_ccm->CCGR1);
+ return 0;
+}
+static u32 decode_pll(enum pll_clocks pll, u32 infreq)
+{
+ u32 div, test_div, pll_num, pll_denom;
+
+ switch (pll) {
+ case PLL_SYS:
+ div = __raw_readl(&imx_ccm->analog_pll_sys);
+ div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
+
+ return (infreq * div) >> 1;
+ case PLL_BUS:
+ div = __raw_readl(&imx_ccm->analog_pll_528);
+ div &= BM_ANADIG_PLL_528_DIV_SELECT;
+
+ return infreq * (20 + (div << 1));
+ case PLL_USBOTG:
+ div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
+ div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
+
+ return infreq * (20 + (div << 1));
+ case PLL_ENET:
+ div = __raw_readl(&imx_ccm->analog_pll_enet);
+ div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
+
+ return 25000000 * (div + (div >> 1) + 1);
+ case PLL_AUDIO:
+ div = __raw_readl(&imx_ccm->analog_pll_audio);
+ if (!(div & BM_ANADIG_PLL_AUDIO_ENABLE))
+ return 0;
+ /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
+ if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
+ return MXC_HCLK;
+ pll_num = __raw_readl(&imx_ccm->analog_pll_audio_num);
+ pll_denom = __raw_readl(&imx_ccm->analog_pll_audio_denom);
+ test_div = (div & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) >>
+ BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT;
+ div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
+ if (test_div == 3) {
+ debug("Error test_div\n");
+ return 0;
+ }
+ test_div = 1 << (2 - test_div);
+
+ return infreq * (div + pll_num / pll_denom) / test_div;
+ case PLL_VIDEO:
+ div = __raw_readl(&imx_ccm->analog_pll_video);
+ if (!(div & BM_ANADIG_PLL_VIDEO_ENABLE))
+ return 0;
+ /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
+ if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
+ return MXC_HCLK;
+ pll_num = __raw_readl(&imx_ccm->analog_pll_video_num);
+ pll_denom = __raw_readl(&imx_ccm->analog_pll_video_denom);
+ test_div = (div & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) >>
+ BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
+ div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
+ if (test_div == 3) {
+ debug("Error test_div\n");
+ return 0;
+ }
+ test_div = 1 << (2 - test_div);
+
+ return infreq * (div + pll_num / pll_denom) / test_div;
+ default:
+ return 0;
+ }
+ /* NOTREACHED */
+}
+static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
+{
+ u32 div;
+ u64 freq;
+
+ switch (pll) {
+ case PLL_BUS:
+ if (!is_mx6ul() && !is_mx6ull()) {
+ if (pfd_num == 3) {
+ /* No PFD3 on PLL2 */
+ return 0;
+ }
+ }
+ div = __raw_readl(&imx_ccm->analog_pfd_528);
+ freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
+ break;
+ case PLL_USBOTG:
+ div = __raw_readl(&imx_ccm->analog_pfd_480);
+ freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
+ break;
+ default:
+ /* No PFD on other PLL */
+ return 0;
+ }
+
+ return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
+ ANATOP_PFD_FRAC_SHIFT(pfd_num));
+}
+
+static u32 get_mcu_main_clk(void)
+{
+ u32 reg, freq;
+
+ reg = __raw_readl(&imx_ccm->cacrr);
+ reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
+ reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
+ freq = decode_pll(PLL_SYS, MXC_HCLK);
+
+ return freq / (reg + 1);
+}
+
+u32 get_periph_clk(void)
+{
+ u32 reg, div = 0, freq = 0;
+
+ reg = __raw_readl(&imx_ccm->cbcdr);
+ if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
+ div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
+ MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
+ reg = __raw_readl(&imx_ccm->cbcmr);
+ reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
+ reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
+
+ switch (reg) {
+ case 0:
+ freq = decode_pll(PLL_USBOTG, MXC_HCLK);
+ break;
+ case 1:
+ case 2:
+ freq = MXC_HCLK;
+ break;
+ default:
+ break;
+ }
+ } else {
+ reg = __raw_readl(&imx_ccm->cbcmr);
+ reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
+ reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
+
+ switch (reg) {
+ case 0:
+ freq = decode_pll(PLL_BUS, MXC_HCLK);
+ break;
+ case 1:
+ freq = mxc_get_pll_pfd(PLL_BUS, 2);
+ break;
+ case 2:
+ freq = mxc_get_pll_pfd(PLL_BUS, 0);
+ break;
+ case 3:
+ /* static / 2 divider */
+ freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
+ break;
+ default:
+ break;
+ }
+ }
+
+ return freq / (div + 1);
+}
+
+static u32 get_ipg_clk(void)
+{
+ u32 reg, ipg_podf;
+
+ reg = __raw_readl(&imx_ccm->cbcdr);
+ reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
+ ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
+
+ return get_ahb_clk() / (ipg_podf + 1);
+}
+
+static u32 get_ipg_per_clk(void)
+{
+ u32 reg, perclk_podf;
+
+ reg = __raw_readl(&imx_ccm->cscmr1);
+ if (is_mx6sll() || is_mx6sl() || is_mx6sx() ||
+ is_mx6dqp() || is_mx6ul() || is_mx6ull()) {
+ if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
+ return MXC_HCLK; /* OSC 24Mhz */
+ }
+
+ perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
+
+ return get_ipg_clk() / (perclk_podf + 1);
+}
+
+static u32 get_uart_clk(void)
+{
+ u32 reg, uart_podf;
+ u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
+ reg = __raw_readl(&imx_ccm->cscdr1);
+
+ if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul() ||
+ is_mx6sll() || is_mx6ull()) {
+ if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
+ freq = MXC_HCLK;
+ }
+
+ reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
+ uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
+
+ return freq / (uart_podf + 1);
+}
+
+static u32 get_cspi_clk(void)
+{
+ u32 reg, cspi_podf;
+
+ reg = __raw_readl(&imx_ccm->cscdr2);
+ cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
+ MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
+
+ if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul() ||
+ is_mx6sll() || is_mx6ull()) {
+ if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
+ return MXC_HCLK / (cspi_podf + 1);
+ }
+
+ return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
+}
+
+static u32 get_axi_clk(void)
+{
+ u32 root_freq, axi_podf;
+ u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
+
+ axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
+ axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
+
+ if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
+ if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
+ root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
+ else
+ root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
+ } else
+ root_freq = get_periph_clk();
+
+ return root_freq / (axi_podf + 1);
+}
+
+static u32 get_emi_slow_clk(void)
+{
+ u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
+
+ cscmr1 = __raw_readl(&imx_ccm->cscmr1);
+ emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
+ emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
+ emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
+ emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
+
+ switch (emi_clk_sel) {
+ case 0:
+ root_freq = get_axi_clk();
+ break;
+ case 1:
+ root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
+ break;
+ case 2:
+ root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
+ break;
+ case 3:
+ root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
+ break;
+ }
+
+ return root_freq / (emi_slow_podf + 1);
+}
+
+static u32 get_mmdc_ch0_clk(void)
+{
+ u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
+ u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
+
+ u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div;
+
+ if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl() ||
+ is_mx6sll()) {
+ podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
+ MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
+ if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
+ per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
+ MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
+ if (is_mx6sl()) {
+ if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
+ freq = MXC_HCLK;
+ else
+ freq = decode_pll(PLL_USBOTG, MXC_HCLK);
+ } else {
+ if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
+ freq = decode_pll(PLL_BUS, MXC_HCLK);
+ else
+ freq = decode_pll(PLL_USBOTG, MXC_HCLK);
+ }
+ } else {
+ per2_clk2_podf = 0;
+ switch ((cbcmr &
+ MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
+ MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
+ case 0:
+ freq = decode_pll(PLL_BUS, MXC_HCLK);
+ break;
+ case 1:
+ freq = mxc_get_pll_pfd(PLL_BUS, 2);
+ break;
+ case 2:
+ freq = mxc_get_pll_pfd(PLL_BUS, 0);
+ break;
+ case 3:
+ if (is_mx6sl()) {
+ freq = mxc_get_pll_pfd(PLL_BUS, 2) >> 1;
+ break;
+ }
+
+ pmu_misc2_audio_div = PMU_MISC2_AUDIO_DIV(__raw_readl(&imx_ccm->pmu_misc2));
+ switch (pmu_misc2_audio_div) {
+ case 0:
+ case 2:
+ pmu_misc2_audio_div = 1;
+ break;
+ case 1:
+ pmu_misc2_audio_div = 2;
+ break;
+ case 3:
+ pmu_misc2_audio_div = 4;
+ break;
+ }
+ freq = decode_pll(PLL_AUDIO, MXC_HCLK) /
+ pmu_misc2_audio_div;
+ break;
+ }
+ }
+ return freq / (podf + 1) / (per2_clk2_podf + 1);
+ } else {
+ podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
+ MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
+ return get_periph_clk() / (podf + 1);
+ }
+}
+
+#if defined(CONFIG_VIDEO_MXS)
+static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom,
+ u32 post_div)
+{
+ u32 reg = 0;
+ ulong start;
+
+ debug("pll5 div = %d, num = %d, denom = %d\n",
+ pll_div, pll_num, pll_denom);
+
+ /* Power up PLL5 video */
+ writel(BM_ANADIG_PLL_VIDEO_POWERDOWN |
+ BM_ANADIG_PLL_VIDEO_BYPASS |
+ BM_ANADIG_PLL_VIDEO_DIV_SELECT |
+ BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
+ &imx_ccm->analog_pll_video_clr);
+
+ /* Set div, num and denom */
+ switch (post_div) {
+ case 1:
+ writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
+ BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x2),
+ &imx_ccm->analog_pll_video_set);
+ break;
+ case 2:
+ writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
+ BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x1),
+ &imx_ccm->analog_pll_video_set);
+ break;
+ case 4:
+ writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
+ BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x0),
+ &imx_ccm->analog_pll_video_set);
+ break;
+ default:
+ puts("Wrong test_div!\n");
+ return -EINVAL;
+ }
+
+ writel(BF_ANADIG_PLL_VIDEO_NUM_A(pll_num),
+ &imx_ccm->analog_pll_video_num);
+ writel(BF_ANADIG_PLL_VIDEO_DENOM_B(pll_denom),
+ &imx_ccm->analog_pll_video_denom);
+
+ /* Wait PLL5 lock */
+ start = get_timer(0); /* Get current timestamp */
+
+ do {
+ reg = readl(&imx_ccm->analog_pll_video);
+ if (reg & BM_ANADIG_PLL_VIDEO_LOCK) {
+ /* Enable PLL out */
+ writel(BM_ANADIG_PLL_VIDEO_ENABLE,
+ &imx_ccm->analog_pll_video_set);
+ return 0;
+ }
+ } while (get_timer(0) < (start + 10)); /* Wait 10ms */
+
+ puts("Lock PLL5 timeout\n");
+
+ return -ETIME;
+}
+
+/*
+ * 24M--> PLL_VIDEO -> LCDIFx_PRED -> LCDIFx_PODF -> LCD
+ *
+ * 'freq' using KHz as unit, see driver/video/mxsfb.c.
+ */
+void mxs_set_lcdclk(u32 base_addr, u32 freq)
+{
+ u32 reg = 0;
+ u32 hck = MXC_HCLK / 1000;
+ /* DIV_SELECT ranges from 27 to 54 */
+ u32 min = hck * 27;
+ u32 max = hck * 54;
+ u32 temp, best = 0;
+ u32 i, j, max_pred = 8, max_postd = 8, pred = 1, postd = 1;
+ u32 pll_div, pll_num, pll_denom, post_div = 1;
+
+ debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
+
+ if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl() &&
+ !is_mx6sll()) {
+ debug("This chip not support lcd!\n");
+ return;
+ }
+
+ if (!is_mx6sl()) {
+ if (base_addr == LCDIF1_BASE_ADDR) {
+ reg = readl(&imx_ccm->cscdr2);
+ /* Can't change clocks when clock not from pre-mux */
+ if ((reg & MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) != 0)
+ return;
+ }
+ }
+
+ if (is_mx6sx()) {
+ reg = readl(&imx_ccm->cscdr2);
+ /* Can't change clocks when clock not from pre-mux */
+ if ((reg & MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK) != 0)
+ return;
+ }
+
+ temp = freq * max_pred * max_postd;
+ if (temp < min) {
+ /*
+ * Register: PLL_VIDEO
+ * Bit Field: POST_DIV_SELECT
+ * 00 — Divide by 4.
+ * 01 — Divide by 2.
+ * 10 — Divide by 1.
+ * 11 — Reserved
+ * No need to check post_div(1)
+ */
+ for (post_div = 2; post_div <= 4; post_div <<= 1) {
+ if ((temp * post_div) > min) {
+ freq *= post_div;
+ break;
+ }
+ }
+
+ if (post_div > 4) {
+ printf("Fail to set rate to %dkhz", freq);
+ return;
+ }
+ }
+
+ /* Choose the best pred and postd to match freq for lcd */
+ for (i = 1; i <= max_pred; i++) {
+ for (j = 1; j <= max_postd; j++) {
+ temp = freq * i * j;
+ if (temp > max || temp < min)
+ continue;
+ if (best == 0 || temp < best) {
+ best = temp;
+ pred = i;
+ postd = j;
+ }
+ }
+ }
+
+ if (best == 0) {
+ printf("Fail to set rate to %dKHz", freq);
+ return;
+ }
+
+ debug("best %d, pred = %d, postd = %d\n", best, pred, postd);
+
+ pll_div = best / hck;
+ pll_denom = 1000000;
+ pll_num = (best - hck * pll_div) * pll_denom / hck;
+
+ /*
+ * pll_num
+ * (24MHz * (pll_div + --------- ))
+ * pll_denom
+ *freq KHz = --------------------------------
+ * post_div * pred * postd * 1000
+ */
+
+ if (base_addr == LCDIF1_BASE_ADDR) {
+ if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
+ return;
+
+ enable_lcdif_clock(base_addr, 0);
+ if (!is_mx6sl()) {
+ /* Select pre-lcd clock to PLL5 and set pre divider */
+ clrsetbits_le32(&imx_ccm->cscdr2,
+ MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK |
+ MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK,
+ (0x2 << MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET) |
+ ((pred - 1) <<
+ MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET));
+
+ /* Set the post divider */
+ clrsetbits_le32(&imx_ccm->cbcmr,
+ MXC_CCM_CBCMR_LCDIF1_PODF_MASK,
+ ((postd - 1) <<
+ MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET));
+ } else {
+ /* Select pre-lcd clock to PLL5 and set pre divider */
+ clrsetbits_le32(&imx_ccm->cscdr2,
+ MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_MASK |
+ MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_MASK,
+ (0x2 << MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_OFFSET) |
+ ((pred - 1) <<
+ MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_OFFSET));
+
+ /* Set the post divider */
+ clrsetbits_le32(&imx_ccm->cscmr1,
+ MXC_CCM_CSCMR1_LCDIF_PIX_PODF_MASK,
+ (((postd - 1)^0x6) <<
+ MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET));
+ }
+
+ enable_lcdif_clock(base_addr, 1);
+ } else if (is_mx6sx()) {
+ /* Setting LCDIF2 for i.MX6SX */
+ if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
+ return;
+
+ enable_lcdif_clock(base_addr, 0);
+ /* Select pre-lcd clock to PLL5 and set pre divider */
+ clrsetbits_le32(&imx_ccm->cscdr2,
+ MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK |
+ MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK,
+ (0x2 << MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET) |
+ ((pred - 1) <<
+ MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET));
+
+ /* Set the post divider */
+ clrsetbits_le32(&imx_ccm->cscmr1,
+ MXC_CCM_CSCMR1_LCDIF2_PODF_MASK,
+ ((postd - 1) <<
+ MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET));
+
+ enable_lcdif_clock(base_addr, 1);
+ }
+}
+
+int enable_lcdif_clock(u32 base_addr, bool enable)
+{
+ u32 reg = 0;
+ u32 lcdif_clk_sel_mask, lcdif_ccgr3_mask;
+
+ if (is_mx6sx()) {
+ if ((base_addr != LCDIF1_BASE_ADDR) &&
+ (base_addr != LCDIF2_BASE_ADDR)) {
+ puts("Wrong LCD interface!\n");
+ return -EINVAL;
+ }
+ /* Set to pre-mux clock at default */
+ lcdif_clk_sel_mask = (base_addr == LCDIF2_BASE_ADDR) ?
+ MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK :
+ MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
+ lcdif_ccgr3_mask = (base_addr == LCDIF2_BASE_ADDR) ?
+ (MXC_CCM_CCGR3_LCDIF2_PIX_MASK |
+ MXC_CCM_CCGR3_DISP_AXI_MASK) :
+ (MXC_CCM_CCGR3_LCDIF1_PIX_MASK |
+ MXC_CCM_CCGR3_DISP_AXI_MASK);
+ } else if (is_mx6ul() || is_mx6ull() || is_mx6sll()) {
+ if (base_addr != LCDIF1_BASE_ADDR) {
+ puts("Wrong LCD interface!\n");
+ return -EINVAL;
+ }
+ /* Set to pre-mux clock at default */
+ lcdif_clk_sel_mask = MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
+ lcdif_ccgr3_mask = MXC_CCM_CCGR3_LCDIF1_PIX_MASK;
+ } else if (is_mx6sl()) {
+ if (base_addr != LCDIF1_BASE_ADDR) {
+ puts("Wrong LCD interface!\n");
+ return -EINVAL;
+ }
+
+ reg = readl(&imx_ccm->CCGR3);
+ reg &= ~(MXC_CCM_CCGR3_LCDIF_AXI_MASK |
+ MXC_CCM_CCGR3_LCDIF_PIX_MASK);
+ writel(reg, &imx_ccm->CCGR3);
+
+ if (enable) {
+ reg = readl(&imx_ccm->cscdr3);
+ reg &= ~MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK;
+ reg |= 1 << MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET;
+ writel(reg, &imx_ccm->cscdr3);
+
+ reg = readl(&imx_ccm->CCGR3);
+ reg |= MXC_CCM_CCGR3_LCDIF_AXI_MASK |
+ MXC_CCM_CCGR3_LCDIF_PIX_MASK;
+ writel(reg, &imx_ccm->CCGR3);
+ }
+
+ return 0;
+ } else {
+ return 0;
+ }
+
+ /* Gate LCDIF clock first */
+ reg = readl(&imx_ccm->CCGR3);
+ reg &= ~lcdif_ccgr3_mask;
+ writel(reg, &imx_ccm->CCGR3);
+
+ reg = readl(&imx_ccm->CCGR2);
+ reg &= ~MXC_CCM_CCGR2_LCD_MASK;
+ writel(reg, &imx_ccm->CCGR2);
+
+ if (enable) {
+ /* Select pre-mux */
+ reg = readl(&imx_ccm->cscdr2);
+ reg &= ~lcdif_clk_sel_mask;
+ writel(reg, &imx_ccm->cscdr2);
+
+ /* Enable the LCDIF pix clock */
+ reg = readl(&imx_ccm->CCGR3);
+ reg |= lcdif_ccgr3_mask;
+ writel(reg, &imx_ccm->CCGR3);
+
+ reg = readl(&imx_ccm->CCGR2);
+ reg |= MXC_CCM_CCGR2_LCD_MASK;
+ writel(reg, &imx_ccm->CCGR2);
+ }
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+/* qspi_num can be from 0 - 1 */
+void enable_qspi_clk(int qspi_num)
+{
+ u32 reg = 0;
+ /* Enable QuadSPI clock */
+ switch (qspi_num) {
+ case 0:
+ /* disable the clock gate */
+ clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
+
+ /* set 50M : (50 = 396 / 2 / 4) */
+ reg = readl(&imx_ccm->cscmr1);
+ reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
+ MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
+ reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
+ (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
+ writel(reg, &imx_ccm->cscmr1);
+
+ /* enable the clock gate */
+ setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
+ break;
+ case 1:
+ /*
+ * disable the clock gate
+ * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
+ * disable both of them.
+ */
+ clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
+
+ /* set 50M : (50 = 396 / 2 / 4) */
+ reg = readl(&imx_ccm->cs2cdr);
+ reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
+ MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
+ MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
+ reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
+ MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
+ writel(reg, &imx_ccm->cs2cdr);
+
+ /*enable the clock gate*/
+ setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
+ break;
+ default:
+ break;
+ }
+}
+#endif
+
+#ifdef CONFIG_FEC_MXC
+int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
+{
+ u32 reg = 0;
+ s32 timeout = 100000;
+
+ struct anatop_regs __iomem *anatop =
+ (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
+
+ if (freq < ENET_25MHZ || freq > ENET_125MHZ)
+ return -EINVAL;
+
+ reg = readl(&anatop->pll_enet);
+
+ if (fec_id == 0) {
+ reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
+ reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
+ } else if (fec_id == 1) {
+ /* Only i.MX6SX/UL support ENET2 */
+ if (!(is_mx6sx() || is_mx6ul() || is_mx6ull()))
+ return -EINVAL;
+ reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
+ reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
+ } else {
+ return -EINVAL;
+ }
+
+ if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
+ (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
+ reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
+ writel(reg, &anatop->pll_enet);
+ while (timeout--) {
+ if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
+ break;
+ }
+ if (timeout < 0)
+ return -ETIMEDOUT;
+ }
+
+ /* Enable FEC clock */
+ if (fec_id == 0)
+ reg |= BM_ANADIG_PLL_ENET_ENABLE;
+ else
+ reg |= BM_ANADIG_PLL_ENET2_ENABLE;
+ reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
+ writel(reg, &anatop->pll_enet);
+
+#ifdef CONFIG_MX6SX
+ /* Disable enet system clcok before switching clock parent */
+ reg = readl(&imx_ccm->CCGR3);
+ reg &= ~MXC_CCM_CCGR3_ENET_MASK;
+ writel(reg, &imx_ccm->CCGR3);
+
+ /*
+ * Set enet ahb clock to 200MHz
+ * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
+ */
+ reg = readl(&imx_ccm->chsccdr);
+ reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
+ | MXC_CCM_CHSCCDR_ENET_PODF_MASK
+ | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
+ /* PLL2 PFD2 */
+ reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
+ /* Div = 2*/
+ reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
+ reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
+ writel(reg, &imx_ccm->chsccdr);
+
+ /* Enable enet system clock */
+ reg = readl(&imx_ccm->CCGR3);
+ reg |= MXC_CCM_CCGR3_ENET_MASK;
+ writel(reg, &imx_ccm->CCGR3);
+#endif
+ return 0;
+}
+#endif
+
+static u32 get_usdhc_clk(u32 port)
+{
+ u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
+ u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
+ u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
+
+ if (is_mx6ul() || is_mx6ull()) {
+ if (port > 1)
+ return 0;
+ }
+
+ if (is_mx6sll()) {
+ if (port > 2)
+ return 0;
+ }
+
+ switch (port) {
+ case 0:
+ usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
+ MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
+ clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
+
+ break;
+ case 1:
+ usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
+ MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
+ clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
+
+ break;
+ case 2:
+ usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
+ MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
+ clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
+
+ break;
+ case 3:
+ usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
+ MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
+ clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
+
+ break;
+ default:
+ break;
+ }
+
+ if (clk_sel)
+ root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
+ else
+ root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
+
+ return root_freq / (usdhc_podf + 1);
+}
+
+u32 imx_get_uartclk(void)
+{
+ return get_uart_clk();
+}
+
+u32 imx_get_fecclk(void)
+{
+ return mxc_get_clock(MXC_IPG_CLK);
+}
+
+#if defined(CONFIG_SATA) || defined(CONFIG_PCIE_IMX)
+static int enable_enet_pll(uint32_t en)
+{
+ struct mxc_ccm_reg *const imx_ccm
+ = (struct mxc_ccm_reg *) CCM_BASE_ADDR;
+ s32 timeout = 100000;
+ u32 reg = 0;
+
+ /* Enable PLLs */
+ reg = readl(&imx_ccm->analog_pll_enet);
+ reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
+ writel(reg, &imx_ccm->analog_pll_enet);
+ reg |= BM_ANADIG_PLL_SYS_ENABLE;
+ while (timeout--) {
+ if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
+ break;
+ }
+ if (timeout <= 0)
+ return -EIO;
+ reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
+ writel(reg, &imx_ccm->analog_pll_enet);
+ reg |= en;
+ writel(reg, &imx_ccm->analog_pll_enet);
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SATA
+static void ungate_sata_clock(void)
+{
+ struct mxc_ccm_reg *const imx_ccm =
+ (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ /* Enable SATA clock. */
+ setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
+}
+
+int enable_sata_clock(void)
+{
+ ungate_sata_clock();
+ return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
+}
+
+void disable_sata_clock(void)
+{
+ struct mxc_ccm_reg *const imx_ccm =
+ (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
+}
+#endif
+
+#ifdef CONFIG_PCIE_IMX
+static void ungate_pcie_clock(void)
+{
+ struct mxc_ccm_reg *const imx_ccm =
+ (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ /* Enable PCIe clock. */
+ setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
+}
+
+int enable_pcie_clock(void)
+{
+ struct anatop_regs *anatop_regs =
+ (struct anatop_regs *)ANATOP_BASE_ADDR;
+ struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ u32 lvds1_clk_sel;
+
+ /*
+ * Here be dragons!
+ *
+ * The register ANATOP_MISC1 is not documented in the Freescale
+ * MX6RM. The register that is mapped in the ANATOP space and
+ * marked as ANATOP_MISC1 is actually documented in the PMU section
+ * of the datasheet as PMU_MISC1.
+ *
+ * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
+ * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
+ * for PCI express link that is clocked from the i.MX6.
+ */
+#define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
+#define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
+#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
+#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
+#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
+
+ if (is_mx6sx())
+ lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
+ else
+ lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
+
+ clrsetbits_le32(&anatop_regs->ana_misc1,
+ ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
+ ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
+ ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
+
+ /* PCIe reference clock sourced from AXI. */
+ clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
+
+ /* Party time! Ungate the clock to the PCIe. */
+#ifdef CONFIG_SATA
+ ungate_sata_clock();
+#endif
+ ungate_pcie_clock();
+
+ return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
+ BM_ANADIG_PLL_ENET_ENABLE_PCIE);
+}
+#endif
+
+#ifdef CONFIG_SECURE_BOOT
+void hab_caam_clock_enable(unsigned char enable)
+{
+ u32 reg;
+
+ if (is_mx6ull() || is_mx6sll()) {
+ /* CG5, DCP clock */
+ reg = __raw_readl(&imx_ccm->CCGR0);
+ if (enable)
+ reg |= MXC_CCM_CCGR0_DCP_CLK_MASK;
+ else
+ reg &= ~MXC_CCM_CCGR0_DCP_CLK_MASK;
+ __raw_writel(reg, &imx_ccm->CCGR0);
+ } else {
+ /* CG4 ~ CG6, CAAM clocks */
+ reg = __raw_readl(&imx_ccm->CCGR0);
+ if (enable)
+ reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
+ MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
+ MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
+ else
+ reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
+ MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
+ MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
+ __raw_writel(reg, &imx_ccm->CCGR0);
+ }
+
+ /* EMI slow clk */
+ reg = __raw_readl(&imx_ccm->CCGR6);
+ if (enable)
+ reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
+ else
+ reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
+ __raw_writel(reg, &imx_ccm->CCGR6);
+}
+#endif
+
+static void enable_pll3(void)
+{
+ struct anatop_regs __iomem *anatop =
+ (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
+
+ /* make sure pll3 is enabled */
+ if ((readl(&anatop->usb1_pll_480_ctrl) &
+ BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
+ /* enable pll's power */
+ writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
+ &anatop->usb1_pll_480_ctrl_set);
+ writel(0x80, &anatop->ana_misc2_clr);
+ /* wait for pll lock */
+ while ((readl(&anatop->usb1_pll_480_ctrl) &
+ BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
+ ;
+ /* disable bypass */
+ writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
+ &anatop->usb1_pll_480_ctrl_clr);
+ /* enable pll output */
+ writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
+ &anatop->usb1_pll_480_ctrl_set);
+ }
+}
+
+void enable_thermal_clk(void)
+{
+ enable_pll3();
+}
+
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+ switch (clk) {
+ case MXC_ARM_CLK:
+ return get_mcu_main_clk();
+ case MXC_PER_CLK:
+ return get_periph_clk();
+ case MXC_AHB_CLK:
+ return get_ahb_clk();
+ case MXC_IPG_CLK:
+ return get_ipg_clk();
+ case MXC_IPG_PERCLK:
+ case MXC_I2C_CLK:
+ return get_ipg_per_clk();
+ case MXC_UART_CLK:
+ return get_uart_clk();
+ case MXC_CSPI_CLK:
+ return get_cspi_clk();
+ case MXC_AXI_CLK:
+ return get_axi_clk();
+ case MXC_EMI_SLOW_CLK:
+ return get_emi_slow_clk();
+ case MXC_DDR_CLK:
+ return get_mmdc_ch0_clk();
+ case MXC_ESDHC_CLK:
+ return get_usdhc_clk(0);
+ case MXC_ESDHC2_CLK:
+ return get_usdhc_clk(1);
+ case MXC_ESDHC3_CLK:
+ return get_usdhc_clk(2);
+ case MXC_ESDHC4_CLK:
+ return get_usdhc_clk(3);
+ case MXC_SATA_CLK:
+ return get_ahb_clk();
+ default:
+ printf("Unsupported MXC CLK: %d\n", clk);
+ break;
+ }
+
+ return 0;
+}
+
+/*
+ * Dump some core clockes.
+ */
+int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ u32 freq;
+ freq = decode_pll(PLL_SYS, MXC_HCLK);
+ printf("PLL_SYS %8d MHz\n", freq / 1000000);
+ freq = decode_pll(PLL_BUS, MXC_HCLK);
+ printf("PLL_BUS %8d MHz\n", freq / 1000000);
+ freq = decode_pll(PLL_USBOTG, MXC_HCLK);
+ printf("PLL_OTG %8d MHz\n", freq / 1000000);
+ freq = decode_pll(PLL_ENET, MXC_HCLK);
+ printf("PLL_NET %8d MHz\n", freq / 1000000);
+
+ printf("\n");
+ printf("ARM %8d kHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000);
+ printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
+ printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
+#ifdef CONFIG_MXC_SPI
+ printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
+#endif
+ printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
+ printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
+ printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
+ printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
+ printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
+ printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
+ printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
+ printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
+ printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
+
+ return 0;
+}
+
+#ifndef CONFIG_MX6SX
+void enable_ipu_clock(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ int reg;
+ reg = readl(&mxc_ccm->CCGR3);
+ reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
+ writel(reg, &mxc_ccm->CCGR3);
+
+ if (is_mx6dqp()) {
+ setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
+ setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
+ }
+}
+#endif
+
+#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) || defined(CONFIG_MX6DL) || \
+ defined(CONFIG_MX6S)
+static void disable_ldb_di_clock_sources(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ int reg;
+
+ /* Make sure PFDs are disabled at boot. */
+ reg = readl(&mxc_ccm->analog_pfd_528);
+ /* Cannot disable pll2_pfd2_396M, as it is the MMDC clock in iMX6DL */
+ if (is_mx6sdl())
+ reg |= 0x80008080;
+ else
+ reg |= 0x80808080;
+ writel(reg, &mxc_ccm->analog_pfd_528);
+
+ /* Disable PLL3 PFDs */
+ reg = readl(&mxc_ccm->analog_pfd_480);
+ reg |= 0x80808080;
+ writel(reg, &mxc_ccm->analog_pfd_480);
+
+ /* Disable PLL5 */
+ reg = readl(&mxc_ccm->analog_pll_video);
+ reg &= ~(1 << 13);
+ writel(reg, &mxc_ccm->analog_pll_video);
+}
+
+static void enable_ldb_di_clock_sources(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ int reg;
+
+ reg = readl(&mxc_ccm->analog_pfd_528);
+ if (is_mx6sdl())
+ reg &= ~(0x80008080);
+ else
+ reg &= ~(0x80808080);
+ writel(reg, &mxc_ccm->analog_pfd_528);
+
+ reg = readl(&mxc_ccm->analog_pfd_480);
+ reg &= ~(0x80808080);
+ writel(reg, &mxc_ccm->analog_pfd_480);
+}
+
+/*
+ * Try call this function as early in the boot process as possible since the
+ * function temporarily disables PLL2 PFD's, PLL3 PFD's and PLL5.
+ */
+void select_ldb_di_clock_source(enum ldb_di_clock clk)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ int reg;
+
+ /*
+ * Need to follow a strict procedure when changing the LDB
+ * clock, else we can introduce a glitch. Things to keep in
+ * mind:
+ * 1. The current and new parent clocks must be disabled.
+ * 2. The default clock for ldb_dio_clk is mmdc_ch1 which has
+ * no CG bit.
+ * 3. In the RTL implementation of the LDB_DI_CLK_SEL mux
+ * the top four options are in one mux and the PLL3 option along
+ * with another option is in the second mux. There is third mux
+ * used to decide between the first and second mux.
+ * The code below switches the parent to the bottom mux first
+ * and then manipulates the top mux. This ensures that no glitch
+ * will enter the divider.
+ *
+ * Need to disable MMDC_CH1 clock manually as there is no CG bit
+ * for this clock. The only way to disable this clock is to move
+ * it to pll3_sw_clk and then to disable pll3_sw_clk
+ * Make sure periph2_clk2_sel is set to pll3_sw_clk
+ */
+
+ /* Disable all ldb_di clock parents */
+ disable_ldb_di_clock_sources();
+
+ /* Set MMDC_CH1 mask bit */
+ reg = readl(&mxc_ccm->ccdr);
+ reg |= MXC_CCM_CCDR_MMDC_CH1_HS_MASK;
+ writel(reg, &mxc_ccm->ccdr);
+
+ /* Set periph2_clk2_sel to be sourced from PLL3_sw_clk */
+ reg = readl(&mxc_ccm->cbcmr);
+ reg &= ~MXC_CCM_CBCMR_PERIPH2_CLK2_SEL;
+ writel(reg, &mxc_ccm->cbcmr);
+
+ /*
+ * Set the periph2_clk_sel to the top mux so that
+ * mmdc_ch1 is from pll3_sw_clk.
+ */
+ reg = readl(&mxc_ccm->cbcdr);
+ reg |= MXC_CCM_CBCDR_PERIPH2_CLK_SEL;
+ writel(reg, &mxc_ccm->cbcdr);
+
+ /* Wait for the clock switch */
+ while (readl(&mxc_ccm->cdhipr))
+ ;
+ /* Disable pll3_sw_clk by selecting bypass clock source */
+ reg = readl(&mxc_ccm->ccsr);
+ reg |= MXC_CCM_CCSR_PLL3_SW_CLK_SEL;
+ writel(reg, &mxc_ccm->ccsr);
+
+ /* Set the ldb_di0_clk and ldb_di1_clk to 111b */
+ reg = readl(&mxc_ccm->cs2cdr);
+ reg |= ((7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
+ | (7 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
+ writel(reg, &mxc_ccm->cs2cdr);
+
+ /* Set the ldb_di0_clk and ldb_di1_clk to 100b */
+ reg = readl(&mxc_ccm->cs2cdr);
+ reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
+ | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
+ reg |= ((4 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
+ | (4 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
+ writel(reg, &mxc_ccm->cs2cdr);
+
+ /* Set the ldb_di0_clk and ldb_di1_clk to desired source */
+ reg = readl(&mxc_ccm->cs2cdr);
+ reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
+ | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
+ reg |= ((clk << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
+ | (clk << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
+ writel(reg, &mxc_ccm->cs2cdr);
+
+ /* Unbypass pll3_sw_clk */
+ reg = readl(&mxc_ccm->ccsr);
+ reg &= ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL;
+ writel(reg, &mxc_ccm->ccsr);
+
+ /*
+ * Set the periph2_clk_sel back to the bottom mux so that
+ * mmdc_ch1 is from its original parent.
+ */
+ reg = readl(&mxc_ccm->cbcdr);
+ reg &= ~MXC_CCM_CBCDR_PERIPH2_CLK_SEL;
+ writel(reg, &mxc_ccm->cbcdr);
+
+ /* Wait for the clock switch */
+ while (readl(&mxc_ccm->cdhipr))
+ ;
+ /* Clear MMDC_CH1 mask bit */
+ reg = readl(&mxc_ccm->ccdr);
+ reg &= ~MXC_CCM_CCDR_MMDC_CH1_HS_MASK;
+ writel(reg, &mxc_ccm->ccdr);
+
+ enable_ldb_di_clock_sources();
+}
+#endif
+
+#ifdef CONFIG_MTD_NOR_FLASH
+void enable_eim_clk(unsigned char enable)
+{
+ u32 reg;
+
+ reg = __raw_readl(&imx_ccm->CCGR6);
+ if (enable)
+ reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
+ else
+ reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
+ __raw_writel(reg, &imx_ccm->CCGR6);
+}
+#endif
+
+/***************************************************/
+
+U_BOOT_CMD(
+ clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,
+ "display clocks",
+ ""
+);
--- /dev/null
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Author: Tim Harvey <tharvey@gateworks.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/types.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/types.h>
+#include <wait_bit.h>
+
+#if defined(CONFIG_MX6_DDRCAL)
+static void reset_read_data_fifos(void)
+{
+ struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
+
+ /* Reset data FIFOs twice. */
+ setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
+ wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
+
+ setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
+ wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
+}
+
+static void precharge_all(const bool cs0_enable, const bool cs1_enable)
+{
+ struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
+
+ /*
+ * Issue the Precharge-All command to the DDR device for both
+ * chip selects. Note, CON_REQ bit should also remain set. If
+ * only using one chip select, then precharge only the desired
+ * chip select.
+ */
+ if (cs0_enable) { /* CS0 */
+ writel(0x04008050, &mmdc0->mdscr);
+ wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 1, 100, 0);
+ }
+
+ if (cs1_enable) { /* CS1 */
+ writel(0x04008058, &mmdc0->mdscr);
+ wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 1, 100, 0);
+ }
+}
+
+static void force_delay_measurement(int bus_size)
+{
+ struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
+ struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
+
+ writel(0x800, &mmdc0->mpmur0);
+ if (bus_size == 0x2)
+ writel(0x800, &mmdc1->mpmur0);
+}
+
+static void modify_dg_result(u32 *reg_st0, u32 *reg_st1, u32 *reg_ctrl)
+{
+ u32 dg_tmp_val, dg_dl_abs_offset, dg_hc_del, val_ctrl;
+
+ /*
+ * DQS gating absolute offset should be modified from reflecting
+ * (HW_DG_LOWx + HW_DG_UPx)/2 to reflecting (HW_DG_UPx - 0x80)
+ */
+
+ val_ctrl = readl(reg_ctrl);
+ val_ctrl &= 0xf0000000;
+
+ dg_tmp_val = ((readl(reg_st0) & 0x07ff0000) >> 16) - 0xc0;
+ dg_dl_abs_offset = dg_tmp_val & 0x7f;
+ dg_hc_del = (dg_tmp_val & 0x780) << 1;
+
+ val_ctrl |= dg_dl_abs_offset + dg_hc_del;
+
+ dg_tmp_val = ((readl(reg_st1) & 0x07ff0000) >> 16) - 0xc0;
+ dg_dl_abs_offset = dg_tmp_val & 0x7f;
+ dg_hc_del = (dg_tmp_val & 0x780) << 1;
+
+ val_ctrl |= (dg_dl_abs_offset + dg_hc_del) << 16;
+
+ writel(val_ctrl, reg_ctrl);
+}
+
+int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo)
+{
+ struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
+ struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
+ u32 esdmisc_val, zq_val;
+ u32 errors = 0;
+ u32 ldectrl[4] = {0};
+ u32 ddr_mr1 = 0x4;
+ u32 rwalat_max;
+
+ /*
+ * Stash old values in case calibration fails,
+ * we need to restore them
+ */
+ ldectrl[0] = readl(&mmdc0->mpwldectrl0);
+ ldectrl[1] = readl(&mmdc0->mpwldectrl1);
+ if (sysinfo->dsize == 2) {
+ ldectrl[2] = readl(&mmdc1->mpwldectrl0);
+ ldectrl[3] = readl(&mmdc1->mpwldectrl1);
+ }
+
+ /* disable DDR logic power down timer */
+ clrbits_le32(&mmdc0->mdpdc, 0xff00);
+
+ /* disable Adopt power down timer */
+ setbits_le32(&mmdc0->mapsr, 0x1);
+
+ debug("Starting write leveling calibration.\n");
+
+ /*
+ * 2. disable auto refresh and ZQ calibration
+ * before proceeding with Write Leveling calibration
+ */
+ esdmisc_val = readl(&mmdc0->mdref);
+ writel(0x0000C000, &mmdc0->mdref);
+ zq_val = readl(&mmdc0->mpzqhwctrl);
+ writel(zq_val & ~0x3, &mmdc0->mpzqhwctrl);
+
+ /* 3. increase walat and ralat to maximum */
+ rwalat_max = (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17);
+ setbits_le32(&mmdc0->mdmisc, rwalat_max);
+ if (sysinfo->dsize == 2)
+ setbits_le32(&mmdc1->mdmisc, rwalat_max);
+ /*
+ * 4 & 5. Configure the external DDR device to enter write-leveling
+ * mode through Load Mode Register command.
+ * Register setting:
+ * Bits[31:16] MR1 value (0x0080 write leveling enable)
+ * Bit[9] set WL_EN to enable MMDC DQS output
+ * Bits[6:4] set CMD bits for Load Mode Register programming
+ * Bits[2:0] set CMD_BA to 0x1 for DDR MR1 programming
+ */
+ writel(0x00808231, &mmdc0->mdscr);
+
+ /* 6. Activate automatic calibration by setting MPWLGCR[HW_WL_EN] */
+ writel(0x00000001, &mmdc0->mpwlgcr);
+
+ /*
+ * 7. Upon completion of this process the MMDC de-asserts
+ * the MPWLGCR[HW_WL_EN]
+ */
+ wait_for_bit("MMDC", &mmdc0->mpwlgcr, 1 << 0, 0, 100, 0);
+
+ /*
+ * 8. check for any errors: check both PHYs for x64 configuration,
+ * if x32, check only PHY0
+ */
+ if (readl(&mmdc0->mpwlgcr) & 0x00000F00)
+ errors |= 1;
+ if (sysinfo->dsize == 2)
+ if (readl(&mmdc1->mpwlgcr) & 0x00000F00)
+ errors |= 2;
+
+ debug("Ending write leveling calibration. Error mask: 0x%x\n", errors);
+
+ /* check to see if cal failed */
+ if ((readl(&mmdc0->mpwldectrl0) == 0x001F001F) &&
+ (readl(&mmdc0->mpwldectrl1) == 0x001F001F) &&
+ ((sysinfo->dsize < 2) ||
+ ((readl(&mmdc1->mpwldectrl0) == 0x001F001F) &&
+ (readl(&mmdc1->mpwldectrl1) == 0x001F001F)))) {
+ debug("Cal seems to have soft-failed due to memory not supporting write leveling on all channels. Restoring original write leveling values.\n");
+ writel(ldectrl[0], &mmdc0->mpwldectrl0);
+ writel(ldectrl[1], &mmdc0->mpwldectrl1);
+ if (sysinfo->dsize == 2) {
+ writel(ldectrl[2], &mmdc1->mpwldectrl0);
+ writel(ldectrl[3], &mmdc1->mpwldectrl1);
+ }
+ errors |= 4;
+ }
+
+ /*
+ * User should issue MRS command to exit write leveling mode
+ * through Load Mode Register command
+ * Register setting:
+ * Bits[31:16] MR1 value "ddr_mr1" value from initialization
+ * Bit[9] clear WL_EN to disable MMDC DQS output
+ * Bits[6:4] set CMD bits for Load Mode Register programming
+ * Bits[2:0] set CMD_BA to 0x1 for DDR MR1 programming
+ */
+ writel((ddr_mr1 << 16) + 0x8031, &mmdc0->mdscr);
+
+ /* re-enable auto refresh and zq cal */
+ writel(esdmisc_val, &mmdc0->mdref);
+ writel(zq_val, &mmdc0->mpzqhwctrl);
+
+ debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08X\n",
+ readl(&mmdc0->mpwldectrl0));
+ debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08X\n",
+ readl(&mmdc0->mpwldectrl1));
+ if (sysinfo->dsize == 2) {
+ debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08X\n",
+ readl(&mmdc1->mpwldectrl0));
+ debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08X\n",
+ readl(&mmdc1->mpwldectrl1));
+ }
+
+ /* We must force a readback of these values, to get them to stick */
+ readl(&mmdc0->mpwldectrl0);
+ readl(&mmdc0->mpwldectrl1);
+ if (sysinfo->dsize == 2) {
+ readl(&mmdc1->mpwldectrl0);
+ readl(&mmdc1->mpwldectrl1);
+ }
+
+ /* enable DDR logic power down timer: */
+ setbits_le32(&mmdc0->mdpdc, 0x00005500);
+
+ /* Enable Adopt power down timer: */
+ clrbits_le32(&mmdc0->mapsr, 0x1);
+
+ /* Clear CON_REQ */
+ writel(0, &mmdc0->mdscr);
+
+ return errors;
+}
+
+int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
+{
+ struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
+ struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
+ struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux =
+ (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
+ bool cs0_enable;
+ bool cs1_enable;
+ bool cs0_enable_initial;
+ bool cs1_enable_initial;
+ u32 esdmisc_val;
+ u32 temp_ref;
+ u32 pddword = 0x00ffff00; /* best so far, place into MPPDCMPR1 */
+ u32 errors = 0;
+ u32 initdelay = 0x40404040;
+
+ /* check to see which chip selects are enabled */
+ cs0_enable_initial = readl(&mmdc0->mdctl) & 0x80000000;
+ cs1_enable_initial = readl(&mmdc0->mdctl) & 0x40000000;
+
+ /* disable DDR logic power down timer: */
+ clrbits_le32(&mmdc0->mdpdc, 0xff00);
+
+ /* disable Adopt power down timer: */
+ setbits_le32(&mmdc0->mapsr, 0x1);
+
+ /* set DQS pull ups */
+ setbits_le32(&mx6_ddr_iomux->dram_sdqs0, 0x7000);
+ setbits_le32(&mx6_ddr_iomux->dram_sdqs1, 0x7000);
+ setbits_le32(&mx6_ddr_iomux->dram_sdqs2, 0x7000);
+ setbits_le32(&mx6_ddr_iomux->dram_sdqs3, 0x7000);
+ setbits_le32(&mx6_ddr_iomux->dram_sdqs4, 0x7000);
+ setbits_le32(&mx6_ddr_iomux->dram_sdqs5, 0x7000);
+ setbits_le32(&mx6_ddr_iomux->dram_sdqs6, 0x7000);
+ setbits_le32(&mx6_ddr_iomux->dram_sdqs7, 0x7000);
+
+ /* Save old RALAT and WALAT values */
+ esdmisc_val = readl(&mmdc0->mdmisc);
+
+ setbits_le32(&mmdc0->mdmisc,
+ (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17));
+
+ /* Disable auto refresh before proceeding with calibration */
+ temp_ref = readl(&mmdc0->mdref);
+ writel(0x0000c000, &mmdc0->mdref);
+
+ /*
+ * Per the ref manual, issue one refresh cycle MDSCR[CMD]= 0x2,
+ * this also sets the CON_REQ bit.
+ */
+ if (cs0_enable_initial)
+ writel(0x00008020, &mmdc0->mdscr);
+ if (cs1_enable_initial)
+ writel(0x00008028, &mmdc0->mdscr);
+
+ /* poll to make sure the con_ack bit was asserted */
+ wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 1, 100, 0);
+
+ /*
+ * Check MDMISC register CALIB_PER_CS to see which CS calibration
+ * is targeted to (under normal cases, it should be cleared
+ * as this is the default value, indicating calibration is directed
+ * to CS0).
+ * Disable the other chip select not being target for calibration
+ * to avoid any potential issues. This will get re-enabled at end
+ * of calibration.
+ */
+ if ((readl(&mmdc0->mdmisc) & 0x00100000) == 0)
+ clrbits_le32(&mmdc0->mdctl, 1 << 30); /* clear SDE_1 */
+ else
+ clrbits_le32(&mmdc0->mdctl, 1 << 31); /* clear SDE_0 */
+
+ /*
+ * Check to see which chip selects are now enabled for
+ * the remainder of the calibration.
+ */
+ cs0_enable = readl(&mmdc0->mdctl) & 0x80000000;
+ cs1_enable = readl(&mmdc0->mdctl) & 0x40000000;
+
+ precharge_all(cs0_enable, cs1_enable);
+
+ /* Write the pre-defined value into MPPDCMPR1 */
+ writel(pddword, &mmdc0->mppdcmpr1);
+
+ /*
+ * Issue a write access to the external DDR device by setting
+ * the bit SW_DUMMY_WR (bit 0) in the MPSWDAR0 and then poll
+ * this bit until it clears to indicate completion of the write access.
+ */
+ setbits_le32(&mmdc0->mpswdar0, 1);
+ wait_for_bit("MMDC", &mmdc0->mpswdar0, 1 << 0, 0, 100, 0);
+
+ /* Set the RD_DL_ABS# bits to their default values
+ * (will be calibrated later in the read delay-line calibration).
+ * Both PHYs for x64 configuration, if x32, do only PHY0.
+ */
+ writel(initdelay, &mmdc0->mprddlctl);
+ if (sysinfo->dsize == 0x2)
+ writel(initdelay, &mmdc1->mprddlctl);
+
+ /* Force a measurment, for previous delay setup to take effect. */
+ force_delay_measurement(sysinfo->dsize);
+
+ /*
+ * ***************************
+ * Read DQS Gating calibration
+ * ***************************
+ */
+ debug("Starting Read DQS Gating calibration.\n");
+
+ /*
+ * Reset the read data FIFOs (two resets); only need to issue reset
+ * to PHY0 since in x64 mode, the reset will also go to PHY1.
+ */
+ reset_read_data_fifos();
+
+ /*
+ * Start the automatic read DQS gating calibration process by
+ * asserting MPDGCTRL0[HW_DG_EN] and MPDGCTRL0[DG_CMP_CYC]
+ * and then poll MPDGCTRL0[HW_DG_EN]] until this bit clears
+ * to indicate completion.
+ * Also, ensure that MPDGCTRL0[HW_DG_ERR] is clear to indicate
+ * no errors were seen during calibration.
+ */
+
+ /*
+ * Set bit 30: chooses option to wait 32 cycles instead of
+ * 16 before comparing read data.
+ */
+ setbits_le32(&mmdc0->mpdgctrl0, 1 << 30);
+ if (sysinfo->dsize == 2)
+ setbits_le32(&mmdc1->mpdgctrl0, 1 << 30);
+
+ /* Set bit 28 to start automatic read DQS gating calibration */
+ setbits_le32(&mmdc0->mpdgctrl0, 5 << 28);
+
+ /* Poll for completion. MPDGCTRL0[HW_DG_EN] should be 0 */
+ wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 28, 0, 100, 0);
+
+ /*
+ * Check to see if any errors were encountered during calibration
+ * (check MPDGCTRL0[HW_DG_ERR]).
+ * Check both PHYs for x64 configuration, if x32, check only PHY0.
+ */
+ if (readl(&mmdc0->mpdgctrl0) & 0x00001000)
+ errors |= 1;
+
+ if ((sysinfo->dsize == 0x2) && (readl(&mmdc1->mpdgctrl0) & 0x00001000))
+ errors |= 2;
+
+ /* now disable mpdgctrl0[DG_CMP_CYC] */
+ clrbits_le32(&mmdc0->mpdgctrl0, 1 << 30);
+ if (sysinfo->dsize == 2)
+ clrbits_le32(&mmdc1->mpdgctrl0, 1 << 30);
+
+ /*
+ * DQS gating absolute offset should be modified from
+ * reflecting (HW_DG_LOWx + HW_DG_UPx)/2 to
+ * reflecting (HW_DG_UPx - 0x80)
+ */
+ modify_dg_result(&mmdc0->mpdghwst0, &mmdc0->mpdghwst1,
+ &mmdc0->mpdgctrl0);
+ modify_dg_result(&mmdc0->mpdghwst2, &mmdc0->mpdghwst3,
+ &mmdc0->mpdgctrl1);
+ if (sysinfo->dsize == 0x2) {
+ modify_dg_result(&mmdc1->mpdghwst0, &mmdc1->mpdghwst1,
+ &mmdc1->mpdgctrl0);
+ modify_dg_result(&mmdc1->mpdghwst2, &mmdc1->mpdghwst3,
+ &mmdc1->mpdgctrl1);
+ }
+ debug("Ending Read DQS Gating calibration. Error mask: 0x%x\n", errors);
+
+ /*
+ * **********************
+ * Read Delay calibration
+ * **********************
+ */
+ debug("Starting Read Delay calibration.\n");
+
+ reset_read_data_fifos();
+
+ /*
+ * 4. Issue the Precharge-All command to the DDR device for both
+ * chip selects. If only using one chip select, then precharge
+ * only the desired chip select.
+ */
+ precharge_all(cs0_enable, cs1_enable);
+
+ /*
+ * 9. Read delay-line calibration
+ * Start the automatic read calibration process by asserting
+ * MPRDDLHWCTL[HW_RD_DL_EN].
+ */
+ writel(0x00000030, &mmdc0->mprddlhwctl);
+
+ /*
+ * 10. poll for completion
+ * MMDC indicates that the write data calibration had finished by
+ * setting MPRDDLHWCTL[HW_RD_DL_EN] = 0. Also, ensure that
+ * no error bits were set.
+ */
+ wait_for_bit("MMDC", &mmdc0->mprddlhwctl, 1 << 4, 0, 100, 0);
+
+ /* check both PHYs for x64 configuration, if x32, check only PHY0 */
+ if (readl(&mmdc0->mprddlhwctl) & 0x0000000f)
+ errors |= 4;
+
+ if ((sysinfo->dsize == 0x2) &&
+ (readl(&mmdc1->mprddlhwctl) & 0x0000000f))
+ errors |= 8;
+
+ debug("Ending Read Delay calibration. Error mask: 0x%x\n", errors);
+
+ /*
+ * ***********************
+ * Write Delay Calibration
+ * ***********************
+ */
+ debug("Starting Write Delay calibration.\n");
+
+ reset_read_data_fifos();
+
+ /*
+ * 4. Issue the Precharge-All command to the DDR device for both
+ * chip selects. If only using one chip select, then precharge
+ * only the desired chip select.
+ */
+ precharge_all(cs0_enable, cs1_enable);
+
+ /*
+ * 8. Set the WR_DL_ABS# bits to their default values.
+ * Both PHYs for x64 configuration, if x32, do only PHY0.
+ */
+ writel(initdelay, &mmdc0->mpwrdlctl);
+ if (sysinfo->dsize == 0x2)
+ writel(initdelay, &mmdc1->mpwrdlctl);
+
+ /*
+ * XXX This isn't in the manual. Force a measurement,
+ * for previous delay setup to effect.
+ */
+ force_delay_measurement(sysinfo->dsize);
+
+ /*
+ * 9. 10. Start the automatic write calibration process
+ * by asserting MPWRDLHWCTL0[HW_WR_DL_EN].
+ */
+ writel(0x00000030, &mmdc0->mpwrdlhwctl);
+
+ /*
+ * Poll for completion.
+ * MMDC indicates that the write data calibration had finished
+ * by setting MPWRDLHWCTL[HW_WR_DL_EN] = 0.
+ * Also, ensure that no error bits were set.
+ */
+ wait_for_bit("MMDC", &mmdc0->mpwrdlhwctl, 1 << 4, 0, 100, 0);
+
+ /* Check both PHYs for x64 configuration, if x32, check only PHY0 */
+ if (readl(&mmdc0->mpwrdlhwctl) & 0x0000000f)
+ errors |= 16;
+
+ if ((sysinfo->dsize == 0x2) &&
+ (readl(&mmdc1->mpwrdlhwctl) & 0x0000000f))
+ errors |= 32;
+
+ debug("Ending Write Delay calibration. Error mask: 0x%x\n", errors);
+
+ reset_read_data_fifos();
+
+ /* Enable DDR logic power down timer */
+ setbits_le32(&mmdc0->mdpdc, 0x00005500);
+
+ /* Enable Adopt power down timer */
+ clrbits_le32(&mmdc0->mapsr, 0x1);
+
+ /* Restore MDMISC value (RALAT, WALAT) to MMDCP1 */
+ writel(esdmisc_val, &mmdc0->mdmisc);
+
+ /* Clear DQS pull ups */
+ clrbits_le32(&mx6_ddr_iomux->dram_sdqs0, 0x7000);
+ clrbits_le32(&mx6_ddr_iomux->dram_sdqs1, 0x7000);
+ clrbits_le32(&mx6_ddr_iomux->dram_sdqs2, 0x7000);
+ clrbits_le32(&mx6_ddr_iomux->dram_sdqs3, 0x7000);
+ clrbits_le32(&mx6_ddr_iomux->dram_sdqs4, 0x7000);
+ clrbits_le32(&mx6_ddr_iomux->dram_sdqs5, 0x7000);
+ clrbits_le32(&mx6_ddr_iomux->dram_sdqs6, 0x7000);
+ clrbits_le32(&mx6_ddr_iomux->dram_sdqs7, 0x7000);
+
+ /* Re-enable SDE (chip selects) if they were set initially */
+ if (cs1_enable_initial)
+ /* Set SDE_1 */
+ setbits_le32(&mmdc0->mdctl, 1 << 30);
+
+ if (cs0_enable_initial)
+ /* Set SDE_0 */
+ setbits_le32(&mmdc0->mdctl, 1 << 31);
+
+ /* Re-enable to auto refresh */
+ writel(temp_ref, &mmdc0->mdref);
+
+ /* Clear the MDSCR (including the con_req bit) */
+ writel(0x0, &mmdc0->mdscr); /* CS0 */
+
+ /* Poll to make sure the con_ack bit is clear */
+ wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 0, 100, 0);
+
+ /*
+ * Print out the registers that were updated as a result
+ * of the calibration process.
+ */
+ debug("MMDC registers updated from calibration\n");
+ debug("Read DQS gating calibration:\n");
+ debug("\tMPDGCTRL0 PHY0 = 0x%08X\n", readl(&mmdc0->mpdgctrl0));
+ debug("\tMPDGCTRL1 PHY0 = 0x%08X\n", readl(&mmdc0->mpdgctrl1));
+ if (sysinfo->dsize == 2) {
+ debug("\tMPDGCTRL0 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl0));
+ debug("\tMPDGCTRL1 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl1));
+ }
+ debug("Read calibration:\n");
+ debug("\tMPRDDLCTL PHY0 = 0x%08X\n", readl(&mmdc0->mprddlctl));
+ if (sysinfo->dsize == 2)
+ debug("\tMPRDDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mprddlctl));
+ debug("Write calibration:\n");
+ debug("\tMPWRDLCTL PHY0 = 0x%08X\n", readl(&mmdc0->mpwrdlctl));
+ if (sysinfo->dsize == 2)
+ debug("\tMPWRDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mpwrdlctl));
+
+ /*
+ * Registers below are for debugging purposes. These print out
+ * the upper and lower boundaries captured during
+ * read DQS gating calibration.
+ */
+ debug("Status registers bounds for read DQS gating:\n");
+ debug("\tMPDGHWST0 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst0));
+ debug("\tMPDGHWST1 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst1));
+ debug("\tMPDGHWST2 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst2));
+ debug("\tMPDGHWST3 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst3));
+ if (sysinfo->dsize == 2) {
+ debug("\tMPDGHWST0 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst0));
+ debug("\tMPDGHWST1 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst1));
+ debug("\tMPDGHWST2 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst2));
+ debug("\tMPDGHWST3 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst3));
+ }
+
+ debug("Final do_dqs_calibration error mask: 0x%x\n", errors);
+
+ return errors;
+}
+#endif
+
+#if defined(CONFIG_MX6SX)
+/* Configure MX6SX mmdc iomux */
+void mx6sx_dram_iocfg(unsigned width,
+ const struct mx6sx_iomux_ddr_regs *ddr,
+ const struct mx6sx_iomux_grp_regs *grp)
+{
+ struct mx6sx_iomux_ddr_regs *mx6_ddr_iomux;
+ struct mx6sx_iomux_grp_regs *mx6_grp_iomux;
+
+ mx6_ddr_iomux = (struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE;
+ mx6_grp_iomux = (struct mx6sx_iomux_grp_regs *)MX6SX_IOM_GRP_BASE;
+
+ /* DDR IO TYPE */
+ writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
+ writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
+
+ /* CLOCK */
+ writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
+
+ /* ADDRESS */
+ writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
+ writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
+ writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
+
+ /* Control */
+ writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
+ writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
+ writel(ddr->dram_sdcke0, &mx6_ddr_iomux->dram_sdcke0);
+ writel(ddr->dram_sdcke1, &mx6_ddr_iomux->dram_sdcke1);
+ writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
+ writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
+ writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
+
+ /* Data Strobes */
+ writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
+ writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
+ writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
+ if (width >= 32) {
+ writel(ddr->dram_sdqs2, &mx6_ddr_iomux->dram_sdqs2);
+ writel(ddr->dram_sdqs3, &mx6_ddr_iomux->dram_sdqs3);
+ }
+
+ /* Data */
+ writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
+ writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
+ writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
+ if (width >= 32) {
+ writel(grp->grp_b2ds, &mx6_grp_iomux->grp_b2ds);
+ writel(grp->grp_b3ds, &mx6_grp_iomux->grp_b3ds);
+ }
+ writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
+ writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
+ if (width >= 32) {
+ writel(ddr->dram_dqm2, &mx6_ddr_iomux->dram_dqm2);
+ writel(ddr->dram_dqm3, &mx6_ddr_iomux->dram_dqm3);
+ }
+}
+#endif
+
+#ifdef CONFIG_MX6UL
+void mx6ul_dram_iocfg(unsigned width,
+ const struct mx6ul_iomux_ddr_regs *ddr,
+ const struct mx6ul_iomux_grp_regs *grp)
+{
+ struct mx6ul_iomux_ddr_regs *mx6_ddr_iomux;
+ struct mx6ul_iomux_grp_regs *mx6_grp_iomux;
+
+ mx6_ddr_iomux = (struct mx6ul_iomux_ddr_regs *)MX6UL_IOM_DDR_BASE;
+ mx6_grp_iomux = (struct mx6ul_iomux_grp_regs *)MX6UL_IOM_GRP_BASE;
+
+ /* DDR IO TYPE */
+ writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
+ writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
+
+ /* CLOCK */
+ writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
+
+ /* ADDRESS */
+ writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
+ writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
+ writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
+
+ /* Control */
+ writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
+ writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
+ writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
+ writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
+ writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
+
+ /* Data Strobes */
+ writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
+ writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
+ writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
+
+ /* Data */
+ writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
+ writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
+ writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
+ writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
+ writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
+}
+#endif
+
+#if defined(CONFIG_MX6SL)
+void mx6sl_dram_iocfg(unsigned width,
+ const struct mx6sl_iomux_ddr_regs *ddr,
+ const struct mx6sl_iomux_grp_regs *grp)
+{
+ struct mx6sl_iomux_ddr_regs *mx6_ddr_iomux;
+ struct mx6sl_iomux_grp_regs *mx6_grp_iomux;
+
+ mx6_ddr_iomux = (struct mx6sl_iomux_ddr_regs *)MX6SL_IOM_DDR_BASE;
+ mx6_grp_iomux = (struct mx6sl_iomux_grp_regs *)MX6SL_IOM_GRP_BASE;
+
+ /* DDR IO TYPE */
+ mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
+ mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
+
+ /* CLOCK */
+ mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
+
+ /* ADDRESS */
+ mx6_ddr_iomux->dram_cas = ddr->dram_cas;
+ mx6_ddr_iomux->dram_ras = ddr->dram_ras;
+ mx6_grp_iomux->grp_addds = grp->grp_addds;
+
+ /* Control */
+ mx6_ddr_iomux->dram_reset = ddr->dram_reset;
+ mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
+ mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
+
+ /* Data Strobes */
+ mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
+ mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
+ mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
+ if (width >= 32) {
+ mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
+ mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
+ }
+
+ /* Data */
+ mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
+ mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
+ mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
+ if (width >= 32) {
+ mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
+ mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
+ }
+
+ mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
+ mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
+ if (width >= 32) {
+ mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
+ mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
+ }
+}
+#endif
+
+#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
+/* Configure MX6DQ mmdc iomux */
+void mx6dq_dram_iocfg(unsigned width,
+ const struct mx6dq_iomux_ddr_regs *ddr,
+ const struct mx6dq_iomux_grp_regs *grp)
+{
+ volatile struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux;
+ volatile struct mx6dq_iomux_grp_regs *mx6_grp_iomux;
+
+ mx6_ddr_iomux = (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
+ mx6_grp_iomux = (struct mx6dq_iomux_grp_regs *)MX6DQ_IOM_GRP_BASE;
+
+ /* DDR IO Type */
+ mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
+ mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
+
+ /* Clock */
+ mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
+ mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
+
+ /* Address */
+ mx6_ddr_iomux->dram_cas = ddr->dram_cas;
+ mx6_ddr_iomux->dram_ras = ddr->dram_ras;
+ mx6_grp_iomux->grp_addds = grp->grp_addds;
+
+ /* Control */
+ mx6_ddr_iomux->dram_reset = ddr->dram_reset;
+ mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
+ mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
+ mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
+ mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
+ mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
+ mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
+
+ /* Data Strobes */
+ mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
+ mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
+ mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
+ if (width >= 32) {
+ mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
+ mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
+ }
+ if (width >= 64) {
+ mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
+ mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
+ mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
+ mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
+ }
+
+ /* Data */
+ mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
+ mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
+ mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
+ if (width >= 32) {
+ mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
+ mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
+ }
+ if (width >= 64) {
+ mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
+ mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
+ mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
+ mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
+ }
+ mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
+ mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
+ if (width >= 32) {
+ mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
+ mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
+ }
+ if (width >= 64) {
+ mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
+ mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
+ mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
+ mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
+ }
+}
+#endif
+
+#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+/* Configure MX6SDL mmdc iomux */
+void mx6sdl_dram_iocfg(unsigned width,
+ const struct mx6sdl_iomux_ddr_regs *ddr,
+ const struct mx6sdl_iomux_grp_regs *grp)
+{
+ volatile struct mx6sdl_iomux_ddr_regs *mx6_ddr_iomux;
+ volatile struct mx6sdl_iomux_grp_regs *mx6_grp_iomux;
+
+ mx6_ddr_iomux = (struct mx6sdl_iomux_ddr_regs *)MX6SDL_IOM_DDR_BASE;
+ mx6_grp_iomux = (struct mx6sdl_iomux_grp_regs *)MX6SDL_IOM_GRP_BASE;
+
+ /* DDR IO Type */
+ mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
+ mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
+
+ /* Clock */
+ mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
+ mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
+
+ /* Address */
+ mx6_ddr_iomux->dram_cas = ddr->dram_cas;
+ mx6_ddr_iomux->dram_ras = ddr->dram_ras;
+ mx6_grp_iomux->grp_addds = grp->grp_addds;
+
+ /* Control */
+ mx6_ddr_iomux->dram_reset = ddr->dram_reset;
+ mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
+ mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
+ mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
+ mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
+ mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
+ mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
+
+ /* Data Strobes */
+ mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
+ mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
+ mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
+ if (width >= 32) {
+ mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
+ mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
+ }
+ if (width >= 64) {
+ mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
+ mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
+ mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
+ mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
+ }
+
+ /* Data */
+ mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
+ mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
+ mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
+ if (width >= 32) {
+ mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
+ mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
+ }
+ if (width >= 64) {
+ mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
+ mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
+ mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
+ mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
+ }
+ mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
+ mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
+ if (width >= 32) {
+ mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
+ mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
+ }
+ if (width >= 64) {
+ mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
+ mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
+ mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
+ mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
+ }
+}
+#endif
+
+/*
+ * Configure mx6 mmdc registers based on:
+ * - board-specific memory configuration
+ * - board-specific calibration data
+ * - ddr3/lpddr2 chip details
+ *
+ * The various calculations here are derived from the Freescale
+ * 1. i.Mx6DQSDL DDR3 Script Aid spreadsheet (DOC-94917) designed to generate
+ * MMDC configuration registers based on memory system and memory chip
+ * parameters.
+ *
+ * 2. i.Mx6SL LPDDR2 Script Aid spreadsheet V0.04 designed to generate MMDC
+ * configuration registers based on memory system and memory chip
+ * parameters.
+ *
+ * The defaults here are those which were specified in the spreadsheet.
+ * For details on each register, refer to the IMX6DQRM and/or IMX6SDLRM
+ * and/or IMX6SLRM section titled MMDC initialization.
+ */
+#define MR(val, ba, cmd, cs1) \
+ ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
+#define MMDC1(entry, value) do { \
+ if (!is_mx6sx() && !is_mx6ul() && !is_mx6sl()) \
+ mmdc1->entry = value; \
+ } while (0)
+
+/*
+ * According JESD209-2B-LPDDR2: Table 103
+ * WL: write latency
+ */
+static int lpddr2_wl(uint32_t mem_speed)
+{
+ switch (mem_speed) {
+ case 1066:
+ case 933:
+ return 4;
+ case 800:
+ return 3;
+ case 677:
+ case 533:
+ return 2;
+ case 400:
+ case 333:
+ return 1;
+ default:
+ puts("invalid memory speed\n");
+ hang();
+ }
+
+ return 0;
+}
+
+/*
+ * According JESD209-2B-LPDDR2: Table 103
+ * RL: read latency
+ */
+static int lpddr2_rl(uint32_t mem_speed)
+{
+ switch (mem_speed) {
+ case 1066:
+ return 8;
+ case 933:
+ return 7;
+ case 800:
+ return 6;
+ case 677:
+ return 5;
+ case 533:
+ return 4;
+ case 400:
+ case 333:
+ return 3;
+ default:
+ puts("invalid memory speed\n");
+ hang();
+ }
+
+ return 0;
+}
+
+void mx6_lpddr2_cfg(const struct mx6_ddr_sysinfo *sysinfo,
+ const struct mx6_mmdc_calibration *calib,
+ const struct mx6_lpddr2_cfg *lpddr2_cfg)
+{
+ volatile struct mmdc_p_regs *mmdc0;
+ u32 val;
+ u8 tcke, tcksrx, tcksre, trrd;
+ u8 twl, txp, tfaw, tcl;
+ u16 tras, twr, tmrd, trtp, twtr, trfc, txsr;
+ u16 trcd_lp, trppb_lp, trpab_lp, trc_lp;
+ u16 cs0_end;
+ u8 coladdr;
+ int clkper; /* clock period in picoseconds */
+ int clock; /* clock freq in mHz */
+ int cs;
+
+ /* only support 16/32 bits */
+ if (sysinfo->dsize > 1)
+ hang();
+
+ mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
+
+ clock = mxc_get_clock(MXC_DDR_CLK) / 1000000U;
+ clkper = (1000 * 1000) / clock; /* pico seconds */
+
+ twl = lpddr2_wl(lpddr2_cfg->mem_speed) - 1;
+
+ /* LPDDR2-S2 and LPDDR2-S4 have the same tRFC value. */
+ switch (lpddr2_cfg->density) {
+ case 1:
+ case 2:
+ case 4:
+ trfc = DIV_ROUND_UP(130000, clkper) - 1;
+ txsr = DIV_ROUND_UP(140000, clkper) - 1;
+ break;
+ case 8:
+ trfc = DIV_ROUND_UP(210000, clkper) - 1;
+ txsr = DIV_ROUND_UP(220000, clkper) - 1;
+ break;
+ default:
+ /*
+ * 64Mb, 128Mb, 256Mb, 512Mb are not supported currently.
+ */
+ hang();
+ break;
+ }
+ /*
+ * txpdll, txpr, taonpd and taofpd are not relevant in LPDDR2 mode,
+ * set them to 0. */
+ txp = DIV_ROUND_UP(7500, clkper) - 1;
+ tcke = 3;
+ if (lpddr2_cfg->mem_speed == 333)
+ tfaw = DIV_ROUND_UP(60000, clkper) - 1;
+ else
+ tfaw = DIV_ROUND_UP(50000, clkper) - 1;
+ trrd = DIV_ROUND_UP(10000, clkper) - 1;
+
+ /* tckesr for LPDDR2 */
+ tcksre = DIV_ROUND_UP(15000, clkper);
+ tcksrx = tcksre;
+ twr = DIV_ROUND_UP(15000, clkper) - 1;
+ /*
+ * tMRR: 2, tMRW: 5
+ * tMRD should be set to max(tMRR, tMRW)
+ */
+ tmrd = 5;
+ tras = DIV_ROUND_UP(lpddr2_cfg->trasmin, clkper / 10) - 1;
+ /* LPDDR2 mode use tRCD_LP filed in MDCFG3. */
+ trcd_lp = DIV_ROUND_UP(lpddr2_cfg->trcd_lp, clkper / 10) - 1;
+ trc_lp = DIV_ROUND_UP(lpddr2_cfg->trasmin + lpddr2_cfg->trppb_lp,
+ clkper / 10) - 1;
+ trppb_lp = DIV_ROUND_UP(lpddr2_cfg->trppb_lp, clkper / 10) - 1;
+ trpab_lp = DIV_ROUND_UP(lpddr2_cfg->trpab_lp, clkper / 10) - 1;
+ /* To LPDDR2, CL in MDCFG0 refers to RL */
+ tcl = lpddr2_rl(lpddr2_cfg->mem_speed) - 3;
+ twtr = DIV_ROUND_UP(7500, clkper) - 1;
+ trtp = DIV_ROUND_UP(7500, clkper) - 1;
+
+ cs0_end = 4 * sysinfo->cs_density - 1;
+
+ debug("density:%d Gb (%d Gb per chip)\n",
+ sysinfo->cs_density, lpddr2_cfg->density);
+ debug("clock: %dMHz (%d ps)\n", clock, clkper);
+ debug("memspd:%d\n", lpddr2_cfg->mem_speed);
+ debug("trcd_lp=%d\n", trcd_lp);
+ debug("trppb_lp=%d\n", trppb_lp);
+ debug("trpab_lp=%d\n", trpab_lp);
+ debug("trc_lp=%d\n", trc_lp);
+ debug("tcke=%d\n", tcke);
+ debug("tcksrx=%d\n", tcksrx);
+ debug("tcksre=%d\n", tcksre);
+ debug("trfc=%d\n", trfc);
+ debug("txsr=%d\n", txsr);
+ debug("txp=%d\n", txp);
+ debug("tfaw=%d\n", tfaw);
+ debug("tcl=%d\n", tcl);
+ debug("tras=%d\n", tras);
+ debug("twr=%d\n", twr);
+ debug("tmrd=%d\n", tmrd);
+ debug("twl=%d\n", twl);
+ debug("trtp=%d\n", trtp);
+ debug("twtr=%d\n", twtr);
+ debug("trrd=%d\n", trrd);
+ debug("cs0_end=%d\n", cs0_end);
+ debug("ncs=%d\n", sysinfo->ncs);
+
+ /*
+ * board-specific configuration:
+ * These values are determined empirically and vary per board layout
+ */
+ mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
+ mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
+ mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
+ mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
+ mmdc0->mprddlctl = calib->p0_mprddlctl;
+ mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
+ mmdc0->mpzqlp2ctl = calib->mpzqlp2ctl;
+
+ /* Read data DQ Byte0-3 delay */
+ mmdc0->mprddqby0dl = 0x33333333;
+ mmdc0->mprddqby1dl = 0x33333333;
+ if (sysinfo->dsize > 0) {
+ mmdc0->mprddqby2dl = 0x33333333;
+ mmdc0->mprddqby3dl = 0x33333333;
+ }
+
+ /* Write data DQ Byte0-3 delay */
+ mmdc0->mpwrdqby0dl = 0xf3333333;
+ mmdc0->mpwrdqby1dl = 0xf3333333;
+ if (sysinfo->dsize > 0) {
+ mmdc0->mpwrdqby2dl = 0xf3333333;
+ mmdc0->mpwrdqby3dl = 0xf3333333;
+ }
+
+ /*
+ * In LPDDR2 mode this register should be cleared,
+ * so no termination will be activated.
+ */
+ mmdc0->mpodtctrl = 0;
+
+ /* complete calibration */
+ val = (1 << 11); /* Force measurement on delay-lines */
+ mmdc0->mpmur0 = val;
+
+ /* Step 1: configuration request */
+ mmdc0->mdscr = (u32)(1 << 15); /* config request */
+
+ /* Step 2: Timing configuration */
+ mmdc0->mdcfg0 = (trfc << 24) | (txsr << 16) | (txp << 13) |
+ (tfaw << 4) | tcl;
+ mmdc0->mdcfg1 = (tras << 16) | (twr << 9) | (tmrd << 5) | twl;
+ mmdc0->mdcfg2 = (trtp << 6) | (twtr << 3) | trrd;
+ mmdc0->mdcfg3lp = (trc_lp << 16) | (trcd_lp << 8) |
+ (trppb_lp << 4) | trpab_lp;
+ mmdc0->mdotc = 0;
+
+ mmdc0->mdasp = cs0_end; /* CS addressing */
+
+ /* Step 3: Configure DDR type */
+ mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
+ (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
+ (sysinfo->ralat << 6) | (1 << 3);
+
+ /* Step 4: Configure delay while leaving reset */
+ mmdc0->mdor = (sysinfo->sde_to_rst << 8) |
+ (sysinfo->rst_to_cke << 0);
+
+ /* Step 5: Configure DDR physical parameters (density and burst len) */
+ coladdr = lpddr2_cfg->coladdr;
+ if (lpddr2_cfg->coladdr == 8) /* 8-bit COL is 0x3 */
+ coladdr += 4;
+ else if (lpddr2_cfg->coladdr == 12) /* 12-bit COL is 0x4 */
+ coladdr += 1;
+ mmdc0->mdctl = (lpddr2_cfg->rowaddr - 11) << 24 | /* ROW */
+ (coladdr - 9) << 20 | /* COL */
+ (0 << 19) | /* Burst Length = 4 for LPDDR2 */
+ (sysinfo->dsize << 16); /* DDR data bus size */
+
+ /* Step 6: Perform ZQ calibration */
+ val = 0xa1390003; /* one-time HW ZQ calib */
+ mmdc0->mpzqhwctrl = val;
+
+ /* Step 7: Enable MMDC with desired chip select */
+ mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
+ ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
+
+ /* Step 8: Write Mode Registers to Init LPDDR2 devices */
+ for (cs = 0; cs < sysinfo->ncs; cs++) {
+ /* MR63: reset */
+ mmdc0->mdscr = MR(63, 0, 3, cs);
+ /* MR10: calibration,
+ * 0xff is calibration command after intilization.
+ */
+ val = 0xA | (0xff << 8);
+ mmdc0->mdscr = MR(val, 0, 3, cs);
+ /* MR1 */
+ val = 0x1 | (0x82 << 8);
+ mmdc0->mdscr = MR(val, 0, 3, cs);
+ /* MR2 */
+ val = 0x2 | (0x04 << 8);
+ mmdc0->mdscr = MR(val, 0, 3, cs);
+ /* MR3 */
+ val = 0x3 | (0x02 << 8);
+ mmdc0->mdscr = MR(val, 0, 3, cs);
+ }
+
+ /* Step 10: Power down control and self-refresh */
+ mmdc0->mdpdc = (tcke & 0x7) << 16 |
+ 5 << 12 | /* PWDT_1: 256 cycles */
+ 5 << 8 | /* PWDT_0: 256 cycles */
+ 1 << 6 | /* BOTH_CS_PD */
+ (tcksrx & 0x7) << 3 |
+ (tcksre & 0x7);
+ mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
+
+ /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
+ val = 0xa1310003;
+ mmdc0->mpzqhwctrl = val;
+
+ /* Step 12: Configure and activate periodic refresh */
+ mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);
+
+ /* Step 13: Deassert config request - init complete */
+ mmdc0->mdscr = 0x00000000;
+
+ /* wait for auto-ZQ calibration to complete */
+ mdelay(1);
+}
+
+void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
+ const struct mx6_mmdc_calibration *calib,
+ const struct mx6_ddr3_cfg *ddr3_cfg)
+{
+ volatile struct mmdc_p_regs *mmdc0;
+ volatile struct mmdc_p_regs *mmdc1;
+ u32 val;
+ u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
+ u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
+ u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */
+ u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
+ u16 cs0_end;
+ u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
+ u8 coladdr;
+ int clkper; /* clock period in picoseconds */
+ int clock; /* clock freq in MHz */
+ int cs;
+ u16 mem_speed = ddr3_cfg->mem_speed;
+
+ mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
+ if (!is_mx6sx() && !is_mx6ul() && !is_mx6sl())
+ mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
+
+ /* Limit mem_speed for MX6D/MX6Q */
+ if (is_mx6dq() || is_mx6dqp()) {
+ if (mem_speed > 1066)
+ mem_speed = 1066; /* 1066 MT/s */
+
+ tcwl = 4;
+ }
+ /* Limit mem_speed for MX6S/MX6DL */
+ else {
+ if (mem_speed > 800)
+ mem_speed = 800; /* 800 MT/s */
+
+ tcwl = 3;
+ }
+
+ clock = mem_speed / 2;
+ /*
+ * Data rate of 1066 MT/s requires 533 MHz DDR3 clock, but MX6D/Q supports
+ * up to 528 MHz, so reduce the clock to fit chip specs
+ */
+ if (is_mx6dq() || is_mx6dqp()) {
+ if (clock > 528)
+ clock = 528; /* 528 MHz */
+ }
+
+ clkper = (1000 * 1000) / clock; /* pico seconds */
+ todtlon = tcwl;
+ taxpd = tcwl;
+ tanpd = tcwl;
+
+ switch (ddr3_cfg->density) {
+ case 1: /* 1Gb per chip */
+ trfc = DIV_ROUND_UP(110000, clkper) - 1;
+ txs = DIV_ROUND_UP(120000, clkper) - 1;
+ break;
+ case 2: /* 2Gb per chip */
+ trfc = DIV_ROUND_UP(160000, clkper) - 1;
+ txs = DIV_ROUND_UP(170000, clkper) - 1;
+ break;
+ case 4: /* 4Gb per chip */
+ trfc = DIV_ROUND_UP(260000, clkper) - 1;
+ txs = DIV_ROUND_UP(270000, clkper) - 1;
+ break;
+ case 8: /* 8Gb per chip */
+ trfc = DIV_ROUND_UP(350000, clkper) - 1;
+ txs = DIV_ROUND_UP(360000, clkper) - 1;
+ break;
+ default:
+ /* invalid density */
+ puts("invalid chip density\n");
+ hang();
+ break;
+ }
+ txpr = txs;
+
+ switch (mem_speed) {
+ case 800:
+ txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
+ tcke = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
+ if (ddr3_cfg->pagesz == 1) {
+ tfaw = DIV_ROUND_UP(40000, clkper) - 1;
+ trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
+ } else {
+ tfaw = DIV_ROUND_UP(50000, clkper) - 1;
+ trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
+ }
+ break;
+ case 1066:
+ txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
+ tcke = DIV_ROUND_UP(max(3 * clkper, 5625), clkper) - 1;
+ if (ddr3_cfg->pagesz == 1) {
+ tfaw = DIV_ROUND_UP(37500, clkper) - 1;
+ trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1;
+ } else {
+ tfaw = DIV_ROUND_UP(50000, clkper) - 1;
+ trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
+ }
+ break;
+ default:
+ puts("invalid memory speed\n");
+ hang();
+ break;
+ }
+ txpdll = DIV_ROUND_UP(max(10 * clkper, 24000), clkper) - 1;
+ tcksre = DIV_ROUND_UP(max(5 * clkper, 10000), clkper);
+ taonpd = DIV_ROUND_UP(2000, clkper) - 1;
+ tcksrx = tcksre;
+ taofpd = taonpd;
+ twr = DIV_ROUND_UP(15000, clkper) - 1;
+ tmrd = DIV_ROUND_UP(max(12 * clkper, 15000), clkper) - 1;
+ trc = DIV_ROUND_UP(ddr3_cfg->trcmin, clkper / 10) - 1;
+ tras = DIV_ROUND_UP(ddr3_cfg->trasmin, clkper / 10) - 1;
+ tcl = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 3;
+ trp = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 1;
+ twtr = ROUND(max(4 * clkper, 7500) / clkper, 1) - 1;
+ trcd = trp;
+ trtp = twtr;
+ cs0_end = 4 * sysinfo->cs_density - 1;
+
+ debug("density:%d Gb (%d Gb per chip)\n",
+ sysinfo->cs_density, ddr3_cfg->density);
+ debug("clock: %dMHz (%d ps)\n", clock, clkper);
+ debug("memspd:%d\n", mem_speed);
+ debug("tcke=%d\n", tcke);
+ debug("tcksrx=%d\n", tcksrx);
+ debug("tcksre=%d\n", tcksre);
+ debug("taofpd=%d\n", taofpd);
+ debug("taonpd=%d\n", taonpd);
+ debug("todtlon=%d\n", todtlon);
+ debug("tanpd=%d\n", tanpd);
+ debug("taxpd=%d\n", taxpd);
+ debug("trfc=%d\n", trfc);
+ debug("txs=%d\n", txs);
+ debug("txp=%d\n", txp);
+ debug("txpdll=%d\n", txpdll);
+ debug("tfaw=%d\n", tfaw);
+ debug("tcl=%d\n", tcl);
+ debug("trcd=%d\n", trcd);
+ debug("trp=%d\n", trp);
+ debug("trc=%d\n", trc);
+ debug("tras=%d\n", tras);
+ debug("twr=%d\n", twr);
+ debug("tmrd=%d\n", tmrd);
+ debug("tcwl=%d\n", tcwl);
+ debug("tdllk=%d\n", tdllk);
+ debug("trtp=%d\n", trtp);
+ debug("twtr=%d\n", twtr);
+ debug("trrd=%d\n", trrd);
+ debug("txpr=%d\n", txpr);
+ debug("cs0_end=%d\n", cs0_end);
+ debug("ncs=%d\n", sysinfo->ncs);
+ debug("Rtt_wr=%d\n", sysinfo->rtt_wr);
+ debug("Rtt_nom=%d\n", sysinfo->rtt_nom);
+ debug("SRT=%d\n", ddr3_cfg->SRT);
+ debug("twr=%d\n", twr);
+
+ /*
+ * board-specific configuration:
+ * These values are determined empirically and vary per board layout
+ * see:
+ * appnote, ddr3 spreadsheet
+ */
+ mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
+ mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
+ mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
+ mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
+ mmdc0->mprddlctl = calib->p0_mprddlctl;
+ mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
+ if (sysinfo->dsize > 1) {
+ MMDC1(mpwldectrl0, calib->p1_mpwldectrl0);
+ MMDC1(mpwldectrl1, calib->p1_mpwldectrl1);
+ MMDC1(mpdgctrl0, calib->p1_mpdgctrl0);
+ MMDC1(mpdgctrl1, calib->p1_mpdgctrl1);
+ MMDC1(mprddlctl, calib->p1_mprddlctl);
+ MMDC1(mpwrdlctl, calib->p1_mpwrdlctl);
+ }
+
+ /* Read data DQ Byte0-3 delay */
+ mmdc0->mprddqby0dl = 0x33333333;
+ mmdc0->mprddqby1dl = 0x33333333;
+ if (sysinfo->dsize > 0) {
+ mmdc0->mprddqby2dl = 0x33333333;
+ mmdc0->mprddqby3dl = 0x33333333;
+ }
+
+ if (sysinfo->dsize > 1) {
+ MMDC1(mprddqby0dl, 0x33333333);
+ MMDC1(mprddqby1dl, 0x33333333);
+ MMDC1(mprddqby2dl, 0x33333333);
+ MMDC1(mprddqby3dl, 0x33333333);
+ }
+
+ /* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */
+ val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227;
+ mmdc0->mpodtctrl = val;
+ if (sysinfo->dsize > 1)
+ MMDC1(mpodtctrl, val);
+
+ /* complete calibration */
+ val = (1 << 11); /* Force measurement on delay-lines */
+ mmdc0->mpmur0 = val;
+ if (sysinfo->dsize > 1)
+ MMDC1(mpmur0, val);
+
+ /* Step 1: configuration request */
+ mmdc0->mdscr = (u32)(1 << 15); /* config request */
+
+ /* Step 2: Timing configuration */
+ mmdc0->mdcfg0 = (trfc << 24) | (txs << 16) | (txp << 13) |
+ (txpdll << 9) | (tfaw << 4) | tcl;
+ mmdc0->mdcfg1 = (trcd << 29) | (trp << 26) | (trc << 21) |
+ (tras << 16) | (1 << 15) /* trpa */ |
+ (twr << 9) | (tmrd << 5) | tcwl;
+ mmdc0->mdcfg2 = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;
+ mmdc0->mdotc = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) |
+ (taxpd << 16) | (todtlon << 12) | (todt_idle_off << 4);
+ mmdc0->mdasp = cs0_end; /* CS addressing */
+
+ /* Step 3: Configure DDR type */
+ mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
+ (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
+ (sysinfo->ralat << 6);
+
+ /* Step 4: Configure delay while leaving reset */
+ mmdc0->mdor = (txpr << 16) | (sysinfo->sde_to_rst << 8) |
+ (sysinfo->rst_to_cke << 0);
+
+ /* Step 5: Configure DDR physical parameters (density and burst len) */
+ coladdr = ddr3_cfg->coladdr;
+ if (ddr3_cfg->coladdr == 8) /* 8-bit COL is 0x3 */
+ coladdr += 4;
+ else if (ddr3_cfg->coladdr == 12) /* 12-bit COL is 0x4 */
+ coladdr += 1;
+ mmdc0->mdctl = (ddr3_cfg->rowaddr - 11) << 24 | /* ROW */
+ (coladdr - 9) << 20 | /* COL */
+ (1 << 19) | /* Burst Length = 8 for DDR3 */
+ (sysinfo->dsize << 16); /* DDR data bus size */
+
+ /* Step 6: Perform ZQ calibration */
+ val = 0xa1390001; /* one-time HW ZQ calib */
+ mmdc0->mpzqhwctrl = val;
+ if (sysinfo->dsize > 1)
+ MMDC1(mpzqhwctrl, val);
+
+ /* Step 7: Enable MMDC with desired chip select */
+ mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
+ ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
+
+ /* Step 8: Write Mode Registers to Init DDR3 devices */
+ for (cs = 0; cs < sysinfo->ncs; cs++) {
+ /* MR2 */
+ val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 |
+ ((tcwl - 3) & 3) << 3;
+ debug("MR2 CS%d: 0x%08x\n", cs, (u32)MR(val, 2, 3, cs));
+ mmdc0->mdscr = MR(val, 2, 3, cs);
+ /* MR3 */
+ debug("MR3 CS%d: 0x%08x\n", cs, (u32)MR(0, 3, 3, cs));
+ mmdc0->mdscr = MR(0, 3, 3, cs);
+ /* MR1 */
+ val = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 |
+ ((sysinfo->rtt_nom & 2) ? 1 : 0) << 6;
+ debug("MR1 CS%d: 0x%08x\n", cs, (u32)MR(val, 1, 3, cs));
+ mmdc0->mdscr = MR(val, 1, 3, cs);
+ /* MR0 */
+ val = ((tcl - 1) << 4) | /* CAS */
+ (1 << 8) | /* DLL Reset */
+ ((twr - 3) << 9) | /* Write Recovery */
+ (sysinfo->pd_fast_exit << 12); /* Precharge PD PLL on */
+ debug("MR0 CS%d: 0x%08x\n", cs, (u32)MR(val, 0, 3, cs));
+ mmdc0->mdscr = MR(val, 0, 3, cs);
+ /* ZQ calibration */
+ val = (1 << 10);
+ mmdc0->mdscr = MR(val, 0, 4, cs);
+ }
+
+ /* Step 10: Power down control and self-refresh */
+ mmdc0->mdpdc = (tcke & 0x7) << 16 |
+ 5 << 12 | /* PWDT_1: 256 cycles */
+ 5 << 8 | /* PWDT_0: 256 cycles */
+ 1 << 6 | /* BOTH_CS_PD */
+ (tcksrx & 0x7) << 3 |
+ (tcksre & 0x7);
+ if (!sysinfo->pd_fast_exit)
+ mmdc0->mdpdc |= (1 << 7); /* SLOW_PD */
+ mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
+
+ /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
+ val = 0xa1390003;
+ mmdc0->mpzqhwctrl = val;
+ if (sysinfo->dsize > 1)
+ MMDC1(mpzqhwctrl, val);
+
+ /* Step 12: Configure and activate periodic refresh */
+ mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);
+
+ /* Step 13: Deassert config request - init complete */
+ mmdc0->mdscr = 0x00000000;
+
+ /* wait for auto-ZQ calibration to complete */
+ mdelay(1);
+}
+
+void mmdc_read_calibration(struct mx6_ddr_sysinfo const *sysinfo,
+ struct mx6_mmdc_calibration *calib)
+{
+ struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
+ struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
+
+ calib->p0_mpwldectrl0 = readl(&mmdc0->mpwldectrl0);
+ calib->p0_mpwldectrl1 = readl(&mmdc0->mpwldectrl1);
+ calib->p0_mpdgctrl0 = readl(&mmdc0->mpdgctrl0);
+ calib->p0_mpdgctrl1 = readl(&mmdc0->mpdgctrl1);
+ calib->p0_mprddlctl = readl(&mmdc0->mprddlctl);
+ calib->p0_mpwrdlctl = readl(&mmdc0->mpwrdlctl);
+
+ if (sysinfo->dsize == 2) {
+ calib->p1_mpwldectrl0 = readl(&mmdc1->mpwldectrl0);
+ calib->p1_mpwldectrl1 = readl(&mmdc1->mpwldectrl1);
+ calib->p1_mpdgctrl0 = readl(&mmdc1->mpdgctrl0);
+ calib->p1_mpdgctrl1 = readl(&mmdc1->mpdgctrl1);
+ calib->p1_mprddlctl = readl(&mmdc1->mprddlctl);
+ calib->p1_mpwrdlctl = readl(&mmdc1->mpwrdlctl);
+ }
+}
+
+void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
+ const struct mx6_mmdc_calibration *calib,
+ const void *ddr_cfg)
+{
+ if (sysinfo->ddr_type == DDR_TYPE_DDR3) {
+ mx6_ddr3_cfg(sysinfo, calib, ddr_cfg);
+ } else if (sysinfo->ddr_type == DDR_TYPE_LPDDR2) {
+ mx6_lpddr2_cfg(sysinfo, calib, ddr_cfg);
+ } else {
+ puts("Unsupported ddr type\n");
+ hang();
+ }
+}
--- /dev/null
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright (C) 2016 Grinn
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6ul_pins.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <linux/sizes.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const emmc_pads[] = {
+ MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ /* RST_B */
+ MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#ifdef CONFIG_FSL_ESDHC
+static struct fsl_esdhc_cfg emmc_cfg = {USDHC2_BASE_ADDR, 0, 8};
+
+#define EMMC_PWR_GPIO IMX_GPIO_NR(4, 10)
+
+int litesom_mmc_init(bd_t *bis)
+{
+ int ret;
+
+ /* eMMC */
+ imx_iomux_v3_setup_multiple_pads(emmc_pads, ARRAY_SIZE(emmc_pads));
+ gpio_direction_output(EMMC_PWR_GPIO, 0);
+ udelay(500);
+ gpio_direction_output(EMMC_PWR_GPIO, 1);
+ emmc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
+ ret = fsl_esdhc_initialize(bis, &emmc_cfg);
+ if (ret) {
+ printf("Warning: failed to initialize mmc dev 1 (eMMC)\n");
+ return ret;
+ }
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#include <libfdt.h>
+#include <spl.h>
+#include <asm/arch/mx6-ddr.h>
+
+
+static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
+ .grp_addds = 0x00000030,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_b0ds = 0x00000030,
+ .grp_ctlds = 0x00000030,
+ .grp_b1ds = 0x00000030,
+ .grp_ddrpke = 0x00000000,
+ .grp_ddrmode = 0x00020000,
+ .grp_ddr_type = 0x000c0000,
+};
+
+static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
+ .dram_dqm0 = 0x00000030,
+ .dram_dqm1 = 0x00000030,
+ .dram_ras = 0x00000030,
+ .dram_cas = 0x00000030,
+ .dram_odt0 = 0x00000030,
+ .dram_odt1 = 0x00000030,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdclk_0 = 0x00000030,
+ .dram_sdqs0 = 0x00000030,
+ .dram_sdqs1 = 0x00000030,
+ .dram_reset = 0x00000030,
+};
+
+static struct mx6_mmdc_calibration mx6_mmcd_calib = {
+ .p0_mpwldectrl0 = 0x00000000,
+ .p0_mpdgctrl0 = 0x41570155,
+ .p0_mprddlctl = 0x4040474A,
+ .p0_mpwrdlctl = 0x40405550,
+};
+
+struct mx6_ddr_sysinfo ddr_sysinfo = {
+ .dsize = 0,
+ .cs_density = 20,
+ .ncs = 1,
+ .cs1_mirror = 0,
+ .rtt_wr = 2,
+ .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
+ .walat = 0, /* Write additional latency */
+ .ralat = 5, /* Read additional latency */
+ .mif3_mode = 3, /* Command prediction working mode */
+ .bi_on = 1, /* Bank interleaving enabled */
+ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
+ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+ .ddr_type = DDR_TYPE_DDR3,
+ .refsel = 0, /* Refresh cycles at 64KHz */
+ .refr = 1, /* 2 refresh commands per refresh cycle */
+};
+
+static struct mx6_ddr3_cfg mem_ddr = {
+ .mem_speed = 800,
+ .density = 4,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 15,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+};
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0xFFFFFFFF, &ccm->CCGR0);
+ writel(0xFFFFFFFF, &ccm->CCGR1);
+ writel(0xFFFFFFFF, &ccm->CCGR2);
+ writel(0xFFFFFFFF, &ccm->CCGR3);
+ writel(0xFFFFFFFF, &ccm->CCGR4);
+ writel(0xFFFFFFFF, &ccm->CCGR5);
+ writel(0xFFFFFFFF, &ccm->CCGR6);
+ writel(0xFFFFFFFF, &ccm->CCGR7);
+}
+
+static void spl_dram_init(void)
+{
+ unsigned long ram_size;
+
+ mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+ mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
+
+ /*
+ * Get actual RAM size, so we can adjust DDR row size for <512M
+ * memories
+ */
+ ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_512M);
+ if (ram_size < SZ_512M) {
+ mem_ddr.rowaddr = 14;
+ mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
+ }
+}
+
+void litesom_init_f(void)
+{
+ ccgr_init();
+
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+ board_early_init_f();
+#endif
+
+ /* setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* DDR initialization */
+ spl_dram_init();
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2014
+ * Gabriel Huau <contact@huau-gabriel.fr>
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/imx-regs.h>
+
+#define MAX_CPUS 4
+static struct src *src = (struct src *)SRC_BASE_ADDR;
+
+static uint32_t cpu_reset_mask[MAX_CPUS] = {
+ 0, /* We don't really want to modify the cpu0 */
+ SRC_SCR_CORE_1_RESET_MASK,
+ SRC_SCR_CORE_2_RESET_MASK,
+ SRC_SCR_CORE_3_RESET_MASK
+};
+
+static uint32_t cpu_ctrl_mask[MAX_CPUS] = {
+ 0, /* We don't really want to modify the cpu0 */
+ SRC_SCR_CORE_1_ENABLE_MASK,
+ SRC_SCR_CORE_2_ENABLE_MASK,
+ SRC_SCR_CORE_3_ENABLE_MASK
+};
+
+int cpu_reset(int nr)
+{
+ /* Software reset of the CPU N */
+ src->scr |= cpu_reset_mask[nr];
+ return 0;
+}
+
+int cpu_status(int nr)
+{
+ printf("core %d => %d\n", nr, !!(src->scr & cpu_ctrl_mask[nr]));
+ return 0;
+}
+
+int cpu_release(int nr, int argc, char *const argv[])
+{
+ uint32_t boot_addr;
+
+ boot_addr = simple_strtoul(argv[0], NULL, 16);
+
+ switch (nr) {
+ case 1:
+ src->gpr3 = boot_addr;
+ break;
+ case 2:
+ src->gpr5 = boot_addr;
+ break;
+ case 3:
+ src->gpr7 = boot_addr;
+ break;
+ default:
+ return 1;
+ }
+
+ /* CPU N is ready to start */
+ src->scr |= cpu_ctrl_mask[nr];
+
+ return 0;
+}
+
+int is_core_valid(unsigned int core)
+{
+ uint32_t nr_cores = get_nr_cpus();
+
+ if (core > nr_cores)
+ return 0;
+
+ return 1;
+}
+
+int cpu_disable(int nr)
+{
+ /* Disable the CPU N */
+ src->scr &= ~cpu_ctrl_mask[nr];
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2017 Armadeus Systems
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/mx6ul_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/io.h>
+#include <common.h>
+#include <environment.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_FEC_MXC
+#include <miiphy.h>
+
+#define MDIO_PAD_CTRL ( \
+ PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm \
+)
+
+#define ENET_PAD_CTRL_PU ( \
+ PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm \
+)
+
+#define ENET_PAD_CTRL_PD ( \
+ PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm \
+)
+
+#define ENET_CLK_PAD_CTRL ( \
+ PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST \
+)
+
+static iomux_v3_cfg_t const fec1_pads[] = {
+ MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
+ MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(MDIO_PAD_CTRL),
+ MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+ MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+ MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+ MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+ MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
+ MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
+ MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
+ /* PHY Int */
+ MX6_PAD_NAND_DQS__GPIO4_IO16 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
+ /* PHY Reset */
+ MX6_PAD_NAND_DATA00__GPIO4_IO02 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+ MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
+};
+
+int board_phy_config(struct phy_device *phydev)
+{
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ struct gpio_desc rst;
+ int ret;
+
+ /* Use 50M anatop loopback REF_CLK1 for ENET1,
+ * clear gpr1[13], set gpr1[17] */
+ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
+ IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
+
+ ret = enable_fec_anatop_clock(0, ENET_50MHZ);
+ if (ret)
+ return ret;
+
+ enable_enet_clk(1);
+
+ imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
+
+ ret = dm_gpio_lookup_name("GPIO4_2", &rst);
+ if (ret) {
+ printf("Cannot get GPIO4_2\n");
+ return ret;
+ }
+
+ ret = dm_gpio_request(&rst, "phy-rst");
+ if (ret) {
+ printf("Cannot request GPIO4_2\n");
+ return ret;
+ }
+
+ dm_gpio_set_dir_flags(&rst, GPIOD_IS_OUT);
+ dm_gpio_set_value(&rst, 0);
+ udelay(1000);
+ dm_gpio_set_value(&rst, 1);
+
+ return fecmxc_initialize(bis);
+}
+#endif /* CONFIG_FEC_MXC */
+
+int board_init(void)
+{
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+int __weak opos6ul_board_late_init(void)
+{
+ return 0;
+}
+
+int board_late_init(void)
+{
+ struct src *psrc = (struct src *)SRC_BASE_ADDR;
+ unsigned reg = readl(&psrc->sbmr2);
+
+ /* In bootstrap don't use the env vars */
+ if (((reg & 0x3000000) >> 24) == 0x1) {
+ set_default_env(NULL);
+ setenv("preboot", "");
+ }
+
+ return opos6ul_board_late_init();
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ return cfg->esdhc_base == USDHC1_BASE_ADDR;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+
+ return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/opos6ul.h>
+#include <libfdt.h>
+#include <spl.h>
+
+#define USDHC_PAD_CTRL ( \
+ PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST \
+)
+
+struct fsl_esdhc_cfg usdhc_cfg[1] = {
+ {USDHC1_BASE_ADDR, 0, 8},
+};
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+ MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
+ .grp_addds = 0x00000030,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_b0ds = 0x00000030,
+ .grp_ctlds = 0x00000030,
+ .grp_b1ds = 0x00000030,
+ .grp_ddrpke = 0x00000000,
+ .grp_ddrmode = 0x00020000,
+ .grp_ddr_type = 0x000c0000,
+};
+
+static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
+ .dram_dqm0 = 0x00000030,
+ .dram_dqm1 = 0x00000030,
+ .dram_ras = 0x00000030,
+ .dram_cas = 0x00000030,
+ .dram_odt0 = 0x00000030,
+ .dram_odt1 = 0x00000030,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdclk_0 = 0x00000008,
+ .dram_sdqs0 = 0x00000038,
+ .dram_sdqs1 = 0x00000030,
+ .dram_reset = 0x00000030,
+};
+
+static struct mx6_mmdc_calibration mx6_mmcd_calib = {
+ .p0_mpwldectrl0 = 0x00070007,
+ .p0_mpdgctrl0 = 0x41490145,
+ .p0_mprddlctl = 0x40404546,
+ .p0_mpwrdlctl = 0x4040524D,
+};
+
+struct mx6_ddr_sysinfo ddr_sysinfo = {
+ .dsize = 0,
+ .cs_density = 20,
+ .ncs = 1,
+ .cs1_mirror = 0,
+ .rtt_wr = 2,
+ .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
+ .walat = 1, /* Write additional latency */
+ .ralat = 5, /* Read additional latency */
+ .mif3_mode = 3, /* Command prediction working mode */
+ .bi_on = 1, /* Bank interleaving enabled */
+ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
+ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+ .ddr_type = DDR_TYPE_DDR3,
+};
+
+static struct mx6_ddr3_cfg mem_ddr = {
+ .mem_speed = 800,
+ .density = 2,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 14,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1500,
+ .trcmin = 5250,
+ .trasmin = 3750,
+};
+
+int board_mmc_init(bd_t *bis)
+{
+ imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0xFFFFFFFF, &ccm->CCGR0);
+ writel(0xFFFFFFFF, &ccm->CCGR1);
+ writel(0xFFFFFFFF, &ccm->CCGR2);
+ writel(0xFFFFFFFF, &ccm->CCGR3);
+ writel(0xFFFFFFFF, &ccm->CCGR4);
+ writel(0xFFFFFFFF, &ccm->CCGR5);
+ writel(0xFFFFFFFF, &ccm->CCGR6);
+ writel(0xFFFFFFFF, &ccm->CCGR7);
+}
+
+static void spl_dram_init(void)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[4];
+ struct fuse_bank4_regs *fuse =
+ (struct fuse_bank4_regs *)bank->fuse_regs;
+ int reg = readl(&fuse->gp1);
+
+ /* 512MB of RAM */
+ if (reg & 0x1) {
+ mem_ddr.density = 4;
+ mem_ddr.rowaddr = 15;
+ mem_ddr.trcd = 1375;
+ mem_ddr.trcmin = 4875;
+ mem_ddr.trasmin = 3500;
+ }
+
+ mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+ mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
+}
+
+void board_init_f(ulong dummy)
+{
+ ccgr_init();
+
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ /* setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ opos6ul_setup_uart_debug();
+ preloader_console_init();
+
+ /* DDR initialization */
+ spl_dram_init();
+}
+#endif /* CONFIG_SPL_BUILD */
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/errno.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/dma.h>
+#include <asm/mach-imx/hab.h>
+#include <stdbool.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/crm_regs.h>
+#include <dm.h>
+#include <imx_thermal.h>
+#include <mmc.h>
+
+enum ldo_reg {
+ LDO_ARM,
+ LDO_SOC,
+ LDO_PU,
+};
+
+struct scu_regs {
+ u32 ctrl;
+ u32 config;
+ u32 status;
+ u32 invalidate;
+ u32 fpga_rev;
+};
+
+#if defined(CONFIG_IMX_THERMAL)
+static const struct imx_thermal_plat imx6_thermal_plat = {
+ .regs = (void *)ANATOP_BASE_ADDR,
+ .fuse_bank = 1,
+ .fuse_word = 6,
+};
+
+U_BOOT_DEVICE(imx6_thermal) = {
+ .name = "imx_thermal",
+ .platdata = &imx6_thermal_plat,
+};
+#endif
+
+#if defined(CONFIG_SECURE_BOOT)
+struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
+ .bank = 0,
+ .word = 6,
+};
+#endif
+
+u32 get_nr_cpus(void)
+{
+ struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
+ return readl(&scu->config) & 3;
+}
+
+u32 get_cpu_rev(void)
+{
+ struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+ u32 reg = readl(&anatop->digprog_sololite);
+ u32 type = ((reg >> 16) & 0xff);
+ u32 major, cfg = 0;
+
+ if (type != MXC_CPU_MX6SL) {
+ reg = readl(&anatop->digprog);
+ struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
+ cfg = readl(&scu->config) & 3;
+ type = ((reg >> 16) & 0xff);
+ if (type == MXC_CPU_MX6DL) {
+ if (!cfg)
+ type = MXC_CPU_MX6SOLO;
+ }
+
+ if (type == MXC_CPU_MX6Q) {
+ if (cfg == 1)
+ type = MXC_CPU_MX6D;
+ }
+
+ }
+ major = ((reg >> 8) & 0xff);
+ if ((major >= 1) &&
+ ((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) {
+ major--;
+ type = MXC_CPU_MX6QP;
+ if (cfg == 1)
+ type = MXC_CPU_MX6DP;
+ }
+ reg &= 0xff; /* mx6 silicon revision */
+ return (type << 12) | (reg + (0x10 * (major + 1)));
+}
+
+/*
+ * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440)
+ * defines a 2-bit SPEED_GRADING
+ */
+#define OCOTP_CFG3_SPEED_SHIFT 16
+#define OCOTP_CFG3_SPEED_800MHZ 0
+#define OCOTP_CFG3_SPEED_850MHZ 1
+#define OCOTP_CFG3_SPEED_1GHZ 2
+#define OCOTP_CFG3_SPEED_1P2GHZ 3
+
+/*
+ * For i.MX6UL
+ */
+#define OCOTP_CFG3_SPEED_528MHZ 1
+#define OCOTP_CFG3_SPEED_696MHZ 2
+
+u32 get_cpu_speed_grade_hz(void)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[0];
+ struct fuse_bank0_regs *fuse =
+ (struct fuse_bank0_regs *)bank->fuse_regs;
+ uint32_t val;
+
+ val = readl(&fuse->cfg3);
+ val >>= OCOTP_CFG3_SPEED_SHIFT;
+ val &= 0x3;
+
+ if (is_mx6ul() || is_mx6ull()) {
+ if (val == OCOTP_CFG3_SPEED_528MHZ)
+ return 528000000;
+ else if (val == OCOTP_CFG3_SPEED_696MHZ)
+ return 69600000;
+ else
+ return 0;
+ }
+
+ switch (val) {
+ /* Valid for IMX6DQ */
+ case OCOTP_CFG3_SPEED_1P2GHZ:
+ if (is_mx6dq() || is_mx6dqp())
+ return 1200000000;
+ /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
+ case OCOTP_CFG3_SPEED_1GHZ:
+ return 996000000;
+ /* Valid for IMX6DQ */
+ case OCOTP_CFG3_SPEED_850MHZ:
+ if (is_mx6dq() || is_mx6dqp())
+ return 852000000;
+ /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
+ case OCOTP_CFG3_SPEED_800MHZ:
+ return 792000000;
+ }
+ return 0;
+}
+
+/*
+ * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480)
+ * defines a 2-bit Temperature Grade
+ *
+ * return temperature grade and min/max temperature in Celsius
+ */
+#define OCOTP_MEM0_TEMP_SHIFT 6
+
+u32 get_cpu_temp_grade(int *minc, int *maxc)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[1];
+ struct fuse_bank1_regs *fuse =
+ (struct fuse_bank1_regs *)bank->fuse_regs;
+ uint32_t val;
+
+ val = readl(&fuse->mem0);
+ val >>= OCOTP_MEM0_TEMP_SHIFT;
+ val &= 0x3;
+
+ if (minc && maxc) {
+ if (val == TEMP_AUTOMOTIVE) {
+ *minc = -40;
+ *maxc = 125;
+ } else if (val == TEMP_INDUSTRIAL) {
+ *minc = -40;
+ *maxc = 105;
+ } else if (val == TEMP_EXTCOMMERCIAL) {
+ *minc = -20;
+ *maxc = 105;
+ } else {
+ *minc = 0;
+ *maxc = 95;
+ }
+ }
+ return val;
+}
+
+#ifdef CONFIG_REVISION_TAG
+u32 __weak get_board_rev(void)
+{
+ u32 cpurev = get_cpu_rev();
+ u32 type = ((cpurev >> 12) & 0xff);
+ if (type == MXC_CPU_MX6SOLO)
+ cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
+
+ if (type == MXC_CPU_MX6D)
+ cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
+
+ return cpurev;
+}
+#endif
+
+static void clear_ldo_ramp(void)
+{
+ struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+ int reg;
+
+ /* ROM may modify LDO ramp up time according to fuse setting, so in
+ * order to be in the safe side we neeed to reset these settings to
+ * match the reset value: 0'b00
+ */
+ reg = readl(&anatop->ana_misc2);
+ reg &= ~(0x3f << 24);
+ writel(reg, &anatop->ana_misc2);
+}
+
+/*
+ * Set the PMU_REG_CORE register
+ *
+ * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
+ * Possible values are from 0.725V to 1.450V in steps of
+ * 0.025V (25mV).
+ */
+static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
+{
+ struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+ u32 val, step, old, reg = readl(&anatop->reg_core);
+ u8 shift;
+
+ if (mv < 725)
+ val = 0x00; /* Power gated off */
+ else if (mv > 1450)
+ val = 0x1F; /* Power FET switched full on. No regulation */
+ else
+ val = (mv - 700) / 25;
+
+ clear_ldo_ramp();
+
+ switch (ldo) {
+ case LDO_SOC:
+ shift = 18;
+ break;
+ case LDO_PU:
+ shift = 9;
+ break;
+ case LDO_ARM:
+ shift = 0;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ old = (reg & (0x1F << shift)) >> shift;
+ step = abs(val - old);
+ if (step == 0)
+ return 0;
+
+ reg = (reg & ~(0x1F << shift)) | (val << shift);
+ writel(reg, &anatop->reg_core);
+
+ /*
+ * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
+ * step
+ */
+ udelay(3 * step);
+
+ return 0;
+}
+
+static void set_ahb_rate(u32 val)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ u32 reg, div;
+
+ div = get_periph_clk() / val - 1;
+ reg = readl(&mxc_ccm->cbcdr);
+
+ writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
+ (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
+}
+
+static void clear_mmdc_ch_mask(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ u32 reg;
+ reg = readl(&mxc_ccm->ccdr);
+
+ /* Clear MMDC channel mask */
+ if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl())
+ reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
+ else
+ reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
+ writel(reg, &mxc_ccm->ccdr);
+}
+
+#define OCOTP_MEM0_REFTOP_TRIM_SHIFT 8
+
+static void init_bandgap(void)
+{
+ struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[1];
+ struct fuse_bank1_regs *fuse =
+ (struct fuse_bank1_regs *)bank->fuse_regs;
+ uint32_t val;
+
+ /*
+ * Ensure the bandgap has stabilized.
+ */
+ while (!(readl(&anatop->ana_misc0) & 0x80))
+ ;
+ /*
+ * For best noise performance of the analog blocks using the
+ * outputs of the bandgap, the reftop_selfbiasoff bit should
+ * be set.
+ */
+ writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
+ /*
+ * On i.MX6ULL,we need to set VBGADJ bits according to the
+ * REFTOP_TRIM[3:0] in fuse table
+ * 000 - set REFTOP_VBGADJ[2:0] to 3b'110,
+ * 110 - set REFTOP_VBGADJ[2:0] to 3b'000,
+ * 001 - set REFTOP_VBGADJ[2:0] to 3b'001,
+ * 010 - set REFTOP_VBGADJ[2:0] to 3b'010,
+ * 011 - set REFTOP_VBGADJ[2:0] to 3b'011,
+ * 100 - set REFTOP_VBGADJ[2:0] to 3b'100,
+ * 101 - set REFTOP_VBGADJ[2:0] to 3b'101,
+ * 111 - set REFTOP_VBGADJ[2:0] to 3b'111,
+ */
+ if (is_mx6ull()) {
+ val = readl(&fuse->mem0);
+ val >>= OCOTP_MEM0_REFTOP_TRIM_SHIFT;
+ val &= 0x7;
+
+ writel(val << BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT,
+ &anatop->ana_misc0_set);
+ }
+}
+
+#ifdef CONFIG_MX6SL
+static void set_preclk_from_osc(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ u32 reg;
+
+ reg = readl(&mxc_ccm->cscmr1);
+ reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
+ writel(reg, &mxc_ccm->cscmr1);
+}
+#endif
+
+int arch_cpu_init(void)
+{
+ init_aips();
+
+ /* Need to clear MMDC_CHx_MASK to make warm reset work. */
+ clear_mmdc_ch_mask();
+
+ /*
+ * Disable self-bias circuit in the analog bandap.
+ * The self-bias circuit is used by the bandgap during startup.
+ * This bit should be set after the bandgap has initialized.
+ */
+ init_bandgap();
+
+ if (!is_mx6ul() && !is_mx6ull()) {
+ /*
+ * When low freq boot is enabled, ROM will not set AHB
+ * freq, so we need to ensure AHB freq is 132MHz in such
+ * scenario.
+ *
+ * To i.MX6UL, when power up, default ARM core and
+ * AHB rate is 396M and 132M.
+ */
+ if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
+ set_ahb_rate(132000000);
+ }
+
+ if (is_mx6ul()) {
+ if (is_soc_rev(CHIP_REV_1_0) == 0) {
+ /*
+ * According to the design team's requirement on
+ * i.MX6UL,the PMIC_STBY_REQ PAD should be configured
+ * as open drain 100K (0x0000b8a0).
+ * Only exists on TO1.0
+ */
+ writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c);
+ } else {
+ /*
+ * From TO1.1, SNVS adds internal pull up control
+ * for POR_B, the register filed is GPBIT[1:0],
+ * after system boot up, it can be set to 2b'01
+ * to disable internal pull up.It can save about
+ * 30uA power in SNVS mode.
+ */
+ writel((readl(MX6UL_SNVS_LP_BASE_ADDR + 0x10) &
+ (~0x1400)) | 0x400,
+ MX6UL_SNVS_LP_BASE_ADDR + 0x10);
+ }
+ }
+
+ if (is_mx6ull()) {
+ /*
+ * GPBIT[1:0] is suggested to set to 2'b11:
+ * 2'b00 : always PUP100K
+ * 2'b01 : PUP100K when PMIC_ON_REQ or SOC_NOT_FAIL
+ * 2'b10 : always disable PUP100K
+ * 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL
+ * register offset is different from i.MX6UL, since
+ * i.MX6UL is fixed by ECO.
+ */
+ writel(readl(MX6UL_SNVS_LP_BASE_ADDR) |
+ 0x3, MX6UL_SNVS_LP_BASE_ADDR);
+ }
+
+ /* Set perclk to source from OSC 24MHz */
+#if defined(CONFIG_MX6SL)
+ set_preclk_from_osc();
+#endif
+
+ imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
+
+ init_src();
+
+ return 0;
+}
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+__weak int board_mmc_get_env_dev(int devno)
+{
+ return CONFIG_SYS_MMC_ENV_DEV;
+}
+
+static int mmc_get_boot_dev(void)
+{
+ struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+ u32 soc_sbmr = readl(&src_regs->sbmr1);
+ u32 bootsel;
+ int devno;
+
+ /*
+ * Refer to
+ * "i.MX 6Dual/6Quad Applications Processor Reference Manual"
+ * Chapter "8.5.3.1 Expansion Device eFUSE Configuration"
+ * i.MX6SL/SX/UL has same layout.
+ */
+ bootsel = (soc_sbmr & 0x000000FF) >> 6;
+
+ /* No boot from sd/mmc */
+ if (bootsel != 1)
+ return -1;
+
+ /* BOOT_CFG2[3] and BOOT_CFG2[4] */
+ devno = (soc_sbmr & 0x00001800) >> 11;
+
+ return devno;
+}
+
+int mmc_get_env_dev(void)
+{
+ int devno = mmc_get_boot_dev();
+
+ /* If not boot from sd/mmc, use default value */
+ if (devno < 0)
+ return CONFIG_SYS_MMC_ENV_DEV;
+
+ return board_mmc_get_env_dev(devno);
+}
+
+#ifdef CONFIG_SYS_MMC_ENV_PART
+__weak int board_mmc_get_env_part(int devno)
+{
+ return CONFIG_SYS_MMC_ENV_PART;
+}
+
+uint mmc_get_env_part(struct mmc *mmc)
+{
+ int devno = mmc_get_boot_dev();
+
+ /* If not boot from sd/mmc, use default value */
+ if (devno < 0)
+ return CONFIG_SYS_MMC_ENV_PART;
+
+ return board_mmc_get_env_part(devno);
+}
+#endif
+#endif
+
+int board_postclk_init(void)
+{
+ set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
+
+ return 0;
+}
+
+#if defined(CONFIG_FEC_MXC)
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[4];
+ struct fuse_bank4_regs *fuse =
+ (struct fuse_bank4_regs *)bank->fuse_regs;
+
+ if ((is_mx6sx() || is_mx6ul() || is_mx6ull()) && dev_id == 1) {
+ u32 value = readl(&fuse->mac_addr2);
+ mac[0] = value >> 24 ;
+ mac[1] = value >> 16 ;
+ mac[2] = value >> 8 ;
+ mac[3] = value ;
+
+ value = readl(&fuse->mac_addr1);
+ mac[4] = value >> 24 ;
+ mac[5] = value >> 16 ;
+
+ } else {
+ u32 value = readl(&fuse->mac_addr1);
+ mac[0] = (value >> 8);
+ mac[1] = value ;
+
+ value = readl(&fuse->mac_addr0);
+ mac[2] = value >> 24 ;
+ mac[3] = value >> 16 ;
+ mac[4] = value >> 8 ;
+ mac[5] = value ;
+ }
+
+}
+#endif
+
+/*
+ * cfg_val will be used for
+ * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
+ * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
+ * instead of SBMR1 to determine the boot device.
+ */
+const struct boot_mode soc_boot_modes[] = {
+ {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
+ /* reserved value should start rom usb */
+#if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
+ {"usb", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
+#else
+ {"usb", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
+#endif
+ {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
+ {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
+ {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
+ {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
+ {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
+ /* 4 bit bus width */
+ {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
+ {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+ {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+ {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+ {NULL, 0},
+};
+
+void reset_misc(void)
+{
+#ifdef CONFIG_VIDEO_MXS
+ lcdif_power_down();
+#endif
+}
+
+void s_init(void)
+{
+ struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ u32 mask480;
+ u32 mask528;
+ u32 reg, periph1, periph2;
+
+ if (is_mx6sx() || is_mx6ul() || is_mx6ull())
+ return;
+
+ /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
+ * to make sure PFD is working right, otherwise, PFDs may
+ * not output clock after reset, MX6DL and MX6SL have added 396M pfd
+ * workaround in ROM code, as bus clock need it
+ */
+
+ mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
+ ANATOP_PFD_CLKGATE_MASK(1) |
+ ANATOP_PFD_CLKGATE_MASK(2) |
+ ANATOP_PFD_CLKGATE_MASK(3);
+ mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
+ ANATOP_PFD_CLKGATE_MASK(3);
+
+ reg = readl(&ccm->cbcmr);
+ periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
+ >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
+ periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
+ >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
+
+ /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
+ if ((periph2 != 0x2) && (periph1 != 0x2))
+ mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
+
+ if ((periph2 != 0x1) && (periph1 != 0x1) &&
+ (periph2 != 0x3) && (periph1 != 0x3))
+ mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
+
+ writel(mask480, &anatop->pfd_480_set);
+ writel(mask528, &anatop->pfd_528_set);
+ writel(mask480, &anatop->pfd_480_clr);
+ writel(mask528, &anatop->pfd_528_clr);
+}
+
+#ifdef CONFIG_IMX_HDMI
+void imx_enable_hdmi_phy(void)
+{
+ struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
+ u8 reg;
+ reg = readb(&hdmi->phy_conf0);
+ reg |= HDMI_PHY_CONF0_PDZ_MASK;
+ writeb(reg, &hdmi->phy_conf0);
+ udelay(3000);
+ reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
+ writeb(reg, &hdmi->phy_conf0);
+ udelay(3000);
+ reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
+ writeb(reg, &hdmi->phy_conf0);
+ writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
+}
+
+void imx_setup_hdmi(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
+ int reg, count;
+ u8 val;
+
+ /* Turn on HDMI PHY clock */
+ reg = readl(&mxc_ccm->CCGR2);
+ reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
+ MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
+ writel(reg, &mxc_ccm->CCGR2);
+ writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
+ reg = readl(&mxc_ccm->chsccdr);
+ reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
+ MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
+ MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
+ reg |= (CHSCCDR_PODF_DIVIDE_BY_3
+ << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
+ |(CHSCCDR_IPU_PRE_CLK_540M_PFD
+ << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
+ writel(reg, &mxc_ccm->chsccdr);
+
+ /* Clear the overflow condition */
+ if (readb(&hdmi->ih_fc_stat2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) {
+ /* TMDS software reset */
+ writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &hdmi->mc_swrstz);
+ val = readb(&hdmi->fc_invidconf);
+ /* Need minimum 3 times to write to clear the register */
+ for (count = 0 ; count < 5 ; count++)
+ writeb(val, &hdmi->fc_invidconf);
+ }
+}
+#endif
+
+#ifdef CONFIG_IMX_BOOTAUX
+int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
+{
+ struct src *src_reg;
+ u32 stack, pc;
+
+ if (!boot_private_data)
+ return -EINVAL;
+
+ stack = *(u32 *)boot_private_data;
+ pc = *(u32 *)(boot_private_data + 4);
+
+ /* Set the stack and pc to M4 bootROM */
+ writel(stack, M4_BOOTROM_BASE_ADDR);
+ writel(pc, M4_BOOTROM_BASE_ADDR + 4);
+
+ /* Enable M4 */
+ src_reg = (struct src *)SRC_BASE_ADDR;
+ clrsetbits_le32(&src_reg->scr, SRC_SCR_M4C_NON_SCLR_RST_MASK,
+ SRC_SCR_M4_ENABLE_MASK);
+
+ return 0;
+}
+
+int arch_auxiliary_core_check_up(u32 core_id)
+{
+ struct src *src_reg = (struct src *)SRC_BASE_ADDR;
+ unsigned val;
+
+ val = readl(&src_reg->scr);
+
+ if (val & SRC_SCR_M4C_NON_SCLR_RST_MASK)
+ return 0; /* assert in reset */
+
+ return 1;
+}
+#endif
--- /dev/null
+if ARCH_MX7
+
+config MX7
+ bool
+ select ROM_UNIFIED_SECTIONS
+ select CPU_V7_HAS_VIRT
+ select CPU_V7_HAS_NONSEC
+ select ARCH_SUPPORT_PSCI
+ imply CMD_FUSE
+ default y
+
+config MX7D
+ select ROM_UNIFIED_SECTIONS
+ imply CMD_FUSE
+ bool
+ imply ENV_IS_IN_MMC
+
+choice
+ prompt "MX7 board select"
+ optional
+
+config TARGET_MX7DSABRESD
+ bool "mx7dsabresd"
+ select BOARD_LATE_INIT
+ select MX7D
+ select DM
+ select DM_THERMAL
+
+config TARGET_PICO_IMX7D
+ bool "pico-imx7d"
+ select BOARD_LATE_INIT
+ select MX7D
+ select DM
+ select DM_THERMAL
+
+config TARGET_WARP7
+ bool "warp7"
+ select BOARD_LATE_INIT
+ select MX7D
+ select DM
+ select DM_THERMAL
+
+config TARGET_COLIBRI_IMX7
+ bool "Support Colibri iMX7S/iMX7D modules"
+ select BOARD_LATE_INIT
+ select DM
+ select DM_SERIAL
+ select DM_THERMAL
+
+endchoice
+
+config SYS_SOC
+ default "mx7"
+
+source "board/freescale/mx7dsabresd/Kconfig"
+source "board/technexion/pico-imx7d/Kconfig"
+source "board/toradex/colibri_imx7/Kconfig"
+source "board/warp7/Kconfig"
+
+endif
--- /dev/null
+#
+# (C) Copyright 2015 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+#
+
+obj-y := soc.o clock.o clock_slice.o
+
+ifdef CONFIG_ARMV7_PSCI
+obj-y += psci-mx7.o psci.o
+endif
--- /dev/null
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Author:
+ * Peng Fan <Peng.Fan@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+
+struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
+ ANATOP_BASE_ADDR;
+struct mxc_ccm_reg *ccm_reg = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+#ifdef CONFIG_FSL_ESDHC
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
+int get_clocks(void)
+{
+#ifdef CONFIG_FSL_ESDHC
+#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+#else
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+#endif
+#endif
+ return 0;
+}
+
+u32 get_ahb_clk(void)
+{
+ return get_root_clk(AHB_CLK_ROOT);
+}
+
+static u32 get_ipg_clk(void)
+{
+ /*
+ * The AHB and IPG are fixed at 2:1 ratio, and synchronized to
+ * each other.
+ */
+ return get_ahb_clk() / 2;
+}
+
+u32 imx_get_uartclk(void)
+{
+ return get_root_clk(UART1_CLK_ROOT);
+}
+
+u32 imx_get_fecclk(void)
+{
+ return get_root_clk(ENET_AXI_CLK_ROOT);
+}
+
+#ifdef CONFIG_MXC_OCOTP
+void enable_ocotp_clk(unsigned char enable)
+{
+ clock_enable(CCGR_OCOTP, enable);
+}
+
+void enable_thermal_clk(void)
+{
+ enable_ocotp_clk(1);
+}
+#endif
+
+void enable_usboh3_clk(unsigned char enable)
+{
+ u32 target;
+
+ if (enable) {
+ /* disable the clock gate first */
+ clock_enable(CCGR_USB_HSIC, 0);
+
+ /* 120Mhz */
+ target = CLK_ROOT_ON |
+ USB_HSIC_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(USB_HSIC_CLK_ROOT, target);
+
+ /* enable the clock gate */
+ clock_enable(CCGR_USB_CTRL, 1);
+ clock_enable(CCGR_USB_HSIC, 1);
+ clock_enable(CCGR_USB_PHY1, 1);
+ clock_enable(CCGR_USB_PHY2, 1);
+ } else {
+ clock_enable(CCGR_USB_CTRL, 0);
+ clock_enable(CCGR_USB_HSIC, 0);
+ clock_enable(CCGR_USB_PHY1, 0);
+ clock_enable(CCGR_USB_PHY2, 0);
+ }
+}
+
+static u32 decode_pll(enum pll_clocks pll, u32 infreq)
+{
+ u32 reg, div_sel;
+ u32 num, denom;
+
+ /*
+ * Alought there are four choices for the bypass src,
+ * we choose OSC_24M which is the default set in ROM.
+ */
+ switch (pll) {
+ case PLL_CORE:
+ reg = readl(&ccm_anatop->pll_arm);
+
+ if (reg & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK)
+ return 0;
+
+ if (reg & CCM_ANALOG_PLL_ARM_BYPASS_MASK)
+ return MXC_HCLK;
+
+ div_sel = (reg & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >>
+ CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT;
+
+ return (infreq * div_sel) / 2;
+
+ case PLL_SYS:
+ reg = readl(&ccm_anatop->pll_480);
+
+ if (reg & CCM_ANALOG_PLL_480_POWERDOWN_MASK)
+ return 0;
+
+ if (reg & CCM_ANALOG_PLL_480_BYPASS_MASK)
+ return MXC_HCLK;
+
+ if (((reg & CCM_ANALOG_PLL_480_DIV_SELECT_MASK) >>
+ CCM_ANALOG_PLL_480_DIV_SELECT_SHIFT) == 0)
+ return 480000000u;
+ else
+ return 528000000u;
+
+ case PLL_ENET:
+ reg = readl(&ccm_anatop->pll_enet);
+
+ if (reg & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK)
+ return 0;
+
+ if (reg & CCM_ANALOG_PLL_ENET_BYPASS_MASK)
+ return MXC_HCLK;
+
+ return 1000000000u;
+
+ case PLL_DDR:
+ reg = readl(&ccm_anatop->pll_ddr);
+
+ if (reg & CCM_ANALOG_PLL_DDR_POWERDOWN_MASK)
+ return 0;
+
+ num = ccm_anatop->pll_ddr_num;
+ denom = ccm_anatop->pll_ddr_denom;
+
+ if (reg & CCM_ANALOG_PLL_DDR_BYPASS_MASK)
+ return MXC_HCLK;
+
+ div_sel = (reg & CCM_ANALOG_PLL_DDR_DIV_SELECT_MASK) >>
+ CCM_ANALOG_PLL_DDR_DIV_SELECT_SHIFT;
+
+ return infreq * (div_sel + num / denom);
+
+ case PLL_USB:
+ return 480000000u;
+
+ default:
+ printf("Unsupported pll clocks %d\n", pll);
+ break;
+ }
+
+ return 0;
+}
+
+static u32 mxc_get_pll_sys_derive(int derive)
+{
+ u32 freq, div, frac;
+ u32 reg;
+
+ div = 1;
+ reg = readl(&ccm_anatop->pll_480);
+ freq = decode_pll(PLL_SYS, MXC_HCLK);
+
+ switch (derive) {
+ case PLL_SYS_MAIN_480M_CLK:
+ if (reg & CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_MASK)
+ return 0;
+ else
+ return freq;
+ case PLL_SYS_MAIN_240M_CLK:
+ if (reg & CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_MASK)
+ return 0;
+ else
+ return freq / 2;
+ case PLL_SYS_MAIN_120M_CLK:
+ if (reg & CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_MASK)
+ return 0;
+ else
+ return freq / 4;
+ case PLL_SYS_PFD0_392M_CLK:
+ reg = readl(&ccm_anatop->pfd_480a);
+ if (reg & CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_MASK)
+ return 0;
+ frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT;
+ break;
+ case PLL_SYS_PFD0_196M_CLK:
+ if (reg & CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_MASK)
+ return 0;
+ reg = readl(&ccm_anatop->pfd_480a);
+ frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT;
+ div = 2;
+ break;
+ case PLL_SYS_PFD1_332M_CLK:
+ reg = readl(&ccm_anatop->pfd_480a);
+ if (reg & CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_MASK)
+ return 0;
+ frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT;
+ break;
+ case PLL_SYS_PFD1_166M_CLK:
+ if (reg & CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_MASK)
+ return 0;
+ reg = readl(&ccm_anatop->pfd_480a);
+ frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT;
+ div = 2;
+ break;
+ case PLL_SYS_PFD2_270M_CLK:
+ reg = readl(&ccm_anatop->pfd_480a);
+ if (reg & CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_MASK)
+ return 0;
+ frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT;
+ break;
+ case PLL_SYS_PFD2_135M_CLK:
+ if (reg & CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_MASK)
+ return 0;
+ reg = readl(&ccm_anatop->pfd_480a);
+ frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT;
+ div = 2;
+ break;
+ case PLL_SYS_PFD3_CLK:
+ reg = readl(&ccm_anatop->pfd_480a);
+ if (reg & CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_MASK)
+ return 0;
+ frac = (reg & CCM_ANALOG_PFD_480A_PFD3_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480A_PFD3_FRAC_SHIFT;
+ break;
+ case PLL_SYS_PFD4_CLK:
+ reg = readl(&ccm_anatop->pfd_480b);
+ if (reg & CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK)
+ return 0;
+ frac = (reg & CCM_ANALOG_PFD_480B_PFD4_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480B_PFD4_FRAC_SHIFT;
+ break;
+ case PLL_SYS_PFD5_CLK:
+ reg = readl(&ccm_anatop->pfd_480b);
+ if (reg & CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_MASK)
+ return 0;
+ frac = (reg & CCM_ANALOG_PFD_480B_PFD5_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480B_PFD5_FRAC_SHIFT;
+ break;
+ case PLL_SYS_PFD6_CLK:
+ reg = readl(&ccm_anatop->pfd_480b);
+ if (reg & CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_MASK)
+ return 0;
+ frac = (reg & CCM_ANALOG_PFD_480B_PFD6_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480B_PFD6_FRAC_SHIFT;
+ break;
+ case PLL_SYS_PFD7_CLK:
+ reg = readl(&ccm_anatop->pfd_480b);
+ if (reg & CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_MASK)
+ return 0;
+ frac = (reg & CCM_ANALOG_PFD_480B_PFD7_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480B_PFD7_FRAC_SHIFT;
+ break;
+ default:
+ printf("Error derived pll_sys clock %d\n", derive);
+ return 0;
+ }
+
+ return ((freq / frac) * 18) / div;
+}
+
+static u32 mxc_get_pll_enet_derive(int derive)
+{
+ u32 freq, reg;
+
+ freq = decode_pll(PLL_ENET, MXC_HCLK);
+ reg = readl(&ccm_anatop->pll_enet);
+
+ switch (derive) {
+ case PLL_ENET_MAIN_500M_CLK:
+ if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK)
+ return freq / 2;
+ break;
+ case PLL_ENET_MAIN_250M_CLK:
+ if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK)
+ return freq / 4;
+ break;
+ case PLL_ENET_MAIN_125M_CLK:
+ if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK)
+ return freq / 8;
+ break;
+ case PLL_ENET_MAIN_100M_CLK:
+ if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK)
+ return freq / 10;
+ break;
+ case PLL_ENET_MAIN_50M_CLK:
+ if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK)
+ return freq / 20;
+ break;
+ case PLL_ENET_MAIN_40M_CLK:
+ if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK)
+ return freq / 25;
+ break;
+ case PLL_ENET_MAIN_25M_CLK:
+ if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK)
+ return freq / 40;
+ break;
+ default:
+ printf("Error derived pll_enet clock %d\n", derive);
+ break;
+ }
+
+ return 0;
+}
+
+static u32 mxc_get_pll_ddr_derive(int derive)
+{
+ u32 freq, reg;
+
+ freq = decode_pll(PLL_DDR, MXC_HCLK);
+ reg = readl(&ccm_anatop->pll_ddr);
+
+ switch (derive) {
+ case PLL_DRAM_MAIN_1066M_CLK:
+ return freq;
+ case PLL_DRAM_MAIN_533M_CLK:
+ if (reg & CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_MASK)
+ return freq / 2;
+ break;
+ default:
+ printf("Error derived pll_ddr clock %d\n", derive);
+ break;
+ }
+
+ return 0;
+}
+
+static u32 mxc_get_pll_derive(enum pll_clocks pll, int derive)
+{
+ switch (pll) {
+ case PLL_SYS:
+ return mxc_get_pll_sys_derive(derive);
+ case PLL_ENET:
+ return mxc_get_pll_enet_derive(derive);
+ case PLL_DDR:
+ return mxc_get_pll_ddr_derive(derive);
+ default:
+ printf("Error pll.\n");
+ return 0;
+ }
+}
+
+static u32 get_root_src_clk(enum clk_root_src root_src)
+{
+ switch (root_src) {
+ case OSC_24M_CLK:
+ return 24000000u;
+ case PLL_ARM_MAIN_800M_CLK:
+ return decode_pll(PLL_CORE, MXC_HCLK);
+
+ case PLL_SYS_MAIN_480M_CLK:
+ case PLL_SYS_MAIN_240M_CLK:
+ case PLL_SYS_MAIN_120M_CLK:
+ case PLL_SYS_PFD0_392M_CLK:
+ case PLL_SYS_PFD0_196M_CLK:
+ case PLL_SYS_PFD1_332M_CLK:
+ case PLL_SYS_PFD1_166M_CLK:
+ case PLL_SYS_PFD2_270M_CLK:
+ case PLL_SYS_PFD2_135M_CLK:
+ case PLL_SYS_PFD3_CLK:
+ case PLL_SYS_PFD4_CLK:
+ case PLL_SYS_PFD5_CLK:
+ case PLL_SYS_PFD6_CLK:
+ case PLL_SYS_PFD7_CLK:
+ return mxc_get_pll_derive(PLL_SYS, root_src);
+
+ case PLL_ENET_MAIN_500M_CLK:
+ case PLL_ENET_MAIN_250M_CLK:
+ case PLL_ENET_MAIN_125M_CLK:
+ case PLL_ENET_MAIN_100M_CLK:
+ case PLL_ENET_MAIN_50M_CLK:
+ case PLL_ENET_MAIN_40M_CLK:
+ case PLL_ENET_MAIN_25M_CLK:
+ return mxc_get_pll_derive(PLL_ENET, root_src);
+
+ case PLL_DRAM_MAIN_1066M_CLK:
+ case PLL_DRAM_MAIN_533M_CLK:
+ return mxc_get_pll_derive(PLL_DDR, root_src);
+
+ case PLL_AUDIO_MAIN_CLK:
+ return decode_pll(PLL_AUDIO, MXC_HCLK);
+ case PLL_VIDEO_MAIN_CLK:
+ return decode_pll(PLL_VIDEO, MXC_HCLK);
+
+ case PLL_USB_MAIN_480M_CLK:
+ return decode_pll(PLL_USB, MXC_HCLK);
+
+ case REF_1M_CLK:
+ return 1000000;
+ case OSC_32K_CLK:
+ return MXC_CLK32;
+
+ case EXT_CLK_1:
+ case EXT_CLK_2:
+ case EXT_CLK_3:
+ case EXT_CLK_4:
+ printf("No EXT CLK supported??\n");
+ break;
+ };
+
+ return 0;
+}
+
+u32 get_root_clk(enum clk_root_index clock_id)
+{
+ enum clk_root_src root_src;
+ u32 post_podf, pre_podf, auto_podf, root_src_clk;
+ int auto_en;
+
+ if (clock_root_enabled(clock_id) <= 0)
+ return 0;
+
+ if (clock_get_prediv(clock_id, &pre_podf) < 0)
+ return 0;
+
+ if (clock_get_postdiv(clock_id, &post_podf) < 0)
+ return 0;
+
+ if (clock_get_autopostdiv(clock_id, &auto_podf, &auto_en) < 0)
+ return 0;
+
+ if (auto_en == 0)
+ auto_podf = 0;
+
+ if (clock_get_src(clock_id, &root_src) < 0)
+ return 0;
+
+ root_src_clk = get_root_src_clk(root_src);
+
+ /*
+ * bypass clk is ignored.
+ */
+
+ return root_src_clk / (post_podf + 1) / (pre_podf + 1) /
+ (auto_podf + 1);
+}
+
+static u32 get_ddrc_clk(void)
+{
+ u32 reg, freq;
+ enum root_post_div post_div;
+
+ reg = readl(&ccm_reg->root[DRAM_CLK_ROOT].target_root);
+ if (reg & CLK_ROOT_MUX_MASK)
+ /* DRAM_ALT_CLK_ROOT */
+ freq = get_root_clk(DRAM_ALT_CLK_ROOT);
+ else
+ /* PLL_DRAM_MAIN_1066M_CLK */
+ freq = mxc_get_pll_derive(PLL_DDR, PLL_DRAM_MAIN_1066M_CLK);
+
+ post_div = reg & DRAM_CLK_ROOT_POST_DIV_MASK;
+
+ return freq / (post_div + 1) / 2;
+}
+
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+ switch (clk) {
+ case MXC_ARM_CLK:
+ return get_root_clk(ARM_A7_CLK_ROOT);
+ case MXC_AXI_CLK:
+ return get_root_clk(MAIN_AXI_CLK_ROOT);
+ case MXC_AHB_CLK:
+ return get_root_clk(AHB_CLK_ROOT);
+ case MXC_IPG_CLK:
+ return get_ipg_clk();
+ case MXC_I2C_CLK:
+ return get_root_clk(I2C1_CLK_ROOT);
+ case MXC_UART_CLK:
+ return get_root_clk(UART1_CLK_ROOT);
+ case MXC_CSPI_CLK:
+ return get_root_clk(ECSPI1_CLK_ROOT);
+ case MXC_DDR_CLK:
+ return get_ddrc_clk();
+ case MXC_ESDHC_CLK:
+ return get_root_clk(USDHC1_CLK_ROOT);
+ case MXC_ESDHC2_CLK:
+ return get_root_clk(USDHC2_CLK_ROOT);
+ case MXC_ESDHC3_CLK:
+ return get_root_clk(USDHC3_CLK_ROOT);
+ default:
+ printf("Unsupported mxc_clock %d\n", clk);
+ break;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_MXC
+/* i2c_num can be 0 - 3 */
+int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
+{
+ u32 target;
+
+ if (i2c_num >= 4)
+ return -EINVAL;
+
+ if (enable) {
+ clock_enable(CCGR_I2C1 + i2c_num, 0);
+
+ /* Set i2c root clock to PLL_SYS_MAIN_120M_CLK */
+
+ target = CLK_ROOT_ON |
+ I2C1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
+ clock_set_target_val(I2C1_CLK_ROOT + i2c_num, target);
+
+ clock_enable(CCGR_I2C1 + i2c_num, 1);
+ } else {
+ clock_enable(CCGR_I2C1 + i2c_num, 0);
+ }
+
+ return 0;
+}
+#endif
+
+static void init_clk_esdhc(void)
+{
+ u32 target;
+
+ /* disable the clock gate first */
+ clock_enable(CCGR_USDHC1, 0);
+ clock_enable(CCGR_USDHC2, 0);
+ clock_enable(CCGR_USDHC3, 0);
+
+ /* 196: 392/2 */
+ target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
+ clock_set_target_val(USDHC1_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
+ clock_set_target_val(USDHC2_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
+ clock_set_target_val(USDHC3_CLK_ROOT, target);
+
+ /* enable the clock gate */
+ clock_enable(CCGR_USDHC1, 1);
+ clock_enable(CCGR_USDHC2, 1);
+ clock_enable(CCGR_USDHC3, 1);
+}
+
+static void init_clk_uart(void)
+{
+ u32 target;
+
+ /* disable the clock gate first */
+ clock_enable(CCGR_UART1, 0);
+ clock_enable(CCGR_UART2, 0);
+ clock_enable(CCGR_UART3, 0);
+ clock_enable(CCGR_UART4, 0);
+ clock_enable(CCGR_UART5, 0);
+ clock_enable(CCGR_UART6, 0);
+ clock_enable(CCGR_UART7, 0);
+
+ /* 24Mhz */
+ target = CLK_ROOT_ON | UART1_CLK_ROOT_FROM_OSC_24M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(UART1_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | UART2_CLK_ROOT_FROM_OSC_24M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(UART2_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | UART3_CLK_ROOT_FROM_OSC_24M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(UART3_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | UART4_CLK_ROOT_FROM_OSC_24M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(UART4_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | UART5_CLK_ROOT_FROM_OSC_24M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(UART5_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | UART6_CLK_ROOT_FROM_OSC_24M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(UART6_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | UART7_CLK_ROOT_FROM_OSC_24M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(UART7_CLK_ROOT, target);
+
+ /* enable the clock gate */
+ clock_enable(CCGR_UART1, 1);
+ clock_enable(CCGR_UART2, 1);
+ clock_enable(CCGR_UART3, 1);
+ clock_enable(CCGR_UART4, 1);
+ clock_enable(CCGR_UART5, 1);
+ clock_enable(CCGR_UART6, 1);
+ clock_enable(CCGR_UART7, 1);
+}
+
+static void init_clk_weim(void)
+{
+ u32 target;
+
+ /* disable the clock gate first */
+ clock_enable(CCGR_WEIM, 0);
+
+ /* 120Mhz */
+ target = CLK_ROOT_ON | EIM_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(EIM_CLK_ROOT, target);
+
+ /* enable the clock gate */
+ clock_enable(CCGR_WEIM, 1);
+}
+
+static void init_clk_ecspi(void)
+{
+ u32 target;
+
+ /* disable the clock gate first */
+ clock_enable(CCGR_ECSPI1, 0);
+ clock_enable(CCGR_ECSPI2, 0);
+ clock_enable(CCGR_ECSPI3, 0);
+ clock_enable(CCGR_ECSPI4, 0);
+
+ /* 60Mhz: 240/4 */
+ target = CLK_ROOT_ON | ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
+ clock_set_target_val(ECSPI1_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
+ clock_set_target_val(ECSPI2_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
+ clock_set_target_val(ECSPI3_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
+ clock_set_target_val(ECSPI4_CLK_ROOT, target);
+
+ /* enable the clock gate */
+ clock_enable(CCGR_ECSPI1, 1);
+ clock_enable(CCGR_ECSPI2, 1);
+ clock_enable(CCGR_ECSPI3, 1);
+ clock_enable(CCGR_ECSPI4, 1);
+}
+
+static void init_clk_wdog(void)
+{
+ u32 target;
+
+ /* disable the clock gate first */
+ clock_enable(CCGR_WDOG1, 0);
+ clock_enable(CCGR_WDOG2, 0);
+ clock_enable(CCGR_WDOG3, 0);
+ clock_enable(CCGR_WDOG4, 0);
+
+ /* 24Mhz */
+ target = CLK_ROOT_ON | WDOG_CLK_ROOT_FROM_OSC_24M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(WDOG_CLK_ROOT, target);
+
+ /* enable the clock gate */
+ clock_enable(CCGR_WDOG1, 1);
+ clock_enable(CCGR_WDOG2, 1);
+ clock_enable(CCGR_WDOG3, 1);
+ clock_enable(CCGR_WDOG4, 1);
+}
+
+#ifdef CONFIG_MXC_EPDC
+static void init_clk_epdc(void)
+{
+ u32 target;
+
+ /* disable the clock gate first */
+ clock_enable(CCGR_EPDC, 0);
+
+ /* 24Mhz */
+ target = CLK_ROOT_ON | EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV12);
+ clock_set_target_val(EPDC_PIXEL_CLK_ROOT, target);
+
+ /* enable the clock gate */
+ clock_enable(CCGR_EPDC, 1);
+}
+#endif
+
+static int enable_pll_enet(void)
+{
+ u32 reg;
+ s32 timeout = 100000;
+
+ reg = readl(&ccm_anatop->pll_enet);
+ /* If pll_enet powered up, no need to set it again */
+ if (reg & ANADIG_PLL_ENET_PWDN_MASK) {
+ reg &= ~ANADIG_PLL_ENET_PWDN_MASK;
+ writel(reg, &ccm_anatop->pll_enet);
+
+ while (timeout--) {
+ if (readl(&ccm_anatop->pll_enet) & ANADIG_PLL_LOCK)
+ break;
+ }
+
+ if (timeout <= 0) {
+ /* If timeout, we set pwdn for pll_enet. */
+ reg |= ANADIG_PLL_ENET_PWDN_MASK;
+ return -ETIME;
+ }
+ }
+
+ /* Clear bypass */
+ writel(CCM_ANALOG_PLL_ENET_BYPASS_MASK, &ccm_anatop->pll_enet_clr);
+
+ writel((CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK
+ | CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK
+ | CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK
+ | CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK
+ | CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK
+ | CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK
+ | CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK),
+ &ccm_anatop->pll_enet_set);
+
+ return 0;
+}
+static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom,
+ u32 post_div)
+{
+ u32 reg = 0;
+ ulong start;
+
+ debug("pll5 div = %d, num = %d, denom = %d\n",
+ pll_div, pll_num, pll_denom);
+
+ /* Power up PLL5 video and disable its output */
+ writel(CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK |
+ CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK |
+ CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK |
+ CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK |
+ CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK |
+ CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK,
+ &ccm_anatop->pll_video_clr);
+
+ /* Set div, num and denom */
+ switch (post_div) {
+ case 1:
+ writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
+ CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x1) |
+ CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
+ &ccm_anatop->pll_video_set);
+ break;
+ case 2:
+ writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
+ CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
+ CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
+ &ccm_anatop->pll_video_set);
+ break;
+ case 3:
+ writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
+ CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
+ CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x1),
+ &ccm_anatop->pll_video_set);
+ break;
+ case 4:
+ writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
+ CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
+ CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x3),
+ &ccm_anatop->pll_video_set);
+ break;
+ case 0:
+ default:
+ writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
+ CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x2) |
+ CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
+ &ccm_anatop->pll_video_set);
+ break;
+ }
+
+ writel(CCM_ANALOG_PLL_VIDEO_NUM_A(pll_num),
+ &ccm_anatop->pll_video_num);
+
+ writel(CCM_ANALOG_PLL_VIDEO_DENOM_B(pll_denom),
+ &ccm_anatop->pll_video_denom);
+
+ /* Wait PLL5 lock */
+ start = get_timer(0); /* Get current timestamp */
+
+ do {
+ reg = readl(&ccm_anatop->pll_video);
+ if (reg & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) {
+ /* Enable PLL out */
+ writel(CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK,
+ &ccm_anatop->pll_video_set);
+ return 0;
+ }
+ } while (get_timer(0) < (start + 10)); /* Wait 10ms */
+
+ printf("Lock PLL5 timeout\n");
+
+ return 1;
+}
+
+int set_clk_qspi(void)
+{
+ u32 target;
+
+ /* disable the clock gate first */
+ clock_enable(CCGR_QSPI, 0);
+
+ /* 49M: 392/2/4 */
+ target = CLK_ROOT_ON | QSPI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
+ clock_set_target_val(QSPI_CLK_ROOT, target);
+
+ /* enable the clock gate */
+ clock_enable(CCGR_QSPI, 1);
+
+ return 0;
+}
+
+int set_clk_nand(void)
+{
+ u32 target;
+
+ /* disable the clock gate first */
+ clock_enable(CCGR_RAWNAND, 0);
+
+ enable_pll_enet();
+ /* 100: 500/5 */
+ target = CLK_ROOT_ON | NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV5);
+ clock_set_target_val(NAND_CLK_ROOT, target);
+
+ /* enable the clock gate */
+ clock_enable(CCGR_RAWNAND, 1);
+
+ return 0;
+}
+
+void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq)
+{
+ u32 hck = MXC_HCLK/1000;
+ u32 min = hck * 27;
+ u32 max = hck * 54;
+ u32 temp, best = 0;
+ u32 i, j, pred = 1, postd = 1;
+ u32 pll_div, pll_num, pll_denom, post_div = 0;
+ u32 target;
+
+ debug("mxs_set_lcdclk, freq = %d\n", freq);
+
+ clock_enable(CCGR_LCDIF, 0);
+
+ temp = (freq * 8 * 8);
+ if (temp < min) {
+ for (i = 1; i <= 4; i++) {
+ if ((temp * (1 << i)) > min) {
+ post_div = i;
+ freq = (freq * (1 << i));
+ break;
+ }
+ }
+
+ if (5 == i) {
+ printf("Fail to set rate to %dkhz", freq);
+ return;
+ }
+ }
+
+ for (i = 1; i <= 8; i++) {
+ for (j = 1; j <= 8; j++) {
+ temp = freq * i * j;
+ if (temp > max || temp < min)
+ continue;
+
+ if (best == 0 || temp < best) {
+ best = temp;
+ pred = i;
+ postd = j;
+ }
+ }
+ }
+
+ if (best == 0) {
+ printf("Fail to set rate to %dkhz", freq);
+ return;
+ }
+
+ debug("best %d, pred = %d, postd = %d\n", best, pred, postd);
+
+ pll_div = best / hck;
+ pll_denom = 1000000;
+ pll_num = (best - hck * pll_div) * pll_denom / hck;
+
+ if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
+ return;
+
+ target = CLK_ROOT_ON | LCDIF_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK |
+ CLK_ROOT_PRE_DIV((pred - 1)) | CLK_ROOT_POST_DIV((postd - 1));
+ clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, target);
+
+ clock_enable(CCGR_LCDIF, 1);
+}
+
+#ifdef CONFIG_FEC_MXC
+int set_clk_enet(enum enet_freq type)
+{
+ u32 target;
+ int ret;
+ u32 enet1_ref, enet2_ref;
+
+ /* disable the clock first */
+ clock_enable(CCGR_ENET1, 0);
+ clock_enable(CCGR_ENET2, 0);
+
+ switch (type) {
+ case ENET_125MHz:
+ enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
+ enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
+ break;
+ case ENET_50MHz:
+ enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
+ enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
+ break;
+ case ENET_25MHz:
+ enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
+ enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ ret = enable_pll_enet();
+ if (ret != 0)
+ return ret;
+
+ /* set enet axi clock 196M: 392/2 */
+ target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
+ clock_set_target_val(ENET_AXI_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | enet1_ref |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(ENET1_REF_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
+ clock_set_target_val(ENET1_TIME_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | enet2_ref |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(ENET2_REF_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | ENET2_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
+ clock_set_target_val(ENET2_TIME_CLK_ROOT, target);
+
+#ifdef CONFIG_FEC_MXC_25M_REF_CLK
+ target = CLK_ROOT_ON |
+ ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(ENET_PHY_REF_CLK_ROOT, target);
+#endif
+ /* enable clock */
+ clock_enable(CCGR_ENET1, 1);
+ clock_enable(CCGR_ENET2, 1);
+
+ return 0;
+}
+#endif
+
+/* Configure PLL/PFD freq */
+void clock_init(void)
+{
+/* Rom has enabled PLL_ARM, PLL_DDR, PLL_SYS, PLL_ENET
+ * In u-boot, we have to:
+ * 1. Configure PFD3- PFD7 for freq we needed in u-boot
+ * 2. Set clock root for peripherals (ip channel) used in u-boot but without set rate
+ * interface. The clocks for these peripherals are enabled after this intialization.
+ * 3. Other peripherals with set clock rate interface does not be set in this function.
+ */
+ u32 reg;
+
+ /*
+ * Configure PFD4 to 392M
+ * 480M * 18 / 0x16 = 392M
+ */
+ reg = readl(&ccm_anatop->pfd_480b);
+
+ reg &= ~(ANATOP_PFD480B_PFD4_FRAC_MASK |
+ CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK);
+ reg |= ANATOP_PFD480B_PFD4_FRAC_392M_VAL;
+
+ writel(reg, &ccm_anatop->pfd_480b);
+
+ init_clk_esdhc();
+ init_clk_uart();
+ init_clk_weim();
+ init_clk_ecspi();
+ init_clk_wdog();
+#ifdef CONFIG_MXC_EPDC
+ init_clk_epdc();
+#endif
+
+ enable_usboh3_clk(1);
+
+ clock_enable(CCGR_SNVS, 1);
+
+#ifdef CONFIG_NAND_MXS
+ clock_enable(CCGR_RAWNAND, 1);
+#endif
+
+ if (IS_ENABLED(CONFIG_IMX_RDC)) {
+ clock_enable(CCGR_RDC, 1);
+ clock_enable(CCGR_SEMA1, 1);
+ clock_enable(CCGR_SEMA2, 1);
+ }
+}
+
+#ifdef CONFIG_SECURE_BOOT
+void hab_caam_clock_enable(unsigned char enable)
+{
+ if (enable)
+ clock_enable(CCGR_CAAM, 1);
+ else
+ clock_enable(CCGR_CAAM, 0);
+}
+#endif
+
+#ifdef CONFIG_MXC_EPDC
+void epdc_clock_enable(void)
+{
+ clock_enable(CCGR_EPDC, 1);
+}
+void epdc_clock_disable(void)
+{
+ clock_enable(CCGR_EPDC, 0);
+}
+#endif
+
+/*
+ * Dump some core clockes.
+ */
+int do_mx7_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ u32 freq;
+ freq = decode_pll(PLL_CORE, MXC_HCLK);
+ printf("PLL_CORE %8d MHz\n", freq / 1000000);
+ freq = decode_pll(PLL_SYS, MXC_HCLK);
+ printf("PLL_SYS %8d MHz\n", freq / 1000000);
+ freq = decode_pll(PLL_ENET, MXC_HCLK);
+ printf("PLL_NET %8d MHz\n", freq / 1000000);
+
+ printf("\n");
+
+ printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
+ printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
+#ifdef CONFIG_MXC_SPI
+ printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
+#endif
+ printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
+ printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
+ printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
+ printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
+ printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
+ printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ clocks, CONFIG_SYS_MAXARGS, 1, do_mx7_showclocks,
+ "display clocks",
+ ""
+);
--- /dev/null
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Author:
+ * Peng Fan <Peng.Fan@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+
+struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+static struct clk_root_map root_array[] = {
+ {ARM_A7_CLK_ROOT, CCM_CORE_CHANNEL,
+ {OSC_24M_CLK, PLL_ARM_MAIN_800M_CLK, PLL_ENET_MAIN_500M_CLK,
+ PLL_DRAM_MAIN_1066M_CLK, PLL_SYS_MAIN_480M_CLK,
+ PLL_SYS_PFD0_392M_CLK, PLL_AUDIO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {ARM_M4_CLK_ROOT, CCM_BUS_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_250M_CLK,
+ PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {ARM_M0_CLK_ROOT, CCM_BUS_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_125M_CLK,
+ PLL_SYS_PFD2_135M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {MAIN_AXI_CLK_ROOT, CCM_BUS_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_ENET_MAIN_250M_CLK, PLL_SYS_PFD5_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD7_CLK}
+ },
+ {DISP_AXI_CLK_ROOT, CCM_BUS_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_ENET_MAIN_250M_CLK, PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK,
+ PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {ENET_AXI_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_ENET_MAIN_250M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK}
+ },
+ {NAND_USDHC_BUS_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_SYS_MAIN_240M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_PFD6_CLK,
+ PLL_ENET_MAIN_250M_CLK, PLL_AUDIO_MAIN_CLK}
+ },
+ {AHB_CLK_ROOT, CCM_AHB_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_SYS_PFD0_392M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK,
+ PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {DRAM_PHYM_CLK_ROOT, CCM_DRAM_PHYM_CHANNEL,
+ {PLL_DRAM_MAIN_1066M_CLK, DRAM_PHYM_ALT_CLK_ROOT}
+ },
+ {DRAM_CLK_ROOT, CCM_DRAM_CHANNEL,
+ {PLL_DRAM_MAIN_1066M_CLK, DRAM_ALT_CLK_ROOT}
+ },
+ {DRAM_PHYM_ALT_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_SYS_MAIN_480M_CLK,
+ PLL_ENET_MAIN_500M_CLK, PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD7_CLK,
+ PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {DRAM_ALT_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_SYS_MAIN_480M_CLK,
+ PLL_ENET_MAIN_500M_CLK, PLL_ENET_MAIN_250M_CLK,
+ PLL_SYS_PFD0_392M_CLK, PLL_AUDIO_MAIN_CLK, PLL_SYS_PFD2_270M_CLK}
+ },
+ {USB_HSIC_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_USB_MAIN_480M_CLK,
+ PLL_SYS_PFD3_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD5_CLK,
+ PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
+ },
+ {PCIE_CTRL_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_250M_CLK, PLL_SYS_MAIN_240M_CLK,
+ PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_SYS_PFD6_CLK}
+ },
+ {PCIE_PHY_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_ENET_MAIN_500M_CLK,
+ EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
+ EXT_CLK_4, PLL_SYS_PFD0_392M_CLK}
+ },
+ {EPDC_PIXEL_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD5_CLK, PLL_SYS_PFD6_CLK,
+ PLL_SYS_PFD7_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {LCDIF_PIXEL_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD5_CLK, PLL_DRAM_MAIN_533M_CLK,
+ EXT_CLK_3, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {MIPI_DSI_EXTSER_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD5_CLK, PLL_SYS_PFD3_CLK,
+ PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD0_196M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_AUDIO_MAIN_CLK}
+ },
+ {MIPI_CSI_WARP_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD3_CLK,
+ PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD0_196M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_AUDIO_MAIN_CLK}
+ },
+ {MIPI_DPHY_REF_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_SYS_PFD5_CLK, REF_1M_CLK, EXT_CLK_2,
+ PLL_VIDEO_MAIN_CLK, EXT_CLK_3}
+ },
+ {SAI1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK,
+ PLL_ENET_MAIN_125M_CLK, EXT_CLK_2}
+ },
+ {SAI2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK,
+ PLL_ENET_MAIN_125M_CLK, EXT_CLK_2}
+ },
+ {SAI3_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK,
+ PLL_ENET_MAIN_125M_CLK, EXT_CLK_3}
+ },
+ {SPDIF_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK,
+ PLL_ENET_MAIN_125M_CLK, EXT_CLK_3}
+ },
+ {ENET1_REF_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_ENET_MAIN_50M_CLK,
+ PLL_ENET_MAIN_25M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, EXT_CLK_4}
+ },
+ {ENET1_TIME_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_AUDIO_MAIN_CLK,
+ EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
+ EXT_CLK_4, PLL_VIDEO_MAIN_CLK}
+ },
+ {ENET2_REF_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_ENET_MAIN_50M_CLK,
+ PLL_ENET_MAIN_25M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, EXT_CLK_4}
+ },
+ {ENET2_TIME_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_AUDIO_MAIN_CLK,
+ EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
+ EXT_CLK_4, PLL_VIDEO_MAIN_CLK}
+ },
+ {ENET_PHY_REF_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_25M_CLK, PLL_ENET_MAIN_50M_CLK,
+ PLL_ENET_MAIN_125M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD3_CLK}
+ },
+ {EIM_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_SYS_PFD3_CLK,
+ PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {NAND_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_SYS_PFD0_392M_CLK, PLL_SYS_PFD3_CLK, PLL_ENET_MAIN_500M_CLK,
+ PLL_ENET_MAIN_250M_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {QSPI_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD4_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD3_CLK, PLL_SYS_PFD2_270M_CLK,
+ PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
+ },
+ {USDHC1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD0_392M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK,
+ PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
+ },
+ {USDHC2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD0_392M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK,
+ PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
+ },
+ {USDHC3_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD0_392M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK,
+ PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
+ },
+ {CAN1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_SYS_MAIN_480M_CLK, PLL_ENET_MAIN_40M_CLK, PLL_USB_MAIN_480M_CLK,
+ EXT_CLK_1, EXT_CLK_4}
+ },
+ {CAN2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_SYS_MAIN_480M_CLK, PLL_ENET_MAIN_40M_CLK, PLL_USB_MAIN_480M_CLK,
+ EXT_CLK_1, EXT_CLK_3}
+ },
+ {I2C1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK,
+ PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK}
+ },
+ {I2C2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK,
+ PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK}
+ },
+ {I2C3_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK,
+ PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK}
+ },
+ {I2C4_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK,
+ PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK}
+ },
+ {UART1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
+ EXT_CLK_4, PLL_USB_MAIN_480M_CLK}
+ },
+ {UART2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
+ EXT_CLK_3, PLL_USB_MAIN_480M_CLK}
+ },
+ {UART3_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
+ EXT_CLK_4, PLL_USB_MAIN_480M_CLK}
+ },
+ {UART4_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
+ EXT_CLK_3, PLL_USB_MAIN_480M_CLK}
+ },
+ {UART5_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
+ EXT_CLK_4, PLL_USB_MAIN_480M_CLK}
+ },
+ {UART6_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
+ EXT_CLK_3, PLL_USB_MAIN_480M_CLK}
+ },
+ {UART7_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
+ EXT_CLK_4, PLL_USB_MAIN_480M_CLK}
+ },
+ {ECSPI1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK,
+ PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {ECSPI2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK,
+ PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {ECSPI3_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK,
+ PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {ECSPI4_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK,
+ PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {PWM1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_1,
+ REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {PWM2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_1,
+ REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {PWM3_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_2,
+ REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {PWM4_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_2,
+ REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {FLEXTIMER1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_3,
+ REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {FLEXTIMER2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_3,
+ REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {SIM1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_USB_MAIN_480M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_ENET_MAIN_125M_CLK, PLL_SYS_PFD7_CLK}
+ },
+ {SIM2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_USB_MAIN_480M_CLK, PLL_VIDEO_MAIN_CLK,
+ PLL_ENET_MAIN_125M_CLK, PLL_SYS_PFD7_CLK}
+ },
+ {GPT1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK,
+ PLL_AUDIO_MAIN_CLK, EXT_CLK_1}
+ },
+ {GPT2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK,
+ PLL_AUDIO_MAIN_CLK, EXT_CLK_2}
+ },
+ {GPT3_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK,
+ PLL_AUDIO_MAIN_CLK, EXT_CLK_3}
+ },
+ {GPT4_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK,
+ PLL_AUDIO_MAIN_CLK, EXT_CLK_4}
+ },
+ {TRACE_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK,
+ EXT_CLK_1, EXT_CLK_3}
+ },
+ {WDOG_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK,
+ REF_1M_CLK, PLL_SYS_PFD1_166M_CLK}
+ },
+ {CSI_MCLK_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {AUDIO_MCLK_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {WRCLK_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_40M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_USB_MAIN_480M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_SYS_PFD2_270M_CLK,
+ PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD7_CLK}
+ },
+ {IPP_DO_CLKO1, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_MAIN_240M_CLK,
+ PLL_SYS_PFD0_196M_CLK, PLL_SYS_PFD3_CLK, PLL_ENET_MAIN_500M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, REF_1M_CLK}
+ },
+ {IPP_DO_CLKO2, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_SYS_PFD0_392M_CLK,
+ PLL_SYS_PFD1_166M_CLK, PLL_SYS_PFD4_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, OSC_32K_CLK}
+ },
+};
+
+/* select which entry of root_array */
+static int select(enum clk_root_index clock_id)
+{
+ int i, size;
+ struct clk_root_map *p = root_array;
+
+ size = ARRAY_SIZE(root_array);
+
+ for (i = 0; i < size; i++, p++) {
+ if (clock_id == p->entry)
+ return i;
+ }
+
+ return -EINVAL;
+}
+
+static int src_supported(int entry, enum clk_root_src clock_src)
+{
+ int i, size;
+ struct clk_root_map *p = &root_array[entry];
+
+ if ((p->type == CCM_DRAM_PHYM_CHANNEL) || (p->type == CCM_DRAM_CHANNEL))
+ size = 2;
+ else
+ size = 8;
+
+ for (i = 0; i < size; i++) {
+ if (p->src_mux[i] == clock_src)
+ return i;
+ }
+
+ return -EINVAL;
+}
+
+/* Set src for clock root slice. */
+int clock_set_src(enum clk_root_index clock_id, enum clk_root_src clock_src)
+{
+ int root_entry, src_entry;
+ u32 reg;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ root_entry = select(clock_id);
+ if (root_entry < 0)
+ return -EINVAL;
+
+ src_entry = src_supported(root_entry, clock_src);
+ if (src_entry < 0)
+ return -EINVAL;
+
+ reg = __raw_readl(&imx_ccm->root[clock_id].target_root);
+ reg &= ~CLK_ROOT_MUX_MASK;
+ reg |= src_entry << CLK_ROOT_MUX_SHIFT;
+ __raw_writel(reg, &imx_ccm->root[clock_id].target_root);
+
+ return 0;
+}
+
+/* Get src of a clock root slice. */
+int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src)
+{
+ u32 val;
+ int root_entry;
+ struct clk_root_map *p;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ val = __raw_readl(&imx_ccm->root[clock_id].target_root);
+ val &= CLK_ROOT_MUX_MASK;
+ val >>= CLK_ROOT_MUX_SHIFT;
+
+ root_entry = select(clock_id);
+ if (root_entry < 0)
+ return -EINVAL;
+
+ p = &root_array[root_entry];
+ *p_clock_src = p->src_mux[val];
+
+ return 0;
+}
+
+int clock_set_prediv(enum clk_root_index clock_id, enum root_pre_div pre_div)
+{
+ int root_entry;
+ struct clk_root_map *p;
+ u32 reg;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ root_entry = select(clock_id);
+ if (root_entry < 0)
+ return -EINVAL;
+
+ p = &root_array[root_entry];
+
+ if ((p->type == CCM_CORE_CHANNEL) ||
+ (p->type == CCM_DRAM_PHYM_CHANNEL) ||
+ (p->type == CCM_DRAM_CHANNEL)) {
+ if (pre_div != CLK_ROOT_PRE_DIV1) {
+ printf("Error pre div!\n");
+ return -EINVAL;
+ }
+ }
+
+ reg = __raw_readl(&imx_ccm->root[clock_id].target_root);
+ reg &= ~CLK_ROOT_PRE_DIV_MASK;
+ reg |= pre_div << CLK_ROOT_PRE_DIV_SHIFT;
+ __raw_writel(reg, &imx_ccm->root[clock_id].target_root);
+
+ return 0;
+}
+
+int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div)
+{
+ u32 val;
+ int root_entry;
+ struct clk_root_map *p;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ root_entry = select(clock_id);
+ if (root_entry < 0)
+ return -EINVAL;
+
+ p = &root_array[root_entry];
+
+ if ((p->type == CCM_CORE_CHANNEL) ||
+ (p->type == CCM_DRAM_PHYM_CHANNEL) ||
+ (p->type == CCM_DRAM_CHANNEL)) {
+ *pre_div = 0;
+ return 0;
+ }
+
+ val = __raw_readl(&imx_ccm->root[clock_id].target_root);
+ val &= CLK_ROOT_PRE_DIV_MASK;
+ val >>= CLK_ROOT_PRE_DIV_SHIFT;
+
+ *pre_div = val;
+
+ return 0;
+}
+
+int clock_set_postdiv(enum clk_root_index clock_id, enum root_post_div div)
+{
+ u32 reg;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ if (clock_id == DRAM_PHYM_CLK_ROOT) {
+ if (div != CLK_ROOT_POST_DIV1) {
+ printf("Error post div!\n");
+ return -EINVAL;
+ }
+ }
+
+ /* Only 3 bit post div. */
+ if ((clock_id == DRAM_CLK_ROOT) && (div > CLK_ROOT_POST_DIV7)) {
+ printf("Error post div!\n");
+ return -EINVAL;
+ }
+
+ reg = __raw_readl(&imx_ccm->root[clock_id].target_root);
+ reg &= ~CLK_ROOT_POST_DIV_MASK;
+ reg |= div << CLK_ROOT_POST_DIV_SHIFT;
+ __raw_writel(reg, &imx_ccm->root[clock_id].target_root);
+
+ return 0;
+}
+
+int clock_get_postdiv(enum clk_root_index clock_id, enum root_post_div *div)
+{
+ u32 val;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ if (clock_id == DRAM_PHYM_CLK_ROOT) {
+ *div = 0;
+ return 0;
+ }
+
+ val = __raw_readl(&imx_ccm->root[clock_id].target_root);
+ if (clock_id == DRAM_CLK_ROOT)
+ val &= DRAM_CLK_ROOT_POST_DIV_MASK;
+ else
+ val &= CLK_ROOT_POST_DIV_MASK;
+ val >>= CLK_ROOT_POST_DIV_SHIFT;
+
+ *div = val;
+
+ return 0;
+}
+
+int clock_set_autopostdiv(enum clk_root_index clock_id, enum root_auto_div div,
+ int auto_en)
+{
+ u32 val;
+ int root_entry;
+ struct clk_root_map *p;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ root_entry = select(clock_id);
+ if (root_entry < 0)
+ return -EINVAL;
+
+ p = &root_array[root_entry];
+
+ if ((p->type != CCM_BUS_CHANNEL) && (p->type != CCM_AHB_CHANNEL)) {
+ printf("Auto postdiv not supported.!\n");
+ return -EINVAL;
+ }
+
+ /*
+ * Each time only one filed can be changed, no use target_root_set.
+ */
+ val = __raw_readl(&imx_ccm->root[clock_id].target_root);
+ val &= ~CLK_ROOT_AUTO_DIV_MASK;
+ val |= (div << CLK_ROOT_AUTO_DIV_SHIFT);
+
+ if (auto_en)
+ val |= CLK_ROOT_AUTO_EN;
+ else
+ val &= ~CLK_ROOT_AUTO_EN;
+
+ __raw_writel(val, &imx_ccm->root[clock_id].target_root);
+
+ return 0;
+}
+
+int clock_get_autopostdiv(enum clk_root_index clock_id, enum root_auto_div *div,
+ int *auto_en)
+{
+ u32 val;
+ int root_entry;
+ struct clk_root_map *p;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ root_entry = select(clock_id);
+ if (root_entry < 0)
+ return -EINVAL;
+
+ p = &root_array[root_entry];
+
+ /*
+ * Only bus/ahb channel supports auto div.
+ * If unsupported, just set auto_en and div with 0.
+ */
+ if ((p->type != CCM_BUS_CHANNEL) && (p->type != CCM_AHB_CHANNEL)) {
+ *auto_en = 0;
+ *div = 0;
+ return 0;
+ }
+
+ val = __raw_readl(&imx_ccm->root[clock_id].target_root);
+ if ((val & CLK_ROOT_AUTO_EN_MASK) == 0)
+ *auto_en = 0;
+ else
+ *auto_en = 1;
+
+ val &= CLK_ROOT_AUTO_DIV_MASK;
+ val >>= CLK_ROOT_AUTO_DIV_SHIFT;
+
+ *div = val;
+
+ return 0;
+}
+
+int clock_get_target_val(enum clk_root_index clock_id, u32 *val)
+{
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ *val = __raw_readl(&imx_ccm->root[clock_id].target_root);
+
+ return 0;
+}
+
+int clock_set_target_val(enum clk_root_index clock_id, u32 val)
+{
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ __raw_writel(val, &imx_ccm->root[clock_id].target_root);
+
+ return 0;
+}
+
+/* Auto_div and auto_en is ignored, they are rarely used. */
+int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,
+ enum root_post_div post_div, enum clk_root_src clock_src)
+{
+ u32 val;
+ int root_entry, src_entry;
+ struct clk_root_map *p;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ root_entry = select(clock_id);
+ if (root_entry < 0)
+ return -EINVAL;
+
+ p = &root_array[root_entry];
+
+ if ((p->type == CCM_CORE_CHANNEL) ||
+ (p->type == CCM_DRAM_PHYM_CHANNEL) ||
+ (p->type == CCM_DRAM_CHANNEL)) {
+ if (pre_div != CLK_ROOT_PRE_DIV1) {
+ printf("Error pre div!\n");
+ return -EINVAL;
+ }
+ }
+
+ /* Only 3 bit post div. */
+ if (p->type == CCM_DRAM_CHANNEL) {
+ if (post_div > CLK_ROOT_POST_DIV7) {
+ printf("Error post div!\n");
+ return -EINVAL;
+ }
+ }
+
+ if (p->type == CCM_DRAM_PHYM_CHANNEL) {
+ if (post_div != CLK_ROOT_POST_DIV1) {
+ printf("Error post div!\n");
+ return -EINVAL;
+ }
+ }
+
+ src_entry = src_supported(root_entry, clock_src);
+ if (src_entry < 0)
+ return -EINVAL;
+
+ val = CLK_ROOT_ON | pre_div << CLK_ROOT_PRE_DIV_SHIFT |
+ post_div << CLK_ROOT_POST_DIV_SHIFT |
+ src_entry << CLK_ROOT_MUX_SHIFT;
+
+ __raw_writel(val, &imx_ccm->root[clock_id].target_root);
+
+ return 0;
+}
+
+int clock_root_enabled(enum clk_root_index clock_id)
+{
+ u32 val;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ /*
+ * No enable bit for DRAM controller and PHY. Just return enabled.
+ */
+ if ((clock_id == DRAM_PHYM_CLK_ROOT) || (clock_id == DRAM_CLK_ROOT))
+ return 1;
+
+ val = __raw_readl(&imx_ccm->root[clock_id].target_root);
+
+ return (val & CLK_ROOT_ENABLE_MASK) ? 1 : 0;
+}
+
+/* CCGR gate operation */
+int clock_enable(enum clk_ccgr_index index, bool enable)
+{
+ if (index >= CCGR_MAX)
+ return -EINVAL;
+
+ if (enable)
+ __raw_writel(CCM_CLK_ON_MSK,
+ &imx_ccm->ccgr_array[index].ccgr_set);
+ else
+ __raw_writel(CCM_CLK_ON_MSK,
+ &imx_ccm->ccgr_array[index].ccgr_clr);
+
+ return 0;
+}
--- /dev/null
+#include <asm/io.h>
+#include <asm/psci.h>
+#include <asm/secure.h>
+#include <asm/arch/imx-regs.h>
+#include <common.h>
+
+
+#define GPC_CPU_PGC_SW_PDN_REQ 0xfc
+#define GPC_CPU_PGC_SW_PUP_REQ 0xf0
+#define GPC_PGC_C1 0x840
+
+#define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7 0x2
+
+/* below is for i.MX7D */
+#define SRC_GPR1_MX7D 0x074
+#define SRC_A7RCR0 0x004
+#define SRC_A7RCR1 0x008
+
+#define BP_SRC_A7RCR0_A7_CORE_RESET0 0
+#define BP_SRC_A7RCR1_A7_CORE1_ENABLE 1
+
+static inline void imx_gpcv2_set_m_core_pgc(bool enable, u32 offset)
+{
+ writel(enable, GPC_IPS_BASE_ADDR + offset);
+}
+
+__secure void imx_gpcv2_set_core1_power(bool pdn)
+{
+ u32 reg = pdn ? GPC_CPU_PGC_SW_PUP_REQ : GPC_CPU_PGC_SW_PDN_REQ;
+ u32 val;
+
+ imx_gpcv2_set_m_core_pgc(true, GPC_PGC_C1);
+
+ val = readl(GPC_IPS_BASE_ADDR + reg);
+ val |= BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7;
+ writel(val, GPC_IPS_BASE_ADDR + reg);
+
+ while ((readl(GPC_IPS_BASE_ADDR + reg) &
+ BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7) != 0)
+ ;
+
+ imx_gpcv2_set_m_core_pgc(false, GPC_PGC_C1);
+}
+
+__secure void imx_enable_cpu_ca7(int cpu, bool enable)
+{
+ u32 mask, val;
+
+ mask = 1 << (BP_SRC_A7RCR1_A7_CORE1_ENABLE + cpu - 1);
+ val = readl(SRC_BASE_ADDR + SRC_A7RCR1);
+ val = enable ? val | mask : val & ~mask;
+ writel(val, SRC_BASE_ADDR + SRC_A7RCR1);
+}
+
+__secure int imx_cpu_on(int fn, int cpu, int pc)
+{
+ writel(pc, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D);
+ imx_gpcv2_set_core1_power(true);
+ imx_enable_cpu_ca7(cpu, true);
+ return 0;
+}
+
+__secure int imx_cpu_off(int cpu)
+{
+ imx_enable_cpu_ca7(cpu, false);
+ imx_gpcv2_set_core1_power(false);
+ writel(0, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D + 4);
+ return 0;
+}
--- /dev/null
+#include <config.h>
+#include <linux/linkage.h>
+
+#include <asm/armv7.h>
+#include <asm/arch-armv7/generictimer.h>
+#include <asm/psci.h>
+
+ .pushsection ._secure.text, "ax"
+
+ .arch_extension sec
+
+.globl psci_cpu_on
+psci_cpu_on:
+ push {r4, r5, lr}
+
+ mov r4, r0
+ mov r5, r1
+ mov r0, r1
+ mov r1, r2
+ bl psci_save_target_pc
+
+ mov r0, r4
+ mov r1, r5
+ ldr r2, =psci_cpu_entry
+ bl imx_cpu_on
+
+ pop {r4, r5, pc}
+
+.globl psci_cpu_off
+psci_cpu_off:
+
+ bl psci_cpu_off_common
+ bl psci_get_cpu_id
+ bl imx_cpu_off
+
+1: wfi
+ b 1b
+
+ .popsection
--- /dev/null
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/dma.h>
+#include <asm/mach-imx/hab.h>
+#include <asm/mach-imx/rdc-sema.h>
+#include <asm/arch/imx-rdc.h>
+#include <asm/arch/crm_regs.h>
+#include <dm.h>
+#include <imx_thermal.h>
+
+#if defined(CONFIG_IMX_THERMAL)
+static const struct imx_thermal_plat imx7_thermal_plat = {
+ .regs = (void *)ANATOP_BASE_ADDR,
+ .fuse_bank = 3,
+ .fuse_word = 3,
+};
+
+U_BOOT_DEVICE(imx7_thermal) = {
+ .name = "imx_thermal",
+ .platdata = &imx7_thermal_plat,
+};
+#endif
+
+#ifdef CONFIG_IMX_RDC
+/*
+ * In current design, if any peripheral was assigned to both A7 and M4,
+ * it will receive ipg_stop or ipg_wait when any of the 2 platforms enter
+ * low power mode. So M4 sleep will cause some peripherals fail to work
+ * at A7 core side. At default, all resources are in domain 0 - 3.
+ *
+ * There are 26 peripherals impacted by this IC issue:
+ * SIM2(sim2/emvsim2)
+ * SIM1(sim1/emvsim1)
+ * UART1/UART2/UART3/UART4/UART5/UART6/UART7
+ * SAI1/SAI2/SAI3
+ * WDOG1/WDOG2/WDOG3/WDOG4
+ * GPT1/GPT2/GPT3/GPT4
+ * PWM1/PWM2/PWM3/PWM4
+ * ENET1/ENET2
+ * Software Workaround:
+ * Here we setup some resources to domain 0 where M4 codes will move
+ * the M4 out of this domain. Then M4 is not able to access them any longer.
+ * This is a workaround for ic issue. So the peripherals are not shared
+ * by them. This way requires the uboot implemented the RDC driver and
+ * set the 26 IPs above to domain 0 only. M4 code will assign resource
+ * to its own domain, if it want to use the resource.
+ */
+static rdc_peri_cfg_t const resources[] = {
+ (RDC_PER_SIM1 | RDC_DOMAIN(0)),
+ (RDC_PER_SIM2 | RDC_DOMAIN(0)),
+ (RDC_PER_UART1 | RDC_DOMAIN(0)),
+ (RDC_PER_UART2 | RDC_DOMAIN(0)),
+ (RDC_PER_UART3 | RDC_DOMAIN(0)),
+ (RDC_PER_UART4 | RDC_DOMAIN(0)),
+ (RDC_PER_UART5 | RDC_DOMAIN(0)),
+ (RDC_PER_UART6 | RDC_DOMAIN(0)),
+ (RDC_PER_UART7 | RDC_DOMAIN(0)),
+ (RDC_PER_SAI1 | RDC_DOMAIN(0)),
+ (RDC_PER_SAI2 | RDC_DOMAIN(0)),
+ (RDC_PER_SAI3 | RDC_DOMAIN(0)),
+ (RDC_PER_WDOG1 | RDC_DOMAIN(0)),
+ (RDC_PER_WDOG2 | RDC_DOMAIN(0)),
+ (RDC_PER_WDOG3 | RDC_DOMAIN(0)),
+ (RDC_PER_WDOG4 | RDC_DOMAIN(0)),
+ (RDC_PER_GPT1 | RDC_DOMAIN(0)),
+ (RDC_PER_GPT2 | RDC_DOMAIN(0)),
+ (RDC_PER_GPT3 | RDC_DOMAIN(0)),
+ (RDC_PER_GPT4 | RDC_DOMAIN(0)),
+ (RDC_PER_PWM1 | RDC_DOMAIN(0)),
+ (RDC_PER_PWM2 | RDC_DOMAIN(0)),
+ (RDC_PER_PWM3 | RDC_DOMAIN(0)),
+ (RDC_PER_PWM4 | RDC_DOMAIN(0)),
+ (RDC_PER_ENET1 | RDC_DOMAIN(0)),
+ (RDC_PER_ENET2 | RDC_DOMAIN(0)),
+};
+
+static void isolate_resource(void)
+{
+ imx_rdc_setup_peripherals(resources, ARRAY_SIZE(resources));
+}
+#endif
+
+#if defined(CONFIG_SECURE_BOOT)
+struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
+ .bank = 1,
+ .word = 3,
+};
+#endif
+
+/*
+ * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
+ * defines a 2-bit SPEED_GRADING
+ */
+#define OCOTP_TESTER3_SPEED_SHIFT 8
+#define OCOTP_TESTER3_SPEED_800MHZ 0
+#define OCOTP_TESTER3_SPEED_500MHZ 1
+#define OCOTP_TESTER3_SPEED_1GHZ 2
+#define OCOTP_TESTER3_SPEED_1P2GHZ 3
+
+u32 get_cpu_speed_grade_hz(void)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[1];
+ struct fuse_bank1_regs *fuse =
+ (struct fuse_bank1_regs *)bank->fuse_regs;
+ uint32_t val;
+
+ val = readl(&fuse->tester3);
+ val >>= OCOTP_TESTER3_SPEED_SHIFT;
+ val &= 0x3;
+
+ switch(val) {
+ case OCOTP_TESTER3_SPEED_800MHZ:
+ return 800000000;
+ case OCOTP_TESTER3_SPEED_500MHZ:
+ return 500000000;
+ case OCOTP_TESTER3_SPEED_1GHZ:
+ return 1000000000;
+ case OCOTP_TESTER3_SPEED_1P2GHZ:
+ return 1200000000;
+ }
+ return 0;
+}
+
+/*
+ * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
+ * defines a 2-bit SPEED_GRADING
+ */
+#define OCOTP_TESTER3_TEMP_SHIFT 6
+
+u32 get_cpu_temp_grade(int *minc, int *maxc)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[1];
+ struct fuse_bank1_regs *fuse =
+ (struct fuse_bank1_regs *)bank->fuse_regs;
+ uint32_t val;
+
+ val = readl(&fuse->tester3);
+ val >>= OCOTP_TESTER3_TEMP_SHIFT;
+ val &= 0x3;
+
+ if (minc && maxc) {
+ if (val == TEMP_AUTOMOTIVE) {
+ *minc = -40;
+ *maxc = 125;
+ } else if (val == TEMP_INDUSTRIAL) {
+ *minc = -40;
+ *maxc = 105;
+ } else if (val == TEMP_EXTCOMMERCIAL) {
+ *minc = -20;
+ *maxc = 105;
+ } else {
+ *minc = 0;
+ *maxc = 95;
+ }
+ }
+ return val;
+}
+
+static bool is_mx7d(void)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[1];
+ struct fuse_bank1_regs *fuse =
+ (struct fuse_bank1_regs *)bank->fuse_regs;
+ int val;
+
+ val = readl(&fuse->tester4);
+ if (val & 1)
+ return false;
+ else
+ return true;
+}
+
+u32 get_cpu_rev(void)
+{
+ struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
+ ANATOP_BASE_ADDR;
+ u32 reg = readl(&ccm_anatop->digprog);
+ u32 type = (reg >> 16) & 0xff;
+
+ if (!is_mx7d())
+ type = MXC_CPU_MX7S;
+
+ reg &= 0xff;
+ return (type << 12) | reg;
+}
+
+#ifdef CONFIG_REVISION_TAG
+u32 __weak get_board_rev(void)
+{
+ return get_cpu_rev();
+}
+#endif
+
+/* enable all periherial can be accessed in nosec mode */
+static void init_csu(void)
+{
+ int i = 0;
+ for (i = 0; i < CSU_NUM_REGS; i++)
+ writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4);
+}
+
+static void imx_enet_mdio_fixup(void)
+{
+ struct iomuxc_gpr_base_regs *gpr_regs =
+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+ /*
+ * The management data input/output (MDIO) requires open-drain,
+ * i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
+ * this feature. So to TO1.1, need to enable open drain by setting
+ * bits GPR0[8:7].
+ */
+
+ if (soc_rev() >= CHIP_REV_1_1) {
+ setbits_le32(&gpr_regs->gpr[0],
+ IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK);
+ }
+}
+
+int arch_cpu_init(void)
+{
+ init_aips();
+
+ init_csu();
+ /* Disable PDE bit of WMCR register */
+ imx_set_wdog_powerdown(false);
+
+ imx_enet_mdio_fixup();
+
+#ifdef CONFIG_APBH_DMA
+ /* Start APBH DMA */
+ mxs_dma_init();
+#endif
+
+ if (IS_ENABLED(CONFIG_IMX_RDC))
+ isolate_resource();
+
+ return 0;
+}
+
+#ifdef CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ if (is_mx7d())
+ setenv("soc", "imx7d");
+ else
+ setenv("soc", "imx7s");
+#endif
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[0];
+ struct fuse_bank0_regs *fuse =
+ (struct fuse_bank0_regs *)bank->fuse_regs;
+
+ serialnr->low = fuse->tester0;
+ serialnr->high = fuse->tester1;
+}
+#endif
+
+#if defined(CONFIG_FEC_MXC)
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[9];
+ struct fuse_bank9_regs *fuse =
+ (struct fuse_bank9_regs *)bank->fuse_regs;
+
+ if (0 == dev_id) {
+ u32 value = readl(&fuse->mac_addr1);
+ mac[0] = (value >> 8);
+ mac[1] = value;
+
+ value = readl(&fuse->mac_addr0);
+ mac[2] = value >> 24;
+ mac[3] = value >> 16;
+ mac[4] = value >> 8;
+ mac[5] = value;
+ } else {
+ u32 value = readl(&fuse->mac_addr2);
+ mac[0] = value >> 24;
+ mac[1] = value >> 16;
+ mac[2] = value >> 8;
+ mac[3] = value;
+
+ value = readl(&fuse->mac_addr1);
+ mac[4] = value >> 24;
+ mac[5] = value >> 16;
+ }
+}
+#endif
+
+#ifdef CONFIG_IMX_BOOTAUX
+int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
+{
+ u32 stack, pc;
+ struct src *src_reg = (struct src *)SRC_BASE_ADDR;
+
+ if (!boot_private_data)
+ return 1;
+
+ stack = *(u32 *)boot_private_data;
+ pc = *(u32 *)(boot_private_data + 4);
+
+ /* Set the stack and pc to M4 bootROM */
+ writel(stack, M4_BOOTROM_BASE_ADDR);
+ writel(pc, M4_BOOTROM_BASE_ADDR + 4);
+
+ /* Enable M4 */
+ clrsetbits_le32(&src_reg->m4rcr, SRC_M4RCR_M4C_NON_SCLR_RST_MASK,
+ SRC_M4RCR_ENABLE_M4_MASK);
+
+ return 0;
+}
+
+int arch_auxiliary_core_check_up(u32 core_id)
+{
+ uint32_t val;
+ struct src *src_reg = (struct src *)SRC_BASE_ADDR;
+
+ val = readl(&src_reg->m4rcr);
+ if (val & 0x00000001)
+ return 0; /* assert in reset */
+
+ return 1;
+}
+#endif
+
+void set_wdog_reset(struct wdog_regs *wdog)
+{
+ u32 reg = readw(&wdog->wcr);
+ /*
+ * Output WDOG_B signal to reset external pmic or POR_B decided by
+ * the board desgin. Without external reset, the peripherals/DDR/
+ * PMIC are not reset, that may cause system working abnormal.
+ */
+ reg = readw(&wdog->wcr);
+ reg |= 1 << 3;
+ /*
+ * WDZST bit is write-once only bit. Align this bit in kernel,
+ * otherwise kernel code will have no chance to set this bit.
+ */
+ reg |= 1 << 0;
+ writew(reg, &wdog->wcr);
+}
+
+/*
+ * cfg_val will be used for
+ * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
+ * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
+ * to SBMR1, which will determine the boot device.
+ */
+const struct boot_mode soc_boot_modes[] = {
+ {"ecspi1:0", MAKE_CFGVAL(0x00, 0x60, 0x00, 0x00)},
+ {"ecspi1:1", MAKE_CFGVAL(0x40, 0x62, 0x00, 0x00)},
+ {"ecspi1:2", MAKE_CFGVAL(0x80, 0x64, 0x00, 0x00)},
+ {"ecspi1:3", MAKE_CFGVAL(0xc0, 0x66, 0x00, 0x00)},
+
+ {"weim", MAKE_CFGVAL(0x00, 0x50, 0x00, 0x00)},
+ {"qspi1", MAKE_CFGVAL(0x10, 0x40, 0x00, 0x00)},
+ /* 4 bit bus width */
+ {"usdhc1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
+ {"usdhc2", MAKE_CFGVAL(0x10, 0x14, 0x00, 0x00)},
+ {"usdhc3", MAKE_CFGVAL(0x10, 0x18, 0x00, 0x00)},
+ {"mmc1", MAKE_CFGVAL(0x10, 0x20, 0x00, 0x00)},
+ {"mmc2", MAKE_CFGVAL(0x10, 0x24, 0x00, 0x00)},
+ {"mmc3", MAKE_CFGVAL(0x10, 0x28, 0x00, 0x00)},
+ {NULL, 0},
+};
+
+enum boot_device get_boot_device(void)
+{
+ struct bootrom_sw_info **p =
+ (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
+
+ enum boot_device boot_dev = SD1_BOOT;
+ u8 boot_type = (*p)->boot_dev_type;
+ u8 boot_instance = (*p)->boot_dev_instance;
+
+ switch (boot_type) {
+ case BOOT_TYPE_SD:
+ boot_dev = boot_instance + SD1_BOOT;
+ break;
+ case BOOT_TYPE_MMC:
+ boot_dev = boot_instance + MMC1_BOOT;
+ break;
+ case BOOT_TYPE_NAND:
+ boot_dev = NAND_BOOT;
+ break;
+ case BOOT_TYPE_QSPI:
+ boot_dev = QSPI_BOOT;
+ break;
+ case BOOT_TYPE_WEIM:
+ boot_dev = WEIM_NOR_BOOT;
+ break;
+ case BOOT_TYPE_SPINOR:
+ boot_dev = SPI_NOR_BOOT;
+ break;
+ default:
+ break;
+ }
+
+ return boot_dev;
+}
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+__weak int board_mmc_get_env_dev(int devno)
+{
+ return CONFIG_SYS_MMC_ENV_DEV;
+}
+
+int mmc_get_env_dev(void)
+{
+ struct bootrom_sw_info **p =
+ (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
+ int devno = (*p)->boot_dev_instance;
+ u8 boot_type = (*p)->boot_dev_type;
+
+ /* If not boot from sd/mmc, use default value */
+ if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC))
+ return CONFIG_SYS_MMC_ENV_DEV;
+
+ return board_mmc_get_env_dev(devno);
+}
+#endif
+
+void s_init(void)
+{
+#if !defined CONFIG_SPL_BUILD
+ /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
+ asm volatile(
+ "mrc p15, 0, r0, c1, c0, 1\n"
+ "orr r0, r0, #1 << 6\n"
+ "mcr p15, 0, r0, c1, c0, 1\n");
+#endif
+ /* clock configuration. */
+ clock_init();
+
+ return;
+}
+
+void reset_misc(void)
+{
+#ifdef CONFIG_VIDEO_MXS
+ lcdif_power_down();
+#endif
+}
+
--- /dev/null
+if ARCH_MX7ULP
+
+config SYS_SOC
+ default "mx7ulp"
+
+choice
+ prompt "MX7ULP board select"
+ optional
+
+config TARGET_MX7ULP_EVK
+ bool "Support mx7ulp EVK board"
+
+endchoice
+
+source "board/freescale/mx7ulp_evk/Kconfig"
+
+endif
--- /dev/null
+#
+# (C) Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+#
+
+obj-y := soc.o clock.o iomux.o pcc.o scg.o
--- /dev/null
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int get_clocks(void)
+{
+#ifdef CONFIG_FSL_ESDHC
+#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC0_RBASE
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC1_RBASE
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+#endif
+#endif
+ return 0;
+}
+
+static u32 get_fast_plat_clk(void)
+{
+ return scg_clk_get_rate(SCG_NIC0_CLK);
+}
+
+static u32 get_slow_plat_clk(void)
+{
+ return scg_clk_get_rate(SCG_NIC1_CLK);
+}
+
+static u32 get_ipg_clk(void)
+{
+ return scg_clk_get_rate(SCG_NIC1_BUS_CLK);
+}
+
+u32 get_lpuart_clk(void)
+{
+ int index = 0;
+
+ const u32 lpuart_array[] = {
+ LPUART0_RBASE,
+ LPUART1_RBASE,
+ LPUART2_RBASE,
+ LPUART3_RBASE,
+ LPUART4_RBASE,
+ LPUART5_RBASE,
+ LPUART6_RBASE,
+ LPUART7_RBASE,
+ };
+
+ const enum pcc_clk lpuart_pcc_clks[] = {
+ PER_CLK_LPUART4,
+ PER_CLK_LPUART5,
+ PER_CLK_LPUART6,
+ PER_CLK_LPUART7,
+ };
+
+ for (index = 0; index < 8; index++) {
+ if (lpuart_array[index] == LPUART_BASE)
+ break;
+ }
+
+ if (index < 4 || index > 7)
+ return 0;
+
+ return pcc_clock_get_rate(lpuart_pcc_clks[index - 4]);
+}
+
+#ifdef CONFIG_SYS_LPI2C_IMX
+int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
+{
+ /* Set parent to FIRC DIV2 clock */
+ const enum pcc_clk lpi2c_pcc_clks[] = {
+ PER_CLK_LPI2C4,
+ PER_CLK_LPI2C5,
+ PER_CLK_LPI2C6,
+ PER_CLK_LPI2C7,
+ };
+
+ if (i2c_num < 4 || i2c_num > 7)
+ return -EINVAL;
+
+ if (enable) {
+ pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], false);
+ pcc_clock_sel(lpi2c_pcc_clks[i2c_num - 4], SCG_FIRC_DIV2_CLK);
+ pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], true);
+ } else {
+ pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], false);
+ }
+ return 0;
+}
+
+u32 imx_get_i2cclk(unsigned i2c_num)
+{
+ const enum pcc_clk lpi2c_pcc_clks[] = {
+ PER_CLK_LPI2C4,
+ PER_CLK_LPI2C5,
+ PER_CLK_LPI2C6,
+ PER_CLK_LPI2C7,
+ };
+
+ if (i2c_num < 4 || i2c_num > 7)
+ return 0;
+
+ return pcc_clock_get_rate(lpi2c_pcc_clks[i2c_num - 4]);
+}
+#endif
+
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+ switch (clk) {
+ case MXC_ARM_CLK:
+ return scg_clk_get_rate(SCG_CORE_CLK);
+ case MXC_AXI_CLK:
+ return get_fast_plat_clk();
+ case MXC_AHB_CLK:
+ return get_slow_plat_clk();
+ case MXC_IPG_CLK:
+ return get_ipg_clk();
+ case MXC_I2C_CLK:
+ return pcc_clock_get_rate(PER_CLK_LPI2C4);
+ case MXC_UART_CLK:
+ return get_lpuart_clk();
+ case MXC_ESDHC_CLK:
+ return pcc_clock_get_rate(PER_CLK_USDHC0);
+ case MXC_ESDHC2_CLK:
+ return pcc_clock_get_rate(PER_CLK_USDHC1);
+ case MXC_DDR_CLK:
+ return scg_clk_get_rate(SCG_DDR_CLK);
+ default:
+ printf("Unsupported mxc_clock %d\n", clk);
+ break;
+ }
+
+ return 0;
+}
+
+void init_clk_usdhc(u32 index)
+{
+ switch (index) {
+ case 0:
+ /*Disable the clock before configure it */
+ pcc_clock_enable(PER_CLK_USDHC0, false);
+
+ /* 158MHz / 1 = 158MHz */
+ pcc_clock_sel(PER_CLK_USDHC0, SCG_NIC1_CLK);
+ pcc_clock_div_config(PER_CLK_USDHC0, false, 1);
+ pcc_clock_enable(PER_CLK_USDHC0, true);
+ break;
+ case 1:
+ /*Disable the clock before configure it */
+ pcc_clock_enable(PER_CLK_USDHC1, false);
+
+ /* 158MHz / 1 = 158MHz */
+ pcc_clock_sel(PER_CLK_USDHC1, SCG_NIC1_CLK);
+ pcc_clock_div_config(PER_CLK_USDHC1, false, 1);
+ pcc_clock_enable(PER_CLK_USDHC1, true);
+ break;
+ default:
+ printf("Invalid index for USDHC %d\n", index);
+ break;
+ }
+}
+
+#ifdef CONFIG_MXC_OCOTP
+
+#define OCOTP_CTRL_PCC1_SLOT (38)
+#define OCOTP_CTRL_HIGH4K_PCC1_SLOT (39)
+
+void enable_ocotp_clk(unsigned char enable)
+{
+ u32 val;
+
+ /*
+ * Seems the OCOTP CLOCKs have been enabled at default,
+ * check its inuse flag
+ */
+
+ val = readl(PCC1_RBASE + 4 * OCOTP_CTRL_PCC1_SLOT);
+ if (!(val & PCC_INUSE_MASK))
+ writel(PCC_CGC_MASK, (PCC1_RBASE + 4 * OCOTP_CTRL_PCC1_SLOT));
+
+ val = readl(PCC1_RBASE + 4 * OCOTP_CTRL_HIGH4K_PCC1_SLOT);
+ if (!(val & PCC_INUSE_MASK))
+ writel(PCC_CGC_MASK,
+ (PCC1_RBASE + 4 * OCOTP_CTRL_HIGH4K_PCC1_SLOT));
+}
+#endif
+
+void enable_usboh3_clk(unsigned char enable)
+{
+ if (enable) {
+ pcc_clock_enable(PER_CLK_USB0, false);
+ pcc_clock_sel(PER_CLK_USB0, SCG_NIC1_BUS_CLK);
+ pcc_clock_enable(PER_CLK_USB0, true);
+
+#ifdef CONFIG_USB_MAX_CONTROLLER_COUNT
+ if (CONFIG_USB_MAX_CONTROLLER_COUNT > 1) {
+ pcc_clock_enable(PER_CLK_USB1, false);
+ pcc_clock_sel(PER_CLK_USB1, SCG_NIC1_BUS_CLK);
+ pcc_clock_enable(PER_CLK_USB1, true);
+ }
+#endif
+
+ pcc_clock_enable(PER_CLK_USB_PHY, true);
+ pcc_clock_enable(PER_CLK_USB_PL301, true);
+ } else {
+ pcc_clock_enable(PER_CLK_USB0, false);
+ pcc_clock_enable(PER_CLK_USB1, false);
+ pcc_clock_enable(PER_CLK_USB_PHY, false);
+ pcc_clock_enable(PER_CLK_USB_PL301, false);
+ }
+}
+
+static void lpuart_set_clk(uint32_t index, enum scg_clk clk)
+{
+ const enum pcc_clk lpuart_pcc_clks[] = {
+ PER_CLK_LPUART4,
+ PER_CLK_LPUART5,
+ PER_CLK_LPUART6,
+ PER_CLK_LPUART7,
+ };
+
+ if (index < 4 || index > 7)
+ return;
+
+#ifndef CONFIG_CLK_DEBUG
+ pcc_clock_enable(lpuart_pcc_clks[index - 4], false);
+#endif
+ pcc_clock_sel(lpuart_pcc_clks[index - 4], clk);
+ pcc_clock_enable(lpuart_pcc_clks[index - 4], true);
+}
+
+static void init_clk_lpuart(void)
+{
+ u32 index = 0, i;
+
+ const u32 lpuart_array[] = {
+ LPUART0_RBASE,
+ LPUART1_RBASE,
+ LPUART2_RBASE,
+ LPUART3_RBASE,
+ LPUART4_RBASE,
+ LPUART5_RBASE,
+ LPUART6_RBASE,
+ LPUART7_RBASE,
+ };
+
+ for (i = 0; i < 8; i++) {
+ if (lpuart_array[i] == LPUART_BASE) {
+ index = i;
+ break;
+ }
+ }
+
+ lpuart_set_clk(index, SCG_SOSC_DIV2_CLK);
+}
+
+static void init_clk_rgpio2p(void)
+{
+ /*Enable RGPIO2P1 clock */
+ pcc_clock_enable(PER_CLK_RGPIO2P1, true);
+
+ /*
+ * Hard code to enable RGPIO2P0 clock since it is not
+ * in clock frame for A7 domain
+ */
+ writel(PCC_CGC_MASK, (PCC0_RBASE + 0x3C));
+}
+
+/* Configure PLL/PFD freq */
+void clock_init(void)
+{
+ /*
+ * ROM has enabled clocks:
+ * A4 side: SIRC 16Mhz (DIV1-3 off), FIRC 48Mhz (DIV1-2 on),
+ * Non-LP-boot: SOSC, SPLL PFD0 (scs selected)
+ * A7 side: SPLL PFD0 (scs selected, 413Mhz),
+ * APLL PFD0 (352Mhz), DDRCLK, all NIC clocks
+ * A7 Plat0 (NIC0) = 176Mhz, Plat1 (NIC1) = 176Mhz,
+ * IP BUS (NIC1_BUS) = 58.6Mhz
+ *
+ * In u-boot:
+ * 1. Enable PFD1-3 of APLL for A7 side. Enable FIRC and DIVs.
+ * 2. Enable USB PLL
+ * 3. Init the clocks of peripherals used in u-boot bu
+ * without set rate interface.The clocks for these
+ * peripherals are enabled in this intialization.
+ * 4.Other peripherals with set clock rate interface
+ * does not be set in this function.
+ */
+
+ scg_a7_firc_init();
+
+ scg_a7_soscdiv_init();
+
+ /* APLL PFD1 = 270Mhz, PFD2=480Mhz, PFD3=800Mhz */
+ scg_enable_pll_pfd(SCG_APLL_PFD1_CLK, 35);
+ scg_enable_pll_pfd(SCG_APLL_PFD2_CLK, 20);
+ scg_enable_pll_pfd(SCG_APLL_PFD3_CLK, 12);
+
+ init_clk_lpuart();
+
+ init_clk_rgpio2p();
+
+ enable_usboh3_clk(1);
+}
+
+#ifdef CONFIG_SECURE_BOOT
+void hab_caam_clock_enable(unsigned char enable)
+{
+ if (enable)
+ pcc_clock_enable(PER_CLK_CAAM, true);
+ else
+ pcc_clock_enable(PER_CLK_CAAM, false);
+}
+#endif
+
+/*
+ * Dump some core clockes.
+ */
+int do_mx7_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ u32 addr = 0;
+ u32 freq;
+ freq = decode_pll(PLL_A7_SPLL);
+ printf("PLL_A7_SPLL %8d MHz\n", freq / 1000000);
+
+ freq = decode_pll(PLL_A7_APLL);
+ printf("PLL_A7_APLL %8d MHz\n", freq / 1000000);
+
+ freq = decode_pll(PLL_USB);
+ printf("PLL_USB %8d MHz\n", freq / 1000000);
+
+ printf("\n");
+
+ printf("CORE %8d kHz\n", scg_clk_get_rate(SCG_CORE_CLK) / 1000);
+ printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
+ printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
+ printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
+ printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
+ printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
+ printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
+ printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
+ printf("I2C4 %8d kHz\n", mxc_get_clock(MXC_I2C_CLK) / 1000);
+
+ addr = (u32) clock_init;
+ printf("[%s] addr = 0x%08X\r\n", __func__, addr);
+ scg_a7_info();
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ clocks, CONFIG_SYS_MAXARGS, 1, do_mx7_showclocks,
+ "display clocks",
+ ""
+);
--- /dev/null
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+
+static void *base = (void *)IOMUXC_BASE_ADDR;
+
+/*
+ * iomuxc0 base address. In imx7ulp-pins.h,
+ * the offsets of pins in iomuxc0 are from 0xD000,
+ * so we set the base address to (0x4103D000 - 0xD000 = 0x41030000)
+ */
+static void *base_mports = (void *)(AIPS0_BASE + 0x30000);
+
+/*
+ * configures a single pad in the iomuxer
+ */
+void mx7ulp_iomux_setup_pad(iomux_cfg_t pad)
+{
+ u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
+ u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
+ u32 sel_input_ofs =
+ (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
+ u32 sel_input =
+ (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
+ u32 pad_ctrl_ofs = mux_ctrl_ofs;
+ u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
+
+ debug("[PAD CFG] = 0x%16llX \r\n\tmux_ctl = 0x%X(0x%X) sel_input = 0x%X(0x%X) pad_ctrl = 0x%X(0x%X)\r\n",
+ pad, mux_ctrl_ofs, mux_mode, sel_input_ofs, sel_input,
+ pad_ctrl_ofs, pad_ctrl);
+
+ if (mux_mode & IOMUX_CONFIG_MPORTS) {
+ mux_mode &= ~IOMUX_CONFIG_MPORTS;
+ base = base_mports;
+ } else {
+ base = (void *)IOMUXC_BASE_ADDR;
+ }
+
+ __raw_writel(((mux_mode << IOMUXC_PCR_MUX_ALT_SHIFT) &
+ IOMUXC_PCR_MUX_ALT_MASK), base + mux_ctrl_ofs);
+
+ if (sel_input_ofs)
+ __raw_writel((sel_input << IOMUXC_PSMI_IMUX_ALT_SHIFT),
+ base + sel_input_ofs);
+
+ if (!(pad_ctrl & NO_PAD_CTRL))
+ __raw_writel(((mux_mode << IOMUXC_PCR_MUX_ALT_SHIFT) &
+ IOMUXC_PCR_MUX_ALT_MASK) |
+ (pad_ctrl & (~IOMUXC_PCR_MUX_ALT_MASK)),
+ base + pad_ctrl_ofs);
+}
+
+/* configures a list of pads within declared with IOMUX_PADS macro */
+void mx7ulp_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list,
+ unsigned count)
+{
+ iomux_cfg_t const *p = pad_list;
+ int i;
+
+ for (i = 0; i < count; i++) {
+ mx7ulp_iomux_setup_pad(*p);
+ p++;
+ }
+}
--- /dev/null
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/pcc.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PCC_CLKSRC_TYPES 2
+#define PCC_CLKSRC_NUM 7
+
+static enum scg_clk pcc_clksrc[PCC_CLKSRC_TYPES][PCC_CLKSRC_NUM] = {
+ { SCG_NIC1_BUS_CLK,
+ SCG_NIC1_CLK,
+ SCG_DDR_CLK,
+ SCG_APLL_PFD2_CLK,
+ SCG_APLL_PFD1_CLK,
+ SCG_APLL_PFD0_CLK,
+ USB_PLL_OUT,
+ },
+ { SCG_SOSC_DIV2_CLK, /* SOSC BUS clock */
+ MIPI_PLL_OUT,
+ SCG_FIRC_DIV2_CLK, /* FIRC BUS clock */
+ SCG_ROSC_CLK,
+ SCG_NIC1_BUS_CLK,
+ SCG_NIC1_CLK,
+ SCG_APLL_PFD3_CLK,
+ },
+};
+
+static struct pcc_entry pcc_arrays[] = {
+ {PCC2_RBASE, DMA1_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
+ {PCC2_RBASE, RGPIO1_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
+ {PCC2_RBASE, FLEXBUS0_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
+ {PCC2_RBASE, SEMA42_1_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
+ {PCC2_RBASE, DMA1_CH_MUX0_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
+ {PCC2_RBASE, SNVS_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
+ {PCC2_RBASE, CAAM_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
+ {PCC2_RBASE, LPTPM4_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
+ {PCC2_RBASE, LPTPM5_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
+ {PCC2_RBASE, LPIT1_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
+ {PCC2_RBASE, LPSPI2_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
+ {PCC2_RBASE, LPSPI3_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
+ {PCC2_RBASE, LPI2C4_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
+ {PCC2_RBASE, LPI2C5_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
+ {PCC2_RBASE, LPUART4_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
+ {PCC2_RBASE, LPUART5_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
+ {PCC2_RBASE, FLEXIO1_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
+ {PCC2_RBASE, USBOTG0_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
+ {PCC2_RBASE, USBOTG1_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
+ {PCC2_RBASE, USBPHY_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
+ {PCC2_RBASE, USB_PL301_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
+ {PCC2_RBASE, USDHC0_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
+ {PCC2_RBASE, USDHC1_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
+ {PCC2_RBASE, WDG1_PCC2_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV},
+ {PCC2_RBASE, WDG2_PCC2_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV},
+
+ {PCC3_RBASE, LPTPM6_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
+ {PCC3_RBASE, LPTPM7_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
+ {PCC3_RBASE, LPI2C6_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
+ {PCC3_RBASE, LPI2C7_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
+ {PCC3_RBASE, LPUART6_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
+ {PCC3_RBASE, LPUART7_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
+ {PCC3_RBASE, VIU0_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
+ {PCC3_RBASE, DSI0_PCC3_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV},
+ {PCC3_RBASE, LCDIF0_PCC3_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
+ {PCC3_RBASE, MMDC0_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
+ {PCC3_RBASE, PORTC_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
+ {PCC3_RBASE, PORTD_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
+ {PCC3_RBASE, PORTE_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
+ {PCC3_RBASE, PORTF_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
+ {PCC3_RBASE, GPU3D_PCC3_SLOT, CLKSRC_PER_PLAT, PCC_NO_DIV},
+ {PCC3_RBASE, GPU2D_PCC3_SLOT, CLKSRC_PER_PLAT, PCC_NO_DIV},
+};
+
+int pcc_clock_enable(enum pcc_clk clk, bool enable)
+{
+ u32 reg, val;
+
+ if (clk >= ARRAY_SIZE(pcc_arrays))
+ return -EINVAL;
+
+ reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
+
+ val = readl(reg);
+
+ clk_debug("pcc_clock_enable: clk %d, reg 0x%x, val 0x%x, enable %d\n",
+ clk, reg, val, enable);
+
+ if (!(val & PCC_PR_MASK) || (val & PCC_INUSE_MASK))
+ return -EPERM;
+
+ if (enable)
+ val |= PCC_CGC_MASK;
+ else
+ val &= ~PCC_CGC_MASK;
+
+ writel(val, reg);
+
+ clk_debug("pcc_clock_enable: val 0x%x\n", val);
+
+ return 0;
+}
+
+/* The clock source select needs clock is disabled */
+int pcc_clock_sel(enum pcc_clk clk, enum scg_clk src)
+{
+ u32 reg, val, i, clksrc_type;
+
+ if (clk >= ARRAY_SIZE(pcc_arrays))
+ return -EINVAL;
+
+ clksrc_type = pcc_arrays[clk].clksrc;
+ if (clksrc_type >= CLKSRC_NO_PCS) {
+ printf("No PCS field for the PCC %d, clksrc type %d\n",
+ clk, clksrc_type);
+ return -EPERM;
+ }
+
+ for (i = 0; i < PCC_CLKSRC_NUM; i++) {
+ if (pcc_clksrc[clksrc_type][i] == src) {
+ /* Find the clock src, then set it to PCS */
+ break;
+ }
+ }
+
+ if (i == PCC_CLKSRC_NUM) {
+ printf("Not find the parent scg_clk in PCS of PCC %d, invalid scg_clk %d\n", clk, src);
+ return -EINVAL;
+ }
+
+ reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
+
+ val = readl(reg);
+
+ clk_debug("pcc_clock_sel: clk %d, reg 0x%x, val 0x%x, clksrc_type %d\n",
+ clk, reg, val, clksrc_type);
+
+ if (!(val & PCC_PR_MASK) || (val & PCC_INUSE_MASK) ||
+ (val & PCC_CGC_MASK)) {
+ printf("Not permit to select clock source val = 0x%x\n", val);
+ return -EPERM;
+ }
+
+ val &= ~PCC_PCS_MASK;
+ val |= ((i + 1) << PCC_PCS_OFFSET);
+
+ writel(val, reg);
+
+ clk_debug("pcc_clock_sel: val 0x%x\n", val);
+
+ return 0;
+}
+
+int pcc_clock_div_config(enum pcc_clk clk, bool frac, u8 div)
+{
+ u32 reg, val;
+
+ if (clk >= ARRAY_SIZE(pcc_arrays) || div > 8 ||
+ (div == 1 && frac != 0))
+ return -EINVAL;
+
+ if (pcc_arrays[clk].div >= PCC_NO_DIV) {
+ printf("No DIV/FRAC field for the PCC %d\n", clk);
+ return -EPERM;
+ }
+
+ reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
+
+ val = readl(reg);
+
+ if (!(val & PCC_PR_MASK) || (val & PCC_INUSE_MASK) ||
+ (val & PCC_CGC_MASK)) {
+ printf("Not permit to set div/frac val = 0x%x\n", val);
+ return -EPERM;
+ }
+
+ if (frac)
+ val |= PCC_FRAC_MASK;
+ else
+ val &= ~PCC_FRAC_MASK;
+
+ val &= ~PCC_PCD_MASK;
+ val |= (div - 1) & PCC_PCD_MASK;
+
+ writel(val, reg);
+
+ return 0;
+}
+
+bool pcc_clock_is_enable(enum pcc_clk clk)
+{
+ u32 reg, val;
+
+ if (clk >= ARRAY_SIZE(pcc_arrays))
+ return -EINVAL;
+
+ reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
+ val = readl(reg);
+
+ if ((val & PCC_INUSE_MASK) || (val & PCC_CGC_MASK))
+ return true;
+
+ return false;
+}
+
+int pcc_clock_get_clksrc(enum pcc_clk clk, enum scg_clk *src)
+{
+ u32 reg, val, clksrc_type;
+
+ if (clk >= ARRAY_SIZE(pcc_arrays))
+ return -EINVAL;
+
+ clksrc_type = pcc_arrays[clk].clksrc;
+ if (clksrc_type >= CLKSRC_NO_PCS) {
+ printf("No PCS field for the PCC %d, clksrc type %d\n",
+ clk, clksrc_type);
+ return -EPERM;
+ }
+
+ reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
+
+ val = readl(reg);
+
+ clk_debug("pcc_clock_get_clksrc: clk %d, reg 0x%x, val 0x%x, type %d\n",
+ clk, reg, val, clksrc_type);
+
+ if (!(val & PCC_PR_MASK)) {
+ printf("This pcc slot is not present = 0x%x\n", val);
+ return -EPERM;
+ }
+
+ val &= PCC_PCS_MASK;
+ val = (val >> PCC_PCS_OFFSET);
+
+ if (!val) {
+ printf("Clock source is off\n");
+ return -EIO;
+ }
+
+ *src = pcc_clksrc[clksrc_type][val - 1];
+
+ clk_debug("pcc_clock_get_clksrc: parent scg clk %d\n", *src);
+
+ return 0;
+}
+
+u32 pcc_clock_get_rate(enum pcc_clk clk)
+{
+ u32 reg, val, rate, frac, div;
+ enum scg_clk parent;
+ int ret;
+
+ ret = pcc_clock_get_clksrc(clk, &parent);
+ if (ret)
+ return 0;
+
+ rate = scg_clk_get_rate(parent);
+
+ clk_debug("pcc_clock_get_rate: parent rate %u\n", rate);
+
+ if (pcc_arrays[clk].div == PCC_HAS_DIV) {
+ reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
+ val = readl(reg);
+
+ frac = (val & PCC_FRAC_MASK) >> PCC_FRAC_OFFSET;
+ div = (val & PCC_PCD_MASK) >> PCC_PCD_OFFSET;
+
+ /*
+ * Theoretically don't have overflow in the calc,
+ * the rate won't exceed 2G
+ */
+ rate = rate * (frac + 1) / (div + 1);
+ }
+
+ clk_debug("pcc_clock_get_rate: rate %u\n", rate);
+ return rate;
+}
--- /dev/null
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/pcc.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+scg_p scg1_regs = (scg_p)SCG1_RBASE;
+
+static u32 scg_src_get_rate(enum scg_clk clksrc)
+{
+ u32 reg;
+
+ switch (clksrc) {
+ case SCG_SOSC_CLK:
+ reg = readl(&scg1_regs->sosccsr);
+ if (!(reg & SCG_SOSC_CSR_SOSCVLD_MASK))
+ return 0;
+
+ return 24000000;
+ case SCG_FIRC_CLK:
+ reg = readl(&scg1_regs->firccsr);
+ if (!(reg & SCG_FIRC_CSR_FIRCVLD_MASK))
+ return 0;
+
+ return 48000000;
+ case SCG_SIRC_CLK:
+ reg = readl(&scg1_regs->sirccsr);
+ if (!(reg & SCG_SIRC_CSR_SIRCVLD_MASK))
+ return 0;
+
+ return 16000000;
+ case SCG_ROSC_CLK:
+ reg = readl(&scg1_regs->rtccsr);
+ if (!(reg & SCG_ROSC_CSR_ROSCVLD_MASK))
+ return 0;
+
+ return 32768;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static u32 scg_sircdiv_get_rate(enum scg_clk clk)
+{
+ u32 reg, val, rate;
+ u32 shift, mask;
+
+ switch (clk) {
+ case SCG_SIRC_DIV1_CLK:
+ mask = SCG_SIRCDIV_DIV1_MASK;
+ shift = SCG_SIRCDIV_DIV1_SHIFT;
+ break;
+ case SCG_SIRC_DIV2_CLK:
+ mask = SCG_SIRCDIV_DIV2_MASK;
+ shift = SCG_SIRCDIV_DIV2_SHIFT;
+ break;
+ case SCG_SIRC_DIV3_CLK:
+ mask = SCG_SIRCDIV_DIV3_MASK;
+ shift = SCG_SIRCDIV_DIV3_SHIFT;
+ break;
+ default:
+ return 0;
+ }
+
+ reg = readl(&scg1_regs->sirccsr);
+ if (!(reg & SCG_SIRC_CSR_SIRCVLD_MASK))
+ return 0;
+
+ reg = readl(&scg1_regs->sircdiv);
+ val = (reg & mask) >> shift;
+
+ if (!val) /*clock disabled*/
+ return 0;
+
+ rate = scg_src_get_rate(SCG_SIRC_CLK);
+ rate = rate / (1 << (val - 1));
+
+ return rate;
+}
+
+static u32 scg_fircdiv_get_rate(enum scg_clk clk)
+{
+ u32 reg, val, rate;
+ u32 shift, mask;
+
+ switch (clk) {
+ case SCG_FIRC_DIV1_CLK:
+ mask = SCG_FIRCDIV_DIV1_MASK;
+ shift = SCG_FIRCDIV_DIV1_SHIFT;
+ break;
+ case SCG_FIRC_DIV2_CLK:
+ mask = SCG_FIRCDIV_DIV2_MASK;
+ shift = SCG_FIRCDIV_DIV2_SHIFT;
+ break;
+ case SCG_FIRC_DIV3_CLK:
+ mask = SCG_FIRCDIV_DIV3_MASK;
+ shift = SCG_FIRCDIV_DIV3_SHIFT;
+ break;
+ default:
+ return 0;
+ }
+
+ reg = readl(&scg1_regs->firccsr);
+ if (!(reg & SCG_FIRC_CSR_FIRCVLD_MASK))
+ return 0;
+
+ reg = readl(&scg1_regs->fircdiv);
+ val = (reg & mask) >> shift;
+
+ if (!val) /*clock disabled*/
+ return 0;
+
+ rate = scg_src_get_rate(SCG_FIRC_CLK);
+ rate = rate / (1 << (val - 1));
+
+ return rate;
+}
+
+static u32 scg_soscdiv_get_rate(enum scg_clk clk)
+{
+ u32 reg, val, rate;
+ u32 shift, mask;
+
+ switch (clk) {
+ case SCG_SOSC_DIV1_CLK:
+ mask = SCG_SOSCDIV_DIV1_MASK;
+ shift = SCG_SOSCDIV_DIV1_SHIFT;
+ break;
+ case SCG_SOSC_DIV2_CLK:
+ mask = SCG_SOSCDIV_DIV2_MASK;
+ shift = SCG_SOSCDIV_DIV2_SHIFT;
+ break;
+ case SCG_SOSC_DIV3_CLK:
+ mask = SCG_SOSCDIV_DIV3_MASK;
+ shift = SCG_SOSCDIV_DIV3_SHIFT;
+ break;
+ default:
+ return 0;
+ }
+
+ reg = readl(&scg1_regs->sosccsr);
+ if (!(reg & SCG_SOSC_CSR_SOSCVLD_MASK))
+ return 0;
+
+ reg = readl(&scg1_regs->soscdiv);
+ val = (reg & mask) >> shift;
+
+ if (!val) /*clock disabled*/
+ return 0;
+
+ rate = scg_src_get_rate(SCG_SOSC_CLK);
+ rate = rate / (1 << (val - 1));
+
+ return rate;
+}
+
+static u32 scg_apll_pfd_get_rate(enum scg_clk clk)
+{
+ u32 reg, val, rate;
+ u32 shift, mask, gate, valid;
+
+ switch (clk) {
+ case SCG_APLL_PFD0_CLK:
+ gate = SCG_PLL_PFD0_GATE_MASK;
+ valid = SCG_PLL_PFD0_VALID_MASK;
+ mask = SCG_PLL_PFD0_FRAC_MASK;
+ shift = SCG_PLL_PFD0_FRAC_SHIFT;
+ break;
+ case SCG_APLL_PFD1_CLK:
+ gate = SCG_PLL_PFD1_GATE_MASK;
+ valid = SCG_PLL_PFD1_VALID_MASK;
+ mask = SCG_PLL_PFD1_FRAC_MASK;
+ shift = SCG_PLL_PFD1_FRAC_SHIFT;
+ break;
+ case SCG_APLL_PFD2_CLK:
+ gate = SCG_PLL_PFD2_GATE_MASK;
+ valid = SCG_PLL_PFD2_VALID_MASK;
+ mask = SCG_PLL_PFD2_FRAC_MASK;
+ shift = SCG_PLL_PFD2_FRAC_SHIFT;
+ break;
+ case SCG_APLL_PFD3_CLK:
+ gate = SCG_PLL_PFD3_GATE_MASK;
+ valid = SCG_PLL_PFD3_VALID_MASK;
+ mask = SCG_PLL_PFD3_FRAC_MASK;
+ shift = SCG_PLL_PFD3_FRAC_SHIFT;
+ break;
+ default:
+ return 0;
+ }
+
+ reg = readl(&scg1_regs->apllpfd);
+ if (reg & gate || !(reg & valid))
+ return 0;
+
+ clk_debug("scg_apll_pfd_get_rate reg 0x%x\n", reg);
+
+ val = (reg & mask) >> shift;
+ rate = decode_pll(PLL_A7_APLL);
+
+ rate = rate / val * 18;
+
+ clk_debug("scg_apll_pfd_get_rate rate %u\n", rate);
+
+ return rate;
+}
+
+static u32 scg_spll_pfd_get_rate(enum scg_clk clk)
+{
+ u32 reg, val, rate;
+ u32 shift, mask, gate, valid;
+
+ switch (clk) {
+ case SCG_SPLL_PFD0_CLK:
+ gate = SCG_PLL_PFD0_GATE_MASK;
+ valid = SCG_PLL_PFD0_VALID_MASK;
+ mask = SCG_PLL_PFD0_FRAC_MASK;
+ shift = SCG_PLL_PFD0_FRAC_SHIFT;
+ break;
+ case SCG_SPLL_PFD1_CLK:
+ gate = SCG_PLL_PFD1_GATE_MASK;
+ valid = SCG_PLL_PFD1_VALID_MASK;
+ mask = SCG_PLL_PFD1_FRAC_MASK;
+ shift = SCG_PLL_PFD1_FRAC_SHIFT;
+ break;
+ case SCG_SPLL_PFD2_CLK:
+ gate = SCG_PLL_PFD2_GATE_MASK;
+ valid = SCG_PLL_PFD2_VALID_MASK;
+ mask = SCG_PLL_PFD2_FRAC_MASK;
+ shift = SCG_PLL_PFD2_FRAC_SHIFT;
+ break;
+ case SCG_SPLL_PFD3_CLK:
+ gate = SCG_PLL_PFD3_GATE_MASK;
+ valid = SCG_PLL_PFD3_VALID_MASK;
+ mask = SCG_PLL_PFD3_FRAC_MASK;
+ shift = SCG_PLL_PFD3_FRAC_SHIFT;
+ break;
+ default:
+ return 0;
+ }
+
+ reg = readl(&scg1_regs->spllpfd);
+ if (reg & gate || !(reg & valid))
+ return 0;
+
+ clk_debug("scg_spll_pfd_get_rate reg 0x%x\n", reg);
+
+ val = (reg & mask) >> shift;
+ rate = decode_pll(PLL_A7_SPLL);
+
+ rate = rate / val * 18;
+
+ clk_debug("scg_spll_pfd_get_rate rate %u\n", rate);
+
+ return rate;
+}
+
+static u32 scg_apll_get_rate(void)
+{
+ u32 reg, val, rate;
+
+ reg = readl(&scg1_regs->apllcfg);
+ val = (reg & SCG_PLL_CFG_PLLSEL_MASK) >> SCG_PLL_CFG_PLLSEL_SHIFT;
+
+ if (!val) {
+ /* APLL clock after two dividers */
+ rate = decode_pll(PLL_A7_APLL);
+
+ val = (reg & SCG_PLL_CFG_POSTDIV1_MASK) >>
+ SCG_PLL_CFG_POSTDIV1_SHIFT;
+ rate = rate / (val + 1);
+
+ val = (reg & SCG_PLL_CFG_POSTDIV2_MASK) >>
+ SCG_PLL_CFG_POSTDIV2_SHIFT;
+ rate = rate / (val + 1);
+ } else {
+ /* APLL PFD clock */
+ val = (reg & SCG_PLL_CFG_PFDSEL_MASK) >>
+ SCG_PLL_CFG_PFDSEL_SHIFT;
+ rate = scg_apll_pfd_get_rate(SCG_APLL_PFD0_CLK + val);
+ }
+
+ return rate;
+}
+
+static u32 scg_spll_get_rate(void)
+{
+ u32 reg, val, rate;
+
+ reg = readl(&scg1_regs->spllcfg);
+ val = (reg & SCG_PLL_CFG_PLLSEL_MASK) >> SCG_PLL_CFG_PLLSEL_SHIFT;
+
+ clk_debug("scg_spll_get_rate reg 0x%x\n", reg);
+
+ if (!val) {
+ /* APLL clock after two dividers */
+ rate = decode_pll(PLL_A7_SPLL);
+
+ val = (reg & SCG_PLL_CFG_POSTDIV1_MASK) >>
+ SCG_PLL_CFG_POSTDIV1_SHIFT;
+ rate = rate / (val + 1);
+
+ val = (reg & SCG_PLL_CFG_POSTDIV2_MASK) >>
+ SCG_PLL_CFG_POSTDIV2_SHIFT;
+ rate = rate / (val + 1);
+
+ clk_debug("scg_spll_get_rate SPLL %u\n", rate);
+
+ } else {
+ /* APLL PFD clock */
+ val = (reg & SCG_PLL_CFG_PFDSEL_MASK) >>
+ SCG_PLL_CFG_PFDSEL_SHIFT;
+ rate = scg_spll_pfd_get_rate(SCG_SPLL_PFD0_CLK + val);
+
+ clk_debug("scg_spll_get_rate PFD %u\n", rate);
+ }
+
+ return rate;
+}
+
+static u32 scg_ddr_get_rate(void)
+{
+ u32 reg, val, rate, div;
+
+ reg = readl(&scg1_regs->ddrccr);
+ val = (reg & SCG_DDRCCR_DDRCS_MASK) >> SCG_DDRCCR_DDRCS_SHIFT;
+ div = (reg & SCG_DDRCCR_DDRDIV_MASK) >> SCG_DDRCCR_DDRDIV_SHIFT;
+
+ if (!div)
+ return 0;
+
+ if (!val) {
+ reg = readl(&scg1_regs->apllcfg);
+ val = (reg & SCG_PLL_CFG_PFDSEL_MASK) >>
+ SCG_PLL_CFG_PFDSEL_SHIFT;
+ rate = scg_apll_pfd_get_rate(SCG_APLL_PFD0_CLK + val);
+ } else {
+ rate = decode_pll(PLL_USB);
+ }
+
+ rate = rate / (1 << (div - 1));
+ return rate;
+}
+
+static u32 scg_nic_get_rate(enum scg_clk clk)
+{
+ u32 reg, val, rate;
+ u32 shift, mask;
+
+ reg = readl(&scg1_regs->niccsr);
+ val = (reg & SCG_NICCSR_NICCS_MASK) >> SCG_NICCSR_NICCS_SHIFT;
+
+ clk_debug("scg_nic_get_rate niccsr 0x%x\n", reg);
+
+ if (!val)
+ rate = scg_src_get_rate(SCG_FIRC_CLK);
+ else
+ rate = scg_ddr_get_rate();
+
+ clk_debug("scg_nic_get_rate parent rate %u\n", rate);
+
+ val = (reg & SCG_NICCSR_NIC0DIV_MASK) >> SCG_NICCSR_NIC0DIV_SHIFT;
+
+ rate = rate / (val + 1);
+
+ clk_debug("scg_nic_get_rate NIC0 rate %u\n", rate);
+
+ switch (clk) {
+ case SCG_NIC0_CLK:
+ return rate;
+ case SCG_GPU_CLK:
+ mask = SCG_NICCSR_GPUDIV_MASK;
+ shift = SCG_NICCSR_GPUDIV_SHIFT;
+ break;
+ case SCG_NIC1_EXT_CLK:
+ case SCG_NIC1_BUS_CLK:
+ case SCG_NIC1_CLK:
+ mask = SCG_NICCSR_NIC1DIV_MASK;
+ shift = SCG_NICCSR_NIC1DIV_SHIFT;
+ break;
+ default:
+ return 0;
+ }
+
+ val = (reg & mask) >> shift;
+ rate = rate / (val + 1);
+
+ clk_debug("scg_nic_get_rate NIC1 rate %u\n", rate);
+
+ switch (clk) {
+ case SCG_GPU_CLK:
+ case SCG_NIC1_CLK:
+ return rate;
+ case SCG_NIC1_EXT_CLK:
+ mask = SCG_NICCSR_NIC1EXTDIV_MASK;
+ shift = SCG_NICCSR_NIC1EXTDIV_SHIFT;
+ break;
+ case SCG_NIC1_BUS_CLK:
+ mask = SCG_NICCSR_NIC1BUSDIV_MASK;
+ shift = SCG_NICCSR_NIC1BUSDIV_SHIFT;
+ break;
+ default:
+ return 0;
+ }
+
+ val = (reg & mask) >> shift;
+ rate = rate / (val + 1);
+
+ clk_debug("scg_nic_get_rate NIC1 bus rate %u\n", rate);
+ return rate;
+}
+
+
+static enum scg_clk scg_scs_array[4] = {
+ SCG_SOSC_CLK, SCG_SIRC_CLK, SCG_FIRC_CLK, SCG_ROSC_CLK,
+};
+
+static u32 scg_sys_get_rate(enum scg_clk clk)
+{
+ u32 reg, val, rate;
+
+ if (clk != SCG_CORE_CLK && clk != SCG_BUS_CLK)
+ return 0;
+
+ reg = readl(&scg1_regs->csr);
+ val = (reg & SCG_CCR_SCS_MASK) >> SCG_CCR_SCS_SHIFT;
+
+ clk_debug("scg_sys_get_rate reg 0x%x\n", reg);
+
+ switch (val) {
+ case SCG_SCS_SYS_OSC:
+ case SCG_SCS_SLOW_IRC:
+ case SCG_SCS_FAST_IRC:
+ case SCG_SCS_RTC_OSC:
+ rate = scg_src_get_rate(scg_scs_array[val]);
+ break;
+ case 5:
+ rate = scg_apll_get_rate();
+ break;
+ case 6:
+ rate = scg_spll_get_rate();
+ break;
+ default:
+ return 0;
+ }
+
+ clk_debug("scg_sys_get_rate parent rate %u\n", rate);
+
+ val = (reg & SCG_CCR_DIVCORE_MASK) >> SCG_CCR_DIVCORE_SHIFT;
+
+ rate = rate / (val + 1);
+
+ if (clk == SCG_BUS_CLK) {
+ val = (reg & SCG_CCR_DIVBUS_MASK) >> SCG_CCR_DIVBUS_SHIFT;
+ rate = rate / (val + 1);
+ }
+
+ return rate;
+}
+
+u32 decode_pll(enum pll_clocks pll)
+{
+ u32 reg, pre_div, infreq, mult;
+ u32 num, denom;
+
+ /*
+ * Alought there are four choices for the bypass src,
+ * we choose OSC_24M which is the default set in ROM.
+ */
+ switch (pll) {
+ case PLL_A7_SPLL:
+ reg = readl(&scg1_regs->spllcsr);
+
+ if (!(reg & SCG_SPLL_CSR_SPLLVLD_MASK))
+ return 0;
+
+ reg = readl(&scg1_regs->spllcfg);
+
+ pre_div = (reg & SCG_PLL_CFG_PREDIV_MASK) >>
+ SCG_PLL_CFG_PREDIV_SHIFT;
+ pre_div += 1;
+
+ mult = (reg & SCG1_SPLL_CFG_MULT_MASK) >>
+ SCG_PLL_CFG_MULT_SHIFT;
+
+ infreq = (reg & SCG_PLL_CFG_CLKSRC_MASK) >>
+ SCG_PLL_CFG_CLKSRC_SHIFT;
+ if (!infreq)
+ infreq = scg_src_get_rate(SCG_SOSC_CLK);
+ else
+ infreq = scg_src_get_rate(SCG_FIRC_CLK);
+
+ num = readl(&scg1_regs->spllnum);
+ denom = readl(&scg1_regs->splldenom);
+
+ infreq = infreq / pre_div;
+
+ return infreq * mult + infreq * num / denom;
+
+ case PLL_A7_APLL:
+ reg = readl(&scg1_regs->apllcsr);
+
+ if (!(reg & SCG_APLL_CSR_APLLVLD_MASK))
+ return 0;
+
+ reg = readl(&scg1_regs->apllcfg);
+
+ pre_div = (reg & SCG_PLL_CFG_PREDIV_MASK) >>
+ SCG_PLL_CFG_PREDIV_SHIFT;
+ pre_div += 1;
+
+ mult = (reg & SCG_APLL_CFG_MULT_MASK) >>
+ SCG_PLL_CFG_MULT_SHIFT;
+
+ infreq = (reg & SCG_PLL_CFG_CLKSRC_MASK) >>
+ SCG_PLL_CFG_CLKSRC_SHIFT;
+ if (!infreq)
+ infreq = scg_src_get_rate(SCG_SOSC_CLK);
+ else
+ infreq = scg_src_get_rate(SCG_FIRC_CLK);
+
+ num = readl(&scg1_regs->apllnum);
+ denom = readl(&scg1_regs->aplldenom);
+
+ infreq = infreq / pre_div;
+
+ return infreq * mult + infreq * num / denom;
+
+ case PLL_USB:
+ reg = readl(&scg1_regs->upllcsr);
+
+ if (!(reg & SCG_UPLL_CSR_UPLLVLD_MASK))
+ return 0;
+
+ return 480000000u;
+
+ case PLL_MIPI:
+ return 480000000u;
+ default:
+ printf("Unsupported pll clocks %d\n", pll);
+ break;
+ }
+
+ return 0;
+}
+
+u32 scg_clk_get_rate(enum scg_clk clk)
+{
+ switch (clk) {
+ case SCG_SIRC_DIV1_CLK:
+ case SCG_SIRC_DIV2_CLK:
+ case SCG_SIRC_DIV3_CLK:
+ return scg_sircdiv_get_rate(clk);
+
+ case SCG_FIRC_DIV1_CLK:
+ case SCG_FIRC_DIV2_CLK:
+ case SCG_FIRC_DIV3_CLK:
+ return scg_fircdiv_get_rate(clk);
+
+ case SCG_SOSC_DIV1_CLK:
+ case SCG_SOSC_DIV2_CLK:
+ case SCG_SOSC_DIV3_CLK:
+ return scg_soscdiv_get_rate(clk);
+
+ case SCG_CORE_CLK:
+ case SCG_BUS_CLK:
+ return scg_sys_get_rate(clk);
+
+ case SCG_SPLL_PFD0_CLK:
+ case SCG_SPLL_PFD1_CLK:
+ case SCG_SPLL_PFD2_CLK:
+ case SCG_SPLL_PFD3_CLK:
+ return scg_spll_pfd_get_rate(clk);
+
+ case SCG_APLL_PFD0_CLK:
+ case SCG_APLL_PFD1_CLK:
+ case SCG_APLL_PFD2_CLK:
+ case SCG_APLL_PFD3_CLK:
+ return scg_apll_pfd_get_rate(clk);
+
+ case SCG_DDR_CLK:
+ return scg_ddr_get_rate();
+
+ case SCG_NIC0_CLK:
+ case SCG_GPU_CLK:
+ case SCG_NIC1_CLK:
+ case SCG_NIC1_BUS_CLK:
+ case SCG_NIC1_EXT_CLK:
+ return scg_nic_get_rate(clk);
+
+ case USB_PLL_OUT:
+ return decode_pll(PLL_USB);
+
+ case MIPI_PLL_OUT:
+ return decode_pll(PLL_MIPI);
+
+ case SCG_SOSC_CLK:
+ case SCG_FIRC_CLK:
+ case SCG_SIRC_CLK:
+ case SCG_ROSC_CLK:
+ return scg_src_get_rate(clk);
+ default:
+ return 0;
+ }
+}
+
+int scg_enable_pll_pfd(enum scg_clk clk, u32 frac)
+{
+ u32 reg;
+ u32 shift, mask, gate, valid;
+ u32 addr;
+
+ if (frac < 12 || frac > 35)
+ return -EINVAL;
+
+ switch (clk) {
+ case SCG_SPLL_PFD0_CLK:
+ case SCG_APLL_PFD0_CLK:
+ gate = SCG_PLL_PFD0_GATE_MASK;
+ valid = SCG_PLL_PFD0_VALID_MASK;
+ mask = SCG_PLL_PFD0_FRAC_MASK;
+ shift = SCG_PLL_PFD0_FRAC_SHIFT;
+
+ if (clk == SCG_SPLL_PFD0_CLK)
+ addr = (u32)(&scg1_regs->spllpfd);
+ else
+ addr = (u32)(&scg1_regs->apllpfd);
+ break;
+ case SCG_SPLL_PFD1_CLK:
+ case SCG_APLL_PFD1_CLK:
+ gate = SCG_PLL_PFD1_GATE_MASK;
+ valid = SCG_PLL_PFD1_VALID_MASK;
+ mask = SCG_PLL_PFD1_FRAC_MASK;
+ shift = SCG_PLL_PFD1_FRAC_SHIFT;
+
+ if (clk == SCG_SPLL_PFD1_CLK)
+ addr = (u32)(&scg1_regs->spllpfd);
+ else
+ addr = (u32)(&scg1_regs->apllpfd);
+ break;
+ case SCG_SPLL_PFD2_CLK:
+ case SCG_APLL_PFD2_CLK:
+ gate = SCG_PLL_PFD2_GATE_MASK;
+ valid = SCG_PLL_PFD2_VALID_MASK;
+ mask = SCG_PLL_PFD2_FRAC_MASK;
+ shift = SCG_PLL_PFD2_FRAC_SHIFT;
+
+ if (clk == SCG_SPLL_PFD2_CLK)
+ addr = (u32)(&scg1_regs->spllpfd);
+ else
+ addr = (u32)(&scg1_regs->apllpfd);
+ break;
+ case SCG_SPLL_PFD3_CLK:
+ case SCG_APLL_PFD3_CLK:
+ gate = SCG_PLL_PFD3_GATE_MASK;
+ valid = SCG_PLL_PFD3_VALID_MASK;
+ mask = SCG_PLL_PFD3_FRAC_MASK;
+ shift = SCG_PLL_PFD3_FRAC_SHIFT;
+
+ if (clk == SCG_SPLL_PFD3_CLK)
+ addr = (u32)(&scg1_regs->spllpfd);
+ else
+ addr = (u32)(&scg1_regs->apllpfd);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* Gate the PFD */
+ reg = readl(addr);
+ reg |= gate;
+ writel(reg, addr);
+
+ /* Write Frac divider */
+ reg &= ~mask;
+ reg |= (frac << shift) & mask;
+ writel(reg, addr);
+
+ /*
+ * Un-gate the PFD
+ * (Need un-gate before checking valid, not align with RM)
+ */
+ reg &= ~gate;
+ writel(reg, addr);
+
+ /* Wait for PFD clock being valid */
+ do {
+ reg = readl(addr);
+ } while (!(reg & valid));
+
+ return 0;
+}
+
+#define SIM_MISC_CTRL0_USB_PLL_EN_MASK (0x1 << 2)
+int scg_enable_usb_pll(bool usb_control)
+{
+ u32 sosc_rate;
+ s32 timeout = 1000000;
+ u32 reg;
+
+ struct usbphy_regs *usbphy =
+ (struct usbphy_regs *)USBPHY_RBASE;
+
+ sosc_rate = scg_src_get_rate(SCG_SOSC_CLK);
+ if (!sosc_rate)
+ return -EPERM;
+
+ reg = readl(SIM0_RBASE + 0x3C);
+ if (usb_control)
+ reg &= ~SIM_MISC_CTRL0_USB_PLL_EN_MASK;
+ else
+ reg |= SIM_MISC_CTRL0_USB_PLL_EN_MASK;
+ writel(reg, SIM0_RBASE + 0x3C);
+
+ if (!(readl(&usbphy->usb1_pll_480_ctrl) & PLL_USB_LOCK_MASK)) {
+ writel(0x1c00000, &usbphy->usb1_pll_480_ctrl_clr);
+
+ switch (sosc_rate) {
+ case 24000000:
+ writel(0xc00000, &usbphy->usb1_pll_480_ctrl_set);
+ break;
+
+ case 30000000:
+ writel(0x800000, &usbphy->usb1_pll_480_ctrl_set);
+ break;
+
+ case 19200000:
+ writel(0x1400000, &usbphy->usb1_pll_480_ctrl_set);
+ break;
+
+ default:
+ writel(0xc00000, &usbphy->usb1_pll_480_ctrl_set);
+ break;
+ }
+
+ /* Enable the regulator first */
+ writel(PLL_USB_REG_ENABLE_MASK,
+ &usbphy->usb1_pll_480_ctrl_set);
+
+ /* Wait at least 15us */
+ udelay(15);
+
+ /* Enable the power */
+ writel(PLL_USB_PWR_MASK, &usbphy->usb1_pll_480_ctrl_set);
+
+ /* Wait lock */
+ while (timeout--) {
+ if (readl(&usbphy->usb1_pll_480_ctrl) &
+ PLL_USB_LOCK_MASK)
+ break;
+ }
+
+ if (timeout <= 0) {
+ /* If timeout, we power down the pll */
+ writel(PLL_USB_PWR_MASK,
+ &usbphy->usb1_pll_480_ctrl_clr);
+ return -ETIME;
+ }
+ }
+
+ /* Clear the bypass */
+ writel(PLL_USB_BYPASS_MASK, &usbphy->usb1_pll_480_ctrl_clr);
+
+ /* Enable the PLL clock out to USB */
+ writel((PLL_USB_EN_USB_CLKS_MASK | PLL_USB_ENABLE_MASK),
+ &usbphy->usb1_pll_480_ctrl_set);
+
+ if (!usb_control) {
+ while (timeout--) {
+ if (readl(&scg1_regs->upllcsr) &
+ SCG_UPLL_CSR_UPLLVLD_MASK)
+ break;
+ }
+
+ if (timeout <= 0) {
+ reg = readl(SIM0_RBASE + 0x3C);
+ reg &= ~SIM_MISC_CTRL0_USB_PLL_EN_MASK;
+ writel(reg, SIM0_RBASE + 0x3C);
+ return -ETIME;
+ }
+ }
+
+ return 0;
+}
+
+
+/* A7 domain system clock source is SPLL */
+#define SCG1_RCCR_SCS_NUM ((SCG_SCS_SYS_PLL) << SCG_CCR_SCS_SHIFT)
+
+/* A7 Core clck = SPLL PFD0 / 1 = 500MHz / 1 = 500MHz */
+#define SCG1_RCCR_DIVCORE_NUM ((0x0) << SCG_CCR_DIVCORE_SHIFT)
+#define SCG1_RCCR_CFG_MASK (SCG_CCR_SCS_MASK | SCG_CCR_DIVBUS_MASK)
+
+/* A7 Plat clck = A7 Core Clock / 2 = 250MHz / 1 = 250MHz */
+#define SCG1_RCCR_DIVBUS_NUM ((0x1) << SCG_CCR_DIVBUS_SHIFT)
+#define SCG1_RCCR_CFG_NUM (SCG1_RCCR_SCS_NUM | SCG1_RCCR_DIVBUS_NUM)
+
+void scg_a7_rccr_init(void)
+{
+ u32 rccr_reg_val = 0;
+
+ rccr_reg_val = readl(&scg1_regs->rccr);
+
+ rccr_reg_val &= (~SCG1_RCCR_CFG_MASK);
+ rccr_reg_val |= (SCG1_RCCR_CFG_NUM);
+
+ writel(rccr_reg_val, &scg1_regs->rccr);
+}
+
+/* POSTDIV2 = 1 */
+#define SCG1_SPLL_CFG_POSTDIV2_NUM ((0x0) << SCG_PLL_CFG_POSTDIV2_SHIFT)
+/* POSTDIV1 = 1 */
+#define SCG1_SPLL_CFG_POSTDIV1_NUM ((0x0) << SCG_PLL_CFG_POSTDIV1_SHIFT)
+
+/* MULT = 22 */
+#define SCG1_SPLL_CFG_MULT_NUM ((22) << SCG_PLL_CFG_MULT_SHIFT)
+
+/* PFD0 output clock selected */
+#define SCG1_SPLL_CFG_PFDSEL_NUM ((0) << SCG_PLL_CFG_PFDSEL_SHIFT)
+/* PREDIV = 1 */
+#define SCG1_SPLL_CFG_PREDIV_NUM ((0x0) << SCG_PLL_CFG_PREDIV_SHIFT)
+/* SPLL output clocks (including PFD outputs) selected */
+#define SCG1_SPLL_CFG_BYPASS_NUM ((0x0) << SCG_PLL_CFG_BYPASS_SHIFT)
+/* SPLL PFD output clock selected */
+#define SCG1_SPLL_CFG_PLLSEL_NUM ((0x1) << SCG_PLL_CFG_PLLSEL_SHIFT)
+/* Clock source is System OSC */
+#define SCG1_SPLL_CFG_CLKSRC_NUM ((0x0) << SCG_PLL_CFG_CLKSRC_SHIFT)
+#define SCG1_SPLL_CFG_NUM_24M_OSC (SCG1_SPLL_CFG_POSTDIV2_NUM | \
+ SCG1_SPLL_CFG_POSTDIV1_NUM | \
+ (22 << SCG_PLL_CFG_MULT_SHIFT) | \
+ SCG1_SPLL_CFG_PFDSEL_NUM | \
+ SCG1_SPLL_CFG_PREDIV_NUM | \
+ SCG1_SPLL_CFG_BYPASS_NUM | \
+ SCG1_SPLL_CFG_PLLSEL_NUM | \
+ SCG1_SPLL_CFG_CLKSRC_NUM)
+/*413Mhz = A7 SPLL(528MHz) * 18/23 */
+#define SCG1_SPLL_PFD0_FRAC_NUM ((23) << SCG_PLL_PFD0_FRAC_SHIFT)
+
+void scg_a7_spll_init(void)
+{
+ u32 val = 0;
+
+ /* Disable A7 System PLL */
+ val = readl(&scg1_regs->spllcsr);
+ val &= ~SCG_SPLL_CSR_SPLLEN_MASK;
+ writel(val, &scg1_regs->spllcsr);
+
+ /*
+ * Per block guide,
+ * "When changing PFD values, it is recommneded PFDx clock
+ * gets gated first by writing a value of 1 to PFDx_CLKGATE register,
+ * then program the new PFD value, then poll the PFDx_VALID
+ * flag to set before writing a value of 0 to PFDx_CLKGATE
+ * to ungate the PFDx clock and allow PFDx clock to run"
+ */
+
+ /* Gate off A7 SPLL PFD0 ~ PDF4 */
+ val = readl(&scg1_regs->spllpfd);
+ val |= (SCG_PLL_PFD3_GATE_MASK |
+ SCG_PLL_PFD2_GATE_MASK |
+ SCG_PLL_PFD1_GATE_MASK |
+ SCG_PLL_PFD0_GATE_MASK);
+ writel(val, &scg1_regs->spllpfd);
+
+ /* ================ A7 SPLL Configuration Start ============== */
+
+ /* Configure A7 System PLL */
+ writel(SCG1_SPLL_CFG_NUM_24M_OSC, &scg1_regs->spllcfg);
+
+ /* Enable A7 System PLL */
+ val = readl(&scg1_regs->spllcsr);
+ val |= SCG_SPLL_CSR_SPLLEN_MASK;
+ writel(val, &scg1_regs->spllcsr);
+
+ /* Wait for A7 SPLL clock ready */
+ while (!(readl(&scg1_regs->spllcsr) & SCG_SPLL_CSR_SPLLVLD_MASK))
+ ;
+
+ /* Configure A7 SPLL PFD0 */
+ val = readl(&scg1_regs->spllpfd);
+ val &= ~SCG_PLL_PFD0_FRAC_MASK;
+ val |= SCG1_SPLL_PFD0_FRAC_NUM;
+ writel(val, &scg1_regs->spllpfd);
+
+ /* Un-gate A7 SPLL PFD0 */
+ val = readl(&scg1_regs->spllpfd);
+ val &= ~SCG_PLL_PFD0_GATE_MASK;
+ writel(val, &scg1_regs->spllpfd);
+
+ /* Wait for A7 SPLL PFD0 clock being valid */
+ while (!(readl(&scg1_regs->spllpfd) & SCG_PLL_PFD0_VALID_MASK))
+ ;
+
+ /* ================ A7 SPLL Configuration End ============== */
+}
+
+/* DDR clock source is APLL PFD0 (396MHz) */
+#define SCG1_DDRCCR_DDRCS_NUM ((0x0) << SCG_DDRCCR_DDRCS_SHIFT)
+/* DDR clock = APLL PFD0 / 1 = 396MHz / 1 = 396MHz */
+#define SCG1_DDRCCR_DDRDIV_NUM ((0x1) << SCG_DDRCCR_DDRDIV_SHIFT)
+/* DDR clock = APLL PFD0 / 2 = 396MHz / 2 = 198MHz */
+#define SCG1_DDRCCR_DDRDIV_LF_NUM ((0x2) << SCG_DDRCCR_DDRDIV_SHIFT)
+#define SCG1_DDRCCR_CFG_NUM (SCG1_DDRCCR_DDRCS_NUM | \
+ SCG1_DDRCCR_DDRDIV_NUM)
+#define SCG1_DDRCCR_CFG_LF_NUM (SCG1_DDRCCR_DDRCS_NUM | \
+ SCG1_DDRCCR_DDRDIV_LF_NUM)
+void scg_a7_ddrclk_init(void)
+{
+ writel(SCG1_DDRCCR_CFG_NUM, &scg1_regs->ddrccr);
+}
+
+/* SCG1(A7) APLLCFG configurations */
+/* divide by 1 <<28 */
+#define SCG1_APLL_CFG_POSTDIV2_NUM ((0x0) << SCG_PLL_CFG_POSTDIV2_SHIFT)
+/* divide by 1 <<24 */
+#define SCG1_APLL_CFG_POSTDIV1_NUM ((0x0) << SCG_PLL_CFG_POSTDIV1_SHIFT)
+/* MULT is 22 <<16 */
+#define SCG1_APLL_CFG_MULT_NUM ((22) << SCG_PLL_CFG_MULT_SHIFT)
+/* PFD0 output clock selected <<14 */
+#define SCG1_APLL_CFG_PFDSEL_NUM ((0) << SCG_PLL_CFG_PFDSEL_SHIFT)
+/* PREDIV = 1 <<8 */
+#define SCG1_APLL_CFG_PREDIV_NUM ((0x0) << SCG_PLL_CFG_PREDIV_SHIFT)
+/* APLL output clocks (including PFD outputs) selected <<2 */
+#define SCG1_APLL_CFG_BYPASS_NUM ((0x0) << SCG_PLL_CFG_BYPASS_SHIFT)
+/* APLL PFD output clock selected <<1 */
+#define SCG1_APLL_CFG_PLLSEL_NUM ((0x0) << SCG_PLL_CFG_PLLSEL_SHIFT)
+/* Clock source is System OSC <<0 */
+#define SCG1_APLL_CFG_CLKSRC_NUM ((0x0) << SCG_PLL_CFG_CLKSRC_SHIFT)
+
+/*
+ * A7 APLL = 24MHz / 1 * 22 / 1 / 1 = 528MHz,
+ * system PLL is sourced from APLL,
+ * APLL clock source is system OSC (24MHz)
+ */
+#define SCG1_APLL_CFG_NUM_24M_OSC (SCG1_APLL_CFG_POSTDIV2_NUM | \
+ SCG1_APLL_CFG_POSTDIV1_NUM | \
+ (22 << SCG_PLL_CFG_MULT_SHIFT) | \
+ SCG1_APLL_CFG_PFDSEL_NUM | \
+ SCG1_APLL_CFG_PREDIV_NUM | \
+ SCG1_APLL_CFG_BYPASS_NUM | \
+ SCG1_APLL_CFG_PLLSEL_NUM | \
+ SCG1_APLL_CFG_CLKSRC_NUM)
+
+/* PFD0 Freq = A7 APLL(528MHz) * 18 / 27 = 352MHz */
+#define SCG1_APLL_PFD0_FRAC_NUM (27)
+
+
+void scg_a7_apll_init(void)
+{
+ u32 val = 0;
+
+ /* Disable A7 Auxiliary PLL */
+ val = readl(&scg1_regs->apllcsr);
+ val &= ~SCG_APLL_CSR_APLLEN_MASK;
+ writel(val, &scg1_regs->apllcsr);
+
+ /* Gate off A7 APLL PFD0 ~ PDF4 */
+ val = readl(&scg1_regs->apllpfd);
+ val |= 0x80808080;
+ writel(val, &scg1_regs->apllpfd);
+
+ /* ================ A7 APLL Configuration Start ============== */
+ /* Configure A7 Auxiliary PLL */
+ writel(SCG1_APLL_CFG_NUM_24M_OSC, &scg1_regs->apllcfg);
+
+ /* Enable A7 Auxiliary PLL */
+ val = readl(&scg1_regs->apllcsr);
+ val |= SCG_APLL_CSR_APLLEN_MASK;
+ writel(val, &scg1_regs->apllcsr);
+
+ /* Wait for A7 APLL clock ready */
+ while (!(readl(&scg1_regs->apllcsr) & SCG_APLL_CSR_APLLVLD_MASK))
+ ;
+
+ /* Configure A7 APLL PFD0 */
+ val = readl(&scg1_regs->apllpfd);
+ val &= ~SCG_PLL_PFD0_FRAC_MASK;
+ val |= SCG1_APLL_PFD0_FRAC_NUM;
+ writel(val, &scg1_regs->apllpfd);
+
+ /* Un-gate A7 APLL PFD0 */
+ val = readl(&scg1_regs->apllpfd);
+ val &= ~SCG_PLL_PFD0_GATE_MASK;
+ writel(val, &scg1_regs->apllpfd);
+
+ /* Wait for A7 APLL PFD0 clock being valid */
+ while (!(readl(&scg1_regs->apllpfd) & SCG_PLL_PFD0_VALID_MASK))
+ ;
+}
+
+/* SCG1(A7) FIRC DIV configurations */
+/* Disable FIRC DIV3 */
+#define SCG1_FIRCDIV_DIV3_NUM ((0x0) << SCG_FIRCDIV_DIV3_SHIFT)
+/* FIRC DIV2 = 48MHz / 1 = 48MHz */
+#define SCG1_FIRCDIV_DIV2_NUM ((0x1) << SCG_FIRCDIV_DIV2_SHIFT)
+/* Disable FIRC DIV1 */
+#define SCG1_FIRCDIV_DIV1_NUM ((0x0) << SCG_FIRCDIV_DIV1_SHIFT)
+
+void scg_a7_firc_init(void)
+{
+ /* Wait for FIRC clock ready */
+ while (!(readl(&scg1_regs->firccsr) & SCG_FIRC_CSR_FIRCVLD_MASK))
+ ;
+
+ /* Configure A7 FIRC DIV1 ~ DIV3 */
+ writel((SCG1_FIRCDIV_DIV3_NUM |
+ SCG1_FIRCDIV_DIV2_NUM |
+ SCG1_FIRCDIV_DIV1_NUM), &scg1_regs->fircdiv);
+}
+
+/* SCG1(A7) NICCCR configurations */
+/* NIC clock source is DDR clock (396/198MHz) */
+#define SCG1_NICCCR_NICCS_NUM ((0x1) << SCG_NICCCR_NICCS_SHIFT)
+
+/* NIC0 clock = DDR Clock / 2 = 396MHz / 2 = 198MHz */
+#define SCG1_NICCCR_NIC0_DIV_NUM ((0x1) << SCG_NICCCR_NIC0_DIV_SHIFT)
+/* NIC0 clock = DDR Clock / 1 = 198MHz / 1 = 198MHz */
+#define SCG1_NICCCR_NIC0_DIV_LF_NUM ((0x0) << SCG_NICCCR_NIC0_DIV_SHIFT)
+/* NIC1 clock = NIC0 Clock / 1 = 198MHz / 2 = 198MHz */
+#define SCG1_NICCCR_NIC1_DIV_NUM ((0x0) << SCG_NICCCR_NIC1_DIV_SHIFT)
+/* NIC1 bus clock = NIC1 Clock / 3 = 198MHz / 3 = 66MHz */
+#define SCG1_NICCCR_NIC1_DIVBUS_NUM ((0x2) << SCG_NICCCR_NIC1_DIVBUS_SHIFT)
+#define SCG1_NICCCR_CFG_NUM (SCG1_NICCCR_NICCS_NUM | \
+ SCG1_NICCCR_NIC0_DIV_NUM | \
+ SCG1_NICCCR_NIC1_DIV_NUM | \
+ SCG1_NICCCR_NIC1_DIVBUS_NUM)
+
+void scg_a7_nicclk_init(void)
+{
+ writel(SCG1_NICCCR_CFG_NUM, &scg1_regs->nicccr);
+}
+
+/* SCG1(A7) FIRC DIV configurations */
+/* Enable FIRC DIV3 */
+#define SCG1_SOSCDIV_DIV3_NUM ((0x1) << SCG_SOSCDIV_DIV3_SHIFT)
+/* FIRC DIV2 = 48MHz / 1 = 48MHz */
+#define SCG1_SOSCDIV_DIV2_NUM ((0x1) << SCG_SOSCDIV_DIV2_SHIFT)
+/* Enable FIRC DIV1 */
+#define SCG1_SOSCDIV_DIV1_NUM ((0x1) << SCG_SOSCDIV_DIV1_SHIFT)
+
+void scg_a7_soscdiv_init(void)
+{
+ /* Wait for FIRC clock ready */
+ while (!(readl(&scg1_regs->sosccsr) & SCG_SOSC_CSR_SOSCVLD_MASK))
+ ;
+
+ /* Configure A7 FIRC DIV1 ~ DIV3 */
+ writel((SCG1_SOSCDIV_DIV3_NUM | SCG1_SOSCDIV_DIV2_NUM |
+ SCG1_SOSCDIV_DIV1_NUM), &scg1_regs->soscdiv);
+}
+
+void scg_a7_sys_clk_sel(enum scg_sys_src clk)
+{
+ u32 rccr_reg_val = 0;
+
+ clk_debug("%s: system clock selected as %s\n", "[SCG]",
+ clk == SCG_SCS_SYS_OSC ? "SYS_OSC" :
+ clk == SCG_SCS_SLOW_IRC ? "SLOW_IRC" :
+ clk == SCG_SCS_FAST_IRC ? "FAST_IRC" :
+ clk == SCG_SCS_RTC_OSC ? "RTC_OSC" :
+ clk == SCG_SCS_AUX_PLL ? "AUX_PLL" :
+ clk == SCG_SCS_SYS_PLL ? "SYS_PLL" :
+ clk == SCG_SCS_USBPHY_PLL ? "USBPHY_PLL" :
+ "Invalid source"
+ );
+
+ rccr_reg_val = readl(&scg1_regs->rccr);
+ rccr_reg_val &= ~SCG_CCR_SCS_MASK;
+ rccr_reg_val |= (clk << SCG_CCR_SCS_SHIFT);
+ writel(rccr_reg_val, &scg1_regs->rccr);
+}
+
+void scg_a7_info(void)
+{
+ debug("SCG Version: 0x%x\n", readl(&scg1_regs->verid));
+ debug("SCG Parameter: 0x%x\n", readl(&scg1_regs->param));
+ debug("SCG RCCR Value: 0x%x\n", readl(&scg1_regs->rccr));
+ debug("SCG Clock Status: 0x%x\n", readl(&scg1_regs->csr));
+}
--- /dev/null
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/hab.h>
+
+static char *get_reset_cause(char *);
+
+#if defined(CONFIG_SECURE_BOOT)
+struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
+ .bank = 29,
+ .word = 6,
+};
+#endif
+
+u32 get_cpu_rev(void)
+{
+ /* Temporally hard code the CPU rev to 0x73, rev 1.0. Fix it later */
+ return (MXC_CPU_MX7ULP << 12) | (1 << 4);
+}
+
+#ifdef CONFIG_REVISION_TAG
+u32 __weak get_board_rev(void)
+{
+ return get_cpu_rev();
+}
+#endif
+
+enum bt_mode get_boot_mode(void)
+{
+ u32 bt0_cfg = 0;
+
+ bt0_cfg = readl(CMC0_RBASE + 0x40);
+ bt0_cfg &= (BT0CFG_LPBOOT_MASK | BT0CFG_DUALBOOT_MASK);
+
+ if (!(bt0_cfg & BT0CFG_LPBOOT_MASK)) {
+ /* No low power boot */
+ if (bt0_cfg & BT0CFG_DUALBOOT_MASK)
+ return DUAL_BOOT;
+ else
+ return SINGLE_BOOT;
+ }
+
+ return LOW_POWER_BOOT;
+}
+
+int arch_cpu_init(void)
+{
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_POSTCLK_INIT
+int board_postclk_init(void)
+{
+ return 0;
+}
+#endif
+
+#define UNLOCK_WORD0 0xC520 /* 1st unlock word */
+#define UNLOCK_WORD1 0xD928 /* 2nd unlock word */
+#define REFRESH_WORD0 0xA602 /* 1st refresh word */
+#define REFRESH_WORD1 0xB480 /* 2nd refresh word */
+
+static void disable_wdog(u32 wdog_base)
+{
+ writel(UNLOCK_WORD0, (wdog_base + 0x04));
+ writel(UNLOCK_WORD1, (wdog_base + 0x04));
+ writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */
+ writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */
+ writel(0x120, (wdog_base + 0x00)); /* Disable it and set update */
+
+ writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */
+ writel(REFRESH_WORD1, (wdog_base + 0x04));
+}
+
+void init_wdog(void)
+{
+ /*
+ * ROM will configure WDOG1, disable it or enable it
+ * depending on FUSE. The update bit is set for reconfigurable.
+ * We have to use unlock sequence to reconfigure it.
+ * WDOG2 is not touched by ROM, so it will have default value
+ * which is enabled. We can directly configure it.
+ * To simplify the codes, we still use same reconfigure
+ * process as WDOG1. Because the update bit is not set for
+ * WDOG2, the unlock sequence won't take effect really.
+ * It actually directly configure the wdog.
+ * In this function, we will disable both WDOG1 and WDOG2,
+ * and set update bit for both. So that kernel can reconfigure them.
+ */
+ disable_wdog(WDG1_RBASE);
+ disable_wdog(WDG2_RBASE);
+}
+
+
+void s_init(void)
+{
+ /* Disable wdog */
+ init_wdog();
+
+ /* clock configuration. */
+ clock_init();
+
+ return;
+}
+
+#ifndef CONFIG_ULP_WATCHDOG
+void reset_cpu(ulong addr)
+{
+ setbits_le32(SIM0_RBASE, SIM_SOPT1_A7_SW_RESET);
+ while (1)
+ ;
+}
+#endif
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+const char *get_imx_type(u32 imxtype)
+{
+ return "7ULP";
+}
+
+int print_cpuinfo(void)
+{
+ u32 cpurev;
+ char cause[18];
+
+ cpurev = get_cpu_rev();
+
+ printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
+ get_imx_type((cpurev & 0xFF000) >> 12),
+ (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0,
+ mxc_get_clock(MXC_ARM_CLK) / 1000000);
+
+ printf("Reset cause: %s\n", get_reset_cause(cause));
+
+ printf("Boot mode: ");
+ switch (get_boot_mode()) {
+ case LOW_POWER_BOOT:
+ printf("Low power boot\n");
+ break;
+ case DUAL_BOOT:
+ printf("Dual boot\n");
+ break;
+ case SINGLE_BOOT:
+ default:
+ printf("Single boot\n");
+ break;
+ }
+
+ return 0;
+}
+#endif
+
+#define CMC_SRS_TAMPER (1 << 31)
+#define CMC_SRS_SECURITY (1 << 30)
+#define CMC_SRS_TZWDG (1 << 29)
+#define CMC_SRS_JTAG_RST (1 << 28)
+#define CMC_SRS_CORE1 (1 << 16)
+#define CMC_SRS_LOCKUP (1 << 15)
+#define CMC_SRS_SW (1 << 14)
+#define CMC_SRS_WDG (1 << 13)
+#define CMC_SRS_PIN_RESET (1 << 8)
+#define CMC_SRS_WARM (1 << 4)
+#define CMC_SRS_HVD (1 << 3)
+#define CMC_SRS_LVD (1 << 2)
+#define CMC_SRS_POR (1 << 1)
+#define CMC_SRS_WUP (1 << 0)
+
+static u32 reset_cause = -1;
+
+static char *get_reset_cause(char *ret)
+{
+ u32 cause1, cause = 0, srs = 0;
+ u32 *reg_ssrs = (u32 *)(SRC_BASE_ADDR + 0x28);
+ u32 *reg_srs = (u32 *)(SRC_BASE_ADDR + 0x20);
+
+ if (!ret)
+ return "null";
+
+ srs = readl(reg_srs);
+ cause1 = readl(reg_ssrs);
+ writel(cause1, reg_ssrs);
+
+ reset_cause = cause1;
+
+ cause = cause1 & (CMC_SRS_POR | CMC_SRS_WUP | CMC_SRS_WARM);
+
+ switch (cause) {
+ case CMC_SRS_POR:
+ sprintf(ret, "%s", "POR");
+ break;
+ case CMC_SRS_WUP:
+ sprintf(ret, "%s", "WUP");
+ break;
+ case CMC_SRS_WARM:
+ cause = cause1 & (CMC_SRS_WDG | CMC_SRS_SW |
+ CMC_SRS_JTAG_RST);
+ switch (cause) {
+ case CMC_SRS_WDG:
+ sprintf(ret, "%s", "WARM-WDG");
+ break;
+ case CMC_SRS_SW:
+ sprintf(ret, "%s", "WARM-SW");
+ break;
+ case CMC_SRS_JTAG_RST:
+ sprintf(ret, "%s", "WARM-JTAG");
+ break;
+ default:
+ sprintf(ret, "%s", "WARM-UNKN");
+ break;
+ }
+ break;
+ default:
+ sprintf(ret, "%s-%X", "UNKN", cause1);
+ break;
+ }
+
+ debug("[%X] SRS[%X] %X - ", cause1, srs, srs^cause1);
+ return ret;
+}
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+__weak int board_mmc_get_env_dev(int devno)
+{
+ return CONFIG_SYS_MMC_ENV_DEV;
+}
+
+int mmc_get_env_dev(void)
+{
+ int devno = 0;
+ u32 bt1_cfg = 0;
+
+ /* If not boot from sd/mmc, use default value */
+ if (get_boot_mode() == LOW_POWER_BOOT)
+ return CONFIG_SYS_MMC_ENV_DEV;
+
+ bt1_cfg = readl(CMC1_RBASE + 0x40);
+ devno = (bt1_cfg >> 9) & 0x7;
+
+ return board_mmc_get_env_dev(devno);
+}
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/mach-imx/rdc-sema.h>
+#include <asm/arch/imx-rdc.h>
+#include <linux/errno.h>
+
+/*
+ * Check if the RDC Semaphore is required for this peripheral.
+ */
+static inline int imx_rdc_check_sema_required(int per_id)
+{
+ struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
+ u32 reg;
+
+ reg = readl(&imx_rdc->pdap[per_id]);
+ /*
+ * No semaphore:
+ * Intial value or this peripheral is assigned to only one domain
+ */
+ if (!(reg & RDC_PDAP_SREQ_MASK))
+ return -ENOENT;
+
+ return 0;
+}
+
+/*
+ * Check the peripheral read / write access permission on Domain [dom_id].
+ */
+int imx_rdc_check_permission(int per_id, int dom_id)
+{
+ struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
+ u32 reg;
+
+ reg = readl(&imx_rdc->pdap[per_id]);
+ if (!(reg & RDC_PDAP_DRW_MASK(dom_id)))
+ return -EACCES; /*No access*/
+
+ return 0;
+}
+
+/*
+ * Lock up the RDC semaphore for this peripheral if semaphore is required.
+ */
+int imx_rdc_sema_lock(int per_id)
+{
+ struct rdc_sema_regs *imx_rdc_sema;
+ int ret;
+ u8 reg;
+
+ ret = imx_rdc_check_sema_required(per_id);
+ if (ret)
+ return ret;
+
+ if (per_id < SEMA_GATES_NUM)
+ imx_rdc_sema = (struct rdc_sema_regs *)SEMAPHORE1_BASE_ADDR;
+ else
+ imx_rdc_sema = (struct rdc_sema_regs *)SEMAPHORE2_BASE_ADDR;
+
+ do {
+ writeb(RDC_SEMA_PROC_ID,
+ &imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
+ reg = readb(&imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
+ if ((reg & RDC_SEMA_GATE_GTFSM_MASK) == RDC_SEMA_PROC_ID)
+ break; /* Get the Semaphore*/
+ } while (1);
+
+ return 0;
+}
+
+/*
+ * Unlock the RDC semaphore for this peripheral if main CPU is the
+ * semaphore owner.
+ */
+int imx_rdc_sema_unlock(int per_id)
+{
+ struct rdc_sema_regs *imx_rdc_sema;
+ int ret;
+ u8 reg;
+
+ ret = imx_rdc_check_sema_required(per_id);
+ if (ret)
+ return ret;
+
+ if (per_id < SEMA_GATES_NUM)
+ imx_rdc_sema = (struct rdc_sema_regs *)SEMAPHORE1_BASE_ADDR;
+ else
+ imx_rdc_sema = (struct rdc_sema_regs *)SEMAPHORE2_BASE_ADDR;
+
+ reg = readb(&imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
+ if ((reg & RDC_SEMA_GATE_GTFSM_MASK) != RDC_SEMA_PROC_ID)
+ return -EACCES; /*Not the semaphore owner */
+
+ writeb(0x0, &imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
+
+ return 0;
+}
+
+/*
+ * Setup RDC setting for one peripheral
+ */
+int imx_rdc_setup_peri(rdc_peri_cfg_t p)
+{
+ struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
+ u32 reg = 0;
+ u32 share_count = 0;
+ u32 peri_id = p & RDC_PERI_MASK;
+ u32 domain = (p & RDC_DOMAIN_MASK) >> RDC_DOMAIN_SHIFT_BASE;
+
+ /* No domain assigned */
+ if (domain == 0)
+ return -EINVAL;
+
+ reg |= domain;
+
+ share_count = (domain & 0x3)
+ + ((domain >> 2) & 0x3)
+ + ((domain >> 4) & 0x3)
+ + ((domain >> 6) & 0x3);
+
+ if (share_count > 0x3)
+ reg |= RDC_PDAP_SREQ_MASK;
+
+ writel(reg, &imx_rdc->pdap[peri_id]);
+
+ return 0;
+}
+
+/*
+ * Setup RDC settings for multiple peripherals
+ */
+int imx_rdc_setup_peripherals(rdc_peri_cfg_t const *peripherals_list,
+ unsigned count)
+{
+ rdc_peri_cfg_t const *p = peripherals_list;
+ int i, ret;
+
+ for (i = 0; i < count; i++) {
+ ret = imx_rdc_setup_peri(*p);
+ if (ret)
+ return ret;
+ p++;
+ }
+
+ return 0;
+}
+
+/*
+ * Setup RDC setting for one master
+ */
+int imx_rdc_setup_ma(rdc_ma_cfg_t p)
+{
+ struct rdc_regs *imx_rdc = (struct rdc_regs *)RDC_BASE_ADDR;
+ u32 master_id = (p & RDC_MASTER_MASK) >> RDC_MASTER_SHIFT;
+ u32 domain = (p & RDC_DOMAIN_MASK) >> RDC_DOMAIN_SHIFT_BASE;
+
+ writel((domain & RDC_MDA_DID_MASK), &imx_rdc->mda[master_id]);
+
+ return 0;
+}
+
+/*
+ * Setup RDC settings for multiple masters
+ */
+int imx_rdc_setup_masters(rdc_ma_cfg_t const *masters_list, unsigned count)
+{
+ rdc_ma_cfg_t const *p = masters_list;
+ int i, ret;
+
+ for (i = 0; i < count; i++) {
+ ret = imx_rdc_setup_ma(*p);
+ if (ret)
+ return ret;
+ p++;
+ }
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/arch/iomux.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+
+int setup_sata(void)
+{
+ struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ int ret;
+
+ if (!is_mx6dq() && !is_mx6dqp())
+ return 1;
+
+ ret = enable_sata_clock();
+ if (ret)
+ return ret;
+
+ clrsetbits_le32(&iomuxc_regs->gpr[13],
+ IOMUXC_GPR13_SATA_MASK,
+ IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
+ |IOMUXC_GPR13_SATA_PHY_7_SATA2M
+ |IOMUXC_GPR13_SATA_SPEED_3G
+ |(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
+ |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
+ |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
+ |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
+ |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
+ |IOMUXC_GPR13_SATA_PHY_1_SLOW);
+
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+
+#ifdef CONFIG_FSL_ESDHC
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
+int get_clocks(void)
+{
+#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_USDHC
+#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC4_BASE_ADDR
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+#else
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+#endif
+#else
+#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC4_BASE_ADDR
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+#else
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+#endif
+#endif
+#endif
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * Author: Tim Harvey <tharvey@gateworks.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/spl.h>
+#include <spl.h>
+#include <asm/mach-imx/hab.h>
+
+#if defined(CONFIG_MX6)
+/* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 register */
+u32 spl_boot_device(void)
+{
+ unsigned int bmode = readl(&src_base->sbmr2);
+ u32 reg = imx6_src_get_boot_mode();
+
+ /*
+ * Check for BMODE if serial downloader is enabled
+ * BOOT_MODE - see IMX6DQRM Table 8-1
+ */
+ if (((bmode >> 24) & 0x03) == 0x01) /* Serial Downloader */
+ return BOOT_DEVICE_UART;
+
+ /* BOOT_CFG1[7:4] - see IMX6DQRM Table 8-8 */
+ switch ((reg & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
+ /* EIM: See 8.5.1, Table 8-9 */
+ case IMX6_BMODE_EMI:
+ /* BOOT_CFG1[3]: NOR/OneNAND Selection */
+ switch ((reg & IMX6_BMODE_EMI_MASK) >> IMX6_BMODE_EMI_SHIFT) {
+ case IMX6_BMODE_ONENAND:
+ return BOOT_DEVICE_ONENAND;
+ case IMX6_BMODE_NOR:
+ return BOOT_DEVICE_NOR;
+ break;
+ }
+ /* Reserved: Used to force Serial Downloader */
+ case IMX6_BMODE_UART:
+ return BOOT_DEVICE_UART;
+ /* SATA: See 8.5.4, Table 8-20 */
+ case IMX6_BMODE_SATA:
+ return BOOT_DEVICE_SATA;
+ /* Serial ROM: See 8.5.5.1, Table 8-22 */
+ case IMX6_BMODE_SERIAL_ROM:
+ /* BOOT_CFG4[2:0] */
+ switch ((reg & IMX6_BMODE_SERIAL_ROM_MASK) >>
+ IMX6_BMODE_SERIAL_ROM_SHIFT) {
+ case IMX6_BMODE_ECSPI1:
+ case IMX6_BMODE_ECSPI2:
+ case IMX6_BMODE_ECSPI3:
+ case IMX6_BMODE_ECSPI4:
+ case IMX6_BMODE_ECSPI5:
+ return BOOT_DEVICE_SPI;
+ case IMX6_BMODE_I2C1:
+ case IMX6_BMODE_I2C2:
+ case IMX6_BMODE_I2C3:
+ return BOOT_DEVICE_I2C;
+ }
+ break;
+ /* SD/eSD: 8.5.3, Table 8-15 */
+ case IMX6_BMODE_SD:
+ case IMX6_BMODE_ESD:
+ return BOOT_DEVICE_MMC1;
+ /* MMC/eMMC: 8.5.3 */
+ case IMX6_BMODE_MMC:
+ case IMX6_BMODE_EMMC:
+ return BOOT_DEVICE_MMC1;
+ /* NAND Flash: 8.5.2, Table 8-10 */
+ case IMX6_BMODE_NAND:
+ return BOOT_DEVICE_NAND;
+ }
+ return BOOT_DEVICE_NONE;
+}
+#endif
+
+#if defined(CONFIG_SPL_MMC_SUPPORT)
+/* called from spl_mmc to see type of boot mode for storage (RAW or FAT) */
+u32 spl_boot_mode(const u32 boot_device)
+{
+ switch (spl_boot_device()) {
+ /* for MMC return either RAW or FAT mode */
+ case BOOT_DEVICE_MMC1:
+ case BOOT_DEVICE_MMC2:
+#if defined(CONFIG_SPL_FAT_SUPPORT)
+ return MMCSD_MODE_FS;
+#elif defined(CONFIG_SUPPORT_EMMC_BOOT)
+ return MMCSD_MODE_EMMCBOOT;
+#else
+ return MMCSD_MODE_RAW;
+#endif
+ break;
+ default:
+ puts("spl: ERROR: unsupported device\n");
+ hang();
+ }
+}
+#endif
+
+#if defined(CONFIG_SECURE_BOOT)
+
+__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+{
+ typedef void __noreturn (*image_entry_noargs_t)(void);
+
+ image_entry_noargs_t image_entry =
+ (image_entry_noargs_t)(unsigned long)spl_image->entry_point;
+
+ debug("image entry point: 0x%lX\n", spl_image->entry_point);
+
+ /* HAB looks for the CSF at the end of the authenticated data therefore,
+ * we need to subtract the size of the CSF from the actual filesize */
+ if (authenticate_image(spl_image->load_addr,
+ spl_image->size - CONFIG_CSF_SIZE)) {
+ image_entry();
+ } else {
+ puts("spl: ERROR: image authentication unsuccessful\n");
+ hang();
+ }
+}
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+IMAGE_VERSION 2
+BOOT_FROM sd
+
+/*
+ * Secure boot support
+ */
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
\ No newline at end of file
--- /dev/null
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * The file use ls102xa/timer.c as a reference.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <div64.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/syscounter.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * This function is intended for SHORT delays only.
+ * It will overflow at around 10 seconds @ 400MHz,
+ * or 20 seconds @ 200MHz.
+ */
+unsigned long usec2ticks(unsigned long usec)
+{
+ ulong ticks;
+
+ if (usec < 1000)
+ ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000;
+ else
+ ticks = ((usec / 10) * (get_tbclk() / 100000));
+
+ return ticks;
+}
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+ unsigned long freq;
+
+ asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
+
+ tick *= CONFIG_SYS_HZ;
+ do_div(tick, freq);
+
+ return tick;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long usec)
+{
+ unsigned long freq;
+
+ asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
+
+ usec = usec * freq + 999999;
+ do_div(usec, 1000000);
+
+ return usec;
+}
+
+int timer_init(void)
+{
+ struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR;
+ unsigned long val, freq;
+
+ freq = CONFIG_SC_TIMER_CLK;
+ asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
+
+ writel(freq, &sctr->cntfid0);
+
+ /* Enable system counter */
+ val = readl(&sctr->cntcr);
+ val &= ~(SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1);
+ val |= SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG;
+ writel(val, &sctr->cntcr);
+
+ gd->arch.tbl = 0;
+ gd->arch.tbu = 0;
+
+ return 0;
+}
+
+unsigned long long get_ticks(void)
+{
+ unsigned long long now;
+
+ asm("mrrc p15, 0, %Q0, %R0, c14" : "=r" (now));
+
+ gd->arch.tbl = (unsigned long)(now & 0xffffffff);
+ gd->arch.tbu = (unsigned long)(now >> 32);
+
+ return now;
+}
+
+ulong get_timer_masked(void)
+{
+ return tick_to_time(get_ticks());
+}
+
+ulong get_timer(ulong base)
+{
+ return get_timer_masked() - base;
+}
+
+void __udelay(unsigned long usec)
+{
+ unsigned long long tmp;
+ ulong tmo;
+
+ tmo = us_to_tick(usec);
+ tmp = get_ticks() + tmo; /* get current timestamp */
+
+ while (get_ticks() < tmp) /* loop till event */
+ /*NOP*/;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ unsigned long freq;
+
+ asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
+
+ return freq;
+}
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <div64.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+
+/* General purpose timers registers */
+struct mxc_gpt {
+ unsigned int control;
+ unsigned int prescaler;
+ unsigned int status;
+ unsigned int nouse[6];
+ unsigned int counter;
+};
+
+static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
+
+/* General purpose timers bitfields */
+#define GPTCR_SWR (1 << 15) /* Software reset */
+#define GPTCR_24MEN (1 << 10) /* Enable 24MHz clock input */
+#define GPTCR_FRR (1 << 9) /* Freerun / restart */
+#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source 32khz */
+#define GPTCR_CLKSOURCE_OSC (5 << 6) /* Clock source OSC */
+#define GPTCR_CLKSOURCE_PRE (1 << 6) /* Clock source PRECLK */
+#define GPTCR_CLKSOURCE_MASK (0x7 << 6)
+#define GPTCR_TEN 1 /* Timer enable */
+
+#define GPTPR_PRESCALER24M_SHIFT 12
+#define GPTPR_PRESCALER24M_MASK (0xF << GPTPR_PRESCALER24M_SHIFT)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static inline int gpt_has_clk_source_osc(void)
+{
+#if defined(CONFIG_MX6)
+ if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) ||
+ is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul() ||
+ is_mx6ull() || is_mx6sll())
+ return 1;
+
+ return 0;
+#else
+ return 0;
+#endif
+}
+
+static inline ulong gpt_get_clk(void)
+{
+#ifdef CONFIG_MXC_GPT_HCLK
+ if (gpt_has_clk_source_osc())
+ return MXC_HCLK >> 3;
+ else
+ return mxc_get_clock(MXC_IPG_PERCLK);
+#else
+ return MXC_CLK32;
+#endif
+}
+
+int timer_init(void)
+{
+ int i;
+
+ /* setup GP Timer 1 */
+ __raw_writel(GPTCR_SWR, &cur_gpt->control);
+
+ /* We have no udelay by now */
+ for (i = 0; i < 100; i++)
+ __raw_writel(0, &cur_gpt->control);
+
+ i = __raw_readl(&cur_gpt->control);
+ i &= ~GPTCR_CLKSOURCE_MASK;
+
+#ifdef CONFIG_MXC_GPT_HCLK
+ if (gpt_has_clk_source_osc()) {
+ i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
+
+ /*
+ * For DL/S, SX, UL, ULL, SLL set 24Mhz OSC
+ * Enable bit and prescaler
+ */
+ if (is_mx6sdl() || is_mx6sx() || is_mx6ul() || is_mx6ull() ||
+ is_mx6sll()) {
+ i |= GPTCR_24MEN;
+
+ /* Produce 3Mhz clock */
+ __raw_writel((7 << GPTPR_PRESCALER24M_SHIFT),
+ &cur_gpt->prescaler);
+ }
+ } else {
+ i |= GPTCR_CLKSOURCE_PRE | GPTCR_TEN;
+ }
+#else
+ __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */
+ i |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
+#endif
+ __raw_writel(i, &cur_gpt->control);
+
+ return 0;
+}
+
+unsigned long timer_read_counter(void)
+{
+ return __raw_readl(&cur_gpt->counter); /* current tick value */
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ return gpt_get_clk();
+}
+
+/*
+ * This function is intended for SHORT delays only.
+ * It will overflow at around 10 seconds @ 400MHz,
+ * or 20 seconds @ 200MHz.
+ */
+unsigned long usec2ticks(unsigned long _usec)
+{
+ unsigned long long usec = _usec;
+
+ usec *= get_tbclk();
+ usec += 999999;
+ do_div(usec, 1000000);
+
+ return usec;
+}
--- /dev/null
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/errno.h>
+#include <asm/mach-imx/video.h>
+
+int board_video_skip(void)
+{
+ int i;
+ int ret;
+ char const *panel = getenv("panel");
+
+ if (!panel) {
+ for (i = 0; i < display_count; i++) {
+ struct display_info_t const *dev = displays+i;
+ if (dev->detect && dev->detect(dev)) {
+ panel = dev->mode.name;
+ printf("auto-detected panel %s\n", panel);
+ break;
+ }
+ }
+ if (!panel) {
+ panel = displays[0].mode.name;
+ printf("No panel detected: default to %s\n", panel);
+ i = 0;
+ }
+ } else {
+ for (i = 0; i < display_count; i++) {
+ if (!strcmp(panel, displays[i].mode.name))
+ break;
+ }
+ }
+
+ if (i < display_count) {
+ ret = ipuv3_fb_init(&displays[i].mode, displays[i].di ? 1 : 0,
+ displays[i].pixfmt);
+ if (!ret) {
+ if (displays[i].enable)
+ displays[i].enable(displays + i);
+
+ printf("Display: %s (%ux%u)\n",
+ displays[i].mode.name,
+ displays[i].mode.xres,
+ displays[i].mode.yres);
+ } else
+ printf("LCD %s cannot be configured: %d\n",
+ displays[i].mode.name, ret);
+ } else {
+ printf("unsupported panel %s\n", panel);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_IMX_HDMI
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/io.h>
+int detect_hdmi(struct display_info_t const *dev)
+{
+ struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
+ return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT;
+}
+#endif
config ARCH_INTEGRATOR_CP
bool "Support Integrator/CP platform"
select ARCH_CINTEGRATOR
+ imply ENV_IS_IN_FLASH
endchoice
config ARCH_CINTEGRATOR
bool
+ imply ENV_IS_IN_FLASH
choice
prompt "Integrator core module select"
u32 addr, dpsc_base = 0x1E80000, freq, load_addr, size;
int rcode = 0;
struct image_header *header;
+ u32 ecrypt_bm_addr = 0;
if (argc < 2)
return CMD_RET_USAGE;
memcpy((void *)load_addr, (void *)(addr + sizeof(struct image_header)),
size);
- rcode = mon_install(load_addr, dpsc_base, freq);
+ if (argc >= 3)
+ ecrypt_bm_addr = simple_strtoul(argv[2], NULL, 16);
+
+ rcode = mon_install(load_addr, dpsc_base, freq, ecrypt_bm_addr);
printf("## installed monitor @ 0x%x, freq [%d], status %d\n",
load_addr, freq, rcode);
return 0;
}
-U_BOOT_CMD(mon_install, 2, 0, do_mon_install,
+U_BOOT_CMD(mon_install, 3, 0, do_mon_install,
"Install boot kernel at 'addr'",
""
);
#ifndef _MACH_MON_H_
#define _MACH_MON_H_
-int mon_install(u32 addr, u32 dpsc, u32 freq);
+int mon_install(u32 addr, u32 dpsc, u32 freq, u32 bm_addr);
int mon_power_on(int core_id, void *ep);
int mon_power_off(int core_id);
#include <spl.h>
asm(".arch_extension sec\n\t");
-int mon_install(u32 addr, u32 dpsc, u32 freq)
+int mon_install(u32 addr, u32 dpsc, u32 freq, u32 bm_addr)
{
int result;
"mov r0, %1\n"
"mov r1, %2\n"
"mov r2, %3\n"
+ "mov r3, %4\n"
"blx r0\n"
+ "mov %0, r0\n"
"ldmfd r13!, {lr}\n"
: "=&r" (result)
- : "r" (addr), "r" (dpsc), "r" (freq)
- : "cc", "r0", "r1", "r2", "memory");
+ : "r" (addr), "r" (dpsc), "r" (freq), "r" (bm_addr)
+ : "cc", "r0", "r1", "r2", "r3", "memory");
return result;
}
"mov r2, %2\n"
"mov r0, #0\n"
"smc #0\n"
+ "mov %0, r0\n"
"ldmfd r13!, {lr}\n"
: "=&r" (result)
: "r" (core_id), "r" (ep)
"mov r1, %1\n"
"mov r0, #1\n"
"smc #1\n"
+ "mov %0, r0\n"
"ldmfd r13!, {lr}\n"
: "=&r" (result)
: "r" (core_id)
"mov r0, %1\n"
"mov r1, %2\n"
"smc #2\n"
+ "mov %0, r0\n"
"ldmfd r13!, {r4-r12, lr}\n"
: "=&r" (result)
: "r" (cmd), "r" (arg1)
int dram_init_banksize(void)
{
/* Reserve first 16 MiB of RAM for firmware */
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE + (16 * 1024 * 1024);
- gd->bd->bi_dram[0].size = gd->ram_size - (16 * 1024 * 1024);
-
+ gd->bd->bi_dram[0].start = 0x1000000;
+ gd->bd->bi_dram[0].size = 0xf000000;
+ /* Reserve 2 MiB for ARM Trusted Firmware (BL31) */
+ gd->bd->bi_dram[1].start = 0x10000000;
+ gd->bd->bi_dram[1].size = gd->ram_size - 0x10200000;
return 0;
}
config ARMADA_XP
bool
select ARMADA_32BIT
+ imply ENV_IS_IN_SPI_FLASH
# ARMv8 SoCs...
config ARMADA_3700
bool "Support DB-88F6820-AMC"
select 88F6820
+config TARGET_TURRIS_OMNIA
+ bool "Support Turris Omnia"
+ select 88F6820
+
config TARGET_MVEBU_ARMADA_8K
bool "Support Armada 7k/8k platforms"
select ARMADA_8K
default "db-88f6720" if TARGET_DB_88F6720
default "db-88f6820-gp" if TARGET_DB_88F6820_GP
default "db-88f6820-amc" if TARGET_DB_88F6820_AMC
+ default "turris_omnia" if TARGET_TURRIS_OMNIA
default "mvebu_armada-8k" if TARGET_MVEBU_ARMADA_8K
default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
default "ds414" if TARGET_DS414
default "ds414" if TARGET_DS414
default "maxbcm" if TARGET_MAXBCM
default "theadorable" if TARGET_THEADORABLE
+ default "turris_omnia" if TARGET_TURRIS_OMNIA
config SYS_VENDOR
default "Marvell" if TARGET_DB_MV784MP_GP
default "Marvell" if TARGET_MVEBU_ARMADA_8K
default "solidrun" if TARGET_CLEARFOG
default "Synology" if TARGET_DS414
+ default "CZ.NIC" if TARGET_TURRIS_OMNIA
config SYS_SOC
default "mvebu"
+if TARGET_TURRIS_OMNIA
+
+choice
+ prompt "Turris Omnia boot method"
+
+config TURRIS_OMNIA_SPL_BOOT_DEVICE_SPI
+ bool "SPI NOR flash"
+
+config TURRIS_OMNIA_SPL_BOOT_DEVICE_MMC
+ bool "SDIO/MMC card"
+
+endchoice
+
+endif
+
config MVEBU_EFUSE
bool "Enable eFuse support"
default n
authenticated) and the code. See the doc/README.ti-secure
file for further details.
+config TI_SECURE_EMIF_REGION_START
+ hex "Reserved EMIF region start address"
+ depends on TI_SECURE_DEVICE
+ default 0x0
+ help
+ Reserved EMIF region start address. Set to "0" to auto-select
+ to be at the end of the external memory region.
+
+config TI_SECURE_EMIF_TOTAL_REGION_SIZE
+ hex "Reserved EMIF region size"
+ depends on TI_SECURE_DEVICE
+ default 0x0
+ help
+ Total reserved EMIF region size. Default is 0, which means no reserved EMIF
+ region on secure devices.
+
+config TI_SECURE_EMIF_PROTECTED_REGION_SIZE
+ hex "Size of protected region within reserved EMIF region"
+ depends on TI_SECURE_DEVICE
+ default 0x0
+ help
+ This config option is used to specify the size of the portion of the total
+ reserved EMIF region set aside for secure OS needs that will be protected
+ using hardware memory firewalls. This value must be smaller than the
+ TI_SECURE_EMIF_TOTAL_REGION_SIZE value.
+
source "arch/arm/mach-omap2/omap3/Kconfig"
source "arch/arm/mach-omap2/omap4/Kconfig"
obj-y += mem-common.o
+obj-y += fdt-common.o
+
obj-$(CONFIG_TI_SECURE_DEVICE) += sec-common.o
obj-y += mux.o
obj-y += prcm-regs.o
obj-y += hw_data.o
+obj-y += fdt.o
obj-$(CONFIG_CLOCK_SYNTHESIZER) += clk_synthesizer.o
.board_data = &otg1_board_data,
};
#endif
-#endif
int arch_misc_init(void)
{
-#ifndef CONFIG_DM_USB
#ifdef CONFIG_AM335X_USB0
musb_register(&otg0_plat, &otg0_board_data,
(void *)USB0_OTG_BASE);
musb_register(&otg1_plat, &otg1_board_data,
(void *)USB1_OTG_BASE);
#endif
-#else
+ return 0;
+}
+
+#else /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
+
+int arch_misc_init(void)
+{
struct udevice *dev;
int ret;
return ret;
}
#endif
-#endif
+
return 0;
}
+#endif /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
+
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
/*
* In the case of non-SPL based booting we'll want to call these
writel(PRCM_MOD_EN, &cmalwon->gpio0clkctrl);
while (readl(&cmalwon->gpio0clkctrl) != PRCM_MOD_EN)
;
- writel((BIT(8)), &cmalwon->gpio0clkctrl);
+ writel((BIT(1) | BIT(8)), &cmalwon->gpio0clkctrl);
+
+ /* Enable gpio1 */
+ writel(PRCM_MOD_EN, &cmalwon->gpio1clkctrl);
+ while (readl(&cmalwon->gpio1clkctrl) != PRCM_MOD_EN)
+ ;
+ writel((BIT(1) | BIT(8)), &cmalwon->gpio1clkctrl);
/* Enable spi */
writel(PRCM_MOD_EN, &cmalwon->spiclkctrl);
--- /dev/null
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <malloc.h>
+
+#include <asm/omap_common.h>
+#include <asm/arch-am33xx/sys_proto.h>
+
+#ifdef CONFIG_TI_SECURE_DEVICE
+
+static void ft_hs_fixups(void *fdt, bd_t *bd)
+{
+ /* Check we are running on an HS/EMU device type */
+ if (GP_DEVICE != get_device_type()) {
+ if ((ft_hs_disable_rng(fdt, bd) == 0) &&
+ (ft_hs_fixup_dram(fdt, bd) == 0) &&
+ (ft_hs_add_tee(fdt, bd) == 0))
+ return;
+ } else {
+ printf("ERROR: Incorrect device type (GP) detected!");
+ }
+ /* Fixup failed or wrong device type */
+ hang();
+}
+#else
+static void ft_hs_fixups(void *fdt, bd_t *bd) { }
+#endif /* #ifdef CONFIG_TI_SECURE_DEVICE */
+
+/*
+ * Place for general cpu/SoC FDT fixups. Board specific
+ * fixups should remain in the board files which is where
+ * this function should be called from.
+ */
+void ft_cpu_setup(void *fdt, bd_t *bd)
+{
+ ft_hs_fixups(fdt, bd);
+}
--- /dev/null
+/*
+ * Copyright 2016-2017 Texas Instruments, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+#include <asm/omap_common.h>
+#include <asm/omap_sec_common.h>
+
+#ifdef CONFIG_TI_SECURE_DEVICE
+
+/* Give zero values if not already defined */
+#ifndef TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ
+#define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ (0)
+#endif
+#ifndef CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ
+#define CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ (0)
+#endif
+
+int ft_hs_disable_rng(void *fdt, bd_t *bd)
+{
+ const char *path;
+ int offs;
+ int ret;
+
+ /* Make HW RNG reserved for secure world use */
+ path = "/ocp/rng";
+ offs = fdt_path_offset(fdt, path);
+ if (offs < 0) {
+ debug("Node %s not found.\n", path);
+ return 0;
+ }
+ ret = fdt_setprop_string(fdt, offs,
+ "status", "disabled");
+ if (ret < 0) {
+ printf("Could not add status property to node %s: %s\n",
+ path, fdt_strerror(ret));
+ return ret;
+ }
+ return 0;
+}
+
+#if (CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE != 0)
+/*
+ * fdt_pack_reg - pack address and size array into the "reg"-suitable stream
+ */
+static int fdt_pack_reg(const void *fdt, void *buf, u64 address, u64 size)
+{
+ int address_cells = fdt_address_cells(fdt, 0);
+ int size_cells = fdt_size_cells(fdt, 0);
+ char *p = buf;
+
+ if (address_cells == 2)
+ *(fdt64_t *)p = cpu_to_fdt64(address);
+ else
+ *(fdt32_t *)p = cpu_to_fdt32(address);
+ p += 4 * address_cells;
+
+ if (size_cells == 2)
+ *(fdt64_t *)p = cpu_to_fdt64(size);
+ else
+ *(fdt32_t *)p = cpu_to_fdt32(size);
+ p += 4 * size_cells;
+
+ return p - (char *)buf;
+}
+
+int ft_hs_fixup_dram(void *fdt, bd_t *bd)
+{
+ const char *path, *subpath;
+ int offs, len;
+ u32 sec_mem_start = get_sec_mem_start();
+ u32 sec_mem_size = CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE;
+ fdt32_t address_cells = cpu_to_fdt32(fdt_address_cells(fdt, 0));
+ fdt32_t size_cells = cpu_to_fdt32(fdt_size_cells(fdt, 0));
+ u8 temp[16]; /* Up to 64-bit address + 64-bit size */
+
+ /* Delete any original secure_reserved node */
+ path = "/reserved-memory/secure_reserved";
+ offs = fdt_path_offset(fdt, path);
+ if (offs >= 0)
+ fdt_del_node(fdt, offs);
+
+ /* Add new secure_reserved node */
+ path = "/reserved-memory";
+ offs = fdt_path_offset(fdt, path);
+ if (offs < 0) {
+ debug("Node %s not found\n", path);
+ path = "/";
+ subpath = "reserved-memory";
+ offs = fdt_path_offset(fdt, path);
+ offs = fdt_add_subnode(fdt, offs, subpath);
+ if (offs < 0) {
+ printf("Could not create %s%s node.\n", path, subpath);
+ return 1;
+ }
+ path = "/reserved-memory";
+ offs = fdt_path_offset(fdt, path);
+
+ fdt_setprop(fdt, offs, "#address-cells", &address_cells, sizeof(address_cells));
+ fdt_setprop(fdt, offs, "#size-cells", &size_cells, sizeof(size_cells));
+ fdt_setprop(fdt, offs, "ranges", NULL, 0);
+ }
+
+ subpath = "secure_reserved";
+ offs = fdt_add_subnode(fdt, offs, subpath);
+ if (offs < 0) {
+ printf("Could not create %s%s node.\n", path, subpath);
+ return 1;
+ }
+
+ fdt_setprop_string(fdt, offs, "compatible", "ti,secure-memory");
+ fdt_setprop_string(fdt, offs, "status", "okay");
+ fdt_setprop(fdt, offs, "no-map", NULL, 0);
+ len = fdt_pack_reg(fdt, temp, sec_mem_start, sec_mem_size);
+ fdt_setprop(fdt, offs, "reg", temp, len);
+
+ return 0;
+}
+#else
+int ft_hs_fixup_dram(void *fdt, bd_t *bd) { return 0; }
+#endif
+
+int ft_hs_add_tee(void *fdt, bd_t *bd)
+{
+ const char *path, *subpath;
+ int offs;
+
+ extern int tee_loaded;
+ if (!tee_loaded)
+ return 0;
+
+ path = "/firmware";
+ offs = fdt_path_offset(fdt, path);
+ if (offs < 0) {
+ path = "/";
+ offs = fdt_path_offset(fdt, path);
+ if (offs < 0) {
+ printf("Could not find root node.\n");
+ return 1;
+ }
+
+ subpath = "firmware";
+ offs = fdt_add_subnode(fdt, offs, subpath);
+ if (offs < 0) {
+ printf("Could not create %s node.\n", subpath);
+ return 1;
+ }
+ }
+
+ subpath = "optee";
+ offs = fdt_add_subnode(fdt, offs, subpath);
+ if (offs < 0) {
+ printf("Could not create %s node.\n", subpath);
+ return 1;
+ }
+
+ fdt_setprop_string(fdt, offs, "compatible", "linaro,optee-tz");
+ fdt_setprop_string(fdt, offs, "method", "smc");
+
+ return 0;
+}
+
+#endif
{
early_system_init();
mem_init();
+ /*
+ * Save the boot parameters passed from romcode.
+ * We cannot delay the saving further than this,
+ * to prevent overwrites.
+ */
+ save_omap_boot_params();
}
#endif
config SYS_SOC
default "omap5"
-config TI_SECURE_EMIF_REGION_START
- hex "Reserved EMIF region start address"
- depends on TI_SECURE_DEVICE
- default 0x0
- help
- Reserved EMIF region start address. Set to "0" to auto-select
- to be at the end of the external memory region.
-
-config TI_SECURE_EMIF_TOTAL_REGION_SIZE
- hex "Reserved EMIF region size"
- depends on TI_SECURE_DEVICE
- default 0x0
- help
- Total reserved EMIF region size. Default is 0, which means no reserved EMIF
- region on secure devices.
-
-config TI_SECURE_EMIF_PROTECTED_REGION_SIZE
- hex "Size of protected region within reserved EMIF region"
- depends on TI_SECURE_DEVICE
- default 0x0
- help
- This config option is used to specify the size of the portion of the total
- reserved EMIF region set aside for secure OS needs that will be protected
- using hardware memory firewalls. This value must be smaller than the
- TI_SECURE_EMIF_TOTAL_REGION_SIZE value.
-
config OMAP_PLATFORM_RESET_TIME_MAX_USEC
int "Something"
range 0 31219
obj-y += abb.o
obj-y += fdt.o
obj-$(CONFIG_IODELAY_RECALIBRATION) += dra7xx_iodelay.o
-obj-$(CONFIG_TI_SECURE_DEVICE) += sec-fxns.o
obj-$(CONFIG_DRA7XX) += sec_entry_cpu1.o
return 0;
}
-static int ft_hs_disable_rng(void *fdt, bd_t *bd)
-{
- const char *path;
- int offs;
- int ret;
-
- /* Make HW RNG reserved for secure world use */
- path = "/ocp/rng";
- offs = fdt_path_offset(fdt, path);
- if (offs < 0) {
- debug("Node %s not found.\n", path);
- return 0;
- }
- ret = fdt_setprop_string(fdt, offs,
- "status", "disabled");
- if (ret < 0) {
- printf("Could not add status property to node %s: %s\n",
- path, fdt_strerror(ret));
- return ret;
- }
- return 0;
-}
-
#if ((TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ != 0) || \
(CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ != 0))
static int ft_hs_fixup_sram(void *fdt, bd_t *bd)
static int ft_hs_fixup_sram(void *fdt, bd_t *bd) { return 0; }
#endif
-#if (CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE != 0)
-static int ft_hs_fixup_dram(void *fdt, bd_t *bd)
-{
- const char *path, *subpath;
- int offs;
- u32 sec_mem_start = CONFIG_TI_SECURE_EMIF_REGION_START;
- u32 sec_mem_size = CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE;
- fdt64_t temp[2];
- fdt32_t two;
-
- /* If start address is zero, place at end of DRAM */
- if (0 == sec_mem_start)
- sec_mem_start =
- (CONFIG_SYS_SDRAM_BASE +
- (omap_sdram_size() - sec_mem_size));
-
- /* Delete any original secure_reserved node */
- path = "/reserved-memory/secure_reserved";
- offs = fdt_path_offset(fdt, path);
- if (offs >= 0)
- fdt_del_node(fdt, offs);
-
- /* Add new secure_reserved node */
- path = "/reserved-memory";
- offs = fdt_path_offset(fdt, path);
- if (offs < 0) {
- debug("Node %s not found\n", path);
- path = "/";
- subpath = "reserved-memory";
- offs = fdt_path_offset(fdt, path);
- offs = fdt_add_subnode(fdt, offs, subpath);
- if (offs < 0) {
- printf("Could not create %s%s node.\n", path, subpath);
- return 1;
- }
- path = "/reserved-memory";
- offs = fdt_path_offset(fdt, path);
- two = cpu_to_fdt32(2);
- fdt_setprop(fdt, offs, "#address-cells", &two, sizeof(two));
- fdt_setprop(fdt, offs, "#size-cells", &two, sizeof(two));
- fdt_setprop(fdt, offs, "ranges", NULL, 0);
- }
-
- subpath = "secure_reserved";
- offs = fdt_add_subnode(fdt, offs, subpath);
- if (offs < 0) {
- printf("Could not create %s%s node.\n", path, subpath);
- return 1;
- }
-
- temp[0] = cpu_to_fdt64(((u64)sec_mem_start));
- temp[1] = cpu_to_fdt64(((u64)sec_mem_size));
- fdt_setprop_string(fdt, offs, "compatible",
- "ti,dra7-secure-memory");
- fdt_setprop_string(fdt, offs, "status", "okay");
- fdt_setprop(fdt, offs, "no-map", NULL, 0);
- fdt_setprop(fdt, offs, "reg", temp, sizeof(temp));
-
- return 0;
-}
-#else
-static int ft_hs_fixup_dram(void *fdt, bd_t *bd) { return 0; }
-#endif
-
-static int ft_hs_add_tee(void *fdt, bd_t *bd)
-{
- const char *path, *subpath;
- int offs;
-
- extern int tee_loaded;
- if (!tee_loaded)
- return 0;
-
- path = "/";
- offs = fdt_path_offset(fdt, path);
-
- subpath = "firmware";
- offs = fdt_add_subnode(fdt, offs, subpath);
- if (offs < 0) {
- printf("Could not create %s node.\n", subpath);
- return 1;
- }
-
- subpath = "optee";
- offs = fdt_add_subnode(fdt, offs, subpath);
- if (offs < 0) {
- printf("Could not create %s node.\n", subpath);
- return 1;
- }
-
- fdt_setprop_string(fdt, offs, "compatible", "linaro,optee-tz");
- fdt_setprop_string(fdt, offs, "method", "smc");
-
- return 0;
-}
-
static void ft_hs_fixups(void *fdt, bd_t *bd)
{
/* Check we are running on an HS/EMU device type */
+++ /dev/null
-/*
- *
- * Security related functions for OMAP5 class devices
- *
- * (C) Copyright 2016
- * Texas Instruments, <www.ti.com>
- *
- * Daniel Allred <d-allred@ti.com>
- * Harinarayan Bhatta <harinarayan@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <stdarg.h>
-
-#include <asm/arch/sys_proto.h>
-#include <asm/omap_common.h>
-#include <asm/omap_sec_common.h>
-#include <asm/spl.h>
-#include <spl.h>
-#include <asm/cache.h>
-#include <mapmem.h>
-#include <tee/optee.h>
-
-/* Index for signature PPA-based TI HAL APIs */
-#define PPA_HAL_SERVICES_START_INDEX (0x200)
-#define PPA_SERV_HAL_TEE_LOAD_MASTER (PPA_HAL_SERVICES_START_INDEX + 23)
-#define PPA_SERV_HAL_TEE_LOAD_SLAVE (PPA_HAL_SERVICES_START_INDEX + 24)
-#define PPA_SERV_HAL_SETUP_SEC_RESVD_REGION (PPA_HAL_SERVICES_START_INDEX + 25)
-#define PPA_SERV_HAL_SETUP_EMIF_FW_REGION (PPA_HAL_SERVICES_START_INDEX + 26)
-#define PPA_SERV_HAL_LOCK_EMIF_FW (PPA_HAL_SERVICES_START_INDEX + 27)
-
-int tee_loaded = 0;
-
-/* Argument for PPA_SERV_HAL_TEE_LOAD_MASTER */
-struct ppa_tee_load_info {
- u32 tee_sec_mem_start; /* Physical start address reserved for TEE */
- u32 tee_sec_mem_size; /* Size of the memory reserved for TEE */
- u32 tee_cert_start; /* Address where signed TEE binary is loaded */
- u32 tee_cert_size; /* Size of TEE certificate (signed binary) */
- u32 tee_jump_addr; /* Address to jump to start TEE execution */
- u32 tee_arg0; /* argument to TEE jump function, in r0 */
-};
-
-static u32 get_sec_mem_start(void)
-{
- u32 sec_mem_start = CONFIG_TI_SECURE_EMIF_REGION_START;
- u32 sec_mem_size = CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE;
- /*
- * Total reserved region is all contiguous with protected
- * region coming first, followed by the non-secure region.
- * If 0x0 start address is given, we simply put the reserved
- * region at the end of the external DRAM.
- */
- if (sec_mem_start == 0)
- sec_mem_start =
- (CONFIG_SYS_SDRAM_BASE +
- (omap_sdram_size() - sec_mem_size));
- return sec_mem_start;
-}
-
-int secure_emif_firewall_setup(uint8_t region_num, uint32_t start_addr,
- uint32_t size, uint32_t access_perm,
- uint32_t initiator_perm)
-{
- int result = 1;
-
- /*
- * Call PPA HAL API to do any other general firewall
- * configuration for regions 1-6 of the EMIF firewall.
- */
- debug("%s: regionNum = %x, startAddr = %x, size = %x", __func__,
- region_num, start_addr, size);
-
- result = secure_rom_call(
- PPA_SERV_HAL_SETUP_EMIF_FW_REGION, 0, 0, 4,
- (start_addr & 0xFFFFFFF0) | (region_num & 0x0F),
- size, access_perm, initiator_perm);
-
- if (result != 0) {
- puts("Secure EMIF Firewall Setup failed!\n");
- debug("Return Value = %x\n", result);
- }
-
- return result;
-}
-
-#if (CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE < \
- CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE)
-#error "TI Secure EMIF: Protected size cannot be larger than total size."
-#endif
-int secure_emif_reserve(void)
-{
- int result = 1;
- u32 sec_mem_start = get_sec_mem_start();
- u32 sec_prot_size = CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE;
-
- /* If there is no protected region, there is no reservation to make */
- if (sec_prot_size == 0)
- return 0;
-
- /*
- * Call PPA HAL API to reserve a chunk of EMIF SDRAM
- * for secure world use. This region should be carved out
- * from use by any public code. EMIF firewall region 7
- * will be used to protect this block of memory.
- */
- result = secure_rom_call(
- PPA_SERV_HAL_SETUP_SEC_RESVD_REGION,
- 0, 0, 2, sec_mem_start, sec_prot_size);
-
- if (result != 0) {
- puts("SDRAM Firewall: Secure memory reservation failed!\n");
- debug("Return Value = %x\n", result);
- }
-
- return result;
-}
-
-int secure_emif_firewall_lock(void)
-{
- int result = 1;
-
- /*
- * Call PPA HAL API to lock the EMIF firewall configurations.
- * After this API is called, none of the PPA HAL APIs for
- * configuring the EMIF firewalls will be usable again (that
- * is, calls to those APIs will return failure and have no
- * effect).
- */
-
- result = secure_rom_call(
- PPA_SERV_HAL_LOCK_EMIF_FW,
- 0, 0, 0);
-
- if (result != 0) {
- puts("Secure EMIF Firewall Lock failed!\n");
- debug("Return Value = %x\n", result);
- }
-
- return result;
-}
-
-static struct ppa_tee_load_info tee_info __aligned(ARCH_DMA_MINALIGN);
-
-int secure_tee_install(u32 addr)
-{
- struct optee_header *hdr;
- void *loadptr;
- u32 tee_file_size;
- u32 sec_mem_start = get_sec_mem_start();
- const u32 size = CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE;
- u32 *smc_cpu1_params;
- u32 ret;
-
- /* If there is no protected region, there is no place to put the TEE */
- if (size == 0) {
- printf("Error loading TEE, no protected memory region available\n");
- return -ENOBUFS;
- }
-
- hdr = (struct optee_header *)map_sysmem(addr, sizeof(struct optee_header));
- /* 280 bytes = size of signature */
- tee_file_size = hdr->init_size + hdr->paged_size +
- sizeof(struct optee_header) + 280;
-
- if ((hdr->magic != OPTEE_MAGIC) ||
- (hdr->version != OPTEE_VERSION) ||
- (hdr->init_load_addr_hi != 0) ||
- (hdr->init_load_addr_lo < (sec_mem_start + sizeof(struct optee_header))) ||
- (tee_file_size > size) ||
- ((hdr->init_load_addr_lo + tee_file_size - 1) >
- (sec_mem_start + size - 1))) {
- printf("Error in TEE header. Check load address and sizes\n");
- unmap_sysmem(hdr);
- return CMD_RET_FAILURE;
- }
-
- tee_info.tee_sec_mem_start = sec_mem_start;
- tee_info.tee_sec_mem_size = size;
- tee_info.tee_jump_addr = hdr->init_load_addr_lo;
- tee_info.tee_cert_start = addr;
- tee_info.tee_cert_size = tee_file_size;
- tee_info.tee_arg0 = hdr->init_size + tee_info.tee_jump_addr;
- unmap_sysmem(hdr);
- loadptr = map_sysmem(addr, tee_file_size);
-
- debug("tee_info.tee_sec_mem_start= %08X\n", tee_info.tee_sec_mem_start);
- debug("tee_info.tee_sec_mem_size = %08X\n", tee_info.tee_sec_mem_size);
- debug("tee_info.tee_jump_addr = %08X\n", tee_info.tee_jump_addr);
- debug("tee_info.tee_cert_start = %08X\n", tee_info.tee_cert_start);
- debug("tee_info.tee_cert_size = %08X\n", tee_info.tee_cert_size);
- debug("tee_info.tee_arg0 = %08X\n", tee_info.tee_arg0);
- debug("tee_file_size = %d\n", tee_file_size);
-
-#if !defined(CONFIG_SYS_DCACHE_OFF)
- flush_dcache_range(
- rounddown((u32)loadptr, ARCH_DMA_MINALIGN),
- roundup((u32)loadptr + tee_file_size, ARCH_DMA_MINALIGN));
-
- flush_dcache_range((u32)&tee_info, (u32)&tee_info +
- roundup(sizeof(tee_info), ARCH_DMA_MINALIGN));
-#endif
- unmap_sysmem(loadptr);
-
- ret = secure_rom_call(PPA_SERV_HAL_TEE_LOAD_MASTER, 0, 0, 1, &tee_info);
- if (ret) {
- printf("TEE_LOAD_MASTER Failed\n");
- return ret;
- }
- printf("TEE_LOAD_MASTER Done\n");
-
- if (!is_dra72x()) {
- /* Reuse the tee_info buffer for SMC params */
- smc_cpu1_params = (u32 *)&tee_info;
- smc_cpu1_params[0] = 0;
-#if !defined(CONFIG_SYS_DCACHE_OFF)
- flush_dcache_range((u32)smc_cpu1_params, (u32)smc_cpu1_params +
- roundup(sizeof(u32), ARCH_DMA_MINALIGN));
-#endif
- ret = omap_smc_sec_cpu1(PPA_SERV_HAL_TEE_LOAD_SLAVE, 0, 0,
- smc_cpu1_params);
- if (ret) {
- printf("TEE_LOAD_SLAVE Failed\n");
- return ret;
- }
- printf("TEE_LOAD_SLAVE Done\n");
- }
-
- tee_loaded = 1;
-
- return 0;
-}
*
* Common security related functions for OMAP devices
*
- * (C) Copyright 2016
+ * (C) Copyright 2016-2017
* Texas Instruments, <www.ti.com>
*
* Daniel Allred <d-allred@ti.com>
* Andreas Dannenberg <dannenberg@ti.com>
+ * Harinarayan Bhatta <harinarayan@ti.com>
+ * Andrew F. Davis <afd@ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <stdarg.h>
#include <asm/arch/sys_proto.h>
+#include <asm/cache.h>
#include <asm/omap_common.h>
#include <asm/omap_sec_common.h>
#include <asm/spl.h>
+#include <asm/ti-common/sys_proto.h>
+#include <mapmem.h>
#include <spl.h>
+#include <tee/optee.h>
/* Index for signature verify ROM API */
#ifdef CONFIG_AM33XX
#define API_HAL_KM_VERIFYCERTIFICATESIGNATURE_INDEX (0x0000000E)
#endif
+/* Index for signature PPA-based TI HAL APIs */
+#define PPA_HAL_SERVICES_START_INDEX (0x200)
+#define PPA_SERV_HAL_TEE_LOAD_MASTER (PPA_HAL_SERVICES_START_INDEX + 23)
+#define PPA_SERV_HAL_TEE_LOAD_SLAVE (PPA_HAL_SERVICES_START_INDEX + 24)
+#define PPA_SERV_HAL_SETUP_SEC_RESVD_REGION (PPA_HAL_SERVICES_START_INDEX + 25)
+#define PPA_SERV_HAL_SETUP_EMIF_FW_REGION (PPA_HAL_SERVICES_START_INDEX + 26)
+#define PPA_SERV_HAL_LOCK_EMIF_FW (PPA_HAL_SERVICES_START_INDEX + 27)
+
+int tee_loaded = 0;
+
+/* Argument for PPA_SERV_HAL_TEE_LOAD_MASTER */
+struct ppa_tee_load_info {
+ u32 tee_sec_mem_start; /* Physical start address reserved for TEE */
+ u32 tee_sec_mem_size; /* Size of the memory reserved for TEE */
+ u32 tee_cert_start; /* Address where signed TEE binary is loaded */
+ u32 tee_cert_size; /* Size of TEE certificate (signed binary) */
+ u32 tee_jump_addr; /* Address to jump to start TEE execution */
+ u32 tee_arg0; /* argument to TEE jump function, in r0 */
+};
+
static uint32_t secure_rom_call_args[5] __aligned(ARCH_DMA_MINALIGN);
u32 secure_rom_call(u32 service, u32 proc_id, u32 flag, ...)
return result;
}
+
+u32 get_sec_mem_start(void)
+{
+ u32 sec_mem_start = CONFIG_TI_SECURE_EMIF_REGION_START;
+ u32 sec_mem_size = CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE;
+ /*
+ * Total reserved region is all contiguous with protected
+ * region coming first, followed by the non-secure region.
+ * If 0x0 start address is given, we simply put the reserved
+ * region at the end of the external DRAM.
+ */
+ if (sec_mem_start == 0)
+ sec_mem_start =
+ (CONFIG_SYS_SDRAM_BASE + (
+#if defined(CONFIG_OMAP54XX)
+ omap_sdram_size()
+#else
+ get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_MAX_RAM_BANK_SIZE)
+#endif
+ - sec_mem_size));
+ return sec_mem_start;
+}
+
+int secure_emif_firewall_setup(uint8_t region_num, uint32_t start_addr,
+ uint32_t size, uint32_t access_perm,
+ uint32_t initiator_perm)
+{
+ int result = 1;
+
+ /*
+ * Call PPA HAL API to do any other general firewall
+ * configuration for regions 1-6 of the EMIF firewall.
+ */
+ debug("%s: regionNum = %x, startAddr = %x, size = %x", __func__,
+ region_num, start_addr, size);
+
+ result = secure_rom_call(
+ PPA_SERV_HAL_SETUP_EMIF_FW_REGION, 0, 0, 4,
+ (start_addr & 0xFFFFFFF0) | (region_num & 0x0F),
+ size, access_perm, initiator_perm);
+
+ if (result != 0) {
+ puts("Secure EMIF Firewall Setup failed!\n");
+ debug("Return Value = %x\n", result);
+ }
+
+ return result;
+}
+
+#if (CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE < \
+ CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE)
+#error "TI Secure EMIF: Protected size cannot be larger than total size."
+#endif
+int secure_emif_reserve(void)
+{
+ int result = 1;
+ u32 sec_mem_start = get_sec_mem_start();
+ u32 sec_prot_size = CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE;
+
+ /* If there is no protected region, there is no reservation to make */
+ if (sec_prot_size == 0)
+ return 0;
+
+ /*
+ * Call PPA HAL API to reserve a chunk of EMIF SDRAM
+ * for secure world use. This region should be carved out
+ * from use by any public code. EMIF firewall region 7
+ * will be used to protect this block of memory.
+ */
+ result = secure_rom_call(
+ PPA_SERV_HAL_SETUP_SEC_RESVD_REGION,
+ 0, 0, 2, sec_mem_start, sec_prot_size);
+
+ if (result != 0) {
+ puts("SDRAM Firewall: Secure memory reservation failed!\n");
+ debug("Return Value = %x\n", result);
+ }
+
+ return result;
+}
+
+int secure_emif_firewall_lock(void)
+{
+ int result = 1;
+
+ /*
+ * Call PPA HAL API to lock the EMIF firewall configurations.
+ * After this API is called, none of the PPA HAL APIs for
+ * configuring the EMIF firewalls will be usable again (that
+ * is, calls to those APIs will return failure and have no
+ * effect).
+ */
+
+ result = secure_rom_call(
+ PPA_SERV_HAL_LOCK_EMIF_FW,
+ 0, 0, 0);
+
+ if (result != 0) {
+ puts("Secure EMIF Firewall Lock failed!\n");
+ debug("Return Value = %x\n", result);
+ }
+
+ return result;
+}
+
+static struct ppa_tee_load_info tee_info __aligned(ARCH_DMA_MINALIGN);
+
+int secure_tee_install(u32 addr)
+{
+ struct optee_header *hdr;
+ void *loadptr;
+ u32 tee_file_size;
+ u32 sec_mem_start = get_sec_mem_start();
+ const u32 size = CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE;
+ u32 ret;
+
+ /* If there is no protected region, there is no place to put the TEE */
+ if (size == 0) {
+ printf("Error loading TEE, no protected memory region available\n");
+ return -ENOBUFS;
+ }
+
+ hdr = (struct optee_header *)map_sysmem(addr, sizeof(struct optee_header));
+ /* 280 bytes = size of signature */
+ tee_file_size = hdr->init_size + hdr->paged_size +
+ sizeof(struct optee_header) + 280;
+
+ if ((hdr->magic != OPTEE_MAGIC) ||
+ (hdr->version != OPTEE_VERSION) ||
+ (hdr->init_load_addr_hi != 0) ||
+ (hdr->init_load_addr_lo < (sec_mem_start + sizeof(struct optee_header))) ||
+ (tee_file_size > size) ||
+ ((hdr->init_load_addr_lo + tee_file_size - 1) >
+ (sec_mem_start + size - 1))) {
+ printf("Error in TEE header. Check load address and sizes\n");
+ unmap_sysmem(hdr);
+ return CMD_RET_FAILURE;
+ }
+
+ tee_info.tee_sec_mem_start = sec_mem_start;
+ tee_info.tee_sec_mem_size = size;
+ tee_info.tee_jump_addr = hdr->init_load_addr_lo;
+ tee_info.tee_cert_start = addr;
+ tee_info.tee_cert_size = tee_file_size;
+ tee_info.tee_arg0 = hdr->init_size + tee_info.tee_jump_addr;
+ unmap_sysmem(hdr);
+ loadptr = map_sysmem(addr, tee_file_size);
+
+ debug("tee_info.tee_sec_mem_start= %08X\n", tee_info.tee_sec_mem_start);
+ debug("tee_info.tee_sec_mem_size = %08X\n", tee_info.tee_sec_mem_size);
+ debug("tee_info.tee_jump_addr = %08X\n", tee_info.tee_jump_addr);
+ debug("tee_info.tee_cert_start = %08X\n", tee_info.tee_cert_start);
+ debug("tee_info.tee_cert_size = %08X\n", tee_info.tee_cert_size);
+ debug("tee_info.tee_arg0 = %08X\n", tee_info.tee_arg0);
+ debug("tee_file_size = %d\n", tee_file_size);
+
+#if !defined(CONFIG_SYS_DCACHE_OFF)
+ flush_dcache_range(
+ rounddown((u32)loadptr, ARCH_DMA_MINALIGN),
+ roundup((u32)loadptr + tee_file_size, ARCH_DMA_MINALIGN));
+
+ flush_dcache_range((u32)&tee_info, (u32)&tee_info +
+ roundup(sizeof(tee_info), ARCH_DMA_MINALIGN));
+#endif
+ unmap_sysmem(loadptr);
+
+ ret = secure_rom_call(PPA_SERV_HAL_TEE_LOAD_MASTER, 0, 0, 1, &tee_info);
+ if (ret) {
+ printf("TEE_LOAD_MASTER Failed\n");
+ return ret;
+ }
+ printf("TEE_LOAD_MASTER Done\n");
+
+#if defined(CONFIG_OMAP54XX)
+ if (!is_dra72x()) {
+ u32 *smc_cpu1_params;
+ /* Reuse the tee_info buffer for SMC params */
+ smc_cpu1_params = (u32 *)&tee_info;
+ smc_cpu1_params[0] = 0;
+#if !defined(CONFIG_SYS_DCACHE_OFF)
+ flush_dcache_range((u32)smc_cpu1_params, (u32)smc_cpu1_params +
+ roundup(sizeof(u32), ARCH_DMA_MINALIGN));
+#endif
+ ret = omap_smc_sec_cpu1(PPA_SERV_HAL_TEE_LOAD_SLAVE, 0, 0,
+ smc_cpu1_params);
+ if (ret) {
+ printf("TEE_LOAD_SLAVE Failed\n");
+ return ret;
+ }
+ printf("TEE_LOAD_SLAVE Done\n");
+ }
+#endif
+
+ tee_loaded = 1;
+
+ return 0;
+}
select SUPPORT_SPL
select SPL
select SPL_SEPARATE_BSS
+ select SPL_SERIAL_SUPPORT
+ select SPL_DRIVERS_MISC_SUPPORT
select ENABLE_ARM_SOC_BOOT0_HOOK
select DEBUG_UART_BOARD_INIT
help
void back_to_bootrom(void)
{
-#if defined(CONFIG_SPL_LIBGENERIC_SUPPORT) && !defined(CONFIG_TPL_BUILD)
- printf("Returning to boot ROM...");
+#if defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && !defined(CONFIG_TPL_BUILD)
+ puts("Returning to boot ROM...");
#endif
_back_to_bootrom_s();
}
while (1)
;
}
-
-void hang(void)
-{
- while (1)
- ;
-}
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <common.h>
#include <asm/arch/timer.h>
#include <asm/io.h>
-#include <common.h>
#include <linux/types.h>
struct rk_timer * const timer_ptr = (void *)CONFIG_SYS_TIMER_BASE;
obj-y += board.o
obj-y += clock_manager.o
-obj-y += fpga_manager.o
obj-y += misc.o
obj-y += reset_manager.o
obj-y += timer.o
obj-y += scan_manager.o
obj-y += system_manager_gen5.o
obj-y += wrap_pll_config.o
+obj-y += fpga_manager.o
endif
ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
#include <altera.h>
-struct socfpga_fpga_manager {
- /* FPGA Manager Module */
- u32 stat; /* 0x00 */
- u32 ctrl;
- u32 dclkcnt;
- u32 dclkstat;
- u32 gpo; /* 0x10 */
- u32 gpi;
- u32 misci; /* 0x18 */
- u32 _pad_0x1c_0x82c[517];
-
- /* Configuration Monitor (MON) Registers */
- u32 gpio_inten; /* 0x830 */
- u32 gpio_intmask;
- u32 gpio_inttype_level;
- u32 gpio_int_polarity;
- u32 gpio_intstatus; /* 0x840 */
- u32 gpio_raw_intstatus;
- u32 _pad_0x848;
- u32 gpio_porta_eoi;
- u32 gpio_ext_porta; /* 0x850 */
- u32 _pad_0x854_0x85c[3];
- u32 gpio_1s_sync; /* 0x860 */
- u32 _pad_0x864_0x868[2];
- u32 gpio_ver_id_code;
- u32 gpio_config_reg2; /* 0x870 */
- u32 gpio_config_reg1;
-};
-
-#define FPGAMGRREGS_STAT_MODE_MASK 0x7
-#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
-#define FPGAMGRREGS_STAT_MSEL_LSB 3
-
-#define FPGAMGRREGS_CTRL_CFGWDTH_MASK 0x200
-#define FPGAMGRREGS_CTRL_AXICFGEN_MASK 0x100
-#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK 0x4
-#define FPGAMGRREGS_CTRL_NCE_MASK 0x2
-#define FPGAMGRREGS_CTRL_EN_MASK 0x1
-#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6
-
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK 0x8
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK 0x4
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK 0x2
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK 0x1
-
-/* FPGA Mode */
-#define FPGAMGRREGS_MODE_FPGAOFF 0x0
-#define FPGAMGRREGS_MODE_RESETPHASE 0x1
-#define FPGAMGRREGS_MODE_CFGPHASE 0x2
-#define FPGAMGRREGS_MODE_INITPHASE 0x3
-#define FPGAMGRREGS_MODE_USERMODE 0x4
-#define FPGAMGRREGS_MODE_UNKNOWN 0x5
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#include <asm/arch/fpga_manager_gen5.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/fpga_manager_arria10.h>
+#endif
/* FPGA CD Ratio Value */
#define CDRATIO_x1 0x0
#define CDRATIO_x4 0x2
#define CDRATIO_x8 0x3
-/* SoCFPGA support functions */
-int fpgamgr_test_fpga_ready(void);
-int fpgamgr_poll_fpga_ready(void);
+#ifndef __ASSEMBLY__
+
+/* Common prototypes */
int fpgamgr_get_mode(void);
+int fpgamgr_poll_fpga_ready(void);
+void fpgamgr_program_write(const void *rbf_data, size_t rbf_size);
+int fpgamgr_test_fpga_ready(void);
+int fpgamgr_dclkcnt_set(unsigned long cnt);
+#endif /* __ASSEMBLY__ */
#endif /* _FPGA_MANAGER_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2017 Intel Corporation <www.intel.com>
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _FPGA_MANAGER_ARRIA10_H_
+#define _FPGA_MANAGER_ARRIA10_H_
+
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK BIT(0)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK BIT(1)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK BIT(2)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK BIT(3)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK BIT(4)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_OE_SET_MSK BIT(5)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK BIT(6)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK BIT(7)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_SET_MSK BIT(8)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_READY_SET_MSK BIT(9)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_SET_MSK BIT(10)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_SET_MSK BIT(11)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK BIT(12)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_SET_MSK BIT(13)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK BIT(16)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK BIT(17)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK BIT(18)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD (\
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK |\
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK |\
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOEMPTY_SET_MSK BIT(24)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOFULL_SET_MSK BIT(25)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_JTAGM_SET_MSK BIT(28)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EMR_SET_MSK BIT(29)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB 16
+
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK BIT(0)
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK BIT(1)
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK BIT(2)
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK BIT(8)
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK BIT(16)
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK BIT(24)
+
+#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK BIT(0)
+#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK BIT(16)
+#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK BIT(24)
+
+#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK BIT(0)
+#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK BIT(8)
+#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK 0x00030000
+#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK BIT(24)
+#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16
+
+#ifndef __ASSEMBLY__
+
+struct socfpga_fpga_manager {
+ u32 _pad_0x0_0x7[2];
+ u32 dclkcnt;
+ u32 dclkstat;
+ u32 gpo;
+ u32 gpi;
+ u32 misci;
+ u32 _pad_0x1c_0x2f[5];
+ u32 emr_data0;
+ u32 emr_data1;
+ u32 emr_data2;
+ u32 emr_data3;
+ u32 emr_data4;
+ u32 emr_data5;
+ u32 emr_valid;
+ u32 emr_en;
+ u32 jtag_config;
+ u32 jtag_status;
+ u32 jtag_kick;
+ u32 _pad_0x5c_0x5f;
+ u32 jtag_data_w;
+ u32 jtag_data_r;
+ u32 _pad_0x68_0x6f[2];
+ u32 imgcfg_ctrl_00;
+ u32 imgcfg_ctrl_01;
+ u32 imgcfg_ctrl_02;
+ u32 _pad_0x7c_0x7f;
+ u32 imgcfg_stat;
+ u32 intr_masked_status;
+ u32 intr_mask;
+ u32 intr_polarity;
+ u32 dma_config;
+ u32 imgcfg_fifo_status;
+};
+
+/* Functions */
+int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size);
+int fpgamgr_program_finish(void);
+int is_fpgamgr_user_mode(void);
+int fpgamgr_wait_early_user_mode(void);
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _FPGA_MANAGER_ARRIA10_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FPGA_MANAGER_GEN5_H_
+#define _FPGA_MANAGER_GEN5_H_
+
+#define FPGAMGRREGS_STAT_MODE_MASK 0x7
+#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
+#define FPGAMGRREGS_STAT_MSEL_LSB 3
+
+#define FPGAMGRREGS_CTRL_CFGWDTH_MASK BIT(9)
+#define FPGAMGRREGS_CTRL_AXICFGEN_MASK BIT(8)
+#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK BIT(2)
+#define FPGAMGRREGS_CTRL_NCE_MASK BIT(1)
+#define FPGAMGRREGS_CTRL_EN_MASK BIT(0)
+#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6
+
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK BIT(3)
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK BIT(2)
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK BIT(1)
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK BIT(0)
+
+/* FPGA Mode */
+#define FPGAMGRREGS_MODE_FPGAOFF 0x0
+#define FPGAMGRREGS_MODE_RESETPHASE 0x1
+#define FPGAMGRREGS_MODE_CFGPHASE 0x2
+#define FPGAMGRREGS_MODE_INITPHASE 0x3
+#define FPGAMGRREGS_MODE_USERMODE 0x4
+#define FPGAMGRREGS_MODE_UNKNOWN 0x5
+
+#ifndef __ASSEMBLY__
+
+struct socfpga_fpga_manager {
+ /* FPGA Manager Module */
+ u32 stat; /* 0x00 */
+ u32 ctrl;
+ u32 dclkcnt;
+ u32 dclkstat;
+ u32 gpo; /* 0x10 */
+ u32 gpi;
+ u32 misci; /* 0x18 */
+ u32 _pad_0x1c_0x82c[517];
+
+ /* Configuration Monitor (MON) Registers */
+ u32 gpio_inten; /* 0x830 */
+ u32 gpio_intmask;
+ u32 gpio_inttype_level;
+ u32 gpio_int_polarity;
+ u32 gpio_intstatus; /* 0x840 */
+ u32 gpio_raw_intstatus;
+ u32 _pad_0x848;
+ u32 gpio_porta_eoi;
+ u32 gpio_ext_porta; /* 0x850 */
+ u32 _pad_0x854_0x85c[3];
+ u32 gpio_1s_sync; /* 0x860 */
+ u32 _pad_0x864_0x868[2];
+ u32 gpio_ver_id_code;
+ u32 gpio_config_reg2; /* 0x870 */
+ u32 gpio_config_reg1;
+};
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _FPGA_MANAGER_GEN5_H_ */
void socfpga_reset_assert_fpga_connected_peripherals(void);
void socfpga_reset_deassert_osc1wd0(void);
void socfpga_reset_uart(int assert);
-int socfpga_bridges_reset(int enable);
+int socfpga_bridges_reset(void);
struct socfpga_reset_manager {
u32 stat;
}
#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
-int socfpga_bridges_reset(int enable)
+int socfpga_bridges_reset(void)
{
/* For SoCFPGA-VT, this is NOP. */
return 0;
}
#else
-int socfpga_bridges_reset(int enable)
+int socfpga_bridges_reset(void)
{
int ret;
select SUNXI_DRAM_DW_32BIT
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
+ imply ENV_IS_IN_MMC
choice
prompt "Sunxi SoC Variant"
select ARM_CORTEX_CPU_IS_UP
select SUNXI_GEN_SUN4I
select SUPPORT_SPL
+ imply ENV_IS_IN_MMC
config MACH_SUN5I
bool "sun5i (Allwinner A13)"
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
+ imply ENV_IS_IN_MMC
config MACH_SUN7I
bool "sun7i (Allwinner A20)"
select SUNXI_GEN_SUN4I
select SUPPORT_SPL
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
+ imply ENV_IS_IN_MMC
config MACH_SUN8I_A23
bool "sun8i (Allwinner A23)"
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
+ imply ENV_IS_IN_MMC
config MACH_SUN8I_A33
bool "sun8i (Allwinner A33)"
select ARCH_SUPPORT_PSCI
select MACH_SUNXI_H3_H5
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
+ imply ENV_IS_IN_MMC
config MACH_SUN8I_R40
bool "sun8i (Allwinner R40)"
bool "Tegra 64-bit common options"
select ARM64
select TEGRA_COMMON
+ imply ENV_IS_IN_MMC
choice
prompt "Tegra SoC select"
select ARM_ERRATA_743622
select ARM_ERRATA_751472
select TEGRA_ARMV7_COMMON
+ imply ENV_IS_IN_MMC
config TEGRA114
bool "Tegra114 family"
config TEGRA124
bool "Tegra124 family"
select TEGRA_ARMV7_COMMON
+ imply ENV_IS_IN_MMC
+ imply REGMAP
+ imply SYSCON
config TEGRA210
bool "Tegra210 family"
#ifdef CONFIG_TEGRA_CLOCK_SCALING
#include <asm/arch/emc.h>
#endif
-#include <power/as3722.h>
#include "emc.h"
DECLARE_GLOBAL_DATA_PTR;
debug("Memory controller init failed: %d\n", err);
# endif
# endif /* CONFIG_TEGRA_PMU */
-#ifdef CONFIG_PMIC_AS3722
- err = as3722_init(NULL);
- if (err && err != -ENODEV)
- return err;
-#endif
#endif /* CONFIG_SYS_I2C_TEGRA */
#ifdef CONFIG_USB_EHCI_TEGRA
pin_mux_nand();
#endif
- tegra_xusb_padctl_init(gd->fdt_blob);
+ tegra_xusb_padctl_init();
#ifdef CONFIG_TEGRA_LP0
/* save Sdram params to PMC 2, 4, and 24 for WB0 */
}
#if CONFIG_IS_ENABLED(OF_CONTROL)
-int clock_decode_periph_id(const void *blob, int node)
+int clock_decode_periph_id(struct udevice *dev)
{
enum periph_id id;
u32 cell[2];
int err;
- err = fdtdec_get_int_array(blob, node, "clocks", cell,
- ARRAY_SIZE(cell));
+ err = dev_read_u32_array(dev, "clocks", cell, ARRAY_SIZE(cell));
if (err)
return -1;
id = clk_id_to_periph_id(cell[1]);
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <debug_uart.h>
#include <spl.h>
#include <asm/io.h>
gpio_early_init_uart();
clock_early_init();
+#ifdef CONFIG_DEBUG_UART
+ debug_uart_init();
+#endif
preloader_console_init();
}
obj-y += clock.o
obj-y += funcmux.o
obj-y += pinmux.o
+obj-y += pmc.o
obj-y += xusb-padctl.o
obj-y += ../xusb-padctl-common.o
--- /dev/null
+/*
+ * Copyright (C) 2017 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+
+static const struct udevice_id tegra124_syscon_ids[] = {
+ { .compatible = "nvidia,tegra124-pmc", .data = TEGRA_SYSCON_PMC },
+};
+
+U_BOOT_DRIVER(syscon_tegra124) = {
+ .name = "tegra124_syscon",
+ .id = UCLASS_SYSCON,
+ .of_match = tegra124_syscon_ids,
+};
#include <common.h>
#include <errno.h>
+#include <dm/of_access.h>
+#include <dm/ofnode.h>
#include "../xusb-padctl-common.h"
.num_phys = ARRAY_SIZE(tegra124_phys),
};
-void tegra_xusb_padctl_init(const void *fdt)
+void tegra_xusb_padctl_init(void)
{
- int count, nodes[1];
+ ofnode nodes[1];
+ int count = 0;
+ int ret;
+
+ debug("%s: start\n", __func__);
+ if (of_live_active()) {
+ struct device_node *np = of_find_compatible_node(NULL, NULL,
+ "nvidia,tegra124-xusb-padctl");
+
+ debug("np=%p\n", np);
+ if (np) {
+ nodes[0] = np_to_ofnode(np);
+ count = 1;
+ }
+ } else {
+ int node_offsets[1];
+ int i;
+
+ count = fdtdec_find_aliases_for_id(gd->fdt_blob, "padctl",
+ COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
+ node_offsets, ARRAY_SIZE(node_offsets));
+ for (i = 0; i < count; i++)
+ nodes[i] = offset_to_ofnode(node_offsets[i]);
+ }
- count = fdtdec_find_aliases_for_id(fdt, "padctl",
- COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
- nodes, ARRAY_SIZE(nodes));
- if (tegra_xusb_process_nodes(fdt, nodes, count, &tegra124_socdata))
- return;
+ ret = tegra_xusb_process_nodes(nodes, count, &tegra124_socdata);
+ debug("%s: done, ret=%d\n", __func__, ret);
}
#include <common.h>
#include <errno.h>
+#include <dm/of_access.h>
+#include <dm/ofnode.h>
#include "../xusb-padctl-common.h"
#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
+DECLARE_GLOBAL_DATA_PTR;
+
enum tegra210_function {
TEGRA210_FUNC_SNPS,
TEGRA210_FUNC_XUSB,
.num_phys = ARRAY_SIZE(tegra210_phys),
};
-void tegra_xusb_padctl_init(const void *fdt)
+void tegra_xusb_padctl_init(void)
{
- int count, nodes[1];
-
- debug("> %s(fdt=%p)\n", __func__, fdt);
-
- count = fdtdec_find_aliases_for_id(fdt, "padctl",
- COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL,
- nodes, ARRAY_SIZE(nodes));
- if (tegra_xusb_process_nodes(fdt, nodes, count, &tegra210_socdata))
- return;
+ ofnode nodes[1];
+ int count = 0;
+ int ret;
+
+ debug("%s: start\n", __func__);
+ if (of_live_active()) {
+ struct device_node *np = of_find_compatible_node(NULL, NULL,
+ "nvidia,tegra210-xusb-padctl");
+
+ debug("np=%p\n", np);
+ if (np) {
+ nodes[0] = np_to_ofnode(np);
+ count = 1;
+ }
+ } else {
+ int node_offsets[1];
+ int i;
+
+ count = fdtdec_find_aliases_for_id(gd->fdt_blob, "padctl",
+ COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL,
+ node_offsets, ARRAY_SIZE(node_offsets));
+ for (i = 0; i < count; i++)
+ nodes[i] = offset_to_ofnode(node_offsets[i]);
+ }
- debug("< %s()\n", __func__);
+ ret = tegra_xusb_process_nodes(nodes, count, &tegra210_socdata);
+ debug("%s: done, ret=%d\n", __func__, ret);
}
static int
tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl *padctl,
struct tegra_xusb_padctl_group *group,
- const void *fdt, int node)
+ ofnode node)
{
unsigned int i;
- int len;
+ int len, ret;
- group->name = fdt_get_name(fdt, node, &len);
+ group->name = ofnode_get_name(node);
- len = fdt_stringlist_count(fdt, node, "nvidia,lanes");
+ len = ofnode_read_string_count(node, "nvidia,lanes");
if (len < 0) {
error("failed to parse \"nvidia,lanes\" property");
return -EINVAL;
group->num_pins = len;
for (i = 0; i < group->num_pins; i++) {
- group->pins[i] = fdt_stringlist_get(fdt, node, "nvidia,lanes",
- i, NULL);
- if (!group->pins[i]) {
+ ret = ofnode_read_string_index(node, "nvidia,lanes", i,
+ &group->pins[i]);
+ if (ret) {
error("failed to read string from \"nvidia,lanes\" property");
return -EINVAL;
}
group->num_pins = len;
- group->func = fdt_stringlist_get(fdt, node, "nvidia,function", 0, NULL);
- if (!group->func) {
+ ret = ofnode_read_string_index(node, "nvidia,function", 0,
+ &group->func);
+ if (ret) {
error("failed to parse \"nvidia,func\" property");
return -EINVAL;
}
- group->iddq = fdtdec_get_int(fdt, node, "nvidia,iddq", -1);
+ group->iddq = ofnode_read_u32_default(node, "nvidia,iddq", -1);
return 0;
}
static int
tegra_xusb_padctl_config_parse_dt(struct tegra_xusb_padctl *padctl,
struct tegra_xusb_padctl_config *config,
- const void *fdt, int node)
+ ofnode node)
{
- int subnode;
+ ofnode subnode;
- config->name = fdt_get_name(fdt, node, NULL);
+ config->name = ofnode_get_name(node);
- fdt_for_each_subnode(subnode, fdt, node) {
+ for (subnode = ofnode_first_subnode(node);
+ ofnode_valid(subnode);
+ subnode = ofnode_next_subnode(subnode)) {
struct tegra_xusb_padctl_group *group;
int err;
group = &config->groups[config->num_groups];
- err = tegra_xusb_padctl_group_parse_dt(padctl, group, fdt,
- subnode);
+ err = tegra_xusb_padctl_group_parse_dt(padctl, group, subnode);
if (err < 0) {
error("failed to parse group %s", group->name);
return err;
}
static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl,
- const void *fdt, int node)
+ ofnode node)
{
- int subnode, err;
+ ofnode subnode;
+ int err;
- err = fdt_get_resource(fdt, node, "reg", 0, &padctl->regs);
+ err = ofnode_read_resource(node, 0, &padctl->regs);
if (err < 0) {
error("registers not found");
return err;
}
- fdt_for_each_subnode(subnode, fdt, node) {
+ for (subnode = ofnode_first_subnode(node);
+ ofnode_valid(subnode);
+ subnode = ofnode_next_subnode(subnode)) {
struct tegra_xusb_padctl_config *config = &padctl->config;
- err = tegra_xusb_padctl_config_parse_dt(padctl, config, fdt,
+ debug("%s: subnode=%s\n", __func__, ofnode_get_name(subnode));
+ err = tegra_xusb_padctl_config_parse_dt(padctl, config,
subnode);
if (err < 0) {
error("failed to parse entry %s: %d",
continue;
}
}
+ debug("%s: done\n", __func__);
return 0;
}
struct tegra_xusb_padctl padctl;
-int tegra_xusb_process_nodes(const void *fdt, int nodes[], unsigned int count,
- const struct tegra_xusb_padctl_soc *socdata)
+int tegra_xusb_process_nodes(ofnode nodes[], unsigned int count,
+ const struct tegra_xusb_padctl_soc *socdata)
{
unsigned int i;
int err;
+ debug("%s: count=%d\n", __func__, count);
for (i = 0; i < count; i++) {
- if (!fdtdec_get_is_enabled(fdt, nodes[i]))
+ debug("%s: i=%d, node=%p\n", __func__, i, nodes[i].np);
+ if (!ofnode_is_available(nodes[i]))
continue;
padctl.socdata = socdata;
- err = tegra_xusb_padctl_parse_dt(&padctl, fdt, nodes[i]);
+ err = tegra_xusb_padctl_parse_dt(&padctl, nodes[i]);
if (err < 0) {
error("failed to parse DT: %d", err);
continue;
/* only a single instance is supported */
break;
}
+ debug("%s: done\n", __func__);
return 0;
}
#include <common.h>
#include <fdtdec.h>
+#include <dm/ofnode.h>
#include <asm/io.h>
#include <asm/arch-tegra/xusb-padctl.h>
+#include <linux/ioport.h>
struct tegra_xusb_padctl_lane {
const char *name;
struct tegra_xusb_padctl {
const struct tegra_xusb_padctl_soc *socdata;
struct tegra_xusb_padctl_config config;
- struct fdt_resource regs;
+ struct resource regs;
unsigned int enable;
};
writel(value, padctl->regs.start + offset);
}
-int tegra_xusb_process_nodes(const void *fdt, int nodes[], unsigned int count,
- const struct tegra_xusb_padctl_soc *socdata);
+int tegra_xusb_process_nodes(ofnode nodes[], unsigned int count,
+ const struct tegra_xusb_padctl_soc *socdata);
#endif
return -ENOSYS;
}
-void __weak tegra_xusb_padctl_init(const void *fdt)
+void __weak tegra_xusb_padctl_init(void)
{
}
select ARMV7_NONSEC
select ARCH_SUPPORT_PSCI
-config ARCH_UNIPHIER_64BIT
- bool
- select ARM64
- select CMD_UNZIP
- select SPL_SEPARATE_BSS if SPL
- select ARMV8_MULTIENTRY if SPL
- select ARMV8_SPIN_TABLE if SPL
-
choice
prompt "UniPhier SoC select"
default ARCH_UNIPHIER_PRO4
bool "UniPhier Pro5/PXs2/LD6b SoCs"
select ARCH_UNIPHIER_32BIT
-config ARCH_UNIPHIER_LD11_SINGLE
- bool "UniPhier LD11 SoC"
- select ARCH_UNIPHIER_64BIT
-
-config ARCH_UNIPHIER_LD20_SINGLE
- bool "UniPhier LD20 SoC"
- select ARCH_UNIPHIER_64BIT
-
config ARCH_UNIPHIER_V8_MULTI
bool "UniPhier V8 SoCs"
depends on !SPL
- select ARCH_UNIPHIER_64BIT
+ select ARM64
+ select CMD_UNZIP
endchoice
default y
config ARCH_UNIPHIER_LD11
- bool "Enable UniPhier LD11 SoC support" if ARCH_UNIPHIER_V8_MULTI
- depends on ARCH_UNIPHIER_LD11_SINGLE || ARCH_UNIPHIER_V8_MULTI
+ bool "Enable UniPhier LD11 SoC support"
+ depends on ARCH_UNIPHIER_V8_MULTI
default y
config ARCH_UNIPHIER_LD20
- bool "Enable UniPhier LD20 SoC support" if ARCH_UNIPHIER_V8_MULTI
- depends on ARCH_UNIPHIER_LD20_SINGLE || ARCH_UNIPHIER_V8_MULTI
+ bool "Enable UniPhier LD20 SoC support"
+ depends on ARCH_UNIPHIER_V8_MULTI
select OF_BOARD_SETUP
default y
# SPDX-License-Identifier: GPL-2.0+
#
-ifdef CONFIG_SPL_BUILD
-obj-y += timer.o
-else
obj-y += mem_map.o
-ifdef CONFIG_ARMV8_MULTIENTRY
-obj-y += smp.o smp_kick_cpus.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD20) += arm-cci500.o
-else
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += lowlevel_init.o
-endif
-endif
+++ /dev/null
-/*
- * Initialization of ARM Corelink CCI-500 Cache Coherency Interconnect
- *
- * Copyright (C) 2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/bitops.h>
-#include <linux/io.h>
-#include <linux/sizes.h>
-
-#include "../init.h"
-
-#define CCI500_BASE 0x5FD00000
-#define CCI500_SLAVE_OFFSET 0x1000
-
-#define CCI500_SNOOP_CTRL
-#define CCI500_SNOOP_CTRL_EN_DVM BIT(1)
-#define CCI500_SNOOP_CTRL_EN_SNOOP BIT(0)
-
-void cci500_init(unsigned int nr_slaves)
-{
- unsigned long slave_base = CCI500_BASE + CCI500_SLAVE_OFFSET;
- int i;
-
- for (i = 0; i < nr_slaves; i++) {
- void __iomem *base;
- u32 tmp;
-
- base = ioremap(slave_base, SZ_4K);
-
- tmp = readl(base);
- tmp |= CCI500_SNOOP_CTRL_EN_DVM | CCI500_SNOOP_CTRL_EN_SNOOP;
- writel(tmp, base);
-
- iounmap(base);
-
- slave_base += CCI500_SLAVE_OFFSET;
- }
-}
+++ /dev/null
-/*
- * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/linkage.h>
-
-ENTRY(uniphier_smp_setup)
- mrs x0, s3_1_c15_c2_1 /* CPUECTLR_EL1 */
- orr x0, x0, #(1 << 6) /* SMPEN */
- msr s3_1_c15_c2_1, x0
- ret
-ENDPROC(uniphier_smp_setup)
-
-ENTRY(uniphier_secondary_startup)
- bl uniphier_smp_setup
- b _start
-ENDPROC(uniphier_secondary_startup)
+++ /dev/null
-/*
- * Copyright (C) 2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-#include <linux/sizes.h>
-
-#include "../init.h"
-
-#define UNIPHIER_SMPCTRL_ROM_RSV0 0x59801200
-
-void uniphier_smp_setup(void);
-void uniphier_secondary_startup(void);
-
-void uniphier_smp_kick_all_cpus(void)
-{
- void __iomem *rom_boot_rsv0;
-
- rom_boot_rsv0 = ioremap(UNIPHIER_SMPCTRL_ROM_RSV0, SZ_8);
-
- writeq((u64)uniphier_secondary_startup, rom_boot_rsv0);
-
- iounmap(rom_boot_rsv0);
-
- uniphier_smp_setup();
-
- asm("dsb ishst\n" /* Ensure the write to ROM_RSV0 is visible */
- "sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */
-}
+++ /dev/null
-/*
- * Copyright (C) 2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/bitops.h>
-#include <linux/io.h>
-#include <linux/sizes.h>
-
-#define CNT_CONTROL_BASE 0x60E00000
-
-#define CNTCR 0x000
-#define CNTCR_EN BIT(0)
-
-/* setup ARMv8 Generic Timer */
-int timer_init(void)
-{
- void __iomem *base;
- u32 tmp;
-
- base = ioremap(CNT_CONTROL_BASE, SZ_4K);
-
- /*
- * Note:
- * In a system that implements both Secure and Non-secure states,
- * this register is only writable in Secure state.
- */
- tmp = readl(base + CNTCR);
- tmp |= CNTCR_EN;
- writel(tmp, base + CNTCR);
-
- iounmap(base);
-
- return 0;
-}
writel(0x0000b500, 0x6184e024);
writel(0x00000001, 0x6184e000);
}
-#ifdef CONFIG_ARMV8_MULTIENTRY
- cci500_init(2);
-#endif
}
#endif
support_card_late_init();
- led_puts("U6");
-
-#ifdef CONFIG_ARMV8_MULTIENTRY
- uniphier_smp_kick_all_cpus();
-#endif
-
led_puts("Uboo");
return 0;
};
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_LD11)
-static const struct uniphier_board_data uniphier_ld11_data = {
- .dram_freq = 1600,
- .dram_ch[0] = {
- .size = 0x20000000,
- .width = 16,
- },
- .dram_ch[1] = {
- .size = 0x20000000,
- .width = 16,
- },
-};
-#endif
-
-#if defined(CONFIG_ARCH_UNIPHIER_LD20)
-static const struct uniphier_board_data uniphier_ld20_ref_data = {
- .dram_freq = 1866,
- .dram_ch[0] = {
- .size = 0x40000000,
- .width = 32,
- },
- .dram_ch[1] = {
- .size = 0x40000000,
- .width = 32,
- },
- .dram_ch[2] = {
- .size = 0x40000000,
- .width = 32,
- },
- .flags = UNIPHIER_BD_BOARD_LD20_REF,
-};
-
-static const struct uniphier_board_data uniphier_ld20_data = {
- .dram_freq = 1866,
- .dram_ch[0] = {
- .size = 0x40000000,
- .width = 32,
- },
- .dram_ch[1] = {
- .size = 0x40000000,
- .width = 32,
- },
- .dram_ch[2] = {
- .size = 0x40000000,
- .width = 32,
- },
- .flags = UNIPHIER_BD_BOARD_LD20_GLOBAL,
-};
-
-static const struct uniphier_board_data uniphier_ld21_data = {
- .dram_freq = 1866,
- .dram_ch[0] = {
- .size = 0x20000000,
- .width = 32,
- },
- .dram_ch[1] = {
- .size = 0x40000000,
- .width = 32,
- },
- .flags = UNIPHIER_BD_DRAM_SPARSE | UNIPHIER_BD_BOARD_LD21_GLOBAL,
-};
-#endif
-
struct uniphier_board_id {
const char *compatible;
const struct uniphier_board_data *param;
#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
{ "socionext,uniphier-ld6b", &uniphier_ld6b_data, },
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_LD11)
- { "socionext,uniphier-ld11", &uniphier_ld11_data, },
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_LD20)
- { "socionext,uniphier-ld21", &uniphier_ld21_data, },
- { "socionext,uniphier-ld20-ref", &uniphier_ld20_ref_data, },
- { "socionext,uniphier-ld20", &uniphier_ld20_data, },
-#endif
};
const struct uniphier_board_data *uniphier_get_board_param(void)
obj-$(CONFIG_ARCH_UNIPHIER_LD11) += boot-device-ld11.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += boot-device-ld11.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += boot-device-pxs3.o
-
-ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_SPL_BOARD_LOAD_IMAGE) += spl_board.o
-endif
+++ /dev/null
-/*
- * Copyright (C) 2017 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-#include <linux/bitops.h>
-#include <linux/compat.h>
-#include <linux/io.h>
-#include <asm/processor.h>
-
-#include "../soc-info.h"
-
-#define MMC_CMD_SWITCH 6
-#define MMC_CMD_SELECT_CARD 7
-#define MMC_CMD_SEND_CSD 9
-#define MMC_CMD_READ_MULTIPLE_BLOCK 18
-
-#define EXT_CSD_PART_CONF 179 /* R/W */
-
-#define MMC_RSP_PRESENT BIT(0)
-#define MMC_RSP_136 BIT(1) /* 136 bit response */
-#define MMC_RSP_CRC BIT(2) /* expect valid crc */
-#define MMC_RSP_BUSY BIT(3) /* card may send busy */
-#define MMC_RSP_OPCODE BIT(4) /* response contains opcode */
-
-#define MMC_RSP_NONE (0)
-#define MMC_RSP_R1 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
-#define MMC_RSP_R1b (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE | \
- MMC_RSP_BUSY)
-#define MMC_RSP_R2 (MMC_RSP_PRESENT | MMC_RSP_136 | MMC_RSP_CRC)
-#define MMC_RSP_R3 (MMC_RSP_PRESENT)
-#define MMC_RSP_R4 (MMC_RSP_PRESENT)
-#define MMC_RSP_R5 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
-#define MMC_RSP_R6 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
-#define MMC_RSP_R7 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
-
-#define SDHCI_DMA_ADDRESS 0x00
-#define SDHCI_BLOCK_SIZE 0x04
-#define SDHCI_MAKE_BLKSZ(dma, blksz) ((((dma) & 0x7) << 12) | ((blksz) & 0xFFF))
-#define SDHCI_BLOCK_COUNT 0x06
-#define SDHCI_ARGUMENT 0x08
-#define SDHCI_TRANSFER_MODE 0x0C
-#define SDHCI_TRNS_DMA BIT(0)
-#define SDHCI_TRNS_BLK_CNT_EN BIT(1)
-#define SDHCI_TRNS_ACMD12 BIT(2)
-#define SDHCI_TRNS_READ BIT(4)
-#define SDHCI_TRNS_MULTI BIT(5)
-#define SDHCI_COMMAND 0x0E
-#define SDHCI_CMD_RESP_MASK 0x03
-#define SDHCI_CMD_CRC 0x08
-#define SDHCI_CMD_INDEX 0x10
-#define SDHCI_CMD_DATA 0x20
-#define SDHCI_CMD_ABORTCMD 0xC0
-#define SDHCI_CMD_RESP_NONE 0x00
-#define SDHCI_CMD_RESP_LONG 0x01
-#define SDHCI_CMD_RESP_SHORT 0x02
-#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
-#define SDHCI_MAKE_CMD(c, f) ((((c) & 0xff) << 8) | ((f) & 0xff))
-#define SDHCI_RESPONSE 0x10
-#define SDHCI_HOST_CONTROL 0x28
-#define SDHCI_CTRL_DMA_MASK 0x18
-#define SDHCI_CTRL_SDMA 0x00
-#define SDHCI_BLOCK_GAP_CONTROL 0x2A
-#define SDHCI_SOFTWARE_RESET 0x2F
-#define SDHCI_RESET_CMD 0x02
-#define SDHCI_RESET_DATA 0x04
-#define SDHCI_INT_STATUS 0x30
-#define SDHCI_INT_RESPONSE BIT(0)
-#define SDHCI_INT_DATA_END BIT(1)
-#define SDHCI_INT_ERROR BIT(15)
-#define SDHCI_SIGNAL_ENABLE 0x38
-
-/* RCA assigned by Boot ROM */
-#define UNIPHIER_EMMC_RCA 0x1000
-
-struct uniphier_mmc_cmd {
- unsigned int cmdidx;
- unsigned int resp_type;
- unsigned int cmdarg;
- unsigned int is_data;
-};
-
-static int uniphier_emmc_send_cmd(void __iomem *host_base,
- struct uniphier_mmc_cmd *cmd)
-{
- u32 mode = 0;
- u32 mask = SDHCI_INT_RESPONSE;
- u32 stat, flags;
-
- writel(U32_MAX, host_base + SDHCI_INT_STATUS);
- writel(0, host_base + SDHCI_SIGNAL_ENABLE);
- writel(cmd->cmdarg, host_base + SDHCI_ARGUMENT);
-
- if (cmd->is_data)
- mode = SDHCI_TRNS_DMA | SDHCI_TRNS_BLK_CNT_EN |
- SDHCI_TRNS_ACMD12 | SDHCI_TRNS_READ |
- SDHCI_TRNS_MULTI;
-
- writew(mode, host_base + SDHCI_TRANSFER_MODE);
-
- if (!(cmd->resp_type & MMC_RSP_PRESENT))
- flags = SDHCI_CMD_RESP_NONE;
- else if (cmd->resp_type & MMC_RSP_136)
- flags = SDHCI_CMD_RESP_LONG;
- else if (cmd->resp_type & MMC_RSP_BUSY)
- flags = SDHCI_CMD_RESP_SHORT_BUSY;
- else
- flags = SDHCI_CMD_RESP_SHORT;
-
- if (cmd->resp_type & MMC_RSP_CRC)
- flags |= SDHCI_CMD_CRC;
- if (cmd->resp_type & MMC_RSP_OPCODE)
- flags |= SDHCI_CMD_INDEX;
- if (cmd->is_data)
- flags |= SDHCI_CMD_DATA;
-
- if (cmd->resp_type & MMC_RSP_BUSY || cmd->is_data)
- mask |= SDHCI_INT_DATA_END;
-
- writew(SDHCI_MAKE_CMD(cmd->cmdidx, flags), host_base + SDHCI_COMMAND);
-
- do {
- stat = readl(host_base + SDHCI_INT_STATUS);
- if (stat & SDHCI_INT_ERROR)
- return -EIO;
-
- } while ((stat & mask) != mask);
-
- return 0;
-}
-
-static int uniphier_emmc_switch_part(void __iomem *host_base, int part_num)
-{
- struct uniphier_mmc_cmd cmd = {};
-
- cmd.cmdidx = MMC_CMD_SWITCH;
- cmd.resp_type = MMC_RSP_R1b;
- cmd.cmdarg = (EXT_CSD_PART_CONF << 16) | (part_num << 8) | (3 << 24);
-
- return uniphier_emmc_send_cmd(host_base, &cmd);
-}
-
-static int uniphier_emmc_is_over_2gb(void __iomem *host_base)
-{
- struct uniphier_mmc_cmd cmd = {};
- u32 csd40, csd72; /* CSD[71:40], CSD[103:72] */
- int ret;
-
- cmd.cmdidx = MMC_CMD_SEND_CSD;
- cmd.resp_type = MMC_RSP_R2;
- cmd.cmdarg = UNIPHIER_EMMC_RCA << 16;
-
- ret = uniphier_emmc_send_cmd(host_base, &cmd);
- if (ret)
- return ret;
-
- csd40 = readl(host_base + SDHCI_RESPONSE + 4);
- csd72 = readl(host_base + SDHCI_RESPONSE + 8);
-
- return !(~csd40 & 0xffc00380) && !(~csd72 & 0x3);
-}
-
-static int uniphier_emmc_load_image(void __iomem *host_base, u32 dev_addr,
- unsigned long load_addr, u32 block_cnt)
-{
- struct uniphier_mmc_cmd cmd = {};
- u8 tmp;
-
- WARN_ON(load_addr >> 32);
-
- writel(load_addr, host_base + SDHCI_DMA_ADDRESS);
- writew(SDHCI_MAKE_BLKSZ(7, 512), host_base + SDHCI_BLOCK_SIZE);
- writew(block_cnt, host_base + SDHCI_BLOCK_COUNT);
-
- tmp = readb(host_base + SDHCI_HOST_CONTROL);
- tmp &= ~SDHCI_CTRL_DMA_MASK;
- tmp |= SDHCI_CTRL_SDMA;
- writeb(tmp, host_base + SDHCI_HOST_CONTROL);
-
- tmp = readb(host_base + SDHCI_BLOCK_GAP_CONTROL);
- tmp &= ~1; /* clear Stop At Block Gap Request */
- writeb(tmp, host_base + SDHCI_BLOCK_GAP_CONTROL);
-
- cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
- cmd.resp_type = MMC_RSP_R1;
- cmd.cmdarg = dev_addr;
- cmd.is_data = 1;
-
- return uniphier_emmc_send_cmd(host_base, &cmd);
-}
-
-static int spl_board_load_image(struct spl_image_info *spl_image,
- struct spl_boot_device *bootdev)
-{
- u32 dev_addr = CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR;
- void __iomem *host_base = (void __iomem *)0x5a000200;
- struct uniphier_mmc_cmd cmd = {};
- int ret;
-
- /*
- * deselect card before SEND_CSD command.
- * Do not check the return code. It fails, but it is OK.
- */
- cmd.cmdidx = MMC_CMD_SELECT_CARD;
- cmd.resp_type = MMC_RSP_R1;
-
- uniphier_emmc_send_cmd(host_base, &cmd); /* CMD7 (arg=0) */
-
- /* reset CMD Line */
- writeb(SDHCI_RESET_CMD | SDHCI_RESET_DATA,
- host_base + SDHCI_SOFTWARE_RESET);
- while (readb(host_base + SDHCI_SOFTWARE_RESET))
- cpu_relax();
-
- ret = uniphier_emmc_is_over_2gb(host_base);
- if (ret < 0)
- return ret;
- if (ret) {
- debug("card is block addressing\n");
- } else {
- debug("card is byte addressing\n");
- dev_addr *= 512;
- }
-
- cmd.cmdarg = UNIPHIER_EMMC_RCA << 16;
-
- /* select card again */
- ret = uniphier_emmc_send_cmd(host_base, &cmd);
- if (ret)
- printf("failed to select card\n");
-
- /* Switch to Boot Partition 1 */
- ret = uniphier_emmc_switch_part(host_base, 1);
- if (ret)
- printf("failed to switch partition\n");
-
- ret = uniphier_emmc_load_image(host_base, dev_addr,
- CONFIG_SYS_TEXT_BASE, 1);
- if (ret) {
- printf("failed to load image\n");
- return ret;
- }
-
- ret = spl_parse_image_header(spl_image, (void *)CONFIG_SYS_TEXT_BASE);
- if (ret)
- return ret;
-
- ret = uniphier_emmc_load_image(host_base, dev_addr,
- spl_image->load_addr,
- spl_image->size / 512);
- if (ret) {
- printf("failed to load image\n");
- return ret;
- }
-
- return 0;
-}
-SPL_LOAD_IMAGE_METHOD("eMMC", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-early-sld3.o clk-dram-pro5.o dpll-pro5.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-early-sld3.o clk-dram-pxs2.o dpll-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-early-sld3.o clk-dram-pxs2.o dpll-pxs2.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD11) += clk-early-ld11.o clk-dram-ld11.o dpll-ld11.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-early-ld11.o clk-dram-ld20.o dpll-ld20.o
else
+++ /dev/null
-/*
- * Copyright (C) 2016-2017 Socionext Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sc64-regs.h"
-
-void uniphier_ld11_dram_clk_init(void)
-{
- u32 tmp;
-
- /* deassert reset */
- tmp = readl(SC_RSTCTRL7);
- tmp |= SC_RSTCTRL7_UMC31 | SC_RSTCTRL7_UMC30;
- writel(tmp, SC_RSTCTRL7);
-
- /* provide clocks */
- tmp = readl(SC_CLKCTRL7);
- tmp |= SC_CLKCTRL7_UMC31 | SC_CLKCTRL7_UMC30;
- writel(tmp, SC_CLKCTRL7);
-}
+++ /dev/null
-/*
- * Copyright (C) 2016-2017 Socionext Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sc64-regs.h"
-
-void uniphier_ld20_dram_clk_init(void)
-{
- u32 tmp;
-
- /* deassert reset */
- tmp = readl(SC_RSTCTRL7);
- tmp |= SC_RSTCTRL7_UMCSB | SC_RSTCTRL7_UMCA2 | SC_RSTCTRL7_UMCA1 |
- SC_RSTCTRL7_UMCA0 | SC_RSTCTRL7_UMC32 | SC_RSTCTRL7_UMC31 |
- SC_RSTCTRL7_UMC30;
- writel(tmp, SC_RSTCTRL7);
-
- /* provide clocks */
- tmp = readl(SC_CLKCTRL7);
- tmp |= SC_CLKCTRL7_UMCSB | SC_CLKCTRL7_UMC32 | SC_CLKCTRL7_UMC31 |
- SC_CLKCTRL7_UMC30;
- writel(tmp, SC_CLKCTRL7);
-}
+++ /dev/null
-/*
- * Copyright (C) 2016-2017 Socionext Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sc64-regs.h"
-
-void uniphier_ld11_early_clk_init(void)
-{
- u32 tmp;
-
- /* provide clocks */
- tmp = readl(SC_CLKCTRL4);
- tmp |= SC_CLKCTRL4_PERI;
- writel(tmp, SC_CLKCTRL4);
-}
+++ /dev/null
-/*
- * Copyright (C) 2016 Socionext Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include "../init.h"
-#include "../sc64-regs.h"
-#include "pll.h"
-
-int uniphier_ld11_dpll_init(const struct uniphier_board_data *bd)
-{
- uniphier_ld20_sscpll_init(SC_DPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include "../init.h"
-#include "../sc64-regs.h"
-#include "pll.h"
-
-int uniphier_ld20_dpll_init(const struct uniphier_board_data *bd)
-{
- uniphier_ld20_sscpll_init(SC_DPLL0CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
- uniphier_ld20_sscpll_init(SC_DPLL1CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
- uniphier_ld20_sscpll_init(SC_DPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
-
- return 0;
-}
model = uniphier_get_soc_model();
rev = uniphier_get_soc_revision();
- puts("CPU: ");
+ puts("SoC: ");
switch (id) {
case UNIPHIER_SLD3_ID:
- puts("sLD3 (MN2WS0220)");
+ puts("sLD3");
required_model = 2;
break;
case UNIPHIER_LD4_ID:
- puts("LD4 (MN2WS0250)");
+ puts("LD4");
required_rev = 2;
break;
case UNIPHIER_PRO4_ID:
- puts("Pro4 (MN2WS0230)");
+ puts("Pro4");
break;
case UNIPHIER_SLD8_ID:
- puts("sLD8 (MN2WS0270)");
+ puts("sLD8");
break;
case UNIPHIER_PRO5_ID:
- puts("Pro5 (MN2WS0300)");
+ puts("Pro5");
break;
case UNIPHIER_PXS2_ID:
- puts("PXs2 (MN2WS0310)");
+ puts("PXs2");
break;
case UNIPHIER_LD6B_ID:
- puts("LD6b (MN2WS0320)");
+ puts("LD6b");
break;
case UNIPHIER_LD11_ID:
- puts("LD11 (SC1405AP1)");
+ puts("LD11");
break;
case UNIPHIER_LD20_ID:
- puts("LD20 (SC1401AJ1)");
+ puts("LD20");
break;
case UNIPHIER_PXS3_ID:
puts("PXs3");
return -ENOTSUPP;
}
- printf(" model %d (revision %d)\n", model, rev);
+ printf(" (model %d, revision %d)\n", model, rev);
if (model < required_model) {
printf("Only model %d or newer is supported.\n",
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += umc-pro5.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += umc-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += umc-pxs2.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD11) += umc-ld11.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD20) += umc-ld20.o
else
+++ /dev/null
-/*
- * Copyright (C) 2016 Socionext Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _DDRUQPHY_REGS_H
-#define _DDRUQPHY_REGS_H
-
-#include <linux/bitops.h>
-
-#define PHY_REG_SHIFT 2
-#define PHY_SLV_DLY_WIDTH 6
-#define PHY_BITLVL_DLY_WIDTH 6
-#define PHY_MAS_DLY_WIDTH 8
-
-#define PHY_SCL_START (0x40 << (PHY_REG_SHIFT))
-#define PHY_SCL_START_GO_DONE BIT(28)
-#define PHY_SCL_DATA_0 (0x41 << (PHY_REG_SHIFT))
-#define PHY_SCL_DATA_1 (0x42 << (PHY_REG_SHIFT))
-#define PHY_SCL_LATENCY (0x43 << (PHY_REG_SHIFT))
-#define PHY_SCL_CONFIG_1 (0x46 << (PHY_REG_SHIFT))
-#define PHY_SCL_CONFIG_2 (0x47 << (PHY_REG_SHIFT))
-#define PHY_PAD_CTRL (0x48 << (PHY_REG_SHIFT))
-#define PHY_DLL_RECALIB (0x49 << (PHY_REG_SHIFT))
-#define PHY_DLL_RECALIB_TRIM_MASK GENMASK(PHY_SLV_DLY_WIDTH - 1, 0)
-#define PHY_DLL_RECALIB_INCR BIT(27)
-#define PHY_DLL_ADRCTRL (0x4A << (PHY_REG_SHIFT))
-#define PHY_DLL_ADRCTRL_TRIM_MASK GENMASK(PHY_SLV_DLY_WIDTH - 1, 0)
-#define PHY_DLL_ADRCTRL_INCR BIT(9)
-#define PHY_DLL_ADRCTRL_MDL_SHIFT 24
-#define PHY_DLL_ADRCTRL_MDL_MASK (GENMASK(PHY_MAS_DLY_WIDTH - 1, 0) << \
- PHY_DLL_ADRCTRL_MDL_SHIFT)
-#define PHY_LANE_SEL (0x4B << (PHY_REG_SHIFT))
-#define PHY_LANE_SEL_LANE_SHIFT 0
-#define PHY_LANE_SEL_LANE_WIDTH 8
-#define PHY_LANE_SEL_BIT_SHIFT 8
-#define PHY_LANE_SEL_BIT_WIDTH 4
-#define PHY_DLL_TRIM_1 (0x4C << (PHY_REG_SHIFT))
-#define PHY_DLL_TRIM_2 (0x4D << (PHY_REG_SHIFT))
-#define PHY_DLL_TRIM_3 (0x4E << (PHY_REG_SHIFT))
-#define PHY_SCL_MAIN_CLK_DELTA (0x50 << (PHY_REG_SHIFT))
-#define PHY_WRLVL_AUTOINC_TRIM (0x53 << (PHY_REG_SHIFT))
-#define PHY_WRLVL_DYN_ODT (0x54 << (PHY_REG_SHIFT))
-#define PHY_WRLVL_ON_OFF (0x55 << (PHY_REG_SHIFT))
-#define PHY_UNQ_ANALOG_DLL_1 (0x57 << (PHY_REG_SHIFT))
-#define PHY_UNQ_ANALOG_DLL_2 (0x58 << (PHY_REG_SHIFT))
-#define PHY_DLL_INCR_TRIM_1 (0x59 << (PHY_REG_SHIFT))
-#define PHY_DLL_INCR_TRIM_3 (0x5A << (PHY_REG_SHIFT))
-#define PHY_SCL_CONFIG_3 (0x5B << (PHY_REG_SHIFT))
-#define PHY_UNIQUIFY_TSMC_IO_1 (0x5C << (PHY_REG_SHIFT))
-#define PHY_SCL_START_ADDR (0x62 << (PHY_REG_SHIFT))
-#define PHY_IP_DQ_DQS_BITWISE_TRIM (0x65 << (PHY_REG_SHIFT))
-#define PHY_IP_DQ_DQS_BITWISE_TRIM_MASK \
- GENMASK(PHY_BITLVL_DLY_WIDTH - 1, 0)
-#define PHY_IP_DQ_DQS_BITWISE_TRIM_INC \
- BIT(PHY_BITLVL_DLY_WIDTH)
-#define PHY_IP_DQ_DQS_BITWISE_TRIM_OVERRIDE \
- BIT(PHY_BITLVL_DLY_WIDTH + 1)
-#define PHY_DSCL_CNT (0x67 << (PHY_REG_SHIFT))
-#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM (0x68 << (PHY_REG_SHIFT))
-#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM_MASK \
- GENMASK(PHY_BITLVL_DLY_WIDTH - 1, 0)
-#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM_INC \
- BIT(PHY_BITLVL_DLY_WIDTH)
-#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM_OVERRIDE \
- BIT(PHY_BITLVL_DLY_WIDTH + 1)
-#define PHY_DLL_TRIM_CLK (0x69 << (PHY_REG_SHIFT))
-#define PHY_DLL_TRIM_CLK_MASK GENMASK(PHY_SLV_DLY_WIDTH, 0)
-#define PHY_DLL_TRIM_CLK_INCR BIT(PHY_SLV_DLY_WIDTH + 1)
-#define PHY_DYNAMIC_BIT_LVL (0x6B << (PHY_REG_SHIFT))
-#define PHY_SCL_WINDOW_TRIM (0x6D << (PHY_REG_SHIFT))
-#define PHY_DISABLE_GATING_FOR_SCL (0x6E << (PHY_REG_SHIFT))
-#define PHY_SCL_CONFIG_4 (0x6F << (PHY_REG_SHIFT))
-#define PHY_DYNAMIC_WRITE_BIT_LVL (0x70 << (PHY_REG_SHIFT))
-#define PHY_VREF_TRAINING (0x72 << (PHY_REG_SHIFT))
-#define PHY_SCL_GATE_TIMING (0x78 << (PHY_REG_SHIFT))
-
-#endif /* _DDRUQPHY_REGS_H */
+++ /dev/null
-/*
- * Copyright (C) 2016 Socionext Inc.
- */
-
-#include <common.h>
-#include <linux/io.h>
-#include <linux/sizes.h>
-#include <asm/processor.h>
-
-#include "../init.h"
-#include "ddrphy-regs.h"
-#include "umc64-regs.h"
-
-#define DDR_FREQ 1600
-
-#define DRAM_CH_NR 2
-#define RANK_BLOCKS_TR 2
-
-enum dram_freq {
- DRAM_FREQ_1600M,
- DRAM_FREQ_NR,
-};
-
-enum dram_size {
- DRAM_SZ_256M,
- DRAM_SZ_512M,
- DRAM_SZ_NR,
-};
-
-/* PHY */
-static const int rof_pos_shift_pre[RANK_BLOCKS_TR][2] = { {0, 0}, {0, 0} };
-static const int rof_neg_shift_pre[RANK_BLOCKS_TR][2] = { {0, 0}, {0, 0} };
-static const int rof_pos_shift[RANK_BLOCKS_TR][2] = { {-35, -35}, {-35, -35} };
-static const int rof_neg_shift[RANK_BLOCKS_TR][2] = { {-17, -17}, {-17, -17} };
-static const int tof_shift[RANK_BLOCKS_TR][2] = { {-50, -50}, {-50, -50} };
-
-/* Register address */
-#define PHY_ZQ0CR1 0x00000184
-#define PHY_ZQ1CR1 0x00000194
-#define PHY_ZQ2CR1 0x000001A4
-#define PHY_DX0GCR 0x000001C0
-#define PHY_DX0GTR 0x000001F0
-#define PHY_DX1GCR 0x00000200
-#define PHY_DX1GTR 0x00000230
-#define PHY_DX2GCR 0x00000240
-#define PHY_DX2GTR 0x00000270
-#define PHY_DX3GCR 0x00000280
-#define PHY_DX3GTR 0x000002B0
-
-#define PHY_DXMDLR(dx) (0x000001EC + 0x40 * (dx))
-#define PHY_DXLCDLR0(dx) (0x000001E0 + 0x40 * (dx))
-#define PHY_DXLCDLR1(dx) (0x000001E4 + 0x40 * (dx))
-#define PHY_DXLCDLR2(dx) (0x000001E8 + 0x40 * (dx))
-#define PHY_DXBDLR1(dx) (0x000001D0 + 0x40 * (dx))
-#define PHY_DXBDLR2(dx) (0x000001D4 + 0x40 * (dx))
-
-/* MASK */
-#define PHY_ACBD_MASK 0x00FC0000
-#define PHY_CK0BD_MASK 0x0000003F
-#define PHY_CK1BD_MASK 0x00000FC0
-#define PHY_IPRD_MASK 0x000000FF
-#define PHY_WLD_MASK(rank) (0xFF << (8 * (rank)))
-#define PHY_DQSGD_MASK(rank) (0xFF << (8 * (rank)))
-#define PHY_DQSGX_MASK BIT(6)
-#define PHY_DSWBD_MASK 0x3F000000 /* bit[29:24] */
-#define PHY_DSDQOE_MASK 0x00000FFF
-
-static void ddrphy_maskwritel(u32 data, u32 mask, void __iomem *addr)
-{
- u32 value;
-
- value = (readl(addr) & ~(mask)) | (data & mask);
- writel(value, addr);
-}
-
-static u32 ddrphy_maskreadl(u32 mask, void __iomem *addr)
-{
- return readl(addr) & mask;
-}
-
-/* step of 0.5T for PUB-byte */
-static u8 ddrphy_get_mdl(int dx, void __iomem *phy_base)
-{
- return ddrphy_maskreadl(PHY_IPRD_MASK, phy_base + PHY_DXMDLR(dx));
-}
-
-/* Calculating step for PUB-byte */
-static int ddrphy_hpstep(int delay, int dx, void __iomem *phy_base)
-{
- return delay * ddrphy_get_mdl(dx, phy_base) * DDR_FREQ / 1000000;
-}
-
-static void ddrphy_vt_ctrl(void __iomem *phy_base, int enable)
-{
- u32 tmp;
-
- tmp = readl(phy_base + PHY_PGCR1);
-
- if (enable)
- tmp &= ~PHY_PGCR1_INHVT;
- else
- tmp |= PHY_PGCR1_INHVT;
-
- writel(tmp, phy_base + PHY_PGCR1);
-
- if (!enable) {
- while (!(readl(phy_base + PHY_PGSR1) & PHY_PGSR1_VTSTOP))
- cpu_relax();
- }
-}
-
-static void ddrphy_set_ckoffset_qoffset(int delay_ckoffset0, int delay_ckoffset1,
- int delay_qoffset, int enable,
- void __iomem *phy_base)
-{
- u8 ck_step0, ck_step1; /* ckoffset_step for clock */
- u8 q_step; /* qoffset_step for clock */
- int dx;
-
- dx = 2; /* use dx2 in sLD11 */
-
- ck_step0 = ddrphy_hpstep(delay_ckoffset0, dx, phy_base); /* CK-Offset */
- ck_step1 = ddrphy_hpstep(delay_ckoffset1, dx, phy_base); /* CK-Offset */
- q_step = ddrphy_hpstep(delay_qoffset, dx, phy_base); /* Q-Offset */
-
- ddrphy_vt_ctrl(phy_base, 0);
-
- /* Q->[23:18], CK1->[11:6], CK0->bit[5:0] */
- if (enable == 1)
- ddrphy_maskwritel((q_step << 18) + (ck_step1 << 6) + ck_step0,
- PHY_ACBD_MASK | PHY_CK1BD_MASK | PHY_CK0BD_MASK,
- phy_base + PHY_ACBDLR);
-
- ddrphy_vt_ctrl(phy_base, 1);
-}
-
-static void ddrphy_set_wl_delay_dx(int dx, int r0_delay, int r1_delay,
- int enable, void __iomem *phy_base)
-{
- int rank;
- int delay_wl[4];
- u32 wl_mask = 0; /* WriteLeveling's Mask */
- u32 wl_value = 0; /* WriteLeveling's Value */
-
- delay_wl[0] = r0_delay & 0xfff;
- delay_wl[1] = r1_delay & 0xfff;
- delay_wl[2] = 0;
- delay_wl[3] = 0;
-
- ddrphy_vt_ctrl(phy_base, 0);
-
- for (rank = 0; rank < 4; rank++) {
- wl_mask |= PHY_WLD_MASK(rank);
- /* WriteLeveling's delay */
- wl_value |= ddrphy_hpstep(delay_wl[rank], dx, phy_base) << (8 * rank);
- }
-
- if (enable == 1)
- ddrphy_maskwritel(wl_value, wl_mask, phy_base + PHY_DXLCDLR0(dx));
-
- ddrphy_vt_ctrl(phy_base, 1);
-}
-
-static void ddrphy_set_dqsg_delay_dx(int dx, int r0_delay, int r1_delay,
- int enable, void __iomem *phy_base)
-{
- int rank;
- int delay_dqsg[4];
- u32 dqsg_mask = 0; /* DQSGating_LCDL_delay's Mask */
- u32 dqsg_value = 0; /* DQSGating_LCDL_delay's Value */
-
- delay_dqsg[0] = r0_delay;
- delay_dqsg[1] = r1_delay;
- delay_dqsg[2] = 0;
- delay_dqsg[3] = 0;
-
- ddrphy_vt_ctrl(phy_base, 0);
-
- for (rank = 0; rank < 4; rank++) {
- dqsg_mask |= PHY_DQSGD_MASK(rank);
- /* DQSGating's delay */
- dqsg_value |= ddrphy_hpstep(delay_dqsg[rank], dx, phy_base) << (8 * rank);
- }
-
- if (enable == 1)
- ddrphy_maskwritel(dqsg_value, dqsg_mask, phy_base + PHY_DXLCDLR2(dx));
-
- ddrphy_vt_ctrl(phy_base, 1);
-}
-
-static void ddrphy_set_dswb_delay_dx(int dx, int delay, int enable, void __iomem *phy_base)
-{
- u8 dswb_step;
-
- ddrphy_vt_ctrl(phy_base, 0);
-
- dswb_step = ddrphy_hpstep(delay, dx, phy_base); /* DQS-BDL's delay */
-
- if (enable == 1)
- ddrphy_maskwritel(dswb_step << 24, PHY_DSWBD_MASK, phy_base + PHY_DXBDLR1(dx));
-
- ddrphy_vt_ctrl(phy_base, 1);
-}
-
-static void ddrphy_set_oe_delay_dx(int dx, int dqs_delay, int dq_delay,
- int enable, void __iomem *phy_base)
-{
- u8 dqs_oe_step, dq_oe_step;
- u32 wdata;
-
- ddrphy_vt_ctrl(phy_base, 0);
-
- /* OE(DQS,DQ) */
- dqs_oe_step = ddrphy_hpstep(dqs_delay, dx, phy_base); /* DQS-oe's delay */
- dq_oe_step = ddrphy_hpstep(dq_delay, dx, phy_base); /* DQ-oe's delay */
- wdata = ((dq_oe_step<<6) + dqs_oe_step) & 0xFFF;
-
- if (enable == 1)
- ddrphy_maskwritel(wdata, PHY_DSDQOE_MASK, phy_base + PHY_DXBDLR2(dx));
-
- ddrphy_vt_ctrl(phy_base, 1);
-}
-
-static void ddrphy_ext_dqsgt(void __iomem *phy_base)
-{
- /* Extend DQSGating_window min:+1T max:+1T */
- ddrphy_maskwritel(PHY_DQSGX_MASK, PHY_DQSGX_MASK, phy_base + PHY_DSGCR);
-}
-
-static void ddrphy_shift_tof_hws(void __iomem *phy_base, const int shift[][2])
-{
- int dx, block, byte;
- u32 lcdlr1, wdqd;
-
- ddrphy_vt_ctrl(phy_base, 0);
-
- for (block = 0; block < RANK_BLOCKS_TR; block++) {
- for (byte = 0; byte < 2; byte++) {
- dx = block * 2 + byte;
- lcdlr1 = readl(phy_base + PHY_DXLCDLR1(dx));
- wdqd = lcdlr1 & 0xff;
- wdqd = clamp(wdqd + ddrphy_hpstep(shift[block][byte], dx, phy_base),
- 0U, 0xffU);
- lcdlr1 = (lcdlr1 & ~0xff) | wdqd;
- writel(lcdlr1, phy_base + PHY_DXLCDLR1(dx));
- readl(phy_base + PHY_DXLCDLR1(dx)); /* relax */
- }
- }
-
- ddrphy_vt_ctrl(phy_base, 1);
-}
-
-static void ddrphy_shift_rof_hws(void __iomem *phy_base, const int pos_shift[][2],
- const int neg_shift[][2])
-{
- int dx, block, byte;
- u32 lcdlr1, rdqsd, rdqnsd;
-
- ddrphy_vt_ctrl(phy_base, 0);
-
- for (block = 0; block < RANK_BLOCKS_TR; block++) {
- for (byte = 0; byte < 2; byte++) {
- dx = block * 2 + byte;
- lcdlr1 = readl(phy_base + PHY_DXLCDLR1(dx));
-
- /* DQS LCDL RDQNSD->[23:16] RDQSD->[15:8] */
- rdqsd = (lcdlr1 >> 8) & 0xff;
- rdqnsd = (lcdlr1 >> 16) & 0xff;
- rdqsd = clamp(rdqsd + ddrphy_hpstep(pos_shift[block][byte], dx, phy_base),
- 0U, 0xffU);
- rdqnsd = clamp(rdqnsd + ddrphy_hpstep(neg_shift[block][byte], dx, phy_base),
- 0U, 0xffU);
- lcdlr1 = (lcdlr1 & ~(0xffff << 8)) | (rdqsd << 8) | (rdqnsd << 16);
- writel(lcdlr1, phy_base + PHY_DXLCDLR1(dx));
- readl(phy_base + PHY_DXLCDLR1(dx)); /* relax */
- }
- }
-
- ddrphy_vt_ctrl(phy_base, 1);
-}
-
-static void ddrphy_boot_run_hws(void __iomem *phy_base)
-{
- /* Hard Training for DIO */
- writel(0x0000f401, phy_base + PHY_PIR);
- while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
- cpu_relax();
-}
-
-static void ddrphy_training(void __iomem *phy_base)
-{
- /* DIO roffset shift before hard training */
- ddrphy_shift_rof_hws(phy_base, rof_pos_shift_pre, rof_neg_shift_pre);
-
- /* Hard Training for each CH */
- ddrphy_boot_run_hws(phy_base);
-
- /* DIO toffset shift after training */
- ddrphy_shift_tof_hws(phy_base, tof_shift);
-
- /* DIO roffset shift after training */
- ddrphy_shift_rof_hws(phy_base, rof_pos_shift, rof_neg_shift);
-
- /* Extend DQSGating window min:+1T max:+1T */
- ddrphy_ext_dqsgt(phy_base);
-}
-
-static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq)
-{
- writel(0x40000000, phy_base + PHY_PIR);
- writel(0x0300C4F1, phy_base + PHY_PGCR1);
- writel(0x0C807D04, phy_base + PHY_PTR0);
- writel(0x27100578, phy_base + PHY_PTR1);
- writel(0x00083DEF, phy_base + PHY_PTR2);
- writel(0x12061A80, phy_base + PHY_PTR3);
- writel(0x08027100, phy_base + PHY_PTR4);
- writel(0x9D9CBB66, phy_base + PHY_DTPR0);
- writel(0x1a878400, phy_base + PHY_DTPR1);
- writel(0x50025200, phy_base + PHY_DTPR2);
- writel(0xF004641A, phy_base + PHY_DSGCR);
- writel(0x0000040B, phy_base + PHY_DCR);
- writel(0x00000d71, phy_base + PHY_MR0);
- writel(0x00000006, phy_base + PHY_MR1);
- writel(0x00000098, phy_base + PHY_MR2);
- writel(0x00000000, phy_base + PHY_MR3);
-
- while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
- cpu_relax();
-
- writel(0x00000059, phy_base + PHY_ZQ0CR1);
- writel(0x00000019, phy_base + PHY_ZQ1CR1);
- writel(0x00000019, phy_base + PHY_ZQ2CR1);
- writel(0x30FC6C20, phy_base + PHY_PGCR2);
-
- ddrphy_set_ckoffset_qoffset(119, 0, 0, 1, phy_base);
- ddrphy_set_wl_delay_dx(0, 220, 220, 1, phy_base);
- ddrphy_set_wl_delay_dx(1, 160, 160, 1, phy_base);
- ddrphy_set_wl_delay_dx(2, 190, 190, 1, phy_base);
- ddrphy_set_wl_delay_dx(3, 150, 150, 1, phy_base);
- ddrphy_set_dqsg_delay_dx(0, 750, 750, 1, phy_base);
- ddrphy_set_dqsg_delay_dx(1, 750, 750, 1, phy_base);
- ddrphy_set_dqsg_delay_dx(2, 750, 750, 1, phy_base);
- ddrphy_set_dqsg_delay_dx(3, 750, 750, 1, phy_base);
- ddrphy_set_dswb_delay_dx(0, 0, 1, phy_base);
- ddrphy_set_dswb_delay_dx(1, 0, 1, phy_base);
- ddrphy_set_dswb_delay_dx(2, 0, 1, phy_base);
- ddrphy_set_dswb_delay_dx(3, 0, 1, phy_base);
- ddrphy_set_oe_delay_dx(0, 0, 0, 1, phy_base);
- ddrphy_set_oe_delay_dx(1, 0, 0, 1, phy_base);
- ddrphy_set_oe_delay_dx(2, 0, 0, 1, phy_base);
- ddrphy_set_oe_delay_dx(3, 0, 0, 1, phy_base);
-
- writel(0x44000E81, phy_base + PHY_DX0GCR);
- writel(0x44000E81, phy_base + PHY_DX1GCR);
- writel(0x44000E81, phy_base + PHY_DX2GCR);
- writel(0x44000E81, phy_base + PHY_DX3GCR);
- writel(0x00055002, phy_base + PHY_DX0GTR);
- writel(0x00055002, phy_base + PHY_DX1GTR);
- writel(0x00055010, phy_base + PHY_DX2GTR);
- writel(0x00055010, phy_base + PHY_DX3GTR);
- writel(0x930035C7, phy_base + PHY_DTCR);
- writel(0x00000003, phy_base + PHY_PIR);
- readl(phy_base + PHY_PIR);
- while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
- cpu_relax();
-
- writel(0x00000181, phy_base + PHY_PIR);
- readl(phy_base + PHY_PIR);
- while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
- cpu_relax();
-
- writel(0x44181884, phy_base + PHY_DXCCR);
- writel(0x00000001, phy_base + PHY_GPR1);
-}
-
-/* UMC */
-static const u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060B0B1C};
-static const u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x27201806};
-static const u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00120B04};
-static const u32 umc_cmdctle[DRAM_FREQ_NR] = {0x00680607};
-static const u32 umc_cmdctlf[DRAM_FREQ_NR] = {0x02000200};
-static const u32 umc_cmdctlg[DRAM_FREQ_NR] = {0x08080808};
-
-static const u32 umc_rdatactl[DRAM_FREQ_NR] = {0x00000810};
-static const u32 umc_wdatactl[DRAM_FREQ_NR] = {0x00000004};
-static const u32 umc_odtctl[DRAM_FREQ_NR] = {0x02000002};
-static const u32 umc_acssetb[DRAM_CH_NR] = {0x00000200, 0x00000203};
-
-static const u32 umc_memconfch[DRAM_FREQ_NR] = {0x00023605};
-
-static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq,
- unsigned long size, int ch)
-{
- /* Wait for PHY Init Complete */
- writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA);
- writel(umc_cmdctlb[freq], dc_base + UMC_CMDCTLB);
- writel(umc_cmdctlc[freq], dc_base + UMC_CMDCTLC);
- writel(umc_cmdctle[freq], dc_base + UMC_CMDCTLE);
- writel(umc_cmdctlf[freq], dc_base + UMC_CMDCTLF);
- writel(umc_cmdctlg[freq], dc_base + UMC_CMDCTLG);
-
- writel(umc_rdatactl[freq], dc_base + UMC_RDATACTL_D0);
- writel(umc_rdatactl[freq], dc_base + UMC_RDATACTL_D1);
-
- writel(umc_wdatactl[freq], dc_base + UMC_WDATACTL_D0);
- writel(umc_wdatactl[freq], dc_base + UMC_WDATACTL_D1);
-
- writel(umc_odtctl[freq], dc_base + UMC_ODTCTL_D0);
- writel(umc_odtctl[freq], dc_base + UMC_ODTCTL_D1);
-
- writel(0x00000003, dc_base + UMC_ACSSETA);
- writel(0x00000103, dc_base + UMC_FLOWCTLG);
- writel(umc_acssetb[ch], dc_base + UMC_ACSSETB);
- writel(0x02020200, dc_base + UMC_SPCSETB);
- writel(umc_memconfch[freq], dc_base + UMC_MEMCONFCH);
- writel(0x00000002, dc_base + UMC_ACFETCHCTRL);
-
- return 0;
-}
-
-static int umc_ch_init(void __iomem *umc_ch_base,
- enum dram_freq freq, unsigned long size, int ch)
-{
- void __iomem *dc_base = umc_ch_base;
-
- return umc_dc_init(dc_base, freq, size, ch);
-}
-
-static void um_init(void __iomem *um_base)
-{
- writel(0x00000001, um_base + UMC_SIORST);
- writel(0x00000001, um_base + UMC_VO0RST);
- writel(0x00000001, um_base + UMC_VPERST);
- writel(0x00000001, um_base + UMC_RGLRST);
- writel(0x00000001, um_base + UMC_A2DRST);
- writel(0x00000001, um_base + UMC_DMDRST);
-}
-
-int uniphier_ld11_umc_init(const struct uniphier_board_data *bd)
-{
- void __iomem *um_base = (void __iomem *)0x5B800000;
- void __iomem *umc_ch_base = (void __iomem *)0x5BC00000;
- void __iomem *phy_base = (void __iomem *)0x5BC01000;
- enum dram_freq freq;
- int ch, ret;
-
- switch (bd->dram_freq) {
- case 1600:
- freq = DRAM_FREQ_1600M;
- break;
- default:
- pr_err("unsupported DRAM frequency %d MHz\n", bd->dram_freq);
- return -EINVAL;
- }
-
- writel(0x00000101, umc_ch_base + UMC_DIOCTLA);
- while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
- cpu_relax();
-
- writel(0x00000000, umc_ch_base + UMC_DIOCTLA);
- writel(0x00000001, umc_ch_base + UMC_DEBUGC);
- writel(0x00000101, umc_ch_base + UMC_DIOCTLA);
-
- writel(0x00000100, umc_ch_base + UMC_INITSET);
- while (readl(umc_ch_base + UMC_INITSTAT) & BIT(8))
- cpu_relax();
-
- writel(0x00000100, umc_ch_base + 0x00200000 + UMC_INITSET);
- while (readl(umc_ch_base + 0x00200000 + UMC_INITSTAT) & BIT(8))
- cpu_relax();
-
- ddrphy_init(phy_base, freq);
-
- for (ch = 0; ch < DRAM_CH_NR; ch++) {
- unsigned long size = bd->dram_ch[ch].size;
- unsigned int width = bd->dram_ch[ch].width;
-
- ret = umc_ch_init(umc_ch_base, freq, size / (width / 16), ch);
- if (ret) {
- pr_err("failed to initialize UMC ch%d\n", ch);
- return ret;
- }
-
- umc_ch_base += 0x00200000;
- }
- ddrphy_training(phy_base);
-
- um_init(um_base);
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2016-2017 Socionext Inc.
- *
- * based on commit 5ffd75ecd4929f22361ef65a35f0331d2fbc0f35 of Diag
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/bitops.h>
-#include <linux/compat.h>
-#include <linux/errno.h>
-#include <linux/io.h>
-#include <linux/sizes.h>
-#include <asm/processor.h>
-
-#include "../init.h"
-#include "ddruqphy-regs.h"
-#include "umc64-regs.h"
-
-#define DRAM_CH_NR 3
-
-enum dram_freq {
- DRAM_FREQ_1866M,
- DRAM_FREQ_NR,
-};
-
-enum dram_size {
- DRAM_SZ_256M,
- DRAM_SZ_512M,
- DRAM_SZ_NR,
-};
-
-enum dram_board { /* board type */
- DRAM_BOARD_LD20_REF, /* LD20 reference */
- DRAM_BOARD_LD20_GLOBAL, /* LD20 TV */
- DRAM_BOARD_LD20_C1, /* LD20 TV C1 */
- DRAM_BOARD_LD21_REF, /* LD21 reference */
- DRAM_BOARD_LD21_GLOBAL, /* LD21 TV */
- DRAM_BOARD_NR,
-};
-
-/* PHY */
-static const int ddrphy_adrctrl[DRAM_BOARD_NR][DRAM_CH_NR] = {
- {268 - 262, 268 - 263, 268 - 378}, /* LD20 reference */
- {268 - 262, 268 - 263, 268 - 378}, /* LD20 TV */
- {268 - 262, 268 - 263, 268 - 378}, /* LD20 TV C1 */
- {268 - 212, 268 - 268, /* No CH2 */}, /* LD21 reference */
- {268 - 212, 268 - 268, /* No CH2 */}, /* LD21 TV */
-};
-
-static const int ddrphy_dlltrimclk[DRAM_BOARD_NR][DRAM_CH_NR] = {
- {268, 268, 268}, /* LD20 reference */
- {268, 268, 268}, /* LD20 TV */
- {189, 189, 189}, /* LD20 TV C1 */
- {268, 268 + 252, /* No CH2 */}, /* LD21 reference */
- {268, 268 + 202, /* No CH2 */}, /* LD21 TV */
-};
-
-static const int ddrphy_dllrecalib[DRAM_BOARD_NR][DRAM_CH_NR] = {
- {268 - 378, 268 - 263, 268 - 378}, /* LD20 reference */
- {268 - 378, 268 - 263, 268 - 378}, /* LD20 TV */
- {268 - 378, 268 - 263, 268 - 378}, /* LD20 TV C1 */
- {268 - 212, 268 - 536, /* No CH2 */}, /* LD21 reference */
- {268 - 212, 268 - 536, /* No CH2 */}, /* LD21 TV */
-};
-
-static const u32 ddrphy_phy_pad_ctrl[DRAM_BOARD_NR][DRAM_CH_NR] = {
- {0x50B840B1, 0x50B840B1, 0x50B840B1}, /* LD20 reference */
- {0x50BB40B1, 0x50BB40B1, 0x50BB40B1}, /* LD20 TV */
- {0x50BB40B1, 0x50BB40B1, 0x50BB40B1}, /* LD20 TV C1 */
- {0x50BB40B4, 0x50B840B1, /* No CH2 */}, /* LD21 reference */
- {0x50BB40B4, 0x50B840B1, /* No CH2 */}, /* LD21 TV */
-};
-
-static const u32 ddrphy_scl_gate_timing[DRAM_CH_NR] = {
- 0x00000140, 0x00000180, 0x00000140
-};
-
-static const short ddrphy_op_dq_shift_val_ld20[DRAM_CH_NR][32] = {
- {
- 2, 1, 0, 1, 2, 1, 1, 1,
- 2, 1, 1, 2, 1, 1, 1, 1,
- 1, 2, 1, 1, 1, 2, 1, 1,
- 2, 2, 0, 1, 1, 2, 2, 1,
- },
- {
- 1, 1, 0, 1, 2, 2, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 0, 0, 1, 1, 0, 0,
- 0, 1, 1, 1, 2, 1, 2, 1,
- },
- {
- 2, 2, 0, 2, 1, 1, 2, 1,
- 1, 1, 0, 1, 1, -1, 1, 1,
- 2, 2, 2, 2, 1, 1, 1, 1,
- 1, 1, 1, 0, 2, 2, 1, 2,
- },
-};
-
-static const short ddrphy_op_dq_shift_val_ld21[DRAM_CH_NR][32] = {
- {
- 1, 1, 0, 1, 1, 1, 1, 1,
- 1, 0, 0, 0, 1, 1, 0, 2,
- 1, 1, 0, 0, 1, 1, 1, 1,
- 1, 0, 0, 0, 1, 0, 0, 1,
- },
- { 1, 0, 2, 1, 1, 1, 1, 0,
- 1, 0, 0, 1, 0, 1, 0, 0,
- 1, 0, 1, 0, 1, 1, 1, 0,
- 1, 1, 1, 1, 0, 1, 0, 0,
- },
- /* No CH2 */
-};
-
-static const short (* const ddrphy_op_dq_shift_val[DRAM_BOARD_NR])[32] = {
- ddrphy_op_dq_shift_val_ld20, /* LD20 reference */
- ddrphy_op_dq_shift_val_ld20, /* LD20 TV */
- ddrphy_op_dq_shift_val_ld20, /* LD20 TV C */
- ddrphy_op_dq_shift_val_ld21, /* LD21 reference */
- ddrphy_op_dq_shift_val_ld21, /* LD21 TV */
-};
-
-static const short ddrphy_ip_dq_shift_val_ld20[DRAM_CH_NR][32] = {
- {
- 3, 3, 3, 2, 3, 2, 0, 2,
- 2, 3, 3, 1, 2, 2, 2, 2,
- 2, 2, 2, 2, 0, 1, 1, 1,
- 2, 2, 2, 2, 3, 0, 2, 2,
- },
- {
- 2, 2, 1, 1, -1, 1, 1, 1,
- 2, 0, 2, 2, 2, 1, 0, 2,
- 2, 1, 2, 1, 0, 1, 1, 1,
- 2, 2, 2, 2, 2, 2, 2, 2,
- },
- {
- 2, 2, 3, 2, 1, 2, 2, 2,
- 2, 3, 4, 2, 3, 4, 3, 3,
- 2, 2, 1, 2, 1, 1, 1, 1,
- 2, 2, 2, 2, 1, 2, 2, 1,
- },
-};
-
-static const short ddrphy_ip_dq_shift_val_ld21[DRAM_CH_NR][32] = {
- {
- 2, 2, 2, 2, 1, 2, 2, 2,
- 2, 3, 3, 2, 2, 2, 2, 2,
- 2, 1, 2, 2, 1, 1, 1, 1,
- 2, 2, 2, 3, 1, 2, 2, 2,
- },
- {
- 3, 4, 4, 1, 0, 1, 1, 1,
- 1, 2, 1, 2, 2, 3, 3, 2,
- 1, 0, 2, 1, 1, 0, 1, 0,
- 0, 1, 0, 0, 1, 1, 0, 1,
- },
- /* No CH2 */
-};
-
-static const short (* const ddrphy_ip_dq_shift_val[DRAM_BOARD_NR])[32] = {
- ddrphy_ip_dq_shift_val_ld20, /* LD20 reference */
- ddrphy_ip_dq_shift_val_ld20, /* LD20 TV */
- ddrphy_ip_dq_shift_val_ld20, /* LD20 TV C */
- ddrphy_ip_dq_shift_val_ld21, /* LD21 reference */
- ddrphy_ip_dq_shift_val_ld21, /* LD21 TV */
-};
-
-static void ddrphy_select_lane(void __iomem *phy_base, unsigned int lane,
- unsigned int bit)
-{
- WARN_ON(lane >= 1 << PHY_LANE_SEL_LANE_WIDTH);
- WARN_ON(bit >= 1 << PHY_LANE_SEL_BIT_WIDTH);
-
- writel((bit << PHY_LANE_SEL_BIT_SHIFT) |
- (lane << PHY_LANE_SEL_LANE_SHIFT),
- phy_base + PHY_LANE_SEL);
-}
-
-#define DDRPHY_EFUSEMON (void *)0x5f900118
-
-static void ddrphy_init(void __iomem *phy_base, enum dram_board board, int ch)
-{
- writel(0x0C001001, phy_base + PHY_UNIQUIFY_TSMC_IO_1);
- while (!(readl(phy_base + PHY_UNIQUIFY_TSMC_IO_1) & BIT(1)))
- cpu_relax();
-
- if (readl(DDRPHY_EFUSEMON) & BIT(ch))
- writel(0x00000000, phy_base + PHY_UNIQUIFY_TSMC_IO_1);
- else
- writel(0x0C001000, phy_base + PHY_UNIQUIFY_TSMC_IO_1);
-
- writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_3);
- writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_1);
- ddrphy_select_lane(phy_base, 0, 0);
- writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
- writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
- ddrphy_select_lane(phy_base, 6, 0);
- writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
- writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
- ddrphy_select_lane(phy_base, 12, 0);
- writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
- writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
- ddrphy_select_lane(phy_base, 18, 0);
- writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
- writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
- writel(0x00000001, phy_base + PHY_SCL_WINDOW_TRIM);
- writel(0x00000000, phy_base + PHY_UNQ_ANALOG_DLL_1);
- writel(ddrphy_phy_pad_ctrl[board][ch], phy_base + PHY_PAD_CTRL);
- writel(0x00000070, phy_base + PHY_VREF_TRAINING);
- writel(0x01000075, phy_base + PHY_SCL_CONFIG_1);
- writel(0x00000501, phy_base + PHY_SCL_CONFIG_2);
- writel(0x00000000, phy_base + PHY_SCL_CONFIG_3);
- writel(0x000261c0, phy_base + PHY_DYNAMIC_WRITE_BIT_LVL);
- writel(0x00000000, phy_base + PHY_SCL_CONFIG_4);
- writel(ddrphy_scl_gate_timing[ch], phy_base + PHY_SCL_GATE_TIMING);
- writel(0x02a000a0, phy_base + PHY_WRLVL_DYN_ODT);
- writel(0x00840004, phy_base + PHY_WRLVL_ON_OFF);
- writel(0x0000020d, phy_base + PHY_DLL_ADRCTRL);
- ddrphy_select_lane(phy_base, 0, 0);
- writel(0x0000008d, phy_base + PHY_DLL_TRIM_CLK);
- writel(0xa800100d, phy_base + PHY_DLL_RECALIB);
- writel(0x00005076, phy_base + PHY_SCL_LATENCY);
-}
-
-static int ddrphy_to_dly_step(void __iomem *phy_base, unsigned int freq,
- int delay)
-{
- int mdl;
-
- mdl = (readl(phy_base + PHY_DLL_ADRCTRL) & PHY_DLL_ADRCTRL_MDL_MASK) >>
- PHY_DLL_ADRCTRL_MDL_SHIFT;
-
- return DIV_ROUND_CLOSEST((long)freq * delay * mdl, 2 * 1000000L);
-}
-
-static void ddrphy_set_delay(void __iomem *phy_base, unsigned int reg,
- u32 mask, u32 incr, int dly_step)
-{
- u32 tmp;
-
- tmp = readl(phy_base + reg);
- tmp &= ~mask;
- tmp |= min_t(u32, abs(dly_step), mask);
-
- if (dly_step >= 0)
- tmp |= incr;
- else
- tmp &= ~incr;
-
- writel(tmp, phy_base + reg);
-}
-
-static void ddrphy_set_dll_recalib(void __iomem *phy_base, int dly_step)
-{
- ddrphy_set_delay(phy_base, PHY_DLL_RECALIB,
- PHY_DLL_RECALIB_TRIM_MASK, PHY_DLL_RECALIB_INCR,
- dly_step);
-}
-
-static void ddrphy_set_dll_adrctrl(void __iomem *phy_base, int dly_step)
-{
- ddrphy_set_delay(phy_base, PHY_DLL_ADRCTRL,
- PHY_DLL_ADRCTRL_TRIM_MASK, PHY_DLL_ADRCTRL_INCR,
- dly_step);
-}
-
-static void ddrphy_set_dll_trim_clk(void __iomem *phy_base, int dly_step)
-{
- ddrphy_select_lane(phy_base, 0, 0);
-
- ddrphy_set_delay(phy_base, PHY_DLL_TRIM_CLK,
- PHY_DLL_TRIM_CLK_MASK, PHY_DLL_TRIM_CLK_INCR,
- dly_step);
-}
-
-static void ddrphy_init_tail(void __iomem *phy_base, enum dram_board board,
- unsigned int freq, int ch)
-{
- int step;
-
- step = ddrphy_to_dly_step(phy_base, freq, ddrphy_adrctrl[board][ch]);
- ddrphy_set_dll_adrctrl(phy_base, step);
-
- step = ddrphy_to_dly_step(phy_base, freq, ddrphy_dlltrimclk[board][ch]);
- ddrphy_set_dll_trim_clk(phy_base, step);
-
- step = ddrphy_to_dly_step(phy_base, freq, ddrphy_dllrecalib[board][ch]);
- ddrphy_set_dll_recalib(phy_base, step);
-}
-
-static void ddrphy_shift_one_dq(void __iomem *phy_base, unsigned int reg,
- u32 mask, u32 incr, short shift_val)
-{
- u32 tmp;
- int val;
-
- tmp = readl(phy_base + reg);
-
- val = tmp & mask;
- if (!(tmp & incr))
- val = -val;
-
- val += shift_val;
-
- tmp &= ~(incr | mask);
- tmp |= min_t(u32, abs(val), mask);
- if (val >= 0)
- tmp |= incr;
-
- writel(tmp, phy_base + reg);
-}
-
-static void ddrphy_shift_dq(void __iomem *phy_base, unsigned int reg,
- u32 mask, u32 incr, u32 override,
- const short *shift_val_array)
-{
- u32 tmp;
- int dx, bit;
-
- tmp = readl(phy_base + reg);
- tmp |= override;
- writel(tmp, phy_base + reg);
-
- for (dx = 0; dx < 4; dx++) {
- for (bit = 0; bit < 8; bit++) {
- ddrphy_select_lane(phy_base,
- (PHY_BITLVL_DLY_WIDTH + 1) * dx,
- bit);
-
- ddrphy_shift_one_dq(phy_base, reg, mask, incr,
- shift_val_array[dx * 8 + bit]);
- }
- }
-
- ddrphy_select_lane(phy_base, 0, 0);
-}
-
-static int ddrphy_training(void __iomem *phy_base, enum dram_board board,
- int ch)
-{
- writel(0x0000000f, phy_base + PHY_WRLVL_AUTOINC_TRIM);
- writel(0x00010000, phy_base + PHY_DLL_TRIM_2);
- writel(0x50000000, phy_base + PHY_SCL_START);
-
- while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE)
- cpu_relax();
-
- writel(0x00000000, phy_base + PHY_DISABLE_GATING_FOR_SCL);
- writel(0xff00ff00, phy_base + PHY_SCL_DATA_0);
- writel(0xff00ff00, phy_base + PHY_SCL_DATA_1);
- writel(0xFBF8FFFF, phy_base + PHY_SCL_START_ADDR);
- writel(0x11000000, phy_base + PHY_SCL_START);
-
- while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE)
- cpu_relax();
-
- writel(0xFBF0FFFF, phy_base + PHY_SCL_START_ADDR);
- writel(0x30500000, phy_base + PHY_SCL_START);
-
- while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE)
- cpu_relax();
-
- writel(0x00000001, phy_base + PHY_DISABLE_GATING_FOR_SCL);
- writel(0x00000010, phy_base + PHY_SCL_MAIN_CLK_DELTA);
- writel(0x789b3de0, phy_base + PHY_SCL_DATA_0);
- writel(0xf10e4a56, phy_base + PHY_SCL_DATA_1);
- writel(0x11000000, phy_base + PHY_SCL_START);
-
- while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE)
- cpu_relax();
-
- writel(0x34000000, phy_base + PHY_SCL_START);
-
- while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE)
- cpu_relax();
-
- writel(0x00000003, phy_base + PHY_DISABLE_GATING_FOR_SCL);
-
- writel(0x000261c0, phy_base + PHY_DYNAMIC_WRITE_BIT_LVL);
- writel(0x00003270, phy_base + PHY_DYNAMIC_BIT_LVL);
- writel(0x011BD0C4, phy_base + PHY_DSCL_CNT);
-
- /* shift ip_dq trim */
- ddrphy_shift_dq(phy_base,
- PHY_IP_DQ_DQS_BITWISE_TRIM,
- PHY_IP_DQ_DQS_BITWISE_TRIM_MASK,
- PHY_IP_DQ_DQS_BITWISE_TRIM_INC,
- PHY_IP_DQ_DQS_BITWISE_TRIM_OVERRIDE,
- ddrphy_ip_dq_shift_val[board][ch]);
-
- /* shift op_dq trim */
- ddrphy_shift_dq(phy_base,
- PHY_OP_DQ_DM_DQS_BITWISE_TRIM,
- PHY_OP_DQ_DM_DQS_BITWISE_TRIM_MASK,
- PHY_OP_DQ_DM_DQS_BITWISE_TRIM_INC,
- PHY_OP_DQ_DM_DQS_BITWISE_TRIM_OVERRIDE,
- ddrphy_op_dq_shift_val[board][ch]);
-
- return 0;
-}
-
-/* UMC */
-static const u32 umc_initctla[DRAM_FREQ_NR] = {0x71016D11};
-static const u32 umc_initctlb[DRAM_FREQ_NR] = {0x07E390AC};
-static const u32 umc_initctlc[DRAM_FREQ_NR] = {0x00FF00FF};
-static const u32 umc_drmmr0[DRAM_FREQ_NR] = {0x00000114};
-static const u32 umc_drmmr2[DRAM_FREQ_NR] = {0x000002a0};
-
-static const u32 umc_memconf0a[DRAM_FREQ_NR][DRAM_SZ_NR] = {
- /* 256MB 512MB */
- {0x00000601, 0x00000801}, /* 1866 MHz */
-};
-
-static const u32 umc_memconf0b[DRAM_FREQ_NR][DRAM_SZ_NR] = {
- /* 256MB 512MB */
- {0x00000120, 0x00000130}, /* 1866 MHz */
-};
-
-static const u32 umc_memconfch[DRAM_FREQ_NR][DRAM_SZ_NR] = {
- /* 256MB 512MB */
- {0x00033603, 0x00033803}, /* 1866 MHz */
-};
-
-static const u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060D0D20};
-static const u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x2D211C08};
-static const u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00150C04};
-static const u32 umc_cmdctle[DRAM_FREQ_NR][DRAM_SZ_NR] = {
- /* 256MB 512MB */
- {0x0049071D, 0x0078071D}, /* 1866 MHz */
-};
-
-static const u32 umc_rdatactl[DRAM_FREQ_NR] = {0x00000610};
-static const u32 umc_wdatactl[DRAM_FREQ_NR] = {0x00000204};
-static const u32 umc_odtctl[DRAM_FREQ_NR] = {0x02000002};
-static const u32 umc_dataset[DRAM_FREQ_NR] = {0x04000000};
-
-static const u32 umc_flowctla[DRAM_FREQ_NR] = {0x0081E01E};
-static const u32 umc_directbusctrla[DRAM_CH_NR] = {
- 0x00000000, 0x00000001, 0x00000001
-};
-
-static void umc_poll_phy_init_complete(void __iomem *dc_base)
-{
- /* Wait for PHY Init Complete */
- while (!(readl(dc_base + UMC_DFISTCTLC) & BIT(0)))
- cpu_relax();
-}
-
-static int umc_dc_init(void __iomem *dc_base, unsigned int freq,
- unsigned long size, int ch)
-{
- enum dram_freq freq_e;
- enum dram_size size_e;
-
- switch (freq) {
- case 1866:
- freq_e = DRAM_FREQ_1866M;
- break;
- default:
- pr_err("unsupported DRAM frequency %ud MHz\n", freq);
- return -EINVAL;
- }
-
- switch (size) {
- case 0:
- return 0;
- case SZ_256M:
- size_e = DRAM_SZ_256M;
- break;
- case SZ_512M:
- size_e = DRAM_SZ_512M;
- break;
- default:
- pr_err("unsupported DRAM size 0x%08lx (per 16bit) for ch%d\n",
- size, ch);
- return -EINVAL;
- }
-
- writel(0x00000001, dc_base + UMC_DFICSOVRRD);
- writel(0x00000000, dc_base + UMC_DFITURNOFF);
-
- writel(umc_initctla[freq_e], dc_base + UMC_INITCTLA);
- writel(umc_initctlb[freq_e], dc_base + UMC_INITCTLB);
- writel(umc_initctlc[freq_e], dc_base + UMC_INITCTLC);
-
- writel(umc_drmmr0[freq_e], dc_base + UMC_DRMMR0);
- writel(0x00000004, dc_base + UMC_DRMMR1);
- writel(umc_drmmr2[freq_e], dc_base + UMC_DRMMR2);
- writel(0x00000000, dc_base + UMC_DRMMR3);
-
- writel(umc_memconf0a[freq_e][size_e], dc_base + UMC_MEMCONF0A);
- writel(umc_memconf0b[freq_e][size_e], dc_base + UMC_MEMCONF0B);
- writel(umc_memconfch[freq_e][size_e], dc_base + UMC_MEMCONFCH);
- writel(0x00000000, dc_base + UMC_MEMMAPSET);
-
- writel(umc_cmdctla[freq_e], dc_base + UMC_CMDCTLA);
- writel(umc_cmdctlb[freq_e], dc_base + UMC_CMDCTLB);
- writel(umc_cmdctlc[freq_e], dc_base + UMC_CMDCTLC);
- writel(umc_cmdctle[freq_e][size_e], dc_base + UMC_CMDCTLE);
-
- writel(umc_rdatactl[freq_e], dc_base + UMC_RDATACTL_D0);
- writel(umc_rdatactl[freq_e], dc_base + UMC_RDATACTL_D1);
-
- writel(umc_wdatactl[freq_e], dc_base + UMC_WDATACTL_D0);
- writel(umc_wdatactl[freq_e], dc_base + UMC_WDATACTL_D1);
- writel(umc_odtctl[freq_e], dc_base + UMC_ODTCTL_D0);
- writel(umc_odtctl[freq_e], dc_base + UMC_ODTCTL_D1);
- writel(umc_dataset[freq_e], dc_base + UMC_DATASET);
-
- writel(0x00400020, dc_base + UMC_DCCGCTL);
- writel(0x00000003, dc_base + UMC_ACSSETA);
- writel(0x00000103, dc_base + UMC_FLOWCTLG);
- writel(0x00010200, dc_base + UMC_ACSSETB);
-
- writel(umc_flowctla[freq_e], dc_base + UMC_FLOWCTLA);
- writel(0x00004444, dc_base + UMC_FLOWCTLC);
- writel(0x00000000, dc_base + UMC_DFICUPDCTLA);
-
- writel(0x00202000, dc_base + UMC_FLOWCTLB);
- writel(0x00000000, dc_base + UMC_BSICMAPSET);
- writel(0x00000000, dc_base + UMC_ERRMASKA);
- writel(0x00000000, dc_base + UMC_ERRMASKB);
-
- writel(umc_directbusctrla[ch], dc_base + UMC_DIRECTBUSCTRLA);
-
- writel(0x00000001, dc_base + UMC_INITSET);
- /* Wait for PHY Init Complete */
- while (readl(dc_base + UMC_INITSTAT) & BIT(0))
- cpu_relax();
-
- writel(0x2A0A0A00, dc_base + UMC_SPCSETB);
- writel(0x00000000, dc_base + UMC_DFICSOVRRD);
-
- return 0;
-}
-
-static int umc_ch_init(void __iomem *umc_ch_base, void __iomem *phy_ch_base,
- enum dram_board board, unsigned int freq,
- unsigned long size, int ch)
-{
- void __iomem *dc_base = umc_ch_base + 0x00011000;
- void __iomem *phy_base = phy_ch_base;
- int ret;
-
- /* PHY Update Mode (ON) */
- writel(0x8000003f, dc_base + UMC_DFIPUPDCTLA);
-
- /* deassert PHY reset signals */
- writel(UMC_DIOCTLA_CTL_NRST | UMC_DIOCTLA_CFG_NRST,
- dc_base + UMC_DIOCTLA);
-
- ddrphy_init(phy_base, board, ch);
-
- umc_poll_phy_init_complete(dc_base);
-
- ddrphy_init_tail(phy_base, board, freq, ch);
-
- ret = umc_dc_init(dc_base, freq, size, ch);
- if (ret)
- return ret;
-
- ret = ddrphy_training(phy_base, board, ch);
- if (ret)
- return ret;
-
- return 0;
-}
-
-static void um_init(void __iomem *um_base)
-{
- writel(0x000000ff, um_base + UMC_MBUS0);
- writel(0x000000ff, um_base + UMC_MBUS1);
- writel(0x000000ff, um_base + UMC_MBUS2);
- writel(0x00000001, um_base + UMC_MBUS3);
- writel(0x00000001, um_base + UMC_MBUS4);
- writel(0x00000001, um_base + UMC_MBUS5);
- writel(0x00000001, um_base + UMC_MBUS6);
- writel(0x00000001, um_base + UMC_MBUS7);
- writel(0x00000001, um_base + UMC_MBUS8);
- writel(0x00000001, um_base + UMC_MBUS9);
- writel(0x00000001, um_base + UMC_MBUS10);
-}
-
-int uniphier_ld20_umc_init(const struct uniphier_board_data *bd)
-{
- void __iomem *um_base = (void __iomem *)0x5b600000;
- void __iomem *umc_ch_base = (void __iomem *)0x5b800000;
- void __iomem *phy_ch_base = (void __iomem *)0x6e200000;
- enum dram_board board;
- int ch, ret;
-
- switch (UNIPHIER_BD_BOARD_GET_TYPE(bd->flags)) {
- case UNIPHIER_BD_BOARD_LD20_REF:
- board = DRAM_BOARD_LD20_REF;
- break;
- case UNIPHIER_BD_BOARD_LD20_GLOBAL:
- board = DRAM_BOARD_LD20_GLOBAL;
- break;
- case UNIPHIER_BD_BOARD_LD20_C1:
- board = DRAM_BOARD_LD20_C1;
- break;
- case UNIPHIER_BD_BOARD_LD21_REF:
- board = DRAM_BOARD_LD21_REF;
- break;
- case UNIPHIER_BD_BOARD_LD21_GLOBAL:
- board = DRAM_BOARD_LD21_GLOBAL;
- break;
- default:
- pr_err("unsupported board type %d\n",
- UNIPHIER_BD_BOARD_GET_TYPE(bd->flags));
- return -EINVAL;
- }
-
- for (ch = 0; ch < DRAM_CH_NR; ch++) {
- unsigned long size = bd->dram_ch[ch].size;
- unsigned int width = bd->dram_ch[ch].width;
-
- if (size) {
- ret = umc_ch_init(umc_ch_base, phy_ch_base, board,
- bd->dram_freq, size / (width / 16),
- ch);
- if (ret) {
- pr_err("failed to initialize UMC ch%d\n", ch);
- return ret;
- }
- }
-
- umc_ch_base += 0x00200000;
- phy_ch_base += 0x00004000;
- }
-
- um_init(um_base);
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2016 Socionext Inc.
- */
-
-#ifndef UMC_LD20_REGS_H
-#define UMC_LD20_REGS_H
-
-#define UMC_CMDCTLA 0x00000000
-#define UMC_CMDCTLB 0x00000004
-#define UMC_CMDCTLC 0x00000008
-#define UMC_INITCTLA 0x00000020
-#define UMC_INITCTLB 0x00000024
-#define UMC_INITCTLC 0x00000028
-#define UMC_DRMMR0 0x00000030
-#define UMC_DRMMR1 0x00000034
-#define UMC_DRMMR2 0x00000038
-#define UMC_DRMMR3 0x0000003C
-#define UMC_INITSET 0x00000040
-#define UMC_INITSTAT 0x00000044
-#define UMC_CMDCTLE 0x00000050
-#define UMC_CMDCTLF 0x00000054
-#define UMC_CMDCTLG 0x00000058
-#define UMC_SPCSETB 0x00000084
-#define UMC_SPCSETB_AREFMD_MASK (0x3) /* Auto Refresh Mode */
-#define UMC_SPCSETB_AREFMD_ARB (0x0) /* control by arbitor */
-#define UMC_SPCSETB_AREFMD_CONT (0x1) /* control by DRAMCONT */
-#define UMC_SPCSETB_AREFMD_REG (0x2) /* control by register */
-#define UMC_ACSSETA 0x000000C0
-#define UMC_ACSSETB 0x000000C4
-#define UMC_MEMCONF0A 0x00000200
-#define UMC_MEMCONF0B 0x00000204
-#define UMC_MEMCONFCH 0x00000240
-#define UMC_MEMMAPSET 0x00000250
-#define UMC_FLOWCTLA 0x00000400
-#define UMC_FLOWCTLB 0x00000404
-#define UMC_FLOWCTLC 0x00000408
-#define UMC_ACFETCHCTRL 0x00000460
-#define UMC_FLOWCTLG 0x00000508
-#define UMC_RDATACTL_D0 0x00000600
-#define UMC_WDATACTL_D0 0x00000604
-#define UMC_RDATACTL_D1 0x00000608
-#define UMC_WDATACTL_D1 0x0000060C
-#define UMC_DATASET 0x00000610
-#define UMC_ODTCTL_D0 0x00000618
-#define UMC_ODTCTL_D1 0x0000061C
-#define UMC_RESPCTL 0x00000624
-#define UMC_DIRECTBUSCTRLA 0x00000680
-#define UMC_DEBUGC 0x00000718
-#define UMC_DCCGCTL 0x00000720
-#define UMC_DICGCTLA 0x00000724
-#define UMC_DICGCTLB 0x00000728
-#define UMC_ERRMASKA 0x00000958
-#define UMC_ERRMASKB 0x0000095C
-#define UMC_BSICMAPSET 0x00000988
-#define UMC_DIOCTLA 0x00000C00
-#define UMC_DIOCTLA_CTL_NRST BIT(8) /* ctl_rst_n */
-#define UMC_DIOCTLA_CFG_NRST BIT(0) /* cfg_rst_n */
-#define UMC_DFISTCTLC 0x00000C18
-#define UMC_DFICUPDCTLA 0x00000C20
-#define UMC_DFIPUPDCTLA 0x00000C30
-#define UMC_DFICSOVRRD 0x00000C84
-#define UMC_DFITURNOFF 0x00000C88
-
-/* UM registers */
-#define UMC_MBUS0 0x00080004
-#define UMC_MBUS1 0x00081004
-#define UMC_MBUS2 0x00082004
-#define UMC_MBUS3 0x00000C78
-#define UMC_MBUS4 0x00000CF8
-#define UMC_MBUS5 0x00000E78
-#define UMC_MBUS6 0x00000EF8
-#define UMC_MBUS7 0x00001278
-#define UMC_MBUS8 0x000012F8
-#define UMC_MBUS9 0x00002478
-#define UMC_MBUS10 0x000024F8
-
-/* UMC1 register */
-#define UMC_SIORST 0x00000728
-#define UMC_VO0RST 0x0000073c
-#define UMC_VPERST 0x00000744
-#define UMC_RGLRST 0x00000750
-#define UMC_A2DRST 0x00000764
-#define UMC_DMDRST 0x00000770
-
-#endif /* UMC_LD20_REGS_H */
#define UNIPHIER_BD_DRAM_SPARSE BIT(9)
#define UNIPHIER_BD_DDR3PLUS BIT(8)
-
-#define UNIPHIER_BD_BOARD_GET_TYPE(f) ((f) & 0x7)
-#define UNIPHIER_BD_BOARD_LD20_REF 0 /* LD20 reference */
-#define UNIPHIER_BD_BOARD_LD20_GLOBAL 1 /* LD20 TV Set */
-#define UNIPHIER_BD_BOARD_LD20_C1 2 /* LD20 TV Set C1 */
-#define UNIPHIER_BD_BOARD_LD21_REF 3 /* LD21 reference */
-#define UNIPHIER_BD_BOARD_LD21_GLOBAL 4 /* LD21 TV Set */
};
const struct uniphier_board_data *uniphier_get_board_param(void);
int uniphier_sld8_init(const struct uniphier_board_data *bd);
int uniphier_pro5_init(const struct uniphier_board_data *bd);
int uniphier_pxs2_init(const struct uniphier_board_data *bd);
-int uniphier_ld11_init(const struct uniphier_board_data *bd);
-int uniphier_ld20_init(const struct uniphier_board_data *bd);
#if defined(CONFIG_MICRO_SUPPORT_CARD)
void uniphier_sbc_init_admulti(void);
int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd);
int uniphier_pro5_dpll_init(const struct uniphier_board_data *bd);
int uniphier_pxs2_dpll_init(const struct uniphier_board_data *bd);
-int uniphier_ld11_dpll_init(const struct uniphier_board_data *bd);
-int uniphier_ld20_dpll_init(const struct uniphier_board_data *bd);
void uniphier_sld3_early_clk_init(void);
-void uniphier_ld11_early_clk_init(void);
void uniphier_sld3_dram_clk_init(void);
void uniphier_pro5_dram_clk_init(void);
void uniphier_pxs2_dram_clk_init(void);
-void uniphier_ld11_dram_clk_init(void);
-void uniphier_ld20_dram_clk_init(void);
int uniphier_sld3_umc_init(const struct uniphier_board_data *bd);
int uniphier_ld4_umc_init(const struct uniphier_board_data *bd);
int uniphier_sld8_umc_init(const struct uniphier_board_data *bd);
int uniphier_pro5_umc_init(const struct uniphier_board_data *bd);
int uniphier_pxs2_umc_init(const struct uniphier_board_data *bd);
-int uniphier_ld20_umc_init(const struct uniphier_board_data *bd);
-int uniphier_ld11_umc_init(const struct uniphier_board_data *bd);
void uniphier_sld3_pll_init(void);
void uniphier_ld4_pll_init(void);
int uniphier_have_internal_stm(void);
int uniphier_boot_from_backend(void);
int uniphier_pin_init(const char *pinconfig_name);
-void uniphier_smp_kick_all_cpus(void);
-void cci500_init(unsigned int nr_slaves);
#undef pr_warn
#define pr_warn(fmt, args...) printf(fmt, ##args)
.umc_init = uniphier_pxs2_umc_init,
},
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_LD11)
- {
- .soc_id = UNIPHIER_LD11_ID,
- .early_clk_init = uniphier_ld11_early_clk_init,
- .dpll_init = uniphier_ld11_dpll_init,
- .memconf_init = uniphier_memconf_2ch_init,
- .dram_clk_init = uniphier_ld11_dram_clk_init,
- .umc_init = uniphier_ld11_umc_init,
- },
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_LD20)
- {
- .soc_id = UNIPHIER_LD20_ID,
- .early_clk_init = uniphier_ld11_early_clk_init,
- .dpll_init = uniphier_ld20_dpll_init,
- .memconf_init = uniphier_memconf_3ch_init,
- .dram_clk_init = uniphier_ld20_dram_clk_init,
- .umc_init = uniphier_ld20_umc_init,
- },
-#endif
};
UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_spl_initdata, uniphier_spl_initdata)
if (initdata->bcu_init)
initdata->bcu_init(bd);
-
initdata->early_clk_init();
-
#ifdef CONFIG_SPL_SERIAL_SUPPORT
preloader_console_init();
#endif
pr_err("failed to init DRAM\n");
hang();
}
-
-#ifdef CONFIG_ARM64
- dcache_disable();
-#endif
}
config MCF52x2
bool
+ imply ENV_IS_IN_FLASH
config MCF523x
bool
config MCF532x
bool
+ imply ENV_IS_IN_FLASH
config MCF537x
bool
config MCF547x_8x
bool
+ imply ENV_IS_IN_FLASH
# processor type
config M5208
config M5282
bool
select MCF52x2
+ imply ENV_IS_IN_FLASH
config M5307
bool
config M547x
bool
select MCF547x_8x
+ imply ENV_IS_IN_FLASH
config M548x
bool
select MCF547x_8x
+ imply ENV_IS_IN_FLASH
choice
prompt "Target select"
config TARGET_M5475EVB
bool "Support M5475EVB"
select M547x
+ imply ENV_IS_IN_FLASH
config TARGET_M5485EVB
bool "Support M5485EVB"
select M548x
+ imply ENV_IS_IN_FLASH
config TARGET_AMCORE
bool "Support AMCORE"
select OF_CONTROL
select DM
select DM_SERIAL
+ select ENV_IS_IN_FLASH
endchoice
mts rshr, r1
addi r1, r1, -4 /* Decrement SP to top of memory */
#else
-#if defined(CONFIG_SYS_MALLOC_F_LEN)
- addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET - CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+ addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET - CONFIG_VAL(SYS_MALLOC_F_LEN)
#else
addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET
#endif
#ifndef CONFIG_SPL_BUILD
or r5, r0, r0 /* flags - empty */
addi r31, r0, _gd
-#if defined(CONFIG_SYS_MALLOC_F_LEN)
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
addi r6, r0, CONFIG_SYS_INIT_SP_OFFSET
swi r6, r31, GD_MALLOC_BASE
#endif
brai board_init_f
#else
addi r31, r0, _gd
-#if defined(CONFIG_SYS_MALLOC_F_LEN)
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
addi r6, r0, CONFIG_SPL_STACK_ADDR
swi r6, r31, GD_MALLOC_BASE
#endif
select SUPPORTS_CPU_MIPS64_R1
select SUPPORTS_CPU_MIPS64_R2
select ROM_EXCEPTION_VECTORS
+ imply ENV_IS_IN_FLASH
config TARGET_MALTA
bool "Support malta"
select SWAP_IO_SPACE
select MIPS_L1_CACHE_SHIFT_6
select ROM_EXCEPTION_VECTORS
+ imply ENV_IS_IN_FLASH
config TARGET_VCT
bool "Support vct"
select CPU
select RAM
select SYSRESET
+ imply ENV_IS_NOWHERE
config MACH_PIC32
bool "Support Microchip PIC32"
select SUPPORTS_CPU_MIPS64_R2
select SUPPORTS_CPU_MIPS64_R6
select ROM_EXCEPTION_VECTORS
+ imply ENV_IS_IN_FLASH
config TARGET_XILFPGA
bool "Support Imagination Xilfpga"
bool "MIPS64 Release 2"
depends on SUPPORTS_CPU_MIPS64_R2
select 64BIT
+ imply ENV_IS_IN_FLASH
help
Choose this option to build a kernel for release 2 through 5 of the
MIPS64 architecture.
--- /dev/null
+#
+# Copyright (c) 2017 Imagination Technologies Ltd.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+PHONY := __archpost
+__archpost:
+
+-include include/config/auto.conf
+include scripts/Kbuild.include
+
+CMD_RELOCS = tools/mips-relocs
+quiet_cmd_relocs = RELOCS $@
+ cmd_relocs = $(CMD_RELOCS) $@
+
+u-boot: FORCE
+ @true
+ $(call if_changed,relocs)
+
+.PHONY: FORCE
+
+FORCE:
# LDFLAGS_vmlinux += -G 0 -static -n -nostdlib
# MODFLAGS += -mlong-calls
#
-# On the other hand, we want PIC in the U-Boot code to relocate it from ROM
-# to RAM. $28 is always used as gp.
-#
-ifdef CONFIG_SPL_BUILD
-PF_ABICALLS := -mno-abicalls
-PF_PIC := -fno-pic
-PF_PIE :=
-else
-PF_ABICALLS := -mabicalls
-PF_PIC := -fpic
-PF_PIE := -pie
-PF_OBJCOPY := -j .got -j .rel.dyn -j .padding
-PF_OBJCOPY += -j .dtb.init.rodata
+ifndef CONFIG_SPL_BUILD
+OBJCOPYFLAGS += -j .got -j .rel -j .padding -j .dtb.init.rodata
+LDFLAGS_FINAL += --emit-relocs
endif
-PLATFORM_CPPFLAGS += -G 0 $(PF_ABICALLS) $(PF_PIC)
+PLATFORM_CPPFLAGS += -G 0 -mno-abicalls -fno-pic
PLATFORM_CPPFLAGS += -msoft-float
PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
-LDFLAGS_FINAL += --gc-sections $(PF_PIE)
+LDFLAGS_FINAL += --gc-sections
OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list
-OBJCOPYFLAGS += $(PF_OBJCOPY)
sp, sp, GD_SIZE # reserve space for gd
and sp, sp, t0 # force 16 byte alignment
move k0, sp # save gd pointer
-#ifdef CONFIG_SYS_MALLOC_F_LEN
- li t2, CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+ li t2, CONFIG_VAL(SYS_MALLOC_F_LEN)
PTR_SUBU \
sp, sp, t2 # reserve space for early malloc
and sp, sp, t0 # force 16 byte alignment
blt t0, t1, 1b
PTR_ADDIU t0, PTRSIZE
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
PTR_S sp, GD_MALLOC_BASE(k0) # gd->malloc_base offset
#endif
.endm
ehb
#endif
- /*
- * Initialize $gp, force pointer sized alignment of bal instruction to
- * forbid the compiler to put nop's between bal and _gp. This is
- * required to keep _gp and ra aligned to 8 byte.
- */
- .align PTRLOG
- bal 1f
- nop
- PTR _gp
-1:
- PTR_L gp, 0(ra)
-
#ifdef CONFIG_MIPS_CM
PTR_LA t9, mips_cm_map
jalr t9
move ra, zero
END(_start)
-
-/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- * a0 = addr_sp
- * a1 = gd
- * a2 = destination address
- */
-ENTRY(relocate_code)
- move sp, a0 # set new stack pointer
- move fp, sp
-
- move s0, a1 # save gd in s0
- move s2, a2 # save destination address in s2
-
- PTR_LI t0, CONFIG_SYS_MONITOR_BASE
- PTR_SUB s1, s2, t0 # s1 <-- relocation offset
-
- PTR_LA t2, __image_copy_end
- move t1, a2
-
- /*
- * t0 = source address
- * t1 = target address
- * t2 = source end address
- */
-1:
- PTR_L t3, 0(t0)
- PTR_S t3, 0(t1)
- PTR_ADDU t0, PTRSIZE
- blt t0, t2, 1b
- PTR_ADDU t1, PTRSIZE
-
- /*
- * Now we want to update GOT.
- *
- * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
- * generated by GNU ld. Skip these reserved entries from relocation.
- */
- PTR_LA t3, num_got_entries
- PTR_LA t8, _GLOBAL_OFFSET_TABLE_
- PTR_ADD t8, s1 # t8 now holds relocated _G_O_T_
- PTR_ADDIU t8, t8, 2 * PTRSIZE # skipping first two entries
- PTR_LI t2, 2
-1:
- PTR_L t1, 0(t8)
- beqz t1, 2f
- PTR_ADD t1, s1
- PTR_S t1, 0(t8)
-2:
- PTR_ADDIU t2, 1
- blt t2, t3, 1b
- PTR_ADDIU t8, PTRSIZE
-
- /* Update dynamic relocations */
- PTR_LA t1, __rel_dyn_start
- PTR_LA t2, __rel_dyn_end
-
- b 2f # skip first reserved entry
- PTR_ADDIU t1, 2 * PTRSIZE
-
-1:
- lw t8, -4(t1) # t8 <-- relocation info
-
- PTR_LI t3, MIPS_RELOC
- bne t8, t3, 2f # skip non-MIPS_RELOC entries
- nop
-
- PTR_L t3, -(2 * PTRSIZE)(t1) # t3 <-- location to fix up in FLASH
-
- PTR_L t8, 0(t3) # t8 <-- original pointer
- PTR_ADD t8, s1 # t8 <-- adjusted pointer
-
- PTR_ADD t3, s1 # t3 <-- location to fix up in RAM
- PTR_S t8, 0(t3)
-
-2:
- blt t1, t2, 1b
- PTR_ADDIU t1, 2 * PTRSIZE # each rel.dyn entry is 2*PTRSIZE bytes
-
- /*
- * Flush caches to ensure our newly modified instructions are visible
- * to the instruction cache. We're still running with the old GOT, so
- * apply the reloc offset to the start address.
- */
- PTR_LA a0, __text_start
- PTR_LA a1, __text_end
- PTR_SUB a1, a1, a0
- PTR_LA t9, flush_cache
- jalr t9
- PTR_ADD a0, s1
-
- PTR_ADD gp, s1 # adjust gp
-
- /*
- * Clear BSS
- *
- * GOT is now relocated. Thus __bss_start and __bss_end can be
- * accessed directly via $gp.
- */
- PTR_LA t1, __bss_start # t1 <-- __bss_start
- PTR_LA t2, __bss_end # t2 <-- __bss_end
-
-1:
- PTR_S zero, 0(t1)
- blt t1, t2, 1b
- PTR_ADDIU t1, PTRSIZE
-
- move a0, s0 # a0 <-- gd
- move a1, s2
- PTR_LA t9, board_init_r
- jr t9
- move ra, zero
-
- END(relocate_code)
*(.data*)
}
- . = .;
- _gp = ALIGN(16) + 0x7ff0;
-
- .got : {
- *(.got)
- }
-
- num_got_entries = SIZEOF(.got) >> PTR_COUNT_SHIFT;
-
. = ALIGN(4);
.sdata : {
*(.sdata*)
__image_copy_end = .;
__init_end = .;
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel.dyn)
- __rel_dyn_end = .;
- }
-
- .padding : {
- /*
- * Workaround for a binutils feature (or bug?).
- *
- * The GNU ld from binutils puts the dynamic relocation
- * entries into the .rel.dyn section. Sometimes it
- * allocates more dynamic relocation entries than it needs
- * and the unused slots are set to R_MIPS_NONE entries.
- *
- * However the size of the .rel.dyn section in the ELF
- * section header does not cover the unused entries, so
- * objcopy removes those during stripping.
- *
- * Create a small section here to avoid that.
- */
- LONG(0xFFFFFFFF)
+ /*
+ * .rel must come last so that the mips-relocs tool can shrink
+ * the section size & the PT_LOAD program header filesz.
+ */
+ .rel : {
+ __rel_start = .;
+ BYTE(0x0)
+ . += (32 * 1024) - 1;
}
_end = .;
- .bss __rel_dyn_start (OVERLAY) : {
+ .bss __rel_start (OVERLAY) : {
__bss_start = .;
*(.sbss.*)
*(.bss.*)
--- /dev/null
+/*
+ * MIPS Relocations
+ *
+ * Copyright (c) 2017 Imagination Technologies Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_MIPS_RELOCS_H__
+#define __ASM_MIPS_RELOCS_H__
+
+#define R_MIPS_NONE 0
+#define R_MIPS_32 2
+#define R_MIPS_26 4
+#define R_MIPS_HI16 5
+#define R_MIPS_LO16 6
+#define R_MIPS_PC16 10
+#define R_MIPS_64 18
+#define R_MIPS_HIGHER 28
+#define R_MIPS_HIGHEST 29
+#define R_MIPS_PC21_S2 60
+#define R_MIPS_PC26_S2 61
+
+#endif /* __ASM_MIPS_RELOCS_H__ */
#include <asm-generic/sections.h>
+/**
+ * __rel_start: Relocation data generated by the mips-relocs tool
+ *
+ * See arch/mips/lib/reloc.c for details on the format & use of this data.
+ */
+extern uint8_t __rel_start[];
+
#endif
obj-y += cache.o
obj-y += cache_init.o
obj-y += genex.o
+obj-y += reloc.o
obj-y += stack.o
obj-y += traps.o
boot_reloc_fdt(images);
boot_setup_fdt(images);
} else {
- if (CONFIG_IS_ENABLED(CONFIG_MIPS_BOOT_ENV_LEGACY))
- linux_env_legacy(images);
-
if (CONFIG_IS_ENABLED(MIPS_BOOT_CMDLINE_LEGACY)) {
linux_cmdline_legacy(images);
- if (!CONFIG_IS_ENABLED(CONFIG_MIPS_BOOT_ENV_LEGACY))
+ if (!CONFIG_IS_ENABLED(MIPS_BOOT_ENV_LEGACY))
linux_cmdline_append(images);
linux_cmdline_dump();
}
+
+ if (CONFIG_IS_ENABLED(MIPS_BOOT_ENV_LEGACY))
+ linux_env_legacy(images);
}
}
--- /dev/null
+/*
+ * MIPS Relocation
+ *
+ * Copyright (c) 2017 Imagination Technologies Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Relocation data, found in the .rel section, is generated by the mips-relocs
+ * tool & contains a record of all locations in the U-Boot binary that need to
+ * be fixed up during relocation.
+ *
+ * The data is a sequence of unsigned integers, which are of somewhat arbitrary
+ * size. This is achieved by encoding integers as a sequence of bytes, each of
+ * which contains 7 bits of data with the most significant bit indicating
+ * whether any further bytes need to be read. The least significant bits of the
+ * integer are found in the first byte - ie. it somewhat resembles little
+ * endian.
+ *
+ * Each pair of two integers represents a relocation that must be applied. The
+ * first integer represents the type of relocation as a standard ELF relocation
+ * type (ie. R_MIPS_*). The second integer represents the offset at which to
+ * apply the relocation, relative to the previous relocation or for the first
+ * relocation the start of the relocated .text section.
+ *
+ * The end of the relocation data is indicated when type R_MIPS_NONE (0) is
+ * read, at which point no further integers should be read. That is, the
+ * terminating R_MIPS_NONE reloc includes no offset.
+ */
+
+#include <common.h>
+#include <asm/relocs.h>
+#include <asm/sections.h>
+
+/**
+ * read_uint() - Read an unsigned integer from the buffer
+ * @buf: pointer to a pointer to the reloc buffer
+ *
+ * Read one whole unsigned integer from the relocation data pointed to by @buf,
+ * advancing @buf past the bytes encoding the integer.
+ *
+ * Returns: the integer read from @buf
+ */
+static unsigned long read_uint(uint8_t **buf)
+{
+ unsigned long val = 0;
+ unsigned int shift = 0;
+ uint8_t new;
+
+ do {
+ new = *(*buf)++;
+ val |= (new & 0x7f) << shift;
+ shift += 7;
+ } while (new & 0x80);
+
+ return val;
+}
+
+/**
+ * apply_reloc() - Apply a single relocation
+ * @type: the type of reloc (R_MIPS_*)
+ * @addr: the address that the reloc should be applied to
+ * @off: the relocation offset, ie. number of bytes we're moving U-Boot by
+ *
+ * Apply a single relocation of type @type at @addr. This function is
+ * intentionally simple, and does the bare minimum needed to fixup the
+ * relocated U-Boot - in particular, it does not check for overflows.
+ */
+static void apply_reloc(unsigned int type, void *addr, long off)
+{
+ uint32_t u32;
+
+ switch (type) {
+ case R_MIPS_26:
+ u32 = *(uint32_t *)addr;
+ u32 = (u32 & GENMASK(31, 26)) |
+ ((u32 + (off >> 2)) & GENMASK(25, 0));
+ *(uint32_t *)addr = u32;
+ break;
+
+ case R_MIPS_32:
+ *(uint32_t *)addr += off;
+ break;
+
+ case R_MIPS_64:
+ *(uint64_t *)addr += off;
+ break;
+
+ case R_MIPS_HI16:
+ *(uint32_t *)addr += off >> 16;
+ break;
+
+ default:
+ panic("Unhandled reloc type %u\n", type);
+ }
+}
+
+/**
+ * relocate_code() - Relocate U-Boot, generally from flash to DDR
+ * @start_addr_sp: new stack pointer
+ * @new_gd: pointer to relocated global data
+ * @relocaddr: the address to relocate to
+ *
+ * Relocate U-Boot from its current location (generally in flash) to a new one
+ * (generally in DDR). This function will copy the U-Boot binary & apply
+ * relocations as necessary, then jump to board_init_r in the new build of
+ * U-Boot. As such, this function does not return.
+ */
+void relocate_code(ulong start_addr_sp, gd_t *new_gd, ulong relocaddr)
+{
+ unsigned long addr, length, bss_len;
+ uint8_t *buf, *bss_start;
+ unsigned int type;
+ long off;
+
+ /*
+ * Ensure that we're relocating by an offset which is a multiple of
+ * 64KiB, ie. doesn't change the least significant 16 bits of any
+ * addresses. This allows us to discard R_MIPS_LO16 relocs, saving
+ * space in the U-Boot binary & complexity in handling them.
+ */
+ off = relocaddr - (unsigned long)__text_start;
+ if (off & 0xffff)
+ panic("Mis-aligned relocation\n");
+
+ /* Copy U-Boot to RAM */
+ length = __image_copy_end - __text_start;
+ memcpy((void *)relocaddr, __text_start, length);
+
+ /* Now apply relocations to the copy in RAM */
+ buf = __rel_start;
+ addr = relocaddr;
+ while (true) {
+ type = read_uint(&buf);
+ if (type == R_MIPS_NONE)
+ break;
+
+ addr += read_uint(&buf) << 2;
+ apply_reloc(type, (void *)addr, off);
+ }
+
+ /* Ensure the icache is coherent */
+ flush_cache(relocaddr, length);
+
+ /* Clear the .bss section */
+ bss_start = (uint8_t *)((unsigned long)__bss_start + off);
+ bss_len = (unsigned long)&__bss_end - (unsigned long)__bss_start;
+ memset(bss_start, 0, bss_len);
+
+ /* Jump to the relocated U-Boot */
+ asm volatile(
+ "move $29, %0\n"
+ " move $4, %1\n"
+ " move $5, %2\n"
+ " move $31, $0\n"
+ " jr %3"
+ : /* no outputs */
+ : "r"(start_addr_sp),
+ "r"(new_gd),
+ "r"(relocaddr),
+ "r"((unsigned long)board_init_r + off));
+
+ /* Since we jumped to the new U-Boot above, we won't get here */
+ unreachable();
+}
bool "MPC86xx"
select SYS_FSL_DDR
select SYS_FSL_DDR_BE
+ imply ENV_IS_IN_FLASH
config 8xx
bool "MPC8xx"
config TARGET_SBC8349
bool "Support sbc8349"
+ imply ENV_IS_IN_FLASH
config TARGET_VE8313
bool "Support ve8313"
config TARGET_MPC832XEMDS
bool "Support MPC832XEMDS"
select BOARD_EARLY_INIT_F
+ imply ENV_IS_IN_FLASH
config TARGET_MPC8349EMDS
bool "Support MPC8349EMDS"
config TARGET_MPC8349ITX
bool "Support MPC8349ITX"
imply CMD_IRQ
+ imply ENV_IS_IN_FLASH
config TARGET_MPC837XEMDS
bool "Support MPC837XEMDS"
bool "Support suvd3"
imply CMD_CRAMFS
imply FS_CRAMFS
+ imply ENV_IS_IN_FLASH
config TARGET_TUXX1
bool "Support tuxx1"
imply CMD_CRAMFS
imply FS_CRAMFS
+ imply ENV_IS_IN_FLASH
config TARGET_TQM834X
bool "Support TQM834x"
config TARGET_STRIDER
bool "Support strider"
select SYS_FSL_ERRATUM_ESDHC111
+ imply ENV_IS_IN_FLASH
endchoice
mtspr SRR1, r3
rfi
- .globl get_svr
-get_svr:
- mfspr r3, SVR
- blr
-
- .globl get_pvr
-get_pvr:
- mfspr r3, PVR
- blr
-
.globl ppcDWstore
ppcDWstore:
lfd 1, 0(r4)
cmplw r3, r4
bne 1b
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
-#if CONFIG_SYS_MALLOC_F_LEN + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
-#error "CONFIG_SYS_MALLOC_F_LEN too large to fit into initial RAM."
+#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
+#error "SYS_MALLOC_F_LEN too large to fit into initial RAM."
#endif
/* r3 = new stack pointer / pre-reloc malloc area */
- subi r3, r3, CONFIG_SYS_MALLOC_F_LEN
+ subi r3, r3, CONFIG_VAL(SYS_MALLOC_F_LEN)
/* Set pointer to pre-reloc malloc area in GD */
stw r3, GD_MALLOC_BASE(r4)
do_bedbug_breakpoint( regs );
#endif
}
-
-/* Probe an address by reading. If not present, return -1, otherwise
- * return 0.
- */
-int addr_probe(uint *addr)
-{
-#if 0
- int retval;
-
- __asm__ __volatile__( \
- "1: lwz %0,0(%1)\n" \
- " eieio\n" \
- " li %0,0\n" \
- "2:\n" \
- ".section .fixup,\"ax\"\n" \
- "3: li %0,-1\n" \
- " b 2b\n" \
- ".section __ex_table,\"a\"\n" \
- " .align 2\n" \
- " .long 1b,3b\n" \
- ".text" \
- : "=r" (retval) : "r"(addr));
-
- return (retval);
-#endif
- return 0;
-}
config TARGET_SBC8548
bool "Support sbc8548"
select ARCH_MPC8548
+ imply ENV_IS_IN_FLASH
config TARGET_SOCRATES
bool "Support socrates"
config TARGET_MPC8548CDS
bool "Support MPC8548CDS"
select ARCH_MPC8548
+ imply ENV_IS_IN_FLASH
config TARGET_MPC8555CDS
bool "Support MPC8555CDS"
select SYS_PPC_E500_USE_DEBUG_TLB
select FSL_IFC
imply CMD_EEPROM
+ imply CMD_MTDPARTS
config ARCH_C29X
bool
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+ imply ENV_IS_IN_FLASH
config ARCH_MPC8555
bool
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
select FSL_ELBC
+ imply ENV_IS_IN_FLASH
config ARCH_P1010
bool
select SYS_PPC_E500_USE_DEBUG_TLB
select FSL_IFC
imply CMD_EEPROM
+ imply CMD_MTDPARTS
imply CMD_SATA
config ARCH_P1011
select SYS_FSL_SEC_COMPAT_5
select FSL_IFC
imply CMD_EEPROM
+ imply CMD_MTDPARTS
config ARCH_T1040
bool
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5
select FSL_IFC
+ imply CMD_MTDPARTS
imply CMD_SATA
config ARCH_T1042
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5
select FSL_IFC
+ imply CMD_MTDPARTS
imply CMD_SATA
config ARCH_T2080
#include <post.h>
#include <asm/processor.h>
#include <fsl_ddr_sdram.h>
+#include <asm/ppc.h>
DECLARE_GLOBAL_DATA_PTR;
* Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
* parameters for IFC and TLBs
*/
-void mpc85xx_reginfo(void)
+void print_reginfo(void)
{
print_tlbcam();
print_laws();
#include <post.h>
#endif
-int interrupt_init_cpu(unsigned int *decrementer_count)
+int interrupt_init_cpu(unsigned *decrementer_count)
{
ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
-#ifdef CONFIG_SYS_MALLOC_F_LEN
-
-#if CONFIG_SYS_MALLOC_F_LEN + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
-#error "CONFIG_SYS_MALLOC_F_LEN too large to fit into initial RAM."
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
+#error "SYS_MALLOC_F_LEN too large to fit into initial RAM."
#endif
/* Leave 16+ byte for back chain termination and NULL return address */
- subi r3,r3,((CONFIG_SYS_MALLOC_F_LEN+16+15)&~0xf)
+ subi r3,r3,((CONFIG_VAL(SYS_MALLOC_F_LEN)+16+15)&~0xf)
#endif
/* End of RAM */
cmplw r4,r3
bne 1b
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
ori r4,r4,(CONFIG_SYS_GBL_DATA_OFFSET)@l
andi. r3,r3,L1CSR0_DCE
blr
- .globl get_pvr
-get_pvr:
- mfspr r3,PVR
- blr
-
- .globl get_svr
-get_svr:
- mfspr r3,SVR
- blr
-
/*------------------------------------------------------------------------------- */
/* Function: in8 */
/* Description: Input 8 bits */
do_bedbug_breakpoint( regs );
#endif
}
-
-/* Probe an address by reading. If not present, return -1, otherwise
- * return 0.
- */
-int addr_probe(uint *addr)
-{
- return 0;
-}
select FSL_LAW
select SYS_FSL_HAS_DDR1
select SYS_FSL_HAS_DDR2
+ imply ENV_IS_IN_FLASH
config FSL_LAW
bool
#include <asm/mmu.h>
#include <mpc86xx.h>
#include <asm/fsl_law.h>
+#include <asm/ppc.h>
DECLARE_GLOBAL_DATA_PTR;
* Print out the state of various machine registers.
* Currently prints out LAWs, BR0/OR0, and BATs
*/
-void mpc86xx_reginfo(void)
+void print_reginfo(void)
{
print_bats();
print_laws();
#include <post.h>
#endif
-int interrupt_init_cpu(unsigned long *decrementer_count)
+int interrupt_init_cpu(unsigned *decrementer_count)
{
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
volatile ccsr_pic_t *pic = &immr->im_pic;
pic->gcr = MPC86xx_PICGCR_MODE;
*decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
- debug("interrupt init: tbclk() = %ld MHz, decrementer_count = %ld\n",
+ debug("interrupt init: tbclk() = %ld MHz, decrementer_count = %d\n",
(get_tbclk() / 1000000),
*decrementer_count);
dc_read:
blr
- .globl get_pvr
-get_pvr:
- mfspr r3, PVR
- blr
-
- .globl get_svr
-get_svr:
- mfspr r3, SVR
- blr
-
/*
* Function: in8
regs->nip, regs->msr, regs->trap);
_exception(0, regs);
}
-
-/*
- * Probe an address by reading.
- * If not present, return -1,
- * otherwise return 0.
- */
-int addr_probe(uint *addr)
-{
- return 0;
-}
obj-y += interrupts.o
obj-$(CONFIG_CMD_REGINFO) += reginfo.o
obj-y += speed.o
+obj-y += cache.o
--- /dev/null
+/*
+ * (C) Copyright 2017
+ * Christophe Leroy, CS Systemes d'Information, christophe.leroy@c-s.fr
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/ppc.h>
+#include <asm/io.h>
+#include <asm/mmu.h>
+
+int icache_status(void)
+{
+ return !!(mfspr(IC_CST) & IDC_ENABLED);
+}
+
+void icache_enable(void)
+{
+ sync();
+ mtspr(IC_CST, IDC_INVALL);
+ mtspr(IC_CST, IDC_ENABLE);
+}
+
+void icache_disable(void)
+{
+ sync();
+ mtspr(IC_CST, IDC_DISABLE);
+}
+
+int dcache_status(void)
+{
+ return !!(mfspr(IC_CST) & IDC_ENABLED);
+}
+
+void dcache_enable(void)
+{
+ mtspr(MD_CTR, MD_RESETVAL); /* Set cache mode with MMU off */
+ mtspr(DC_CST, IDC_INVALL);
+ mtspr(DC_CST, IDC_ENABLE);
+}
+
+void dcache_disable(void)
+{
+ sync();
+ mtspr(DC_CST, IDC_DISABLE);
+ mtspr(DC_CST, IDC_INVALL);
+}
DECLARE_GLOBAL_DATA_PTR;
-static char *cpu_warning = "\n " \
- "*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***";
-
static int check_CPU(long clock, uint pvr, uint immr)
{
- char *id_str =
- NULL;
immap_t __iomem *immap = (immap_t __iomem *)(immr & 0xFFFF0000);
- uint k, m;
+ uint k;
char buf[32];
- char pre = 'X';
- char *mid = "xx";
- char *suf;
/* the highest 16 bits should be 0x0050 for a 860 */
k = (immr << 16) |
in_be16(&immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)]);
- m = 0;
- suf = "";
/*
* Some boards use sockets so different CPUs can be used.
switch (k) {
/* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */
case 0x08010004: /* Rev. A.0 */
- suf = "A";
- /* fall through */
+ printf("MPC866xxxZPnnA");
+ break;
case 0x08000003: /* Rev. 0.3 */
- pre = 'M'; m = 1;
- if (id_str == NULL)
- id_str =
- "PC866x"; /* Unknown chip from MPC866 family */
+ printf("MPC866xxxZPnn");
break;
- case 0x09000000:
- pre = 'M'; mid = suf = ""; m = 1;
- if (id_str == NULL)
- id_str = "PC885"; /* 870/875/880/885 */
+ case 0x09000000: /* 870/875/880/885 */
+ puts("MPC885ZPnn");
break;
default:
- suf = NULL;
+ printf("unknown MPC86x (0x%08x)", k);
break;
}
- if (id_str == NULL)
- id_str = "PC86x"; /* Unknown 86x chip */
- if (suf)
- printf("%c%s%sZPnn%s", pre, id_str, mid, suf);
- else
- printf("unknown M%s (0x%08x)", id_str, k);
-
printf(" at %s MHz: ", strmhz(buf, clock));
print_size(checkicache(), " I-Cache ");
if (in_be32(&immap->im_cpm.cp_fec.fec_addr_low) == 0x12345678)
printf(" FEC present");
- if (!m)
- puts(cpu_warning);
-
putc('\n');
return 0;
/* unlock TBSCRK */
out_be32(&immr->im_sitk.sitk_tbscrk, KAPWR_KEY);
- out_be16(&immr->im_sit.sit_tbscr, CONFIG_SYS_TBSCR);
+ out_be16(&immr->im_sit.sit_tbscr, CONFIG_SYS_TBSCR | TBSCR_TBE);
+
+ /* Unlock timebase register */
+ out_be32(&immr->im_sitk.sitk_tbk, KAPWR_KEY);
/* initialize the PIT (11-31) */
DECLARE_GLOBAL_DATA_PTR;
-int do_siuinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_siuinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
sysconf8xx_t __iomem *sc = &immap->im_siu_conf;
return 0;
}
-int do_memcinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_memcinfo(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
memctl8xx_t __iomem *memctl = &immap->im_memctl;
return 0;
}
-int do_carinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_carinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
car8xx_t __iomem *car = &immap->im_clkrst;
#define PC_NBITS 12
#define PD_NBITS 13
-int do_iopinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_iopinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
iop8xx_t __iomem *iop = &immap->im_ioport;
* this needs a clean up for smaller tighter code
* use *uint and set the address based on cmd + port
*/
-int do_iopset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_iopset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
uint rcode = 0;
iopin_t iopin;
putc('\n');
}
-int do_brginfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_brginfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
cpm8xx_t __iomem *cp = &immap->im_cpm;
#include <common.h>
#include <mpc8xx.h>
#include <asm/io.h>
+#include <asm/ppc.h>
-void mpc8xx_reginfo(void)
+void print_reginfo(void)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
memctl8xx_t __iomem *memctl = &immap->im_memctl;
DECLARE_GLOBAL_DATA_PTR;
-void get_brgclk(uint sccr)
-{
- uint divider = 0;
-
- switch ((sccr & SCCR_DFBRG11) >> 11) {
- case 0:
- divider = 1;
- break;
- case 1:
- divider = 4;
- break;
- case 2:
- divider = 16;
- break;
- case 3:
- divider = 64;
- break;
- }
- gd->arch.brg_clk = gd->cpu_clk / divider;
-}
-
/*
* get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ
*/
uint immr = get_immr(0); /* Return full IMMR contents */
immap_t __iomem *immap = (immap_t __iomem *)(immr & 0xFFFF0000);
uint sccr = in_be32(&immap->im_clkrst.car_sccr);
+ uint divider = 1 << (((sccr & SCCR_DFBRG11) >> 11) * 2);
+
/*
* If for some reason measuring the gclk frequency won't
* work, we return the hardwired value.
gd->bus_clk = gd->cpu_clk / 2;
}
- get_brgclk(sccr);
+ gd->arch.brg_clk = gd->cpu_clk / divider;
return 0;
}
SYNC
rfi
-/* Cache functions.
-*/
- .globl icache_enable
-icache_enable:
- SYNC
- lis r3, IDC_INVALL@h
- mtspr IC_CST, r3
- lis r3, IDC_ENABLE@h
- mtspr IC_CST, r3
- blr
-
- .globl icache_disable
-icache_disable:
- SYNC
- lis r3, IDC_DISABLE@h
- mtspr IC_CST, r3
- blr
-
- .globl icache_status
-icache_status:
- mfspr r3, IC_CST
- srwi r3, r3, 31 /* >>31 => select bit 0 */
- blr
-
- .globl dcache_enable
-dcache_enable:
- lis r3, 0x0400 /* Set cache mode with MMU off */
- mtspr MD_CTR, r3
-
- lis r3, IDC_INVALL@h
- mtspr DC_CST, r3
- lis r3, IDC_ENABLE@h
- mtspr DC_CST, r3
- blr
-
- .globl dcache_disable
-dcache_disable:
- SYNC
- lis r3, IDC_DISABLE@h
- mtspr DC_CST, r3
- lis r3, IDC_INVALL@h
- mtspr DC_CST, r3
- blr
-
- .globl dcache_status
-dcache_status:
- mfspr r3, DC_CST
- srwi r3, r3, 31 /* >>31 => select bit 0 */
- blr
-
- .globl dc_read
-dc_read:
- mtspr DC_ADR, r3
- mfspr r3, DC_DAT
- blr
-
-/*
- * unsigned int get_immr (unsigned int mask)
- *
- * return (mask ? (IMMR & mask) : IMMR);
- */
- .globl get_immr
-get_immr:
- mr r4,r3 /* save mask */
- mfspr r3, IMMR /* IMMR */
- cmpwi 0,r4,0 /* mask != 0 ? */
- beq 4f
- and r3,r3,r4 /* IMMR & mask */
-4:
- blr
-
- .globl get_pvr
-get_pvr:
- mfspr r3, PVR
- blr
-
-
- .globl wr_ic_cst
-wr_ic_cst:
- mtspr IC_CST, r3
- blr
-
- .globl rd_ic_cst
-rd_ic_cst:
- mfspr r3, IC_CST
- blr
-
- .globl wr_ic_adr
-wr_ic_adr:
- mtspr IC_ADR, r3
- blr
-
-
- .globl wr_dc_cst
-wr_dc_cst:
- mtspr DC_CST, r3
- blr
-
- .globl rd_dc_cst
-rd_dc_cst:
- mfspr r3, DC_CST
- blr
-
- .globl wr_dc_adr
-wr_dc_adr:
- mtspr DC_ADR, r3
- blr
-
/*------------------------------------------------------------------------------*/
/*
printf("\n");
}
-void show_regs(struct pt_regs *regs)
+static void show_regs(struct pt_regs *regs)
{
int i;
printf("Debugger trap at @ %lx\n", regs->nip);
show_regs(regs);
}
-
-/* Probe an address by reading. If not present, return -1, otherwise
- * return 0.
- */
-int addr_probe(uint *addr)
-{
- return 0;
-}
#define DC_DFWT 0x40000000 /* Data cache is forced write through */
#define DC_LES 0x20000000 /* Caches are little endian mode */
+
+#if !defined(__ASSEMBLY__)
+static inline uint rd_ic_cst(void)
+{
+ return mfspr(IC_CST);
+}
+
+static inline void wr_ic_cst(uint val)
+{
+ mtspr(IC_CST, val);
+}
+
+static inline void wr_ic_adr(uint val)
+{
+ mtspr(IC_ADR, val);
+}
+
+static inline uint rd_dc_cst(void)
+{
+ return mfspr(DC_CST);
+}
+
+static inline void wr_dc_cst(uint val)
+{
+ mtspr(DC_CST, val);
+}
+
+static inline void wr_dc_adr(uint val)
+{
+ mtspr(DC_ADR, val);
+}
+#endif
#endif /* CONFIG_8xx */
#endif
#include <asm/arch/immap_lsch2.h>
#endif
+#include <asm/processor.h>
+
#if defined(CONFIG_8xx)
-uint get_immr(uint);
+static inline uint get_immr(uint mask)
+{
+ uint immr = mfspr(SPRN_IMMR);
+
+ return mask ? (immr & mask) : immr;
+}
#endif
-uint get_pvr(void);
-uint get_svr(void);
-uint rd_ic_cst(void);
-void wr_ic_cst(uint);
-void wr_ic_adr(uint);
-uint rd_dc_cst(void);
-void wr_dc_cst(uint);
-void wr_dc_adr(uint);
+static inline uint get_pvr(void)
+{
+ return mfspr(PVR);
+}
+
+static inline uint get_svr(void)
+{
+ return mfspr(SVR);
+}
#if defined(CONFIG_MPC85xx) || \
defined(CONFIG_MPC86xx) || \
ulong get_ddr_freq(ulong);
#endif
+static inline unsigned long get_msr(void)
+{
+ unsigned long msr;
+
+ asm volatile ("mfmsr %0" : "=r" (msr) : );
+
+ return msr;
+}
+
+static inline void set_msr(unsigned long msr)
+{
+ asm volatile ("mtmsr %0" : : "r" (msr));
+}
+
+#ifdef CONFIG_CMD_REGINFO
+void print_reginfo(void);
+#endif
+
+int interrupt_init_cpu(unsigned *);
+void timer_interrupt_cpu(struct pt_regs *);
+unsigned long search_exception_table(unsigned long addr);
+
#endif /* !__ASSEMBLY__ */
#ifdef CONFIG_PPC
#define PVR_850 PVR_821
#define PVR_860 PVR_821
#define PVR_7400 0x000C0000
-#define PVR_8240 0x00810100
-
-/*
- * PowerQUICC II family processors report different PVR values depending
- * on silicon process (HiP3, HiP4, HiP7, etc.)
- */
-#define PVR_8260 PVR_8240
-#define PVR_8260_HIP3 0x00810101
-#define PVR_8260_HIP4 0x80811014
-#define PVR_8260_HIP7 0x80822011
-#define PVR_8260_HIP7R1 0x80822013
-#define PVR_8260_HIP7RA 0x80822014
/*
* MPC 52xx
void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
int prt_83xx_rsr(void);
-int prt_8260_rsr(void);
-int prt_8260_clks(void);
#endif /* ndef ASSEMBLY*/
#include <environment.h>
#include <asm/byteorder.h>
#include <asm/mp.h>
+#include <bootm.h>
+#include <vxworks.h>
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#define CONFIG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2)
#endif
-extern int interrupt_init_cpu (unsigned *);
-extern void timer_interrupt_cpu (struct pt_regs *);
-
static unsigned decrementer_count; /* count value for 1e6/HZ microseconds */
-static __inline__ unsigned long get_msr (void)
-{
- unsigned long msr;
-
- asm volatile ("mfmsr %0":"=r" (msr):);
-
- return msr;
-}
-
-static __inline__ void set_msr (unsigned long msr)
-{
- asm volatile ("mtmsr %0"::"r" (msr));
-}
-
static __inline__ unsigned long get_dec (void)
{
unsigned long val;
: "=&r"(temp) : "r" (buf), "r" (val));
}
-static inline unsigned long
-get_msr(void)
-{
- unsigned long msr;
- asm volatile("mfmsr %0" : "=r" (msr):);
- return msr;
-}
-
-static inline void
-set_msr(unsigned long msr)
-{
- asm volatile("mtmsr %0" : : "r" (msr));
-}
-
/* Convert the SPARC hardware trap type code to a unix signal number. */
/*
* This table contains the mapping between PowerPC hardware trap types, and
{
unsigned long temp;
-#if defined(CONFIG_8xx)
- immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
-
- /* unlock */
- out_be32(&immap->im_sitk.sitk_tbk, KAPWR_KEY);
-#endif
-
/* reset */
- asm volatile("li %0,0 ; mttbu %0 ; mttbl %0;"
+ asm volatile("li %0,0 ; mttbl %0 ; mttbu %0;"
: "=&r"(temp) );
-#if defined(CONFIG_8xx)
- /* enable */
- setbits_be16(&immap->im_sit.sit_tbscr, TBSCR_TBE);
-#endif
return (0);
}
/* ------------------------------------------------------------------------- */
return 0;
}
-void os_putc(int ch)
-{
- putchar(ch);
-}
-
-void os_puts(const char *str)
-{
- while (*str)
- os_putc(*str++);
-}
-
int os_write_ram_buf(const char *fname)
{
struct sandbox_state *state = state_get_current();
memset(&data, '\0', sizeof(data));
gd = &data;
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
gd->malloc_base = CONFIG_MALLOC_F_ADDR;
#endif
setup_ram_buf(state);
config CPU_SH2
bool
+ imply ENV_IS_IN_FLASH
config CPU_SH2A
bool
select CPU_SH2
+ imply ENV_IS_IN_FLASH
config CPU_SH3
bool
+ imply ENV_IS_IN_FLASH
config CPU_SH4
bool
source "arch/x86/cpu/qemu/Kconfig"
source "arch/x86/cpu/quark/Kconfig"
source "arch/x86/cpu/queensbay/Kconfig"
+source "arch/x86/cpu/tangier/Kconfig"
# architecture-specific options below
obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/
obj-$(CONFIG_INTEL_QUARK) += quark/
obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/
+obj-$(CONFIG_INTEL_TANGIER) += tangier/
obj-y += lapic.o ioapic.o
obj-y += irq.o
ifndef CONFIG_$(SPL_)X86_64
config INTEL_BAYTRAIL
bool
select HAVE_FSP if !EFI
+ imply ENV_IS_IN_SPI_FLASH
if INTEL_BAYTRAIL
config INTERNAL_UART
#include <asm/acpi_s3.h>
#include <asm/acpi_table.h>
#include <asm/io.h>
-#include <asm/ioapic.h>
-#include <asm/mpspec.h>
#include <asm/tables.h>
#include <asm/arch/global_nvs.h>
#include <asm/arch/iomap.h>
header->checksum = table_compute_checksum(fadt, header->length);
}
-static int acpi_create_madt_irq_overrides(u32 current)
-{
- struct acpi_madt_irqoverride *irqovr;
- u16 sci_flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH;
- int length = 0;
-
- irqovr = (void *)current;
- length += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
-
- irqovr = (void *)(current + length);
- length += acpi_create_madt_irqoverride(irqovr, 0, 9, 9, sci_flags);
-
- return length;
-}
-
-u32 acpi_fill_madt(u32 current)
-{
- current += acpi_create_madt_lapics(current);
-
- current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,
- io_apic_read(IO_APIC_ID) >> 24, IO_APIC_ADDR, 0);
-
- current += acpi_create_madt_irq_overrides(current);
-
- return current;
-}
-
void acpi_create_gnvs(struct acpi_global_nvs *gnvs)
{
struct udevice *dev;
#include <common.h>
#include <asm/acpi_table.h>
-#include <asm/ioapic.h>
-#include <asm/mpspec.h>
#include <asm/tables.h>
#include <asm/arch/global_nvs.h>
#include <asm/arch/iomap.h>
header->checksum = table_compute_checksum(fadt, header->length);
}
-static int acpi_create_madt_irq_overrides(u32 current)
-{
- struct acpi_madt_irqoverride *irqovr;
- u16 sci_flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH;
- int length = 0;
-
- irqovr = (void *)current;
- length += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
-
- irqovr = (void *)(current + length);
- length += acpi_create_madt_irqoverride(irqovr, 0, 9, 9, sci_flags);
-
- return length;
-}
-
-u32 acpi_fill_madt(u32 current)
-{
- current += acpi_create_madt_lapics(current);
-
- current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,
- io_apic_read(IO_APIC_ID) >> 24, IO_APIC_ADDR, 0);
-
- current += acpi_create_madt_irq_overrides(current);
-
- return current;
-}
-
void acpi_create_gnvs(struct acpi_global_nvs *gnvs)
{
/* quark is a uni-processor */
--- /dev/null
+#
+# Copyright (c) 2017 Intel Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+config INTEL_TANGIER
+ bool
+ depends on INTEL_MID
+
+config SYS_CAR_ADDR
+ hex
+ default 0x19200000
+
+config SYS_CAR_SIZE
+ hex
+ default 0x4000
+ help
+ Space in bytes in eSRAM used as Cache-As-RAM (CAR).
+ Note this size must not exceed eSRAM's total size.
+
+config SYS_USB_OTG_BASE
+ hex
+ default 0xf9100000
--- /dev/null
+#
+# Copyright (c) 2017 Intel Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += car.o tangier.o sdram.o
--- /dev/null
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2010-2011
+ * Graeme Russ, <graeme.russ@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+.section .text
+
+.globl car_init
+car_init:
+ jmp car_init_ret
--- /dev/null
+/*
+ * Copyright (c) 2017 Intel Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/e820.h>
+#include <asm/global_data.h>
+#include <asm/sfi.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * SFI tables are part of the first stage bootloader.
+ *
+ * U-Boot finds the System Table by searching 16-byte boundaries between
+ * physical address 0x000E0000 and 0x000FFFFF. U-Boot shall search this region
+ * starting at the low address and shall stop searching when the 1st valid SFI
+ * System Table is found.
+ */
+#define SFI_BASE_ADDR 0x000E0000
+#define SFI_LENGTH 0x00020000
+#define SFI_TABLE_LENGTH 16
+
+static int sfi_table_check(struct sfi_table_header *sbh)
+{
+ char chksum = 0;
+ char *pos = (char *)sbh;
+ u32 i;
+
+ if (sbh->len < SFI_TABLE_LENGTH)
+ return -ENXIO;
+
+ if (sbh->len > SFI_LENGTH)
+ return -ENXIO;
+
+ for (i = 0; i < sbh->len; i++)
+ chksum += *pos++;
+
+ if (chksum)
+ error("sfi: Invalid checksum\n");
+
+ /* Checksum is OK if zero */
+ return chksum ? -EILSEQ : 0;
+}
+
+static int sfi_table_is_type(struct sfi_table_header *sbh, const char *signature)
+{
+ return !strncmp(sbh->sig, signature, SFI_SIGNATURE_SIZE) &&
+ !sfi_table_check(sbh);
+}
+
+static struct sfi_table_simple *sfi_get_table_by_sig(unsigned long addr,
+ const char *signature)
+{
+ struct sfi_table_simple *sb;
+ u32 i;
+
+ for (i = 0; i < SFI_LENGTH; i += SFI_TABLE_LENGTH) {
+ sb = (struct sfi_table_simple *)(addr + i);
+ if (sfi_table_is_type(&sb->header, signature))
+ return sb;
+ }
+
+ return NULL;
+}
+
+static struct sfi_table_simple *sfi_search_mmap(void)
+{
+ struct sfi_table_header *sbh;
+ struct sfi_table_simple *sb;
+ u32 sys_entry_cnt;
+ u32 i;
+
+ /* Find SYST table */
+ sb = sfi_get_table_by_sig(SFI_BASE_ADDR, SFI_SIG_SYST);
+ if (!sb) {
+ error("sfi: failed to locate SYST table\n");
+ return NULL;
+ }
+
+ sys_entry_cnt = (sb->header.len - sizeof(*sbh)) / 8;
+
+ /* Search through each SYST entry for MMAP table */
+ for (i = 0; i < sys_entry_cnt; i++) {
+ sbh = (struct sfi_table_header *)(unsigned long)sb->pentry[i];
+
+ if (sfi_table_is_type(sbh, SFI_SIG_MMAP))
+ return (struct sfi_table_simple *)sbh;
+ }
+
+ error("sfi: failed to locate SFI MMAP table\n");
+ return NULL;
+}
+
+#define sfi_for_each_mentry(i, sb, mentry) \
+ for (i = 0, mentry = (struct sfi_mem_entry *)sb->pentry; \
+ i < SFI_GET_NUM_ENTRIES(sb, struct sfi_mem_entry); \
+ i++, mentry++) \
+
+static unsigned sfi_setup_e820(unsigned max_entries, struct e820entry *entries)
+{
+ struct sfi_table_simple *sb;
+ struct sfi_mem_entry *mentry;
+ unsigned long long start, end, size;
+ int type, total = 0;
+ u32 i;
+
+ sb = sfi_search_mmap();
+ if (!sb)
+ return 0;
+
+ sfi_for_each_mentry(i, sb, mentry) {
+ start = mentry->phys_start;
+ size = mentry->pages << 12;
+ end = start + size;
+
+ if (start > end)
+ continue;
+
+ /* translate SFI mmap type to E820 map type */
+ switch (mentry->type) {
+ case SFI_MEM_CONV:
+ type = E820_RAM;
+ break;
+ case SFI_MEM_UNUSABLE:
+ case SFI_RUNTIME_SERVICE_DATA:
+ continue;
+ default:
+ type = E820_RESERVED;
+ }
+
+ if (total == E820MAX)
+ break;
+ entries[total].addr = start;
+ entries[total].size = size;
+ entries[total].type = type;
+
+ total++;
+ }
+
+ return total;
+}
+
+static int sfi_get_bank_size(void)
+{
+ struct sfi_table_simple *sb;
+ struct sfi_mem_entry *mentry;
+ int bank = 0;
+ u32 i;
+
+ sb = sfi_search_mmap();
+ if (!sb)
+ return 0;
+
+ sfi_for_each_mentry(i, sb, mentry) {
+ if (mentry->type != SFI_MEM_CONV)
+ continue;
+
+ gd->bd->bi_dram[bank].start = mentry->phys_start;
+ gd->bd->bi_dram[bank].size = mentry->pages << 12;
+ bank++;
+ }
+
+ return bank;
+}
+
+static phys_size_t sfi_get_ram_size(void)
+{
+ struct sfi_table_simple *sb;
+ struct sfi_mem_entry *mentry;
+ phys_size_t ram = 0;
+ u32 i;
+
+ sb = sfi_search_mmap();
+ if (!sb)
+ return 0;
+
+ sfi_for_each_mentry(i, sb, mentry) {
+ if (mentry->type != SFI_MEM_CONV)
+ continue;
+
+ ram += mentry->pages << 12;
+ }
+
+ debug("sfi: RAM size %llu\n", ram);
+ return ram;
+}
+
+unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
+{
+ return sfi_setup_e820(max_entries, entries);
+}
+
+int dram_init_banksize(void)
+{
+ sfi_get_bank_size();
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = sfi_get_ram_size();
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (c) 2017 Intel Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/scu.h>
+#include <asm/u-boot-x86.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+int arch_cpu_init(void)
+{
+ return x86_cpu_init_f();
+}
+
+int checkcpu(void)
+{
+ return 0;
+}
+
+int print_cpuinfo(void)
+{
+ return default_print_cpuinfo();
+}
+
+void reset_cpu(ulong addr)
+{
+ scu_ipc_simple_command(IPCMSG_COLD_RESET, 0);
+}
cougarcanyon2.dtb \
crownbay.dtb \
dfi-bt700-q7x-151.dtb \
+ edison.dtb \
efi.dtb \
galileo.dtb \
minnowmax.dtb \
fsp,enable-spi;
fsp,enable-sata;
fsp,sata-mode = <SATA_MODE_AHCI>;
+#ifdef CONFIG_USB_XHCI_HCD
+ fsp,enable-xhci;
+#endif
fsp,lpe-mode = <LPE_MODE_PCI>;
fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
fsp,enable-dma0;
pad-offset = <0x3a0>;
mode-func = <1>;
};
+
+ xhci_hub_reset: usb_ulpi_stp@0 {
+ gpio-offset = <0xa0 10>;
+ pad-offset = <0x23b0>;
+ mode-func = <0>;
+ mode-gpio;
+ output-value = <1>;
+ direction = <PIN_OUTPUT>;
+ };
};
chosen {
fsp,enable-spi;
fsp,enable-sata;
fsp,sata-mode = <SATA_MODE_AHCI>;
+#ifdef CONFIG_USB_XHCI_HCD
+ fsp,enable-xhci;
+#endif
fsp,lpe-mode = <LPE_MODE_PCI>;
fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
fsp,enable-dma0;
--- /dev/null
+/*
+ * Copyright (c) 2017 Intel Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/x86-gpio.h>
+#include <dt-bindings/interrupt-router/intel-irq.h>
+
+/include/ "skeleton.dtsi"
+/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"
+
+/ {
+ model = "Intel Edison";
+ compatible = "intel,edison";
+
+ aliases {
+ serial0 = &serial0;
+ };
+
+ chosen {
+ stdout-path = &serial0;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "cpu-x86";
+ reg = <0>;
+ intel,apic-id = <0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "cpu-x86";
+ reg = <1>;
+ intel,apic-id = <2>;
+ };
+ };
+
+ pci {
+ compatible = "pci-x86";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
+ 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
+ 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
+ };
+
+ serial0: serial@ff010180 {
+ compatible = "intel,mid-uart";
+ reg = <0xff010180 0x100>;
+ reg-shift = <0>;
+ clock-frequency = <29491200>;
+ current-speed = <115200>;
+ };
+
+ emmc: mmc@ff3fc000 {
+ compatible = "intel,sdhci-tangier";
+ reg = <0xff3fc000 0x1000>;
+ };
+
+/*
+ * FIXME: For now U-Boot DM model doesn't allow to power up this controller.
+ * Enabling it will make U-Boot hang.
+ *
+ sdcard: mmc@ff3fa000 {
+ compatible = "intel,sdhci-tangier";
+ reg = <0xff3fa000 0x1000>;
+ };
+ */
+
+ pmu: power@ff00b000 {
+ compatible = "intel,pmu-mid";
+ reg = <0xff00b000 0x1000>;
+ };
+
+ scu: ipc@ff009000 {
+ compatible = "intel,scu-ipc";
+ reg = <0xff009000 0x1000>;
+ };
+};
fsp,enable-spi;
fsp,enable-sata;
fsp,sata-mode = <SATA_MODE_AHCI>;
+#ifdef CONFIG_USB_XHCI_HCD
+ fsp,enable-xhci;
+#endif
fsp,lpe-mode = <LPE_MODE_PCI>;
fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
fsp,enable-dma0;
u32 flags;
struct acpi_gen_regaddr reset_reg;
u8 reset_value;
- u8 res3;
- u8 res4;
- u8 res5;
+ u16 arm_boot_arch;
+ u8 minor_revision;
u32 x_firmware_ctl_l;
u32 x_firmware_ctl_h;
u32 x_dsdt_l;
int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi,
u8 cpu, u16 flags, u8 lint);
u32 acpi_fill_madt(u32 current);
+int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig, u32 base,
+ u16 seg_nr, u8 start, u8 end);
+u32 acpi_fill_mcfg(u32 current);
void acpi_create_gnvs(struct acpi_global_nvs *gnvs);
/**
* enter_acpi_mode() - enter into ACPI mode
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __ASM_X86_DMA_MAPPING_H
+#define __ASM_X86_DMA_MAPPING_H
+
+#define dma_mapping_error(x, y) 0
+
+enum dma_data_direction {
+ DMA_BIDIRECTIONAL = 0,
+ DMA_TO_DEVICE = 1,
+ DMA_FROM_DEVICE = 2,
+};
+
+static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
+{
+ *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len);
+ return (void *)*handle;
+}
+
+static inline void dma_free_coherent(void *addr)
+{
+ free(addr);
+}
+
+static inline unsigned long dma_map_single(volatile void *vaddr, size_t len,
+ enum dma_data_direction dir)
+{
+ return (unsigned long)vaddr;
+}
+
+static inline void dma_unmap_single(volatile void *vaddr, size_t len,
+ unsigned long paddr)
+{
+}
+
+#endif /* __ASM_X86_DMA_MAPPING_H */
u64 attrib;
};
+/* Memory type definitions */
+enum sfi_mem_type {
+ SFI_MEM_RESERVED,
+ SFI_LOADER_CODE,
+ SFI_LOADER_DATA,
+ SFI_BOOT_SERVICE_CODE,
+ SFI_BOOT_SERVICE_DATA,
+ SFI_RUNTIME_SERVICE_CODE,
+ SFI_RUNTIME_SERVICE_DATA,
+ SFI_MEM_CONV,
+ SFI_MEM_UNUSABLE,
+ SFI_ACPI_RECLAIM,
+ SFI_ACPI_NVS,
+ SFI_MEM_MMIO,
+ SFI_MEM_IOPORT,
+ SFI_PAL_CODE,
+ SFI_MEM_TYPEMAX,
+};
+
struct __packed sfi_cpu_table_entry {
u32 apic_id;
};
#include <cpu.h>
#include <dm.h>
#include <dm/uclass-internal.h>
+#include <version.h>
#include <asm/acpi/global_nvs.h>
#include <asm/acpi_table.h>
#include <asm/io.h>
+#include <asm/ioapic.h>
#include <asm/lapic.h>
+#include <asm/mpspec.h>
#include <asm/tables.h>
#include <asm/arch/global_nvs.h>
memcpy(header->signature, signature, 4);
memcpy(header->oem_id, OEM_ID, 6);
memcpy(header->oem_table_id, OEM_TABLE_ID, 8);
+ header->oem_revision = U_BOOT_BUILD_DATE;
memcpy(header->aslc_id, ASLC_ID, 4);
}
return lapic_nmi->length;
}
+static int acpi_create_madt_irq_overrides(u32 current)
+{
+ struct acpi_madt_irqoverride *irqovr;
+ u16 sci_flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH;
+ int length = 0;
+
+ irqovr = (void *)current;
+ length += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
+
+ irqovr = (void *)(current + length);
+ length += acpi_create_madt_irqoverride(irqovr, 0, 9, 9, sci_flags);
+
+ return length;
+}
+
+__weak u32 acpi_fill_madt(u32 current)
+{
+ current += acpi_create_madt_lapics(current);
+
+ current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,
+ io_apic_read(IO_APIC_ID) >> 24, IO_APIC_ADDR, 0);
+
+ current += acpi_create_madt_irq_overrides(current);
+
+ return current;
+}
+
static void acpi_create_madt(struct acpi_madt *madt)
{
struct acpi_table_header *header = &(madt->header);
header->checksum = table_compute_checksum((void *)madt, header->length);
}
-static int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig,
- u32 base, u16 seg_nr, u8 start, u8 end)
+int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig, u32 base,
+ u16 seg_nr, u8 start, u8 end)
{
memset(mmconfig, 0, sizeof(*mmconfig));
mmconfig->base_address_l = base;
return sizeof(struct acpi_mcfg_mmconfig);
}
-static u32 acpi_fill_mcfg(u32 current)
+__weak u32 acpi_fill_mcfg(u32 current)
{
current += acpi_create_mcfg_mmconfig
((struct acpi_mcfg_mmconfig *)current,
debug("ACPI: done\n");
+ /* Don't touch ACPI hardware on HW reduced platforms */
+ if (fadt->flags & ACPI_FADT_HW_REDUCED_ACPI)
+ return current;
+
/*
* Other than waiting for OSPM to request us to switch to ACPI mode,
* do it by ourselves, since SMI will not be triggered.
}
#ifdef CONFIG_NAND
dtbsize = 0x20000;
- rc = nand_read_skip_bad(nand_info[0], 0x40000, (size_t *)&dtbsize,
+ rc = nand_read_skip_bad(get_nand_dev_by_index(0), 0x40000,
+ (size_t *)&dtbsize,
NULL, 0x20000, (u_char *)dtbaddr);
#else
char *dtbname = getenv("dtb");
--- /dev/null
+#
+# Copyright (C) 2017 Marek Behun <marek.behun@nic.cz>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := turris_omnia.o
--- /dev/null
+#
+# Copyright (C) 2014 Stefan Roese <sr@denx.de>
+#
+
+# Armada XP uses version 1 image format
+VERSION 1
+
+# Boot Media configurations
+BOOT_FROM spi
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY spl/u-boot-spl.bin 0000005b 00000068
--- /dev/null
+/*
+ * Copyright (C) 2017 Marek Behun <marek.behun@nic.cz>
+ * Copyright (C) 2016 Tomas Hlavacek <tomas.hlavacek@nic.cz>
+ *
+ * Derived from the code for
+ * Marvell/db-88f6820-gp by Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <dm/uclass.h>
+#include <fdt_support.h>
+#include <time.h>
+
+#ifdef CONFIG_ATSHA204A
+# include <atsha204a-i2c.h>
+#endif
+
+#ifdef CONFIG_WDT_ORION
+# include <wdt.h>
+#endif
+
+#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
+#include <../serdes/a38x/high_speed_env_spec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define OMNIA_I2C_EEPROM_DM_NAME "i2c@0"
+#define OMNIA_I2C_EEPROM 0x54
+#define OMNIA_I2C_EEPROM_CONFIG_ADDR 0x0
+#define OMNIA_I2C_EEPROM_ADDRLEN 2
+#define OMNIA_I2C_EEPROM_MAGIC 0x0341a034
+
+#define OMNIA_I2C_MCU_DM_NAME "i2c@0"
+#define OMNIA_I2C_MCU_ADDR_STATUS 0x1
+#define OMNIA_I2C_MCU_SATA 0x20
+#define OMNIA_I2C_MCU_CARDDET 0x10
+#define OMNIA_I2C_MCU 0x2a
+#define OMNIA_I2C_MCU_WDT_ADDR 0x0b
+
+#define OMNIA_ATSHA204_OTP_VERSION 0
+#define OMNIA_ATSHA204_OTP_SERIAL 1
+#define OMNIA_ATSHA204_OTP_MAC0 3
+#define OMNIA_ATSHA204_OTP_MAC1 4
+
+#define MVTWSI_ARMADA_DEBUG_REG 0x8c
+
+/*
+ * Those values and defines are taken from the Marvell U-Boot version
+ * "u-boot-2013.01-2014_T3.0"
+ */
+#define OMNIA_GPP_OUT_ENA_LOW \
+ (~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \
+ BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) | \
+ BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
+#define OMNIA_GPP_OUT_ENA_MID \
+ (~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \
+ BIT(16) | BIT(17) | BIT(18)))
+
+#define OMNIA_GPP_OUT_VAL_LOW 0x0
+#define OMNIA_GPP_OUT_VAL_MID 0x0
+#define OMNIA_GPP_POL_LOW 0x0
+#define OMNIA_GPP_POL_MID 0x0
+
+static struct serdes_map board_serdes_map_pex[] = {
+ {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+ {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+ {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+ {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+ {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+ {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
+};
+
+static struct serdes_map board_serdes_map_sata[] = {
+ {SATA0, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+ {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+ {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+ {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+ {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+ {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
+};
+
+static bool omnia_detect_sata(void)
+{
+ struct udevice *bus, *dev;
+ int ret;
+ u16 mode;
+
+ puts("SERDES0 card detect: ");
+
+ if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_MCU_DM_NAME, &bus)) {
+ puts("Cannot find MCU bus!\n");
+ return false;
+ }
+
+ ret = i2c_get_chip(bus, OMNIA_I2C_MCU, 1, &dev);
+ if (ret) {
+ puts("Cannot get MCU chip!\n");
+ return false;
+ }
+
+ ret = dm_i2c_read(dev, OMNIA_I2C_MCU_ADDR_STATUS, (uchar *) &mode, 2);
+ if (ret) {
+ puts("I2C read failed! Default PEX\n");
+ return false;
+ }
+
+ if (!(mode & OMNIA_I2C_MCU_CARDDET)) {
+ puts("NONE\n");
+ return false;
+ }
+
+ if (mode & OMNIA_I2C_MCU_SATA) {
+ puts("SATA\n");
+ return true;
+ } else {
+ puts("PEX\n");
+ return false;
+ }
+}
+
+int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
+{
+ if (omnia_detect_sata()) {
+ *serdes_map_array = board_serdes_map_sata;
+ *count = ARRAY_SIZE(board_serdes_map_sata);
+ } else {
+ *serdes_map_array = board_serdes_map_pex;
+ *count = ARRAY_SIZE(board_serdes_map_pex);
+ }
+
+ return 0;
+}
+
+struct omnia_eeprom {
+ u32 magic;
+ u32 ramsize;
+ char region[4];
+ u32 crc;
+};
+
+static bool omnia_read_eeprom(struct omnia_eeprom *oep)
+{
+ struct udevice *bus, *dev;
+ int ret, crc, retry = 3;
+
+ if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_EEPROM_DM_NAME, &bus)) {
+ puts("Cannot find EEPROM bus\n");
+ return false;
+ }
+
+ ret = i2c_get_chip(bus, OMNIA_I2C_EEPROM, OMNIA_I2C_EEPROM_ADDRLEN, &dev);
+ if (ret) {
+ puts("Cannot get EEPROM chip\n");
+ return false;
+ }
+
+ for (; retry > 0; --retry) {
+ ret = dm_i2c_read(dev, OMNIA_I2C_EEPROM_CONFIG_ADDR, (uchar *) oep, sizeof(struct omnia_eeprom));
+ if (ret)
+ continue;
+
+ if (oep->magic != OMNIA_I2C_EEPROM_MAGIC) {
+ puts("I2C EEPROM missing magic number!\n");
+ continue;
+ }
+
+ crc = crc32(0, (unsigned char *) oep,
+ sizeof(struct omnia_eeprom) - 4);
+ if (crc == oep->crc) {
+ break;
+ } else {
+ printf("CRC of EEPROM memory config failed! "
+ "calc=0x%04x saved=0x%04x\n", crc, oep->crc);
+ }
+ }
+
+ if (!retry) {
+ puts("I2C EEPROM read failed!\n");
+ return false;
+ }
+
+ return true;
+}
+
+/*
+ * Define the DDR layout / topology here in the board file. This will
+ * be used by the DDR3 init code in the SPL U-Boot version to configure
+ * the DDR3 controller.
+ */
+static struct hws_topology_map board_topology_map_1g = {
+ 0x1, /* active interfaces */
+ /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
+ { { { {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0} },
+ SPEED_BIN_DDR_1600K, /* speed_bin */
+ BUS_WIDTH_16, /* memory_width */
+ MEM_4G, /* mem_size */
+ DDR_FREQ_800, /* frequency */
+ 0, 0, /* cas_l cas_wl */
+ HWS_TEMP_NORMAL, /* temperature */
+ HWS_TIM_2T} }, /* timing (force 2t) */
+ 5, /* Num Of Bus Per Interface*/
+ BUS_MASK_32BIT /* Busses mask */
+};
+
+static struct hws_topology_map board_topology_map_2g = {
+ 0x1, /* active interfaces */
+ /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
+ { { { {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0} },
+ SPEED_BIN_DDR_1600K, /* speed_bin */
+ BUS_WIDTH_16, /* memory_width */
+ MEM_8G, /* mem_size */
+ DDR_FREQ_800, /* frequency */
+ 0, 0, /* cas_l cas_wl */
+ HWS_TEMP_NORMAL, /* temperature */
+ HWS_TIM_2T} }, /* timing (force 2t) */
+ 5, /* Num Of Bus Per Interface*/
+ BUS_MASK_32BIT /* Busses mask */
+};
+
+struct hws_topology_map *ddr3_get_topology_map(void)
+{
+ static int mem = 0;
+ struct omnia_eeprom oep;
+
+ /* Get the board config from EEPROM */
+ if (mem == 0) {
+ if(!omnia_read_eeprom(&oep))
+ goto out;
+
+ printf("Memory config in EEPROM: 0x%02x\n", oep.ramsize);
+
+ if (oep.ramsize == 0x2)
+ mem = 2;
+ else
+ mem = 1;
+ }
+
+out:
+ /* Hardcoded fallback */
+ if (mem == 0) {
+ puts("WARNING: Memory config from EEPROM read failed.\n");
+ puts("Falling back to default 1GiB map.\n");
+ mem = 1;
+ }
+
+ /* Return the board topology as defined in the board code */
+ if (mem == 1)
+ return &board_topology_map_1g;
+ if (mem == 2)
+ return &board_topology_map_2g;
+
+ return &board_topology_map_1g;
+}
+
+#ifndef CONFIG_SPL_BUILD
+static int set_regdomain(void)
+{
+ struct omnia_eeprom oep;
+ char rd[3] = {' ', ' ', 0};
+
+ if (omnia_read_eeprom(&oep))
+ memcpy(rd, &oep.region, 2);
+ else
+ puts("EEPROM regdomain read failed.\n");
+
+ printf("Regdomain set to %s\n", rd);
+ return setenv("regdomain", rd);
+}
+#endif
+
+int board_early_init_f(void)
+{
+ u32 i2c_debug_reg;
+
+ /* Configure MPP */
+ writel(0x11111111, MVEBU_MPP_BASE + 0x00);
+ writel(0x11111111, MVEBU_MPP_BASE + 0x04);
+ writel(0x11244011, MVEBU_MPP_BASE + 0x08);
+ writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
+ writel(0x22200002, MVEBU_MPP_BASE + 0x10);
+ writel(0x30042022, MVEBU_MPP_BASE + 0x14);
+ writel(0x55550555, MVEBU_MPP_BASE + 0x18);
+ writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
+
+ /* Set GPP Out value */
+ writel(OMNIA_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+ writel(OMNIA_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
+
+ /* Set GPP Polarity */
+ writel(OMNIA_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
+ writel(OMNIA_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
+
+ /* Set GPP Out Enable */
+ writel(OMNIA_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+ writel(OMNIA_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
+
+ /* Disable I2C debug mode blocking 0x64 I2C address */
+ i2c_debug_reg = readl(MVEBU_TWSI_BASE + MVTWSI_ARMADA_DEBUG_REG);
+ i2c_debug_reg &= ~(1<<18);
+ writel(i2c_debug_reg, MVEBU_TWSI_BASE + MVTWSI_ARMADA_DEBUG_REG);
+
+ return 0;
+}
+
+#ifndef CONFIG_SPL_BUILD
+static bool disable_mcu_watchdog(void)
+{
+ struct udevice *bus, *dev;
+ int ret, retry = 3;
+ uchar buf[1] = {0x0};
+
+ if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_MCU_DM_NAME, &bus)) {
+ puts("Cannot find MCU bus! Can not disable MCU WDT.\n");
+ return false;
+ }
+
+ ret = i2c_get_chip(bus, OMNIA_I2C_MCU, 1, &dev);
+ if (ret) {
+ puts("Cannot get MCU chip! Can not disable MCU WDT.\n");
+ return false;
+ }
+
+ for (; retry > 0; --retry)
+ if (!dm_i2c_write(dev, OMNIA_I2C_MCU_WDT_ADDR, (uchar *) buf, 1))
+ break;
+
+ if (retry <= 0) {
+ puts("I2C MCU watchdog failed to disable!\n");
+ return false;
+ }
+
+ return true;
+}
+#endif
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT_ORION)
+static struct udevice *watchdog_dev = NULL;
+#endif
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+#ifndef CONFIG_SPL_BUILD
+# ifdef CONFIG_WDT_ORION
+ if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
+ puts("Cannot find Armada 385 watchdog!\n");
+ } else {
+ puts("Enabling Armada 385 watchdog.\n");
+ wdt_start(watchdog_dev, (u32) 25000000 * 120, 0);
+ }
+# endif
+
+ if (disable_mcu_watchdog())
+ puts("Disabled MCU startup watchdog.\n");
+
+ set_regdomain();
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_WATCHDOG
+/* Called by macro WATCHDOG_RESET */
+void watchdog_reset(void)
+{
+# if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT_ORION)
+ static ulong next_reset = 0;
+ ulong now;
+
+ if (!watchdog_dev)
+ return;
+
+ now = timer_get_us();
+
+ /* Do not reset the watchdog too often */
+ if (now > next_reset) {
+ wdt_reset(watchdog_dev);
+ next_reset = now + 1000;
+ }
+# endif
+}
+#endif
+
+int board_late_init(void)
+{
+#ifndef CONFIG_SPL_BUILD
+ set_regdomain();
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_ATSHA204A
+static struct udevice *get_atsha204a_dev(void)
+{
+ static struct udevice *dev = NULL;
+
+ if (dev != NULL)
+ return dev;
+
+ if (uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", &dev)) {
+ puts("Cannot find ATSHA204A on I2C bus!\n");
+ dev = NULL;
+ }
+
+ return dev;
+}
+#endif
+
+int checkboard(void)
+{
+ u32 version_num, serial_num;
+ int err = 1;
+
+#ifdef CONFIG_ATSHA204A
+ struct udevice *dev = get_atsha204a_dev();
+
+ if (dev) {
+ err = atsha204a_wakeup(dev);
+ if (err)
+ goto out;
+
+ err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
+ OMNIA_ATSHA204_OTP_VERSION,
+ (u8 *) &version_num);
+ if (err)
+ goto out;
+
+ err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
+ OMNIA_ATSHA204_OTP_SERIAL,
+ (u8 *) &serial_num);
+ if (err)
+ goto out;
+
+ atsha204a_sleep(dev);
+ }
+
+out:
+#endif
+
+ if (err)
+ printf("Board: Turris Omnia (ver N/A). SN: N/A\n");
+ else
+ printf("Board: Turris Omnia SNL %08X%08X\n",
+ be32_to_cpu(version_num), be32_to_cpu(serial_num));
+
+ return 0;
+}
+
+static void increment_mac(u8 *mac)
+{
+ int i;
+
+ for (i = 5; i >= 3; i--) {
+ mac[i] += 1;
+ if (mac[i])
+ break;
+ }
+}
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_ATSHA204A
+ int err;
+ struct udevice *dev = get_atsha204a_dev();
+ u8 mac0[4], mac1[4], mac[6];
+
+ if (!dev)
+ goto out;
+
+ err = atsha204a_wakeup(dev);
+ if (err)
+ goto out;
+
+ err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
+ OMNIA_ATSHA204_OTP_MAC0, mac0);
+ if (err)
+ goto out;
+
+ err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
+ OMNIA_ATSHA204_OTP_MAC1, mac1);
+ if (err)
+ goto out;
+
+ atsha204a_sleep(dev);
+
+ mac[0] = mac0[1];
+ mac[1] = mac0[2];
+ mac[2] = mac0[3];
+ mac[3] = mac1[1];
+ mac[4] = mac1[2];
+ mac[5] = mac1[3];
+
+ if (is_valid_ethaddr(mac))
+ eth_setenv_enetaddr("ethaddr", mac);
+
+ increment_mac(mac);
+
+ if (is_valid_ethaddr(mac))
+ eth_setenv_enetaddr("eth1addr", mac);
+
+ increment_mac(mac);
+
+ if (is_valid_ethaddr(mac))
+ eth_setenv_enetaddr("eth2addr", mac);
+
+out:
+#endif
+
+ return 0;
+}
+
MEM_4G, /* mem_size */
DDR_FREQ_800, /* frequency */
0, 0, /* cas_l cas_wl */
- HWS_TEMP_LOW} }, /* temperature */
+ HWS_TEMP_LOW, /* temperature */
+ HWS_TIM_DEFAULT} }, /* timing */
5, /* Num Of Bus Per Interface*/
BUS_MASK_32BIT /* Busses mask */
};
MEM_4G, /* mem_size */
DDR_FREQ_800, /* frequency */
0, 0, /* cas_l cas_wl */
- HWS_TEMP_LOW} }, /* temperature */
+ HWS_TEMP_LOW, /* temperature */
+ HWS_TIM_DEFAULT} }, /* timing */
5, /* Num Of Bus Per Interface*/
BUS_MASK_32BIT /* Busses mask */
};
#include <asm/arch/mx6-pins.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
M28EVK BOARD
-M: Marek Vasut <marek.vasut@gmail.com>
-S: Maintained
+#M: Marek Vasut <marek.vasut@gmail.com>
+S: Orphan (since 2017-07)
F: board/aries/m28evk/
F: include/configs/m28evk.h
F: configs/m28evk_defconfig
M53EVK BOARD
-M: Marek Vasut <marek.vasut@gmail.com>
-S: Maintained
+#M: Marek Vasut <marek.vasut@gmail.com>
+S: Orphan (since 2017-07)
F: board/aries/m53evk/
F: include/configs/m53evk.h
F: configs/m53evk_defconfig
*
* The syntax is taken as close as possible with the kwbimage
*/
-#include <asm/imx-common/imximage.cfg>
+#include <asm/mach-imx/imximage.cfg>
/* image version */
IMAGE_VERSION 2
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux-mx53.h>
-#include <asm/imx-common/mx5_video.h>
+#include <asm/mach-imx/mx5_video.h>
#include <asm/spl.h>
#include <linux/errno.h>
#include <netdev.h>
Aries MA5D4EVK BOARD
-M: Marek Vasut <marek.vasut@gmail.com>
-S: Maintained
+#M: Marek Vasut <marek.vasut@gmail.com>
+S: Orphan (since 2017-07)
F: board/aries/ma5d4evk/
F: include/configs/ma5d4evk.h
F: configs/ma5d4evk_defconfig
Aries MCVEVK BOARD
-M: Marek Vasut <marek.vasut@gmail.com>
-S: Maintained
+#M: Marek Vasut <marek.vasut@gmail.com>
+S: Orphan (since 2017-07)
F: include/configs/socfpga_mcvevk.h
F: configs/socfpga_mcvevk_defconfig
#include <asm/arch/mx6-pins.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <asm/arch/mx6-pins.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <asm/arch/mx6-pins.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
default "opos6uldev"
config IMX_CONFIG
- default "arch/arm/imx-common/spl_sd.cfg"
+ default "arch/arm/mach-imx/spl_sd.cfg"
endif
#include <asm/arch/opos6ul.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
#include <common.h>
dram_size += gd->bd->bi_dram[i].size;
nand_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += nand_info[i]->size;
+ nand_size += get_nand_dev_by_index(i)->size;
lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
dram_size >> 20,
nand_size >> 20 );
dram_size += gd->bd->bi_dram[i].size;
nand_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += nand_info[i]->size;
+ nand_size += get_nand_dev_by_index(i)->size;
#ifdef CONFIG_MTD_NOR_FLASH
flash_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
dram_size += gd->bd->bi_dram[i].size;
nand_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += nand_info[i]->size;
+ nand_size += get_nand_dev_by_index(i)->size;
lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
dram_size >> 20,
nand_size >> 20 );
dram_size += gd->bd->bi_dram[i].size;
nand_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += nand_info[i]->size;
+ nand_size += get_nand_dev_by_index(i)->size;
lcd_printf(" %ld MB SDRAM, %ld MB NAND\n",
dram_size >> 20,
nand_size >> 20);
dram_size += gd->bd->bi_dram[i].size;
nand_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += nand_info[i]->size;
+ nand_size += get_nand_dev_by_index(i)->size;
lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
dram_size >> 20,
nand_size >> 20 );
dram_size += gd->bd->bi_dram[i].size;
nand_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += nand_info[i]->size;
+ nand_size += get_nand_dev_by_index(i)->size;
lcd_printf(" %ld MB SDRAM, %ld MB NAND\n",
dram_size >> 20,
nand_size >> 20);
nand_size = 0;
#ifdef CONFIG_NAND_ATMEL
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += nand_info[i]->size;
+ nand_size += get_nand_dev_by_index(i)->size;
#endif
lcd_printf("%ld MB SDRAM, %lld MB NAND\n",
dram_size >> 20, nand_size >> 20);
nand_size = 0;
#ifdef CONFIG_NAND_ATMEL
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += nand_info[i]->size;
+ nand_size += get_nand_dev_by_index(i)->size;
#endif
lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
dram_size >> 20, nand_size >> 20);
nand_size = 0;
#ifdef CONFIG_NAND_ATMEL
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += nand_info[i]->size;
+ nand_size += get_nand_dev_by_index(i)->size;
#endif
lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
dram_size >> 20, nand_size >> 20);
#include <asm/arch/iomux.h>
#include <malloc.h>
#include <asm/arch/mx6-pins.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/sata.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/boot_mode.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/sys_proto.h>
#include <mmc.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
#include "platinum.h"
#include <asm/arch/clock.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <i2c.h>
#include <miiphy.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <miiphy.h>
#include <micrel.h>
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <spl.h>
#include "platinum.h"
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <spl.h>
#include "platinum.h"
#include <asm/arch/crm_regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/boot_mode.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <micrel.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux-mx53.h>
#include <asm/arch/clock.h>
-#include <asm/imx-common/mx5_video.h>
+#include <asm/mach-imx/mx5_video.h>
#include <ACEX1K.h>
#include <netdev.h>
#include <i2c.h>
#include <asm/arch/mx6-pins.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/sata.h>
-#include <asm/imx-common/spi.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/spi.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <micrel.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <asm/io.h>
#include <common.h>
#include <fsl_esdhc.h>
#ifdef CONFIG_PCI_TEGRA
int tegra_pcie_board_init(void)
{
+/* TODO: Convert to driver model
struct udevice *pmic;
int err;
error("failed to set SD4 voltage: %d\n", err);
return err;
}
+*/
return 0;
}
#include <asm/arch/sys_proto.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mxc_hdmi.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/sata.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/video.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <dm/platform_data/serial_mxc.h>
#include <common.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/spi.h>
+#include <asm/mach-imx/spi.h>
#include <fsl_esdhc.h>
#include "common.h"
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
#include <fsl_esdhc.h>
#include "common.h"
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/sata.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
select X86_RESET_VECTOR if !EFI_STUB
select INTEL_BAYTRAIL
select BOARD_ROMSIZE_KB_8192
+ select BOARD_LATE_INIT
config PCIE_ECAM_BASE
default 0xe0000000
select X86_RESET_VECTOR if !EFI_STUB
select INTEL_BAYTRAIL
select BOARD_ROMSIZE_KB_8192
+ select BOARD_LATE_INIT
config PCIE_ECAM_BASE
default 0xe0000000
return 0;
}
+
+int board_late_init(void)
+{
+ struct gpio_desc desc;
+ int ret;
+
+ ret = dm_gpio_lookup_name("F10", &desc);
+ if (ret)
+ debug("gpio ret=%d\n", ret);
+ ret = dm_gpio_request(&desc, "xhci_hub_reset");
+ if (ret)
+ debug("gpio_request ret=%d\n", ret);
+ ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
+ if (ret)
+ debug("gpio dir ret=%d\n", ret);
+
+ /* Pull xHCI hub reset to low (active low) */
+ dm_gpio_set_value(&desc, 0);
+
+ /* Wait at least 5 ms, so lets choose 10 to be safe */
+ mdelay(10);
+
+ /* Pull xHCI hub reset to high (active low) */
+ dm_gpio_set_value(&desc, 1);
+
+ return 0;
+}
#include <asm/arch/mx6-pins.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <asm/arch/mx6-pins.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/spi.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/spi.h>
+#include <asm/mach-imx/video.h>
#include <i2c.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/video.h>
DECLARE_GLOBAL_DATA_PTR;
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
#include "../common/board.h"
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/video.h>
#include "../common/board.h"
S: Maintained
F: board/engicam/icorem6_rqs
F: include/configs/imx6qdl_icore_rqs.h
-F: configs/imx6qdl_icore_rqs_mmc_defconfig
+F: configs/imx6qdl_icore_rqs_defconfig
F: arch/arm/dts/imx6qdl-icore-rqs.dtsi
F: arch/arm/dts/imx6q-icore-rqs.dts
F: arch/arm/dts/imx6dl-icore-rqs.dts
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
#include "../common/board.h"
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
#include "../common/board.h"
select SPL_BOARD_INIT if (ARM && SPL)
select SHA_HW_ACCEL
select SHA_PROG_HW_ACCEL
+ select ENV_IS_NOWHERE
bool
default y
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
-#include <asm/imx-common/mx5_video.h>
+#include <asm/mach-imx/mx5_video.h>
#include <i2c.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux-mx53.h>
#include <linux/errno.h>
-#include <asm/imx-common/boot_mode.h>
+#include <asm/mach-imx/boot_mode.h>
#include <netdev.h>
#include <i2c.h>
#include <mmc.h>
#include <asm/arch/iomux-mx53.h>
#include <asm/arch/clock.h>
#include <linux/errno.h>
-#include <asm/imx-common/mx5_video.h>
+#include <asm/mach-imx/mx5_video.h>
#include <netdev.h>
#include <i2c.h>
#include <mmc.h>
#include <asm/arch/clock.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
+++ /dev/null
-if TARGET_MX6QSABREAUTO
-
-config SYS_BOARD
- default "mx6qsabreauto"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "mx6qsabreauto"
-
-endif
+++ /dev/null
-MX6QSABREAUTO BOARD
-M: Fabio Estevam <fabio.estevam@nxp.com>
-M: Peng Fan <peng.fan@nxp.com>
-S: Maintained
-F: board/freescale/mx6qsabreauto/
-F: include/configs/mx6qsabreauto.h
-F: configs/mx6dlsabreauto_defconfig
-F: configs/mx6qsabreauto_defconfig
-F: configs/mx6qpsabreauto_defconfig
+++ /dev/null
-#
-# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
-#
-# (C) Copyright 2011 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := mx6qsabreauto.o
+++ /dev/null
-/*
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Refer doc/README.imximage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-/* image version */
-
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of
- * spi, sd (the board has no nand neither onenand)
- */
-BOOT_FROM sd
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type Address Value
- *
- * where:
- * Addr-type register length (1,2 or 4 bytes)
- * Address absolute address of the register
- * value value to be stored in the register
- */
-DATA 4 0x020e0798 0x000C0000
-DATA 4 0x020e0758 0x00000000
-DATA 4 0x020e0588 0x00000030
-DATA 4 0x020e0594 0x00000030
-DATA 4 0x020e056c 0x00000030
-DATA 4 0x020e0578 0x00000030
-DATA 4 0x020e074c 0x00000030
-DATA 4 0x020e057c 0x00000030
-DATA 4 0x020e058c 0x00000000
-DATA 4 0x020e059c 0x00000030
-DATA 4 0x020e05a0 0x00000030
-DATA 4 0x020e078c 0x00000030
-DATA 4 0x020e0750 0x00020000
-DATA 4 0x020e05a8 0x00000028
-DATA 4 0x020e05b0 0x00000028
-DATA 4 0x020e0524 0x00000028
-DATA 4 0x020e051c 0x00000028
-DATA 4 0x020e0518 0x00000028
-DATA 4 0x020e050c 0x00000028
-DATA 4 0x020e05b8 0x00000028
-DATA 4 0x020e05c0 0x00000028
-DATA 4 0x020e0774 0x00020000
-DATA 4 0x020e0784 0x00000028
-DATA 4 0x020e0788 0x00000028
-DATA 4 0x020e0794 0x00000028
-DATA 4 0x020e079c 0x00000028
-DATA 4 0x020e07a0 0x00000028
-DATA 4 0x020e07a4 0x00000028
-DATA 4 0x020e07a8 0x00000028
-DATA 4 0x020e0748 0x00000028
-DATA 4 0x020e05ac 0x00000028
-DATA 4 0x020e05b4 0x00000028
-DATA 4 0x020e0528 0x00000028
-DATA 4 0x020e0520 0x00000028
-DATA 4 0x020e0514 0x00000028
-DATA 4 0x020e0510 0x00000028
-DATA 4 0x020e05bc 0x00000028
-DATA 4 0x020e05c4 0x00000028
-DATA 4 0x021b0800 0xa1390003
-DATA 4 0x021b080c 0x001F001F
-DATA 4 0x021b0810 0x001F001F
-DATA 4 0x021b480c 0x001F001F
-DATA 4 0x021b4810 0x001F001F
-DATA 4 0x021b083c 0x43260335
-DATA 4 0x021b0840 0x031A030B
-DATA 4 0x021b483c 0x4323033B
-DATA 4 0x021b4840 0x0323026F
-DATA 4 0x021b0848 0x483D4545
-DATA 4 0x021b4848 0x44433E48
-DATA 4 0x021b0850 0x41444840
-DATA 4 0x021b4850 0x4835483E
-DATA 4 0x021b081c 0x33333333
-DATA 4 0x021b0820 0x33333333
-DATA 4 0x021b0824 0x33333333
-DATA 4 0x021b0828 0x33333333
-DATA 4 0x021b481c 0x33333333
-DATA 4 0x021b4820 0x33333333
-DATA 4 0x021b4824 0x33333333
-DATA 4 0x021b4828 0x33333333
-DATA 4 0x021b08b8 0x00000800
-DATA 4 0x021b48b8 0x00000800
-DATA 4 0x021b0004 0x00020036
-DATA 4 0x021b0008 0x09444040
-DATA 4 0x021b000c 0x8A8F7955
-DATA 4 0x021b0010 0xFF328F64
-DATA 4 0x021b0014 0x01FF00DB
-DATA 4 0x021b0018 0x00001740
-DATA 4 0x021b001c 0x00008000
-DATA 4 0x021b002c 0x000026d2
-DATA 4 0x021b0030 0x008F1023
-DATA 4 0x021b0040 0x00000047
-DATA 4 0x021b0000 0x841A0000
-DATA 4 0x021b001c 0x04088032
-DATA 4 0x021b001c 0x00008033
-DATA 4 0x021b001c 0x00048031
-DATA 4 0x021b001c 0x09408030
-DATA 4 0x021b001c 0x04008040
-DATA 4 0x021b0020 0x00005800
-DATA 4 0x021b0818 0x00011117
-DATA 4 0x021b4818 0x00011117
-DATA 4 0x021b0004 0x00025576
-DATA 4 0x021b0404 0x00011006
-DATA 4 0x021b001c 0x00000000
-
-/* set the default clock gate to save power */
-DATA 4 0x020c4068 0x00C03F3F
-DATA 4 0x020c406c 0x0030FC03
-DATA 4 0x020c4070 0x0FFFC000
-DATA 4 0x020c4074 0x3FF00000
-DATA 4 0x020c4078 0xFFFFF300
-DATA 4 0x020c407c 0x0F0000F3
-DATA 4 0x020c4080 0x00000FFF
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4 0x020e0010 0xF00000CF
-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4 0x020e0018 0x007F007F
-DATA 4 0x020e001c 0x007F007F
+++ /dev/null
-/*
- * Copyright (C) 2013 Freescale Semiconductor, Inc.
- * Jason Liu <r64343@freescale.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Refer doc/README.imximage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-/* image version */
-
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of
- * spi, sd (the board has no nand neither onenand)
- */
-BOOT_FROM sd
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type Address Value
- *
- * where:
- * Addr-type register length (1,2 or 4 bytes)
- * Address absolute address of the register
- * value value to be stored in the register
- */
-DATA 4 0x020e0774 0x000C0000
-DATA 4 0x020e0754 0x00000000
-DATA 4 0x020e04ac 0x00000030
-DATA 4 0x020e04b0 0x00000030
-DATA 4 0x020e0464 0x00000030
-DATA 4 0x020e0490 0x00000030
-DATA 4 0x020e074c 0x00000030
-DATA 4 0x020e0494 0x00000030
-DATA 4 0x020e04a0 0x00000000
-DATA 4 0x020e04b4 0x00000030
-DATA 4 0x020e04b8 0x00000030
-DATA 4 0x020e076c 0x00000030
-DATA 4 0x020e0750 0x00020000
-DATA 4 0x020e04bc 0x00000028
-DATA 4 0x020e04c0 0x00000028
-DATA 4 0x020e04c4 0x00000028
-DATA 4 0x020e04c8 0x00000028
-DATA 4 0x020e04cc 0x00000028
-DATA 4 0x020e04d0 0x00000028
-DATA 4 0x020e04d4 0x00000028
-DATA 4 0x020e04d8 0x00000028
-DATA 4 0x020e0760 0x00020000
-DATA 4 0x020e0764 0x00000028
-DATA 4 0x020e0770 0x00000028
-DATA 4 0x020e0778 0x00000028
-DATA 4 0x020e077c 0x00000028
-DATA 4 0x020e0780 0x00000028
-DATA 4 0x020e0784 0x00000028
-DATA 4 0x020e078c 0x00000028
-DATA 4 0x020e0748 0x00000028
-DATA 4 0x020e0470 0x00000028
-DATA 4 0x020e0474 0x00000028
-DATA 4 0x020e0478 0x00000028
-DATA 4 0x020e047c 0x00000028
-DATA 4 0x020e0480 0x00000028
-DATA 4 0x020e0484 0x00000028
-DATA 4 0x020e0488 0x00000028
-DATA 4 0x020e048c 0x00000028
-DATA 4 0x021b0800 0xa1390003
-DATA 4 0x021b080c 0x001F001F
-DATA 4 0x021b0810 0x001F001F
-DATA 4 0x021b480c 0x001F001F
-DATA 4 0x021b4810 0x001F001F
-DATA 4 0x021b083c 0x42190217
-DATA 4 0x021b0840 0x017B017B
-DATA 4 0x021b483c 0x4176017B
-DATA 4 0x021b4840 0x015F016C
-DATA 4 0x021b0848 0x4C4C4D4C
-DATA 4 0x021b4848 0x4A4D4C48
-DATA 4 0x021b0850 0x3F3F3F40
-DATA 4 0x021b4850 0x3538382E
-DATA 4 0x021b081c 0x33333333
-DATA 4 0x021b0820 0x33333333
-DATA 4 0x021b0824 0x33333333
-DATA 4 0x021b0828 0x33333333
-DATA 4 0x021b481c 0x33333333
-DATA 4 0x021b4820 0x33333333
-DATA 4 0x021b4824 0x33333333
-DATA 4 0x021b4828 0x33333333
-DATA 4 0x021b08b8 0x00000800
-DATA 4 0x021b48b8 0x00000800
-DATA 4 0x021b0004 0x00020025
-DATA 4 0x021b0008 0x00333030
-DATA 4 0x021b000c 0x676B5313
-DATA 4 0x021b0010 0xB66E8B63
-DATA 4 0x021b0014 0x01FF00DB
-DATA 4 0x021b0018 0x00001740
-DATA 4 0x021b001c 0x00008000
-DATA 4 0x021b002c 0x000026d2
-DATA 4 0x021b0030 0x006B1023
-DATA 4 0x021b0040 0x00000047
-DATA 4 0x021b0000 0x841A0000
-DATA 4 0x021b001c 0x04008032
-DATA 4 0x021b001c 0x00008033
-DATA 4 0x021b001c 0x00048031
-DATA 4 0x021b001c 0x05208030
-DATA 4 0x021b001c 0x04008040
-DATA 4 0x021b0020 0x00005800
-DATA 4 0x021b0818 0x00011117
-DATA 4 0x021b4818 0x00011117
-DATA 4 0x021b0004 0x00025565
-DATA 4 0x021b0404 0x00011006
-DATA 4 0x021b001c 0x00000000
-
-/* set the default clock gate to save power */
-DATA 4 0x020c4068 0x00C03F3F
-DATA 4 0x020c406c 0x0030FC03
-DATA 4 0x020c4070 0x0FFFC000
-DATA 4 0x020c4074 0x3FF00000
-DATA 4 0x020c4078 0xFFFFF300
-DATA 4 0x020c407c 0x0F0000C3
-DATA 4 0x020c4080 0x00000FFF
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4 0x020e0010 0xF00000CF
-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4 0x020e0018 0x007F007F
-DATA 4 0x020e001c 0x007F007F
+++ /dev/null
-/*
- * Copyright (C) 2015 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Refer doc/README.imximage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-/* image version */
-
-#define __ASSEMBLY__
-#include <config.h>
-
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of spi, sd, eimnor, nand, sata:
- * spinor: flash_offset: 0x0400
- * nand: flash_offset: 0x0400
- * sata: flash_offset: 0x0400
- * sd/mmc: flash_offset: 0x0400
- * eimnor: flash_offset: 0x1000
- */
-BOOT_FROM sd
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type Address Value
- *
- * where:
- * Addr-type register length (1,2 or 4 bytes)
- * Address absolute address of the register
- * value value to be stored in the register
- */
-DATA 4 0x020e0798 0x000C0000
-DATA 4 0x020e0758 0x00000000
-DATA 4 0x020e0588 0x00000030
-DATA 4 0x020e0594 0x00000030
-DATA 4 0x020e056c 0x00000030
-DATA 4 0x020e0578 0x00000030
-DATA 4 0x020e074c 0x00000030
-DATA 4 0x020e057c 0x00000030
-DATA 4 0x020e058c 0x00000000
-DATA 4 0x020e059c 0x00000030
-DATA 4 0x020e05a0 0x00000030
-DATA 4 0x020e078c 0x00000030
-DATA 4 0x020e0750 0x00020000
-DATA 4 0x020e05a8 0x00000030
-DATA 4 0x020e05b0 0x00000030
-DATA 4 0x020e0524 0x00000030
-DATA 4 0x020e051c 0x00000030
-DATA 4 0x020e0518 0x00000030
-DATA 4 0x020e050c 0x00000030
-DATA 4 0x020e05b8 0x00000030
-DATA 4 0x020e05c0 0x00000030
-DATA 4 0x020e0774 0x00020000
-DATA 4 0x020e0784 0x00000030
-DATA 4 0x020e0788 0x00000030
-DATA 4 0x020e0794 0x00000030
-DATA 4 0x020e079c 0x00000030
-DATA 4 0x020e07a0 0x00000030
-DATA 4 0x020e07a4 0x00000030
-DATA 4 0x020e07a8 0x00000030
-DATA 4 0x020e0748 0x00000030
-DATA 4 0x020e05ac 0x00000030
-DATA 4 0x020e05b4 0x00000030
-DATA 4 0x020e0528 0x00000030
-DATA 4 0x020e0520 0x00000030
-DATA 4 0x020e0514 0x00000030
-DATA 4 0x020e0510 0x00000030
-DATA 4 0x020e05bc 0x00000030
-DATA 4 0x020e05c4 0x00000030
-DATA 4 0x021b0800 0xa1390003
-DATA 4 0x021b080c 0x001b001e
-DATA 4 0x021b0810 0x002e0029
-DATA 4 0x021b480c 0x001b002a
-DATA 4 0x021b4810 0x0019002c
-DATA 4 0x021b083c 0x43240334
-DATA 4 0x021b0840 0x0324031a
-DATA 4 0x021b483c 0x43340344
-DATA 4 0x021b4840 0x03280276
-DATA 4 0x021b0848 0x44383A3E
-DATA 4 0x021b4848 0x3C3C3846
-DATA 4 0x021b0850 0x2e303230
-DATA 4 0x021b4850 0x38283E34
-DATA 4 0x021b081c 0x33333333
-DATA 4 0x021b0820 0x33333333
-DATA 4 0x021b0824 0x33333333
-DATA 4 0x021b0828 0x33333333
-DATA 4 0x021b481c 0x33333333
-DATA 4 0x021b4820 0x33333333
-DATA 4 0x021b4824 0x33333333
-DATA 4 0x021b4828 0x33333333
-DATA 4 0x021b08c0 0x24912492
-DATA 4 0x021b48c0 0x24912492
-DATA 4 0x021b08b8 0x00000800
-DATA 4 0x021b48b8 0x00000800
-DATA 4 0x021b0004 0x00020036
-DATA 4 0x021b0008 0x09444040
-DATA 4 0x021b000c 0x898E7955
-DATA 4 0x021b0010 0xFF328F64
-DATA 4 0x021b0014 0x01FF00DB
-DATA 4 0x021b0018 0x00001740
-DATA 4 0x021b001c 0x00008000
-
-DATA 4 0x021b002c 0x000026d2
-DATA 4 0x021b0030 0x008E1023
-DATA 4 0x021b0040 0x00000047
-DATA 4 0x021b0400 0x14420000
-DATA 4 0x021b0000 0x841A0000
-DATA 4 0x00bb0008 0x00000004
-DATA 4 0x00bb000c 0x2891E41A
-DATA 4 0x00bb0038 0x00000564
-DATA 4 0x00bb0014 0x00000040
-DATA 4 0x00bb0028 0x00000020
-DATA 4 0x00bb002c 0x00000020
-DATA 4 0x021b001c 0x04088032
-DATA 4 0x021b001c 0x00008033
-DATA 4 0x021b001c 0x00048031
-DATA 4 0x021b001c 0x09408030
-DATA 4 0x021b001c 0x04008040
-DATA 4 0x021b0020 0x00005800
-DATA 4 0x021b0818 0x00011117
-DATA 4 0x021b4818 0x00011117
-DATA 4 0x021b0004 0x00025576
-DATA 4 0x021b0404 0x00011006
-DATA 4 0x021b001c 0x00000000
-/* set the default clock gate to save power */
-DATA 4, 0x020c4068, 0x00C03F3F
-DATA 4, 0x020c406c, 0x0030FC03
-DATA 4, 0x020c4070, 0x0FFFC000
-DATA 4, 0x020c4074, 0x3FF00000
-DATA 4, 0x020c4078, 0xFFFFF300
-DATA 4, 0x020c407c, 0x0F0000F3
-DATA 4, 0x020c4080, 0x00000FFF
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4, 0x020e0010, 0xF00000CF
-/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
-DATA 4, 0x020e0018, 0x77177717
-DATA 4, 0x020e001c, 0x77177717
+++ /dev/null
-/*
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
- *
- * Author: Fabio Estevam <fabio.estevam@freescale.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-pins.h>
-#include <linux/errno.h>
-#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/spi.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <asm/arch/sys_proto.h>
-#include <i2c.h>
-#include <asm/arch/mxc_hdmi.h>
-#include <asm/imx-common/video.h>
-#include <asm/arch/crm_regs.h>
-#include <pca953x.h>
-#include <power/pmic.h>
-#include <power/pfuze100_pmic.h>
-#include "../common/pfuze.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
- PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
-#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
-#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
- PAD_CTL_SRE_FAST)
-#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
-
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-
-#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-#define I2C_PMIC 1
-
-int dram_init(void)
-{
- gd->ram_size = imx_ddr_size();
-
- return 0;
-}
-
-static iomux_v3_cfg_t const uart4_pads[] = {
- MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const enet_pads[] = {
- MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
-};
-
-/* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
-static struct i2c_pads_info i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
- .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
- .gp = IMX_GPIO_NR(2, 30)
- },
- .sda = {
- .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
- .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
- .gp = IMX_GPIO_NR(4, 13)
- }
-};
-
-#ifndef CONFIG_SYS_FLASH_CFI
-/*
- * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
- * Compass Sensor, Accelerometer, Res Touch
- */
-static struct i2c_pads_info i2c_pad_info2 = {
- .scl = {
- .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
- .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
- .gp = IMX_GPIO_NR(1, 3)
- },
- .sda = {
- .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
- .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
- .gp = IMX_GPIO_NR(3, 18)
- }
-};
-#endif
-
-static iomux_v3_cfg_t const i2c3_pads[] = {
- MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const port_exp[] = {
- MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-/*Define for building port exp gpio, pin starts from 0*/
-#define PORTEXP_IO_NR(chip, pin) \
- ((chip << 5) + pin)
-
-/*Get the chip addr from a ioexp gpio*/
-#define PORTEXP_IO_TO_CHIP(gpio_nr) \
- (gpio_nr >> 5)
-
-/*Get the pin number from a ioexp gpio*/
-#define PORTEXP_IO_TO_PIN(gpio_nr) \
- (gpio_nr & 0x1f)
-
-static int port_exp_direction_output(unsigned gpio, int value)
-{
- int ret;
-
- i2c_set_bus_num(2);
- ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
- if (ret)
- return ret;
-
- ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
- (1 << PORTEXP_IO_TO_PIN(gpio)),
- (PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));
-
- if (ret)
- return ret;
-
- ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
- (1 << PORTEXP_IO_TO_PIN(gpio)),
- (value << PORTEXP_IO_TO_PIN(gpio)));
-
- if (ret)
- return ret;
-
- return 0;
-}
-
-static iomux_v3_cfg_t const eimnor_pads[] = {
- MX6_PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL) ,
- MX6_PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
- MX6_PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static void eimnor_cs_setup(void)
-{
- struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
-
- writel(0x00020181, &weim_regs->cs0gcr1);
- writel(0x00000001, &weim_regs->cs0gcr2);
- writel(0x0a020000, &weim_regs->cs0rcr1);
- writel(0x0000c000, &weim_regs->cs0rcr2);
- writel(0x0804a240, &weim_regs->cs0wcr1);
- writel(0x00000120, &weim_regs->wcr);
-
- set_chipselect_size(CS0_128);
-}
-
-static void eim_clk_setup(void)
-{
- struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- int cscmr1, ccgr6;
-
-
- /* Turn off EIM clock */
- ccgr6 = readl(&imx_ccm->CCGR6);
- ccgr6 &= ~(0x3 << 10);
- writel(ccgr6, &imx_ccm->CCGR6);
-
- /*
- * Configure clk_eim_slow_sel = 00 --> derive clock from AXI clk root
- * and aclk_eim_slow_podf = 01 --> divide by 2
- * so that we can have EIM at the maximum clock of 132MHz
- */
- cscmr1 = readl(&imx_ccm->cscmr1);
- cscmr1 &= ~(MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK |
- MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK);
- cscmr1 |= (1 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET);
- writel(cscmr1, &imx_ccm->cscmr1);
-
- /* Turn on EIM clock */
- ccgr6 |= (0x3 << 10);
- writel(ccgr6, &imx_ccm->CCGR6);
-}
-
-static void setup_iomux_eimnor(void)
-{
- imx_iomux_v3_setup_multiple_pads(eimnor_pads, ARRAY_SIZE(eimnor_pads));
-
- gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
-
- eimnor_cs_setup();
-}
-
-static void setup_iomux_enet(void)
-{
- imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
-}
-
-static iomux_v3_cfg_t const usdhc3_pads[] = {
- MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static void setup_iomux_uart(void)
-{
- imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
-}
-
-#ifdef CONFIG_FSL_ESDHC
-static struct fsl_esdhc_cfg usdhc_cfg[1] = {
- {USDHC3_BASE_ADDR},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- gpio_direction_input(IMX_GPIO_NR(6, 15));
- return !gpio_get_value(IMX_GPIO_NR(6, 15));
-}
-
-int board_mmc_init(bd_t *bis)
-{
- imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
-
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
-}
-#endif
-
-#ifdef CONFIG_NAND_MXS
-static iomux_v3_cfg_t gpmi_pads[] = {
- MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0),
- MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL1),
-};
-
-static void setup_gpmi_nand(void)
-{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- /* config gpmi nand iomux */
- imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
-
- setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
- MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
- MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)));
-
- /* enable apbh clock gating */
- setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
-}
-#endif
-
-static void setup_fec(void)
-{
- if (is_mx6dqp()) {
- /*
- * select ENET MAC0 TX clock from PLL
- */
- imx_iomux_set_gpr_register(5, 9, 1, 1);
- enable_fec_anatop_clock(0, ENET_125MHZ);
- }
-
- setup_iomux_enet();
-}
-
-int board_eth_init(bd_t *bis)
-{
- setup_fec();
-
- return cpu_eth_init(bis);
-}
-
-#define BOARD_REV_B 0x200
-#define BOARD_REV_A 0x100
-
-static int mx6sabre_rev(void)
-{
- /*
- * Get Board ID information from OCOTP_GP1[15:8]
- * i.MX6Q ARD RevA: 0x01
- * i.MX6Q ARD RevB: 0x02
- */
- struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
- struct fuse_bank *bank = &ocotp->bank[4];
- struct fuse_bank4_regs *fuse =
- (struct fuse_bank4_regs *)bank->fuse_regs;
- int reg = readl(&fuse->gp1);
- int ret;
-
- switch (reg >> 8 & 0x0F) {
- case 0x02:
- ret = BOARD_REV_B;
- break;
- case 0x01:
- default:
- ret = BOARD_REV_A;
- break;
- }
-
- return ret;
-}
-
-u32 get_board_rev(void)
-{
- int rev = mx6sabre_rev();
-
- return (get_cpu_rev() & ~(0xF << 8)) | rev;
-}
-
-#if defined(CONFIG_VIDEO_IPUV3)
-static void disable_lvds(struct display_info_t const *dev)
-{
- struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
- clrbits_le32(&iomux->gpr[2],
- IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
- IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
-}
-
-static void do_enable_hdmi(struct display_info_t const *dev)
-{
- disable_lvds(dev);
- imx_enable_hdmi_phy();
-}
-
-struct display_info_t const displays[] = {{
- .bus = -1,
- .addr = 0,
- .pixfmt = IPU_PIX_FMT_RGB666,
- .detect = NULL,
- .enable = NULL,
- .mode = {
- .name = "Hannstar-XGA",
- .refresh = 60,
- .xres = 1024,
- .yres = 768,
- .pixclock = 15385,
- .left_margin = 220,
- .right_margin = 40,
- .upper_margin = 21,
- .lower_margin = 7,
- .hsync_len = 60,
- .vsync_len = 10,
- .sync = FB_SYNC_EXT,
- .vmode = FB_VMODE_NONINTERLACED
-} }, {
- .bus = -1,
- .addr = 0,
- .pixfmt = IPU_PIX_FMT_RGB24,
- .detect = detect_hdmi,
- .enable = do_enable_hdmi,
- .mode = {
- .name = "HDMI",
- .refresh = 60,
- .xres = 1024,
- .yres = 768,
- .pixclock = 15385,
- .left_margin = 220,
- .right_margin = 40,
- .upper_margin = 21,
- .lower_margin = 7,
- .hsync_len = 60,
- .vsync_len = 10,
- .sync = FB_SYNC_EXT,
- .vmode = FB_VMODE_NONINTERLACED,
-} } };
-size_t display_count = ARRAY_SIZE(displays);
-
-iomux_v3_cfg_t const backlight_pads[] = {
- MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-};
-
-static void setup_iomux_backlight(void)
-{
- gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
- imx_iomux_v3_setup_multiple_pads(backlight_pads,
- ARRAY_SIZE(backlight_pads));
-}
-
-static void setup_display(void)
-{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
- int reg;
-
- setup_iomux_backlight();
- enable_ipu_clock();
- imx_setup_hdmi();
-
- /* Turn on LDB_DI0 and LDB_DI1 clocks */
- reg = readl(&mxc_ccm->CCGR3);
- reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
- writel(reg, &mxc_ccm->CCGR3);
-
- /* Set LDB_DI0 and LDB_DI1 clk select to 3b'011 */
- reg = readl(&mxc_ccm->cs2cdr);
- reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
- MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
- reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
- (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
- writel(reg, &mxc_ccm->cs2cdr);
-
- reg = readl(&mxc_ccm->cscmr2);
- reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
- writel(reg, &mxc_ccm->cscmr2);
-
- reg = readl(&mxc_ccm->chsccdr);
- reg |= (CHSCCDR_CLK_SEL_LDB_DI0
- << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
- reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
- MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
- writel(reg, &mxc_ccm->chsccdr);
-
- reg = IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
- IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
- IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
- IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
- IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
- IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
- IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
- IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED;
- writel(reg, &iomux->gpr[2]);
-
- reg = readl(&iomux->gpr[3]);
- reg &= ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
- IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
- reg |= (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
- IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
- (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
- IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET);
- writel(reg, &iomux->gpr[3]);
-}
-#endif /* CONFIG_VIDEO_IPUV3 */
-
-/*
- * Do not overwrite the console
- * Use always serial for U-Boot console
- */
-int overwrite_console(void)
-{
- return 1;
-}
-
-int board_early_init_f(void)
-{
- setup_iomux_uart();
-
-#ifdef CONFIG_NAND_MXS
- setup_gpmi_nand();
-#endif
- eim_clk_setup();
-
- return 0;
-}
-
-int board_init(void)
-{
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
- /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
- /* I2C 3 Steer */
- gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
- imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
-#ifndef CONFIG_SYS_FLASH_CFI
- setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
-#endif
- gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
- imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));
-
-#ifdef CONFIG_VIDEO_IPUV3
- setup_display();
-#endif
- setup_iomux_eimnor();
- return 0;
-}
-
-#ifdef CONFIG_MXC_SPI
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
-{
- return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
-}
-#endif
-
-int power_init_board(void)
-{
- struct pmic *p;
- unsigned int value;
-
- p = pfuze_common_init(I2C_PMIC);
- if (!p)
- return -ENODEV;
-
- if (is_mx6dqp()) {
- /* set SW2 staby volatage 0.975V*/
- pmic_reg_read(p, PFUZE100_SW2STBY, &value);
- value &= ~0x3f;
- value |= 0x17;
- pmic_reg_write(p, PFUZE100_SW2STBY, value);
- }
-
- return pfuze_mode_init(p, APS_PFM);
-}
-
-#ifdef CONFIG_CMD_BMODE
-static const struct boot_mode board_boot_modes[] = {
- /* 4 bit bus width */
- {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
- {NULL, 0},
-};
-#endif
-
-int board_late_init(void)
-{
-#ifdef CONFIG_CMD_BMODE
- add_board_boot_modes(board_boot_modes);
-#endif
-
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
- setenv("board_name", "SABREAUTO");
-
- if (is_mx6dqp())
- setenv("board_rev", "MX6QP");
- else if (is_mx6dq())
- setenv("board_rev", "MX6Q");
- else if (is_mx6sdl())
- setenv("board_rev", "MX6DL");
-#endif
-
- return 0;
-}
-
-int checkboard(void)
-{
- int rev = mx6sabre_rev();
- char *revname;
-
- switch (rev) {
- case BOARD_REV_B:
- revname = "B";
- break;
- case BOARD_REV_A:
- default:
- revname = "A";
- break;
- }
-
- printf("Board: MX6Q-Sabreauto rev%s\n", revname);
-
- return 0;
-}
-
-#ifdef CONFIG_USB_EHCI_MX6
-#define USB_HOST1_PWR PORTEXP_IO_NR(0x32, 7)
-#define USB_OTG_PWR PORTEXP_IO_NR(0x34, 1)
-
-iomux_v3_cfg_t const usb_otg_pads[] = {
- MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-int board_ehci_hcd_init(int port)
-{
- switch (port) {
- case 0:
- imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
- ARRAY_SIZE(usb_otg_pads));
-
- /*
- * Set daisy chain for otg_pin_id on 6q.
- * For 6dl, this bit is reserved.
- */
- imx_iomux_set_gpr_register(1, 13, 1, 0);
- break;
- case 1:
- break;
- default:
- printf("MXC USB port %d not yet supported\n", port);
- return -EINVAL;
- }
- return 0;
-}
-
-int board_ehci_power(int port, int on)
-{
- switch (port) {
- case 0:
- if (on)
- port_exp_direction_output(USB_OTG_PWR, 1);
- else
- port_exp_direction_output(USB_OTG_PWR, 0);
- break;
- case 1:
- if (on)
- port_exp_direction_output(USB_HOST1_PWR, 1);
- else
- port_exp_direction_output(USB_HOST1_PWR, 0);
- break;
- default:
- printf("MXC USB port %d not yet supported\n", port);
- return -EINVAL;
- }
-
- return 0;
-}
-#endif
--- /dev/null
+if TARGET_MX6SABREAUTO
+
+config SYS_BOARD
+ default "mx6sabreauto"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "mx6sabreauto"
+
+endif
--- /dev/null
+MX6SABREAUTO BOARD
+M: Fabio Estevam <fabio.estevam@nxp.com>
+M: Peng Fan <peng.fan@nxp.com>
+S: Maintained
+F: board/freescale/mx6sabreauto/
+F: include/configs/mx6sabreauto.h
+F: configs/mx6sabreauto_defconfig
--- /dev/null
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mx6sabreauto.o
--- /dev/null
+How to use and build U-Boot on mx6sabreauto
+-------------------------------------------
+
+mx6sabreauto_defconfig target supports mx6q/mx6dl/mx6qp sabreauto variants.
+
+In order to build it:
+
+$ make mx6sabreauto_defconfig
+
+$ make
+
+This will generate the SPL and u-boot.img binaries.
+
+- Flash the SPL binary into the SD card:
+
+$ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 && sync
+
+- Flash the u-boot.img binary into the SD card:
+
+$ sudo dd if=u-boot.img of=/dev/sdX bs=1K seek=69 && sync
+
+Booting via Falcon mode
+-----------------------
+
+Write in mx6sabreauto_defconfig the following define below:
+
+CONFIG_SPL_OS_BOOT=y
+
+In order to build it:
+
+$ make mx6sabreauto_defconfig
+
+$ make
+
+This will generate the SPL image called SPL and the u-boot.img.
+
+- Flash the SPL image into the SD card:
+
+$ sudo dd if=SPL of=/dev/sdb bs=1K seek=1 && sync
+
+- Flash the u-boot.img image into the SD card:
+
+$ sudo dd if=u-boot.img of=/dev/sdb bs=1K seek=69 && sync
+
+Create a FAT16 boot partition to store uImage and the dtb file, then copy the files there:
+
+$ sudo cp uImage /media/boot
+
+$ sudo cp imx6dl-sabreauto.dtb /media/boot
+
+Create a partition for root file system and extract it there:
+
+$ sudo tar xvf rootfs.tar.gz -C /media/root
+
+The SD card must have enough space for raw "args" and "kernel".
+To configure Falcon mode for the first time, on U-Boot do the following commands:
+
+- Load dtb file from boot partition:
+
+# load mmc 0:1 ${fdt_addr} imx6dl-sabreauto.dtb
+
+- Load kernel image from boot partition:
+
+# load mmc 0:1 ${loadaddr} uImage
+
+- Write kernel at 2MB offset:
+
+# mmc write ${loadaddr} 0x1000 0x4000
+
+- Setup kernel bootargs:
+
+# setenv bootargs "console=ttymxc3,115200 root=/dev/mmcblk0p1 rootfstype=ext4 rootwait quiet rw"
+
+- Prepare args:
+
+# spl export fdt ${loadaddr} - ${fdt_addr}
+
+- Write args 1MB data (0x800 sectors) to 1MB offset (0x800 sectors)
+
+# mmc write 18000000 0x800 0x800
+
+- Restart the board and then SPL binary will launch the kernel directly.
--- /dev/null
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <linux/errno.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/spi.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/sys_proto.h>
+#include <i2c.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/mach-imx/video.h>
+#include <asm/arch/crm_regs.h>
+#include <pca953x.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include "../common/pfuze.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
+ PAD_CTL_SRE_FAST)
+#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define I2C_PMIC 1
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const uart4_pads[] = {
+ IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const enet_pads[] = {
+ IOMUX_PADS(PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+};
+
+/* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
+static struct i2c_pads_info mx6q_i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6Q_PAD_EIM_EB2__I2C2_SCL | PC,
+ .gpio_mode = MX6Q_PAD_EIM_EB2__GPIO2_IO30 | PC,
+ .gp = IMX_GPIO_NR(2, 30)
+ },
+ .sda = {
+ .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
+ .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+ .gp = IMX_GPIO_NR(4, 13)
+ }
+};
+
+static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6DL_PAD_EIM_EB2__I2C2_SCL | PC,
+ .gpio_mode = MX6DL_PAD_EIM_EB2__GPIO2_IO30 | PC,
+ .gp = IMX_GPIO_NR(2, 30)
+ },
+ .sda = {
+ .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
+ .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+ .gp = IMX_GPIO_NR(4, 13)
+ }
+};
+
+#ifndef CONFIG_SYS_FLASH_CFI
+/*
+ * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
+ * Compass Sensor, Accelerometer, Res Touch
+ */
+static struct i2c_pads_info mx6q_i2c_pad_info2 = {
+ .scl = {
+ .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
+ .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
+ .gp = IMX_GPIO_NR(1, 3)
+ },
+ .sda = {
+ .i2c_mode = MX6Q_PAD_EIM_D18__I2C3_SDA | PC,
+ .gpio_mode = MX6Q_PAD_EIM_D18__GPIO3_IO18 | PC,
+ .gp = IMX_GPIO_NR(3, 18)
+ }
+};
+
+static struct i2c_pads_info mx6dl_i2c_pad_info2 = {
+ .scl = {
+ .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
+ .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
+ .gp = IMX_GPIO_NR(1, 3)
+ },
+ .sda = {
+ .i2c_mode = MX6DL_PAD_EIM_D18__I2C3_SDA | PC,
+ .gpio_mode = MX6DL_PAD_EIM_D18__GPIO3_IO18 | PC,
+ .gp = IMX_GPIO_NR(3, 18)
+ }
+};
+#endif
+
+static iomux_v3_cfg_t const i2c3_pads[] = {
+ IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const port_exp[] = {
+ IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+/*Define for building port exp gpio, pin starts from 0*/
+#define PORTEXP_IO_NR(chip, pin) \
+ ((chip << 5) + pin)
+
+/*Get the chip addr from a ioexp gpio*/
+#define PORTEXP_IO_TO_CHIP(gpio_nr) \
+ (gpio_nr >> 5)
+
+/*Get the pin number from a ioexp gpio*/
+#define PORTEXP_IO_TO_PIN(gpio_nr) \
+ (gpio_nr & 0x1f)
+
+static int port_exp_direction_output(unsigned gpio, int value)
+{
+ int ret;
+
+ i2c_set_bus_num(2);
+ ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
+ if (ret)
+ return ret;
+
+ ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
+ (1 << PORTEXP_IO_TO_PIN(gpio)),
+ (PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));
+
+ if (ret)
+ return ret;
+
+ ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
+ (1 << PORTEXP_IO_TO_PIN(gpio)),
+ (value << PORTEXP_IO_TO_PIN(gpio)));
+
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+#ifdef CONFIG_MTD_NOR_FLASH
+static iomux_v3_cfg_t const eimnor_pads[] = {
+ IOMUX_PADS(PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void eimnor_cs_setup(void)
+{
+ struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
+
+ writel(0x00020181, &weim_regs->cs0gcr1);
+ writel(0x00000001, &weim_regs->cs0gcr2);
+ writel(0x0a020000, &weim_regs->cs0rcr1);
+ writel(0x0000c000, &weim_regs->cs0rcr2);
+ writel(0x0804a240, &weim_regs->cs0wcr1);
+ writel(0x00000120, &weim_regs->wcr);
+
+ set_chipselect_size(CS0_128);
+}
+
+static void eim_clk_setup(void)
+{
+ struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ int cscmr1, ccgr6;
+
+
+ /* Turn off EIM clock */
+ ccgr6 = readl(&imx_ccm->CCGR6);
+ ccgr6 &= ~(0x3 << 10);
+ writel(ccgr6, &imx_ccm->CCGR6);
+
+ /*
+ * Configure clk_eim_slow_sel = 00 --> derive clock from AXI clk root
+ * and aclk_eim_slow_podf = 01 --> divide by 2
+ * so that we can have EIM at the maximum clock of 132MHz
+ */
+ cscmr1 = readl(&imx_ccm->cscmr1);
+ cscmr1 &= ~(MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK |
+ MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK);
+ cscmr1 |= (1 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET);
+ writel(cscmr1, &imx_ccm->cscmr1);
+
+ /* Turn on EIM clock */
+ ccgr6 |= (0x3 << 10);
+ writel(ccgr6, &imx_ccm->CCGR6);
+}
+
+static void setup_iomux_eimnor(void)
+{
+ SETUP_IOMUX_PADS(eimnor_pads);
+
+ gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
+
+ eimnor_cs_setup();
+}
+#endif
+
+static void setup_iomux_enet(void)
+{
+ SETUP_IOMUX_PADS(enet_pads);
+}
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void setup_iomux_uart(void)
+{
+ SETUP_IOMUX_PADS(uart4_pads);
+}
+
+#ifdef CONFIG_FSL_ESDHC
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+ {USDHC3_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ gpio_direction_input(IMX_GPIO_NR(6, 15));
+ return !gpio_get_value(IMX_GPIO_NR(6, 15));
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ SETUP_IOMUX_PADS(usdhc3_pads);
+
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+#endif
+
+#ifdef CONFIG_NAND_MXS
+static iomux_v3_cfg_t gpmi_pads[] = {
+ IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0)),
+ IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL1)),
+};
+
+static void setup_gpmi_nand(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ /* config gpmi nand iomux */
+ SETUP_IOMUX_PADS(gpmi_pads);
+
+ setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
+ MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)));
+
+ /* enable apbh clock gating */
+ setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+#endif
+
+static void setup_fec(void)
+{
+ if (is_mx6dqp()) {
+ /*
+ * select ENET MAC0 TX clock from PLL
+ */
+ imx_iomux_set_gpr_register(5, 9, 1, 1);
+ enable_fec_anatop_clock(0, ENET_125MHZ);
+ }
+
+ setup_iomux_enet();
+}
+
+int board_eth_init(bd_t *bis)
+{
+ setup_fec();
+
+ return cpu_eth_init(bis);
+}
+
+#define BOARD_REV_B 0x200
+#define BOARD_REV_A 0x100
+
+static int mx6sabre_rev(void)
+{
+ /*
+ * Get Board ID information from OCOTP_GP1[15:8]
+ * i.MX6Q ARD RevA: 0x01
+ * i.MX6Q ARD RevB: 0x02
+ */
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[4];
+ struct fuse_bank4_regs *fuse =
+ (struct fuse_bank4_regs *)bank->fuse_regs;
+ int reg = readl(&fuse->gp1);
+ int ret;
+
+ switch (reg >> 8 & 0x0F) {
+ case 0x02:
+ ret = BOARD_REV_B;
+ break;
+ case 0x01:
+ default:
+ ret = BOARD_REV_A;
+ break;
+ }
+
+ return ret;
+}
+
+u32 get_board_rev(void)
+{
+ int rev = mx6sabre_rev();
+
+ return (get_cpu_rev() & ~(0xF << 8)) | rev;
+}
+
+static int ar8031_phy_fixup(struct phy_device *phydev)
+{
+ unsigned short val;
+
+ /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+ val &= 0xffe3;
+ val |= 0x18;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+ /* introduce tx clock delay */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+ val |= 0x0100;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ ar8031_phy_fixup(phydev);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+#if defined(CONFIG_VIDEO_IPUV3)
+static void disable_lvds(struct display_info_t const *dev)
+{
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ clrbits_le32(&iomux->gpr[2],
+ IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
+ IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
+}
+
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+ disable_lvds(dev);
+ imx_enable_hdmi_phy();
+}
+
+struct display_info_t const displays[] = {{
+ .bus = -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB666,
+ .detect = NULL,
+ .enable = NULL,
+ .mode = {
+ .name = "Hannstar-XGA",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} }, {
+ .bus = -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = detect_hdmi,
+ .enable = do_enable_hdmi,
+ .mode = {
+ .name = "HDMI",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED,
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+iomux_v3_cfg_t const backlight_pads[] = {
+ IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+};
+
+static void setup_iomux_backlight(void)
+{
+ gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
+ SETUP_IOMUX_PADS(backlight_pads);
+}
+
+static void setup_display(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ int reg;
+
+ setup_iomux_backlight();
+ enable_ipu_clock();
+ imx_setup_hdmi();
+
+ /* Turn on LDB_DI0 and LDB_DI1 clocks */
+ reg = readl(&mxc_ccm->CCGR3);
+ reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
+ writel(reg, &mxc_ccm->CCGR3);
+
+ /* Set LDB_DI0 and LDB_DI1 clk select to 3b'011 */
+ reg = readl(&mxc_ccm->cs2cdr);
+ reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
+ MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+ reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
+ (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+ writel(reg, &mxc_ccm->cs2cdr);
+
+ reg = readl(&mxc_ccm->cscmr2);
+ reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
+ writel(reg, &mxc_ccm->cscmr2);
+
+ reg = readl(&mxc_ccm->chsccdr);
+ reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+ << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+ reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
+ MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
+ writel(reg, &mxc_ccm->chsccdr);
+
+ reg = IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
+ IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
+ IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
+ IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
+ IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
+ IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
+ IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
+ IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED;
+ writel(reg, &iomux->gpr[2]);
+
+ reg = readl(&iomux->gpr[3]);
+ reg &= ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
+ IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
+ reg |= (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+ IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
+ (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+ IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET);
+ writel(reg, &iomux->gpr[3]);
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+ return 1;
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
+#ifdef CONFIG_NAND_MXS
+ setup_gpmi_nand();
+#endif
+
+#ifdef CONFIG_MTD_NOR_FLASH
+ eim_clk_setup();
+#endif
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
+ if (is_mx6dq() || is_mx6dqp())
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
+ else
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
+ /* I2C 3 Steer */
+ gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
+ SETUP_IOMUX_PADS(i2c3_pads);
+#ifndef CONFIG_SYS_FLASH_CFI
+ if (is_mx6dq() || is_mx6dqp())
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
+ else
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
+#endif
+ gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
+ SETUP_IOMUX_PADS(port_exp);
+
+#ifdef CONFIG_VIDEO_IPUV3
+ setup_display();
+#endif
+
+#ifdef CONFIG_MTD_NOR_FLASH
+ setup_iomux_eimnor();
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
+}
+#endif
+
+int power_init_board(void)
+{
+ struct pmic *p;
+ unsigned int value;
+
+ p = pfuze_common_init(I2C_PMIC);
+ if (!p)
+ return -ENODEV;
+
+ if (is_mx6dqp()) {
+ /* set SW2 staby volatage 0.975V*/
+ pmic_reg_read(p, PFUZE100_SW2STBY, &value);
+ value &= ~0x3f;
+ value |= 0x17;
+ pmic_reg_write(p, PFUZE100_SW2STBY, value);
+ }
+
+ return pfuze_mode_init(p, APS_PFM);
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+ {NULL, 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ setenv("board_name", "SABREAUTO");
+
+ if (is_mx6dqp())
+ setenv("board_rev", "MX6QP");
+ else if (is_mx6dq())
+ setenv("board_rev", "MX6Q");
+ else if (is_mx6sdl())
+ setenv("board_rev", "MX6DL");
+#endif
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ int rev = mx6sabre_rev();
+ char *revname;
+
+ switch (rev) {
+ case BOARD_REV_B:
+ revname = "B";
+ break;
+ case BOARD_REV_A:
+ default:
+ revname = "A";
+ break;
+ }
+
+ printf("Board: MX6Q-Sabreauto rev%s\n", revname);
+
+ return 0;
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_HOST1_PWR PORTEXP_IO_NR(0x32, 7)
+#define USB_OTG_PWR PORTEXP_IO_NR(0x34, 1)
+
+iomux_v3_cfg_t const usb_otg_pads[] = {
+ IOMUX_PADS(PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+int board_ehci_hcd_init(int port)
+{
+ switch (port) {
+ case 0:
+ SETUP_IOMUX_PADS(usb_otg_pads);
+
+ /*
+ * Set daisy chain for otg_pin_id on 6q.
+ * For 6dl, this bit is reserved.
+ */
+ imx_iomux_set_gpr_register(1, 13, 1, 0);
+ break;
+ case 1:
+ break;
+ default:
+ printf("MXC USB port %d not yet supported\n", port);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+ switch (port) {
+ case 0:
+ if (on)
+ port_exp_direction_output(USB_OTG_PWR, 1);
+ else
+ port_exp_direction_output(USB_OTG_PWR, 0);
+ break;
+ case 1:
+ if (on)
+ port_exp_direction_output(USB_HOST1_PWR, 1);
+ else
+ port_exp_direction_output(USB_HOST1_PWR, 0);
+ break;
+ default:
+ printf("MXC USB port %d not yet supported\n", port);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#include <asm/arch/mx6-ddr.h>
+#include <spl.h>
+#include <libfdt.h>
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+ return 0;
+}
+#endif
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0x00C03F3F, &ccm->CCGR0);
+ writel(0x0030FC03, &ccm->CCGR1);
+ writel(0x0FFFC000, &ccm->CCGR2);
+ writel(0x3FF00000, &ccm->CCGR3);
+ writel(0x00FFF300, &ccm->CCGR4);
+ writel(0x0F0000C3, &ccm->CCGR5);
+ writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void gpr_init(void)
+{
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ /* enable AXI cache for VDOA/VPU/IPU */
+ writel(0xF00000CF, &iomux->gpr[4]);
+ if (is_mx6dqp()) {
+ /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
+ writel(0x007F007F, &iomux->gpr[6]);
+ writel(0x007F007F, &iomux->gpr[7]);
+ } else {
+ /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+ writel(0x007F007F, &iomux->gpr[6]);
+ writel(0x007F007F, &iomux->gpr[7]);
+ }
+}
+
+static int mx6q_dcd_table[] = {
+ 0x020e0798, 0x000C0000,
+ 0x020e0758, 0x00000000,
+ 0x020e0588, 0x00000030,
+ 0x020e0594, 0x00000030,
+ 0x020e056c, 0x00000030,
+ 0x020e0578, 0x00000030,
+ 0x020e074c, 0x00000030,
+ 0x020e057c, 0x00000030,
+ 0x020e058c, 0x00000000,
+ 0x020e059c, 0x00000030,
+ 0x020e05a0, 0x00000030,
+ 0x020e078c, 0x00000030,
+ 0x020e0750, 0x00020000,
+ 0x020e05a8, 0x00000028,
+ 0x020e05b0, 0x00000028,
+ 0x020e0524, 0x00000028,
+ 0x020e051c, 0x00000028,
+ 0x020e0518, 0x00000028,
+ 0x020e050c, 0x00000028,
+ 0x020e05b8, 0x00000028,
+ 0x020e05c0, 0x00000028,
+ 0x020e0774, 0x00020000,
+ 0x020e0784, 0x00000028,
+ 0x020e0788, 0x00000028,
+ 0x020e0794, 0x00000028,
+ 0x020e079c, 0x00000028,
+ 0x020e07a0, 0x00000028,
+ 0x020e07a4, 0x00000028,
+ 0x020e07a8, 0x00000028,
+ 0x020e0748, 0x00000028,
+ 0x020e05ac, 0x00000028,
+ 0x020e05b4, 0x00000028,
+ 0x020e0528, 0x00000028,
+ 0x020e0520, 0x00000028,
+ 0x020e0514, 0x00000028,
+ 0x020e0510, 0x00000028,
+ 0x020e05bc, 0x00000028,
+ 0x020e05c4, 0x00000028,
+ 0x021b0800, 0xa1390003,
+ 0x021b080c, 0x001F001F,
+ 0x021b0810, 0x001F001F,
+ 0x021b480c, 0x001F001F,
+ 0x021b4810, 0x001F001F,
+ 0x021b083c, 0x43260335,
+ 0x021b0840, 0x031A030B,
+ 0x021b483c, 0x4323033B,
+ 0x021b4840, 0x0323026F,
+ 0x021b0848, 0x483D4545,
+ 0x021b4848, 0x44433E48,
+ 0x021b0850, 0x41444840,
+ 0x021b4850, 0x4835483E,
+ 0x021b081c, 0x33333333,
+ 0x021b0820, 0x33333333,
+ 0x021b0824, 0x33333333,
+ 0x021b0828, 0x33333333,
+ 0x021b481c, 0x33333333,
+ 0x021b4820, 0x33333333,
+ 0x021b4824, 0x33333333,
+ 0x021b4828, 0x33333333,
+ 0x021b08b8, 0x00000800,
+ 0x021b48b8, 0x00000800,
+ 0x021b0004, 0x00020036,
+ 0x021b0008, 0x09444040,
+ 0x021b000c, 0x8A8F7955,
+ 0x021b0010, 0xFF328F64,
+ 0x021b0014, 0x01FF00DB,
+ 0x021b0018, 0x00001740,
+ 0x021b001c, 0x00008000,
+ 0x021b002c, 0x000026d2,
+ 0x021b0030, 0x008F1023,
+ 0x021b0040, 0x00000047,
+ 0x021b0000, 0x841A0000,
+ 0x021b001c, 0x04088032,
+ 0x021b001c, 0x00008033,
+ 0x021b001c, 0x00048031,
+ 0x021b001c, 0x09408030,
+ 0x021b001c, 0x04008040,
+ 0x021b0020, 0x00005800,
+ 0x021b0818, 0x00011117,
+ 0x021b4818, 0x00011117,
+ 0x021b0004, 0x00025576,
+ 0x021b0404, 0x00011006,
+ 0x021b001c, 0x00000000,
+ 0x020c4068, 0x00C03F3F,
+ 0x020c406c, 0x0030FC03,
+ 0x020c4070, 0x0FFFC000,
+ 0x020c4074, 0x3FF00000,
+ 0x020c4078, 0xFFFFF300,
+ 0x020c407c, 0x0F0000F3,
+ 0x020c4080, 0x00000FFF,
+ 0x020e0010, 0xF00000CF,
+ 0x020e0018, 0x007F007F,
+ 0x020e001c, 0x007F007F,
+};
+
+static int mx6qp_dcd_table[] = {
+ 0x020e0798, 0x000C0000,
+ 0x020e0758, 0x00000000,
+ 0x020e0588, 0x00000030,
+ 0x020e0594, 0x00000030,
+ 0x020e056c, 0x00000030,
+ 0x020e0578, 0x00000030,
+ 0x020e074c, 0x00000030,
+ 0x020e057c, 0x00000030,
+ 0x020e058c, 0x00000000,
+ 0x020e059c, 0x00000030,
+ 0x020e05a0, 0x00000030,
+ 0x020e078c, 0x00000030,
+ 0x020e0750, 0x00020000,
+ 0x020e05a8, 0x00000030,
+ 0x020e05b0, 0x00000030,
+ 0x020e0524, 0x00000030,
+ 0x020e051c, 0x00000030,
+ 0x020e0518, 0x00000030,
+ 0x020e050c, 0x00000030,
+ 0x020e05b8, 0x00000030,
+ 0x020e05c0, 0x00000030,
+ 0x020e0774, 0x00020000,
+ 0x020e0784, 0x00000030,
+ 0x020e0788, 0x00000030,
+ 0x020e0794, 0x00000030,
+ 0x020e079c, 0x00000030,
+ 0x020e07a0, 0x00000030,
+ 0x020e07a4, 0x00000030,
+ 0x020e07a8, 0x00000030,
+ 0x020e0748, 0x00000030,
+ 0x020e05ac, 0x00000030,
+ 0x020e05b4, 0x00000030,
+ 0x020e0528, 0x00000030,
+ 0x020e0520, 0x00000030,
+ 0x020e0514, 0x00000030,
+ 0x020e0510, 0x00000030,
+ 0x020e05bc, 0x00000030,
+ 0x020e05c4, 0x00000030,
+ 0x021b0800, 0xa1390003,
+ 0x021b080c, 0x001b001e,
+ 0x021b0810, 0x002e0029,
+ 0x021b480c, 0x001b002a,
+ 0x021b4810, 0x0019002c,
+ 0x021b083c, 0x43240334,
+ 0x021b0840, 0x0324031a,
+ 0x021b483c, 0x43340344,
+ 0x021b4840, 0x03280276,
+ 0x021b0848, 0x44383A3E,
+ 0x021b4848, 0x3C3C3846,
+ 0x021b0850, 0x2e303230,
+ 0x021b4850, 0x38283E34,
+ 0x021b081c, 0x33333333,
+ 0x021b0820, 0x33333333,
+ 0x021b0824, 0x33333333,
+ 0x021b0828, 0x33333333,
+ 0x021b481c, 0x33333333,
+ 0x021b4820, 0x33333333,
+ 0x021b4824, 0x33333333,
+ 0x021b4828, 0x33333333,
+ 0x021b08c0, 0x24912492,
+ 0x021b48c0, 0x24912492,
+ 0x021b08b8, 0x00000800,
+ 0x021b48b8, 0x00000800,
+ 0x021b0004, 0x00020036,
+ 0x021b0008, 0x09444040,
+ 0x021b000c, 0x898E7955,
+ 0x021b0010, 0xFF328F64,
+ 0x021b0014, 0x01FF00DB,
+ 0x021b0018, 0x00001740,
+ 0x021b001c, 0x00008000,
+ 0x021b002c, 0x000026d2,
+ 0x021b0030, 0x008E1023,
+ 0x021b0040, 0x00000047,
+ 0x021b0400, 0x14420000,
+ 0x021b0000, 0x841A0000,
+ 0x00bb0008, 0x00000004,
+ 0x00bb000c, 0x2891E41A,
+ 0x00bb0038, 0x00000564,
+ 0x00bb0014, 0x00000040,
+ 0x00bb0028, 0x00000020,
+ 0x00bb002c, 0x00000020,
+ 0x021b001c, 0x04088032,
+ 0x021b001c, 0x00008033,
+ 0x021b001c, 0x00048031,
+ 0x021b001c, 0x09408030,
+ 0x021b001c, 0x04008040,
+ 0x021b0020, 0x00005800,
+ 0x021b0818, 0x00011117,
+ 0x021b4818, 0x00011117,
+ 0x021b0004, 0x00025576,
+ 0x021b0404, 0x00011006,
+ 0x021b001c, 0x00000000,
+ 0x020c4068, 0x00C03F3F,
+ 0x020c406c, 0x0030FC03,
+ 0x020c4070, 0x0FFFC000,
+ 0x020c4074, 0x3FF00000,
+ 0x020c4078, 0xFFFFF300,
+ 0x020c407c, 0x0F0000F3,
+ 0x020c4080, 0x00000FFF,
+ 0x020e0010, 0xF00000CF,
+ 0x020e0018, 0x77177717,
+ 0x020e001c, 0x77177717,
+};
+
+static int mx6dl_dcd_table[] = {
+ 0x020e0774, 0x000C0000,
+ 0x020e0754, 0x00000000,
+ 0x020e04ac, 0x00000030,
+ 0x020e04b0, 0x00000030,
+ 0x020e0464, 0x00000030,
+ 0x020e0490, 0x00000030,
+ 0x020e074c, 0x00000030,
+ 0x020e0494, 0x00000030,
+ 0x020e04a0, 0x00000000,
+ 0x020e04b4, 0x00000030,
+ 0x020e04b8, 0x00000030,
+ 0x020e076c, 0x00000030,
+ 0x020e0750, 0x00020000,
+ 0x020e04bc, 0x00000028,
+ 0x020e04c0, 0x00000028,
+ 0x020e04c4, 0x00000028,
+ 0x020e04c8, 0x00000028,
+ 0x020e04cc, 0x00000028,
+ 0x020e04d0, 0x00000028,
+ 0x020e04d4, 0x00000028,
+ 0x020e04d8, 0x00000028,
+ 0x020e0760, 0x00020000,
+ 0x020e0764, 0x00000028,
+ 0x020e0770, 0x00000028,
+ 0x020e0778, 0x00000028,
+ 0x020e077c, 0x00000028,
+ 0x020e0780, 0x00000028,
+ 0x020e0784, 0x00000028,
+ 0x020e078c, 0x00000028,
+ 0x020e0748, 0x00000028,
+ 0x020e0470, 0x00000028,
+ 0x020e0474, 0x00000028,
+ 0x020e0478, 0x00000028,
+ 0x020e047c, 0x00000028,
+ 0x020e0480, 0x00000028,
+ 0x020e0484, 0x00000028,
+ 0x020e0488, 0x00000028,
+ 0x020e048c, 0x00000028,
+ 0x021b0800, 0xa1390003,
+ 0x021b080c, 0x001F001F,
+ 0x021b0810, 0x001F001F,
+ 0x021b480c, 0x001F001F,
+ 0x021b4810, 0x001F001F,
+ 0x021b083c, 0x42190217,
+ 0x021b0840, 0x017B017B,
+ 0x021b483c, 0x4176017B,
+ 0x021b4840, 0x015F016C,
+ 0x021b0848, 0x4C4C4D4C,
+ 0x021b4848, 0x4A4D4C48,
+ 0x021b0850, 0x3F3F3F40,
+ 0x021b4850, 0x3538382E,
+ 0x021b081c, 0x33333333,
+ 0x021b0820, 0x33333333,
+ 0x021b0824, 0x33333333,
+ 0x021b0828, 0x33333333,
+ 0x021b481c, 0x33333333,
+ 0x021b4820, 0x33333333,
+ 0x021b4824, 0x33333333,
+ 0x021b4828, 0x33333333,
+ 0x021b08b8, 0x00000800,
+ 0x021b48b8, 0x00000800,
+ 0x021b0004, 0x00020025,
+ 0x021b0008, 0x00333030,
+ 0x021b000c, 0x676B5313,
+ 0x021b0010, 0xB66E8B63,
+ 0x021b0014, 0x01FF00DB,
+ 0x021b0018, 0x00001740,
+ 0x021b001c, 0x00008000,
+ 0x021b002c, 0x000026d2,
+ 0x021b0030, 0x006B1023,
+ 0x021b0040, 0x00000047,
+ 0x021b0000, 0x841A0000,
+ 0x021b001c, 0x04008032,
+ 0x021b001c, 0x00008033,
+ 0x021b001c, 0x00048031,
+ 0x021b001c, 0x05208030,
+ 0x021b001c, 0x04008040,
+ 0x021b0020, 0x00005800,
+ 0x021b0818, 0x00011117,
+ 0x021b4818, 0x00011117,
+ 0x021b0004, 0x00025565,
+ 0x021b0404, 0x00011006,
+ 0x021b001c, 0x00000000,
+ 0x020c4068, 0x00C03F3F,
+ 0x020c406c, 0x0030FC03,
+ 0x020c4070, 0x0FFFC000,
+ 0x020c4074, 0x3FF00000,
+ 0x020c4078, 0xFFFFF300,
+ 0x020c407c, 0x0F0000C3,
+ 0x020c4080, 0x00000FFF,
+ 0x020e0010, 0xF00000CF,
+ 0x020e0018, 0x007F007F,
+ 0x020e001c, 0x007F007F,
+};
+
+static void ddr_init(int *table, int size)
+{
+ int i;
+
+ for (i = 0; i < size / 2 ; i++)
+ writel(table[2 * i + 1], table[2 * i]);
+}
+
+static void spl_dram_init(void)
+{
+ if (is_mx6dq())
+ ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
+ else if (is_mx6dqp())
+ ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
+ else if (is_mx6sdl())
+ ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
+}
+
+void board_init_f(ulong dummy)
+{
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ ccgr_init();
+ gpr_init();
+
+ /* iomux and setup of i2c */
+ board_early_init_f();
+
+ /* setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* load/boot image from boot device */
+ board_init_r(NULL, 0);
+}
+#endif
#include <asm/arch/mx6-pins.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/spi.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/spi.h>
#include <asm/io.h>
#include <linux/sizes.h>
#include <common.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
#include <asm/io.h>
#include <common.h>
#include <linux/sizes.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
#include <asm/io.h>
#include <linux/sizes.h>
#include <common.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <linux/sizes.h>
#include <common.h>
#include <fsl_esdhc.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <asm/io.h>
#include <common.h>
#include <fsl_esdhc.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
#include <asm/io.h>
#include <common.h>
#include <fsl_esdhc.h>
#include <asm/arch/mx7-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
#include <linux/sizes.h>
#include <common.h>
#include <power/pfuze3000_pmic.h>
#include "../common/pfuze.h"
#include <i2c.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <asm/arch/crm_regs.h>
DECLARE_GLOBAL_DATA_PTR;
pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1);
+ /*
+ * Set the voltage of VLDO4 output to 2.8V which feeds
+ * the MIPI DSI and MIPI CSI inputs.
+ */
+ pmic_clrsetbits(dev, PFUZE3000_VLD4CTL, 0xF, 0xA);
+
return 0;
}
#endif
*
* The syntax is taken as close as possible with the kwbimage
*/
-#include <asm/imx-common/imximage.cfg>
+#include <asm/mach-imx/imximage.cfg>
/* image version */
IMAGE_VERSION 2
*
* The syntax is taken as close as possible with the kwbimage
*/
-#include <asm/imx-common/imximage.cfg>
+#include <asm/mach-imx/imximage.cfg>
/* image version */
IMAGE_VERSION 2
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <fsl_esdhc.h>
#include <hwconfig.h>
#include <power/pmic.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/sata.h>
-#include <asm/imx-common/spi.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/spi.h>
+#include <asm/mach-imx/video.h>
#include <asm/io.h>
#include <asm/setup.h>
#include <dm.h>
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <environment.h>
#include <i2c.h>
#include <spl.h>
MEM_4G, /* mem_size */
DDR_FREQ_533, /* frequency */
0, 0, /* cas_l cas_wl */
- HWS_TEMP_LOW} }, /* temperature */
+ HWS_TEMP_LOW, /* temperature */
+ HWS_TIM_DEFAULT} }, /* timing */
5, /* Num Of Bus Per Interface*/
BUS_MASK_32BIT /* Busses mask */
};
#include <asm/arch/mx6-pins.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
#include <asm/io.h>
#include <common.h>
#include <fsl_esdhc.h>
Intel Platform Controller Hub EG20T, other system components and
peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.
+config TARGET_EDISON
+ bool "Edison"
+ help
+ This is the Intel Edison Compute Module. It contains a dual core Intel
+ Atom Tangier CPU, 1 GB RAM integrated on package. There is also 4 GB
+ eMMC flash on board, Wi-Fi, Bluetooth 4 and USB controllers.
+
config TARGET_GALILEO
bool "Galileo"
help
source "board/intel/bayleybay/Kconfig"
source "board/intel/cougarcanyon2/Kconfig"
source "board/intel/crownbay/Kconfig"
+source "board/intel/edison/Kconfig"
source "board/intel/galileo/Kconfig"
source "board/intel/minnowmax/Kconfig"
--- /dev/null
+if TARGET_EDISON
+
+config SYS_BOARD
+ default "edison"
+
+config SYS_VENDOR
+ default "intel"
+
+config SYS_SOC
+ default "tangier"
+
+config SYS_CONFIG_NAME
+ default "edison"
+
+config SYS_TEXT_BASE
+ default 0x01101000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select X86_LOAD_FROM_32_BIT
+ select INTEL_MID
+ select INTEL_TANGIER
+ select BOARD_LATE_INIT
+ select MD5
+
+endif
--- /dev/null
+Intel Edison Board
+M: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+S: Maintained
+F: board/intel/edison
+F: include/configs/edison.h
+F: configs/edison_defconfig
--- /dev/null
+#
+# Copyright (c) 2017 Intel Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += start.o edison.o
--- /dev/null
+#
+# Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
+# Copyright (c) 2017 Intel Corporation
+#
+# SPDX-License-Identifier: GPL-2.0 BSD-3-Clause
+#
+
+# Add 4096 bytes of zeroes to u-boot.bin
+quiet_cmd_mkalign_eds = EDSALGN $@
+cmd_mkalign_eds = \
+ dd if=$^ of=$@ bs=4k seek=1 2>/dev/null && \
+ mv $@ $^
+
+ALL-y += u-boot-align.bin
+u-boot-align.bin: u-boot.bin
+ $(call if_changed,mkalign_eds)
+
+HOSTCFLAGS_autoconf.mk.dep = -Wno-variadic-macros
--- /dev/null
+/*
+ * Copyright (c) 2017 Intel Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <dwc3-uboot.h>
+#include <mmc.h>
+#include <u-boot/md5.h>
+#include <usb.h>
+#include <watchdog.h>
+
+#include <linux/usb/gadget.h>
+
+#include <asm/cache.h>
+#include <asm/scu.h>
+#include <asm/u-boot-x86.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct dwc3_device dwc3_device_data = {
+ .maximum_speed = USB_SPEED_HIGH,
+ .base = CONFIG_SYS_USB_OTG_BASE,
+ .dr_mode = USB_DR_MODE_PERIPHERAL,
+ .index = 0,
+};
+
+int usb_gadget_handle_interrupts(int controller_index)
+{
+ dwc3_uboot_handle_interrupt(controller_index);
+ WATCHDOG_RESET();
+ return 0;
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ if (index == 0 && init == USB_INIT_DEVICE)
+ return dwc3_uboot_init(&dwc3_device_data);
+ return -EINVAL;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ if (index == 0 && init == USB_INIT_DEVICE) {
+ dwc3_uboot_exit(index);
+ return 0;
+ }
+ return -EINVAL;
+}
+
+static void assign_serial(void)
+{
+ struct mmc *mmc = find_mmc_device(0);
+ unsigned char ssn[16];
+ char usb0addr[18];
+ char serial[33];
+ int i;
+
+ if (!mmc)
+ return;
+
+ md5((unsigned char *)mmc->cid, sizeof(mmc->cid), ssn);
+
+ snprintf(usb0addr, sizeof(usb0addr), "02:00:86:%02x:%02x:%02x",
+ ssn[13], ssn[14], ssn[15]);
+ setenv("usb0addr", usb0addr);
+
+ for (i = 0; i < 16; i++)
+ snprintf(&serial[2 * i], 3, "%02x", ssn[i]);
+ setenv("serial#", serial);
+
+#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE)
+ saveenv();
+#endif
+}
+
+static void assign_hardware_id(void)
+{
+ struct ipc_ifwi_version v;
+ char hardware_id[4];
+ int ret;
+
+ ret = scu_ipc_command(IPCMSG_GET_FW_REVISION, 1, NULL, 0, (u32 *)&v, 4);
+ if (ret < 0)
+ printf("Can't retrieve hardware revision\n");
+
+ snprintf(hardware_id, sizeof(hardware_id), "%02X", v.hardware_id);
+ setenv("hardware_id", hardware_id);
+
+#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE)
+ saveenv();
+#endif
+}
+
+int board_late_init(void)
+{
+ if (!getenv("serial#"))
+ assign_serial();
+
+ if (!getenv("hardware_id"))
+ assign_hardware_id();
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* board early intialization */
+.globl early_board_init
+early_board_init:
+ /* No 32-bit board specific initialisation */
+ jmp early_board_init_ret
/* take care of the possible MAC address offset and the IVM content offset */
static int process_mac(unsigned char *valbuf, unsigned char *buf,
- int offset)
+ int offset, bool unique)
{
unsigned char mac[6];
unsigned long val = (buf[4] << 16) + (buf[5] << 8) + buf[6];
*/
memcpy(mac, buf+1, 6);
+ /* MAC adress can be set to locally administred, this is only allowed
+ * for interfaces which have now connection to the outside. For these
+ * addresses we need to set the second bit in the first byte.
+ */
+ if (!unique)
+ mac[0] |= 0x2;
+
if (offset) {
val += offset;
mac[3] = (val >> 16) & 0xff;
return 0;
page2 = &buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN*2];
+#ifndef CONFIG_KMTEGR1
/* if an offset is defined, add it */
- process_mac(valbuf, page2, CONFIG_PIGGY_MAC_ADRESS_OFFSET);
- if (getenv("ethaddr") == NULL)
- setenv((char *)"ethaddr", (char *)valbuf);
+ process_mac(valbuf, page2, CONFIG_PIGGY_MAC_ADRESS_OFFSET, true);
+ setenv((char *)"ethaddr", (char *)valbuf);
#ifdef CONFIG_KMVECT1
/* KMVECT1 has two ethernet interfaces */
- if (getenv("eth1addr") == NULL) {
- process_mac(valbuf, page2, 1);
- setenv((char *)"eth1addr", (char *)valbuf);
- }
+ process_mac(valbuf, page2, 1, true);
+ setenv((char *)"eth1addr", (char *)valbuf);
+#endif
+#else
+/* KMTEGR1 has a special setup. eth0 has no connection to the outside and
+ * gets an locally administred MAC address, eth1 is the debug interface and
+ * gets the official MAC address from the IVM
+ */
+ process_mac(valbuf, page2, CONFIG_PIGGY_MAC_ADRESS_OFFSET, false);
+ setenv((char *)"ethaddr", (char *)valbuf);
+ process_mac(valbuf, page2, CONFIG_PIGGY_MAC_ADRESS_OFFSET, true);
+ setenv((char *)"eth1addr", (char *)valbuf);
#endif
return 0;
#include <asm/arch/iomux.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/sata.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/video.h>
#include <fsl_esdhc.h>
#include <i2c.h>
#include <input.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <asm/arch/crm_regs.h>
#include <i2c.h>
#include <mmc.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/video.h>
#include <i2c.h>
#include <input.h>
#include <ipu_pixfmt.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/spi.h>
-#include <asm/imx-common/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/spi.h>
+#include <asm/mach-imx/boot_mode.h>
#include <asm/io.h>
#include <fsl_esdhc.h>
#include <mmc.h>
#include <asm/arch/mx6-pins.h>
#include <errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
DECLARE_GLOBAL_DATA_PTR;
* The syntax is taken as close as possible with the kwbimage
*/
-#include <asm/imx-common/imximage.cfg>
+#include <asm/mach-imx/imximage.cfg>
/* image version */
IMAGE_VERSION 2
*/
#include <common.h>
+#include <dm.h>
#include <power/as3722.h>
+#include <power/pmic.h>
#include <asm/arch/gpio.h>
#include <asm/arch/pinmux.h>
}
#ifdef CONFIG_PCI_TEGRA
-int tegra_pcie_board_init(void)
+/* TODO: Convert to driver model */
+static int as3722_sd_enable(struct udevice *pmic, unsigned int sd)
{
- struct udevice *pmic;
int err;
- err = as3722_init(&pmic);
+ if (sd > 6)
+ return -EINVAL;
+
+ err = pmic_clrsetbits(pmic, AS3722_SD_CONTROL, 0, 1 << sd);
if (err) {
- error("failed to initialize AS3722 PMIC: %d\n", err);
+ error("failed to update SD control register: %d", err);
return err;
}
- err = as3722_sd_enable(pmic, 4);
- if (err < 0) {
- error("failed to enable SD4: %d\n", err);
- return err;
+ return 0;
+}
+
+int tegra_pcie_board_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_PMIC,
+ DM_GET_DRIVER(pmic_as3722), &dev);
+ if (ret) {
+ debug("%s: Failed to find PMIC\n", __func__);
+ return ret;
}
- err = as3722_sd_set_voltage(pmic, 4, 0x24);
- if (err < 0) {
- error("failed to set SD4 voltage: %d\n", err);
- return err;
+ ret = as3722_sd_enable(dev, 4);
+ if (ret < 0) {
+ error("failed to enable SD4: %d\n", ret);
+ return ret;
+ }
+
+ ret = as3722_sd_set_voltage(dev, 4, 0x24);
+ if (ret < 0) {
+ error("failed to set SD4 voltage: %d\n", ret);
+ return ret;
}
return 0;
*/
#include <common.h>
+#include <dm.h>
#include <errno.h>
#include <asm/gpio.h>
#include <asm/io.h>
int tegra_lcd_pmic_init(int board_id)
{
- struct udevice *pmic;
+ struct udevice *dev;
int ret;
- ret = as3722_get(&pmic);
- if (ret)
- return -ENOENT;
+ ret = uclass_get_device_by_driver(UCLASS_PMIC,
+ DM_GET_DRIVER(pmic_as3722), &dev);
+ if (ret) {
+ debug("%s: Failed to find PMIC\n", __func__);
+ return ret;
+ }
if (board_id == 0)
- as3722_write(pmic, 0x00, 0x3c);
+ pmic_reg_write(dev, 0x00, 0x3c);
else
- as3722_write(pmic, 0x00, 0x50);
- as3722_write(pmic, 0x12, 0x10);
- as3722_write(pmic, 0x0c, 0x07);
- as3722_write(pmic, 0x20, 0x10);
+ pmic_reg_write(dev, 0x00, 0x50);
+ pmic_reg_write(dev, 0x12, 0x10);
+ pmic_reg_write(dev, 0x0c, 0x07);
+ pmic_reg_write(dev, 0x20, 0x10);
return 0;
}
*
* The syntax is taken as close as possible with the kwbimage
*/
-#include <asm/imx-common/imximage.cfg>
+#include <asm/mach-imx/imximage.cfg>
/* image version */
IMAGE_VERSION 2
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/spi.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/spi.h>
#include <linux/errno.h>
#include <asm/gpio.h>
#include <mmc.h>
nand_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += nand_info[i]->size;
+ nand_size += get_nand_dev_by_index(i)->size;
flash_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
nand_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += nand_info[i]->size;
+ nand_size += get_nand_dev_by_index(i)->size;
flash_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <linux/sizes.h>
#include <common.h>
#include <fsl_esdhc.h>
#include <asm/arch/mx6-pins.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <micrel.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <i2c.h>
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
#include <asm/arch/mx6-pins.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
#include <malloc.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <micrel.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <i2c.h>
#include "../common/mx6.h"
MEM_4G, /* mem_size */
DDR_FREQ_800, /* frequency */
0, 0, /* cas_l cas_wl */
- HWS_TEMP_LOW} }, /* temperature */
+ HWS_TEMP_LOW, /* temperature */
+ HWS_TIM_DEFAULT} }, /* timing */
5, /* Num Of Bus Per Interface*/
BUS_MASK_32BIT /* Busses mask */
};
# Copyright (C) 2015 Stefan Roese <sr@denx.de>
#
-# Armada XP uses version 1 image format
+# Armada 38x use version 1 image format
VERSION 1
# Boot Media configurations
#include <asm/arch/mxc_hdmi.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <malloc.h>
ret = setup_display();
#endif
+#ifdef CONFIG_CMD_SATA
+ setup_sata();
+#endif
+
#ifdef CONFIG_USB_EHCI_MX6
setup_usb();
#endif
#include <asm/armv7m.h>
#include <asm/arch/stm32.h>
#include <asm/arch/gpio.h>
-#include <asm/arch/fmc.h>
-#include <dm/platform_data/serial_stm32x7.h>
#include <asm/arch/stm32_periph.h>
#include <asm/arch/stm32_defs.h>
#include <asm/arch/syscfg.h>
#include <asm/arch/mx6-pins.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/sata.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <asm/io.h>
#include <common.h>
#include <miiphy.h>
#include <asm/arch/mx7-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <asm/io.h>
#include <common.h>
#include <fsl_esdhc.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
-#include <asm/imx-common/mx5_video.h>
+#include <asm/mach-imx/mx5_video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <mc13892.h>
#include <ram.h>
#include <dm/pinctrl.h>
#include <dm/uclass-internal.h>
-#include <misc.h>
#include <asm/setup.h>
#include <asm/arch/periph.h>
#include <power/regulator.h>
#include <u-boot/sha256.h>
-#define RK3399_CPUID_OFF 0x7
-#define RK3399_CPUID_LEN 0x10
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define RK3399_CPUID_OFF 0x7
-#define RK3399_CPUID_LEN 0x10
-
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
static void setup_serial(void)
{
#if CONFIG_IS_ENABLED(ROCKCHIP_EFUSE)
+ const u32 cpuid_offset = 0x7;
+ const u32 cpuid_length = 0x10;
+
struct udevice *dev;
int ret, i;
- u8 cpuid[RK3399_CPUID_LEN];
- u8 low[RK3399_CPUID_LEN/2], high[RK3399_CPUID_LEN/2];
- char cpuid_str[RK3399_CPUID_LEN * 2 + 1];
+ u8 cpuid[cpuid_length];
+ u8 low[cpuid_length/2], high[cpuid_length/2];
+ char cpuid_str[cpuid_length * 2 + 1];
u64 serialno;
char serialno_str[16];
}
/* read the cpu_id range from the efuses */
- ret = misc_read(dev, RK3399_CPUID_OFF, &cpuid, sizeof(cpuid));
+ ret = misc_read(dev, cpuid_offset, &cpuid, sizeof(cpuid));
if (ret) {
debug("%s: reading cpuid from the efuses failed\n",
__func__);
}
#endif
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+ return 0;
+}
+#endif
+
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
{
secure_boot_verify_image(p_image, p_size);
}
+
+void board_tee_image_process(ulong tee_image, size_t tee_size)
+{
+ secure_tee_install((u32)tee_image);
+}
+
+U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
#endif
#define board_is_x15() board_ti_is("BBRDX15_")
#define board_is_x15_revb1() (board_ti_is("BBRDX15_") && \
- (strncmp("B.10", board_ti_get_rev(), 3) <= 0))
+ !strncmp("B.10", board_ti_get_rev(), 3))
+#define board_is_x15_revc() (board_ti_is("BBRDX15_") && \
+ !strncmp("C.00", board_ti_get_rev(), 3))
#define board_is_am572x_evm() board_ti_is("AM572PM_")
#define board_is_am572x_evm_reva3() \
(board_ti_is("AM572PM_") && \
- (strncmp("A.30", board_ti_get_rev(), 3) <= 0))
+ !strncmp("A.30", board_ti_get_rev(), 3))
#define board_is_am572x_idk() board_ti_is("AM572IDK")
#define board_is_am571x_idk() board_ti_is("AM571IDK")
if (board_is_x15()) {
if (board_is_x15_revb1())
name = "beagle_x15_revb1";
+ else if (board_is_x15_revc())
+ name = "beagle_x15_revc";
else
name = "beagle_x15";
} else if (board_is_am572x_evm()) {
/* Now do the weird minor deltas that should be safe */
if (board_is_x15() || board_is_am572x_evm()) {
- if (board_is_x15_revb1() || board_is_am572x_evm_reva3()) {
+ if (board_is_x15_revb1() || board_is_am572x_evm_reva3() ||
+ board_is_x15_revc()) {
pconf = core_padconf_array_delta_x15_sr2_0;
pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
} else {
#ifdef CONFIG_PCI_TEGRA
int tegra_pcie_board_init(void)
{
+ /* TODO: Convert to driver model
struct udevice *pmic;
int err;
error("failed to set GPIO#2 high: %d\n", err);
return err;
}
+ */
/* Reset I210 Gigabit Ethernet Controller */
gpio_request(LAN_RESET_N, "LAN_RESET_N");
gpio_direction_output(TEGRA_GPIO(O, 6), 0);
/* Make sure LDO9 and LDO10 are initially enabled @ 0V */
+ /* TODO: Convert to driver model
err = as3722_ldo_enable(pmic, 9);
if (err < 0) {
error("failed to enable LDO9: %d\n", err);
error("failed to set LDO10 voltage: %d\n", err);
return err;
}
+ */
mdelay(100);
gpio_set_value(TEGRA_GPIO(O, 6), 1);
/* Enable LDO9 and LDO10 for +V3.3_ETH on patched prototypes */
+ /* TODO: Convert to driver model
err = as3722_ldo_set_voltage(pmic, 9, 0xff);
if (err < 0) {
error("failed to set LDO9 voltage: %d\n", err);
error("failed to set LDO10 voltage: %d\n", err);
return err;
}
+ */
mdelay(100);
gpio_set_value(LAN_RESET_N, 1);
#include <asm/bootm.h>
#include <asm/gpio.h>
#include <asm/io.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/sata.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/video.h>
#include <dm/platform_data/serial_mxc.h>
#include <dm/platdata.h>
#include <fsl_esdhc.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
#include "pf0100_otp.inc"
#include "pf0100.h"
#include <asm/arch/sys_proto.h>
#include <asm/bootm.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/sata.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/video.h>
#include <asm/io.h>
#include <dm/platform_data/serial_mxc.h>
#include <dm/platdata.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
#include "pf0100_otp.inc"
#include "pf0100.h"
#include <asm/arch/mx7-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
#include <common.h>
#include <dm.h>
{
printf("Model: Toradex Colibri T20 %dMB V%s\n",
(gd->ram_size == 0x10000000) ? 256 : 512,
- (nand_info[0]->erasesize >> 10 == 512) ?
+ (get_nand_dev_by_index(0)->erasesize >> 10 == 512) ?
((gd->ram_size == 0x10000000) ? "1.1B" : "1.1C") : "1.2A");
return 0;
*
* The syntax is taken as close as possible with the kwbimage
*/
-#include <asm/imx-common/imximage.cfg>
+#include <asm/mach-imx/imximage.cfg>
/* image version */
IMAGE_VERSION 2
size_t size = TDX_CFG_BLOCK_MAX_SIZE;
/* Read production parameter config block from NAND page */
- return nand_read_skip_bad(nand_info[0], CONFIG_TDX_CFG_BLOCK_OFFSET,
- &size, NULL, TDX_CFG_BLOCK_MAX_SIZE, config_block);
+ return nand_read_skip_bad(get_nand_dev_by_index(0),
+ CONFIG_TDX_CFG_BLOCK_OFFSET,
+ &size, NULL, TDX_CFG_BLOCK_MAX_SIZE,
+ config_block);
}
static int write_tdx_cfg_block_to_nand(unsigned char *config_block)
size_t size = TDX_CFG_BLOCK_MAX_SIZE;
/* Write production parameter config block to NAND page */
- return nand_write_skip_bad(nand_info[0], CONFIG_TDX_CFG_BLOCK_OFFSET,
+ return nand_write_skip_bad(get_nand_dev_by_index(0),
+ CONFIG_TDX_CFG_BLOCK_OFFSET,
&size, NULL, TDX_CFG_BLOCK_MAX_SIZE,
config_block, WITH_WR_VERIFY);
}
* empty (config block invalid...)
*/
printf("NAND erase block %d need to be erased before creating a Toradex config block\n",
- CONFIG_TDX_CFG_BLOCK_OFFSET / nand_info[0]->erasesize);
+ CONFIG_TDX_CFG_BLOCK_OFFSET /
+ get_nand_dev_by_index(0)->erasesize);
goto out;
#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NOR)
/*
#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/io.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/spi.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/spi.h>
#include <common.h>
#include <fsl_esdhc.h>
#include <libfdt.h>
#include <asm/arch/sys_proto.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <common.h>
#include <fsl_esdhc.h>
#include <asm/arch/sys_proto.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <common.h>
#include <fsl_esdhc.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <asm/arch/sys_proto.h>
#include <spl.h>
#include <linux/sizes.h>
#include <asm/arch/mx6-pins.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/sata.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/sata.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/mx6-pins.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/mx6-pins.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <asm/arch/crm_regs.h>
mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
mx6_dram_cfg(&mem_q, &mx6q_2g_mmdc_calib, &h5t04g63afr);
}
-
- udelay(100);
}
void board_init_f(ulong dummy)
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/video.h>
-#include <asm/imx-common/sata.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/video.h>
+#include <asm/mach-imx/sata.h>
#include <asm/io.h>
#include <linux/sizes.h>
#include <common.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <asm/io.h>
#include <linux/sizes.h>
#include <common.h>
}
static struct fsl_esdhc_cfg usdhc_cfg[1] = {
- {USDHC2_BASE_ADDR},
+ {USDHC2_BASE_ADDR, 0, 0, 0, 1},
};
int board_mmc_getcd(struct mmc *mmc)
#include <asm/arch/mx7-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <asm/io.h>
#include <common.h>
#include <fsl_esdhc.h>
filesystem information.
config CMD_MTDPARTS
- depends on ARCH_SUNXI
bool "MTD partition support"
help
MTD partition support
tristate "Enable UBI - Unsorted block images commands"
select CRC32
select MTD_UBI
+ select CMD_MTDPARTS
default y if NAND_SUNXI
help
UBI is a software layer above MTD layer which admits use of LVM-like
tristate "Enable UBIFS - Unsorted block images filesystem commands"
depends on CMD_UBI
select CRC32
- select RBTREE if ARCH_SUNXI
- select LZO if ARCH_SUNXI
- default y if NAND_SUNXI
+ select LZO
+ default y if CMD_UBI
help
UBIFS is a file system for flash devices which works on top of UBI.
#ifdef CONFIG_BOARD_TYPES
printf("Board Type = %ld\n", gd->board_type);
#endif
-#ifdef CONFIG_SYS_MALLOC_F
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
printf("Early malloc usage: %lx / %x\n", gd->malloc_ptr,
- CONFIG_SYS_MALLOC_F_LEN);
+ CONFIG_VAL(SYS_MALLOC_F_LEN));
#endif
if (gd->fdt_blob)
printf("fdt_blob = %p\n", gd->fdt_blob);
printf("\n");
for (nand_dev = 0; nand_dev < CONFIG_SYS_MAX_NAND_DEVICE; nand_dev++) {
- mtd = nand_info[nand_dev];
+ mtd = get_nand_dev_by_index(nand_dev);
if (!mtd->name || !mtd->size)
continue;
#endif
} else if (type == MTD_DEV_TYPE_NAND) {
#if defined(CONFIG_JFFS2_NAND) && defined(CONFIG_CMD_NAND)
- if (num < CONFIG_SYS_MAX_NAND_DEVICE) {
- *size = nand_info[num]->size;
+ struct mtd_info *mtd = get_nand_dev_by_index(num);
+ if (mtd) {
+ *size = mtd->size;
return 0;
}
#if defined(CONFIG_JFFS2_NAND) && defined(CONFIG_CMD_NAND)
struct mtd_info *mtd;
- mtd = nand_info[id->num];
+ mtd = get_nand_dev_by_index(id->num);
return mtd->erasesize;
#else
return CMD_RET_FAILURE;
}
/* Switch to the RPMB partition */
+#ifndef CONFIG_BLK
original_part = mmc->block_dev.hwpart;
+#else
+ original_part = mmc_get_blk_desc(mmc)->hwpart;
+#endif
if (blk_select_hwpart_devnum(IF_TYPE_MMC, curr_device, MMC_PART_RPMB) !=
0)
return CMD_RET_FAILURE;
{
int ret;
uint32_t block_size;
- struct mtd_info *nand;
- int dev = nand_curr_device;
+ struct mtd_info *mtd;
- if ((dev < 0) || (dev >= CONFIG_SYS_MAX_NAND_DEVICE) ||
- (!nand_info[dev]->name)) {
+ mtd = get_nand_dev_by_index(nand_curr_device);
+ if (!mtd) {
puts("\nno devices available\n");
return -ENOMEDIUM;
}
- nand = nand_info[dev];
- block_size = nand->erasesize;
+ block_size = mtd->erasesize;
/* Align U-Boot size to currently used blocksize */
image_size = ((image_size + (block_size - 1)) & (~(block_size - 1)));
/* Erase the U-BOOT image space */
printf("Erasing 0x%x - 0x%x:...", 0, (int)image_size);
- ret = nand_erase(nand, 0, image_size);
+ ret = nand_erase(mtd, 0, image_size);
if (ret) {
printf("Error!\n");
goto error;
/* Write the image to flash */
printf("Writing %d bytes from 0x%lx to offset 0 ... ",
(int)image_size, get_load_addr());
- ret = nand_write(nand, 0, &image_size, (void *)get_load_addr());
+ ret = nand_write(mtd, 0, &image_size, (void *)get_load_addr());
if (ret)
printf("Error!\n");
else
static int set_dev(int dev)
{
- if (dev < 0 || dev >= CONFIG_SYS_MAX_NAND_DEVICE || !nand_info[dev]) {
- puts("No such device\n");
- return -1;
- }
+ struct mtd_info *mtd = get_nand_dev_by_index(dev);
+
+ if (!mtd)
+ return -ENODEV;
if (nand_curr_device == dev)
return 0;
- printf("Device %d: %s", dev, nand_info[dev]->name);
+ printf("Device %d: %s", dev, mtd->name);
puts("... is now current device\n");
nand_curr_device = dev;
#ifdef CONFIG_SYS_NAND_SELECT_DEVICE
- board_nand_select_device(nand_info[dev]->priv, dev);
+ board_nand_select_device(mtd_to_nand(mtd), dev);
#endif
return 0;
{
int ret;
uint32_t oob_buf[ENV_OFFSET_SIZE/sizeof(uint32_t)];
- struct mtd_info *mtd = nand_info[0];
+ struct mtd_info *mtd = get_nand_dev_by_index(0);
char *cmd = argv[1];
if (CONFIG_SYS_MAX_NAND_DEVICE == 0 || !mtd) {
if (argc < 3)
goto usage;
+ mtd = get_nand_dev_by_index(idx);
/* We don't care about size, or maxsize. */
if (mtd_arg_off(argv[2], &idx, &addr, &maxsize, &maxsize,
- MTD_DEV_TYPE_NAND, nand_info[idx]->size)) {
+ MTD_DEV_TYPE_NAND, mtd->size)) {
puts("Offset or partition name expected\n");
return 1;
}
static void nand_print_and_set_info(int idx)
{
- struct mtd_info *mtd = nand_info[idx];
- struct nand_chip *chip = mtd_to_nand(mtd);
+ struct mtd_info *mtd;
+ struct nand_chip *chip;
+
+ mtd = get_nand_dev_by_index(idx);
+ if (!mtd)
+ return;
+ chip = mtd_to_nand(mtd);
printf("Device %d: ", idx);
if (chip->numchips > 1)
printf("%dx ", chip->numchips);
/* We grab the nand info object here fresh because this is usually
* called after arg_off_size() which can change the value of dev.
*/
- struct mtd_info *mtd = nand_info[dev];
+ struct mtd_info *mtd = get_nand_dev_by_index(dev);
loff_t maxoffset = offset + *size;
int badblocks = 0;
if (strcmp(cmd, "info") == 0) {
putc('\n');
- for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) {
- if (nand_info[i])
- nand_print_and_set_info(i);
- }
+ for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+ nand_print_and_set_info(i);
return 0;
}
* one before these commands can run, even if a partition specifier
* for another device is to be used.
*/
- if (dev < 0 || dev >= CONFIG_SYS_MAX_NAND_DEVICE ||
- !nand_info[dev]) {
+ mtd = get_nand_dev_by_index(dev);
+ if (!mtd) {
puts("\nno devices available\n");
return 1;
}
- mtd = nand_info[dev];
if (strcmp(cmd, "bad") == 0) {
printf("\nDevice %d bad blocks:\n", dev);
/* skip first two or three arguments, look for offset and size */
if (mtd_arg_off_size(argc - o, argv + o, &dev, &off, &size,
&maxsize, MTD_DEV_TYPE_NAND,
- nand_info[dev]->size) != 0)
+ mtd->size) != 0)
return 1;
if (set_dev(dev))
return 1;
- mtd = nand_info[dev];
+ mtd = get_nand_dev_by_index(dev);
memset(&opts, 0, sizeof(opts));
opts.offset = off;
if (mtd_arg_off(argv[3], &dev, &off, &size, &maxsize,
MTD_DEV_TYPE_NAND,
- nand_info[dev]->size))
+ mtd->size))
return 1;
if (set_dev(dev))
return 1;
- mtd = nand_info[dev];
+ mtd = get_nand_dev_by_index(dev);
if (argc > 4 && !str2long(argv[4], &pagecount)) {
printf("'%s' is not a number\n", argv[4]);
if (mtd_arg_off_size(argc - 3, argv + 3, &dev, &off,
&size, &maxsize,
MTD_DEV_TYPE_NAND,
- nand_info[dev]->size) != 0)
+ mtd->size) != 0)
return 1;
if (set_dev(dev))
rwsize = size;
}
- mtd = nand_info[dev];
+ mtd = get_nand_dev_by_index(dev);
if (!s || !strcmp(s, ".jffs2") ||
!strcmp(s, ".e") || !strcmp(s, ".i")) {
if (mtd_arg_off_size(argc - 2, argv + 2, &dev, &off, &size,
&maxsize, MTD_DEV_TYPE_NAND,
- nand_info[dev]->size) < 0)
+ mtd->size) < 0)
return 1;
if (set_dev(dev))
return 1;
- if (!nand_unlock(nand_info[dev], off, size, allexcept)) {
+ mtd = get_nand_dev_by_index(dev);
+
+ if (!nand_unlock(mtd, off, size, allexcept)) {
puts("NAND flash successfully unlocked\n");
} else {
puts("Error unlocking NAND flash, "
char *boot_device = NULL;
int idx;
ulong addr, offset = 0;
+ struct mtd_info *mtd;
#if defined(CONFIG_CMD_MTDPARTS)
struct mtd_device *dev;
struct part_info *part;
addr = simple_strtoul(argv[1], NULL, 16);
else
addr = CONFIG_SYS_LOAD_ADDR;
- return nand_load_image(cmdtp, nand_info[dev->id->num],
- part->offset, addr, argv[0]);
+
+ mtd = get_nand_dev_by_index(dev->id->num);
+ return nand_load_image(cmdtp, mtd, part->offset,
+ addr, argv[0]);
}
}
#endif
idx = simple_strtoul(boot_device, NULL, 16);
- if (idx < 0 || idx >= CONFIG_SYS_MAX_NAND_DEVICE || !nand_info[idx]) {
+ mtd = get_nand_dev_by_index(idx);
+ if (!mtd) {
printf("\n** Device %d not available\n", idx);
bootstage_error(BOOTSTAGE_ID_NAND_AVAILABLE);
return 1;
}
bootstage_mark(BOOTSTAGE_ID_NAND_AVAILABLE);
- return nand_load_image(cmdtp, nand_info[idx], offset, addr, argv[0]);
+ return nand_load_image(cmdtp, mtd, offset, addr, argv[0]);
}
U_BOOT_CMD(nboot, 4, 1, do_nandboot,
#include <common.h>
#include <command.h>
-#if defined(CONFIG_8xx)
-void mpc8xx_reginfo(void);
-#elif defined(CONFIG_MPC86xx)
-extern void mpc86xx_reginfo(void);
-#elif defined(CONFIG_MPC85xx)
-extern void mpc85xx_reginfo(void);
-#endif
+#include <asm/ppc.h>
static int do_reginfo(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
-#if defined(CONFIG_8xx)
- mpc8xx_reginfo();
-
-#elif defined(CONFIG_MPC86xx)
- mpc86xx_reginfo();
-
-#elif defined(CONFIG_MPC85xx)
- mpc85xx_reginfo();
-#endif
+ print_reginfo();
return 0;
}
/**************************************************/
-#if defined(CONFIG_CMD_REGINFO)
U_BOOT_CMD(
reginfo, 2, 1, do_reginfo,
"print register information",
""
);
-#endif
case 2:
if (strncmp(argv[1], "res", 3) == 0) {
printf("\nReset SCSI\n");
+#ifndef CONFIG_DM_SCSI
scsi_bus_reset(NULL);
+#endif
ret = scsi_scan(true);
if (ret)
return CMD_RET_FAILURE;
static void usb_display_desc(struct usb_device *dev)
{
+ uint packet_size = dev->descriptor.bMaxPacketSize0;
+
if (dev->descriptor.bDescriptorType == USB_DT_DEVICE) {
printf("%d: %s, USB Revision %x.%x\n", dev->devnum,
usb_get_class_desc(dev->config.if_desc[0].desc.bInterfaceClass),
usb_get_class_desc(
dev->config.if_desc[0].desc.bInterfaceClass));
}
+ if (dev->descriptor.bcdUSB >= cpu_to_le16(0x0300))
+ packet_size = 1 << packet_size;
printf(" - PacketSize: %d Configurations: %d\n",
- dev->descriptor.bMaxPacketSize0,
- dev->descriptor.bNumConfigurations);
+ packet_size, dev->descriptor.bNumConfigurations);
printf(" - Vendor: 0x%04x Product 0x%04x Version %d.%d\n",
dev->descriptor.idVendor, dev->descriptor.idProduct,
(dev->descriptor.bcdDevice>>8) & 0xff,
menu "Environment"
-if ARCH_SUNXI
+config ENV_IS_IN_DATAFLASH
+ bool "Environment in dataflash"
+ depends on !CHAIN_OF_TRUST
+ help
+ Define this if you have a DataFlash memory device which you
+ want to use for the environment.
+
+ - CONFIG_ENV_OFFSET:
+ - CONFIG_ENV_ADDR:
+ - CONFIG_ENV_SIZE:
+
+ These three #defines specify the offset and size of the
+ environment area within the total memory of your DataFlash placed
+ at the specified address.
+
+config ENV_IS_IN_EEPROM
+ bool "Environment in EEPROM"
+ depends on !CHAIN_OF_TRUST
+ help
+ Use this if you have an EEPROM or similar serial access
+ device and a driver for it.
+
+ - CONFIG_ENV_OFFSET:
+ - CONFIG_ENV_SIZE:
+
+ These two #defines specify the offset and size of the
+ environment area within the total memory of your EEPROM.
+
+ - CONFIG_SYS_I2C_EEPROM_ADDR:
+ If defined, specified the chip address of the EEPROM device.
+ The default address is zero.
+
+ - CONFIG_SYS_I2C_EEPROM_BUS:
+ If defined, specified the i2c bus of the EEPROM device.
+
+ - CONFIG_SYS_EEPROM_PAGE_WRITE_BITS:
+ If defined, the number of bits used to address bytes in a
+ single page in the EEPROM device. A 64 byte page, for example
+ would require six bits.
+
+ - CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS:
+ If defined, the number of milliseconds to delay between
+ page writes. The default is zero milliseconds.
+
+ - CONFIG_SYS_I2C_EEPROM_ADDR_LEN:
+ The length in bytes of the EEPROM memory array address. Note
+ that this is NOT the chip address length!
+
+ - CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW:
+ EEPROM chips that implement "address overflow" are ones
+ like Catalyst 24WC04/08/16 which has 9/10/11 bits of
+ address and the extra bits end up in the "chip address" bit
+ slots. This makes a 24WC08 (1Kbyte) chip look like four 256
+ byte chips.
+
+ Note that we consider the length of the address field to
+ still be one byte because the extra address bits are hidden
+ in the chip address.
+
+ - CONFIG_SYS_EEPROM_SIZE:
+ The size in bytes of the EEPROM device.
+
+ - CONFIG_ENV_EEPROM_IS_ON_I2C
+ define this, if you have I2C and SPI activated, and your
+ EEPROM, which holds the environment, is on the I2C bus.
+
+ - CONFIG_I2C_ENV_EEPROM_BUS
+ if you have an Environment on an EEPROM reached over
+ I2C muxes, you can define here, how to reach this
+ EEPROM. For example:
+
+ #define CONFIG_I2C_ENV_EEPROM_BUS 1
+
+ EEPROM which holds the environment, is reached over
+ a pca9547 i2c mux with address 0x70, channel 3.
+
+config ENV_IS_IN_FAT
+ bool "Environment is in a FAT filesystem"
+ depends on !CHAIN_OF_TRUST
+ help
+ Define this if you want to use the FAT file system for the environment.
+
+ - FAT_ENV_INTERFACE:
+
+ Define this to a string that is the name of the block device.
+
+ - FAT_ENV_DEVICE_AND_PART:
+
+ Define this to a string to specify the partition of the device. It can
+ be as following:
+
+ "D:P", "D:0", "D", "D:" or "D:auto" (D, P are integers. And P >= 1)
+ - "D:P": device D partition P. Error occurs if device D has no
+ partition table.
+ - "D:0": device D.
+ - "D" or "D:": device D partition 1 if device D has partition
+ table, or the whole device D if has no partition
+ table.
+ - "D:auto": first partition in device D with bootable flag set.
+ If none, first valid partition in device D. If no
+ partition table then means device D.
-choice
- prompt "Environment Device"
- default ENV_IS_IN_MMC if ARCH_SUNXI
+ - FAT_ENV_FILE:
+
+ It's a string of the FAT file name. This file use to store the
+ environment.
+
+ - CONFIG_FAT_WRITE:
+ This must be enabled. Otherwise it cannot save the environment file.
+
+config ENV_IS_IN_FLASH
+ bool "Environment in flash memory"
+ depends on !CHAIN_OF_TRUST
+ help
+ Define this if you have a flash device which you want to use for the
+ environment.
+
+ a) The environment occupies one whole flash sector, which is
+ "embedded" in the text segment with the U-Boot code. This
+ happens usually with "bottom boot sector" or "top boot
+ sector" type flash chips, which have several smaller
+ sectors at the start or the end. For instance, such a
+ layout can have sector sizes of 8, 2x4, 16, Nx32 kB. In
+ such a case you would place the environment in one of the
+ 4 kB sectors - with U-Boot code before and after it. With
+ "top boot sector" type flash chips, you would put the
+ environment in one of the last sectors, leaving a gap
+ between U-Boot and the environment.
+
+ CONFIG_ENV_OFFSET:
+
+ Offset of environment data (variable area) to the
+ beginning of flash memory; for instance, with bottom boot
+ type flash chips the second sector can be used: the offset
+ for this sector is given here.
+
+ CONFIG_ENV_OFFSET is used relative to CONFIG_SYS_FLASH_BASE.
+
+ CONFIG_ENV_ADDR:
+
+ This is just another way to specify the start address of
+ the flash sector containing the environment (instead of
+ CONFIG_ENV_OFFSET).
+
+ CONFIG_ENV_SECT_SIZE:
+
+ Size of the sector containing the environment.
+
+
+ b) Sometimes flash chips have few, equal sized, BIG sectors.
+ In such a case you don't want to spend a whole sector for
+ the environment.
+
+ CONFIG_ENV_SIZE:
+
+ If you use this in combination with CONFIG_ENV_IS_IN_FLASH
+ and CONFIG_ENV_SECT_SIZE, you can specify to use only a part
+ of this flash sector for the environment. This saves
+ memory for the RAM copy of the environment.
+
+ It may also save flash memory if you decide to use this
+ when your environment is "embedded" within U-Boot code,
+ since then the remainder of the flash sector could be used
+ for U-Boot code. It should be pointed out that this is
+ STRONGLY DISCOURAGED from a robustness point of view:
+ updating the environment in flash makes it always
+ necessary to erase the WHOLE sector. If something goes
+ wrong before the contents has been restored from a copy in
+ RAM, your target system will be dead.
+
+ CONFIG_ENV_ADDR_REDUND
+ CONFIG_ENV_SIZE_REDUND
+
+ These settings describe a second storage area used to hold
+ a redundant copy of the environment data, so that there is
+ a valid backup copy in case there is a power failure during
+ a "saveenv" operation.
+
+ BE CAREFUL! Any changes to the flash layout, and some changes to the
+ source code will make it necessary to adapt <board>/u-boot.lds*
+ accordingly!
config ENV_IS_IN_MMC
bool "Environment in an MMC device"
- depends on CMD_MMC
+ depends on !CHAIN_OF_TRUST
+ default y if ARCH_SUNXI
help
Define this if you have an MMC device which you want to use for the
environment.
+ CONFIG_SYS_MMC_ENV_DEV:
+
+ Specifies which MMC device the environment is stored in.
+
+ CONFIG_SYS_MMC_ENV_PART (optional):
+
+ Specifies which MMC partition the environment is stored in. If not
+ set, defaults to partition 0, the user area. Common values might be
+ 1 (first MMC boot partition), 2 (second MMC boot partition).
+
+ CONFIG_ENV_OFFSET:
+ CONFIG_ENV_SIZE:
+
+ These two #defines specify the offset and size of the environment
+ area within the specified MMC device.
+
+ If offset is positive (the usual case), it is treated as relative to
+ the start of the MMC partition. If offset is negative, it is treated
+ as relative to the end of the MMC partition. This can be useful if
+ your board may be fitted with different MMC devices, which have
+ different sizes for the MMC partitions, and you always want the
+ environment placed at the very end of the partition, to leave the
+ maximum possible space before it, to store other data.
+
+ These two values are in units of bytes, but must be aligned to an
+ MMC sector boundary.
+
+ CONFIG_ENV_OFFSET_REDUND (optional):
+
+ Specifies a second storage area, of CONFIG_ENV_SIZE size, used to
+ hold a redundant copy of the environment data. This provides a
+ valid backup copy in case the other copy is corrupted, e.g. due
+ to a power failure during a "saveenv" operation.
+
+ This value may also be positive or negative; this is handled in the
+ same way as CONFIG_ENV_OFFSET.
+
+ This value is also in units of bytes, but must also be aligned to
+ an MMC sector boundary.
+
+ CONFIG_ENV_SIZE_REDUND (optional):
+
+ This value need not be set, even when CONFIG_ENV_OFFSET_REDUND is
+ set. If this value is set, it must be set to the same value as
+ CONFIG_ENV_SIZE.
+
config ENV_IS_IN_NAND
bool "Environment in a NAND device"
- depends on CMD_NAND
+ depends on !CHAIN_OF_TRUST
help
Define this if you have a NAND device which you want to use for the
environment.
+ - CONFIG_ENV_OFFSET:
+ - CONFIG_ENV_SIZE:
+
+ These two #defines specify the offset and size of the environment
+ area within the first NAND device. CONFIG_ENV_OFFSET must be
+ aligned to an erase block boundary.
+
+ - CONFIG_ENV_OFFSET_REDUND (optional):
+
+ This setting describes a second storage area of CONFIG_ENV_SIZE
+ size used to hold a redundant copy of the environment data, so
+ that there is a valid backup copy in case there is a power failure
+ during a "saveenv" operation. CONFIG_ENV_OFFSET_REDUND must be
+ aligned to an erase block boundary.
+
+ - CONFIG_ENV_RANGE (optional):
+
+ Specifies the length of the region in which the environment
+ can be written. This should be a multiple of the NAND device's
+ block size. Specifying a range with more erase blocks than
+ are needed to hold CONFIG_ENV_SIZE allows bad blocks within
+ the range to be avoided.
+
+ - CONFIG_ENV_OFFSET_OOB (optional):
+
+ Enables support for dynamically retrieving the offset of the
+ environment from block zero's out-of-band data. The
+ "nand env.oob" command can be used to record this offset.
+ Currently, CONFIG_ENV_OFFSET_REDUND is not supported when
+ using CONFIG_ENV_OFFSET_OOB.
+
+config ENV_IS_IN_NVRAM
+ bool "Environment in a non-volatile RAM"
+ depends on !CHAIN_OF_TRUST
+ help
+ Define this if you have some non-volatile memory device
+ (NVRAM, battery buffered SRAM) which you want to use for the
+ environment.
+
+ - CONFIG_ENV_ADDR:
+ - CONFIG_ENV_SIZE:
+
+ These two #defines are used to determine the memory area you
+ want to use for environment. It is assumed that this memory
+ can just be read and written to, without any special
+ provision.
+
+config ENV_IS_IN_ONENAND
+ bool "Environment is in OneNAND"
+ depends on !CHAIN_OF_TRUST
+ help
+ Define this if you want to put your local device's environment in
+ OneNAND.
+
+ - CONFIG_ENV_ADDR:
+ - CONFIG_ENV_SIZE:
+
+ These two #defines are used to determine the device range you
+ want to use for environment. It is assumed that this memory
+ can just be read and written to, without any special
+ provision.
+
+config ENV_IS_IN_REMOTE
+ bool "Environment is in remove memory space"
+ depends on !CHAIN_OF_TRUST
+ help
+ Define this if you have a remote memory space which you
+ want to use for the local device's environment.
+
+ - CONFIG_ENV_ADDR:
+ - CONFIG_ENV_SIZE:
+
+ These two #defines specify the address and size of the
+ environment area within the remote memory space. The
+ local device can get the environment from remote memory
+ space by SRIO or PCIE links.
+
+config ENV_IS_IN_SPI_FLASH
+ bool "Environment is in SPI flash"
+ depends on !CHAIN_OF_TRUST
+ help
+ Define this if you have a SPI Flash memory device which you
+ want to use for the environment.
+
+ - CONFIG_ENV_OFFSET:
+ - CONFIG_ENV_SIZE:
+
+ These two #defines specify the offset and size of the
+ environment area within the SPI Flash. CONFIG_ENV_OFFSET must be
+ aligned to an erase sector boundary.
+
+ - CONFIG_ENV_SECT_SIZE:
+
+ Define the SPI flash's sector size.
+
+ - CONFIG_ENV_OFFSET_REDUND (optional):
+
+ This setting describes a second storage area of CONFIG_ENV_SIZE
+ size used to hold a redundant copy of the environment data, so
+ that there is a valid backup copy in case there is a power failure
+ during a "saveenv" operation. CONFIG_ENV_OFFSET_REDUND must be
+ aligned to an erase sector boundary.
+
+ - CONFIG_ENV_SPI_BUS (optional):
+ - CONFIG_ENV_SPI_CS (optional):
+
+ Define the SPI bus and chip select. If not defined they will be 0.
+
+ - CONFIG_ENV_SPI_MAX_HZ (optional):
+
+ Define the SPI max work clock. If not defined then use 1MHz.
+
+ - CONFIG_ENV_SPI_MODE (optional):
+
+ Define the SPI work mode. If not defined then use SPI_MODE_3.
+
config ENV_IS_IN_UBI
bool "Environment in a UBI volume"
- depends on CMD_UBI
- depends on CMD_MTDPARTS
+ depends on !CHAIN_OF_TRUST
help
- Define this if you have a UBI volume which you want to use for the
- environment.
+ Define this if you have an UBI volume that you want to use for the
+ environment. This has the benefit of wear-leveling the environment
+ accesses, which is important on NAND.
+
+ - CONFIG_ENV_UBI_PART:
+
+ Define this to a string that is the mtd partition containing the UBI.
+
+ - CONFIG_ENV_UBI_VOLUME:
+
+ Define this to the name of the volume that you want to store the
+ environment in.
+
+ - CONFIG_ENV_UBI_VOLUME_REDUND:
+
+ Define this to the name of another volume to store a second copy of
+ the environment in. This will enable redundant environments in UBI.
+ It is assumed that both volumes are in the same MTD partition.
+
+ - CONFIG_UBI_SILENCE_MSG
+ - CONFIG_UBIFS_SILENCE_MSG
+
+ You will probably want to define these to avoid a really noisy system
+ when storing the env in UBI.
config ENV_IS_NOWHERE
bool "Environment is not stored"
Define this if you don't want to or can't have an environment stored
on a storage medium
-endchoice
+if ARCH_SUNXI
config ENV_OFFSET
hex "Environment Offset"
endif
obj-$(CONFIG_CROS_EC) += cros_ec.o
obj-y += dlmalloc.o
-ifdef CONFIG_SYS_MALLOC_F_LEN
+ifdef CONFIG_SYS_MALLOC_F
+ifneq ($(CONFIG_$(SPL_)SYS_MALLOC_F_LEN),0)
obj-y += malloc_simple.o
endif
+endif
obj-y += image.o
obj-$(CONFIG_ANDROID_BOOT_IMAGE) += image-android.o
obj-$(CONFIG_$(SPL_)OF_LIBFDT) += image-fdt.o
*/
gd->relocaddr -= gd->mon_len;
gd->relocaddr &= ~(4096 - 1);
-#ifdef CONFIG_E500
+#if defined(CONFIG_E500) || defined(CONFIG_MIPS)
/* round down to next 64 kB limit so that IVPR stays aligned */
gd->relocaddr &= ~(65536 - 1);
#endif
static int initf_console_record(void)
{
-#if defined(CONFIG_CONSOLE_RECORD) && defined(CONFIG_SYS_MALLOC_F_LEN)
+#if defined(CONFIG_CONSOLE_RECORD) && CONFIG_VAL(SYS_MALLOC_F_LEN)
return console_record_init();
#else
return 0;
static int initf_dm(void)
{
-#if defined(CONFIG_DM) && defined(CONFIG_SYS_MALLOC_F_LEN)
+#if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN)
int ret;
bootstage_start(BOOTSTATE_ID_ACCUM_DM_F, "dm_f");
{
ulong malloc_start;
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
debug("Pre-reloc malloc() used %#lx bytes (%ld KB)\n", gd->malloc_ptr,
gd->malloc_ptr / 1024);
#endif
unmap_sysmem(buffer);
}
-static void pre_console_puts(const char *s)
-{
- while (*s)
- pre_console_putc(*s++);
-}
-
static void print_pre_console_buffer(int flushpoint)
{
unsigned long in = 0, out = 0;
}
#else
static inline void pre_console_putc(const char c) {}
-static inline void pre_console_puts(const char *s) {}
static inline void print_pre_console_buffer(int flushpoint) {}
#endif
void puts(const char *s)
{
-#ifdef CONFIG_DEBUG_UART
- if (!gd || !(gd->flags & GD_FLG_SERIAL_READY)) {
- while (*s) {
- int ch = *s++;
-
- printch(ch);
- }
- return;
- }
-#endif
-#ifdef CONFIG_CONSOLE_RECORD
- if (gd && (gd->flags & GD_FLG_RECORD) && gd->console_out.start)
- membuff_put(&gd->console_out, s, strlen(s));
-#endif
-#ifdef CONFIG_SILENT_CONSOLE
- if (gd->flags & GD_FLG_SILENT)
- return;
-#endif
-
-#ifdef CONFIG_DISABLE_CONSOLE
- if (gd->flags & GD_FLG_DISABLE_CONSOLE)
- return;
-#endif
-
- if (!gd->have_console)
- return pre_console_puts(s);
-
- if (gd->flags & GD_FLG_DEVINIT) {
- /* Send to the standard output */
- fputs(stdout, s);
- } else {
- /* Send directly to the handler */
- pre_console_puts(s);
- serial_puts(s);
- }
+ while (*s)
+ putc(*s++);
}
#ifdef CONFIG_CONSOLE_RECORD
INTERNAL_SIZE_T nb;
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT))
return malloc_simple(bytes);
#endif
mchunkptr fwd; /* misc temp for linking */
int islr; /* track whether merging with last_remainder */
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
/* free() is a no-op - all the memory will be freed on relocation */
if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT))
return;
/* realloc of null is supposed to be same as malloc */
if (oldmem == NULL) return mALLOc(bytes);
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT)) {
/* This is harder to support and should not be needed */
panic("pre-reloc realloc() is not supported");
return NULL;
else
{
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT)) {
MALLOC_ZERO(mem, sz);
return mem;
int initf_malloc(void)
{
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
assert(gd->malloc_base); /* Set up by crt0.S */
- gd->malloc_limit = CONFIG_SYS_MALLOC_F_LEN;
+ gd->malloc_limit = CONFIG_VAL(SYS_MALLOC_F_LEN);
gd->malloc_ptr = 0;
#endif
return 0;
}
+#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
+static unsigned char env_flags;
+
+int env_import_redund(const char *buf1, const char *buf2)
+{
+ int crc1_ok, crc2_ok;
+ env_t *ep, *tmp_env1, *tmp_env2;
+
+ tmp_env1 = (env_t *)buf1;
+ tmp_env2 = (env_t *)buf2;
+
+ crc1_ok = crc32(0, tmp_env1->data, ENV_SIZE) ==
+ tmp_env1->crc;
+ crc2_ok = crc32(0, tmp_env2->data, ENV_SIZE) ==
+ tmp_env2->crc;
+
+ if (!crc1_ok && !crc2_ok) {
+ set_default_env("!bad CRC");
+ return 0;
+ } else if (crc1_ok && !crc2_ok) {
+ gd->env_valid = 1;
+ } else if (!crc1_ok && crc2_ok) {
+ gd->env_valid = 2;
+ } else {
+ /* both ok - check serial */
+ if (tmp_env1->flags == 255 && tmp_env2->flags == 0)
+ gd->env_valid = 2;
+ else if (tmp_env2->flags == 255 && tmp_env1->flags == 0)
+ gd->env_valid = 1;
+ else if (tmp_env1->flags > tmp_env2->flags)
+ gd->env_valid = 1;
+ else if (tmp_env2->flags > tmp_env1->flags)
+ gd->env_valid = 2;
+ else /* flags are equal - almost impossible */
+ gd->env_valid = 1;
+ }
+
+ if (gd->env_valid == 1)
+ ep = tmp_env1;
+ else
+ ep = tmp_env2;
+
+ env_flags = ep->flags;
+ return env_import((char *)ep, 0);
+}
+#endif /* CONFIG_SYS_REDUNDAND_ENVIRONMENT */
+
/* Export the environment and generate CRC for it. */
int env_export(env_t *env_out)
{
env_out->crc = crc32(0, env_out->data, ENV_SIZE);
+#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
+ env_out->flags = ++env_flags; /* increase the serial */
+#endif
+
return 0;
}
return (n == blk_cnt) ? 0 : -1;
}
-#ifdef CONFIG_ENV_OFFSET_REDUND
-static unsigned char env_flags;
-#endif
-
int saveenv(void)
{
ALLOC_CACHE_ALIGN_BUFFER(env_t, env_new, 1);
goto fini;
#ifdef CONFIG_ENV_OFFSET_REDUND
- env_new->flags = ++env_flags; /* increase the serial */
-
if (gd->env_valid == 1)
copy = 1;
#endif
struct mmc *mmc;
u32 offset1, offset2;
int read1_fail = 0, read2_fail = 0;
- int crc1_ok = 0, crc2_ok = 0;
- env_t *ep;
int ret;
int dev = mmc_get_env_dev();
const char *errmsg = NULL;
puts("*** Warning - some problems detected "
"reading environment; recovered successfully\n");
- crc1_ok = !read1_fail &&
- (crc32(0, tmp_env1->data, ENV_SIZE) == tmp_env1->crc);
- crc2_ok = !read2_fail &&
- (crc32(0, tmp_env2->data, ENV_SIZE) == tmp_env2->crc);
-
- if (!crc1_ok && !crc2_ok) {
+ if (read1_fail && read2_fail) {
errmsg = "!bad CRC";
ret = 1;
goto fini;
- } else if (crc1_ok && !crc2_ok) {
+ } else if (!read1_fail && read2_fail) {
gd->env_valid = 1;
- } else if (!crc1_ok && crc2_ok) {
+ env_import((char *)tmp_env1, 1);
+ } else if (read1_fail && !read2_fail) {
gd->env_valid = 2;
+ env_import((char *)tmp_env2, 1);
} else {
- /* both ok - check serial */
- if (tmp_env1->flags == 255 && tmp_env2->flags == 0)
- gd->env_valid = 2;
- else if (tmp_env2->flags == 255 && tmp_env1->flags == 0)
- gd->env_valid = 1;
- else if (tmp_env1->flags > tmp_env2->flags)
- gd->env_valid = 1;
- else if (tmp_env2->flags > tmp_env1->flags)
- gd->env_valid = 2;
- else /* flags are equal - almost impossible */
- gd->env_valid = 1;
+ env_import_redund((char *)tmp_env1, (char *)tmp_env2);
}
- free(env_ptr);
-
- if (gd->env_valid == 1)
- ep = tmp_env1;
- else
- ep = tmp_env2;
-
- env_flags = ep->flags;
- env_import((char *)ep, 0);
ret = 0;
fini:
size_t end = offset + CONFIG_ENV_RANGE;
size_t amount_saved = 0;
size_t blocksize, len;
+ struct mtd_info *mtd;
u_char *char_ptr;
- blocksize = nand_info[0]->erasesize;
+ mtd = get_nand_dev_by_index(0);
+ if (!mtd)
+ return 1;
+
+ blocksize = mtd->erasesize;
len = min(blocksize, (size_t)CONFIG_ENV_SIZE);
while (amount_saved < CONFIG_ENV_SIZE && offset < end) {
- if (nand_block_isbad(nand_info[0], offset)) {
+ if (nand_block_isbad(mtd, offset)) {
offset += blocksize;
} else {
char_ptr = &buf[amount_saved];
- if (nand_write(nand_info[0], offset, &len, char_ptr))
+ if (nand_write(mtd, offset, &len, char_ptr))
return 1;
offset += blocksize;
static int erase_and_write_env(const struct env_location *location,
u_char *env_new)
{
+ struct mtd_info *mtd;
int ret = 0;
- if (!nand_info[0])
+ mtd = get_nand_dev_by_index(0);
+ if (!mtd)
return 1;
printf("Erasing %s...\n", location->name);
- if (nand_erase_opts(nand_info[0], &location->erase_opts))
+ if (nand_erase_opts(mtd, &location->erase_opts))
return 1;
printf("Writing to %s... ", location->name);
return ret;
}
-#ifdef CONFIG_ENV_OFFSET_REDUND
-static unsigned char env_flags;
-#endif
-
int saveenv(void)
{
int ret = 0;
return ret;
#ifdef CONFIG_ENV_OFFSET_REDUND
- env_new->flags = ++env_flags; /* increase the serial */
env_idx = (gd->env_valid == 1);
#endif
size_t end = offset + CONFIG_ENV_RANGE;
size_t amount_loaded = 0;
size_t blocksize, len;
+ struct mtd_info *mtd;
u_char *char_ptr;
- if (!nand_info[0])
+ mtd = get_nand_dev_by_index(0);
+ if (!mtd)
return 1;
- blocksize = nand_info[0]->erasesize;
+ blocksize = mtd->erasesize;
len = min(blocksize, (size_t)CONFIG_ENV_SIZE);
while (amount_loaded < CONFIG_ENV_SIZE && offset < end) {
- if (nand_block_isbad(nand_info[0], offset)) {
+ if (nand_block_isbad(mtd, offset)) {
offset += blocksize;
} else {
char_ptr = &buf[amount_loaded];
- if (nand_read_skip_bad(nand_info[0], offset,
+ if (nand_read_skip_bad(mtd, offset,
&len, NULL,
- nand_info[0]->size, char_ptr))
+ mtd->size, char_ptr))
return 1;
offset += blocksize;
{
#if !defined(ENV_IS_EMBEDDED)
int read1_fail = 0, read2_fail = 0;
- int crc1_ok = 0, crc2_ok = 0;
- env_t *ep, *tmp_env1, *tmp_env2;
+ env_t *tmp_env1, *tmp_env2;
tmp_env1 = (env_t *)malloc(CONFIG_ENV_SIZE);
tmp_env2 = (env_t *)malloc(CONFIG_ENV_SIZE);
puts("*** Warning - some problems detected "
"reading environment; recovered successfully\n");
- crc1_ok = !read1_fail &&
- (crc32(0, tmp_env1->data, ENV_SIZE) == tmp_env1->crc);
- crc2_ok = !read2_fail &&
- (crc32(0, tmp_env2->data, ENV_SIZE) == tmp_env2->crc);
-
- if (!crc1_ok && !crc2_ok) {
- set_default_env("!bad CRC");
+ if (read1_fail && read2_fail) {
+ set_default_env("!bad env area");
goto done;
- } else if (crc1_ok && !crc2_ok) {
+ } else if (!read1_fail && read2_fail) {
gd->env_valid = 1;
- } else if (!crc1_ok && crc2_ok) {
+ env_import((char *)tmp_env1, 1);
+ } else if (read1_fail && !read2_fail) {
gd->env_valid = 2;
+ env_import((char *)tmp_env2, 1);
} else {
- /* both ok - check serial */
- if (tmp_env1->flags == 255 && tmp_env2->flags == 0)
- gd->env_valid = 2;
- else if (tmp_env2->flags == 255 && tmp_env1->flags == 0)
- gd->env_valid = 1;
- else if (tmp_env1->flags > tmp_env2->flags)
- gd->env_valid = 1;
- else if (tmp_env2->flags > tmp_env1->flags)
- gd->env_valid = 2;
- else /* flags are equal - almost impossible */
- gd->env_valid = 1;
+ env_import_redund((char *)tmp_env1, (char *)tmp_env2);
}
- free(env_ptr);
-
- if (gd->env_valid == 1)
- ep = tmp_env1;
- else
- ep = tmp_env2;
-
- env_flags = ep->flags;
- env_import((char *)ep, 0);
-
done:
free(tmp_env1);
free(tmp_env2);
ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE);
#if defined(CONFIG_ENV_OFFSET_OOB)
+ struct mtd_info *mtd = get_nand_dev_by_index(0);
/*
* If unable to read environment offset from NAND OOB then fall through
* to the normal environment reading code below
*/
- if (nand_info[0] && !get_nand_env_oob(nand_info[0],
- &nand_env_oob_offset)) {
+ if (mtd && !get_nand_env_oob(mtd, &nand_env_oob_offset)) {
printf("Found Environment offset in OOB..\n");
} else {
set_default_env("!no env offset in OOB");
#ifdef CONFIG_CMD_SAVEENV
#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
-static unsigned char env_flags;
-
int saveenv(void)
{
ALLOC_CACHE_ALIGN_BUFFER(env_t, env_new, 1);
return 1;
}
- env_new->flags = ++env_flags; /* increase the serial */
-
if (gd->env_valid == 1) {
puts("Writing to redundant UBI... ");
if (ubi_volume_write(CONFIG_ENV_UBI_VOLUME_REDUND,
{
ALLOC_CACHE_ALIGN_BUFFER(char, env1_buf, CONFIG_ENV_SIZE);
ALLOC_CACHE_ALIGN_BUFFER(char, env2_buf, CONFIG_ENV_SIZE);
- int crc1_ok = 0, crc2_ok = 0;
- env_t *ep, *tmp_env1, *tmp_env2;
+ env_t *tmp_env1, *tmp_env2;
/*
* In case we have restarted u-boot there is a chance that buffer
CONFIG_ENV_UBI_PART, CONFIG_ENV_UBI_VOLUME_REDUND);
}
- crc1_ok = crc32(0, tmp_env1->data, ENV_SIZE) == tmp_env1->crc;
- crc2_ok = crc32(0, tmp_env2->data, ENV_SIZE) == tmp_env2->crc;
-
- if (!crc1_ok && !crc2_ok) {
- set_default_env("!bad CRC");
- return;
- } else if (crc1_ok && !crc2_ok) {
- gd->env_valid = 1;
- } else if (!crc1_ok && crc2_ok) {
- gd->env_valid = 2;
- } else {
- /* both ok - check serial */
- if (tmp_env1->flags == 255 && tmp_env2->flags == 0)
- gd->env_valid = 2;
- else if (tmp_env2->flags == 255 && tmp_env1->flags == 0)
- gd->env_valid = 1;
- else if (tmp_env1->flags > tmp_env2->flags)
- gd->env_valid = 1;
- else if (tmp_env2->flags > tmp_env1->flags)
- gd->env_valid = 2;
- else /* flags are equal - almost impossible */
- gd->env_valid = 1;
- }
-
- if (gd->env_valid == 1)
- ep = tmp_env1;
- else
- ep = tmp_env2;
-
- env_flags = ep->flags;
- env_import((char *)ep, 0);
+ env_import_redund((char *)tmp_env1, (char *)tmp_env2);
}
#else /* ! CONFIG_SYS_REDUNDAND_ENVIRONMENT */
void env_relocate_spec(void)
return -EINVAL;
}
- *mtd = nand_info[dev->id->num];
+ *mtd = get_nand_dev_by_index(dev->id->num);
return 0;
}
ulong board_init_f_alloc_reserve(ulong top)
{
/* Reserve early malloc arena */
-#if defined(CONFIG_SYS_MALLOC_F)
- top -= CONFIG_SYS_MALLOC_F_LEN;
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+ top -= CONFIG_VAL(SYS_MALLOC_F_LEN);
#endif
/* LAST : reserve GD (rounded up to a multiple of 16 bytes) */
top = rounddown(top-sizeof(struct global_data), 16);
* Use gd as it is now properly set for all architectures.
*/
-#if defined(CONFIG_SYS_MALLOC_F)
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
/* go down one 'early malloc arena' */
gd->malloc_base = base;
/* next alloc will be higher by one 'early malloc arena' size */
- base += CONFIG_SYS_MALLOC_F_LEN;
+ base += CONFIG_VAL(SYS_MALLOC_F_LEN);
#endif
}
debug("spl_early_init()\n");
-#if defined(CONFIG_SYS_MALLOC_F_LEN)
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
if (setup_malloc) {
#ifdef CONFIG_MALLOC_F_ADDR
gd->malloc_base = CONFIG_MALLOC_F_ADDR;
#endif
- gd->malloc_limit = CONFIG_SYS_MALLOC_F_LEN;
+ gd->malloc_limit = CONFIG_VAL(SYS_MALLOC_F_LEN);
gd->malloc_ptr = 0;
}
#endif
default:
debug("Unsupported OS image.. Jumping nevertheless..\n");
}
-#if defined(CONFIG_SYS_MALLOC_F_LEN) && !defined(CONFIG_SYS_SPL_MALLOC_SIZE)
+#if CONFIG_VAL(SYS_MALLOC_F_LEN) && !defined(CONFIG_SYS_SPL_MALLOC_SIZE)
debug("SPL malloc() used %#lx bytes (%ld KB)\n", gd->malloc_ptr,
gd->malloc_ptr / 1024);
#endif
gd_t *new_gd;
ulong ptr = CONFIG_SPL_STACK_R_ADDR;
-#ifdef CONFIG_SPL_SYS_MALLOC_SIMPLE
+#if defined(CONFIG_SPL_SYS_MALLOC_SIMPLE) && CONFIG_SPL_SYS_MALLOC_F_LEN
if (CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN) {
ptr -= CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN;
gd->malloc_base = ptr;
return 0;
}
-int spl_mmc_get_device_index(u32 boot_device)
+static int spl_mmc_get_device_index(u32 boot_device)
{
switch (boot_device) {
case BOOT_DEVICE_MMC1:
#ifdef CONFIG_CMD_NAND
static int splash_nand_read_raw(u32 bmp_load_addr, int offset, size_t read_size)
{
- return nand_read_skip_bad(nand_info[nand_curr_device], offset,
+ struct mtd_info *mtd = get_nand_dev_by_index(nand_curr_device);
+ return nand_read_skip_bad(mtd, offset,
&read_size, NULL,
- nand_info[nand_curr_device]->size,
+ mtd->size,
(u_char *)bmp_load_addr);
}
#else
struct list_head list;
};
-/* TODO(sjg@chromium.org): Remove this when CONFIG_DM_USB is defined */
-static struct usb_hub_device hub_dev[USB_MAX_HUB];
-static int usb_hub_index;
static LIST_HEAD(usb_scan_list);
__weak void usb_hub_reset_devices(int port)
return;
}
+static inline bool usb_hub_is_superspeed(struct usb_device *hdev)
+{
+ return hdev->descriptor.bDeviceProtocol == 3;
+}
+
+#ifdef CONFIG_DM_USB
+bool usb_hub_is_root_hub(struct udevice *hub)
+{
+ if (device_get_uclass_id(hub->parent) != UCLASS_USB_HUB)
+ return true;
+
+ return false;
+}
+
+static int usb_set_hub_depth(struct usb_device *dev, int depth)
+{
+ if (depth < 0 || depth > 4)
+ return -EINVAL;
+
+ return usb_control_msg(dev, usb_sndctrlpipe(dev, 0),
+ USB_REQ_SET_HUB_DEPTH, USB_DIR_OUT | USB_RT_HUB,
+ depth, 0, NULL, 0, USB_CNTL_TIMEOUT);
+}
+#endif
+
static int usb_get_hub_descriptor(struct usb_device *dev, void *data, int size)
{
+ unsigned short dtype = USB_DT_HUB;
+
+ if (usb_hub_is_superspeed(dev))
+ dtype = USB_DT_SS_HUB;
+
return usb_control_msg(dev, usb_rcvctrlpipe(dev, 0),
USB_REQ_GET_DESCRIPTOR, USB_DIR_IN | USB_RT_HUB,
- USB_DT_HUB << 8, 0, data, size, USB_CNTL_TIMEOUT);
+ dtype << 8, 0, data, size, USB_CNTL_TIMEOUT);
}
static int usb_clear_port_feature(struct usb_device *dev, int port, int feature)
int usb_get_port_status(struct usb_device *dev, int port, void *data)
{
- return usb_control_msg(dev, usb_rcvctrlpipe(dev, 0),
+ int ret;
+
+ ret = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0),
USB_REQ_GET_STATUS, USB_DIR_IN | USB_RT_PORT, 0, port,
- data, sizeof(struct usb_hub_status), USB_CNTL_TIMEOUT);
+ data, sizeof(struct usb_port_status), USB_CNTL_TIMEOUT);
+
+#ifdef CONFIG_DM_USB
+ if (ret < 0)
+ return ret;
+
+ /*
+ * Translate the USB 3.0 hub port status field into the old version
+ * that U-Boot understands. Do this only when the hub is not root hub.
+ * For root hub, the port status field has already been translated
+ * in the host controller driver (see xhci_submit_root() in xhci.c).
+ *
+ * Note: this only supports driver model.
+ */
+
+ if (!usb_hub_is_root_hub(dev->dev) && usb_hub_is_superspeed(dev)) {
+ struct usb_port_status *status = (struct usb_port_status *)data;
+ u16 tmp = (status->wPortStatus) & USB_SS_PORT_STAT_MASK;
+
+ if (status->wPortStatus & USB_SS_PORT_STAT_POWER)
+ tmp |= USB_PORT_STAT_POWER;
+ if ((status->wPortStatus & USB_SS_PORT_STAT_SPEED) ==
+ USB_SS_PORT_STAT_SPEED_5GBPS)
+ tmp |= USB_PORT_STAT_SUPER_SPEED;
+
+ status->wPortStatus = tmp;
+ }
+#endif
+
+ return ret;
}
max(100, (int)pgood_delay) + 1000);
}
+#ifndef CONFIG_DM_USB
+static struct usb_hub_device hub_dev[USB_MAX_HUB];
+static int usb_hub_index;
+
void usb_hub_reset(void)
{
usb_hub_index = 0;
printf("ERROR: USB_MAX_HUB (%d) reached\n", USB_MAX_HUB);
return NULL;
}
+#endif
#define MAX_TRIES 5
return speed_str;
}
-int legacy_hub_port_reset(struct usb_device *dev, int port,
- unsigned short *portstat)
+/**
+ * usb_hub_port_reset() - reset a port given its usb_device pointer
+ *
+ * Reset a hub port and see if a device is present on that port, providing
+ * sufficient time for it to show itself. The port status is returned.
+ *
+ * @dev: USB device to reset
+ * @port: Port number to reset (note ports are numbered from 0 here)
+ * @portstat: Returns port status
+ */
+static int usb_hub_port_reset(struct usb_device *dev, int port,
+ unsigned short *portstat)
{
int err, tries;
ALLOC_CACHE_ALIGN_BUFFER(struct usb_port_status, portsts, 1);
return 0;
}
-#ifdef CONFIG_DM_USB
-int hub_port_reset(struct udevice *dev, int port, unsigned short *portstat)
-{
- struct usb_device *udev = dev_get_parent_priv(dev);
-
- return legacy_hub_port_reset(udev, port, portstat);
-}
-#endif
-
int usb_hub_port_connect_change(struct usb_device *dev, int port)
{
ALLOC_CACHE_ALIGN_BUFFER(struct usb_port_status, portsts, 1);
}
/* Reset the port */
- ret = legacy_hub_port_reset(dev, port, &portstatus);
+ ret = usb_hub_port_reset(dev, port, &portstatus);
if (ret < 0) {
if (ret != -ENXIO)
printf("cannot reset port %i!?\n", port + 1);
portchange = le16_to_cpu(portsts->wPortChange);
debug("Port %d Status %X Change %X\n", i + 1, portstatus, portchange);
- /* No connection change happened, wait a bit more. */
- if (!(portchange & USB_PORT_STAT_C_CONNECTION)) {
+ /*
+ * No connection change happened, wait a bit more.
+ *
+ * For some situation, the hub reports no connection change but a
+ * device is connected to the port (eg: CCS bit is set but CSC is not
+ * in the PORTSC register of a root hub), ignore such case.
+ */
+ if (!(portchange & USB_PORT_STAT_C_CONNECTION) &&
+ !(portstatus & USB_PORT_STAT_CONNECTION)) {
if (get_timer(0) >= hub->connect_timeout) {
debug("devnum=%d port=%d: timeout\n",
dev->devnum, i + 1);
return 0;
}
- /* Test if the connection came up, and if not exit */
- if (!(portstatus & USB_PORT_STAT_CONNECTION))
- return 0;
-
/* A new USB device is ready at this point */
debug("devnum=%d port=%d: USB dev found\n", dev->devnum, i + 1);
return ret;
}
+static struct usb_hub_device *usb_get_hub_device(struct usb_device *dev)
+{
+ struct usb_hub_device *hub;
+
+#ifndef CONFIG_DM_USB
+ /* "allocate" Hub device */
+ hub = usb_hub_allocate();
+#else
+ hub = dev_get_uclass_priv(dev->dev);
+#endif
+
+ return hub;
+}
+
static int usb_hub_configure(struct usb_device *dev)
{
int i, length;
__maybe_unused struct usb_hub_status *hubsts;
int ret;
- /* "allocate" Hub device */
- hub = usb_hub_allocate();
+ hub = usb_get_hub_device(dev);
if (hub == NULL)
return -ENOMEM;
hub->pusb_dev = dev;
+
/* Get the the hub descriptor */
ret = usb_get_hub_descriptor(dev, buffer, 4);
if (ret < 0) {
&descriptor->wHubCharacteristics)),
&hub->desc.wHubCharacteristics);
/* set the bitmap */
- bitmap = (unsigned char *)&hub->desc.DeviceRemovable[0];
+ bitmap = (unsigned char *)&hub->desc.u.hs.DeviceRemovable[0];
/* devices not removable by default */
memset(bitmap, 0xff, (USB_MAXCHILDREN+1+7)/8);
- bitmap = (unsigned char *)&hub->desc.PortPowerCtrlMask[0];
+ bitmap = (unsigned char *)&hub->desc.u.hs.PortPowerCtrlMask[0];
memset(bitmap, 0xff, (USB_MAXCHILDREN+1+7)/8); /* PowerMask = 1B */
for (i = 0; i < ((hub->desc.bNbrPorts + 1 + 7)/8); i++)
- hub->desc.DeviceRemovable[i] = descriptor->DeviceRemovable[i];
+ hub->desc.u.hs.DeviceRemovable[i] =
+ descriptor->u.hs.DeviceRemovable[i];
for (i = 0; i < ((hub->desc.bNbrPorts + 1 + 7)/8); i++)
- hub->desc.PortPowerCtrlMask[i] = descriptor->PortPowerCtrlMask[i];
+ hub->desc.u.hs.PortPowerCtrlMask[i] =
+ descriptor->u.hs.PortPowerCtrlMask[i];
dev->maxchild = descriptor->bNbrPorts;
debug("%d ports detected\n", dev->maxchild);
break;
}
+ switch (dev->descriptor.bDeviceProtocol) {
+ case USB_HUB_PR_FS:
+ break;
+ case USB_HUB_PR_HS_SINGLE_TT:
+ debug("Single TT\n");
+ break;
+ case USB_HUB_PR_HS_MULTI_TT:
+ ret = usb_set_interface(dev, 0, 1);
+ if (ret == 0) {
+ debug("TT per port\n");
+ hub->tt.multi = true;
+ } else {
+ debug("Using single TT (err %d)\n", ret);
+ }
+ break;
+ case USB_HUB_PR_SS:
+ /* USB 3.0 hubs don't have a TT */
+ break;
+ default:
+ debug("Unrecognized hub protocol %d\n",
+ dev->descriptor.bDeviceProtocol);
+ break;
+ }
+
+ /* Note 8 FS bit times == (8 bits / 12000000 bps) ~= 666ns */
+ switch (hubCharacteristics & HUB_CHAR_TTTT) {
+ case HUB_TTTT_8_BITS:
+ if (dev->descriptor.bDeviceProtocol != 0) {
+ hub->tt.think_time = 666;
+ debug("TT requires at most %d FS bit times (%d ns)\n",
+ 8, hub->tt.think_time);
+ }
+ break;
+ case HUB_TTTT_16_BITS:
+ hub->tt.think_time = 666 * 2;
+ debug("TT requires at most %d FS bit times (%d ns)\n",
+ 16, hub->tt.think_time);
+ break;
+ case HUB_TTTT_24_BITS:
+ hub->tt.think_time = 666 * 3;
+ debug("TT requires at most %d FS bit times (%d ns)\n",
+ 24, hub->tt.think_time);
+ break;
+ case HUB_TTTT_32_BITS:
+ hub->tt.think_time = 666 * 4;
+ debug("TT requires at most %d FS bit times (%d ns)\n",
+ 32, hub->tt.think_time);
+ break;
+ }
+
debug("power on to power good time: %dms\n",
descriptor->bPwrOn2PwrGood * 2);
debug("hub controller current requirement: %dmA\n",
for (i = 0; i < dev->maxchild; i++)
debug("port %d is%s removable\n", i + 1,
- hub->desc.DeviceRemovable[(i + 1) / 8] & \
+ hub->desc.u.hs.DeviceRemovable[(i + 1) / 8] & \
(1 << ((i + 1) % 8)) ? " not" : "");
if (sizeof(struct usb_hub_status) > USB_BUFSIZ) {
debug("%sover-current condition exists\n",
(le16_to_cpu(hubsts->wHubStatus) & HUB_STATUS_OVERCURRENT) ? \
"" : "no ");
+
+#ifdef CONFIG_DM_USB
+ /*
+ * Update USB host controller's internal representation of this hub
+ * after the hub descriptor is fetched.
+ */
+ ret = usb_update_hub_device(dev);
+ if (ret < 0 && ret != -ENOSYS) {
+ debug("%s: failed to update hub device for HCD (%x)\n",
+ __func__, ret);
+ return ret;
+ }
+
+ /*
+ * A maximum of seven tiers are allowed in a USB topology, and the
+ * root hub occupies the first tier. The last tier ends with a normal
+ * USB device. USB 3.0 hubs use a 20-bit field called 'route string'
+ * to route packets to the designated downstream port. The hub uses a
+ * hub depth value multiplied by four as an offset into the 'route
+ * string' to locate the bits it uses to determine the downstream
+ * port number.
+ */
+ if (usb_hub_is_root_hub(dev->dev)) {
+ hub->hub_depth = -1;
+ } else {
+ struct udevice *hdev;
+ int depth = 0;
+
+ hdev = dev->dev->parent;
+ while (!usb_hub_is_root_hub(hdev)) {
+ depth++;
+ hdev = hdev->parent;
+ }
+
+ hub->hub_depth = depth;
+
+ if (usb_hub_is_superspeed(dev)) {
+ debug("set hub (%p) depth to %d\n", dev, depth);
+ /*
+ * This request sets the value that the hub uses to
+ * determine the index into the 'route string index'
+ * for this hub.
+ */
+ ret = usb_set_hub_depth(dev, depth);
+ if (ret < 0) {
+ debug("%s: failed to set hub depth (%lX)\n",
+ __func__, dev->status);
+ return ret;
+ }
+ }
+ }
+#endif
+
usb_hub_power_on(hub);
/*
.child_pre_probe = usb_child_pre_probe,
.per_child_auto_alloc_size = sizeof(struct usb_device),
.per_child_platdata_auto_alloc_size = sizeof(struct usb_dev_platdata),
+ .per_device_auto_alloc_size = sizeof(struct usb_hub_device),
};
static const struct usb_device_id hub_id_table[] = {
CONFIG_SYS_CONFIG_NAME="10m50_devboard"
CONFIG_DEFAULT_DEVICE_TREE="10m50_devboard"
CONFIG_FIT=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_CONFIG_NAME="3c120_devboard"
CONFIG_DEFAULT_DEVICE_TREE="3c120_devboard"
CONFIG_FIT=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_ENV_IS_IN_REMOTE=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND,SYS_CLK_100"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_FSL_CAAM=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_FSL_CAAM=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_FSL_CAAM=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_FSL_CAAM=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND,SYS_CLK_100_DDR_100"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND,SYS_CLK_100_DDR_133"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_100"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_133"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD,SYS_CLK_100_DDR_100"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD,SYS_CLK_100_DDR_133"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100_DDR_100"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100_DDR_133"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_USB0_VBUS_PIN="PB10"
CONFIG_VIDEO_COMPOSITE=y
CONFIG_DEFAULT_DEVICE_TREE="sun5i-r8-chip"
+# CONFIG_ENV_IS_IN_MMC is not set
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_SPL=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
CONFIG_USB0_VBUS_PIN="PB10"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-gr8-chip-pro"
CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BLOCK_SIZE=0x40000,SYS_NAND_PAGE_SIZE=4096,SYS_NAND_OOBSIZE=256"
+# CONFIG_ENV_IS_IN_MMC is not set
CONFIG_ENV_IS_IN_UBI=y
CONFIG_ENV_UBI_PART="UBI"
CONFIG_ENV_UBI_VOLUME="uboot-env"
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=sunxi-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=sunxi-nand.0:256k(spl),256k(spl-backup),2m(uboot),2m(uboot-backup),-(UBI)"
# CONFIG_MMC is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_CONSOLE_MUX=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_CONSOLE_MUX=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_TARGET_M5208EVBE=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_TARGET_M52277EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SPANSION_BOOT"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_SYS_TEXT_BASE=0x43E00000
CONFIG_TARGET_M52277EVB=y
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_SF=y
CONFIG_SYS_TEXT_BASE=0xFFC00000
CONFIG_TARGET_M5235EVB=y
CONFIG_SYS_EXTRA_OPTIONS="NORFLASH_PS32BIT"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_LOADB is not set
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFFE00000
CONFIG_TARGET_M5235EVB=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_TARGET_M53017EVB=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_SYS_TEXT_BASE=0x47E00000
CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=50000000"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="-> "
CONFIG_SYS_TEXT_BASE=0x47E00000
CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_INPUT_CLKSRC=25000000"
+CONFIG_ENV_IS_NOWHERE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="-> "
CONFIG_SYS_TEXT_BASE=0x47E00000
CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_INPUT_CLKSRC=50000000"
+CONFIG_ENV_IS_NOWHERE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="-> "
CONFIG_SYS_TEXT_BASE=0x47E00000
CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,LOW_MCFCLK,SYS_INPUT_CLKSRC=50000000"
+CONFIG_ENV_IS_NOWHERE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="-> "
CONFIG_SYS_TEXT_BASE=0x47E00000
CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=25000000"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="-> "
CONFIG_SYS_TEXT_BASE=0x47E00000
CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=50000000"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="-> "
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_TARGET_M54451EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_INPUT_CLKSRC=24000000"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=1
CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_LOADB is not set
CONFIG_SYS_TEXT_BASE=0x47e00000
CONFIG_TARGET_M54451EVB=y
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT,SYS_INPUT_CLKSRC=24000000"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=1
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_SYS_TEXT_BASE=0x04000000
CONFIG_TARGET_M54455EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_INPUT_CLKSRC=66666666"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=1
CONFIG_CMD_IDE=y
# CONFIG_CMD_LOADB is not set
CONFIG_SYS_TEXT_BASE=0x04000000
CONFIG_TARGET_M54455EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_INPUT_CLKSRC=33333333"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=1
CONFIG_SYS_PROMPT="-> "
CONFIG_CMD_IDE=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_TARGET_M54455EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_INPUT_CLKSRC=66666666"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=1
CONFIG_CMD_IDE=y
# CONFIG_CMD_LOADB is not set
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_TARGET_M54455EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_INPUT_CLKSRC=33333333"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=1
CONFIG_CMD_IDE=y
# CONFIG_CMD_LOADB is not set
CONFIG_SYS_TEXT_BASE=0x4FE00000
CONFIG_TARGET_M54455EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_STMICRO_BOOT,CF_SBF,SYS_INPUT_CLKSRC=33333333"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=1
CONFIG_CMD_IDE=y
# CONFIG_CMD_LOADB is not set
CONFIG_PPC=y
CONFIG_8xx=y
CONFIG_TARGET_MCR3000=y
-CONFIG_BOOTDELAY=5
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_NET=y
-CONFIG_CMD_DHCP=y
-# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_PCI is not set
-CONFIG_OF_LIBFDT=y
-CONFIG_SYS_PROMPT="S3K> "
-CONFIG_NETDEVICES=y
-CONFIG_MPC8XX_FEC=y
-
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_FLASH=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_CMD_NAND=y
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_MD5SUM is not set
-# CONFIG_CMD_MISC is not set
-# CONFIG_CMD_SETGETDCR is not set
-# CONFIG_CMD_SHA1 is not set
-# CONFIG_CMD_SOURCE is not set
+CONFIG_8xx_GCLK_FREQ=132000000
CONFIG_CMD_IMMAP=y
-
-CONFIG_SYS_IMMR=0xFF000000
-
-CONFIG_SYS_OR0_PRELIM=0xFFC00926
+CONFIG_SYS_SIUMCR=0x00600400
+CONFIG_SYS_SYPCR=0xFFFFFF8F
+CONFIG_SYS_TBSCR=0x00C3
+CONFIG_SYS_PISCR=0x0000
+CONFIG_SYS_PLPRCR_BOOL=y
+CONFIG_SYS_PLPRCR=0x00460004
+CONFIG_SYS_SCCR=0x00C20000
+CONFIG_SYS_SCCR_MASK=0x60000000
+CONFIG_SYS_DER=0x2002000F
CONFIG_SYS_BR0_PRELIM=0x04000801
+CONFIG_SYS_OR0_PRELIM=0xFFC00926
CONFIG_SYS_BR1_PRELIM_BOOL=y
CONFIG_SYS_BR1_PRELIM=0x00000081
CONFIG_SYS_OR1_PRELIM=0xFE000E00
CONFIG_SYS_BR7_PRELIM_BOOL=y
CONFIG_SYS_BR7_PRELIM=0x1C000001
CONFIG_SYS_OR7_PRELIM=0xFFFF810A
-
-CONFIG_8xx_GCLK_FREQ=132000000
-
-CONFIG_SYS_SYPCR=0xFFFFFF8F
-CONFIG_SYS_SIUMCR=0x00600400
-CONFIG_SYS_TBSCR=0x00C3
-CONFIG_SYS_PISCR=0x0000
-CONFIG_SYS_PLPRCR_BOOL=y
-CONFIG_SYS_PLPRCR=0x00460004
-CONFIG_SYS_SCCR_MASK=0x60000000
-CONFIG_SYS_SCCR=0x00C20000
-CONFIG_SYS_DER=0x2002000F
-
-CONFIG_AUTOBOOT=y
+CONFIG_SYS_IMMR=0xFF000000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_BOOTDELAY=5
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="S3K> "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="\nEnter password - autoboot in %d sec...\n"
CONFIG_AUTOBOOT_DELAY_STR="root"
-
-CONFIG_OF_BOARD_SETUP=y
-
-CONFIG_LZMA=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_NAND=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+# CONFIG_CMD_MISC is not set
+# CONFIG_MMC is not set
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_MPC8XX_FEC=y
+# CONFIG_PCI is not set
CONFIG_SHA256=y
-
+CONFIG_LZMA=y
+CONFIG_OF_LIBFDT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=5
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=6
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+CONFIG_CMD_MTDPARTS=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=6
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+CONFIG_CMD_MTDPARTS=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ,NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=6
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+CONFIG_CMD_MTDPARTS=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ,NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=6
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+CONFIG_CMD_MTDPARTS=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_TARGET_MPC8315ERDB=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=6
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
+CONFIG_CMD_MTDPARTS=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_TARGET_MPC8323ERDB=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=6
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_TARGET_MPC8349EMDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=6
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
CONFIG_TARGET_MPC837XEMDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=6
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_TARGET_MPC837XEMDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=6
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_TARGET_MPC837XERDB=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=6
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_PHYS_64BIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
# CONFIG_CONSOLE_MUX is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
# CONFIG_CONSOLE_MUX is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
# CONFIG_CONSOLE_MUX is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_TARGET_MPC8536DS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
# CONFIG_CONSOLE_MUX is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_TARGET_MPC8541CDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="LEGACY"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
CONFIG_TARGET_MPC8544DS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
# CONFIG_CONSOLE_MUX is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_PING=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
-CONFIG_SCSI=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_RTL8139=y
+CONFIG_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_TARGET_MPC8555CDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="LEGACY"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
CONFIG_TARGET_MPC8568MDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="ATM"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_TARGET_MPC8569MDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BMP=y
CONFIG_CMD_EXT2=y
CONFIG_DOS_PARTITION=y
-CONFIG_SCSI=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
+CONFIG_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_KEYBOARD=y
CONFIG_SH=y
CONFIG_TARGET_MIGOR=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
# CONFIG_CMD_BDI is not set
CONFIG_AXP_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-r16-nintendo-nes-classic-edition"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+# CONFIG_ENV_IS_IN_MMC is not set
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=-1
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_ENV_IS_IN_REMOTE=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_ENV_IS_IN_REMOTE=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_ENV_IS_IN_REMOTE=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_ENV_IS_IN_REMOTE=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_DM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_DM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_ENV_IS_IN_REMOTE=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
# CONFIG_CMD_IRQ is not set
CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
# CONFIG_CMD_IRQ is not set
CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
# CONFIG_CMD_IRQ is not set
CONFIG_DM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
# CONFIG_CMD_IRQ is not set
CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_ENV_IS_IN_REMOTE=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
# CONFIG_CMD_IRQ is not set
CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_ENV_IS_IN_REMOTE=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_ENV_IS_IN_REMOTE=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_TARGET_TQM834X=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=6
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_DATE=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="TWR_P1025"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="B$ "
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_MMC=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_MMC=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_ALT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_BOOTZ=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_DELAY_STR="d"
CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x81000000
+CONFIG_FASTBOOT_BUF_SIZE=0x07000000
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
+CONFIG_LZO=y
CONFIG_OF_LIBFDT=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_DELAY_STR="d"
CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x81000000
+CONFIG_FASTBOOT_BUF_SIZE=0x07000000
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
+CONFIG_LZO=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_ENV_IS_IN_FAT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_MUSB_NEW_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x81000000
+CONFIG_FASTBOOT_BUF_SIZE=0x07000000
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MTDPARTS=y
CONFIG_OF_CONTROL=y
CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2"
# CONFIG_BLK is not set
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_RSA=y
+CONFIG_LZO=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_ENV_IS_IN_FAT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_MUSB_NEW_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x81000000
+CONFIG_FASTBOOT_BUF_SIZE=0x07000000
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_NAND=y
CONFIG_DFU_RAM=y
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_FAT_WRITE=y
+CONFIG_LZO=y
CONFIG_OF_LIBFDT=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_NOR=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NOR_BOOT=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x81000000
+CONFIG_FASTBOOT_BUF_SIZE=0x07000000
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MTDPARTS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_MMC_OMAP_HS=y
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
+CONFIG_LZO=y
CONFIG_OF_LIBFDT=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="SPI_BOOT"
CONFIG_SPI_BOOT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_MUSB_NEW_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x81000000
+CONFIG_FASTBOOT_BUF_SIZE=0x07000000
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MTDPARTS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_MMC_OMAP_HS=y
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
+CONFIG_LZO=y
CONFIG_OF_LIBFDT=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_ENV_IS_IN_FAT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_USB_GADGET_SUPPORT=y
CONFIG_SPL_USBETH_SUPPORT=y
# CONFIG_SPL_YMODEM_SUPPORT is not set
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x81000000
+CONFIG_FASTBOOT_BUF_SIZE=0x07000000
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MTDPARTS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_NAND=y
CONFIG_DFU_RAM=y
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
+CONFIG_LZO=y
CONFIG_OF_LIBFDT=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_ENV_IS_IN_FAT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MTDPARTS=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2"
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_RSA=y
+CONFIG_LZO=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0033"
+CONFIG_ENV_IS_IN_UBI=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_SERIES=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_FAT_WRITE=y
+CONFIG_LZO=y
CONFIG_OF_LIBFDT=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_SHC_ICT=y
CONFIG_SERIES=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_FAT_WRITE=y
+CONFIG_LZO=y
CONFIG_OF_LIBFDT=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_SHC_NETBOOT=y
CONFIG_SERIES=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_FAT_WRITE=y
+CONFIG_LZO=y
CONFIG_OF_LIBFDT=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_SERIES=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_FAT_WRITE=y
+CONFIG_LZO=y
CONFIG_OF_LIBFDT=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_SHC_SDBOOT=y
CONFIG_SERIES=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_FAT_WRITE=y
+CONFIG_LZO=y
CONFIG_OF_LIBFDT=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_SHC_SDBOOT=y
CONFIG_SERIES=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_FAT_WRITE=y
+CONFIG_LZO=y
CONFIG_OF_LIBFDT=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_FAT_WRITE=y
+CONFIG_LZO=y
CONFIG_OF_LIBFDT=y
CONFIG_ARCH_OMAP2PLUS=y
# CONFIG_SPL_GPIO_SUPPORT is not set
CONFIG_TARGET_AM3517_CRANE=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
# CONFIG_SPL_EXT_SUPPORT is not set
# CONFIG_SPL_GPIO_SUPPORT is not set
CONFIG_TARGET_AM3517_EVM=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
CONFIG_SPL_LOAD_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1,NAND"
+CONFIG_ENV_IS_IN_FAT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MTDPARTS=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm"
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_AM43XX=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
+CONFIG_ENV_IS_IN_FAT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_ISO_PARTITION=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_ISW_ENTRY_ADDR=0x30000000
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,QSPI,QSPI_BOOT"
CONFIG_QSPI_BOOT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
CONFIG_SPL_LOAD_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
+CONFIG_ENV_IS_IN_FAT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm"
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_AM43XX=y
CONFIG_TI_SECURE_DEVICE=y
+CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
+CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
+CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000
CONFIG_ISW_ENTRY_ADDR=0x403018e0
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1,NAND"
+CONFIG_ENV_IS_IN_FAT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MTDPARTS=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm"
CONFIG_DEFAULT_DEVICE_TREE="am572x-idk"
CONFIG_SPL_LOAD_FIT=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_OMAP54XX=y
CONFIG_TI_SECURE_DEVICE=y
-CONFIG_TARGET_AM57XX_EVM=y
CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000
+CONFIG_TARGET_AM57XX_EVM=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_TEXT_BASE=0xffc00000
CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_TARGET_AMCORE=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_ATH79=y
CONFIG_DEFAULT_DEVICE_TREE="ap121"
CONFIG_DEBUG_UART=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_DISPLAY_CPUINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
+CONFIG_CMD_MTDPARTS=y
# CONFIG_ISO_PARTITION is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_SPI_FLASH=y
CONFIG_TARGET_AP143=y
CONFIG_DEFAULT_DEVICE_TREE="ap143"
CONFIG_DEBUG_UART=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_DISPLAY_CPUINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_CMD_MTDPARTS=y
# CONFIG_ISO_PARTITION is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SH=y
CONFIG_TARGET_AP325RXA=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
# CONFIG_CMD_BDI is not set
CONFIG_SH=y
CONFIG_TARGET_AP_SH4A_4A=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
# CONFIG_CMD_BDI is not set
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_TEGRA=y
+CONFIG_DM_PMIC=y
CONFIG_PMIC_AS3722=y
+CONFIG_DM_REGULATOR=y
+CONFIG_REGULATOR_AS3722=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_CMD_HDMIDETECT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=1
# CONFIG_CONSOLE_MUX is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_VIDEO=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis_imx6/apalis_imx6q.cfg,MX6Q,DDR_MB=1024"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=1
# CONFIG_CONSOLE_MUX is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_VIDEO=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis_imx6/apalis_imx6q.cfg,MX6Q,DDR_MB=2048"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=1
# CONFIG_CONSOLE_MUX is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_IDENT_STRING=" apf27 patch 3.10"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=5
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=1
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_VIDEO=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg,MX6DL"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_VIDEO=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg,MX6DL"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_VIDEO=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos.cfg,MX6DL"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_RMOBILE=y
CONFIG_TARGET_ARMADILLO_800EVA=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
# CONFIG_CMD_BDI is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
CONFIG_ARM=y
CONFIG_TARGET_ASPENITE=y
CONFIG_IDENT_STRING="\nMarvell-Aspenite DB"
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
CONFIG_CMD_JFFS2=y
+CONFIG_FPGA_ALTERA=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91RM9200EK=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_SYS_STDIO_DEREGISTER is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91RM9200EK=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_SYS_STDIO_DEREGISTER is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek"
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS0"
+CONFIG_ENV_IS_IN_DATAFLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek"
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS1"
+CONFIG_ENV_IS_IN_DATAFLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek"
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_NANDFLASH"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS0"
+CONFIG_ENV_IS_IN_DATAFLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS3"
+CONFIG_ENV_IS_IN_DATAFLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_NANDFLASH"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
+CONFIG_ENV_IS_IN_DATAFLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
+CONFIG_ENV_IS_IN_DATAFLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_BOOT_NORFLASH"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NORFLASH"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS0"
+CONFIG_ENV_IS_IN_DATAFLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS3"
+CONFIG_ENV_IS_IN_DATAFLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_NANDFLASH"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek_2mmc"
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_MMC"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek_2mmc"
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_NANDFLASH"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek"
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS0"
+CONFIG_ENV_IS_IN_DATAFLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek"
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS1"
+CONFIG_ENV_IS_IN_DATAFLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek"
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_NANDFLASH"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_DEFAULT_DEVICE_TREE="at91sam9m10g45ek"
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC"
+CONFIG_ENV_IS_IN_FAT=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9m10g45ek"
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_NANDFLASH"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9n12ek"
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_MMC"
+CONFIG_ENV_IS_IN_FAT=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_CLK=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9n12ek"
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_NANDFLASH"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_CLK=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9n12ek"
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_SPIFLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_CLK=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9rlek"
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_DATAFLASH"
+CONFIG_ENV_IS_IN_DATAFLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9rlek"
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_MMC"
+CONFIG_ENV_IS_IN_FAT=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9rlek"
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_NANDFLASH"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek"
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_DATAFLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek"
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_MMC"
+CONFIG_ENV_IS_IN_FAT=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek"
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NANDFLASH"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek"
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_SPIFLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek"
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS0"
+CONFIG_ENV_IS_IN_DATAFLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek"
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS1"
+CONFIG_ENV_IS_IN_DATAFLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek"
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_NANDFLASH"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20-taurus"
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_TEXT_BASE=0x81000000
CONFIG_SYS_CLK_FREQ=750000000
CONFIG_DEFAULT_DEVICE_TREE="axs101"
+CONFIG_ENV_IS_IN_FAT=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_PROMPT="AXS# "
CONFIG_SYS_TEXT_BASE=0x81000000
CONFIG_SYS_CLK_FREQ=100000000
CONFIG_DEFAULT_DEVICE_TREE="axs103"
+CONFIG_ENV_IS_IN_FAT=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_PROMPT="AXS# "
CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
-CONFIG_SCSI=y
CONFIG_CPU=y
CONFIG_MMC=y
CONFIG_MMC_PCI=y
CONFIG_E1000=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
+CONFIG_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_ICH_SPI=y
CONFIG_TIMER=y
-CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_ARM=y
CONFIG_TARGET_BCM28155_AP=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_MMC_ENV_DEV=0"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARM=y
CONFIG_TARGET_BCM28155_AP=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARM=y
CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
CONFIG_TARGET_BCM23550_W1D=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARM=y
CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
CONFIG_TARGET_BCM28155_AP=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
CONFIG_TARGET_BCM28155_AP=y
CONFIG_SYS_EXTRA_OPTIONS="BCM_SF2_ETH,BCM_SF2_ETH_GMAC"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARM=y
CONFIG_TARGET_BCMCYGNUS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x20000000,ARMV7_NONSEC"
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARM=y
CONFIG_TARGET_BCMCYGNUS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x20000000"
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARM=y
CONFIG_TARGET_BCMCYGNUS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000"
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARM=y
CONFIG_TARGET_BCMCYGNUS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000,ARMV7_NONSEC"
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARM=y
CONFIG_TARGET_BCMCYGNUS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000"
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARM=y
CONFIG_TARGET_BCMCYGNUS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000"
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARM=y
CONFIG_TARGET_BCMNSP=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x01000000"
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_TARGET_BCMNS2=y
CONFIG_IDENT_STRING=" Broadcom Northstar 2"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_PROMPT="u-boot> "
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_LIVE=y
CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_BAV_VERSION=1
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_FAT_WRITE=y
+CONFIG_LZO=y
CONFIG_OF_LIBFDT=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_BAV_VERSION=2
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_FAT_WRITE=y
+CONFIG_LZO=y
CONFIG_OF_LIBFDT=y
CONFIG_ARCH_VF610=y
CONFIG_TARGET_BK4R1=y
CONFIG_DEFAULT_DEVICE_TREE="bk4r1"
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg,ENV_IS_IN_NAND"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_BLANCHE=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,EMMC_BOOT"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=-2
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=-2
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_NETCONSOLE=y
# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT"
CONFIG_SPI_BOOT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=-2
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_NETCONSOLE=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=-2
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="CADDY2"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=6
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TARGET_OMAP3_CAIRO=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=-2
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
CONFIG_MMC_OMAP_HS=y
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_CALIMAIN=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=0
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_TEGRA=y
+CONFIG_DM_PMIC=y
CONFIG_PMIC_AS3722=y
+CONFIG_DM_REGULATOR=y
+CONFIG_REGULATOR_AS3722=y
CONFIG_SYS_NS16550=y
CONFIG_TEGRA114_SPI=y
CONFIG_USB=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_VIDEO=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6QDL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_DM_GPIO=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_STORAGE=y
CONFIG_FAT_WRITE=y
+CONFIG_LZO=y
CONFIG_OF_LIBFDT=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-mickey"
CONFIG_DEBUG_UART=y
+CONFIG_ENV_IS_NOWHERE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-jerry"
CONFIG_DEBUG_UART=y
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_SILENT_CONSOLE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_CPU_SUPPORT=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_BLK=y
CONFIG_CPU=y
CONFIG_DM_I2C=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_ICH_SPI=y
CONFIG_TIMER=y
CONFIG_TPM_TIS_LPC=y
-CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_BLK=y
CONFIG_CPU=y
CONFIG_DM_I2C=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_ICH_SPI=y
CONFIG_TIMER=y
CONFIG_TPM_TIS_LPC=y
-CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-minnie"
CONFIG_DEBUG_UART=y
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_SILENT_CONSOLE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_HAVE_VGA_BIOS=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
-CONFIG_SCSI=y
CONFIG_CPU=y
CONFIG_INTEL_BROADWELL_GPIO=y
CONFIG_CROS_EC=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
+CONFIG_SCSI=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_ICH_SPI=y
CONFIG_TIMER=y
CONFIG_TPM_TIS_LPC=y
-CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_BLK=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_LPC=y
CONFIG_RTL8169=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_ICH_SPI=y
CONFIG_TIMER=y
CONFIG_TPM_TIS_LPC=y
-CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_OMAP54XX=y
CONFIG_TARGET_CL_SOM_AM57X=y
# CONFIG_SPL_NAND_SUPPORT is not set
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog"
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_VIDEO=y
# CONFIG_CMD_BMODE is not set
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL,SPL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
CONFIG_LED_STATUS=y
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TARGET_CM_T3517=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS_GPIO=y
CONFIG_LED_STATUS0=y
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TARGET_CM_T35=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS_GPIO=y
CONFIG_LED_STATUS0=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_ISO_PARTITION=y
CONFIG_DM=y
CONFIG_DM_GPIO=y
CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC=16296
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_OF_BOARD_SETUP=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
-CONFIG_SCSI=y
CONFIG_MMC_OMAP_HS=y
+CONFIG_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_CMD_HDMIDETECT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6DL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6DL"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=1
# CONFIG_CONSOLE_MUX is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_VIDEO=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_imx6/colibri_imx6.cfg,MX6DL,DDR_MB=256"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=1
# CONFIG_CONSOLE_MUX is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_IMX_BOOTAUX=y
CONFIG_DEFAULT_DEVICE_TREE="imx7-colibri"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_imx7/imximage.cfg,MX7D"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=1
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARM=y
CONFIG_TARGET_COLIBRI_PXA270=y
+CONFIG_ENV_IS_IN_FLASH=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="$ "
# CONFIG_CMD_ELF is not set
CONFIG_TARGET_COLIBRI_T20=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-colibri"
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_STDIO_DEREGISTER=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_VIDEO=y
CONFIG_TARGET_COLIBRI_VF=y
CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri"
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_IS_IN_NAND,IMX_NAND"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,IMX_NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=1
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_NS16550=y
CONFIG_ICH_SPI=y
CONFIG_TIMER=y
-CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_SYS_NS16550=y
CONFIG_ICH_SPI=y
CONFIG_TIMER=y
-CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD,DEVELOP"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_CONTROLCENTERD=y
CONFIG_SYS_EXTRA_OPTIONS="TRAILBLAZER,SPIFLASH,DEVELOP"
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_BOOTDELAY=-2
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_CONTROLCENTERD=y
CONFIG_SYS_EXTRA_OPTIONS="TRAILBLAZER,SPIFLASH"
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_BOOTDELAY=-2
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_EFI_PARTITION=y
CONFIG_OF_BOARD_FIXUP=y
CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_SCSI=y
CONFIG_DM_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_MMC_SDHCI_MV=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SCSI=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_NS16550=y
CONFIG_TIMER=y
CONFIG_TPM_TIS_LPC=y
-CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g45-corvus"
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,MACH_TYPE=2066,SYS_USE_NANDFLASH"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_CLK=y
CONFIG_VENDOR_INTEL=y
CONFIG_DEFAULT_DEVICE_TREE="cougarcanyon2"
CONFIG_TARGET_COUGARCANYON2=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_ARCH_EARLY_INIT_R is not set
CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
-CONFIG_SCSI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
+CONFIG_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_ICH_SPI=y
CONFIG_TIMER=y
-CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_MP_TABLE=y
CONFIG_FIT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
-CONFIG_SCSI=y
CONFIG_CPU=y
CONFIG_MMC=y
CONFIG_MMC_PCI=y
CONFIG_PCH_GBE=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
+CONFIG_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_ICH_SPI=y
CONFIG_TIMER=y
-CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_TARGET_NET2BIG_V2=y
CONFIG_IDENT_STRING=" D2 v2"
CONFIG_SYS_EXTRA_OPTIONS="D2NET_V2"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DA850EVM=y
CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH,USE_NOR,DIRECT_NOR_BOOT"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_TARGET_DALMORE=y
CONFIG_DEFAULT_DEVICE_TREE="tegra114-dalmore"
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra114 (Dalmore) # "
CONFIG_DEFAULT_DEVICE_TREE="armada-375-db"
CONFIG_DEBUG_UART=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="armada-388-gp"
CONFIG_DEBUG_UART=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_PARTITION_UUIDS is not set
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_SCSI=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_MV=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PCI=y
+CONFIG_SCSI=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_MIPS=y
CONFIG_TARGET_DBAU1X00=y
CONFIG_SYS_EXTRA_OPTIONS="DBAU1000"
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_SYS_PROMPT="DbAu1xx0 # "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_ELF is not set
CONFIG_MIPS=y
CONFIG_TARGET_DBAU1X00=y
CONFIG_DBAU1100=y
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_SYS_PROMPT="DbAu1xx0 # "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_ELF is not set
CONFIG_MIPS=y
CONFIG_TARGET_DBAU1X00=y
CONFIG_DBAU1500=y
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_SYS_PROMPT="DbAu1xx0 # "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_ELF is not set
CONFIG_MIPS=y
CONFIG_TARGET_DBAU1X00=y
CONFIG_DBAU1550=y
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_SYS_PROMPT="DbAu1xx0 # "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_ELF is not set
CONFIG_TARGET_DBAU1X00=y
CONFIG_DBAU1550=y
CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_SYS_PROMPT="DbAu1xx0 # "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_ELF is not set
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=1
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TARGET_DEVKIT8000=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_ICH_SPI=y
CONFIG_TIMER=y
-CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_TARGET_ADVANTECH_DMS_BA16=y
CONFIG_SYS_DDR_1G=y
CONFIG_VIDEO=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=1
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_ADVANTECH_DMS_BA16=y
CONFIG_VIDEO=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=1
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_DNS325=y
CONFIG_IDENT_STRING="\nD-Link DNS-325"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_KIRKWOOD=y
CONFIG_TARGET_DOCKSTAR=y
CONFIG_IDENT_STRING="\nSeagate FreeAgent DockStar"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="DockStar> "
CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
CONFIG_SPL_LOAD_FIT=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_DM_SCSI=y
CONFIG_DWC_AHCI=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_REGULATOR_PALMAS=y
CONFIG_DM_REGULATOR_LP873X=y
+CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_OMAP54XX=y
CONFIG_TI_SECURE_DEVICE=y
-CONFIG_TARGET_DRA7XX_EVM=y
CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000
+CONFIG_TARGET_DRA7XX_EVM=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
-CONFIG_DM_SCSI=y
CONFIG_DWC_AHCI=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_REGULATOR_PALMAS=y
CONFIG_DM_REGULATOR_LP873X=y
+CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 410C"
CONFIG_DEFAULT_DEVICE_TREE="dragonboard410c"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_ENV_IS_NOWHERE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="dragonboard410c => "
CONFIG_KIRKWOOD=y
CONFIG_TARGET_DREAMPLUG=y
CONFIG_IDENT_STRING="\nMarvell-DreamPlug"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_DS109=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_IDE=y
CONFIG_TARGET_DUOVERO=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_EA20=y
CONFIG_VIDEO=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TARGET_ECO5PK=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_SH=y
CONFIG_TARGET_ECOVEC=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
# CONFIG_CMD_BDI is not set
CONFIG_ARM=y
CONFIG_TARGET_EDB93XX=y
CONFIG_SYS_EXTRA_OPTIONS="MK_edb9315a"
+CONFIG_ENV_IS_IN_FLASH=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
--- /dev/null
+CONFIG_X86=y
+CONFIG_VENDOR_INTEL=y
+CONFIG_DEFAULT_DEVICE_TREE="edison"
+CONFIG_TARGET_EDISON=y
+CONFIG_SMP=y
+# CONFIG_ARCH_EARLY_INIT_R is not set
+# CONFIG_BOARD_EARLY_INIT_F is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_ENV_CALLBACK=y
+CONFIG_CMD_ENV_FLAGS=y
+CONFIG_CMD_MEMINFO=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_CPU=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_MMC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_TANGIER=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_DM_RTC=y
+CONFIG_INTEL_MID_SERIAL=y
+CONFIG_TIMER=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Intel"
+CONFIG_G_DNL_VENDOR_NUM=0x8087
+CONFIG_G_DNL_PRODUCT_NUM=0x0a99
+CONFIG_TANGIER_WATCHDOG=y
+CONFIG_FAT_WRITE=y
+CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SHA1=y
CONFIG_TARGET_EDMINIV2=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_IDENT_STRING=" EDMiniV2"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_TARGET_EFI=y
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_ARCH_EARLY_INIT_R is not set
CONFIG_DEBUG_UART_CLOCK=0
CONFIG_ICH_SPI=y
CONFIG_TIMER=y
-CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_EFI=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_IDENT_STRING=" for ESPRESSO7420"
CONFIG_DEFAULT_DEVICE_TREE="exynos7420-espresso7420"
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SH=y
CONFIG_TARGET_ESPT=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=-1
CONFIG_VERSION_VARIABLE=y
# CONFIG_CMD_BDI is not set
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_ETHERNUT5=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_TARGET_EVB_AST2500=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="ast2500-evb"
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_PRE_CON_BUF_ADDR=0x1e720000
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_TARGET_EVB_PX5=y
CONFIG_DEFAULT_DEVICE_TREE="rk3368-px5-evb"
CONFIG_DEBUG_UART=y
+CONFIG_ENV_IS_NOWHERE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ARCH_EARLY_INIT_R=y
CONFIG_FASTBOOT=y
CONFIG_ARM=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ROCKCHIP_RK3036=y
CONFIG_TARGET_EVB_RK3036=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk"
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x0
CONFIG_DEBUG_UART=y
+CONFIG_ENV_IS_NOWHERE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
# CONFIG_CMD_IMLS is not set
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ROCKCHIP_RK3036=y
-# CONFIG_SPL_SERIAL_PRESENT is not set
+# CONFIG_SPL_DM_SERIAL is not set
CONFIG_DEBUG_UART_BASE=0x20068000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
+CONFIG_SPL_TINY_MEMSET=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
CONFIG_TARGET_EVB_RK3229=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3229-evb"
+CONFIG_DEBUG_UART=y
+CONFIG_ENV_IS_IN_MMC=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ROCKCHIP_RK322X=y
-# CONFIG_SPL_PINCTRL_FULL is not set
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0x11030000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-evb"
CONFIG_DEBUG_UART=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DEFAULT_DEVICE_TREE="rk3328-evb"
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
+CONFIG_ENV_IS_IN_MMC=y
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x00800800
+CONFIG_FASTBOOT_BUF_SIZE=0x08000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_GPT=y
CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC2=y
CONFIG_USB_STORAGE=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_RK=y
CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_GADGET_DUALSPEED=y
CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="Rockchip"
CONFIG_G_DNL_VENDOR_NUM=0x2207
CONFIG_G_DNL_PRODUCT_NUM=0x330a
-CONFIG_FASTBOOT=y
-CONFIG_CMD_FASTBOOT=y
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=1
-CONFIG_FASTBOOT_BUF_ADDR=0x00800800
-CONFIG_FASTBOOT_BUF_SIZE=0x08000000
CONFIG_USE_TINY_PRINTF=y
CONFIG_ERRNO_STR=y
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_ENV_IS_IN_MMC=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
CONFIG_TARGET_EVB_RV1108=y
CONFIG_DEFAULT_DEVICE_TREE="rv1108-evb"
CONFIG_DEBUG_UART=y
+CONFIG_ENV_IS_NOWHERE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_SF=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-fennec"
CONFIG_DEBUG_UART=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-firefly"
CONFIG_DEBUG_UART=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SILENT_CONSOLE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_DM_KEYBOARD=y
+CONFIG_SYS_USB_EVENT_POLL=y
+CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_ENV_IS_IN_MMC=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
CONFIG_TARGET_FLEA3=y
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_CMD_MTDPARTS=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_OF_LIBFDT=y
CONFIG_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SYS_NS16550=y
CONFIG_ICH_SPI=y
CONFIG_TIMER=y
-CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_GE_B450V3=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_GE_B650V3=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_GE_B850V3=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_TARGET_GEEKBOX=y
CONFIG_DEFAULT_DEVICE_TREE="rk3368-geekbox"
CONFIG_DEBUG_UART=y
+CONFIG_ENV_IS_NOWHERE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_CMD_IMLS is not set
CONFIG_REGMAP=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_GOFLEXHOME=y
CONFIG_IDENT_STRING="\nSeagate GoFlex Home"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_GOSE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_BOOTZ=y
CONFIG_ARM=y
CONFIG_TARGET_GPLUGD=y
CONFIG_IDENT_STRING="\nMarvell-gplugD"
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g45-gurnard"
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G45"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_GURUPLUG=y
CONFIG_IDENT_STRING="\nMarvell-GuruPlug"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
# CONFIG_SYS_STDIO_DEREGISTER is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
# CONFIG_SYS_STDIO_DEREGISTER is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_SYS_STDIO_DEREGISTER is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_TARGET_H2200=y
CONFIG_FIT=y
# CONFIG_FIT_ENABLE_SHA256_SUPPORT is not set
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_TARGET_HARMONY=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-harmony"
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra20 (Harmony) # "
# CONFIG_CMD_IMI is not set
CONFIG_ARCH_HIGHBANK=y
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_ENV_IS_IN_NVRAM=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
-CONFIG_SCSI=y
# CONFIG_MMC is not set
+CONFIG_SCSI=y
CONFIG_OF_LIBFDT=y
CONFIG_IDENT_STRING="hikey"
CONFIG_DEFAULT_DEVICE_TREE="hi6220-hikey"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_ENV_IS_IN_FAT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=5
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="HRCON_DH"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=5
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_TEXT_BASE=0x81000000
CONFIG_SYS_CLK_FREQ=1000000000
CONFIG_DEFAULT_DEVICE_TREE="hsdk"
+CONFIG_ENV_IS_IN_FAT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_PROMPT="hsdk# "
# CONFIG_CMD_IMLS is not set
CONFIG_KIRKWOOD=y
CONFIG_TARGET_IB62X0=y
CONFIG_IDENT_STRING=" RaidSonic ICY BOX IB-NAS62x0"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_ICONNECT=y
CONFIG_IDENT_STRING=" Iomega iConnect"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="iconnect => "
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFFF00000"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=1
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020"
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS_GPIO=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030"
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS_GPIO=y
CONFIG_TARGET_OMAP3_IGEP00X0=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
CONFIG_DEFAULT_DEVICE_TREE="nexys4ddr"
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_ARM=y
CONFIG_TARGET_IMX31_PHYCORE=y
+CONFIG_ENV_IS_IN_EEPROM=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_PROMPT="uboot> "
CONFIG_CMD_EEPROM=y
CONFIG_ARM=y
CONFIG_TARGET_IMX31_PHYCORE_EET=y
CONFIG_VIDEO=y
+CONFIG_ENV_IS_IN_EEPROM=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_TARGET_MX6LOGICPD=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-logicpd"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg,MX6Q"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
# CONFIG_BLK is not set
CONFIG_SYS_I2C_MXC=y
# CONFIG_DM_MMC_OPS is not set
CONFIG_VIDEO=y
# CONFIG_CMD_BMODE is not set
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore"
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_FEC_MXC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
+CONFIG_DEBUG_UART_MXC=y
+CONFIG_DEBUG_UART_BASE=0x021f0000
+CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_VIDEO_IPUV3=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_NAND"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
CONFIG_SPL_DMA_SUPPORT=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_TARGET_MX6Q_ICORE_RQS=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+# CONFIG_CMD_BMODE is not set
+CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore-rqs"
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_BOOTDELAY=3
+CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="icorem6qdl-rqs> "
+# CONFIG_CMD_IMLS is not set
+CONFIG_CRC32_VERIFY=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_LIST="imx6q-icore-rqs imx6dl-icore-rqs"
+# CONFIG_BLK is not set
+CONFIG_SYS_I2C_MXC=y
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ9021=y
+CONFIG_FEC_MXC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_MXC_UART=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_MX6Q_ICORE_RQS=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-# CONFIG_CMD_BMODE is not set
-CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore-rqs"
-CONFIG_FIT=y
-CONFIG_FIT_SIGNATURE=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC"
-CONFIG_BOOTDELAY=3
-CONFIG_SPL=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="icorem6qdl-rqs> "
-# CONFIG_CMD_IMLS is not set
-CONFIG_CRC32_VERIFY=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_LIST="imx6q-icore-rqs imx6dl-icore-rqs"
-# CONFIG_BLK is not set
-CONFIG_SYS_I2C_MXC=y
-# CONFIG_DM_MMC_OPS is not set
-CONFIG_PHYLIB=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ9021=y
-CONFIG_FEC_MXC=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_IMX6=y
-CONFIG_MXC_UART=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_NAND"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_NAND"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_TARGET_NETSPACE_V2=y
CONFIG_IDENT_STRING=" IS v2"
CONFIG_SYS_EXTRA_OPTIONS="INETSPACE_V2"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_AP=y
CONFIG_CM720T=y
+CONFIG_ENV_IS_NOWHERE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_AP=y
CONFIG_CM920T=y
+CONFIG_ENV_IS_NOWHERE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_AP=y
CONFIG_CM926EJ_S=y
+CONFIG_ENV_IS_NOWHERE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_AP=y
CONFIG_CM946ES=y
+CONFIG_ENV_IS_NOWHERE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_LIVE=y
CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_TEGRA=y
+CONFIG_DM_PMIC=y
CONFIG_PMIC_AS3722=y
+CONFIG_DM_REGULATOR=y
+CONFIG_REGULATOR_AS3722=y
CONFIG_SYS_NS16550=y
CONFIG_TEGRA114_SPI=y
CONFIG_USB=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2e-evm"
CONFIG_OF_BOARD_SETUP=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DTB_RESELECT=y
+CONFIG_FIT_EMBED=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
-CONFIG_DTB_RESELECT=y
-CONFIG_FIT_EMBED=y
-CONFIG_OF_LIST="keystone-k2e-evm"
CONFIG_TARGET_K2E_EVM=y
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2e-evm"
CONFIG_OF_BOARD_SETUP=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2g-evm"
CONFIG_OF_BOARD_SETUP=y
+CONFIG_ENV_IS_IN_FAT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DTB_RESELECT=y
+CONFIG_FIT_EMBED=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
CONFIG_OF_CONTROL=y
+CONFIG_OF_LIST="keystone-k2g-generic keystone-k2g-evm keystone-k2g-ice"
CONFIG_DM=y
# CONFIG_BLK is not set
CONFIG_DM_MMC=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
-CONFIG_DTB_RESELECT=y
-CONFIG_FIT_EMBED=y
-CONFIG_OF_LIST="keystone-k2g-generic keystone-k2g-evm keystone-k2g-ice"
CONFIG_TARGET_K2G_EVM=y
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2g-evm"
CONFIG_OF_BOARD_SETUP=y
+CONFIG_ENV_IS_IN_FAT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2hk-evm"
CONFIG_OF_BOARD_SETUP=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DTB_RESELECT=y
+CONFIG_FIT_EMBED=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
-CONFIG_DTB_RESELECT=y
-CONFIG_FIT_EMBED=y
-CONFIG_OF_LIST="keystone-k2hk-evm"
CONFIG_TARGET_K2HK_EVM=y
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2hk-evm"
CONFIG_OF_BOARD_SETUP=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2l-evm"
CONFIG_OF_BOARD_SETUP=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DTB_RESELECT=y
+CONFIG_FIT_EMBED=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
-CONFIG_DTB_RESELECT=y
-CONFIG_FIT_EMBED=y
-CONFIG_OF_LIST="keystone-k2l-evm"
CONFIG_OMAP44XX=y
CONFIG_TARGET_KC1=y
# CONFIG_SPL_NAND_SUPPORT is not set
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_IDENT_STRING="\nKeymile Kirkwood 128M16"
CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_128M16"
+CONFIG_ENV_IS_IN_EEPROM=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_PING=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_IDENT_STRING="\nKeymile Kirkwood"
CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD"
+CONFIG_ENV_IS_IN_EEPROM=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_PING=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_IDENT_STRING="\nKeymile Kirkwood PCI"
CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_PCI"
+CONFIG_ENV_IS_IN_EEPROM=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_PING=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="KMCOGE4"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_JFFS2=y
# CONFIG_CMD_IRQ is not set
CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
CONFIG_DOS_PARTITION=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="KMCOGE5NE"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_CMD_PING=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_IDENT_STRING="\nKeymile COGE5UN"
CONFIG_SYS_EXTRA_OPTIONS="KM_COGE5UN"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_PING=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="KMETER1"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_CMD_PING=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="KMLION1"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_JFFS2=y
# CONFIG_CMD_IRQ is not set
CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
CONFIG_DOS_PARTITION=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_IDENT_STRING="\nKeymile NUSA"
CONFIG_SYS_EXTRA_OPTIONS="KM_NUSA"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_PING=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_PING=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_IDENT_STRING="\nKeymile SUGP1"
CONFIG_SYS_EXTRA_OPTIONS="KM_SUGP1"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_PING=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_PING=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_IDENT_STRING="\nKeymile SUV31"
CONFIG_SYS_EXTRA_OPTIONS="KM_SUV31"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_PING=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_DIAG=y
CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_CMD_PING=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_CMD_JFFS2=y
CONFIG_CMD_DIAG=y
CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_KOELSCH=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_BOOTZ=y
CONFIG_ARM=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ROCKCHIP_RK3036=y
CONFIG_TARGET_KYLIN_RK3036=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x0
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
# CONFIG_CMD_IMLS is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ROCKCHIP_RK3036=y
CONFIG_DM_REGULATOR_FIXED=y
+# CONFIG_SPL_DM_SERIAL is not set
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
CONFIG_USB_STORAGE=y
+CONFIG_SPL_TINY_MEMSET=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_RMOBILE=y
CONFIG_TARGET_KZM9G=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
CONFIG_SYS_PROMPT="KZM-A9-GT# "
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_LAGER=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_BOOTZ=y
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_LEGOEV3=y
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_BOOTDELAY=0
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=1
CONFIG_DEFAULT_FDT_FILE="imx6ul-liteboard.dtb"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_QSPI_BOOT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_QSPI_BOOT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
-# CONFIG_BLK is not set
CONFIG_SCSI=y
+# CONFIG_BLK is not set
CONFIG_DM_MMC=y
# CONFIG_DM_MMC_OPS is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_QSPI_BOOT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_TARGET_LS1021AIOT=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart"
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_CMD_GPT=y
CONFIG_CMD_FAT=y
CONFIG_TARGET_LS1021AIOT=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart"
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="LPUART"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
CONFIG_NAND_BOOT=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="LPUART"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_QSPI_BOOT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
CONFIG_SD_BOOT=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
CONFIG_SD_BOOT=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="LPUART"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_QSPI_BOOT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
CONFIG_SD_BOOT=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
CONFIG_SD_BOOT=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="LPUART"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
CONFIG_NAND_BOOT=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_QSPI_BOOT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
CONFIG_SD_BOOT=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
CONFIG_SD_BOOT=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GPT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
CONFIG_NAND_BOOT=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
CONFIG_SD_BOOT=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="LPUART"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL"
CONFIG_NAND_BOOT=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_QSPI_BOOT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL"
CONFIG_SD_BOOT=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT_QSPI"
CONFIG_SD_BOOT=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,EMMC_BOOT"
CONFIG_SD_BOOT=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_QSPI_BOOT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL"
CONFIG_SD_BOOT=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="EMU"
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_BOOTDELAY=10
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_CONSOLE is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SIMU"
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_BOOTDELAY=10
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_CONSOLE is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_NAND_BOOT=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_QSPI_BOOT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
CONFIG_SD_BOOT=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_NAND_BOOT=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_QSPI_BOOT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_GREPENV=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
-CONFIG_SCSI=y
CONFIG_FSL_CAAM=y
CONFIG_DM_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_QSPI_BOOT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_GREPENV=y
CONFIG_TARGET_LSXL=y
CONFIG_IDENT_STRING=" LS-CHLv2"
CONFIG_SYS_EXTRA_OPTIONS="LSCHLV2"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="LSXHL"
CONFIG_API=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_FIT=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_CMD_BMODE is not set
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aries/m53evk/imximage.cfg"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_TARGET_EMBESTMX6BOARDS=y
CONFIG_VIDEO=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,ENV_IS_IN_SPI_FLASH"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SPL_SERIAL_SUPPORT=y
# CONFIG_CMD_BMODE is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_nor.cfg,MX6QDL"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_DM=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPL_SERIAL_SUPPORT=y
# CONFIG_CMD_BMODE is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_sd.cfg,MX6QDL"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_DM=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
# CONFIG_SPL_GPIO_SUPPORT is not set
CONFIG_TARGET_MCX=y
CONFIG_VIDEO=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-medcom-wide"
CONFIG_FIT=y
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra20 (Medcom-Wide) # "
# CONFIG_CMD_IMI is not set
CONFIG_TARGET_MEESC=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
+CONFIG_ENV_IS_IN_DATAFLASH=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_TARGET_MEESC=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_IDENT_STRING="\nKeymile COGE3UN"
CONFIG_SYS_EXTRA_OPTIONS="KM_MGCOGE3UN"
+CONFIG_ENV_IS_IN_EEPROM=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_PING=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_PING=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_NETCONSOLE=y
CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
-CONFIG_SCSI=y
CONFIG_CPU=y
CONFIG_MMC=y
CONFIG_MMC_PCI=y
CONFIG_RTL8169=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
+CONFIG_SCSI=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_SYS_NS16550=y
CONFIG_ICH_SPI=y
CONFIG_TIMER=y
-CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_DM_VIDEO=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-miqi"
CONFIG_DEBUG_UART=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SILENT_CONSOLE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_TARGET_MPC8308_P1M=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=5
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
CONFIG_SH=y
CONFIG_TARGET_MS7722SE=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
# CONFIG_CMD_BDI is not set
CONFIG_SH=y
CONFIG_TARGET_MS7750SE=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=-1
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TARGET_MT_VENTOUX=y
CONFIG_VIDEO=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_MVEBU=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_MVEBU_ARMADA_8K=y
-CONFIG_DEFAULT_DEVICE_TREE="armada-7040-db-nand"
-CONFIG_SMBIOS_PRODUCT_NAME=""
-CONFIG_DEBUG_UART=y
-CONFIG_AHCI=y
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_ARCH_EARLY_INIT_R=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PART=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_MVEBU_BUBT=y
-CONFIG_MVEBU_NAND_BOOT=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
-CONFIG_BLOCK_CACHE=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_MVTWSI=y
-CONFIG_MISC=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_XENON=y
-CONFIG_NAND_PXA3XX=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_PCIE_DW_MVEBU=y
-CONFIG_MVEBU_COMPHY_SUPPORT=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_ARMADA_8K=y
-# CONFIG_SPL_SERIAL_PRESENT is not set
-CONFIG_DEBUG_UART_BASE=0xf0512000
-CONFIG_DEBUG_UART_CLOCK=200000000
-CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_SMBIOS_MANUFACTURER=""
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_MVEBU=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_MVEBU_ARMADA_8K=y
-CONFIG_DEFAULT_DEVICE_TREE="armada-7040-db"
-CONFIG_SMBIOS_PRODUCT_NAME=""
-CONFIG_DEBUG_UART=y
-CONFIG_AHCI=y
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_ARCH_EARLY_INIT_R=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PART=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_MVEBU_BUBT=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
-CONFIG_BLOCK_CACHE=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_MVTWSI=y
-CONFIG_MISC=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_XENON=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHY_MARVELL=y
-CONFIG_MVPP2=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_PCIE_DW_MVEBU=y
-CONFIG_MVEBU_COMPHY_SUPPORT=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_ARMADA_8K=y
-# CONFIG_SPL_SERIAL_PRESENT is not set
-CONFIG_DEBUG_UART_BASE=0xf0512000
-CONFIG_DEBUG_UART_CLOCK=200000000
-CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_SMBIOS_MANUFACTURER=""
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_MVEBU=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_MVEBU_ARMADA_8K=y
-CONFIG_DEFAULT_DEVICE_TREE="armada-8040-db"
-CONFIG_SMBIOS_PRODUCT_NAME=""
-CONFIG_DEBUG_UART=y
-CONFIG_AHCI=y
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_ARCH_EARLY_INIT_R=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PART=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_MVEBU_BUBT=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
-CONFIG_BLOCK_CACHE=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_MVTWSI=y
-CONFIG_MISC=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_XENON=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHY_MARVELL=y
-CONFIG_MVPP2=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_PCIE_DW_MVEBU=y
-CONFIG_MVEBU_COMPHY_SUPPORT=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_ARMADA_8K=y
-# CONFIG_SPL_SERIAL_PRESENT is not set
-CONFIG_DEBUG_UART_BASE=0xf0512000
-CONFIG_DEBUG_UART_CLOCK=200000000
-CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_SMBIOS_MANUFACTURER=""
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_MVEBU_ARMADA_8K=y
+CONFIG_DEFAULT_DEVICE_TREE="armada-8040-db"
+CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_ARCH_EARLY_INIT_R=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_MVEBU_BUBT=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
+CONFIG_BLOCK_CACHE=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_XENON=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_MARVELL=y
+CONFIG_MVPP2=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCIE_DW_MVEBU=y
+CONFIG_MVEBU_COMPHY_SUPPORT=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_ARMADA_8K=y
+# CONFIG_SPL_SERIAL_PRESENT is not set
+CONFIG_DEBUG_UART_BASE=0xf0512000
+CONFIG_DEBUG_UART_CLOCK=200000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_SMBIOS_MANUFACTURER=""
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_VIDEO=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=1
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARM=y
CONFIG_TARGET_MX25PDK=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=1
CONFIG_DEFAULT_FDT_FILE="imx25-pdk.dtb"
CONFIG_HUSH_PARSER=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_VIDEO=y
-CONFIG_SYS_EXTRA_OPTIONS="MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_MMC"
+CONFIG_SYS_EXTRA_OPTIONS="MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=1
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_MMC"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=1
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_VIDEO=y
-CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=1
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_VIDEO=y
-CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_SPI_FLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=1
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARM=y
CONFIG_TARGET_MX31ADS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_CMD_SPI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=1
CONFIG_SPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_ARM=y
CONFIG_TARGET_MX35PDK=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_VIDEO=y
# CONFIG_CMD_BMODE is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx51evk/imximage.cfg"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=1
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_TARGET_MX53ARD=y
# CONFIG_CMD_BMODE is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="imx53-ard.dtb"
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BMODE is not set
CONFIG_DEFAULT_DEVICE_TREE="imx53-cx9020"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/beckhoff/mx53cx9020/imximage.cfg"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=1
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
+CONFIG_CMD_PXE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_ARCH_MX5=y
CONFIG_TARGET_MX53EVK=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53evk/imximage.cfg"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
CONFIG_VIDEO=y
# CONFIG_CMD_BMODE is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53loco/imximage.cfg"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=1
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_TARGET_MX53SMD=y
# CONFIG_CMD_BMODE is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53smd/imximage.cfg"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_BMODE is not set
CONFIG_CMD_HDMIDETECT=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
+CONFIG_ENV_IS_IN_MMC=y
# CONFIG_SYS_STDIO_DEREGISTER is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
+CONFIG_CMD_SATA=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_TARGET_MX6QARM2=y
# CONFIG_CMD_BMODE is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,DDR_MB=2048"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_TARGET_MX6QARM2=y
# CONFIG_CMD_BMODE is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,MX6DL_LPDDR2,DDR_MB=512"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_TARGET_MX6QSABREAUTO=y
-CONFIG_VIDEO=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6dl.cfg,MX6DL"
-CONFIG_BOOTDELAY=3
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_SF=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_CI_UDC=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_G_DNL_MANUFACTURER="FSL"
-CONFIG_G_DNL_VENDOR_NUM=0x0525
-CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
-# CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_OF_LIBFDT=y
CONFIG_TARGET_MX6QARM2=y
# CONFIG_CMD_BMODE is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,DDR_MB=2048"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_TARGET_MX6QARM2=y
# CONFIG_CMD_BMODE is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,MX6DQ_LPDDR2,DDR_MB=512"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_TARGET_MX6QSABREAUTO=y
-CONFIG_VIDEO=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6qp.cfg,MX6Q"
-CONFIG_BOOTDELAY=3
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_SF=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_CI_UDC=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_G_DNL_MANUFACTURER="FSL"
-CONFIG_G_DNL_VENDOR_NUM=0x0525
-CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
-# CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_TARGET_MX6QSABREAUTO=y
-CONFIG_VIDEO=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q"
-CONFIG_BOOTDELAY=3
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_SF=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_CI_UDC=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_G_DNL_MANUFACTURER="FSL"
-CONFIG_G_DNL_VENDOR_NUM=0x0525
-CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
-# CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_OF_LIBFDT=y
CONFIG_VIDEO=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
# CONFIG_SYS_STDIO_DEREGISTER is not set
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_TARGET_MX6SABREAUTO=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_VIDEO=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SPL,MX6QDL"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_SF=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="FSL"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_OF_LIBFDT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_VIDEO=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6QDL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_BMODE is not set
CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL"
CONFIG_SPI_BOOT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
# CONFIG_CMD_BMODE is not set
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6SL,SYS_I2C"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6SL,SYS_I2C"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
CONFIG_DEFAULT_DEVICE_TREE="imx6sll-evk"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sllevk/imximage.cfg"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BMODE is not set
CONFIG_DEFAULT_DEVICE_TREE="imx6sll-evk"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sllevk/imximage.cfg"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_VIDEO=y
# CONFIG_CMD_BMODE is not set
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_VIDEO=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_VIDEO=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_TARGET_MX6ULL_14X14_EVK=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-evk"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_USE_IMXIMG_PLUGIN=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-evk"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_TARGET_MX7ULP_EVK=y
CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_TARGET_MX7ULP_EVK=y
CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_NAS220=y
CONFIG_IDENT_STRING="\nNAS 220"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_TARGET_NET2BIG_V2=y
CONFIG_IDENT_STRING=" 2Big v2"
CONFIG_SYS_EXTRA_OPTIONS="NET2BIG_V2"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_TARGET_NETSPACE_V2=y
CONFIG_IDENT_STRING=" NS v2 Lite"
CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_LITE_V2"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_TARGET_NETSPACE_V2=y
CONFIG_IDENT_STRING=" NS Max v2"
CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MAX_V2"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_TARGET_NETSPACE_V2=y
CONFIG_IDENT_STRING=" NS v2 Mini"
CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MINI_V2"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_TARGET_NETSPACE_V2=y
CONFIG_IDENT_STRING=" NS v2"
CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_V2"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_VIDEO=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
# CONFIG_SYS_STDIO_DEREGISTER is not set
CONFIG_VIDEO=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
# CONFIG_SYS_STDIO_DEREGISTER is not set
CONFIG_VIDEO=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
# CONFIG_SYS_STDIO_DEREGISTER is not set
CONFIG_VIDEO=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
# CONFIG_SYS_STDIO_DEREGISTER is not set
CONFIG_VIDEO=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
# CONFIG_SYS_STDIO_DEREGISTER is not set
CONFIG_VIDEO=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
# CONFIG_SYS_STDIO_DEREGISTER is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TARGET_NOKIA_RX51=y
CONFIG_VIDEO=y
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_BOOTDELAY=30
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_NSA310S=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_TEXT_BASE=0x81000000
CONFIG_SYS_CLK_FREQ=70000000
CONFIG_DEFAULT_DEVICE_TREE="nsim"
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_PROMPT="nsim# "
# CONFIG_CMD_IMLS is not set
CONFIG_SYS_TEXT_BASE=0x81000000
CONFIG_SYS_CLK_FREQ=70000000
CONFIG_DEFAULT_DEVICE_TREE="nsim"
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_PROMPT="nsim# "
# CONFIG_CMD_IMLS is not set
CONFIG_SYS_TEXT_BASE=0x81000000
CONFIG_SYS_CLK_FREQ=70000000
CONFIG_DEFAULT_DEVICE_TREE="nsim"
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_PROMPT="nsim# "
# CONFIG_CMD_IMLS is not set
CONFIG_SYS_TEXT_BASE=0x81000000
CONFIG_SYS_CLK_FREQ=70000000
CONFIG_DEFAULT_DEVICE_TREE="nsim"
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_PROMPT="nsim# "
# CONFIG_CMD_IMLS is not set
CONFIG_TEGRA124=y
CONFIG_TARGET_NYAN_BIG=y
CONFIG_DEFAULT_DEVICE_TREE="tegra124-nyan-big"
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_OF_SYSTEM_SETUP=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_BMP=y
-CONFIG_CMD_BOOTSTAGE=y
CONFIG_CMD_CACHE=y
+CONFIG_CMD_BOOTSTAGE=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_TPM=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_LIVE=y
CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_AS3722=y
CONFIG_DM_REGULATOR=y
+CONFIG_REGULATOR_AS3722=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_PWM_TEGRA=y
-CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0x70006000
CONFIG_DEBUG_UART_CLOCK=408000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_IDENT_STRING=" odroid-c2"
CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-odroidc2"
CONFIG_DEBUG_UART=y
+CONFIG_ENV_IS_NOWHERE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_DM_ETH=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_PROMPT="ODROID-XU3 # "
CONFIG_TARGET_OMAP3_BEAGLE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS0=y
CONFIG_LED_STATUS_BIT=1
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TARGET_OMAP3_EVM=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TARGET_TAO3530=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BOARD_OMAP3_HA"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_DEFAULT_DEVICE_TREE="logicpd-torpedo-37xx-devkit"
CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_OMAP3_OVERO=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TARGET_OMAP3_PANDORA=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TARGET_OMAP3_ZOOM1=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
CONFIG_MMC_OMAP_HS=y
CONFIG_TARGET_OMAP4_PANDA=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_ENV_IS_IN_FAT=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_BAT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC=16296
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_ARMV7_LPAE=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ISO_PARTITION=y
-CONFIG_SCSI=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_MMC_OMAP_HS=y
+CONFIG_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_TARGET_OPENRD=y
CONFIG_IDENT_STRING="\nOpenRD-Base"
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_BASE"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_IMLS is not set
CONFIG_TARGET_OPENRD=y
CONFIG_IDENT_STRING="\nOpenRD-Client"
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_CLIENT"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_IMLS is not set
CONFIG_TARGET_OPENRD=y
CONFIG_IDENT_STRING="\nOpenRD-Ultimate"
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_ULTIMATE"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_IMLS is not set
CONFIG_VIDEO=y
# CONFIG_CMD_BMODE is not set
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-opos6uldev"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=5
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_OT1200=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/bachmann/ot1200/mx6q_4x_mt41j128.cfg,MX6Q"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_DM=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_DM=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_LIVE=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_TARGET_PAZ00=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-paz00"
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra20 (Paz00) MOD # "
# CONFIG_CMD_IMI is not set
CONFIG_MIPS=y
CONFIG_TARGET_PB1X00=y
CONFIG_SYS_EXTRA_OPTIONS="PB1000"
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_SYS_PROMPT="Pb1x00 # "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_ELF is not set
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="REV1"
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="REV3"
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_ARCH_VF610=y
CONFIG_TARGET_PCM052=y
CONFIG_DEFAULT_DEVICE_TREE="pcm052"
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg,ENV_IS_IN_NAND"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SILENT_CONSOLE=y
CONFIG_SPL=y
CONFIG_SYS_PROMPT="Peach-Pi # "
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SILENT_CONSOLE=y
CONFIG_SPL=y
CONFIG_SYS_PROMPT="Peach-Pit # "
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_DIAG=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-phycore-rdk"
CONFIG_DEBUG_UART=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_MIPS_BOOT_FDT=y
CONFIG_DEFAULT_DEVICE_TREE="pic32mzda_sk"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_BOOTDELAY=5
CONFIG_SYS_PROMPT="dask # "
# CONFIG_CMD_IMLS is not set
CONFIG_TARGET_PICO_IMX6UL=y
# CONFIG_CMD_BMODE is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/technexion/pico-imx6ul/imximage.cfg"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-hobbit.dtb"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC"
+CONFIG_ENV_IS_IN_FAT=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6DL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6DL"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-plutux"
CONFIG_FIT=y
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra20 (Plutux) # "
CONFIG_ARCH_AT91=y
CONFIG_TARGET_PM9261=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_PM9263=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_PM9G45=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G45"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_KIRKWOOD=y
CONFIG_TARGET_POGO_E02=y
CONFIG_IDENT_STRING="\nPogo E02"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="PogoE02> "
CONFIG_TARGET_POPLAR=y
CONFIG_IDENT_STRING="poplar"
CONFIG_DEFAULT_DEVICE_TREE="hi3798cv200-poplar"
-CONFIG_SYS_PROMPT="poplar# "
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_DISPLAY_CPUINFO=n
-CONFIG_DISPLAY_BOARDINFO=y
-CONFIG_ISO_PARTITION=n
+CONFIG_ENV_IS_IN_MMC=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SYS_PROMPT="poplar# "
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_UNZIP=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_ISO_PARTITION is not set
CONFIG_MMC_DW=y
CONFIG_MMC_DW_K3=y
-CONFIG_PL011_SERIAL=y
-CONFIG_PSCI_RESET=y
CONFIG_USB=y
-CONFIG_USB_EHCI=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y
-CONFIG_NET=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_DM_GPIO is not set
CONFIG_LIB_RAND=y
-CONFIG_CMD_UNZIP=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-popmetal"
CONFIG_DEBUG_UART=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_PORTER=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_BOOTZ=y
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_IDENT_STRING="\nKeymile Port-L2"
CONFIG_SYS_EXTRA_OPTIONS="KM_PORTL2"
+CONFIG_ENV_IS_IN_EEPROM=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_PING=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_SOURCE="board/theobroma-systems/puma_rk3399/fit_spl_atf.its"
+CONFIG_ENV_IS_IN_MMC=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_VIDEO=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-pxm50"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_SYS_NS16550=y
CONFIG_TIMER=y
-CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_HUSH_PARSER=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
CONFIG_TIMER=y
-CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_HUSH_PARSER=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
CONFIG_TIMER=y
-CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_HUSH_PARSER=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
CONFIG_TIMER=y
-CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_SH=y
CONFIG_TARGET_R0P7734=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
# CONFIG_CMD_BDI is not set
CONFIG_SH=y
CONFIG_TARGET_R2DPLUS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=-1
CONFIG_CMD_IDE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SH=y
CONFIG_TARGET_R7780MP=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_SALVATOR_X=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_DEFAULT_FDT_FILE="r8a7795-salvator-x.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_BOOTZ=y
CONFIG_RCAR_GEN3=y
CONFIG_R8A7796=y
CONFIG_TARGET_SALVATOR_X=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_DEFAULT_FDT_FILE="r8a7796-salvator-x.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_BOOTZ=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_TARGET_EMBESTMX6BOARDS=y
CONFIG_VIDEO=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024,ENV_IS_IN_MMC"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024"
+CONFIG_ENV_IS_IN_MMC=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-rock2-square"
CONFIG_DEBUG_UART=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SILENT_CONSOLE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_ADDR=0x60080000
CONFIG_DEFAULT_DEVICE_TREE="rk3188-radxarock"
CONFIG_DEBUG_UART=y
+CONFIG_ENV_IS_IN_MMC=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_VIDEO=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-rut"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_MALLOC_F=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/s32v234evb/s32v234evb.cfg"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_CMD_BOOTZ=y
CONFIG_OF_LIBFDT=y
CONFIG_ARCH_S5PC1XX=y
CONFIG_TARGET_S5P_GONI=y
CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-goni"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Goni # "
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_NANDFLASH"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_SERIALFLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC"
+CONFIG_ENV_IS_IN_FAT=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_SERIALFLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
+CONFIG_ENV_IS_IN_FAT=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_SERIALFLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
+CONFIG_ENV_IS_IN_FAT=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
+CONFIG_ENV_IS_IN_FAT=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_SERIALFLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC"
+CONFIG_ENV_IS_IN_FAT=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC"
+CONFIG_ENV_IS_IN_FAT=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_BOOTSTAGE_STASH=y
CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_CONSOLE_RECORD=y
CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
CONFIG_SILENT_CONSOLE=y
CONFIG_BOOTSTAGE_STASH=y
CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_CONSOLE_RECORD=y
CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
CONFIG_SILENT_CONSOLE=y
CONFIG_BOOTSTAGE_STASH=y
CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_CONSOLE_RECORD=y
CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
CONFIG_SILENT_CONSOLE=y
CONFIG_BOOTSTAGE_STASH=y
CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_CONSOLE_RECORD=y
CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
CONFIG_SILENT_CONSOLE=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_VIDEO=y
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_TARGET_SEABOARD=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-seaboard"
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_PROMPT="Tegra20 (SeaBoard) # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
CONFIG_SECOMX6_UQ7=y
CONFIG_SECOMX6Q=y
CONFIG_SECOMX6_2GB=y
-CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_MMC"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SH=y
CONFIG_SH_32BIT=y
CONFIG_TARGET_SH7752EVB=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
# CONFIG_CMD_BDI is not set
CONFIG_SH=y
CONFIG_TARGET_SH7753EVB=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
# CONFIG_CMD_BDI is not set
CONFIG_SH=y
CONFIG_SH_32BIT=y
CONFIG_TARGET_SH7757LCR=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
# CONFIG_CMD_BDI is not set
CONFIG_SH=y
CONFIG_TARGET_SH7763RDP=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=-1
CONFIG_VERSION_VARIABLE=y
# CONFIG_CMD_BDI is not set
CONFIG_SH=y
CONFIG_SH_32BIT=y
CONFIG_TARGET_SH7785LCR=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
# CONFIG_CMD_BDI is not set
CONFIG_SH=y
CONFIG_TARGET_SH7785LCR=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
# CONFIG_CMD_BDI is not set
CONFIG_ROCKCHIP_RK3368=y
CONFIG_DEFAULT_DEVICE_TREE="rk3368-sheep"
CONFIG_DEBUG_UART=y
+CONFIG_ENV_IS_NOWHERE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_FASTBOOT=y
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_SHEEVAPLUG=y
CONFIG_IDENT_STRING="\nMarvell-Sheevaplug"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SILK=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_BOOTZ=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9260-smartweb"
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
# CONFIG_DOS_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
CONFIG_TARGET_SMDKC100=y
CONFIG_IDENT_STRING=" for SMDKC100"
CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-smdkc100"
+CONFIG_ENV_IS_IN_ONENAND=y
CONFIG_BOOTDELAY=3
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="SMDKC100 # "
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
# CONFIG_MMC is not set
CONFIG_TARGET_SNAPPER9260=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_TARGET_SNAPPER9260=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TARGET_SNIPER=y
# CONFIG_SPL_NAND_SUPPORT is not set
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SILENT_CONSOLE=y
CONFIG_SPL=y
CONFIG_SYS_PROMPT="snow # "
CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
CONFIG_IDENT_STRING="socfpga_arria10"
CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb"
CONFIG_SPL=y
+CONFIG_SPL_FPGA_SUPPORT=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_MMC=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
CONFIG_FIT=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_SYS_I2C_DW=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
CONFIG_FIT=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_SYS_I2C_DW=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de0_nano_soc"
CONFIG_FIT=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_CMD_UBI=y
CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_SYS_I2C_DW=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de10_nano"
CONFIG_FIT=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_SYS_I2C_DW=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de1_soc"
CONFIG_FIT=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
+CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_SYS_I2C_DW=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_is1"
CONFIG_FIT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_CMD_UBI=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_SYS_I2C_DW=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_mcvevk"
CONFIG_FIT=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_CMD_UBI=y
CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_SYS_I2C_DW=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit"
CONFIG_FIT=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_SYS_I2C_DW=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
CONFIG_FIT=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_SYS_I2C_DW=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
CONFIG_FIT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_CMD_UBI=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_SYS_I2C_DW=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_vining_fpga"
CONFIG_FIT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=5
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
+CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_LED_STATUS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=1
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
-CONFIG_SCSI=y
CONFIG_CPU=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_E1000=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
+CONFIG_SCSI=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_SYS_NS16550=y
CONFIG_ICH_SPI=y
CONFIG_TIMER=y
-CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_TARGET_SPEAR300=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR300"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_TARGET_SPEAR300=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR300,NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_TARGET_SPEAR300=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR300,USBTTY"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_TARGET_SPEAR300=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR300,USBTTY,NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_TARGET_SPEAR310=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR310"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_TARGET_SPEAR310=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR310,NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_TARGET_SPEAR310=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR310,FLASH_PNOR"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_TARGET_SPEAR310=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR310,USBTTY"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_TARGET_SPEAR310=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR310,USBTTY,NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_TARGET_SPEAR310=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR310,USBTTY,FLASH_PNOR"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_TARGET_SPEAR320=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR320"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_TARGET_SPEAR320=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR320,NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_TARGET_SPEAR320=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR320,FLASH_PNOR"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_TARGET_SPEAR320=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR320,USBTTY"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_TARGET_SPEAR320=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR320,USBTTY,NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_TARGET_SPEAR320=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR320,USBTTY,FLASH_PNOR"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_TARGET_SPEAR600=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR600"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_TARGET_SPEAR600=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR600,NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_TARGET_SPEAR600=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR600,USBTTY"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_TARGET_SPEAR600=y
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_SYS_EXTRA_OPTIONS="SPEAR600,USBTTY,NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SILENT_CONSOLE=y
CONFIG_SPL=y
CONFIG_SYS_PROMPT="spring # "
CONFIG_DEFAULT_DEVICE_TREE="stih410-b2260"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_ENV_IS_NOWHERE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_PROMPT="stih410-b2260 => "
# CONFIG_CMD_IMLS is not set
CONFIG_STM32=y
CONFIG_STM32F4=y
CONFIG_TARGET_STM32F429_DISCOVERY=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_STM32F7=y
CONFIG_TARGET_STM32F746_DISCO=y
CONFIG_DEFAULT_DEVICE_TREE="stm32f746-disco"
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_STOUT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="stv0991"
CONFIG_SYS_EXTRA_OPTIONS="STV0991"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_PING=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TARGET_TAO3530=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20-taurus"
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
+CONFIG_CMD_MTDPARTS=y
# CONFIG_DOS_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_SYS_CLK_FREQ=500000000
CONFIG_DEFAULT_DEVICE_TREE="abilis_tb100"
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_PROMPT="[tb100]:~# "
# CONFIG_CMD_IMLS is not set
CONFIG_VIDEO=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_FIT=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_PRE_CON_BUF_ADDR=0x7c000000
CONFIG_DEFAULT_DEVICE_TREE="tegra20-tec"
CONFIG_FIT=y
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra20 (TEC) # "
# CONFIG_CMD_IMI is not set
CONFIG_ENABLE_MRC_CACHE=y
CONFIG_SMP=y
CONFIG_HAVE_VGA_BIOS=y
+CONFIG_VGA_BIOS_ADDR=0xfffa0000
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_MP_TABLE=y
CONFIG_GENERATE_ACPI_TABLE=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_SYS_NS16550=y
CONFIG_ICH_SPI=y
CONFIG_TIMER=y
-CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_FPGA_ALTERA=y
CONFIG_DM_GPIO=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
# CONFIG_PARTITION_UUIDS is not set
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_FPGA_ALTERA=y
CONFIG_DM_GPIO=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_IDENT_STRING=" for Cavium Thunder CN88XX ARM v8 Multi-Core"
CONFIG_DEFAULT_DEVICE_TREE="thunderx-88xx"
CONFIG_DEBUG_UART=y
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_DEFAULT_DEVICE_TREE="dm8168-evm"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_MTDPARTS=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-tinker"
CONFIG_DEBUG_UART=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ARCH_MX6=y
CONFIG_TARGET_TITANIUM=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/barco/titanium/imximage.cfg"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miami/ps7_regs.txt"
CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miami"
CONFIG_DEBUG_UART=y
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_BOOTDELAY=0
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt"
CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamilite"
CONFIG_DEBUG_UART=y
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_BOOTDELAY=0
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt"
CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamiplus"
CONFIG_DEBUG_UART=y
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_BOOTDELAY=0
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_ARCH_ATH79=y
CONFIG_BOARD_TPLINK_WDR4300=y
CONFIG_DEFAULT_DEVICE_TREE="tplink_wdr4300"
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="imx6dl-mba6x.dtb"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="imx6dl-mba6x.dtb"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="imx6q-mba6x.dtb"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="imx6q-mba6x.dtb"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="imx6dl-mba6x.dtb"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="imx6dl-mba6x.dtb"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="imx6s-wru4.dtb"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TARGET_TRICORDER=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=0
CONFIG_SILENT_CONSOLE=y
CONFIG_SPL=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TARGET_TRICORDER=y
CONFIG_SYS_EXTRA_OPTIONS="FLASHCARD"
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_BOOTDELAY=0
CONFIG_SILENT_CONSOLE=y
CONFIG_SPL=y
CONFIG_TARGET_TRIMSLICE=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-trimslice"
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra20 (TrimSlice) # "
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_MMC"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_ARCH_MX5=y
CONFIG_TARGET_TS4800=y
# CONFIG_CMD_BMODE is not set
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=1
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_PING=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_TURRIS_OMNIA=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="armada-385-turris-omnia"
+CONFIG_DEBUG_UART=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+# CONFIG_SPL_PARTITION_UUIDS is not set
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_MISC=y
+CONFIG_ATSHA204A=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_MV=y
+CONFIG_DEBUG_UART_BASE=0xd0012000
+CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_WDT=y
+CONFIG_WDT_ORION=y
CONFIG_CMD_PING=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TARGET_TWISTER=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
# CONFIG_CMD_BMODE is not set
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_SPL_ENV_SUPPORT=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_UNIPHIER=y
-CONFIG_SYS_TEXT_BASE=0x84000000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_ARCH_UNIPHIER_LD11_SINGLE=y
-CONFIG_MICRO_SUPPORT_CARD=y
-CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld11-ref"
-# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
-CONFIG_SPL=y
-CONFIG_SPL_NOR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_CONFIG=y
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-CONFIG_CMD_GPT=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-# CONFIG_CMD_MISC is not set
-CONFIG_CMD_FAT=y
-# CONFIG_SPL_DOS_PARTITION is not set
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_GPIO_UNIPHIER=y
-CONFIG_MISC=y
-CONFIG_I2C_EEPROM=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_SDMA=y
-CONFIG_MMC_SDHCI_CADENCE=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_GENERIC=y
-CONFIG_USB_STORAGE=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_UNIPHIER=y
-CONFIG_SYS_TEXT_BASE=0x84000000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_ARCH_UNIPHIER_LD20_SINGLE=y
-CONFIG_MICRO_SUPPORT_CARD=y
-CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld20-ref"
-# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
-CONFIG_SPL=y
-CONFIG_SPL_NOR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_CONFIG=y
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-CONFIG_CMD_GPT=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-# CONFIG_CMD_MISC is not set
-CONFIG_CMD_FAT=y
-# CONFIG_SPL_DOS_PARTITION is not set
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_GPIO_UNIPHIER=y
-CONFIG_MISC=y
-CONFIG_I2C_EEPROM=y
-CONFIG_MMC_UNIPHIER=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_CADENCE=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_STORAGE=y
CONFIG_CMD_TIME=y
# CONFIG_CMD_MISC is not set
CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CMD_TIME=y
# CONFIG_CMD_MISC is not set
CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CMD_TIME=y
# CONFIG_CMD_MISC is not set
CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CMD_TIME=y
# CONFIG_CMD_MISC is not set
CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CMD_TIME=y
# CONFIG_CMD_MISC is not set
CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_GPIO_UNIPHIER=y
CONFIG_MISC=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_USB_A9263=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
+CONFIG_ENV_IS_IN_DATAFLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_TARGET_USBARMORY=y
# CONFIG_CMD_BMODE is not set
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_ENV_IS_IN_MMC=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
CONFIG_MIPS=y
CONFIG_TARGET_VCT=y
CONFIG_VCT_PLATINUM=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=5
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SYS_PROMPT="$ "
CONFIG_TARGET_VCT=y
CONFIG_VCT_PLATINUM=y
CONFIG_VCT_ONENAND=y
+CONFIG_ENV_IS_IN_ONENAND=y
CONFIG_BOOTDELAY=5
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SYS_PROMPT="$ "
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_VCT_PLATINUM=y
CONFIG_VCT_ONENAND=y
CONFIG_VCT_SMALL_IMAGE=y
+CONFIG_ENV_IS_IN_ONENAND=y
CONFIG_BOOTDELAY=5
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SYS_PROMPT="$ "
# CONFIG_CMD_MISC is not set
CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_SYS_NS16550=y
CONFIG_TARGET_VCT=y
CONFIG_VCT_PLATINUM=y
CONFIG_VCT_SMALL_IMAGE=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=5
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SYS_PROMPT="$ "
CONFIG_MIPS=y
CONFIG_TARGET_VCT=y
CONFIG_VCT_PLATINUMAVC=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=5
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SYS_PROMPT="VCT# "
CONFIG_TARGET_VCT=y
CONFIG_VCT_PLATINUMAVC=y
CONFIG_VCT_ONENAND=y
+CONFIG_ENV_IS_IN_ONENAND=y
CONFIG_BOOTDELAY=5
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SYS_PROMPT="$ "
# CONFIG_CMD_NFS is not set
CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_SYS_NS16550=y
CONFIG_VCT_PLATINUMAVC=y
CONFIG_VCT_ONENAND=y
CONFIG_VCT_SMALL_IMAGE=y
+CONFIG_ENV_IS_IN_ONENAND=y
CONFIG_BOOTDELAY=5
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SYS_PROMPT="$ "
# CONFIG_CMD_MISC is not set
CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_SYS_NS16550=y
CONFIG_TARGET_VCT=y
CONFIG_VCT_PLATINUMAVC=y
CONFIG_VCT_SMALL_IMAGE=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=5
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SYS_PROMPT="$ "
CONFIG_MIPS=y
CONFIG_TARGET_VCT=y
CONFIG_VCT_PREMIUM=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=5
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SYS_PROMPT="$ "
CONFIG_TARGET_VCT=y
CONFIG_VCT_PREMIUM=y
CONFIG_VCT_ONENAND=y
+CONFIG_ENV_IS_IN_ONENAND=y
CONFIG_BOOTDELAY=5
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SYS_PROMPT="$ "
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_VCT_PREMIUM=y
CONFIG_VCT_ONENAND=y
CONFIG_VCT_SMALL_IMAGE=y
+CONFIG_ENV_IS_IN_ONENAND=y
CONFIG_BOOTDELAY=5
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SYS_PROMPT="$ "
# CONFIG_CMD_MISC is not set
CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_SYS_NS16550=y
CONFIG_TARGET_VCT=y
CONFIG_VCT_PREMIUM=y
CONFIG_VCT_SMALL_IMAGE=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=5
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SYS_PROMPT="$ "
CONFIG_TARGET_VE8313=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=6
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_TARGET_VENTANA=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-ventana"
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_PROMPT="Tegra20 (Ventana) # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_IDENT_STRING=" vexpress_aemv8a"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_IDENT_STRING=" vexpress_aemv8a"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_IDENT_STRING=" vexpress_aemv8a"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_TARGET_VEXPRESS_CA15_TC2=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_ENV_IS_IN_FLASH=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_CONSOLE is not set
CONFIG_ARM=y
CONFIG_TARGET_VEXPRESS_CA5X2=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_ENV_IS_IN_FLASH=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_CONSOLE is not set
CONFIG_ARM=y
CONFIG_TARGET_VEXPRESS_CA9X4=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_ENV_IS_IN_FLASH=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_CONSOLE is not set
CONFIG_ARM=y
CONFIG_ARCH_VF610=y
CONFIG_DEFAULT_DEVICE_TREE="vf610-twr"
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg,ENV_IS_IN_MMC"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_ARM=y
CONFIG_ARCH_VF610=y
CONFIG_DEFAULT_DEVICE_TREE="vf610-twr"
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg,ENV_IS_IN_NAND"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg"
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_VINCO=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_TARGET_VME8349=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=6
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
CONFIG_VIDEO=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
+CONFIG_ENV_IS_IN_MMC=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_TARGET_WARP=y
# CONFIG_CMD_BMODE is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp/imximage.cfg,MX6SL"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DFU=y
CONFIG_ARM=y
CONFIG_TARGET_WOODBURN=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/woodburn/imximage.cfg"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_CMD_HD44760=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_IDENT_STRING="-SPEAr"
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_VIDEO=y
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_ENV_IS_IN_FAT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_ENV_IS_IN_FAT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_ENV_IS_NOWHERE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_ENV_IS_IN_FAT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_ENV_IS_IN_FAT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_ENV_IS_IN_FAT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_ENV_IS_IN_FAT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_XPRESS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ccv/xpress/imximage.cfg"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_XTENSA=y
CONFIG_SYS_CPU="dc233c"
CONFIG_XTFPGA_KC705=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=10
CONFIG_VERSION_VARIABLE=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="imx6q-zc5202.dtb"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="imx6q-zc5601.dtb"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_ARM=y
CONFIG_TARGET_ZIPITZ2=y
+CONFIG_ENV_IS_IN_FLASH=y
# CONFIG_CONSOLE_MUX is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_ARM=y
CONFIG_TARGET_ZMX25=y
+CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
+CONFIG_LZO=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_OS_BOOT=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_DEFAULT_DEVICE_TREE="zynq-picozed"
+CONFIG_ENV_IS_NOWHERE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_OS_BOOT=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_OS_BOOT=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_OS_BOOT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_OS_BOOT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM011"
+CONFIG_ENV_IS_NOWHERE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_OS_BOOT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012"
+CONFIG_ENV_IS_IN_FLASH=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_OS_BOOT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013"
+CONFIG_ENV_IS_NOWHERE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_OS_BOOT=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_OS_BOOT=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_OS_BOOT=y
- CONFIG_SYS_FSL_ESDHC_BE
ESDHC IP is in big-endian mode. Accessing ESDHC registers can be determined
by ESDHC IP's endian mode or processor's endian mode.
-
- - CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT forces to run at 1.8V.
value shall be set to one of the
values found in the file:
arch/arm/include/asm/\
- imx-common/imximage.cfg
+ mach-imx/imximage.cfg
Example:
BOOT_OFFSET FLASH_OFFSET_STANDARD
--- /dev/null
+Marvell U-Boot Build Instructions
+=================================
+
+This document describes how to compile the U-Boot and how to change U-Boot configuration
+
+Build Procedure
+----------------
+1. Install required packages:
+
+ # sudo apt-get install libssl-dev
+ # sudo apt-get install device-tree-compiler
+ # sudo apt-get install swig libpython-dev
+
+2. Set the cross compiler:
+
+ # export CROSS_COMPILE=/path/to/toolchain/aarch64-marvell-linux-gnu-
+
+3. Clean-up old residuals:
+
+ # make mrproper
+
+4. Configure the U-Boot:
+
+ # make <defconfig_file>
+
+ - For the Armada-70x0/80x0 DB board use "mvebu_db_armada8k_defconfig"
+ - For the Armada-80x0 MacchiatoBin use "make mvebu_mcbin-88f8040_defconfig"
+ - For the Armada-3700 DB board use "make mvebu_db-88f3720_defconfig"
+ - For the Armada-3700 EsspressoBin use "make mvebu_espressobin-88f3720_defconfig"
+
+5. Configure the device-tree and build the U-Boot image:
+
+ Compile u-boot and set the required device-tree using:
+
+ # make DEVICE_TREE=<name>
+
+ NOTE:
+ Compilation with "mvebu_db_armada8k_defconfig" requires explicitly exporting DEVICE_TREE
+ for the requested board.
+ By default, u-boot is compiled with armada-8040-db device-tree.
+ Using A80x0 device-tree on A70x0 might break the device.
+ In order to prevent this, the required device-tree MUST be set during compilation.
+ All device-tree files are located in ./arch/arm/dts/ folder.
+
+ NOTE:
+ The u-boot.bin should not be used as a stand-alone image.
+ The ARM Trusted Firmware (ATF) build process uses this image to generate the
+ flash image.
+
+Configuration update
+---------------------
+ To update the U-Boot configuration, please refer to doc/README.kconfig
+
Recommended toolchains
----------------------
-The UniPhir platform is well tested with Linaro toolchanis.
+The UniPhier platform is well tested with Linaro toolchains.
You can download pre-built toolchains from:
http://www.linaro.org/downloads/
Compile the source
------------------
-sLD3 reference board:
- $ make uniphier_sld3_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabihf-
+The source can be configured and built with the following commands:
-LD4 reference board:
- $ make uniphier_ld4_sld8_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabihf-
+ $ make <defconfig>
+ $ make CROSS_COMPILE=<toolchain-prefix> DEVICE_TREE=<device-tree>
-sLD8 reference board:
- $ make uniphier_ld4_sld8_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-sld8-ref
+The recommended <toolchain-prefix> is `arm-linux-gnueabihf-` for 32bit SoCs,
+`aarch64-linux-gnu-` for 64bit SoCs, but you may wish to change it to use your
+favorite compiler.
-Pro4 reference board:
- $ make uniphier_pro4_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabihf-
+The following tables show <defconfig> and <device-tree> for each board.
-Pro4 Ace board:
- $ make uniphier_pro4_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pro4-ace
+32bit SoC boards:
-Pro4 Sanji board:
- $ make uniphier_pro4_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pro4-sanji
+ Board | <defconfig> | <device-tree>
+---------------|------------------------------|------------------------------
+sLD3 reference | uniphier_sld3_defconfig | uniphier-sld3-ref (default)
+LD4 reference | uniphier_ld4_sld8_defconfig | uniphier-ld4-ref (default)
+sld8 reference | uniphier_ld4_sld8_defconfig | uniphier-sld8-def
+Pro4 reference | uniphier_pro4_defconfig | uniphier-pro4-ref (default)
+Pro4 Ace | uniphier_pro4_defconfig | uniphier-pro4-ace
+Pro4 Sanji | uniphier_pro4_defconfig | uniphier-pro4-sanji
+Pro5 4KBOX | uniphier_pxs2_ld6b_defconfig | uniphier-pro5-4kbox
+PXs2 Gentil | uniphier_pxs2_ld6b_defconfig | uniphier-pxs2-gentil
+PXs2 Vodka | uniphier_pxs2_ld6b_defconfig | uniphier-pxs2-vodka (default)
+LD6b reference | uniphier_pxs2_ld6b_defconfig | uniphier-ld6b-ref
-Pro5 4KBOX Board:
- $ make uniphier_pxs2_ld6b_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pro5-4kbox
+64bit SoC boards:
-PXs2 Gentil board:
- $ make uniphier_pxs2_ld6b_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pxs2-gentil
+ Board | <defconfig> | <device-tree>
+---------------|-----------------------|----------------------------
+LD11 reference | uniphier_v8_defconfig | uniphier-ld11-ref
+LD11 Global | uniphier_v8_defconfig | uniphier-ld11-global
+LD20 reference | uniphier_v8_defconfig | uniphier-ld20-ref (default)
+LD20 Global | uniphier_v8_defconfig | uniphier-ld20-global
-PXs2 Vodka board:
- $ make uniphier_pxs2_ld6b_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabihf-
+For example, to compile the source for PXs2 Vodka board, run the following:
-LD6b reference board:
$ make uniphier_pxs2_ld6b_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-ld6b-ref
+ $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pxs2-vodka
-LD11 reference board:
- $ make uniphier_ld11_defconfig
- $ make CROSS_COMPILE=aarch64-linux-gnu-
+The device tree marked as (default) can be omitted. `uniphier-pxs2-vodka` is
+the default device tree for the configuration `uniphier_pxs2_ld6b_defconfig`,
+so the following gives the same result.
-LD20 reference board:
- $ make uniphier_ld20_defconfig
- $ make CROSS_COMPILE=aarch64-linux-gnu-
-
-PXs3 reference board:
- $ make uniphier_v8_defconfig
- $ make CROSS_COMPILE=aarch64-linux-gnu- DEVICE_TREE=uniphier-pxs3-ref
+ $ make uniphier_pxs2_ld6b_defconfig
+ $ make CROSS_COMPILE=arm-linux-gnueabihf-
-You may wish to change the "CROSS_COMPILE=..." to use your favorite compiler.
+Booting 32bit SoC boards
+------------------------
-Burn U-Boot images to NAND
---------------------------
+The build command will generate the following:
+- u-boot.bin
+- spl/u-boot.bin
-Write the following to the NAND device:
+U-Boot can boot UniPhier 32bit SoC boards by itself. Flash the generated images
+to the storage device (NAND or eMMC) on your board.
- spl/u-boot-spl.bin at the offset address 0x00000000
- u-boot.bin at the offset address 0x00020000
-or
+The `u-boot-with-spl.bin` is the concatenation of the two (with appropriate
+padding), so you can also do:
- u-boot-with-spl.bin at the offset address 0x00000000
If a TFTP server is available, the images can be easily updated.
Just copy the u-boot-spl.bin and u-boot.bin to the TFTP public directory,
-and then run the following command at the U-Boot command line:
+and run the following command at the U-Boot command line:
- => run nandupdate
+To update the images in NAND:
+ => run nandupdate
-Burn U-Boot images to eMMC
---------------------------
+To update the images in eMMC:
-Write the following to the Boot partition 1 of the eMMC device:
+ => run emmcupdate
- - spl/u-boot-spl.bin at the offset address 0x00000000
- - u-boot.bin at the offset address 0x00020000
-or
+Booting 64bit SoC boards
+------------------------
- - u-boot-with-spl.bin at the offset address 0x00000000
+The build command will generate the following:
+- u-boot.bin
-If a TFTP server is available, the images can be easily updated.
-Just copy the u-boot-spl.bin and u-boot.bin to the TFTP public directory,
-and then run the following command at the U-Boot command line:
+However, U-Boot is not the first stage loader for UniPhier 64bit SoC boards.
+U-Boot serves as a non-secure boot loader loaded by [ARM Trusted Firmware],
+so you need to provide the `u-boot.bin` to the build command of ARM Trusted
+Firmware.
- => run emmcupdate
+[ARM Trusted Firmware]: https://github.com/ARM-software/arm-trusted-firmware
UniPhier specific commands
--
Masahiro Yamada <yamada.masahiro@socionext.com>
-Jan. 2017
+Jul. 2017
work with minimal adjustments on other x86 boards since coreboot deals with
most of the low-level details.
+U-Boot is a main bootloader on Intel Edison board.
+
U-Boot also supports booting directly from x86 reset vector, without coreboot.
In this case, known as bare mode, from the fact that it runs on the
'bare metal', U-Boot acts like a BIOS replacement. The following platforms
to point to a new board. You can also change the Cache-As-RAM (CAR) related
settings here if the default values do not fit your new board.
+Build Instructions for U-Boot as main bootloader
+------------------------------------------------
+
+Intel Edison instructions:
+
+Simple you can build U-Boot and obtain u-boot.bin
+
+$ make edison_defconfig
+$ make all
+
Build Instructions for U-Boot as BIOS replacement (bare mode)
-------------------------------------------------------------
Building a ROM version of U-Boot (hereafter referred to as u-boot.rom) is a
=> zboot 01000000 - 04000000 1b1ab50
+Updating U-Boot on Edison
+-------------------------
+By default Intel Edison boards are shipped with preinstalled heavily
+patched U-Boot v2014.04. Though it supports DFU which we may be able to
+use.
+
+1. Prepare u-boot.bin as described in chapter above. You still need one
+more step (if and only if you have original U-Boot), i.e. run the
+following command:
+
+$ truncate -s %4096 u-boot.bin
+
+2. Run your board and interrupt booting to U-Boot console. In the console
+call:
+
+ => run do_force_flash_os
+
+3. Wait for few seconds, it will prepare environment variable and runs
+DFU. Run DFU command from the host system:
+
+$ dfu-util -v -d 8087:0a99 --alt u-boot0 -D u-boot.bin
+
+4. Return to U-Boot console and following hint. i.e. push Ctrl+C, and
+reset the board:
+
+ => reset
+
CPU Microcode
-------------
Modern CPUs usually require a special bit stream called microcode [8] to be
pinctrl-names = "default";
status = "okay";
- mr-nbanks = <1>;
/* sdram memory configuration from sdram datasheet */
- bank1: bank@0 {
- st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2
+ bank1: bank@0 {
+ st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2
CAS_3 RD_BURST_EN RD_PIPE_DL_0>;
- st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
+ st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
TRCD_18>;
- };
-}
+ };
+
+ /* sdram memory configuration from sdram datasheet */
+ bank2: bank@1 {
+ st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2
+ CAS_3 RD_BURST_EN RD_PIPE_DL_0>;
+ st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
+ TRCD_18>;
+ };
+ }
Mandatory properties:
- description : Textual description of the component sub-image
- type : Name of component sub-image type, supported types are:
- "standalone", "kernel", "ramdisk", "firmware", "script", "filesystem",
- "flat_dt" and others (see uimage_type in common/image.c).
+ "standalone", "kernel", "kernel_noload", "ramdisk", "firmware", "script",
+ "filesystem", "flat_dt" and others (see uimage_type in common/image.c).
- data : Path to the external file which contains this node's binary data.
- compression : Compression used by included data. Supported compressions
are "gzip" and "bzip2". If no compression is used compression property
obj-$(CONFIG_SPL_SATA_SUPPORT) += ata/ scsi/
obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/
obj-$(CONFIG_SPL_MMC_SUPPORT) += block/
+obj-$(CONFIG_SPL_FPGA_SUPPORT) += fpga/
endif
ifdef CONFIG_TPL_BUILD
ret = ahci_start_ports(uc_priv);
if (ret)
return ret;
-
- debug("Scanning %s\n", dev->name);
- ret = scsi_scan_dev(dev, true);
- if (ret)
- return ret;
#endif
return 0;
debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
assert(clk);
+ clk->dev = NULL;
+
ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
index, &args);
if (ret) {
int index;
debug("%s(dev=%p, name=%s, clk=%p)\n", __func__, dev, name, clk);
+ clk->dev = NULL;
index = dev_read_stringlist_search(dev, "clock-names", name);
if (index < 0) {
return clk_get_by_index(dev, index, clk);
}
+
+int clk_release_all(struct clk *clk, int count)
+{
+ int i, ret;
+
+ for (i = 0; i < count; i++) {
+ debug("%s(clk[%d]=%p)\n", __func__, i, &clk[i]);
+
+ /* check if clock has been previously requested */
+ if (!clk[i].dev)
+ continue;
+
+ ret = clk_disable(&clk[i]);
+ if (ret && ret != -ENOSYS)
+ return ret;
+
+ ret = clk_free(&clk[i]);
+ if (ret && ret != -ENOSYS)
+ return ret;
+ }
+
+ return 0;
+}
+
#endif /* OF_CONTROL */
int clk_request(struct udevice *dev, struct clk *clk)
#include <asm/arch/stm32.h>
#include <asm/arch/stm32_periph.h>
+#include <dt-bindings/mfd/stm32f7-rcc.h>
+
#define RCC_CR_HSION BIT(0)
#define RCC_CR_HSEON BIT(16)
#define RCC_CR_HSERDY BIT(17)
#define APB_PSC_8 0x6
#define APB_PSC_16 0x7
+struct stm32_clk {
+ struct stm32_rcc_regs *base;
+};
+
#if !defined(CONFIG_STM32_HSE_HZ)
#error "CONFIG_STM32_HSE_HZ not defined!"
#else
#endif
#endif
-int configure_clocks(void)
+static int configure_clocks(struct udevice *dev)
{
+ struct stm32_clk *priv = dev_get_priv(dev);
+ struct stm32_rcc_regs *regs = priv->base;
+
/* Reset RCC configuration */
- setbits_le32(&STM32_RCC->cr, RCC_CR_HSION);
- writel(0, &STM32_RCC->cfgr); /* Reset CFGR */
- clrbits_le32(&STM32_RCC->cr, (RCC_CR_HSEON | RCC_CR_CSSON
+ setbits_le32(®s->cr, RCC_CR_HSION);
+ writel(0, ®s->cfgr); /* Reset CFGR */
+ clrbits_le32(®s->cr, (RCC_CR_HSEON | RCC_CR_CSSON
| RCC_CR_PLLON));
- writel(0x24003010, &STM32_RCC->pllcfgr); /* Reset value from RM */
- clrbits_le32(&STM32_RCC->cr, RCC_CR_HSEBYP);
- writel(0, &STM32_RCC->cir); /* Disable all interrupts */
+ writel(0x24003010, ®s->pllcfgr); /* Reset value from RM */
+ clrbits_le32(®s->cr, RCC_CR_HSEBYP);
+ writel(0, ®s->cir); /* Disable all interrupts */
/* Configure for HSE+PLL operation */
- setbits_le32(&STM32_RCC->cr, RCC_CR_HSEON);
- while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY))
+ setbits_le32(®s->cr, RCC_CR_HSEON);
+ while (!(readl(®s->cr) & RCC_CR_HSERDY))
;
- setbits_le32(&STM32_RCC->cfgr, ((
+ setbits_le32(®s->cfgr, ((
sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT)
| (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
| (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
pllcfgr |= sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT;
pllcfgr |= ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT;
pllcfgr |= sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT;
- writel(pllcfgr, &STM32_RCC->pllcfgr);
+ writel(pllcfgr, ®s->pllcfgr);
/* Enable the main PLL */
- setbits_le32(&STM32_RCC->cr, RCC_CR_PLLON);
- while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY))
+ setbits_le32(®s->cr, RCC_CR_PLLON);
+ while (!(readl(®s->cr) & RCC_CR_PLLRDY))
;
/* Enable high performance mode, System frequency up to 200 MHz */
- setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN);
+ setbits_le32(®s->apb1enr, RCC_APB1ENR_PWREN);
setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODEN);
/* Infinite wait! */
while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODRDY))
;
stm32_flash_latency_cfg(5);
- clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
- setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL);
+ clrbits_le32(®s->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
+ setbits_le32(®s->cfgr, RCC_CFGR_SW_PLL);
- while ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) !=
+ while ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) !=
RCC_CFGR_SWS_PLL)
;
return 0;
}
-unsigned long clock_get(enum clock clck)
+static unsigned long stm32_clk_get_rate(struct clk *clk)
{
+ struct stm32_clk *priv = dev_get_priv(clk->dev);
+ struct stm32_rcc_regs *regs = priv->base;
u32 sysclk = 0;
u32 shift = 0;
/* Prescaler table lookups for clock computation */
0, 0, 0, 0, 1, 2, 3, 4
};
- if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) ==
+ if ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) ==
RCC_CFGR_SWS_PLL) {
u16 pllm, plln, pllp;
- pllm = (readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
- plln = ((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
+ pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
+ plln = ((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
>> RCC_PLLCFGR_PLLN_SHIFT);
- pllp = ((((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
+ pllp = ((((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
>> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp;
+ } else {
+ return -EINVAL;
}
- switch (clck) {
- case CLOCK_CORE:
- return sysclk;
- break;
- case CLOCK_AHB:
+ switch (clk->id) {
+ /*
+ * AHB CLOCK: 3 x 32 bits consecutive registers are used :
+ * AHB1, AHB2 and AHB3
+ */
+ case STM32F7_AHB1_CLOCK(GPIOA) ... STM32F7_AHB3_CLOCK(QSPI):
shift = ahb_psc_table[(
- (readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK)
+ (readl(®s->cfgr) & RCC_CFGR_AHB_PSC_MASK)
>> RCC_CFGR_HPRE_SHIFT)];
return sysclk >>= shift;
break;
- case CLOCK_APB1:
+ /* APB1 CLOCK */
+ case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8):
shift = apb_psc_table[(
- (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK)
+ (readl(®s->cfgr) & RCC_CFGR_APB1_PSC_MASK)
>> RCC_CFGR_PPRE1_SHIFT)];
return sysclk >>= shift;
break;
- case CLOCK_APB2:
+ /* APB2 CLOCK */
+ case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(LTDC):
shift = apb_psc_table[(
- (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK)
+ (readl(®s->cfgr) & RCC_CFGR_APB2_PSC_MASK)
>> RCC_CFGR_PPRE2_SHIFT)];
return sysclk >>= shift;
break;
default:
- return 0;
+ error("clock index %ld out of range\n", clk->id);
+ return -EINVAL;
break;
}
}
static int stm32_clk_enable(struct clk *clk)
{
+ struct stm32_clk *priv = dev_get_priv(clk->dev);
+ struct stm32_rcc_regs *regs = priv->base;
u32 offset = clk->id / 32;
u32 bit_index = clk->id % 32;
debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n",
__func__, clk->id, offset, bit_index);
- setbits_le32(&STM32_RCC->ahb1enr + offset, BIT(bit_index));
+ setbits_le32(®s->ahb1enr + offset, BIT(bit_index));
return 0;
}
static int stm32_clk_probe(struct udevice *dev)
{
debug("%s: stm32_clk_probe\n", __func__);
- configure_clocks();
+
+ struct stm32_clk *priv = dev_get_priv(dev);
+ fdt_addr_t addr;
+
+ addr = devfdt_get_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->base = (struct stm32_rcc_regs *)addr;
+
+ configure_clocks(dev);
return 0;
}
static struct clk_ops stm32_clk_ops = {
.of_xlate = stm32_clk_of_xlate,
.enable = stm32_clk_enable,
+ .get_rate = stm32_clk_get_rate,
};
static const struct udevice_id stm32_clk_ids[] = {
.name = "rockchip_rk3368_cru",
.id = UCLASS_CLK,
.of_match = rk3368_clk_ids,
- .priv_auto_alloc_size = sizeof(struct rk3368_cru),
+ .priv_auto_alloc_size = sizeof(struct rk3368_clk_priv),
.ofdata_to_platdata = rk3368_clk_ofdata_to_platdata,
.ops = &rk3368_clk_ops,
.bind = rk3368_clk_bind,
suitable malloc() implementation. If you are not using the
full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START,
consider using CONFIG_SYS_MALLOC_SIMPLE. In that case you
- must provide CONFIG_SYS_MALLOC_F_LEN to set the size.
+ must provide CONFIG_SPL_SYS_MALLOC_F_LEN to set the size.
In most cases driver model will only allocate a few uclasses
and devices in SPL, so 1KB should be enable. See
- CONFIG_SYS_MALLOC_F_LEN for more details on how to enable it.
+ CONFIG_SPL_SYS_MALLOC_F_LEN for more details on how to enable it.
config TPL_DM
bool "Enable Driver Model for TPL"
suitable malloc() implementation. If you are not using the
full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START,
consider using CONFIG_SYS_MALLOC_SIMPLE. In that case you
- must provide CONFIG_SYS_MALLOC_F_LEN to set the size.
+ must provide CONFIG_SPL_SYS_MALLOC_F_LEN to set the size.
In most cases driver model will only allocate a few uclasses
and devices in SPL, so 1KB should be enough. See
- CONFIG_SYS_MALLOC_F_LEN for more details on how to enable it.
+ CONFIG_SPL_SYS_MALLOC_F_LEN for more details on how to enable it.
Disable this for very small implementations.
config DM_WARN
index, out_args);
}
+int of_count_phandle_with_args(const struct device_node *np,
+ const char *list_name, const char *cells_name)
+{
+ return __of_parse_phandle_with_args(np, list_name, cells_name, 0,
+ -1, NULL);
+}
+
static void of_alias_add(struct alias_prop *ap, struct device_node *np,
int id, const char *stem, int stem_len)
{
#include <dm/of_addr.h>
#include <dm/ofnode.h>
#include <linux/err.h>
+#include <linux/ioport.h>
int ofnode_read_u32(ofnode node, const char *propname, u32 *outp)
{
const __be32 *prop_val;
uint flags;
u64 size;
+ int na;
- prop_val = of_get_address(
- (struct device_node *)ofnode_to_np(node), index,
- &size, &flags);
+ prop_val = of_get_address(ofnode_to_np(node), index, &size,
+ &flags);
if (!prop_val)
return FDT_ADDR_T_NONE;
- return be32_to_cpup(prop_val);
+ na = of_n_addr_cells(ofnode_to_np(node));
+ return of_read_number(prop_val, na);
} else {
return fdt_get_base_address(gd->fdt_blob,
ofnode_to_offset(node));
return 0;
}
+int ofnode_count_phandle_with_args(ofnode node, const char *list_name,
+ const char *cells_name)
+{
+ if (ofnode_is_np(node))
+ return of_count_phandle_with_args(ofnode_to_np(node),
+ list_name, cells_name);
+ else
+ return fdtdec_parse_phandle_with_args(gd->fdt_blob,
+ ofnode_to_offset(node), list_name, cells_name,
+ 0, -1, NULL);
+}
+
ofnode ofnode_path(const char *path)
{
if (of_live_active())
return false;
}
+
+int ofnode_read_resource(ofnode node, uint index, struct resource *res)
+{
+ if (ofnode_is_np(node)) {
+ return of_address_to_resource(ofnode_to_np(node), index, res);
+ } else {
+ struct fdt_resource fres;
+ int ret;
+
+ ret = fdt_get_resource(gd->fdt_blob, ofnode_to_offset(node),
+ "reg", index, &fres);
+ if (ret < 0)
+ return -EINVAL;
+ memset(res, '\0', sizeof(*res));
+ res->start = fres.start;
+ res->end = fres.end;
+
+ return 0;
+ }
+}
return fdt_get_phandle(gd->fdt_blob, ofnode_to_offset(node));
}
-const u32 *dev_read_prop(struct udevice *dev, const char *propname, int *lenp)
+const void *dev_read_prop(struct udevice *dev, const char *propname, int *lenp)
{
return ofnode_get_property(dev_ofnode(dev), propname, lenp);
}
return fdtdec_get_is_enabled(gd->fdt_blob,
ofnode_to_offset(node));
}
+
+int dev_read_resource(struct udevice *dev, uint index, struct resource *res)
+{
+ return ofnode_read_resource(dev_ofnode(dev), index, res);
+}
#include <dm/read.h>
#include <linux/ioport.h>
-int dev_read_resource(struct udevice *dev, uint index, struct resource *res)
-{
- ofnode node = dev_ofnode(dev);
-
-#ifdef CONFIG_OF_LIVE
- if (ofnode_is_np(node)) {
- return of_address_to_resource(ofnode_to_np(node), index, res);
- } else
-#endif
- {
- struct fdt_resource fres;
- int ret;
-
- ret = fdt_get_resource(gd->fdt_blob, ofnode_to_offset(node),
- "reg", index, &fres);
- if (ret < 0)
- return -EINVAL;
- memset(res, '\0', sizeof(*res));
- res->start = fres.start;
- res->end = fres.end;
-
- return 0;
- }
-}
+/* This file can hold non-inlined dev_read_...() functions */
enum hws_speed_bin speed_bin_index = SPEED_BIN_DDR_2133N;
enum hws_mem_size memory_size = MEM_2G;
enum hws_ddr_freq freq = init_freq;
+ enum hws_timing timing;
u32 cs_mask = 0;
u32 cl_value = 0, cwl_val = 0;
u32 refresh_interval_cnt = 0, bus_cnt = 0, adll_tap = 0;
DUNIT_CONTROL_HIGH_REG,
(init_cntr_prm->msys_init << 7), (1 << 7)));
+ timing = tm->interface_params[if_id].timing;
+
if (mode2_t != 0xff) {
t2t = mode2_t;
+ } else if (timing != HWS_TIM_DEFAULT) {
+ /* Board topology map is forcing timing */
+ t2t = (timing == HWS_TIM_2T) ? 1 : 0;
} else {
/* calculate number of CS (per interface) */
CHECK_STATUS(calc_cs_num
MEM_SIZE_LAST
};
+enum hws_timing {
+ HWS_TIM_DEFAULT,
+ HWS_TIM_1T,
+ HWS_TIM_2T
+};
+
struct bus_params {
/* Chip Select (CS) bitmask (bits 0-CS0, bit 1- CS1 ...) */
u8 cs_bitmask;
/* operation temperature */
enum hws_temperature interface_temp;
+
+ /* 2T vs 1T mode (by default computed from number of CSs) */
+ enum hws_timing timing;
};
struct hws_topology_map {
return ret;
}
-void dfu_write_transaction_cleanup(struct dfu_entity *dfu)
+void dfu_transaction_cleanup(struct dfu_entity *dfu)
{
/* clear everything */
dfu->crc = 0;
dfu->offset = 0;
dfu->i_blk_seq_num = 0;
- dfu->i_buf_start = dfu_buf;
- dfu->i_buf_end = dfu_buf;
+ dfu->i_buf_start = dfu_get_buf(dfu);
+ dfu->i_buf_end = dfu->i_buf_start;
dfu->i_buf = dfu->i_buf_start;
+ dfu->r_left = 0;
+ dfu->b_left = 0;
+ dfu->bad_skip = 0;
+
dfu->inited = 0;
}
+int dfu_transaction_initiate(struct dfu_entity *dfu, bool read)
+{
+ int ret = 0;
+
+ if (dfu->inited)
+ return 0;
+
+ dfu_transaction_cleanup(dfu);
+
+ if (dfu->i_buf_start == NULL)
+ return -ENOMEM;
+
+ dfu->i_buf_end = dfu->i_buf_start + dfu_get_buf_size();
+
+ if (read) {
+ ret = dfu->get_medium_size(dfu, &dfu->r_left);
+ if (ret < 0)
+ return ret;
+ debug("%s: %s %lld [B]\n", __func__, dfu->name, dfu->r_left);
+ }
+
+ dfu->inited = 1;
+
+ return 0;
+}
+
int dfu_flush(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num)
{
int ret = 0;
printf("\nDFU complete %s: 0x%08x\n", dfu_hash_algo->name,
dfu->crc);
- dfu_write_transaction_cleanup(dfu);
+ dfu_transaction_cleanup(dfu);
return ret;
}
__func__, dfu->name, buf, size, blk_seq_num, dfu->offset,
(unsigned long)(dfu->i_buf - dfu->i_buf_start));
- if (!dfu->inited) {
- /* initial state */
- dfu->crc = 0;
- dfu->offset = 0;
- dfu->bad_skip = 0;
- dfu->i_blk_seq_num = 0;
- dfu->i_buf_start = dfu_get_buf(dfu);
- if (dfu->i_buf_start == NULL)
- return -ENOMEM;
- dfu->i_buf_end = dfu_get_buf(dfu) + dfu_buf_size;
- dfu->i_buf = dfu->i_buf_start;
-
- dfu->inited = 1;
- }
+ ret = dfu_transaction_initiate(dfu, false);
+ if (ret < 0)
+ return ret;
if (dfu->i_blk_seq_num != blk_seq_num) {
printf("%s: Wrong sequence number! [%d] [%d]\n",
__func__, dfu->i_blk_seq_num, blk_seq_num);
- dfu_write_transaction_cleanup(dfu);
+ dfu_transaction_cleanup(dfu);
return -1;
}
if ((dfu->i_buf + size) > dfu->i_buf_end) {
ret = dfu_write_buffer_drain(dfu);
if (ret) {
- dfu_write_transaction_cleanup(dfu);
+ dfu_transaction_cleanup(dfu);
return ret;
}
}
if ((dfu->i_buf + size) > dfu->i_buf_end) {
error("Buffer overflow! (0x%p + 0x%x > 0x%p)\n", dfu->i_buf,
size, dfu->i_buf_end);
- dfu_write_transaction_cleanup(dfu);
+ dfu_transaction_cleanup(dfu);
return -1;
}
if (size == 0 || (dfu->i_buf + size) > dfu->i_buf_end) {
ret = dfu_write_buffer_drain(dfu);
if (ret) {
- dfu_write_transaction_cleanup(dfu);
+ dfu_transaction_cleanup(dfu);
return ret;
}
}
debug("%s: name: %s buf: 0x%p size: 0x%x p_num: 0x%x i_buf: 0x%p\n",
__func__, dfu->name, buf, size, blk_seq_num, dfu->i_buf);
- if (!dfu->inited) {
- dfu->i_buf_start = dfu_get_buf(dfu);
- if (dfu->i_buf_start == NULL)
- return -ENOMEM;
-
- dfu->r_left = dfu->get_medium_size(dfu);
- if (dfu->r_left < 0)
- return dfu->r_left;
-
- debug("%s: %s %ld [B]\n", __func__, dfu->name, dfu->r_left);
-
- dfu->i_blk_seq_num = 0;
- dfu->crc = 0;
- dfu->offset = 0;
- dfu->i_buf_end = dfu_get_buf(dfu) + dfu_buf_size;
- dfu->i_buf = dfu->i_buf_start;
- dfu->b_left = 0;
-
- dfu->bad_skip = 0;
-
- dfu->inited = 1;
- }
+ ret = dfu_transaction_initiate(dfu, true);
+ if (ret < 0)
+ return ret;
if (dfu->i_blk_seq_num != blk_seq_num) {
printf("%s: Wrong sequence number! [%d] [%d]\n",
dfu_hash_algo->name, dfu->crc);
puts("\nUPLOAD ... done\nCtrl+C to exit ...\n");
- dfu->i_blk_seq_num = 0;
- dfu->crc = 0;
- dfu->offset = 0;
- dfu->i_buf_start = dfu_buf;
- dfu->i_buf_end = dfu_buf;
- dfu->i_buf = dfu->i_buf_start;
- dfu->b_left = 0;
-
- dfu->bad_skip = 0;
-
- dfu->inited = 0;
+ dfu_transaction_cleanup(dfu);
}
return ret;
#include <mmc.h>
static unsigned char *dfu_file_buf;
-static long dfu_file_buf_len;
+static u64 dfu_file_buf_len;
static long dfu_file_buf_filled;
static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu,
}
static int mmc_file_op(enum dfu_op op, struct dfu_entity *dfu,
- void *buf, long *len)
+ void *buf, u64 *len)
{
const char *fsname, *opname;
char cmd_buf[DFU_CMD_BUF_SIZE];
sprintf(cmd_buf + strlen(cmd_buf), " %s", dfu->name);
if (op == DFU_OP_WRITE)
- sprintf(cmd_buf + strlen(cmd_buf), " %lx", *len);
+ sprintf(cmd_buf + strlen(cmd_buf), " %llx", *len);
debug("%s: %s 0x%p\n", __func__, cmd_buf, cmd_buf);
return ret;
}
-long dfu_get_medium_size_mmc(struct dfu_entity *dfu)
+int dfu_get_medium_size_mmc(struct dfu_entity *dfu, u64 *size)
{
int ret;
- long len;
switch (dfu->layout) {
case DFU_RAW_ADDR:
- return dfu->data.mmc.lba_size * dfu->data.mmc.lba_blk_size;
+ *size = dfu->data.mmc.lba_size * dfu->data.mmc.lba_blk_size;
+ return 0;
case DFU_FS_FAT:
case DFU_FS_EXT4:
dfu_file_buf_filled = -1;
- ret = mmc_file_op(DFU_OP_SIZE, dfu, NULL, &len);
+ ret = mmc_file_op(DFU_OP_SIZE, dfu, NULL, size);
if (ret < 0)
return ret;
- if (len > CONFIG_SYS_DFU_MAX_FILE_SIZE)
+ if (*size > CONFIG_SYS_DFU_MAX_FILE_SIZE)
return -1;
- return len;
+ return 0;
default:
printf("%s: Layout (%s) not (yet) supported!\n", __func__,
dfu_get_layout(dfu->layout));
long *len)
{
int ret;
- long file_len;
+ u64 file_len;
if (dfu_file_buf_filled == -1) {
ret = mmc_file_op(DFU_OP_READ, dfu, dfu_file_buf, &file_len);
lim = dfu->data.nand.start + dfu->data.nand.size - start;
count = *len;
+ mtd = get_nand_dev_by_index(nand_curr_device);
+
if (nand_curr_device < 0 ||
nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
- !nand_info[nand_curr_device]) {
+ !mtd) {
printf("%s: invalid nand device\n", __func__);
return -1;
}
- mtd = nand_info[nand_curr_device];
-
if (op == DFU_OP_READ) {
ret = nand_read_skip_bad(mtd, start, &count, &actual,
lim, buf);
return ret;
}
-long dfu_get_medium_size_nand(struct dfu_entity *dfu)
+int dfu_get_medium_size_nand(struct dfu_entity *dfu, u64 *size)
{
- return dfu->data.nand.size;
+ *size = dfu->data.nand.size;
+
+ return 0;
}
static int dfu_read_medium_nand(struct dfu_entity *dfu, u64 offset, void *buf,
/* in case of ubi partition, erase rest of the partition */
if (dfu->data.nand.ubi) {
- struct mtd_info *mtd;
+ struct mtd_info *mtd = get_nand_dev_by_index(nand_curr_device);
nand_erase_options_t opts;
if (nand_curr_device < 0 ||
nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
- !nand_info[nand_curr_device]) {
+ !mtd) {
printf("%s: invalid nand device\n", __func__);
return -1;
}
- mtd = nand_info[nand_curr_device];
-
memset(&opts, 0, sizeof(opts));
off = dfu->offset;
if ((off & (mtd->erasesize - 1)) != 0) {
return dfu_transfer_medium_ram(DFU_OP_WRITE, dfu, offset, buf, len);
}
-long dfu_get_medium_size_ram(struct dfu_entity *dfu)
+int dfu_get_medium_size_ram(struct dfu_entity *dfu, u64 *size)
{
- return dfu->data.ram.size;
+ *size = dfu->data.ram.size;
+
+ return 0;
}
static int dfu_read_medium_ram(struct dfu_entity *dfu, u64 offset,
#include <spi.h>
#include <spi_flash.h>
-static long dfu_get_medium_size_sf(struct dfu_entity *dfu)
+static int dfu_get_medium_size_sf(struct dfu_entity *dfu, u64 *size)
{
- return dfu->data.sf.size;
+ *size = dfu->data.sf.size;
+
+ return 0;
}
static int dfu_read_medium_sf(struct dfu_entity *dfu, u64 offset, void *buf,
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/dma.h>
-#include <asm/imx-common/regs-apbh.h>
+#include <asm/mach-imx/dma.h>
+#include <asm/mach-imx/regs-apbh.h>
static struct mxs_dma_chan mxs_dma_channels[MXS_MAX_DMA_CHANNELS];
Enable Altera FPGA specific functions which includes bitstream
(in BIT format), fpga and device validation.
+config FPGA_SOCFPGA
+ bool "Enable Gen5 and Arria10 common FPGA drivers"
+ select FPGA_ALTERA
+ help
+ Say Y here to enable the Gen5 and Arria10 common FPGA driver
+
+ This provides common functionality for Gen5 and Arria10 devices.
+
config FPGA_CYCLON2
bool "Enable Altera FPGA driver for Cyclone II"
depends on FPGA_ALTERA
obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o
endif
static struct socfpga_fpga_manager *fpgamgr_regs =
(struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
-static struct socfpga_system_manager *sysmgr_regs =
- (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-/* Set CD ratio */
-static void fpgamgr_set_cd_ratio(unsigned long ratio)
-{
- clrsetbits_le32(&fpgamgr_regs->ctrl,
- 0x3 << FPGAMGRREGS_CTRL_CDRATIO_LSB,
- (ratio & 0x3) << FPGAMGRREGS_CTRL_CDRATIO_LSB);
-}
-
-static int fpgamgr_dclkcnt_set(unsigned long cnt)
+int fpgamgr_dclkcnt_set(unsigned long cnt)
{
unsigned long i;
return -ETIMEDOUT;
}
-/* Start the FPGA programming by initialize the FPGA Manager */
-static int fpgamgr_program_init(void)
-{
- unsigned long msel, i;
-
- /* Get the MSEL value */
- msel = readl(&fpgamgr_regs->stat);
- msel &= FPGAMGRREGS_STAT_MSEL_MASK;
- msel >>= FPGAMGRREGS_STAT_MSEL_LSB;
-
- /*
- * Set the cfg width
- * If MSEL[3] = 1, cfg width = 32 bit
- */
- if (msel & 0x8) {
- setbits_le32(&fpgamgr_regs->ctrl,
- FPGAMGRREGS_CTRL_CFGWDTH_MASK);
-
- /* To determine the CD ratio */
- /* MSEL[1:0] = 0, CD Ratio = 1 */
- if ((msel & 0x3) == 0x0)
- fpgamgr_set_cd_ratio(CDRATIO_x1);
- /* MSEL[1:0] = 1, CD Ratio = 4 */
- else if ((msel & 0x3) == 0x1)
- fpgamgr_set_cd_ratio(CDRATIO_x4);
- /* MSEL[1:0] = 2, CD Ratio = 8 */
- else if ((msel & 0x3) == 0x2)
- fpgamgr_set_cd_ratio(CDRATIO_x8);
-
- } else { /* MSEL[3] = 0 */
- clrbits_le32(&fpgamgr_regs->ctrl,
- FPGAMGRREGS_CTRL_CFGWDTH_MASK);
-
- /* To determine the CD ratio */
- /* MSEL[1:0] = 0, CD Ratio = 1 */
- if ((msel & 0x3) == 0x0)
- fpgamgr_set_cd_ratio(CDRATIO_x1);
- /* MSEL[1:0] = 1, CD Ratio = 2 */
- else if ((msel & 0x3) == 0x1)
- fpgamgr_set_cd_ratio(CDRATIO_x2);
- /* MSEL[1:0] = 2, CD Ratio = 4 */
- else if ((msel & 0x3) == 0x2)
- fpgamgr_set_cd_ratio(CDRATIO_x4);
- }
-
- /* To enable FPGA Manager configuration */
- clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCE_MASK);
-
- /* To enable FPGA Manager drive over configuration line */
- setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK);
-
- /* Put FPGA into reset phase */
- setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);
-
- /* (1) wait until FPGA enter reset phase */
- for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
- if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_RESETPHASE)
- break;
- }
-
- /* If not in reset state, return error */
- if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_RESETPHASE) {
- puts("FPGA: Could not reset\n");
- return -1;
- }
-
- /* Release FPGA from reset phase */
- clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);
-
- /* (2) wait until FPGA enter configuration phase */
- for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
- if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_CFGPHASE)
- break;
- }
-
- /* If not in configuration state, return error */
- if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_CFGPHASE) {
- puts("FPGA: Could not configure\n");
- return -2;
- }
-
- /* Clear all interrupts in CB Monitor */
- writel(0xFFF, &fpgamgr_regs->gpio_porta_eoi);
-
- /* Enable AXI configuration */
- setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK);
-
- return 0;
-}
-
/* Write the RBF data to FPGA Manager */
-static void fpgamgr_program_write(const void *rbf_data, unsigned long rbf_size)
+void fpgamgr_program_write(const void *rbf_data, size_t rbf_size)
{
uint32_t src = (uint32_t)rbf_data;
uint32_t dst = SOCFPGA_FPGAMGRDATA_ADDRESS;
: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc");
}
-/* Ensure the FPGA entering config done */
-static int fpgamgr_program_poll_cd(void)
-{
- const uint32_t mask = FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK |
- FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK;
- unsigned long reg, i;
-
- /* (3) wait until full config done */
- for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
- reg = readl(&fpgamgr_regs->gpio_ext_porta);
-
- /* Config error */
- if (!(reg & mask)) {
- printf("FPGA: Configuration error.\n");
- return -3;
- }
-
- /* Config done without error */
- if (reg & mask)
- break;
- }
-
- /* Timeout happened, return error */
- if (i == FPGA_TIMEOUT_CNT) {
- printf("FPGA: Timeout waiting for program.\n");
- return -4;
- }
-
- /* Disable AXI configuration */
- clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK);
-
- return 0;
-}
-
-/* Ensure the FPGA entering init phase */
-static int fpgamgr_program_poll_initphase(void)
-{
- unsigned long i;
-
- /* Additional clocks for the CB to enter initialization phase */
- if (fpgamgr_dclkcnt_set(0x4))
- return -5;
-
- /* (4) wait until FPGA enter init phase or user mode */
- for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
- if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_INITPHASE)
- break;
- if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE)
- break;
- }
-
- /* If not in configuration state, return error */
- if (i == FPGA_TIMEOUT_CNT)
- return -6;
-
- return 0;
-}
-
-/* Ensure the FPGA entering user mode */
-static int fpgamgr_program_poll_usermode(void)
-{
- unsigned long i;
-
- /* Additional clocks for the CB to exit initialization phase */
- if (fpgamgr_dclkcnt_set(0x5000))
- return -7;
-
- /* (5) wait until FPGA enter user mode */
- for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
- if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE)
- break;
- }
- /* If not in configuration state, return error */
- if (i == FPGA_TIMEOUT_CNT)
- return -8;
-
- /* To release FPGA Manager drive over configuration line */
- clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK);
-
- return 0;
-}
-
-/*
- * FPGA Manager to program the FPGA. This is the interface used by FPGA driver.
- * Return 0 for sucess, non-zero for error.
- */
-int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
-{
- unsigned long status;
-
- if ((uint32_t)rbf_data & 0x3) {
- puts("FPGA: Unaligned data, realign to 32bit boundary.\n");
- return -EINVAL;
- }
-
- /* Prior programming the FPGA, all bridges need to be shut off */
-
- /* Disable all signals from hps peripheral controller to fpga */
- writel(0, &sysmgr_regs->fpgaintfgrp_module);
-
- /* Disable all signals from FPGA to HPS SDRAM */
-#define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080
- writel(0, SOCFPGA_SDR_ADDRESS + SDR_CTRLGRP_FPGAPORTRST_ADDRESS);
-
- /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
- socfpga_bridges_reset(1);
-
- /* Unmap the bridges from NIC-301 */
- writel(0x1, SOCFPGA_L3REGS_ADDRESS);
-
- /* Initialize the FPGA Manager */
- status = fpgamgr_program_init();
- if (status)
- return status;
-
- /* Write the RBF data to FPGA Manager */
- fpgamgr_program_write(rbf_data, rbf_size);
-
- /* Ensure the FPGA entering config done */
- status = fpgamgr_program_poll_cd();
- if (status)
- return status;
-
- /* Ensure the FPGA entering init phase */
- status = fpgamgr_program_poll_initphase();
- if (status)
- return status;
-
- /* Ensure the FPGA entering user mode */
- return fpgamgr_program_poll_usermode();
-}
--- /dev/null
+/*
+ * Copyright (C) 2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <asm/io.h>
+#include <asm/arch/fpga_manager.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <asm/arch/sdram.h>
+#include <asm/arch/misc.h>
+#include <altera.h>
+#include <common.h>
+#include <errno.h>
+#include <wait_bit.h>
+#include <watchdog.h>
+
+#define CFGWDTH_32 1
+#define MIN_BITSTREAM_SIZECHECK 230
+#define ENCRYPTION_OFFSET 69
+#define COMPRESSION_OFFSET 229
+#define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */
+#define FPGA_TIMEOUT_CNT 0x1000000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_fpga_manager *fpga_manager_base =
+ (void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
+
+static const struct socfpga_system_manager *system_manager_base =
+ (void *)SOCFPGA_SYSMGR_ADDRESS;
+
+static void fpgamgr_set_cd_ratio(unsigned long ratio);
+
+static uint32_t fpgamgr_get_msel(void)
+{
+ u32 reg;
+
+ reg = readl(&fpga_manager_base->imgcfg_stat);
+ reg = (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD) >>
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB;
+
+ return reg;
+}
+
+static void fpgamgr_set_cfgwdth(int width)
+{
+ if (width)
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+ ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
+ else
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+ ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
+}
+
+int is_fpgamgr_user_mode(void)
+{
+ return (readl(&fpga_manager_base->imgcfg_stat) &
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) != 0;
+}
+
+static int wait_for_user_mode(void)
+{
+ return wait_for_bit(__func__,
+ &fpga_manager_base->imgcfg_stat,
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK,
+ 1, FPGA_TIMEOUT_MSEC, false);
+}
+
+static int is_fpgamgr_early_user_mode(void)
+{
+ return (readl(&fpga_manager_base->imgcfg_stat) &
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0;
+}
+
+int fpgamgr_wait_early_user_mode(void)
+{
+ u32 sync_data = 0xffffffff;
+ u32 i = 0;
+ unsigned start = get_timer(0);
+ unsigned long cd_ratio;
+
+ /* Getting existing CDRATIO */
+ cd_ratio = (readl(&fpga_manager_base->imgcfg_ctrl_02) &
+ ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK) >>
+ ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB;
+
+ /* Using CDRATIO_X1 for better compatibility */
+ fpgamgr_set_cd_ratio(CDRATIO_x1);
+
+ while (!is_fpgamgr_early_user_mode()) {
+ if (get_timer(start) > FPGA_TIMEOUT_MSEC)
+ return -ETIMEDOUT;
+ fpgamgr_program_write((const long unsigned int *)&sync_data,
+ sizeof(sync_data));
+ udelay(FPGA_TIMEOUT_MSEC);
+ i++;
+ }
+
+ debug("Additional %i sync word needed\n", i);
+
+ /* restoring original CDRATIO */
+ fpgamgr_set_cd_ratio(cd_ratio);
+
+ return 0;
+}
+
+/* Read f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted */
+static int wait_for_nconfig_pin_and_nstatus_pin(void)
+{
+ unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK;
+
+ /* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted,
+ * timeout at 1000ms
+ */
+ return wait_for_bit(__func__,
+ &fpga_manager_base->imgcfg_stat,
+ mask,
+ false, FPGA_TIMEOUT_MSEC, false);
+}
+
+static int wait_for_f2s_nstatus_pin(unsigned long value)
+{
+ /* Poll until f2s to specific value, timeout at 1000ms */
+ return wait_for_bit(__func__,
+ &fpga_manager_base->imgcfg_stat,
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK,
+ value, FPGA_TIMEOUT_MSEC, false);
+}
+
+/* set CD ratio */
+static void fpgamgr_set_cd_ratio(unsigned long ratio)
+{
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+ ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
+
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+ (ratio << ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB) &
+ ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
+}
+
+/* get the MSEL value, verify we are set for FPP configuration mode */
+static int fpgamgr_verify_msel(void)
+{
+ u32 msel = fpgamgr_get_msel();
+
+ if (msel & ~BIT(0)) {
+ printf("Fail: read msel=%d\n", msel);
+ return -EPERM;
+ }
+
+ return 0;
+}
+
+/*
+ * Write cdratio and cdwidth based on whether the bitstream is compressed
+ * and/or encoded
+ */
+static int fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width, u32 *rbf_data,
+ size_t rbf_size)
+{
+ unsigned int cd_ratio;
+ bool encrypt, compress;
+
+ /*
+ * According to the bitstream specification,
+ * both encryption and compression status are
+ * in location before offset 230 of the buffer.
+ */
+ if (rbf_size < MIN_BITSTREAM_SIZECHECK)
+ return -EINVAL;
+
+ encrypt = (rbf_data[ENCRYPTION_OFFSET] >> 2) & 3;
+ encrypt = encrypt != 0;
+
+ compress = (rbf_data[COMPRESSION_OFFSET] >> 1) & 1;
+ compress = !compress;
+
+ debug("header word %d = %08x\n", 69, rbf_data[69]);
+ debug("header word %d = %08x\n", 229, rbf_data[229]);
+ debug("read from rbf header: encrypt=%d compress=%d\n", encrypt, compress);
+
+ /*
+ * from the register map description of cdratio in imgcfg_ctrl_02:
+ * Normal Configuration : 32bit Passive Parallel
+ * Partial Reconfiguration : 16bit Passive Parallel
+ */
+
+ /*
+ * cd ratio is dependent on cfg width and whether the bitstream
+ * is encrypted and/or compressed.
+ *
+ * | width | encr. | compr. | cd ratio |
+ * | 16 | 0 | 0 | 1 |
+ * | 16 | 0 | 1 | 4 |
+ * | 16 | 1 | 0 | 2 |
+ * | 16 | 1 | 1 | 4 |
+ * | 32 | 0 | 0 | 1 |
+ * | 32 | 0 | 1 | 8 |
+ * | 32 | 1 | 0 | 4 |
+ * | 32 | 1 | 1 | 8 |
+ */
+ if (!compress && !encrypt) {
+ cd_ratio = CDRATIO_x1;
+ } else {
+ if (compress)
+ cd_ratio = CDRATIO_x4;
+ else
+ cd_ratio = CDRATIO_x2;
+
+ /* if 32 bit, double the cd ratio (so register
+ field setting is incremented) */
+ if (cfg_width == CFGWDTH_32)
+ cd_ratio += 1;
+ }
+
+ fpgamgr_set_cfgwdth(cfg_width);
+ fpgamgr_set_cd_ratio(cd_ratio);
+
+ return 0;
+}
+
+static int fpgamgr_reset(void)
+{
+ unsigned long reg;
+
+ /* S2F_NCONFIG = 0 */
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
+
+ /* Wait for f2s_nstatus == 0 */
+ if (wait_for_f2s_nstatus_pin(0))
+ return -ETIME;
+
+ /* S2F_NCONFIG = 1 */
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
+
+ /* Wait for f2s_nstatus == 1 */
+ if (wait_for_f2s_nstatus_pin(1))
+ return -ETIME;
+
+ /* read and confirm f2s_condone_pin = 0 and f2s_condone_oe = 1 */
+ reg = readl(&fpga_manager_base->imgcfg_stat);
+ if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) != 0)
+ return -EPERM;
+
+ if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK) == 0)
+ return -EPERM;
+
+ return 0;
+}
+
+/* Start the FPGA programming by initialize the FPGA Manager */
+int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size)
+{
+ int ret;
+
+ /* Step 1 */
+ if (fpgamgr_verify_msel())
+ return -EPERM;
+
+ /* Step 2 */
+ if (fpgamgr_set_cdratio_cdwidth(CFGWDTH_32, rbf_data, rbf_size))
+ return -EPERM;
+
+ /*
+ * Step 3:
+ * Make sure no other external devices are trying to interfere with
+ * programming:
+ */
+ if (wait_for_nconfig_pin_and_nstatus_pin())
+ return -ETIME;
+
+ /*
+ * Step 4:
+ * Deassert the signal drives from HPS
+ *
+ * S2F_NCE = 1
+ * S2F_PR_REQUEST = 0
+ * EN_CFG_CTRL = 0
+ * EN_CFG_DATA = 0
+ * S2F_NCONFIG = 1
+ * S2F_NSTATUS_OE = 0
+ * S2F_CONDONE_OE = 0
+ */
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
+ ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
+
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
+ ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK);
+
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+ ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
+ ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
+
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
+
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK |
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK);
+
+ /*
+ * Step 5:
+ * Enable overrides
+ * S2F_NENABLE_CONFIG = 0
+ * S2F_NENABLE_NCONFIG = 0
+ */
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
+ ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
+
+ /*
+ * Disable driving signals that HPS doesn't need to drive.
+ * S2F_NENABLE_NSTATUS = 1
+ * S2F_NENABLE_CONDONE = 1
+ */
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK |
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK);
+
+ /*
+ * Step 6:
+ * Drive chip select S2F_NCE = 0
+ */
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
+ ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
+
+ /* Step 7 */
+ if (wait_for_nconfig_pin_and_nstatus_pin())
+ return -ETIME;
+
+ /* Step 8 */
+ ret = fpgamgr_reset();
+
+ if (ret)
+ return ret;
+
+ /*
+ * Step 9:
+ * EN_CFG_CTRL and EN_CFG_DATA = 1
+ */
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+ ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
+ ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
+
+ return 0;
+}
+
+/* Ensure the FPGA entering config done */
+static int fpgamgr_program_poll_cd(void)
+{
+ unsigned long reg, i;
+
+ for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
+ reg = readl(&fpga_manager_base->imgcfg_stat);
+ if (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK)
+ return 0;
+
+ if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) == 0) {
+ printf("nstatus == 0 while waiting for condone\n");
+ return -EPERM;
+ }
+ }
+
+ if (i == FPGA_TIMEOUT_CNT)
+ return -ETIME;
+
+ return 0;
+}
+
+/* Ensure the FPGA entering user mode */
+static int fpgamgr_program_poll_usermode(void)
+{
+ unsigned long reg;
+ int ret = 0;
+
+ if (fpgamgr_dclkcnt_set(0xf))
+ return -ETIME;
+
+ ret = wait_for_user_mode();
+ if (ret < 0) {
+ printf("%s: Failed to enter user mode with ", __func__);
+ printf("error code %d\n", ret);
+ return ret;
+ }
+
+ /*
+ * Step 14:
+ * Stop DATA path and Dclk
+ * EN_CFG_CTRL and EN_CFG_DATA = 0
+ */
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+ ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
+ ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
+
+ /*
+ * Step 15:
+ * Disable overrides
+ * S2F_NENABLE_CONFIG = 1
+ * S2F_NENABLE_NCONFIG = 1
+ */
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
+ ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
+
+ /* Disable chip select S2F_NCE = 1 */
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
+ ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
+
+ /*
+ * Step 16:
+ * Final check
+ */
+ reg = readl(&fpga_manager_base->imgcfg_stat);
+ if (((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) !=
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) ||
+ ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) !=
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) ||
+ ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) !=
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK))
+ return -EPERM;
+
+ return 0;
+}
+
+int fpgamgr_program_finish(void)
+{
+ /* Ensure the FPGA entering config done */
+ int status = fpgamgr_program_poll_cd();
+
+ if (status) {
+ printf("FPGA: Poll CD failed with error code %d\n", status);
+ return -EPERM;
+ }
+ WATCHDOG_RESET();
+
+ /* Ensure the FPGA entering user mode */
+ status = fpgamgr_program_poll_usermode();
+ if (status) {
+ printf("FPGA: Poll usermode failed with error code %d\n",
+ status);
+ return -EPERM;
+ }
+
+ printf("Full Configuration Succeeded.\n");
+
+ return 0;
+}
+
+/*
+ * FPGA Manager to program the FPGA. This is the interface used by FPGA driver.
+ * Return 0 for sucess, non-zero for error.
+ */
+int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
+{
+ unsigned long status;
+
+ /* disable all signals from hps peripheral controller to fpga */
+ writel(0, &system_manager_base->fpgaintf_en_global);
+
+ /* disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
+ socfpga_bridges_reset();
+
+ /* Initialize the FPGA Manager */
+ status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
+ if (status)
+ return status;
+
+ /* Write the RBF data to FPGA Manager */
+ fpgamgr_program_write(rbf_data, rbf_size);
+
+ return fpgamgr_program_finish();
+}
--- /dev/null
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/fpga_manager.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define FPGA_TIMEOUT_CNT 0x1000000
+
+static struct socfpga_fpga_manager *fpgamgr_regs =
+ (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
+static struct socfpga_system_manager *sysmgr_regs =
+ (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+/* Set CD ratio */
+static void fpgamgr_set_cd_ratio(unsigned long ratio)
+{
+ clrsetbits_le32(&fpgamgr_regs->ctrl,
+ 0x3 << FPGAMGRREGS_CTRL_CDRATIO_LSB,
+ (ratio & 0x3) << FPGAMGRREGS_CTRL_CDRATIO_LSB);
+}
+
+/* Start the FPGA programming by initialize the FPGA Manager */
+static int fpgamgr_program_init(void)
+{
+ unsigned long msel, i;
+
+ /* Get the MSEL value */
+ msel = readl(&fpgamgr_regs->stat);
+ msel &= FPGAMGRREGS_STAT_MSEL_MASK;
+ msel >>= FPGAMGRREGS_STAT_MSEL_LSB;
+
+ /*
+ * Set the cfg width
+ * If MSEL[3] = 1, cfg width = 32 bit
+ */
+ if (msel & 0x8) {
+ setbits_le32(&fpgamgr_regs->ctrl,
+ FPGAMGRREGS_CTRL_CFGWDTH_MASK);
+
+ /* To determine the CD ratio */
+ /* MSEL[1:0] = 0, CD Ratio = 1 */
+ if ((msel & 0x3) == 0x0)
+ fpgamgr_set_cd_ratio(CDRATIO_x1);
+ /* MSEL[1:0] = 1, CD Ratio = 4 */
+ else if ((msel & 0x3) == 0x1)
+ fpgamgr_set_cd_ratio(CDRATIO_x4);
+ /* MSEL[1:0] = 2, CD Ratio = 8 */
+ else if ((msel & 0x3) == 0x2)
+ fpgamgr_set_cd_ratio(CDRATIO_x8);
+
+ } else { /* MSEL[3] = 0 */
+ clrbits_le32(&fpgamgr_regs->ctrl,
+ FPGAMGRREGS_CTRL_CFGWDTH_MASK);
+
+ /* To determine the CD ratio */
+ /* MSEL[1:0] = 0, CD Ratio = 1 */
+ if ((msel & 0x3) == 0x0)
+ fpgamgr_set_cd_ratio(CDRATIO_x1);
+ /* MSEL[1:0] = 1, CD Ratio = 2 */
+ else if ((msel & 0x3) == 0x1)
+ fpgamgr_set_cd_ratio(CDRATIO_x2);
+ /* MSEL[1:0] = 2, CD Ratio = 4 */
+ else if ((msel & 0x3) == 0x2)
+ fpgamgr_set_cd_ratio(CDRATIO_x4);
+ }
+
+ /* To enable FPGA Manager configuration */
+ clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCE_MASK);
+
+ /* To enable FPGA Manager drive over configuration line */
+ setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK);
+
+ /* Put FPGA into reset phase */
+ setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);
+
+ /* (1) wait until FPGA enter reset phase */
+ for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
+ if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_RESETPHASE)
+ break;
+ }
+
+ /* If not in reset state, return error */
+ if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_RESETPHASE) {
+ puts("FPGA: Could not reset\n");
+ return -1;
+ }
+
+ /* Release FPGA from reset phase */
+ clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);
+
+ /* (2) wait until FPGA enter configuration phase */
+ for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
+ if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_CFGPHASE)
+ break;
+ }
+
+ /* If not in configuration state, return error */
+ if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_CFGPHASE) {
+ puts("FPGA: Could not configure\n");
+ return -2;
+ }
+
+ /* Clear all interrupts in CB Monitor */
+ writel(0xFFF, &fpgamgr_regs->gpio_porta_eoi);
+
+ /* Enable AXI configuration */
+ setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK);
+
+ return 0;
+}
+
+/* Ensure the FPGA entering config done */
+static int fpgamgr_program_poll_cd(void)
+{
+ const uint32_t mask = FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK |
+ FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK;
+ unsigned long reg, i;
+
+ /* (3) wait until full config done */
+ for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
+ reg = readl(&fpgamgr_regs->gpio_ext_porta);
+
+ /* Config error */
+ if (!(reg & mask)) {
+ printf("FPGA: Configuration error.\n");
+ return -3;
+ }
+
+ /* Config done without error */
+ if (reg & mask)
+ break;
+ }
+
+ /* Timeout happened, return error */
+ if (i == FPGA_TIMEOUT_CNT) {
+ printf("FPGA: Timeout waiting for program.\n");
+ return -4;
+ }
+
+ /* Disable AXI configuration */
+ clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK);
+
+ return 0;
+}
+
+/* Ensure the FPGA entering init phase */
+static int fpgamgr_program_poll_initphase(void)
+{
+ unsigned long i;
+
+ /* Additional clocks for the CB to enter initialization phase */
+ if (fpgamgr_dclkcnt_set(0x4))
+ return -5;
+
+ /* (4) wait until FPGA enter init phase or user mode */
+ for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
+ if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_INITPHASE)
+ break;
+ if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE)
+ break;
+ }
+
+ /* If not in configuration state, return error */
+ if (i == FPGA_TIMEOUT_CNT)
+ return -6;
+
+ return 0;
+}
+
+/* Ensure the FPGA entering user mode */
+static int fpgamgr_program_poll_usermode(void)
+{
+ unsigned long i;
+
+ /* Additional clocks for the CB to exit initialization phase */
+ if (fpgamgr_dclkcnt_set(0x5000))
+ return -7;
+
+ /* (5) wait until FPGA enter user mode */
+ for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
+ if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE)
+ break;
+ }
+ /* If not in configuration state, return error */
+ if (i == FPGA_TIMEOUT_CNT)
+ return -8;
+
+ /* To release FPGA Manager drive over configuration line */
+ clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK);
+
+ return 0;
+}
+
+/*
+ * FPGA Manager to program the FPGA. This is the interface used by FPGA driver.
+ * Return 0 for sucess, non-zero for error.
+ */
+int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
+{
+ unsigned long status;
+
+ if ((uint32_t)rbf_data & 0x3) {
+ puts("FPGA: Unaligned data, realign to 32bit boundary.\n");
+ return -EINVAL;
+ }
+
+ /* Prior programming the FPGA, all bridges need to be shut off */
+
+ /* Disable all signals from hps peripheral controller to fpga */
+ writel(0, &sysmgr_regs->fpgaintfgrp_module);
+
+ /* Disable all signals from FPGA to HPS SDRAM */
+#define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080
+ writel(0, SOCFPGA_SDR_ADDRESS + SDR_CTRLGRP_FPGAPORTRST_ADDRESS);
+
+ /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
+ socfpga_bridges_reset(1);
+
+ /* Unmap the bridges from NIC-301 */
+ writel(0x1, SOCFPGA_L3REGS_ADDRESS);
+
+ /* Initialize the FPGA Manager */
+ status = fpgamgr_program_init();
+ if (status)
+ return status;
+
+ /* Write the RBF data to FPGA Manager */
+ fpgamgr_program_write(rbf_data, rbf_size);
+
+ /* Ensure the FPGA entering config done */
+ status = fpgamgr_program_poll_cd();
+ if (status)
+ return status;
+
+ /* Ensure the FPGA entering init phase */
+ status = fpgamgr_program_poll_initphase();
+ if (status)
+ return status;
+
+ /* Ensure the FPGA entering user mode */
+ return fpgamgr_program_poll_usermode();
+}
* This driver does not make use of interrupts, other than to figure
* out the number of GPIO banks
*/
- if (!fdt_getprop(gd->fdt_blob, dev_of_offset(parent), "interrupts",
- &len))
- return -EINVAL;
+ len = dev_read_size(parent, "interrupts");
+ if (len < 0)
+ return len;
bank_count = len / 3 / sizeof(u32);
- ctlr = (struct gpio_ctlr *)devfdt_get_addr(parent);
+ ctlr = (struct gpio_ctlr *)dev_read_addr(parent);
+ if ((ulong)ctlr == FDT_ADDR_T_NONE)
+ return -EINVAL;
}
#endif
for (bank = 0; bank < bank_count; bank++) {
#include <errno.h>
#include <fdtdec.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
#include <malloc.h>
DECLARE_GLOBAL_DATA_PTR;
+enum pca_type {
+ PCA9544,
+ PCA9547,
+ PCA9548
+};
+
+struct chip_desc {
+ u8 enable;
+ enum muxtype {
+ pca954x_ismux = 0,
+ pca954x_isswi,
+ } muxtype;
+};
+
struct pca954x_priv {
u32 addr; /* I2C mux address */
u32 width; /* I2C mux width - number of busses */
};
+static const struct chip_desc chips[] = {
+ [PCA9544] = {
+ .enable = 0x4,
+ .muxtype = pca954x_ismux,
+ },
+ [PCA9547] = {
+ .enable = 0x8,
+ .muxtype = pca954x_ismux,
+ },
+ [PCA9548] = {
+ .enable = 0x8,
+ .muxtype = pca954x_isswi,
+ },
+};
+
static int pca954x_deselect(struct udevice *mux, struct udevice *bus,
uint channel)
{
uint channel)
{
struct pca954x_priv *priv = dev_get_priv(mux);
- uchar byte = 1 << channel;
+ const struct chip_desc *chip = &chips[dev_get_driver_data(mux)];
+ uchar byte;
+
+ if (chip->muxtype == pca954x_ismux)
+ byte = channel | chip->enable;
+ else
+ byte = 1 << channel;
return dm_i2c_write(mux, priv->addr, &byte, 1);
}
};
static const struct udevice_id pca954x_ids[] = {
- { .compatible = "nxp,pca9548", .data = (ulong)8 },
- { .compatible = "nxp,pca9544", .data = (ulong)4 },
+ { .compatible = "nxp,pca9544", .data = PCA9544 },
+ { .compatible = "nxp,pca9547", .data = PCA9547 },
+ { .compatible = "nxp,pca9548", .data = PCA9548 },
{ }
};
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <linux/errno.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <asm/io.h>
#include <i2c.h>
#include <watchdog.h>
*/
#include <common.h>
-#ifdef CONFIG_MPC8260 /* only valid for MPC8260 */
-#include <ioports.h>
-#include <asm/io.h>
-#endif
#if defined(CONFIG_AT91FAMILY)
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <common.h>
#include <dm.h>
#include <errno.h>
-#include <fdtdec.h>
#include <i2c.h>
#include <asm/io.h>
#include <clk.h>
i2c_bus->id = dev->seq;
i2c_bus->type = dev_get_driver_data(dev);
- i2c_bus->regs = (struct i2c_ctlr *)devfdt_get_addr(dev);
+ i2c_bus->regs = (struct i2c_ctlr *)dev_read_addr(dev);
+ if ((ulong)i2c_bus->regs == FDT_ADDR_T_NONE) {
+ debug("%s: Cannot get regs address\n", __func__);
+ return -EINVAL;
+ }
ret = reset_get_by_name(dev, "i2c", &i2c_bus->reset_ctl);
if (ret) {
Select this to enable a sysid for Altera devices. Please find
details on the "Embedded Peripherals IP User Guide" of Altera.
+config ATSHA204A
+ bool "Support for Atmel ATSHA204A module"
+ depends on MISC
+ help
+ Enable support for I2C connected Atmel's ATSHA204A
+ CryptoAuthentication module found for example on the Turris Omnia
+ board.
+
config ROCKCHIP_EFUSE
bool "Rockchip e-fuse support"
depends on MISC
obj-$(CONFIG_MISC) += misc-uclass.o
obj-$(CONFIG_ALI152X) += ali512x.o
obj-$(CONFIG_ALTERA_SYSID) += altera_sysid.o
+obj-$(CONFIG_ATSHA204A) += atsha204a-i2c.o
obj-$(CONFIG_DS4510) += ds4510.o
obj-$(CONFIG_CBMEM_CONSOLE) += cbmem_console.o
ifndef CONFIG_SPL_BUILD
--- /dev/null
+/*
+ * I2C Driver for Atmel ATSHA204 over I2C
+ *
+ * Copyright (C) 2014 Josh Datko, Cryptotronix, jbd@cryptotronix.com
+ * 2016 Tomas Hlavacek, CZ.NIC, tmshlvck@gmail.com
+ * 2017 Marek Behun, CZ.NIC, marek.behun@nic.cz
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <i2c.h>
+#include <errno.h>
+#include <atsha204a-i2c.h>
+
+#define ATSHA204A_TWLO 60
+#define ATSHA204A_TRANSACTION_TIMEOUT 100000
+#define ATSHA204A_TRANSACTION_RETRY 5
+#define ATSHA204A_EXECTIME 5000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * The ATSHA204A uses an (to me) unknown CRC-16 algorithm.
+ * The Reveng CRC-16 catalogue does not contain it.
+ *
+ * Because in Atmel's documentation only a primitive implementation
+ * can be found, I have implemented this one with lookup table.
+ */
+
+/*
+ * This is the code that computes the table below:
+ *
+ * int i, j;
+ * for (i = 0; i < 256; ++i) {
+ * u8 c = 0;
+ * for (j = 0; j < 8; ++j) {
+ * c = (c << 1) | ((i >> j) & 1);
+ * }
+ * bitreverse_table[i] = c;
+ * }
+ */
+
+static u8 const bitreverse_table[256] = {
+ 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
+ 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
+ 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
+ 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
+ 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
+ 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
+ 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
+ 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
+ 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
+ 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
+ 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
+ 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
+ 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
+ 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
+ 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
+ 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
+ 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
+ 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
+ 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
+ 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
+ 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
+ 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
+ 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
+ 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
+ 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
+ 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
+ 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
+ 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
+ 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
+ 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
+ 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
+ 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff,
+};
+
+/*
+ * This is the code that computes the table below:
+ *
+ * int i, j;
+ * for (i = 0; i < 256; ++i) {
+ * u16 c = i << 8;
+ * for (j = 0; j < 8; ++j) {
+ * int b = c >> 15;
+ * c <<= 1;
+ * if (b)
+ * c ^= 0x8005;
+ * }
+ * crc16_table[i] = c;
+ * }
+ */
+static u16 const crc16_table[256] = {
+ 0x0000, 0x8005, 0x800f, 0x000a, 0x801b, 0x001e, 0x0014, 0x8011,
+ 0x8033, 0x0036, 0x003c, 0x8039, 0x0028, 0x802d, 0x8027, 0x0022,
+ 0x8063, 0x0066, 0x006c, 0x8069, 0x0078, 0x807d, 0x8077, 0x0072,
+ 0x0050, 0x8055, 0x805f, 0x005a, 0x804b, 0x004e, 0x0044, 0x8041,
+ 0x80c3, 0x00c6, 0x00cc, 0x80c9, 0x00d8, 0x80dd, 0x80d7, 0x00d2,
+ 0x00f0, 0x80f5, 0x80ff, 0x00fa, 0x80eb, 0x00ee, 0x00e4, 0x80e1,
+ 0x00a0, 0x80a5, 0x80af, 0x00aa, 0x80bb, 0x00be, 0x00b4, 0x80b1,
+ 0x8093, 0x0096, 0x009c, 0x8099, 0x0088, 0x808d, 0x8087, 0x0082,
+ 0x8183, 0x0186, 0x018c, 0x8189, 0x0198, 0x819d, 0x8197, 0x0192,
+ 0x01b0, 0x81b5, 0x81bf, 0x01ba, 0x81ab, 0x01ae, 0x01a4, 0x81a1,
+ 0x01e0, 0x81e5, 0x81ef, 0x01ea, 0x81fb, 0x01fe, 0x01f4, 0x81f1,
+ 0x81d3, 0x01d6, 0x01dc, 0x81d9, 0x01c8, 0x81cd, 0x81c7, 0x01c2,
+ 0x0140, 0x8145, 0x814f, 0x014a, 0x815b, 0x015e, 0x0154, 0x8151,
+ 0x8173, 0x0176, 0x017c, 0x8179, 0x0168, 0x816d, 0x8167, 0x0162,
+ 0x8123, 0x0126, 0x012c, 0x8129, 0x0138, 0x813d, 0x8137, 0x0132,
+ 0x0110, 0x8115, 0x811f, 0x011a, 0x810b, 0x010e, 0x0104, 0x8101,
+ 0x8303, 0x0306, 0x030c, 0x8309, 0x0318, 0x831d, 0x8317, 0x0312,
+ 0x0330, 0x8335, 0x833f, 0x033a, 0x832b, 0x032e, 0x0324, 0x8321,
+ 0x0360, 0x8365, 0x836f, 0x036a, 0x837b, 0x037e, 0x0374, 0x8371,
+ 0x8353, 0x0356, 0x035c, 0x8359, 0x0348, 0x834d, 0x8347, 0x0342,
+ 0x03c0, 0x83c5, 0x83cf, 0x03ca, 0x83db, 0x03de, 0x03d4, 0x83d1,
+ 0x83f3, 0x03f6, 0x03fc, 0x83f9, 0x03e8, 0x83ed, 0x83e7, 0x03e2,
+ 0x83a3, 0x03a6, 0x03ac, 0x83a9, 0x03b8, 0x83bd, 0x83b7, 0x03b2,
+ 0x0390, 0x8395, 0x839f, 0x039a, 0x838b, 0x038e, 0x0384, 0x8381,
+ 0x0280, 0x8285, 0x828f, 0x028a, 0x829b, 0x029e, 0x0294, 0x8291,
+ 0x82b3, 0x02b6, 0x02bc, 0x82b9, 0x02a8, 0x82ad, 0x82a7, 0x02a2,
+ 0x82e3, 0x02e6, 0x02ec, 0x82e9, 0x02f8, 0x82fd, 0x82f7, 0x02f2,
+ 0x02d0, 0x82d5, 0x82df, 0x02da, 0x82cb, 0x02ce, 0x02c4, 0x82c1,
+ 0x8243, 0x0246, 0x024c, 0x8249, 0x0258, 0x825d, 0x8257, 0x0252,
+ 0x0270, 0x8275, 0x827f, 0x027a, 0x826b, 0x026e, 0x0264, 0x8261,
+ 0x0220, 0x8225, 0x822f, 0x022a, 0x823b, 0x023e, 0x0234, 0x8231,
+ 0x8213, 0x0216, 0x021c, 0x8219, 0x0208, 0x820d, 0x8207, 0x0202,
+};
+
+static inline u16 crc16_byte(u16 crc, const u8 data)
+{
+ u16 t = crc16_table[((crc >> 8) ^ bitreverse_table[data]) & 0xff];
+ return ((crc << 8) ^ t);
+}
+
+static u16 atsha204a_crc16(const u8 *buffer, size_t len)
+{
+ u16 crc = 0;
+
+ while (len--)
+ crc = crc16_byte(crc, *buffer++);
+
+ return cpu_to_le16(crc);
+}
+
+static int atsha204a_send(struct udevice *dev, const u8 *buf, u8 len)
+{
+ fdt_addr_t *priv = dev_get_priv(dev);
+ struct i2c_msg msg;
+
+ msg.addr = *priv;
+ msg.flags = I2C_M_STOP;
+ msg.len = len;
+ msg.buf = (u8 *) buf;
+
+ return dm_i2c_xfer(dev, &msg, 1);
+}
+
+static int atsha204a_recv(struct udevice *dev, u8 *buf, u8 len)
+{
+ fdt_addr_t *priv = dev_get_priv(dev);
+ struct i2c_msg msg;
+
+ msg.addr = *priv;
+ msg.flags = I2C_M_RD | I2C_M_STOP;
+ msg.len = len;
+ msg.buf = (u8 *) buf;
+
+ return dm_i2c_xfer(dev, &msg, 1);
+}
+
+static int atsha204a_recv_resp(struct udevice *dev,
+ struct atsha204a_resp *resp)
+{
+ int res;
+ u16 resp_crc, computed_crc;
+ u8 *p = (u8 *) resp;
+
+ res = atsha204a_recv(dev, p, 4);
+ if (res)
+ return res;
+
+ if (resp->length > 4) {
+ if (resp->length > sizeof(*resp))
+ return -EMSGSIZE;
+
+ res = atsha204a_recv(dev, p + 4, resp->length - 4);
+ if (res)
+ return res;
+ }
+
+ resp_crc = (u16) p[resp->length - 2]
+ | (((u16) p[resp->length - 1]) << 8);
+ computed_crc = atsha204a_crc16(p, resp->length - 2);
+
+ if (resp_crc != computed_crc) {
+ debug("Invalid checksum in ATSHA204A response\n");
+ return -EBADMSG;
+ }
+
+ return 0;
+}
+
+int atsha204a_wakeup(struct udevice *dev)
+{
+ u8 req[4];
+ struct atsha204a_resp resp;
+ int try, res;
+
+ debug("Waking up ATSHA204A\n");
+
+ for (try = 1; try <= 10; ++try) {
+ debug("Try %i... ", try);
+
+ memset(req, 0, 4);
+ res = atsha204a_send(dev, req, 4);
+ if (res) {
+ debug("failed on I2C send, trying again\n");
+ continue;
+ }
+
+ udelay(ATSHA204A_TWLO);
+
+ res = atsha204a_recv_resp(dev, &resp);
+ if (res) {
+ debug("failed on receiving response, ending\n");
+ return res;
+ }
+
+ if (resp.code != ATSHA204A_STATUS_AFTER_WAKE) {
+ debug ("failed (responce code = %02x), ending\n",
+ resp.code);
+ return -EBADMSG;
+ }
+
+ debug("success\n");
+ break;
+ }
+
+ return 0;
+}
+
+int atsha204a_idle(struct udevice *dev)
+{
+ int res;
+ u8 req = ATSHA204A_FUNC_IDLE;
+
+ res = atsha204a_send(dev, &req, 1);
+ if (res)
+ debug("Failed putting ATSHA204A idle\n");
+ return res;
+}
+
+int atsha204a_sleep(struct udevice *dev)
+{
+ int res;
+ u8 req = ATSHA204A_FUNC_IDLE;
+
+ res = atsha204a_send(dev, &req, 1);
+ if (res)
+ debug("Failed putting ATSHA204A to sleep\n");
+ return res;
+}
+
+static int atsha204a_transaction(struct udevice *dev, struct atsha204a_req *req,
+ struct atsha204a_resp *resp)
+{
+ int res, timeout = ATSHA204A_TRANSACTION_TIMEOUT;
+
+ res = atsha204a_send(dev, (u8 *) req, req->length + 1);
+ if (res) {
+ debug("ATSHA204A transaction send failed\n");
+ return -EBUSY;
+ }
+
+ do {
+ res = atsha204a_recv_resp(dev, resp);
+ if (!res || res == -EMSGSIZE || res == -EBADMSG)
+ break;
+
+ debug("ATSHA204A transaction polling for response "
+ "(timeout = %d)\n", timeout);
+
+ udelay(ATSHA204A_EXECTIME);
+ timeout -= ATSHA204A_EXECTIME;
+ } while (timeout > 0);
+
+ if (timeout <= 0) {
+ debug("ATSHA204A transaction timed out\n");
+ return -ETIMEDOUT;
+ }
+
+ return res;
+}
+
+static void atsha204a_req_crc32(struct atsha204a_req *req)
+{
+ u8 *p = (u8 *) req;
+ u16 computed_crc;
+ u16 *crc_ptr = (u16 *) &p[req->length - 1];
+
+ /* The buffer to crc16 starts at byte 1, not 0 */
+ computed_crc = atsha204a_crc16(p + 1, req->length - 2);
+
+ *crc_ptr = cpu_to_le16(computed_crc);
+}
+
+int atsha204a_read(struct udevice *dev, enum atsha204a_zone zone, bool read32,
+ u16 addr, u8 *buffer)
+{
+ int res, retry = ATSHA204A_TRANSACTION_RETRY;
+ struct atsha204a_req req;
+ struct atsha204a_resp resp;
+
+ req.function = ATSHA204A_FUNC_COMMAND;
+ req.length = 7;
+ req.command = ATSHA204A_CMD_READ;
+
+ req.param1 = (u8) zone;
+ if (read32)
+ req.param1 |= 0x80;
+
+ req.param2 = cpu_to_le16(addr);
+
+ atsha204a_req_crc32(&req);
+
+ do {
+ res = atsha204a_transaction(dev, &req, &resp);
+ if (!res)
+ break;
+
+ debug("ATSHA204A read retry (%d)\n", retry);
+ retry--;
+ atsha204a_wakeup(dev);
+ } while (retry >= 0);
+
+ if (res) {
+ debug("ATSHA204A read failed\n");
+ return res;
+ }
+
+ if (resp.length != (read32 ? 32 : 4) + 3) {
+ debug("ATSHA204A read bad response length (%d)\n",
+ resp.length);
+ return -EBADMSG;
+ }
+
+ memcpy(buffer, ((u8 *) &resp) + 1, read32 ? 32 : 4);
+
+ return 0;
+}
+
+int atsha204a_get_random(struct udevice *dev, u8 *buffer, size_t max)
+{
+ int res;
+ struct atsha204a_req req;
+ struct atsha204a_resp resp;
+
+ req.function = ATSHA204A_FUNC_COMMAND;
+ req.length = 7;
+ req.command = ATSHA204A_CMD_RANDOM;
+
+ req.param1 = 1;
+ req.param2 = 0;
+
+ /* We do not have to compute the checksum dynamically */
+ req.data[0] = 0x27;
+ req.data[1] = 0x47;
+
+ res = atsha204a_transaction(dev, &req, &resp);
+ if (res) {
+ debug("ATSHA204A random transaction failed\n");
+ return res;
+ }
+
+ memcpy(buffer, ((u8 *) &resp) + 1, max >= 32 ? 32 : max);
+ return 0;
+}
+
+static int atsha204a_ofdata_to_platdata(struct udevice *dev)
+{
+ fdt_addr_t *priv = dev_get_priv(dev);
+ fdt_addr_t addr;
+
+ addr = fdtdec_get_addr(gd->fdt_blob, dev_of_offset(dev), "reg");
+ if (addr == FDT_ADDR_T_NONE) {
+ debug("Can't get ATSHA204A I2C base address\n");
+ return -ENXIO;
+ }
+
+ *priv = addr;
+ return 0;
+}
+
+static const struct udevice_id atsha204a_ids[] = {
+ { .compatible = "atmel,atsha204a" },
+ { }
+};
+
+U_BOOT_DRIVER(atsha204) = {
+ .name = "atsha204",
+ .id = UCLASS_MISC,
+ .of_match = atsha204a_ids,
+ .ofdata_to_platdata = atsha204a_ofdata_to_platdata,
+ .priv_auto_alloc_size = sizeof(fdt_addr_t),
+};
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/sys_proto.h>
+#include <asm/mach-imx/sys_proto.h>
#define BO_CTRL_WR_UNLOCK 16
#define BM_CTRL_WR_UNLOCK 0xffff0000
{
struct rockchip_efuse_platdata *plat = dev_get_platdata(dev);
- plat->base = (void *)devfdt_get_addr(dev);
+ plat->base = (void *)dev_read_addr(dev);
return 0;
}
#include <hwconfig.h>
#include <mmc.h>
#include <part.h>
+#include <power/regulator.h>
#include <malloc.h>
#include <fsl_esdhc.h>
#include <fdt_support.h>
* @dev: pointer for the device
* @non_removable: 0: removable; 1: non-removable
* @wp_enable: 1: enable checking wp; 0: no check
+ * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
* @cd_gpio: gpio for card detection
* @wp_gpio: gpio for write protection
*/
struct udevice *dev;
int non_removable;
int wp_enable;
+ int vs18_enable;
#ifdef CONFIG_DM_GPIO
struct gpio_desc cd_gpio;
struct gpio_desc wp_gpio;
/* Set timout to the maximum value */
esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
-#ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
- esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
-#endif
+ if (priv->vs18_enable)
+ esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
return 0;
}
VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
#endif
+ if (priv->vs18_enable)
+ esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
+
writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
memset(&priv->cfg, 0, sizeof(priv->cfg));
priv->bus_width = cfg->max_bus_width;
priv->sdhc_clk = cfg->sdhc_clk;
priv->wp_enable = cfg->wp_enable;
+ priv->vs18_enable = cfg->vs18_enable;
return 0;
};
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
+ struct udevice *vqmmc_dev;
fdt_addr_t addr;
unsigned int val;
int ret;
if (ret)
priv->wp_enable = 0;
#endif
+
+ priv->vs18_enable = 0;
+
+#ifdef CONFIG_DM_REGULATOR
+ /*
+ * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
+ * otherwise, emmc will work abnormally.
+ */
+ ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
+ if (ret) {
+ dev_dbg(dev, "no vqmmc-supply\n");
+ } else {
+ ret = regulator_set_enable(vqmmc_dev, true);
+ if (ret) {
+ dev_err(dev, "fail to enable vqmmc-supply\n");
+ return ret;
+ }
+
+ if (regulator_get_value(vqmmc_dev) == 1800000)
+ priv->vs18_enable = 1;
+ }
+#endif
+
/*
* TODO:
* Because lack of clk driver, if SDHC clk is not enabled,
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/dma.h>
+#include <asm/mach-imx/dma.h>
#include <bouncebuf.h>
struct mxsmmc_priv {
unsigned char mac[RPMB_SZ_MAC];
unsigned char data[RPMB_SZ_DATA];
unsigned char nonce[RPMB_SZ_NONCE];
- unsigned long write_counter;
+ unsigned int write_counter;
unsigned short address;
unsigned short block_count;
unsigned short result;
static int sdhci_cdns_phy_init(struct sdhci_cdns_plat *plat,
const void *fdt, int nodeoffset)
{
- const u32 *prop;
+ const fdt32_t *prop;
int ret, i;
for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++) {
#include <common.h>
#include <dm.h>
#include <errno.h>
+#include <mmc.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch-tegra/tegra_mmc.h>
-#include <mmc.h>
DECLARE_GLOBAL_DATA_PTR;
cfg->name = dev->name;
- bus_width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
- "bus-width", 1);
+ bus_width = dev_read_u32_default(dev, "bus-width", 1);
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
cfg->host_caps = 0;
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
- priv->reg = (void *)devfdt_get_addr(dev);
+ priv->reg = (void *)dev_read_addr(dev);
ret = reset_get_by_name(dev, "sdhci", &priv->reset_ctl);
if (ret) {
return ret;
/* These GPIOs are optional */
- gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
- GPIOD_IS_IN);
- gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
- GPIOD_IS_IN);
- gpio_request_by_name(dev, "power-gpios", 0,
- &priv->pwr_gpio, GPIOD_IS_OUT);
+ gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
+ gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
+ gpio_request_by_name(dev, "power-gpios", 0, &priv->pwr_gpio,
+ GPIOD_IS_OUT);
if (dm_gpio_is_valid(&priv->pwr_gpio))
dm_gpio_set_value(&priv->pwr_gpio, 1);
* Nomadik SoC is currently supporting this fsmc_nand_switch_ecc()
* function, as it doesn't need to switch to a different ECC layout.
*/
- mtd = nand_info[nand_curr_device];
+ mtd = get_nand_dev_by_index(nand_curr_device);
nand = mtd_to_nand(mtd);
/* Setup the ecc configurations again */
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/regs-bch.h>
-#include <asm/imx-common/regs-gpmi.h>
+#include <asm/mach-imx/regs-bch.h>
+#include <asm/mach-imx/regs-gpmi.h>
#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/dma.h>
+#include <asm/mach-imx/dma.h>
#define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
}
/* Init the DMA controller. */
+ mxs_dma_init();
for (j = MXS_DMA_CHANNEL_AHB_APBH_GPMI0;
j <= MXS_DMA_CHANNEL_AHB_APBH_GPMI7; j++) {
ret = mxs_dma_init_channel(j);
int nand_curr_device = -1;
-
-struct mtd_info *nand_info[CONFIG_SYS_MAX_NAND_DEVICE];
+static struct mtd_info *nand_info[CONFIG_SYS_MAX_NAND_DEVICE];
#ifndef CONFIG_SYS_NAND_SELF_INIT
static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
static unsigned long total_nand_size; /* in kiB */
+struct mtd_info *get_nand_dev_by_index(int dev)
+{
+ if (dev < 0 || dev >= CONFIG_SYS_MAX_NAND_DEVICE || !nand_info[dev] ||
+ !nand_info[dev]->name)
+ return NULL;
+
+ return nand_info[dev];
+}
+
int nand_mtd_to_devnum(struct mtd_info *mtd)
{
int i;
- for (i = 0; i < ARRAY_SIZE(nand_info); i++) {
- if (mtd && nand_info[i] == mtd)
+ for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) {
+ if (mtd && get_nand_dev_by_index(i) == mtd)
return i;
}
int i;
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) {
- if (nand_info[i] != NULL) {
- nand_info_list[nand_devices_found] = nand_info[i];
+ struct mtd_info *mtd = get_nand_dev_by_index(i);
+ if (mtd != NULL) {
+ nand_info_list[nand_devices_found] = mtd;
nand_devices_found++;
}
}
/*
* Select the chip in the board/cpu specific driver
*/
- board_nand_select_device(mtd_to_nand(nand_info[nand_curr_device]),
+ board_nand_select_device(mtd_to_nand(get_nand_dev_by_index(nand_curr_device)),
nand_curr_device);
#endif
int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
{
struct nand_chip *nand;
- struct mtd_info *mtd;
+ struct mtd_info *mtd = get_nand_dev_by_index(nand_curr_device);
int err = 0;
- if (nand_curr_device < 0 ||
- nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
- !nand_info[nand_curr_device]) {
+ if (!mtd) {
printf("nand: error: no NAND devices found\n");
return -ENODEV;
}
- mtd = nand_info[nand_curr_device];
nand = mtd_to_nand(mtd);
nand->options |= NAND_OWN_BUFFERS;
nand->options &= ~NAND_SUBPAGE_READ;
}
xnand->nand_base = (void __iomem *)ZYNQ_NAND_BASEADDR;
- mtd = (struct mtd_info *)&nand_info[0];
+ mtd = get_nand_dev_by_index(0);
nand_chip->priv = xnand;
mtd->priv = nand_chip;
config MTD_UBI
bool "Enable UBI - Unsorted block images"
select CRC32
- select RBTREE if ARCH_SUNXI
+ select RBTREE
+ select MTD_PARTITIONS
help
UBI is a software layer above MTD layer which admits of LVM-like
logical volumes on top of MTD devices, hides some complexities of
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/sys_proto.h>
+#include <asm/mach-imx/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
if (ret)
return ret;
- bus = fec_get_miibus((uint32_t)priv->eth, dev_id);
- if (!bus)
- goto err_mii;
-
- priv->bus = bus;
- priv->xcv_type = CONFIG_FEC_XCV_TYPE;
- priv->interface = pdata->phy_interface;
- ret = fec_phy_init(priv, dev);
- if (ret)
- goto err_phy;
-
/* Reset chip. */
writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET,
&priv->eth->ecntrl);
fec_reg_setup(priv);
priv->dev_id = (dev_id == -1) ? 0 : dev_id;
+ bus = fec_get_miibus(dev, dev_id);
+ if (!bus) {
+ ret = -ENOMEM;
+ goto err_mii;
+ }
+
+ priv->bus = bus;
+ priv->xcv_type = CONFIG_FEC_XCV_TYPE;
+ priv->interface = pdata->phy_interface;
+ ret = fec_phy_init(priv, dev);
+ if (ret)
+ goto err_phy;
+
return 0;
err_timeout:
size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
- rc = nand_read(nand_info[0], (loff_t)CONFIG_SYS_FMAN_FW_ADDR,
+ rc = nand_read(get_nand_dev_by_index(0),
+ (loff_t)CONFIG_SYS_FMAN_FW_ADDR,
&fw_length, (u_char *)addr);
if (rc == -EUCLEAN) {
printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
#include <commproc.h>
#include <malloc.h>
#include <net.h>
+#include <netdev.h>
#include <asm/io.h>
#include <phy.h>
size_t fw_length = CONFIG_CORTINA_FW_LENGTH;
addr = malloc(CONFIG_CORTINA_FW_LENGTH);
- ret = nand_read(nand_info[0], (loff_t)CONFIG_CORTINA_FW_ADDR,
+ ret = nand_read(get_nand_dev_by_index(0),
+ (loff_t)CONFIG_CORTINA_FW_ADDR,
&fw_length, (u_char *)addr);
if (ret == -EUCLEAN) {
printf("NAND read of Cortina firmware at 0x%x failed %d\n",
#include <clk.h>
#include <dm.h>
#include <errno.h>
-#include <fdtdec.h>
#include <malloc.h>
#include <pci.h>
#include <power-domain.h>
#include <asm/io.h>
#include <asm/gpio.h>
+#include <linux/ioport.h>
#include <linux/list.h>
#ifndef CONFIG_TEGRA186
struct tegra_pcie {
struct pci_controller hose;
- struct fdt_resource pads;
- struct fdt_resource afi;
- struct fdt_resource cs;
+ struct resource pads;
+ struct resource afi;
+ struct resource cs;
struct list_head ports;
unsigned long xbar;
return 0;
}
-static int tegra_pcie_port_parse_dt(const void *fdt, int node,
- struct tegra_pcie_port *port)
+static int tegra_pcie_port_parse_dt(ofnode node, struct tegra_pcie_port *port)
{
const u32 *addr;
int len;
- addr = fdt_getprop(fdt, node, "assigned-addresses", &len);
+ addr = ofnode_get_property(node, "assigned-addresses", &len);
if (!addr) {
error("property \"assigned-addresses\" not found");
return -FDT_ERR_NOTFOUND;
return 0;
}
-static int tegra_pcie_get_xbar_config(const void *fdt, int node, u32 lanes,
+static int tegra_pcie_get_xbar_config(ofnode node, u32 lanes,
enum tegra_pci_id id, unsigned long *xbar)
{
switch (id) {
return -FDT_ERR_NOTFOUND;
}
-static int tegra_pcie_parse_port_info(const void *fdt, int node,
- unsigned int *index,
- unsigned int *lanes)
+static int tegra_pcie_parse_port_info(ofnode node, uint *index, uint *lanes)
{
struct fdt_pci_addr addr;
int err;
- err = fdtdec_get_int(fdt, node, "nvidia,num-lanes", 0);
+ err = ofnode_read_u32_default(node, "nvidia,num-lanes", -1);
if (err < 0) {
error("failed to parse \"nvidia,num-lanes\" property");
return err;
*lanes = err;
- err = fdtdec_get_pci_addr(fdt, node, 0, "reg", &addr);
+ err = ofnode_read_pci_addr(node, 0, "reg", &addr);
if (err < 0) {
error("failed to parse \"reg\" property");
return err;
return 0;
}
-static int tegra_pcie_parse_dt(const void *fdt, int node, enum tegra_pci_id id,
+static int tegra_pcie_parse_dt(struct udevice *dev, enum tegra_pci_id id,
struct tegra_pcie *pcie)
{
- int err, subnode;
+ ofnode subnode;
u32 lanes = 0;
+ int err;
- err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "pads",
- &pcie->pads);
+ err = dev_read_resource(dev, 0, &pcie->pads);
if (err < 0) {
error("resource \"pads\" not found");
return err;
}
- err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "afi",
- &pcie->afi);
+ err = dev_read_resource(dev, 1, &pcie->afi);
if (err < 0) {
error("resource \"afi\" not found");
return err;
}
- err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "cs",
- &pcie->cs);
+ err = dev_read_resource(dev, 2, &pcie->cs);
if (err < 0) {
error("resource \"cs\" not found");
return err;
}
#endif
- fdt_for_each_subnode(subnode, fdt, node) {
+ dev_for_each_subnode(subnode, dev) {
unsigned int index = 0, num_lanes = 0;
struct tegra_pcie_port *port;
- err = tegra_pcie_parse_port_info(fdt, subnode, &index,
- &num_lanes);
+ err = tegra_pcie_parse_port_info(subnode, &index, &num_lanes);
if (err < 0) {
error("failed to obtain root port info");
continue;
lanes |= num_lanes << (index << 3);
- if (!fdtdec_get_is_enabled(fdt, subnode))
+ if (!ofnode_is_available(subnode))
continue;
port = malloc(sizeof(*port));
port->num_lanes = num_lanes;
port->index = index;
- err = tegra_pcie_port_parse_dt(fdt, subnode, port);
+ err = tegra_pcie_port_parse_dt(subnode, port);
if (err < 0) {
free(port);
continue;
port->pcie = pcie;
}
- err = tegra_pcie_get_xbar_config(fdt, node, lanes, id, &pcie->xbar);
+ err = tegra_pcie_get_xbar_config(dev_ofnode(dev), lanes, id,
+ &pcie->xbar);
if (err < 0) {
error("invalid lane configuration");
return err;
/* BAR 0: type 1 extended configuration space */
fpci = 0xfe100000;
- size = fdt_resource_size(&pcie->cs);
+ size = resource_size(&pcie->cs);
axi = pcie->cs.start;
afi_writel(pcie, axi, AFI_AXI_BAR0_START);
INIT_LIST_HEAD(&pcie->ports);
- if (tegra_pcie_parse_dt(gd->fdt_blob, dev_of_offset(dev), id, pcie))
+ if (tegra_pcie_parse_dt(dev, id, pcie))
return -EINVAL;
return 0;
This select a dummy sandbox PHY driver. It used only to implement
the unit tests for the phy framework
+config NOP_PHY
+ bool "NOP PHY driver"
+ depends on PHY
+ help
+ Support for a no-op PHY driver (stubbed PHY driver).
+
+ This is useful when a driver uses the PHY framework but no real PHY
+ hardware exists.
+
+config SPL_NOP_PHY
+ bool "NOP PHY driver in SPL"
+ depends on SPL_PHY
+ help
+ Support for a no-op PHY driver (stubbed PHY driver) in the SPL.
+
+ This is useful when a driver uses the PHY framework but no real PHY
+ hardware exists.
+
config PIPE3_PHY
bool "Support omap's PIPE3 PHY"
depends on PHY && ARCH_OMAP2PLUS
#
obj-$(CONFIG_$(SPL_)PHY) += phy-uclass.o
+obj-$(CONFIG_$(SPL_)NOP_PHY) += nop-phy.o
obj-$(CONFIG_PHY_SANDBOX) += sandbox-phy.o
obj-$(CONFIG_$(SPL_)PIPE3_PHY) += ti-pipe3-phy.o
--- /dev/null
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Written by Jean-Jacques Hiblot <jjhiblot@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device.h>
+#include <generic-phy.h>
+
+static const struct udevice_id nop_phy_ids[] = {
+ { .compatible = "nop-phy" },
+ { }
+};
+
+static struct phy_ops nop_phy_ops = {
+};
+
+U_BOOT_DRIVER(nop_phy) = {
+ .name = "nop_phy",
+ .id = UCLASS_PHY,
+ .of_match = nop_phy_ids,
+ .ops = &nop_phy_ops,
+};
debug("%s(dev=%p, index=%d, phy=%p)\n", __func__, dev, index, phy);
assert(phy);
+ phy->dev = NULL;
ret = dev_read_phandle_with_args(dev, "phys", "#phy-cells", 0, index,
&args);
if (ret) {
FUNCTION(i2c_slave_ao),
};
+static struct meson_bank meson_gxbb_periphs_banks[] = {
+ /* name first last pullen pull dir out in */
+ BANK("X", PIN(GPIOX_0, EE_OFF), PIN(GPIOX_22, EE_OFF), 4, 0, 4, 0, 12, 0, 13, 0, 14, 0),
+ BANK("Y", PIN(GPIOY_0, EE_OFF), PIN(GPIOY_16, EE_OFF), 1, 0, 1, 0, 3, 0, 4, 0, 5, 0),
+ BANK("DV", PIN(GPIODV_0, EE_OFF), PIN(GPIODV_29, EE_OFF), 0, 0, 0, 0, 0, 0, 1, 0, 2, 0),
+ BANK("H", PIN(GPIOH_0, EE_OFF), PIN(GPIOH_3, EE_OFF), 1, 20, 1, 20, 3, 20, 4, 20, 5, 20),
+ BANK("Z", PIN(GPIOZ_0, EE_OFF), PIN(GPIOZ_15, EE_OFF), 3, 0, 3, 0, 9, 0, 10, 0, 11, 0),
+ BANK("CARD", PIN(CARD_0, EE_OFF), PIN(CARD_6, EE_OFF), 2, 20, 2, 20, 6, 20, 7, 20, 8, 20),
+ BANK("BOOT", PIN(BOOT_0, EE_OFF), PIN(BOOT_17, EE_OFF), 2, 0, 2, 0, 6, 0, 7, 0, 8, 0),
+ BANK("CLK", PIN(GPIOCLK_0, EE_OFF), PIN(GPIOCLK_3, EE_OFF), 3, 28, 3, 28, 9, 28, 10, 28, 11, 28),
+};
+
+static struct meson_bank meson_gxbb_aobus_banks[] = {
+ /* name first last pullen pull dir out in */
+ BANK("AO", PIN(GPIOAO_0, 0), PIN(GPIOAO_13, 0), 0, 0, 0, 16, 0, 0, 0, 16, 1, 0),
+};
+
struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data = {
.name = "periphs-banks",
.pin_base = 14,
.groups = meson_gxbb_periphs_groups,
.funcs = meson_gxbb_periphs_functions,
+ .banks = meson_gxbb_periphs_banks,
.num_pins = 120,
.num_groups = ARRAY_SIZE(meson_gxbb_periphs_groups),
.num_funcs = ARRAY_SIZE(meson_gxbb_periphs_functions),
+ .num_banks = ARRAY_SIZE(meson_gxbb_periphs_banks),
};
struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = {
.pin_base = 0,
.groups = meson_gxbb_aobus_groups,
.funcs = meson_gxbb_aobus_functions,
+ .banks = meson_gxbb_aobus_banks,
.num_pins = 14,
.num_groups = ARRAY_SIZE(meson_gxbb_aobus_groups),
.num_funcs = ARRAY_SIZE(meson_gxbb_aobus_functions),
+ .num_banks = ARRAY_SIZE(meson_gxbb_aobus_banks),
};
static const struct udevice_id meson_gxbb_pinctrl_match[] = {
#include <common.h>
#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
#include <dm/pinctrl.h>
#include <fdt_support.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sizes.h>
+#include <asm/gpio.h>
#include "pinctrl-meson.h"
.set_state = pinctrl_generic_set_state,
};
+static int meson_gpio_calc_reg_and_bit(struct udevice *dev, unsigned int offset,
+ enum meson_reg_type reg_type,
+ unsigned int *reg, unsigned int *bit)
+{
+ struct meson_pinctrl *priv = dev_get_priv(dev->parent);
+ struct meson_bank *bank = NULL;
+ struct meson_reg_desc *desc;
+ unsigned int pin;
+ int i;
+
+ pin = priv->data->pin_base + offset;
+
+ for (i = 0; i < priv->data->num_banks; i++) {
+ if (pin >= priv->data->banks[i].first &&
+ pin <= priv->data->banks[i].last) {
+ bank = &priv->data->banks[i];
+ break;
+ }
+ }
+
+ if (!bank)
+ return -EINVAL;
+
+ desc = &bank->regs[reg_type];
+ *reg = desc->reg * 4;
+ *bit = desc->bit + pin - bank->first;
+
+ return 0;
+}
+
+static int meson_gpio_get(struct udevice *dev, unsigned int offset)
+{
+ struct meson_pinctrl *priv = dev_get_priv(dev->parent);
+ unsigned int reg, bit;
+ int ret;
+
+ ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_IN, ®, &bit);
+ if (ret)
+ return ret;
+
+ return !!(readl(priv->reg_gpio + reg) & BIT(bit));
+}
+
+static int meson_gpio_set(struct udevice *dev, unsigned int offset, int value)
+{
+ struct meson_pinctrl *priv = dev_get_priv(dev->parent);
+ unsigned int reg, bit;
+ int ret;
+
+ ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_OUT, ®, &bit);
+ if (ret)
+ return ret;
+
+ clrsetbits_le32(priv->reg_gpio + reg, BIT(bit), value ? BIT(bit) : 0);
+
+ return 0;
+}
+
+static int meson_gpio_get_direction(struct udevice *dev, unsigned int offset)
+{
+ struct meson_pinctrl *priv = dev_get_priv(dev->parent);
+ unsigned int reg, bit, val;
+ int ret;
+
+ ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_DIR, ®, &bit);
+ if (ret)
+ return ret;
+
+ val = readl(priv->reg_gpio + reg);
+
+ return (val & BIT(bit)) ? GPIOF_INPUT : GPIOF_OUTPUT;
+}
+
+static int meson_gpio_direction_input(struct udevice *dev, unsigned int offset)
+{
+ struct meson_pinctrl *priv = dev_get_priv(dev->parent);
+ unsigned int reg, bit;
+ int ret;
+
+ ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_DIR, ®, &bit);
+ if (ret)
+ return ret;
+
+ clrsetbits_le32(priv->reg_gpio + reg, BIT(bit), 1);
+
+ return 0;
+}
+
+static int meson_gpio_direction_output(struct udevice *dev,
+ unsigned int offset, int value)
+{
+ struct meson_pinctrl *priv = dev_get_priv(dev->parent);
+ unsigned int reg, bit;
+ int ret;
+
+ ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_DIR, ®, &bit);
+ if (ret)
+ return ret;
+
+ clrsetbits_le32(priv->reg_gpio + reg, BIT(bit), 0);
+
+ ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_OUT, ®, &bit);
+ if (ret)
+ return ret;
+
+ clrsetbits_le32(priv->reg_gpio + reg, BIT(bit), value ? BIT(bit) : 0);
+
+ return 0;
+}
+
+static int meson_gpio_probe(struct udevice *dev)
+{
+ struct meson_pinctrl *priv = dev_get_priv(dev->parent);
+ struct gpio_dev_priv *uc_priv;
+
+ uc_priv = dev_get_uclass_priv(dev);
+ uc_priv->bank_name = priv->data->name;
+ uc_priv->gpio_count = priv->data->num_pins;
+
+ return 0;
+}
+
+static const struct dm_gpio_ops meson_gpio_ops = {
+ .set_value = meson_gpio_set,
+ .get_value = meson_gpio_get,
+ .get_function = meson_gpio_get_direction,
+ .direction_input = meson_gpio_direction_input,
+ .direction_output = meson_gpio_direction_output,
+};
+
+static struct driver meson_gpio_driver = {
+ .name = "meson-gpio",
+ .id = UCLASS_GPIO,
+ .probe = meson_gpio_probe,
+ .ops = &meson_gpio_ops,
+};
+
static fdt_addr_t parse_address(int offset, const char *name, int na, int ns)
{
int index, len = 0;
int meson_pinctrl_probe(struct udevice *dev)
{
struct meson_pinctrl *priv = dev_get_priv(dev);
+ struct uclass_driver *drv;
+ struct udevice *gpio_dev;
fdt_addr_t addr;
int node, gpio = -1, len;
int na, ns;
+ char *name;
na = fdt_address_cells(gd->fdt_blob, dev_of_offset(dev->parent));
if (na < 1) {
addr = parse_address(gpio, "mux", na, ns);
if (addr == FDT_ADDR_T_NONE) {
- debug("mux not found\n");
+ debug("mux address not found\n");
return -EINVAL;
}
-
priv->reg_mux = (void __iomem *)addr;
+
+ addr = parse_address(gpio, "gpio", na, ns);
+ if (addr == FDT_ADDR_T_NONE) {
+ debug("gpio address not found\n");
+ return -EINVAL;
+ }
+ priv->reg_gpio = (void __iomem *)addr;
priv->data = (struct meson_pinctrl_data *)dev_get_driver_data(dev);
+ /* Lookup GPIO driver */
+ drv = lists_uclass_lookup(UCLASS_GPIO);
+ if (!drv) {
+ puts("Cannot find GPIO driver\n");
+ return -ENOENT;
+ }
+
+ name = calloc(1, 32);
+ sprintf(name, "meson-gpio");
+
+ /* Create child device UCLASS_GPIO and bind it */
+ device_bind(dev, &meson_gpio_driver, name, NULL, gpio, &gpio_dev);
+ dev_set_of_offset(gpio_dev, gpio);
+
return 0;
}
const char *name;
struct meson_pmx_group *groups;
struct meson_pmx_func *funcs;
+ struct meson_bank *banks;
unsigned int pin_base;
unsigned int num_pins;
unsigned int num_groups;
unsigned int num_funcs;
+ unsigned int num_banks;
};
struct meson_pinctrl {
struct meson_pinctrl_data *data;
void __iomem *reg_mux;
+ void __iomem *reg_gpio;
+};
+
+/**
+ * struct meson_reg_desc - a register descriptor
+ *
+ * @reg: register offset in the regmap
+ * @bit: bit index in register
+ *
+ * The structure describes the information needed to control pull,
+ * pull-enable, direction, etc. for a single pin
+ */
+struct meson_reg_desc {
+ unsigned int reg;
+ unsigned int bit;
+};
+
+/**
+ * enum meson_reg_type - type of registers encoded in @meson_reg_desc
+ */
+enum meson_reg_type {
+ REG_PULLEN,
+ REG_PULL,
+ REG_DIR,
+ REG_OUT,
+ REG_IN,
+ NUM_REG,
+};
+
+/**
+ * struct meson bank
+ *
+ * @name: bank name
+ * @first: first pin of the bank
+ * @last: last pin of the bank
+ * @regs: array of register descriptors
+ *
+ * A bank represents a set of pins controlled by a contiguous set of
+ * bits in the domain registers. The structure specifies which bits in
+ * the regmap control the different functionalities. Each member of
+ * the @regs array refers to the first pin of the bank.
+ */
+struct meson_bank {
+ const char *name;
+ unsigned int first;
+ unsigned int last;
+ struct meson_reg_desc regs[NUM_REG];
};
#define PIN(x, b) (b + x)
.num_groups = ARRAY_SIZE(fn ## _groups), \
}
+#define BANK(n, f, l, per, peb, pr, pb, dr, db, or, ob, ir, ib) \
+ { \
+ .name = n, \
+ .first = f, \
+ .last = l, \
+ .regs = { \
+ [REG_PULLEN] = { per, peb }, \
+ [REG_PULL] = { pr, pb }, \
+ [REG_DIR] = { dr, db }, \
+ [REG_OUT] = { or, ob }, \
+ [REG_IN] = { ir, ib }, \
+ }, \
+ }
+
#define MESON_PIN(x, b) PINCTRL_PIN(PIN(x, b), #x)
extern const struct pinctrl_ops meson_pinctrl_ops;
(GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(6)) |
(GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(7)));
+ rk_clrsetreg(&grf->gpio4bl_iomux,
+ GPIO4B1_MASK << GPIO4B1_SHIFT,
+ GPIO4B1_MAC_TXCLK << GPIO4B1_SHIFT);
+
/* switch GPIO4B1 to 12ma drive-strength */
rk_clrsetreg(&grf->gpio1_e[3][1],
GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(1),
GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(1));
- /* Set pull normal for GPIO4B1, pull up for GPIO4B0 */
+ /* Set pull normal for GPIO4B1 */
rk_clrsetreg(&grf->gpio1_p[3][1],
- (GPIO_PULL_MASK << GPIO_PULL_SHIFT(0)) |
(GPIO_PULL_MASK << GPIO_PULL_SHIFT(1)),
- (GPIO_PULL_UP << GPIO_PULL_SHIFT(0)) |
(GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(1)));
break;
value |= (mask << (shift + 16)) | (muxval << shift);
writel(value, addr);
- /* Handle pullup/pulldown */
+ /* Handle pullup/pulldown/drive-strength */
if (flags) {
uint val = 0;
val = 1;
else if (flags & (1 << PIN_CONFIG_BIAS_PULL_DOWN))
val = 2;
+ else if (flags & (1 << PIN_CONFIG_DRIVE_STRENGTH))
+ val = 3;
+
shift = (index & 7) * 2;
ind = index >> 3;
if (banknum == 0)
addr = &priv->pmu->gpio0pull[ind];
+ else if (flags & (1 << PIN_CONFIG_DRIVE_STRENGTH))
+ addr = &priv->grf->gpio1_e[banknum - 1][ind];
else
addr = &priv->grf->gpio1_p[banknum - 1][ind];
debug("%s: addr=%p, val=%x, shift=%x\n", __func__, addr, val,
if (flags < 0)
return flags;
+ if (fdtdec_get_int(blob, pcfg_node, "drive-strength", 0) == 12)
+ flags |= 1 << PIN_CONFIG_DRIVE_STRENGTH;
+
ret = rk3288_pinctrl_set_pins(dev, ptr[0], ptr[1], ptr[2],
flags);
if (ret)
UNIPHIER_PINCTRL_GROUP(i2c3),
UNIPHIER_PINCTRL_GROUP(i2c4),
UNIPHIER_PINCTRL_GROUP(nand),
- UNIPHIER_PINCTRL_GROUP_SPL(system_bus),
- UNIPHIER_PINCTRL_GROUP_SPL(system_bus_cs1),
- UNIPHIER_PINCTRL_GROUP_SPL(uart0),
- UNIPHIER_PINCTRL_GROUP_SPL(uart1),
- UNIPHIER_PINCTRL_GROUP_SPL(uart2),
- UNIPHIER_PINCTRL_GROUP_SPL(uart3),
+ UNIPHIER_PINCTRL_GROUP(system_bus),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
+ UNIPHIER_PINCTRL_GROUP(uart0),
+ UNIPHIER_PINCTRL_GROUP(uart1),
+ UNIPHIER_PINCTRL_GROUP(uart2),
+ UNIPHIER_PINCTRL_GROUP(uart3),
UNIPHIER_PINCTRL_GROUP(usb0),
UNIPHIER_PINCTRL_GROUP(usb1),
UNIPHIER_PINCTRL_GROUP(usb2),
UNIPHIER_PINMUX_FUNCTION(i2c3),
UNIPHIER_PINMUX_FUNCTION(i2c4),
UNIPHIER_PINMUX_FUNCTION(nand),
- UNIPHIER_PINMUX_FUNCTION_SPL(system_bus),
- UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
- UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
- UNIPHIER_PINMUX_FUNCTION_SPL(uart2),
- UNIPHIER_PINMUX_FUNCTION_SPL(uart3),
+ UNIPHIER_PINMUX_FUNCTION(system_bus),
+ UNIPHIER_PINMUX_FUNCTION(uart0),
+ UNIPHIER_PINMUX_FUNCTION(uart1),
+ UNIPHIER_PINMUX_FUNCTION(uart2),
+ UNIPHIER_PINMUX_FUNCTION(uart3),
UNIPHIER_PINMUX_FUNCTION(usb0),
UNIPHIER_PINMUX_FUNCTION(usb1),
UNIPHIER_PINMUX_FUNCTION(usb2),
UNIPHIER_PINCTRL_GROUP(i2c4),
UNIPHIER_PINCTRL_GROUP(nand),
UNIPHIER_PINCTRL_GROUP(sd),
- UNIPHIER_PINCTRL_GROUP_SPL(system_bus),
- UNIPHIER_PINCTRL_GROUP_SPL(system_bus_cs1),
- UNIPHIER_PINCTRL_GROUP_SPL(uart0),
- UNIPHIER_PINCTRL_GROUP_SPL(uart1),
- UNIPHIER_PINCTRL_GROUP_SPL(uart2),
- UNIPHIER_PINCTRL_GROUP_SPL(uart3),
+ UNIPHIER_PINCTRL_GROUP(system_bus),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
+ UNIPHIER_PINCTRL_GROUP(uart0),
+ UNIPHIER_PINCTRL_GROUP(uart1),
+ UNIPHIER_PINCTRL_GROUP(uart2),
+ UNIPHIER_PINCTRL_GROUP(uart3),
UNIPHIER_PINCTRL_GROUP(usb0),
UNIPHIER_PINCTRL_GROUP(usb1),
UNIPHIER_PINCTRL_GROUP(usb2),
UNIPHIER_PINMUX_FUNCTION(i2c4),
UNIPHIER_PINMUX_FUNCTION(nand),
UNIPHIER_PINMUX_FUNCTION(sd),
- UNIPHIER_PINMUX_FUNCTION_SPL(system_bus),
- UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
- UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
- UNIPHIER_PINMUX_FUNCTION_SPL(uart2),
- UNIPHIER_PINMUX_FUNCTION_SPL(uart3),
+ UNIPHIER_PINMUX_FUNCTION(system_bus),
+ UNIPHIER_PINMUX_FUNCTION(uart0),
+ UNIPHIER_PINMUX_FUNCTION(uart1),
+ UNIPHIER_PINMUX_FUNCTION(uart2),
+ UNIPHIER_PINMUX_FUNCTION(uart3),
UNIPHIER_PINMUX_FUNCTION(usb0),
UNIPHIER_PINMUX_FUNCTION(usb1),
UNIPHIER_PINMUX_FUNCTION(usb2),
UNIPHIER_PINCTRL_GROUP(i2c3),
UNIPHIER_PINCTRL_GROUP(nand),
UNIPHIER_PINCTRL_GROUP(sd),
- UNIPHIER_PINCTRL_GROUP_SPL(system_bus),
- UNIPHIER_PINCTRL_GROUP_SPL(system_bus_cs1),
- UNIPHIER_PINCTRL_GROUP_SPL(uart0),
- UNIPHIER_PINCTRL_GROUP_SPL(uart1),
- UNIPHIER_PINCTRL_GROUP_SPL(uart2),
- UNIPHIER_PINCTRL_GROUP_SPL(uart3),
+ UNIPHIER_PINCTRL_GROUP(system_bus),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
+ UNIPHIER_PINCTRL_GROUP(uart0),
+ UNIPHIER_PINCTRL_GROUP(uart1),
+ UNIPHIER_PINCTRL_GROUP(uart2),
+ UNIPHIER_PINCTRL_GROUP(uart3),
UNIPHIER_PINCTRL_GROUP(usb0),
UNIPHIER_PINCTRL_GROUP(usb1),
UNIPHIER_PINCTRL_GROUP(usb2),
UNIPHIER_PINMUX_FUNCTION(i2c3),
UNIPHIER_PINMUX_FUNCTION(nand),
UNIPHIER_PINMUX_FUNCTION(sd),
- UNIPHIER_PINMUX_FUNCTION_SPL(system_bus),
- UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
- UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
- UNIPHIER_PINMUX_FUNCTION_SPL(uart2),
- UNIPHIER_PINMUX_FUNCTION_SPL(uart3),
+ UNIPHIER_PINMUX_FUNCTION(system_bus),
+ UNIPHIER_PINMUX_FUNCTION(uart0),
+ UNIPHIER_PINMUX_FUNCTION(uart1),
+ UNIPHIER_PINMUX_FUNCTION(uart2),
+ UNIPHIER_PINMUX_FUNCTION(uart3),
UNIPHIER_PINMUX_FUNCTION(usb0),
UNIPHIER_PINMUX_FUNCTION(usb1),
UNIPHIER_PINMUX_FUNCTION(usb2),
obj-$(CONFIG_PMIC_S2MPS11) += s2mps11.o
obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o
obj-$(CONFIG_PMIC_ACT8846) += act8846.o
-obj-$(CONFIG_PMIC_AS3722) += as3722.o
+obj-$(CONFIG_PMIC_AS3722) += as3722.o as3722_gpio.o
obj-$(CONFIG_PMIC_MAX8997) += max8997.o
obj-$(CONFIG_PMIC_PM8916) += pm8916.o
obj-$(CONFIG_PMIC_RK8XX) += rk8xx.o
#include <errno.h>
#include <fdtdec.h>
#include <i2c.h>
-
+#include <dm/lists.h>
#include <power/as3722.h>
+#include <power/pmic.h>
-#define AS3722_SD_VOLTAGE(n) (0x00 + (n))
-#define AS3722_GPIO_CONTROL(n) (0x08 + (n))
-#define AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH (1 << 0)
-#define AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDL (7 << 0)
-#define AS3722_GPIO_CONTROL_INVERT (1 << 7)
-#define AS3722_LDO_VOLTAGE(n) (0x10 + (n))
-#define AS3722_GPIO_SIGNAL_OUT 0x20
-#define AS3722_SD_CONTROL 0x4d
-#define AS3722_LDO_CONTROL 0x4e
-#define AS3722_ASIC_ID1 0x90
-#define AS3722_DEVICE_ID 0x0c
-#define AS3722_ASIC_ID2 0x91
-
-int as3722_read(struct udevice *pmic, u8 reg, u8 *value)
-{
- int err;
-
- err = dm_i2c_read(pmic, reg, value, 1);
- if (err < 0)
- return err;
-
- return 0;
-}
+#define AS3722_NUM_OF_REGS 0x92
-int as3722_write(struct udevice *pmic, u8 reg, u8 value)
+static int as3722_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
{
- int err;
+ int ret;
- err = dm_i2c_write(pmic, reg, &value, 1);
- if (err < 0)
- return err;
+ ret = dm_i2c_read(dev, reg, buff, len);
+ if (ret < 0)
+ return ret;
return 0;
}
-static int as3722_read_id(struct udevice *pmic, u8 *id, u8 *revision)
+static int as3722_write(struct udevice *dev, uint reg, const uint8_t *buff,
+ int len)
{
- int err;
+ int ret;
- err = as3722_read(pmic, AS3722_ASIC_ID1, id);
- if (err) {
- error("failed to read ID1 register: %d", err);
- return err;
- }
-
- err = as3722_read(pmic, AS3722_ASIC_ID2, revision);
- if (err) {
- error("failed to read ID2 register: %d", err);
- return err;
- }
+ ret = dm_i2c_write(dev, reg, buff, len);
+ if (ret < 0)
+ return ret;
return 0;
}
-int as3722_sd_enable(struct udevice *pmic, unsigned int sd)
+static int as3722_read_id(struct udevice *dev, uint *idp, uint *revisionp)
{
- u8 value;
- int err;
-
- if (sd > 6)
- return -EINVAL;
+ int ret;
- err = as3722_read(pmic, AS3722_SD_CONTROL, &value);
- if (err) {
- error("failed to read SD control register: %d", err);
- return err;
+ ret = pmic_reg_read(dev, AS3722_ASIC_ID1);
+ if (ret < 0) {
+ error("failed to read ID1 register: %d", ret);
+ return ret;
}
+ *idp = ret;
- value |= 1 << sd;
-
- err = as3722_write(pmic, AS3722_SD_CONTROL, value);
- if (err < 0) {
- error("failed to write SD control register: %d", err);
- return err;
+ ret = pmic_reg_read(dev, AS3722_ASIC_ID2);
+ if (ret < 0) {
+ error("failed to read ID2 register: %d", ret);
+ return ret;
}
+ *revisionp = ret;
return 0;
}
-int as3722_sd_set_voltage(struct udevice *pmic, unsigned int sd, u8 value)
+/* TODO(treding@nvidia.com): Add proper regulator support to avoid this */
+int as3722_sd_set_voltage(struct udevice *dev, unsigned int sd, u8 value)
{
- int err;
+ int ret;
if (sd > 6)
return -EINVAL;
- err = as3722_write(pmic, AS3722_SD_VOLTAGE(sd), value);
- if (err < 0) {
- error("failed to write SD%u voltage register: %d", sd, err);
- return err;
+ ret = pmic_reg_write(dev, AS3722_SD_VOLTAGE(sd), value);
+ if (ret < 0) {
+ error("failed to write SD%u voltage register: %d", sd, ret);
+ return ret;
}
return 0;
}
-int as3722_ldo_enable(struct udevice *pmic, unsigned int ldo)
+int as3722_ldo_set_voltage(struct udevice *dev, unsigned int ldo, u8 value)
{
- u8 value;
- int err;
+ int ret;
if (ldo > 11)
return -EINVAL;
- err = as3722_read(pmic, AS3722_LDO_CONTROL, &value);
- if (err) {
- error("failed to read LDO control register: %d", err);
- return err;
- }
-
- value |= 1 << ldo;
-
- err = as3722_write(pmic, AS3722_LDO_CONTROL, value);
- if (err < 0) {
- error("failed to write LDO control register: %d", err);
- return err;
- }
-
- return 0;
-}
-
-int as3722_ldo_set_voltage(struct udevice *pmic, unsigned int ldo, u8 value)
-{
- int err;
-
- if (ldo > 11)
- return -EINVAL;
-
- err = as3722_write(pmic, AS3722_LDO_VOLTAGE(ldo), value);
- if (err < 0) {
+ ret = pmic_reg_write(dev, AS3722_LDO_VOLTAGE(ldo), value);
+ if (ret < 0) {
error("failed to write LDO%u voltage register: %d", ldo,
- err);
- return err;
+ ret);
+ return ret;
}
return 0;
}
-int as3722_gpio_configure(struct udevice *pmic, unsigned int gpio,
- unsigned long flags)
+static int as3722_probe(struct udevice *dev)
{
- u8 value = 0;
- int err;
+ uint id, revision;
+ int ret;
- if (flags & AS3722_GPIO_OUTPUT_VDDH)
- value |= AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH;
-
- if (flags & AS3722_GPIO_INVERT)
- value |= AS3722_GPIO_CONTROL_INVERT;
-
- err = as3722_write(pmic, AS3722_GPIO_CONTROL(gpio), value);
- if (err) {
- error("failed to configure GPIO#%u: %d", gpio, err);
- return err;
+ ret = as3722_read_id(dev, &id, &revision);
+ if (ret < 0) {
+ error("failed to read ID: %d", ret);
+ return ret;
}
- return 0;
-}
-
-static int as3722_gpio_set(struct udevice *pmic, unsigned int gpio,
- unsigned int level)
-{
- const char *l;
- u8 value;
- int err;
-
- if (gpio > 7)
- return -EINVAL;
-
- err = as3722_read(pmic, AS3722_GPIO_SIGNAL_OUT, &value);
- if (err < 0) {
- error("failed to read GPIO signal out register: %d", err);
- return err;
- }
-
- if (level == 0) {
- value &= ~(1 << gpio);
- l = "low";
- } else {
- value |= 1 << gpio;
- l = "high";
+ if (id != AS3722_DEVICE_ID) {
+ error("unknown device");
+ return -ENOENT;
}
- err = as3722_write(pmic, AS3722_GPIO_SIGNAL_OUT, value);
- if (err) {
- error("failed to set GPIO#%u %s: %d", gpio, l, err);
- return err;
- }
+ debug("AS3722 revision %#x found on I2C bus %s\n", revision, dev->name);
return 0;
}
-int as3722_gpio_direction_output(struct udevice *pmic, unsigned int gpio,
- unsigned int level)
-{
- u8 value;
- int err;
-
- if (gpio > 7)
- return -EINVAL;
+#if CONFIG_IS_ENABLED(PMIC_CHILDREN)
+static const struct pmic_child_info pmic_children_info[] = {
+ { .prefix = "sd", .driver = "as3722_stepdown"},
+ { .prefix = "ldo", .driver = "as3722_ldo"},
+ { },
+};
- if (level == 0)
- value = AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDL;
- else
- value = AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH;
+static int as3722_bind(struct udevice *dev)
+{
+ struct udevice *gpio_dev;
+ ofnode regulators_node;
+ int children;
+ int ret;
- err = as3722_write(pmic, AS3722_GPIO_CONTROL(gpio), value);
- if (err) {
- error("failed to configure GPIO#%u as output: %d", gpio, err);
- return err;
+ regulators_node = dev_read_subnode(dev, "regulators");
+ if (!ofnode_valid(regulators_node)) {
+ debug("%s: %s regulators subnode not found\n", __func__,
+ dev->name);
+ return -ENXIO;
}
- err = as3722_gpio_set(pmic, gpio, level);
- if (err < 0) {
- error("failed to set GPIO#%u high: %d", gpio, err);
- return err;
+ children = pmic_bind_children(dev, regulators_node, pmic_children_info);
+ if (!children)
+ debug("%s: %s - no child found\n", __func__, dev->name);
+ ret = device_bind_driver(dev, "gpio_as3722", "gpio_as3722", &gpio_dev);
+ if (ret) {
+ debug("%s: Cannot bind GPIOs (ret=%d)\n", __func__, ret);
+ return ret;
}
return 0;
}
+#endif
-/* Temporary function until we get the pmic framework */
-int as3722_get(struct udevice **devp)
+static int as3722_reg_count(struct udevice *dev)
{
- int bus = 0;
- int address = 0x40;
-
- return i2c_get_chip_for_busnum(bus, address, 1, devp);
+ return AS3722_NUM_OF_REGS;
}
-int as3722_init(struct udevice **devp)
-{
- struct udevice *pmic;
- u8 id, revision;
- const unsigned int bus = 0;
- const unsigned int address = 0x40;
- int err;
-
- err = i2c_get_chip_for_busnum(bus, address, 1, &pmic);
- if (err)
- return err;
- err = as3722_read_id(pmic, &id, &revision);
- if (err < 0) {
- error("failed to read ID: %d", err);
- return err;
- }
-
- if (id != AS3722_DEVICE_ID) {
- error("unknown device");
- return -ENOENT;
- }
-
- debug("AS3722 revision %#x found on I2C bus %u, address %#x\n",
- revision, bus, address);
- if (devp)
- *devp = pmic;
-
- return 0;
-}
+static struct dm_pmic_ops as3722_ops = {
+ .reg_count = as3722_reg_count,
+ .read = as3722_read,
+ .write = as3722_write,
+};
+
+static const struct udevice_id as3722_ids[] = {
+ { .compatible = "ams,as3722" },
+ { }
+};
+
+U_BOOT_DRIVER(pmic_as3722) = {
+ .name = "as3722_pmic",
+ .id = UCLASS_PMIC,
+ .of_match = as3722_ids,
+#if CONFIG_IS_ENABLED(PMIC_CHILDREN)
+ .bind = as3722_bind,
+#endif
+ .probe = as3722_probe,
+ .ops = &as3722_ops,
+};
--- /dev/null
+/*
+ * Copyright (C) 2014 NVIDIA Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/gpio.h>
+#include <power/as3722.h>
+#include <power/pmic.h>
+
+#define NUM_GPIOS 8
+
+int as3722_gpio_configure(struct udevice *pmic, unsigned int gpio,
+ unsigned long flags)
+{
+ u8 value = 0;
+ int err;
+
+ if (flags & AS3722_GPIO_OUTPUT_VDDH)
+ value |= AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH;
+
+ if (flags & AS3722_GPIO_INVERT)
+ value |= AS3722_GPIO_CONTROL_INVERT;
+
+ err = pmic_reg_write(pmic, AS3722_GPIO_CONTROL(gpio), value);
+ if (err) {
+ error("failed to configure GPIO#%u: %d", gpio, err);
+ return err;
+ }
+
+ return 0;
+}
+
+static int as3722_gpio_set_value(struct udevice *dev, unsigned int gpio,
+ int level)
+{
+ struct udevice *pmic = dev_get_parent(dev);
+ const char *l;
+ u8 value;
+ int err;
+
+ if (gpio >= NUM_GPIOS)
+ return -EINVAL;
+
+ err = pmic_reg_read(pmic, AS3722_GPIO_SIGNAL_OUT);
+ if (err < 0) {
+ error("failed to read GPIO signal out register: %d", err);
+ return err;
+ }
+ value = err;
+
+ if (level == 0) {
+ value &= ~(1 << gpio);
+ l = "low";
+ } else {
+ value |= 1 << gpio;
+ l = "high";
+ }
+
+ err = pmic_reg_write(pmic, AS3722_GPIO_SIGNAL_OUT, value);
+ if (err) {
+ error("failed to set GPIO#%u %s: %d", gpio, l, err);
+ return err;
+ }
+
+ return 0;
+}
+
+int as3722_gpio_direction_output(struct udevice *dev, unsigned int gpio,
+ int value)
+{
+ struct udevice *pmic = dev_get_parent(dev);
+ int err;
+
+ if (gpio > 7)
+ return -EINVAL;
+
+ if (value == 0)
+ value = AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDL;
+ else
+ value = AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH;
+
+ err = pmic_reg_write(pmic, AS3722_GPIO_CONTROL(gpio), value);
+ if (err) {
+ error("failed to configure GPIO#%u as output: %d", gpio, err);
+ return err;
+ }
+
+ err = as3722_gpio_set_value(pmic, gpio, value);
+ if (err < 0) {
+ error("failed to set GPIO#%u high: %d", gpio, err);
+ return err;
+ }
+
+ return 0;
+}
+
+static int as3722_gpio_probe(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ uc_priv->gpio_count = NUM_GPIOS;
+ uc_priv->bank_name = "as3722_";
+
+ return 0;
+}
+
+static const struct dm_gpio_ops gpio_as3722_ops = {
+ .direction_output = as3722_gpio_direction_output,
+ .set_value = as3722_gpio_set_value,
+};
+
+U_BOOT_DRIVER(gpio_as3722) = {
+ .name = "gpio_as3722",
+ .id = UCLASS_GPIO,
+ .ops = &gpio_as3722_ops,
+ .probe = as3722_gpio_probe,
+};
by the PMIC device. This driver is controlled by a device tree node
which includes voltage limits.
+config REGULATOR_AS3722
+ bool "Enable driver for AS7322 regulator"
+ depends on DM_REGULATOR && PMIC_AS3722
+ help
+ Enable support for the regulator functions of the AS3722. The
+ driver implements enable/disable for step-down bucks and LDOs,
+ but does not yet support change voltages. Currently this must be
+ done using direct register writes to the PMIC.
+
config DM_REGULATOR_PFUZE100
bool "Enable Driver Model for REGULATOR PFUZE100"
depends on DM_REGULATOR && DM_PMIC_PFUZE100
obj-$(CONFIG_$(SPL_)DM_REGULATOR) += regulator-uclass.o
obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o
+obj-$(CONFIG_REGULATOR_AS3722) += as3722_regulator.o
obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o
obj-$(CONFIG_DM_REGULATOR_PFUZE100) += pfuze100.o
obj-$(CONFIG_REGULATOR_PWM) += pwm_regulator.o
enable ? LDO_EN_MASK : 0);
}
-static bool reg_get_enable(struct udevice *dev)
+static int reg_get_enable(struct udevice *dev)
{
int reg = dev->driver_data;
int ret;
--- /dev/null
+/*
+ * Copyright (C) 2017 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * Placeholder regulator driver for as3722.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <power/as3722.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+
+static int stepdown_get_value(struct udevice *dev)
+{
+ return -ENOSYS;
+}
+
+static int stepdown_set_value(struct udevice *dev, int uvolt)
+{
+ return -ENOSYS;
+}
+
+static int stepdown_set_enable(struct udevice *dev, bool enable)
+{
+ struct udevice *pmic = dev_get_parent(dev);
+ int sd = dev->driver_data;
+ int ret;
+
+ ret = pmic_clrsetbits(pmic, AS3722_SD_CONTROL, 0, 1 << sd);
+ if (ret < 0) {
+ debug("%s: failed to write SD control register: %d", __func__,
+ ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int stepdown_get_enable(struct udevice *dev)
+{
+ struct udevice *pmic = dev_get_parent(dev);
+ int sd = dev->driver_data;
+ int ret;
+
+ ret = pmic_reg_read(pmic, AS3722_SD_CONTROL);
+ if (ret < 0) {
+ debug("%s: failed to read SD control register: %d", __func__,
+ ret);
+ return ret;
+ }
+
+ return ret & (1 << sd) ? true : false;
+}
+
+static int ldo_get_value(struct udevice *dev)
+{
+ return -ENOSYS;
+}
+
+static int ldo_set_value(struct udevice *dev, int uvolt)
+{
+ return -ENOSYS;
+}
+
+static int ldo_set_enable(struct udevice *dev, bool enable)
+{
+ struct udevice *pmic = dev_get_parent(dev);
+ int ldo = dev->driver_data;
+ int ret;
+
+ ret = pmic_clrsetbits(pmic, AS3722_LDO_CONTROL, 0, 1 << ldo);
+ if (ret < 0) {
+ debug("%s: failed to write LDO control register: %d", __func__,
+ ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ldo_get_enable(struct udevice *dev)
+{
+ struct udevice *pmic = dev_get_parent(dev);
+ int ldo = dev->driver_data;
+ int ret;
+
+ ret = pmic_reg_read(pmic, AS3722_LDO_CONTROL);
+ if (ret < 0) {
+ debug("%s: failed to read SD control register: %d", __func__,
+ ret);
+ return ret;
+ }
+
+ return ret & (1 << ldo) ? true : false;
+}
+
+static int as3722_stepdown_probe(struct udevice *dev)
+{
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+
+ uc_pdata->type = REGULATOR_TYPE_BUCK;
+
+ return 0;
+}
+
+static int as3722_ldo_probe(struct udevice *dev)
+{
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+
+ uc_pdata->type = REGULATOR_TYPE_LDO;
+
+ return 0;
+}
+
+static const struct dm_regulator_ops as3722_stepdown_ops = {
+ .get_value = stepdown_get_value,
+ .set_value = stepdown_set_value,
+ .get_enable = stepdown_get_enable,
+ .set_enable = stepdown_set_enable,
+};
+
+static const struct dm_regulator_ops as3722_ldo_ops = {
+ .get_value = ldo_get_value,
+ .set_value = ldo_set_value,
+ .get_enable = ldo_get_enable,
+ .set_enable = ldo_set_enable,
+};
+
+U_BOOT_DRIVER(as3722_stepdown) = {
+ .name = "as3722_stepdown",
+ .id = UCLASS_REGULATOR,
+ .ops = &as3722_stepdown_ops,
+ .probe = as3722_stepdown_probe,
+};
+
+U_BOOT_DRIVER(as3722_ldo) = {
+ .name = "as3722_ldo",
+ .id = UCLASS_REGULATOR,
+ .ops = &as3722_ldo_ops,
+ .probe = as3722_ldo_probe,
+};
return uc_pdata->min_uA;
}
-static bool fixed_regulator_get_enable(struct udevice *dev)
+static int fixed_regulator_get_enable(struct udevice *dev)
{
struct fixed_regulator_platdata *dev_pdata = dev_get_platdata(dev);
return lp873x_ldo_val(dev, PMIC_OP_SET, &uV);
}
-static bool ldo_get_enable(struct udevice *dev)
+static int ldo_get_enable(struct udevice *dev)
{
bool enable = false;
int ret;
return lp873x_buck_val(dev, PMIC_OP_SET, &uV);
}
-static bool buck_get_enable(struct udevice *dev)
+static int buck_get_enable(struct udevice *dev)
{
bool enable = false;
int ret;
return lp87565_buck_val(dev, PMIC_OP_SET, &uV);
}
-static bool buck_get_enable(struct udevice *dev)
+static int buck_get_enable(struct udevice *dev)
{
bool enable = false;
int ret;
return max77686_ldo_val(dev, PMIC_OP_SET, &uV);
}
-static bool ldo_get_enable(struct udevice *dev)
+static int ldo_get_enable(struct udevice *dev)
{
bool enable = false;
int ret;
return max77686_buck_val(dev, PMIC_OP_SET, &uV);
}
-static bool buck_get_enable(struct udevice *dev)
+static int buck_get_enable(struct udevice *dev)
{
bool enable = false;
int ret;
return palmas_ldo_val(dev, PMIC_OP_SET, &uV);
}
-static bool ldo_get_enable(struct udevice *dev)
+static int ldo_get_enable(struct udevice *dev)
{
bool enable = false;
int ret;
return palmas_smps_val(dev, PMIC_OP_SET, &uV);
}
-static bool smps_get_enable(struct udevice *dev)
+static int smps_get_enable(struct udevice *dev)
{
bool enable = false;
int ret;
return pfuze100_regulator_val(dev, PMIC_OP_SET, &uV);
}
-static bool pfuze100_regulator_get_enable(struct udevice *dev)
+static int pfuze100_regulator_get_enable(struct udevice *dev)
{
int ret;
bool enable = false;
}
ret = pwm_set_config(priv->pwm, priv->pwm_id,
- (priv->period_ns / 100) * duty_cycle, priv->period_ns);
+ priv->period_ns, (priv->period_ns / 100) * duty_cycle);
if (ret) {
dev_err(dev, "Failed to configure PWM\n");
return ret;
}
- ret = pwm_set_enable(priv->pwm, priv->pwm_id, true);
- if (ret) {
- dev_err(dev, "Failed to enable PWM\n");
- return ret;
- }
priv->volt_uV = uvolt;
+
return ret;
}
if (priv->init_voltage)
pwm_regulator_set_voltage(dev, priv->init_voltage);
- pwm_regulator_enable(dev, 1);
-
return 0;
}
return ops->set_current(dev, uA);
}
-bool regulator_get_enable(struct udevice *dev)
+int regulator_get_enable(struct udevice *dev)
{
const struct dm_regulator_ops *ops = dev_get_driver_ops(dev);
return _buck_set_enable(dev->parent, buck, enable);
}
-static bool buck_get_enable(struct udevice *dev)
+static int buck_get_enable(struct udevice *dev)
{
int buck = dev->driver_data - 1;
int ret;
enable ? mask : 0);
}
-static bool ldo_get_enable(struct udevice *dev)
+static int ldo_get_enable(struct udevice *dev)
{
int ldo = dev->driver_data - 1;
int ret;
enable ? mask : 0);
}
-static bool switch_get_enable(struct udevice *dev)
+static int switch_get_enable(struct udevice *dev)
{
int sw = dev->driver_data - 1;
int ret;
return ret;
}
-static bool ldo_get_enable(struct udevice *dev)
+static int ldo_get_enable(struct udevice *dev)
{
int ldo = dev->driver_data;
return reg_set_value(dev, &buck_param[buck], uv);
}
-static bool buck_get_enable(struct udevice *dev)
+static int buck_get_enable(struct udevice *dev)
{
int buck = dev->driver_data;
buck_current_range, uA);
}
-static bool buck_get_enable(struct udevice *dev)
+static int buck_get_enable(struct udevice *dev)
{
if (out_get_mode(dev) == BUCK_OM_OFF)
return false;
ldo_current_range, uA);
}
-static bool ldo_get_enable(struct udevice *dev)
+static int ldo_get_enable(struct udevice *dev)
{
if (out_get_mode(dev) == LDO_OM_OFF)
return false;
return 0;
}
-static bool tps65090_fet_get_enable(struct udevice *dev)
+static int tps65090_fet_get_enable(struct udevice *dev)
{
struct udevice *pmic = dev_get_parent(dev);
int ret, fet_id;
struct rk_pwm_priv *priv = dev_get_priv(dev);
debug("%s: polarity=%u\n", __func__, polarity);
+ priv->enable_conf &= ~(PWM_DUTY_MASK | PWM_INACTIVE_MASK);
if (polarity)
priv->enable_conf |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSTIVE;
else
{
struct tegra_pwm_priv *priv = dev_get_priv(dev);
- priv->regs = (struct pwm_ctlr *)devfdt_get_addr(dev);
+ priv->regs = (struct pwm_ctlr *)dev_read_addr(dev);
return 0;
}
#include <dm.h>
#include <ram.h>
#include <asm/io.h>
-#include <asm/arch/fmc.h>
-#include <asm/arch/stm32.h>
DECLARE_GLOBAL_DATA_PTR;
+struct stm32_fmc_regs {
+ /* 0x0 */
+ u32 bcr1; /* NOR/PSRAM Chip select control register 1 */
+ u32 btr1; /* SRAM/NOR-Flash Chip select timing register 1 */
+ u32 bcr2; /* NOR/PSRAM Chip select Control register 2 */
+ u32 btr2; /* SRAM/NOR-Flash Chip select timing register 2 */
+ u32 bcr3; /* NOR/PSRAMChip select Control register 3 */
+ u32 btr3; /* SRAM/NOR-Flash Chip select timing register 3 */
+ u32 bcr4; /* NOR/PSRAM Chip select Control register 4 */
+ u32 btr4; /* SRAM/NOR-Flash Chip select timing register 4 */
+ u32 reserved1[24];
+
+ /* 0x80 */
+ u32 pcr; /* NAND Flash control register */
+ u32 sr; /* FIFO status and interrupt register */
+ u32 pmem; /* Common memory space timing register */
+ u32 patt; /* Attribute memory space timing registers */
+ u32 reserved2[1];
+ u32 eccr; /* ECC result registers */
+ u32 reserved3[27];
+
+ /* 0x104 */
+ u32 bwtr1; /* SRAM/NOR-Flash write timing register 1 */
+ u32 reserved4[1];
+ u32 bwtr2; /* SRAM/NOR-Flash write timing register 2 */
+ u32 reserved5[1];
+ u32 bwtr3; /* SRAM/NOR-Flash write timing register 3 */
+ u32 reserved6[1];
+ u32 bwtr4; /* SRAM/NOR-Flash write timing register 4 */
+ u32 reserved7[8];
+
+ /* 0x140 */
+ u32 sdcr1; /* SDRAM Control register 1 */
+ u32 sdcr2; /* SDRAM Control register 2 */
+ u32 sdtr1; /* SDRAM Timing register 1 */
+ u32 sdtr2; /* SDRAM Timing register 2 */
+ u32 sdcmr; /* SDRAM Mode register */
+ u32 sdrtr; /* SDRAM Refresh timing register */
+ u32 sdsr; /* SDRAM Status register */
+};
+
+/*
+ * NOR/PSRAM Control register BCR1
+ * FMC controller Enable, only availabe for H7
+ */
+#define FMC_BCR1_FMCEN BIT(31)
+
+/* Control register SDCR */
+#define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */
+#define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */
+#define FMC_SDCR_SDCLK_SHIFT 10 /* SDRAM clock divisor shift */
+#define FMC_SDCR_WP_SHIFT 9 /* Write protection shift */
+#define FMC_SDCR_CAS_SHIFT 7 /* CAS latency shift */
+#define FMC_SDCR_NB_SHIFT 6 /* Number of banks shift */
+#define FMC_SDCR_MWID_SHIFT 4 /* Memory width shift */
+#define FMC_SDCR_NR_SHIFT 2 /* Number of row address bits shift */
+#define FMC_SDCR_NC_SHIFT 0 /* Number of col address bits shift */
+
+/* Timings register SDTR */
+#define FMC_SDTR_TMRD_SHIFT 0 /* Load mode register to active */
+#define FMC_SDTR_TXSR_SHIFT 4 /* Exit self-refresh time */
+#define FMC_SDTR_TRAS_SHIFT 8 /* Self-refresh time */
+#define FMC_SDTR_TRC_SHIFT 12 /* Row cycle delay */
+#define FMC_SDTR_TWR_SHIFT 16 /* Recovery delay */
+#define FMC_SDTR_TRP_SHIFT 20 /* Row precharge delay */
+#define FMC_SDTR_TRCD_SHIFT 24 /* Row-to-column delay */
+
+#define FMC_SDCMR_NRFS_SHIFT 5
+
+#define FMC_SDCMR_MODE_NORMAL 0
+#define FMC_SDCMR_MODE_START_CLOCK 1
+#define FMC_SDCMR_MODE_PRECHARGE 2
+#define FMC_SDCMR_MODE_AUTOREFRESH 3
+#define FMC_SDCMR_MODE_WRITE_MODE 4
+#define FMC_SDCMR_MODE_SELFREFRESH 5
+#define FMC_SDCMR_MODE_POWERDOWN 6
+
+#define FMC_SDCMR_BANK_1 BIT(4)
+#define FMC_SDCMR_BANK_2 BIT(3)
+
+#define FMC_SDCMR_MODE_REGISTER_SHIFT 9
+
+#define FMC_SDSR_BUSY BIT(5)
+
+#define FMC_BUSY_WAIT(regs) do { \
+ __asm__ __volatile__ ("dsb" : : : "memory"); \
+ while (regs->sdsr & FMC_SDSR_BUSY) \
+ ; \
+ } while (0)
+
struct stm32_sdram_control {
u8 no_columns;
u8 no_rows;
u8 twr;
u8 trcd;
};
+enum stm32_fmc_bank {
+ SDRAM_BANK1,
+ SDRAM_BANK2,
+ MAX_SDRAM_BANK,
+};
+
+enum stm32_fmc_family {
+ STM32F7_FMC,
+ STM32H7_FMC,
+};
+
+struct bank_params {
+ struct stm32_sdram_control *sdram_control;
+ struct stm32_sdram_timing *sdram_timing;
+ u32 sdram_ref_count;
+ enum stm32_fmc_bank target_bank;
+};
+
struct stm32_sdram_params {
+ struct stm32_fmc_regs *base;
u8 no_sdram_banks;
- struct stm32_sdram_control sdram_control;
- struct stm32_sdram_timing sdram_timing;
- u32 sdram_ref_count;
+ struct bank_params bank_params[MAX_SDRAM_BANK];
+ enum stm32_fmc_family family;
};
#define SDRAM_MODE_BL_SHIFT 0
int stm32_sdram_init(struct udevice *dev)
{
struct stm32_sdram_params *params = dev_get_platdata(dev);
+ struct stm32_sdram_control *control;
+ struct stm32_sdram_timing *timing;
+ struct stm32_fmc_regs *regs = params->base;
+ enum stm32_fmc_bank target_bank;
+ u32 ctb; /* SDCMR register: Command Target Bank */
+ u32 ref_count;
+ u8 i;
+
+ /* disable the FMC controller */
+ if (params->family == STM32H7_FMC)
+ clrbits_le32(®s->bcr1, FMC_BCR1_FMCEN);
+
+ for (i = 0; i < params->no_sdram_banks; i++) {
+ control = params->bank_params[i].sdram_control;
+ timing = params->bank_params[i].sdram_timing;
+ target_bank = params->bank_params[i].target_bank;
+ ref_count = params->bank_params[i].sdram_ref_count;
+
+ writel(control->sdclk << FMC_SDCR_SDCLK_SHIFT
+ | control->cas_latency << FMC_SDCR_CAS_SHIFT
+ | control->no_banks << FMC_SDCR_NB_SHIFT
+ | control->memory_width << FMC_SDCR_MWID_SHIFT
+ | control->no_rows << FMC_SDCR_NR_SHIFT
+ | control->no_columns << FMC_SDCR_NC_SHIFT
+ | control->rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT
+ | control->rd_burst << FMC_SDCR_RBURST_SHIFT,
+ ®s->sdcr1);
+
+ if (target_bank == SDRAM_BANK2)
+ writel(control->cas_latency << FMC_SDCR_CAS_SHIFT
+ | control->no_banks << FMC_SDCR_NB_SHIFT
+ | control->memory_width << FMC_SDCR_MWID_SHIFT
+ | control->no_rows << FMC_SDCR_NR_SHIFT
+ | control->no_columns << FMC_SDCR_NC_SHIFT,
+ ®s->sdcr2);
- writel(params->sdram_control.sdclk << FMC_SDCR_SDCLK_SHIFT
- | params->sdram_control.cas_latency << FMC_SDCR_CAS_SHIFT
- | params->sdram_control.no_banks << FMC_SDCR_NB_SHIFT
- | params->sdram_control.memory_width << FMC_SDCR_MWID_SHIFT
- | params->sdram_control.no_rows << FMC_SDCR_NR_SHIFT
- | params->sdram_control.no_columns << FMC_SDCR_NC_SHIFT
- | params->sdram_control.rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT
- | params->sdram_control.rd_burst << FMC_SDCR_RBURST_SHIFT,
- &STM32_SDRAM_FMC->sdcr1);
-
- writel(params->sdram_timing.trcd << FMC_SDTR_TRCD_SHIFT
- | params->sdram_timing.trp << FMC_SDTR_TRP_SHIFT
- | params->sdram_timing.twr << FMC_SDTR_TWR_SHIFT
- | params->sdram_timing.trc << FMC_SDTR_TRC_SHIFT
- | params->sdram_timing.tras << FMC_SDTR_TRAS_SHIFT
- | params->sdram_timing.txsr << FMC_SDTR_TXSR_SHIFT
- | params->sdram_timing.tmrd << FMC_SDTR_TMRD_SHIFT,
- &STM32_SDRAM_FMC->sdtr1);
-
- writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK,
- &STM32_SDRAM_FMC->sdcmr);
- udelay(200); /* 200 us delay, page 10, "Power-Up" */
- FMC_BUSY_WAIT();
-
- writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE,
- &STM32_SDRAM_FMC->sdcmr);
- udelay(100);
- FMC_BUSY_WAIT();
-
- writel((FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH
- | 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr);
- udelay(100);
- FMC_BUSY_WAIT();
-
- writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
- | params->sdram_control.cas_latency << SDRAM_MODE_CAS_SHIFT)
- << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
- &STM32_SDRAM_FMC->sdcmr);
- udelay(100);
- FMC_BUSY_WAIT();
-
- writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL,
- &STM32_SDRAM_FMC->sdcmr);
- FMC_BUSY_WAIT();
-
- /* Refresh timer */
- writel((params->sdram_ref_count) << 1, &STM32_SDRAM_FMC->sdrtr);
+ writel(timing->trcd << FMC_SDTR_TRCD_SHIFT
+ | timing->trp << FMC_SDTR_TRP_SHIFT
+ | timing->twr << FMC_SDTR_TWR_SHIFT
+ | timing->trc << FMC_SDTR_TRC_SHIFT
+ | timing->tras << FMC_SDTR_TRAS_SHIFT
+ | timing->txsr << FMC_SDTR_TXSR_SHIFT
+ | timing->tmrd << FMC_SDTR_TMRD_SHIFT,
+ ®s->sdtr1);
+
+ if (target_bank == SDRAM_BANK2)
+ writel(timing->trcd << FMC_SDTR_TRCD_SHIFT
+ | timing->trp << FMC_SDTR_TRP_SHIFT
+ | timing->twr << FMC_SDTR_TWR_SHIFT
+ | timing->trc << FMC_SDTR_TRC_SHIFT
+ | timing->tras << FMC_SDTR_TRAS_SHIFT
+ | timing->txsr << FMC_SDTR_TXSR_SHIFT
+ | timing->tmrd << FMC_SDTR_TMRD_SHIFT,
+ ®s->sdtr2);
+
+ if (target_bank == SDRAM_BANK1)
+ ctb = FMC_SDCMR_BANK_1;
+ else
+ ctb = FMC_SDCMR_BANK_2;
+
+ writel(ctb | FMC_SDCMR_MODE_START_CLOCK, ®s->sdcmr);
+ udelay(200); /* 200 us delay, page 10, "Power-Up" */
+ FMC_BUSY_WAIT(regs);
+
+ writel(ctb | FMC_SDCMR_MODE_PRECHARGE, ®s->sdcmr);
+ udelay(100);
+ FMC_BUSY_WAIT(regs);
+
+ writel((ctb | FMC_SDCMR_MODE_AUTOREFRESH | 7 << FMC_SDCMR_NRFS_SHIFT),
+ ®s->sdcmr);
+ udelay(100);
+ FMC_BUSY_WAIT(regs);
+
+ writel(ctb | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
+ | control->cas_latency << SDRAM_MODE_CAS_SHIFT)
+ << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
+ ®s->sdcmr);
+ udelay(100);
+ FMC_BUSY_WAIT(regs);
+
+ writel(ctb | FMC_SDCMR_MODE_NORMAL, ®s->sdcmr);
+ FMC_BUSY_WAIT(regs);
+
+ /* Refresh timer */
+ writel(ref_count << 1, ®s->sdrtr);
+ }
+
+ /* enable the FMC controller */
+ if (params->family == STM32H7_FMC)
+ setbits_le32(®s->bcr1, FMC_BCR1_FMCEN);
return 0;
}
static int stm32_fmc_ofdata_to_platdata(struct udevice *dev)
{
- int ret;
- int node = dev_of_offset(dev);
- const void *blob = gd->fdt_blob;
struct stm32_sdram_params *params = dev_get_platdata(dev);
+ struct bank_params *bank_params;
+ ofnode bank_node;
+ char *bank_name;
+ u8 bank = 0;
- params->no_sdram_banks = fdtdec_get_uint(blob, node, "mr-nbanks", 1);
- debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks);
+ dev_for_each_subnode(bank_node, dev) {
+ /* extract the bank index from DT */
+ bank_name = (char *)ofnode_get_name(bank_node);
+ strsep(&bank_name, "@");
+ if (!bank_name) {
+ error("missing sdram bank index");
+ return -EINVAL;
+ }
+
+ bank_params = ¶ms->bank_params[bank];
+ strict_strtoul(bank_name, 10,
+ (long unsigned int *)&bank_params->target_bank);
+
+ if (bank_params->target_bank >= MAX_SDRAM_BANK) {
+ error("Found bank %d , but only bank 0 and 1 are supported",
+ bank_params->target_bank);
+ return -EINVAL;
+ }
- fdt_for_each_subnode(node, blob, node) {
- ret = fdtdec_get_byte_array(blob, node, "st,sdram-control",
- (u8 *)¶ms->sdram_control,
- sizeof(params->sdram_control));
- if (ret)
- return ret;
- ret = fdtdec_get_byte_array(blob, node, "st,sdram-timing",
- (u8 *)¶ms->sdram_timing,
- sizeof(params->sdram_timing));
- if (ret)
- return ret;
-
- params->sdram_ref_count = fdtdec_get_int(blob, node,
+ debug("Find bank %s %u\n", bank_name, bank_params->target_bank);
+
+ params->bank_params[bank].sdram_control =
+ (struct stm32_sdram_control *)
+ ofnode_read_u8_array_ptr(bank_node,
+ "st,sdram-control",
+ sizeof(struct stm32_sdram_control));
+
+ if (!params->bank_params[bank].sdram_control) {
+ error("st,sdram-control not found for %s",
+ ofnode_get_name(bank_node));
+ return -EINVAL;
+ }
+
+
+ params->bank_params[bank].sdram_timing =
+ (struct stm32_sdram_timing *)
+ ofnode_read_u8_array_ptr(bank_node,
+ "st,sdram-timing",
+ sizeof(struct stm32_sdram_timing));
+
+ if (!params->bank_params[bank].sdram_timing) {
+ error("st,sdram-timing not found for %s",
+ ofnode_get_name(bank_node));
+ return -EINVAL;
+ }
+
+
+ bank_params->sdram_ref_count = ofnode_read_u32_default(bank_node,
"st,sdram-refcount", 8196);
+ bank++;
}
+ params->no_sdram_banks = bank;
+ debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks);
+
return 0;
}
static int stm32_fmc_probe(struct udevice *dev)
{
+ struct stm32_sdram_params *params = dev_get_platdata(dev);
int ret;
+ fdt_addr_t addr;
+
+ addr = dev_read_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ params->base = (struct stm32_fmc_regs *)addr;
+ params->family = dev_get_driver_data(dev);
+
#ifdef CONFIG_CLK
struct clk clk;
};
static const struct udevice_id stm32_fmc_ids[] = {
- { .compatible = "st,stm32-fmc" },
+ { .compatible = "st,stm32-fmc", .data = STM32F7_FMC },
+ { .compatible = "st,stm32h7-fmc", .data = STM32H7_FMC },
{ }
};
debug("%s(dev=%p, index=%d, reset_ctl=%p)\n", __func__, dev, index,
reset_ctl);
+ reset_ctl->dev = NULL;
ret = dev_read_phandle_with_args(dev, "resets", "#reset-cells", 0,
index, &args);
debug("%s(dev=%p, name=%s, reset_ctl=%p)\n", __func__, dev, name,
reset_ctl);
+ reset_ctl->dev = NULL;
index = dev_read_stringlist_search(dev, "reset-names", name);
if (index < 0) {
return reset_get_by_index(dev, index, reset_ctl);
}
+int reset_request(struct reset_ctl *reset_ctl)
+{
+ struct reset_ops *ops = reset_dev_ops(reset_ctl->dev);
+
+ debug("%s(reset_ctl=%p)\n", __func__, reset_ctl);
+
+ return ops->request(reset_ctl);
+}
+
int reset_free(struct reset_ctl *reset_ctl)
{
struct reset_ops *ops = reset_dev_ops(reset_ctl->dev);
return ops->rst_deassert(reset_ctl);
}
+int reset_release_all(struct reset_ctl *reset_ctl, int count)
+{
+ int i, ret;
+
+ for (i = 0; i < count; i++) {
+ debug("%s(reset_ctl[%d]=%p)\n", __func__, i, &reset_ctl[i]);
+
+ /* check if reset has been previously requested */
+ if (!reset_ctl[i].dev)
+ continue;
+
+ ret = reset_assert(&reset_ctl[i]);
+ if (ret)
+ return ret;
+
+ ret = reset_free(&reset_ctl[i]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
UCLASS_DRIVER(reset) = {
.id = UCLASS_RESET,
.name = "reset",
implements serial_putc() etc. The uclass interface is
defined in include/serial.h.
+config SERIAL_IRQ_BUFFER
+ bool "Enable RX interrupt buffer for serial input"
+ depends on DM_SERIAL
+ default n
+ help
+ Enable RX interrupt buffer support for the serial driver.
+ This enables pasting longer strings, even when the RX FIFO
+ of the UART is not big enough (e.g. 16 bytes on the normal
+ NS16550).
+
config SPL_DM_SERIAL
bool "Enable Driver Model for serial drivers in SPL"
depends on DM_SERIAL
will need to provide parameters to make this work. The driver will
be available until the real driver model serial is running.
+config DEBUG_UART_MXC
+ bool "IMX Serial port"
+ depends on MXC_UART
+ help
+ Select this to enable a debug UART using the serial_mxc driver. You
+ will need to provide parameters to make this work. The driver will
+ be available until the real driver model serial is running.
+
config DEBUG_UART_UNIPHIER
bool "UniPhier on-chip UART"
depends on ARCH_UNIPHIER
#endif
#ifdef CONFIG_DM_SERIAL
+
+#if CONFIG_IS_ENABLED(SERIAL_IRQ_BUFFER)
+
+#define BUF_COUNT 256
+
+static void rx_fifo_to_buf(struct udevice *dev)
+{
+ struct NS16550 *const com_port = dev_get_priv(dev);
+ struct ns16550_platdata *plat = dev->platdata;
+
+ /* Read all available chars into buffer */
+ while ((serial_in(&com_port->lsr) & UART_LSR_DR)) {
+ plat->buf[plat->wr_ptr++] = serial_in(&com_port->rbr);
+ plat->wr_ptr %= BUF_COUNT;
+ }
+}
+
+static int rx_pending(struct udevice *dev)
+{
+ struct ns16550_platdata *plat = dev->platdata;
+
+ /*
+ * At startup it may happen, that some already received chars are
+ * "stuck" in the RX FIFO, even with the interrupt enabled. This
+ * RX FIFO flushing makes sure, that these chars are read out and
+ * the RX interrupts works as expected.
+ */
+ rx_fifo_to_buf(dev);
+
+ return plat->rd_ptr != plat->wr_ptr ? 1 : 0;
+}
+
+static int rx_get(struct udevice *dev)
+{
+ struct ns16550_platdata *plat = dev->platdata;
+ char val;
+
+ val = plat->buf[plat->rd_ptr++];
+ plat->rd_ptr %= BUF_COUNT;
+
+ return val;
+}
+
+void ns16550_handle_irq(void *data)
+{
+ struct udevice *dev = (struct udevice *)data;
+ struct NS16550 *const com_port = dev_get_priv(dev);
+
+ /* Check if interrupt is pending */
+ if (serial_in(&com_port->iir) & UART_IIR_NO_INT)
+ return;
+
+ /* Flush all available characters from the RX FIFO into the RX buffer */
+ rx_fifo_to_buf(dev);
+}
+
+#else /* CONFIG_SERIAL_IRQ_BUFFER */
+
+static int rx_pending(struct udevice *dev)
+{
+ struct NS16550 *const com_port = dev_get_priv(dev);
+
+ return serial_in(&com_port->lsr) & UART_LSR_DR ? 1 : 0;
+}
+
+static int rx_get(struct udevice *dev)
+{
+ struct NS16550 *const com_port = dev_get_priv(dev);
+
+ return serial_in(&com_port->rbr);
+}
+
+#endif /* CONFIG_SERIAL_IRQ_BUFFER */
+
static int ns16550_serial_putc(struct udevice *dev, const char ch)
{
struct NS16550 *const com_port = dev_get_priv(dev);
struct NS16550 *const com_port = dev_get_priv(dev);
if (input)
- return serial_in(&com_port->lsr) & UART_LSR_DR ? 1 : 0;
+ return rx_pending(dev);
else
return serial_in(&com_port->lsr) & UART_LSR_THRE ? 0 : 1;
}
static int ns16550_serial_getc(struct udevice *dev)
{
- struct NS16550 *const com_port = dev_get_priv(dev);
-
- if (!(serial_in(&com_port->lsr) & UART_LSR_DR))
+ if (!ns16550_serial_pending(dev, true))
return -EAGAIN;
- return serial_in(&com_port->rbr);
+ return rx_get(dev);
}
static int ns16550_serial_setbrg(struct udevice *dev, int baudrate)
com_port->plat = dev_get_platdata(dev);
NS16550_init(com_port, -1);
+#if CONFIG_IS_ENABLED(SERIAL_IRQ_BUFFER)
+ if (gd->flags & GD_FLG_RELOC) {
+ struct ns16550_platdata *plat = dev->platdata;
+
+ /* Allocate the RX buffer */
+ plat->buf = malloc(BUF_COUNT);
+
+ /* Install the interrupt handler */
+ irq_install_handler(plat->irq, ns16550_handle_irq, dev);
+
+ /* Enable RX interrupts */
+ serial_out(UART_IER_RDI, &com_port->ier);
+ }
+#endif
+
+ return 0;
+}
+
+#if CONFIG_IS_ENABLED(SERIAL_PRESENT) && \
+ (!defined(CONFIG_TPL_BUILD) || defined(CONFIG_TPL_DM_SERIAL))
+static int ns16550_serial_remove(struct udevice *dev)
+{
+#if CONFIG_IS_ENABLED(SERIAL_IRQ_BUFFER)
+ if (gd->flags & GD_FLG_RELOC) {
+ struct ns16550_platdata *plat = dev->platdata;
+
+ irq_free_handler(plat->irq);
+ }
+#endif
+
return 0;
}
+#endif
#if CONFIG_IS_ENABLED(OF_CONTROL)
enum {
if (port_type == PORT_JZ4780)
plat->fcr |= UART_FCR_UME;
+#if CONFIG_IS_ENABLED(SERIAL_IRQ_BUFFER)
+ plat->irq = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "interrupts", 0);
+ if (!plat->irq) {
+ debug("ns16550 interrupt not provided\n");
+ return -EINVAL;
+ }
+#endif
+
return 0;
}
#endif
#endif
.priv_auto_alloc_size = sizeof(struct NS16550),
.probe = ns16550_serial_probe,
+ .remove = ns16550_serial_remove,
.ops = &ns16550_serial_ops,
.flags = DM_FLAG_PRE_RELOC,
};
*/
static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE;
-#ifndef CONFIG_SYS_MALLOC_F_LEN
-#error "Serial is required before relocation - define CONFIG_SYS_MALLOC_F_LEN to make this work"
+#if !CONFIG_VAL(SYS_MALLOC_F_LEN)
+#error "Serial is required before relocation - define CONFIG_$(SPL_)SYS_MALLOC_F_LEN to make this work"
#endif
static int serial_check_stdout(const void *blob, struct udevice **devp)
serial_initfunc(max3100_serial_initialize);
serial_initfunc(mcf_serial_initialize);
serial_initfunc(ml2_serial_initialize);
-serial_initfunc(mpc5xx_serial_initialize);
-serial_initfunc(mpc8260_scc_serial_initialize);
-serial_initfunc(mpc8260_smc_serial_initialize);
serial_initfunc(mpc85xx_serial_initialize);
serial_initfunc(mpc8xx_serial_initialize);
serial_initfunc(mxc_serial_initialize);
#include <linux/compiler.h>
/* UART Control Register Bit Fields.*/
-#define URXD_CHARRDY (1<<15)
-#define URXD_ERR (1<<14)
-#define URXD_OVRRUN (1<<13)
-#define URXD_FRMERR (1<<12)
-#define URXD_BRK (1<<11)
-#define URXD_PRERR (1<<10)
-#define URXD_RX_DATA (0xFF)
-#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
-#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
-#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
-#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
-#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
-#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
-#define UCR1_IREN (1<<7) /* Infrared interface enable */
-#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
-#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
-#define UCR1_SNDBRK (1<<4) /* Send break */
-#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
-#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
-#define UCR1_DOZE (1<<1) /* Doze */
-#define UCR1_UARTEN (1<<0) /* UART enabled */
-#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
-#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
-#define UCR2_CTSC (1<<13) /* CTS pin control */
-#define UCR2_CTS (1<<12) /* Clear to send */
-#define UCR2_ESCEN (1<<11) /* Escape enable */
-#define UCR2_PREN (1<<8) /* Parity enable */
-#define UCR2_PROE (1<<7) /* Parity odd/even */
-#define UCR2_STPB (1<<6) /* Stop */
-#define UCR2_WS (1<<5) /* Word size */
-#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
-#define UCR2_TXEN (1<<2) /* Transmitter enabled */
-#define UCR2_RXEN (1<<1) /* Receiver enabled */
-#define UCR2_SRST (1<<0) /* SW reset */
-#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
-#define UCR3_PARERREN (1<<12) /* Parity enable */
-#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
-#define UCR3_DSR (1<<10) /* Data set ready */
-#define UCR3_DCD (1<<9) /* Data carrier detect */
-#define UCR3_RI (1<<8) /* Ring indicator */
-#define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
-#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
-#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
-#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
-#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
-#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
-#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
-#define UCR3_BPEN (1<<0) /* Preset registers enable */
-#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
-#define UCR4_INVR (1<<9) /* Inverted infrared reception */
-#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
-#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
-#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
-#define UCR4_IRSC (1<<5) /* IR special case */
-#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
-#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
-#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
-#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
-#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
-#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
-#define UFCR_RFDIV_SHF 7 /* Reference freq divider shift */
-#define UFCR_DCEDTE (1<<6) /* DTE mode select */
-#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
-#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
-#define USR1_RTSS (1<<14) /* RTS pin status */
-#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
-#define USR1_RTSD (1<<12) /* RTS delta */
-#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
-#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
-#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
-#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
-#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
-#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
-#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
-#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
-#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
-#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
-#define USR2_IDLE (1<<12) /* Idle condition */
-#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
-#define USR2_WAKE (1<<7) /* Wake */
-#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
-#define USR2_TXDC (1<<3) /* Transmitter complete */
-#define USR2_BRCD (1<<2) /* Break condition */
-#define USR2_ORE (1<<1) /* Overrun error */
-#define USR2_RDR (1<<0) /* Recv data ready */
-#define UTS_FRCPERR (1<<13) /* Force parity error */
-#define UTS_LOOP (1<<12) /* Loop tx and rx */
-#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
-#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
-#define UTS_TXFULL (1<<4) /* TxFIFO full */
-#define UTS_RXFULL (1<<3) /* RxFIFO full */
-#define UTS_SOFTRST (1<<0) /* Software reset */
+#define URXD_CHARRDY (1<<15)
+#define URXD_ERR (1<<14)
+#define URXD_OVRRUN (1<<13)
+#define URXD_FRMERR (1<<12)
+#define URXD_BRK (1<<11)
+#define URXD_PRERR (1<<10)
+#define URXD_RX_DATA (0xFF)
+#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
+#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
+#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
+#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
+#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
+#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
+#define UCR1_IREN (1<<7) /* Infrared interface enable */
+#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
+#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
+#define UCR1_SNDBRK (1<<4) /* Send break */
+#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
+#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
+#define UCR1_DOZE (1<<1) /* Doze */
+#define UCR1_UARTEN (1<<0) /* UART enabled */
+#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
+#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
+#define UCR2_CTSC (1<<13) /* CTS pin control */
+#define UCR2_CTS (1<<12) /* Clear to send */
+#define UCR2_ESCEN (1<<11) /* Escape enable */
+#define UCR2_PREN (1<<8) /* Parity enable */
+#define UCR2_PROE (1<<7) /* Parity odd/even */
+#define UCR2_STPB (1<<6) /* Stop */
+#define UCR2_WS (1<<5) /* Word size */
+#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
+#define UCR2_TXEN (1<<2) /* Transmitter enabled */
+#define UCR2_RXEN (1<<1) /* Receiver enabled */
+#define UCR2_SRST (1<<0) /* SW reset */
+#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
+#define UCR3_PARERREN (1<<12) /* Parity enable */
+#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
+#define UCR3_DSR (1<<10) /* Data set ready */
+#define UCR3_DCD (1<<9) /* Data carrier detect */
+#define UCR3_RI (1<<8) /* Ring indicator */
+#define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
+#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
+#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
+#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
+#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
+#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
+#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
+#define UCR3_BPEN (1<<0) /* Preset registers enable */
+#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
+#define UCR4_INVR (1<<9) /* Inverted infrared reception */
+#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
+#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
+#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
+#define UCR4_IRSC (1<<5) /* IR special case */
+#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
+#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
+#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
+#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
+#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
+#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
+#define UFCR_RFDIV_SHF 7 /* Reference freq divider shift */
+#define RFDIV 4 /* divide input clock by 2 */
+#define UFCR_DCEDTE (1<<6) /* DTE mode select */
+#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
+#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
+#define USR1_RTSS (1<<14) /* RTS pin status */
+#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
+#define USR1_RTSD (1<<12) /* RTS delta */
+#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
+#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
+#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
+#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
+#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
+#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
+#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
+#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
+#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
+#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
+#define USR2_IDLE (1<<12) /* Idle condition */
+#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
+#define USR2_WAKE (1<<7) /* Wake */
+#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
+#define USR2_TXDC (1<<3) /* Transmitter complete */
+#define USR2_BRCD (1<<2) /* Break condition */
+#define USR2_ORE (1<<1) /* Overrun error */
+#define USR2_RDR (1<<0) /* Recv data ready */
+#define UTS_FRCPERR (1<<13) /* Force parity error */
+#define UTS_LOOP (1<<12) /* Loop tx and rx */
+#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
+#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
+#define UTS_TXFULL (1<<4) /* TxFIFO full */
+#define UTS_RXFULL (1<<3) /* RxFIFO full */
+#define UTS_SOFTRS (1<<0) /* Software reset */
+#define TXTL 2 /* reset default */
+#define RXTL 1 /* reset default */
DECLARE_GLOBAL_DATA_PTR;
+struct mxc_uart {
+ u32 rxd;
+ u32 spare0[15];
+
+ u32 txd;
+ u32 spare1[15];
+
+ u32 cr1;
+ u32 cr2;
+ u32 cr3;
+ u32 cr4;
+
+ u32 fcr;
+ u32 sr1;
+ u32 sr2;
+ u32 esc;
+
+ u32 tim;
+ u32 bir;
+ u32 bmr;
+ u32 brc;
+
+ u32 onems;
+ u32 ts;
+};
+
+static void _mxc_serial_init(struct mxc_uart *base)
+{
+ writel(0, &base->cr1);
+ writel(0, &base->cr2);
+
+ while (!(readl(&base->cr2) & UCR2_SRST));
+
+ writel(0x704 | UCR3_ADNIMP, &base->cr3);
+ writel(0x8000, &base->cr4);
+ writel(0x2b, &base->esc);
+ writel(0, &base->tim);
+
+ writel(0, &base->ts);
+}
+
+static void _mxc_serial_setbrg(struct mxc_uart *base, unsigned long clk,
+ unsigned long baudrate, bool use_dte)
+{
+ u32 tmp;
+
+ tmp = RFDIV << UFCR_RFDIV_SHF;
+ if (use_dte)
+ tmp |= UFCR_DCEDTE;
+ else
+ tmp |= (TXTL << UFCR_TXTL_SHF) | (RXTL << UFCR_RXTL_SHF);
+ writel(tmp, &base->fcr);
+
+ writel(0xf, &base->bir);
+ writel(clk / (2 * baudrate), &base->bmr);
+
+ writel(UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST,
+ &base->cr2);
+ writel(UCR1_UARTEN, &base->cr1);
+}
+
#ifndef CONFIG_DM_SERIAL
#ifndef CONFIG_MXC_UART_BASE
#error "define CONFIG_MXC_UART_BASE to use the MXC UART driver"
#endif
-#define UART_PHYS CONFIG_MXC_UART_BASE
-
-#define __REG(x) (*((volatile u32 *)(x)))
-
-/* Register definitions */
-#define URXD 0x0 /* Receiver Register */
-#define UTXD 0x40 /* Transmitter Register */
-#define UCR1 0x80 /* Control Register 1 */
-#define UCR2 0x84 /* Control Register 2 */
-#define UCR3 0x88 /* Control Register 3 */
-#define UCR4 0x8c /* Control Register 4 */
-#define UFCR 0x90 /* FIFO Control Register */
-#define USR1 0x94 /* Status Register 1 */
-#define USR2 0x98 /* Status Register 2 */
-#define UESC 0x9c /* Escape Character Register */
-#define UTIM 0xa0 /* Escape Timer Register */
-#define UBIR 0xa4 /* BRM Incremental Register */
-#define UBMR 0xa8 /* BRM Modulator Register */
-#define UBRC 0xac /* Baud Rate Count Register */
-#define UTS 0xb4 /* UART Test Register (mx31) */
-
-#define TXTL 2 /* reset default */
-#define RXTL 1 /* reset default */
-#define RFDIV 4 /* divide input clock by 2 */
+#define mxc_base ((struct mxc_uart *)CONFIG_MXC_UART_BASE)
static void mxc_serial_setbrg(void)
{
if (!gd->baudrate)
gd->baudrate = CONFIG_BAUDRATE;
- __REG(UART_PHYS + UFCR) = (RFDIV << UFCR_RFDIV_SHF)
- | (TXTL << UFCR_TXTL_SHF)
- | (RXTL << UFCR_RXTL_SHF);
- __REG(UART_PHYS + UBIR) = 0xf;
- __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate);
-
+ _mxc_serial_setbrg(mxc_base, clk, gd->baudrate, false);
}
static int mxc_serial_getc(void)
{
- while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
+ while (readl(&mxc_base->ts) & UTS_RXEMPTY)
WATCHDOG_RESET();
- return (__REG(UART_PHYS + URXD) & URXD_RX_DATA); /* mask out status from upper word */
+ return (readl(&mxc_base->rxd) & URXD_RX_DATA); /* mask out status from upper word */
}
static void mxc_serial_putc(const char c)
if (c == '\n')
serial_putc('\r');
- __REG(UART_PHYS + UTXD) = c;
+ writel(c, &mxc_base->txd);
/* wait for transmitter to be ready */
- while (!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY))
+ while (!(readl(&mxc_base->ts) & UTS_TXEMPTY))
WATCHDOG_RESET();
}
-/*
- * Test whether a character is in the RX buffer
- */
+/* Test whether a character is in the RX buffer */
static int mxc_serial_tstc(void)
{
/* If receive fifo is empty, return false */
- if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
+ if (readl(&mxc_base->ts) & UTS_RXEMPTY)
return 0;
return 1;
}
/*
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
- *
*/
static int mxc_serial_init(void)
{
- __REG(UART_PHYS + UCR1) = 0x0;
- __REG(UART_PHYS + UCR2) = 0x0;
-
- while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST));
-
- __REG(UART_PHYS + UCR3) = 0x0704 | UCR3_ADNIMP;
- __REG(UART_PHYS + UCR4) = 0x8000;
- __REG(UART_PHYS + UESC) = 0x002b;
- __REG(UART_PHYS + UTIM) = 0x0;
-
- __REG(UART_PHYS + UTS) = 0x0;
+ _mxc_serial_init(mxc_base);
serial_setbrg();
- __REG(UART_PHYS + UCR2) = UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST;
-
- __REG(UART_PHYS + UCR1) = UCR1_UARTEN;
-
return 0;
}
#ifdef CONFIG_DM_SERIAL
-struct mxc_uart {
- u32 rxd;
- u32 spare0[15];
-
- u32 txd;
- u32 spare1[15];
-
- u32 cr1;
- u32 cr2;
- u32 cr3;
- u32 cr4;
-
- u32 fcr;
- u32 sr1;
- u32 sr2;
- u32 esc;
-
- u32 tim;
- u32 bir;
- u32 bmr;
- u32 brc;
-
- u32 onems;
- u32 ts;
-};
-
int mxc_serial_setbrg(struct udevice *dev, int baudrate)
{
struct mxc_serial_platdata *plat = dev->platdata;
- struct mxc_uart *const uart = plat->reg;
u32 clk = imx_get_uartclk();
- u32 tmp;
-
- tmp = 4 << UFCR_RFDIV_SHF;
- if (plat->use_dte)
- tmp |= UFCR_DCEDTE;
- writel(tmp, &uart->fcr);
-
- writel(0xf, &uart->bir);
- writel(clk / (2 * baudrate), &uart->bmr);
- writel(UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST,
- &uart->cr2);
- writel(UCR1_UARTEN, &uart->cr1);
+ _mxc_serial_setbrg(plat->reg, clk, baudrate, plat->use_dte);
return 0;
}
static int mxc_serial_probe(struct udevice *dev)
{
struct mxc_serial_platdata *plat = dev->platdata;
- struct mxc_uart *const uart = plat->reg;
- writel(0, &uart->cr1);
- writel(0, &uart->cr2);
- while (!(readl(&uart->cr2) & UCR2_SRST));
- writel(0x704 | UCR3_ADNIMP, &uart->cr3);
- writel(0x8000, &uart->cr4);
- writel(0x2b, &uart->esc);
- writel(0, &uart->tim);
- writel(0, &uart->ts);
+ _mxc_serial_init(plat->reg);
return 0;
}
.flags = DM_FLAG_PRE_RELOC,
};
#endif
+
+#ifdef CONFIG_DEBUG_UART_MXC
+#include <debug_uart.h>
+
+static inline void _debug_uart_init(void)
+{
+ struct mxc_uart *base = (struct mxc_uart *)CONFIG_DEBUG_UART_BASE;
+
+ _mxc_serial_init(base);
+ _mxc_serial_setbrg(base, CONFIG_DEBUG_UART_CLOCK,
+ CONFIG_BAUDRATE, false);
+}
+
+static inline void _debug_uart_putc(int ch)
+{
+ struct mxc_uart *base = (struct mxc_uart *)CONFIG_DEBUG_UART_BASE;
+
+ while (!(readl(&base->ts) & UTS_TXEMPTY))
+ WATCHDOG_RESET();
+
+ writel(ch, &base->txd);
+}
+
+DEBUG_UART_FUNCS
+
+#endif
#include <asm/io.h>
#include <serial.h>
#include <asm/arch/stm32.h>
-#include <dm/platform_data/serial_stm32x7.h>
#include "serial_stm32x7.h"
DECLARE_GLOBAL_DATA_PTR;
{
struct stm32x7_serial_platdata *plat = dev->platdata;
struct stm32_usart *const usart = plat->base;
- u32 clock, int_div, mantissa, fraction, oversampling;
+ u32 int_div, mantissa, fraction, oversampling;
- if (((u32)usart & STM32_BUS_MASK) == APB1_PERIPH_BASE)
- clock = clock_get(CLOCK_APB1);
- else if (((u32)usart & STM32_BUS_MASK) == APB2_PERIPH_BASE)
- clock = clock_get(CLOCK_APB2);
- else
- return -EINVAL;
-
- int_div = DIV_ROUND_CLOSEST(clock, baudrate);
+ int_div = DIV_ROUND_CLOSEST(plat->clock_rate, baudrate);
if (int_div < 16) {
oversampling = 8;
}
#endif
+ plat->clock_rate = clk_get_rate(&clk);
+ if (plat->clock_rate < 0) {
+ clk_disable(&clk);
+ return plat->clock_rate;
+ };
+
/* Disable usart-> disable overrun-> enable usart */
clrbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE);
setbits_le32(&usart->cr3, USART_CR3_OVRDIS);
u32 tx_dr;
};
+/* Information about a serial port */
+struct stm32x7_serial_platdata {
+ struct stm32_usart *base; /* address of registers in physical memory */
+ unsigned long int clock_rate;
+};
#define USART_CR1_OVER8 (1 << 15)
#define USART_CR1_TE (1 << 3)
#include <asm/gpio.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
-#include <asm/imx-common/spi.h>
+#include <asm/mach-imx/spi.h>
#ifdef CONFIG_MX27
/* i.MX27 has a completely wrong register layout and register definitions in the
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/dma.h>
+#include <asm/mach-imx/dma.h>
#define MXS_SPI_MAX_TIMEOUT 1000000
#define MXS_SPI_PORT_OFFSET 0x2000
struct stm32_qspi_priv {
struct stm32_qspi_regs *regs;
+ ulong clock_rate;
u32 max_hz;
u32 mode;
dev_err(bus, "failed to enable clock\n");
return ret;
}
+
+ priv->clock_rate = clk_get_rate(&clk);
+ if (priv->clock_rate < 0) {
+ clk_disable(&clk);
+ return priv->clock_rate;
+ }
+
#endif
setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
if (speed > plat->max_hz)
speed = plat->max_hz;
- u32 qspi_clk = clock_get(CLOCK_AHB);
+ u32 qspi_clk = priv->clock_rate;
u32 prescaler = 255;
if (speed > 0) {
prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;
#include <asm/arch/clock.h>
#include <asm/arch-tegra/clk_rst.h>
#include <spi.h>
-#include <fdtdec.h>
#include "tegra_spi.h"
DECLARE_GLOBAL_DATA_PTR;
static int tegra114_spi_ofdata_to_platdata(struct udevice *bus)
{
struct tegra_spi_platdata *plat = bus->platdata;
- const void *blob = gd->fdt_blob;
- int node = dev_of_offset(bus);
- plat->base = devfdt_get_addr(bus);
- plat->periph_id = clock_decode_periph_id(blob, node);
+ plat->base = dev_read_addr(bus);
+ plat->periph_id = clock_decode_periph_id(bus);
if (plat->periph_id == PERIPH_ID_NONE) {
debug("%s: could not decode periph id %d\n", __func__,
}
/* Use 500KHz as a suitable default */
- plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
- 500000);
- plat->deactivate_delay_us = fdtdec_get_int(blob, node,
- "spi-deactivate-delay", 0);
+ plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
+ 500000);
+ plat->deactivate_delay_us = dev_read_u32_default(bus,
+ "spi-deactivate-delay", 0);
debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
__func__, plat->base, plat->periph_id, plat->frequency,
plat->deactivate_delay_us);
int node = dev_of_offset(bus);
plat->base = devfdt_get_addr(bus);
- plat->periph_id = clock_decode_periph_id(blob, node);
+ plat->periph_id = clock_decode_periph_id(bus);
if (plat->periph_id == PERIPH_ID_NONE) {
debug("%s: could not decode periph id %d\n", __func__,
int node = dev_of_offset(bus);
plat->base = devfdt_get_addr(bus);
- plat->periph_id = clock_decode_periph_id(blob, node);
+ plat->periph_id = clock_decode_periph_id(bus);
if (plat->periph_id == PERIPH_ID_NONE) {
debug("%s: could not decode periph id %d\n", __func__,
int node = dev_of_offset(bus);
plat->base = devfdt_get_addr(bus);
- plat->periph_id = clock_decode_periph_id(blob, node);
+ plat->periph_id = clock_decode_periph_id(bus);
if (plat->periph_id == PERIPH_ID_NONE) {
debug("%s: could not decode periph id %d\n", __func__,
1 << 7),
.bPwrOn2PwrGood = 2,
.bHubContrCurrent = 5,
- .DeviceRemovable = {0, 0xff}, /* all ports removeable */
+ {
+ {
+ /* all ports removeable */
+ .DeviceRemovable = {0, 0xff}
+ }
+ }
#if SANDBOX_NUM_PORTS > 8
#error "This code sets up an incorrect mask"
#endif
}
if (dev->out_ep->driver_data) {
+ free(dev->out_req->buf);
dev->out_req->buf = NULL;
usb_ep_free_request(dev->out_ep, dev->out_req);
usb_ep_disable(dev->out_ep);
SoCs, which includes Armada8K, Armada3700 and other Armada
family SoCs.
+config USB_XHCI_PCI
+ bool "Support for PCI-based xHCI USB controller"
+ depends on DM_USB
+ default y if X86
+ help
+ Enables support for the PCI-based xHCI controller.
+
config USB_XHCI_ROCKCHIP
bool "Support for Rockchip on-chip xHCI USB controller"
depends on ARCH_ROCKCHIP
#include <common.h>
#include <clk.h>
+#include <dm/ofnode.h>
+#include <generic-phy.h>
#include <reset.h>
#include <asm/io.h>
#include <dm.h>
*/
struct generic_ehci {
struct ehci_ctrl ctrl;
+ struct clk *clocks;
+ struct reset_ctl *resets;
+ struct phy phy;
+ int clock_count;
+ int reset_count;
};
static int ehci_usb_probe(struct udevice *dev)
{
+ struct generic_ehci *priv = dev_get_priv(dev);
struct ehci_hccr *hccr;
struct ehci_hcor *hcor;
- int i;
-
- for (i = 0; ; i++) {
- struct clk clk;
- int ret;
-
- ret = clk_get_by_index(dev, i, &clk);
- if (ret < 0)
- break;
- if (clk_enable(&clk))
- printf("failed to enable clock %d\n", i);
- clk_free(&clk);
+ int i, err, ret, clock_nb, reset_nb;
+
+ err = 0;
+ priv->clock_count = 0;
+ clock_nb = ofnode_count_phandle_with_args(dev_ofnode(dev), "clocks",
+ "#clock-cells");
+ if (clock_nb > 0) {
+ priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk),
+ GFP_KERNEL);
+ if (!priv->clocks)
+ return -ENOMEM;
+
+ for (i = 0; i < clock_nb; i++) {
+ err = clk_get_by_index(dev, i, &priv->clocks[i]);
+
+ if (err < 0)
+ break;
+ err = clk_enable(&priv->clocks[i]);
+ if (err) {
+ error("failed to enable clock %d\n", i);
+ clk_free(&priv->clocks[i]);
+ goto clk_err;
+ }
+ priv->clock_count++;
+ }
+ } else {
+ if (clock_nb != -ENOENT) {
+ error("failed to get clock phandle(%d)\n", clock_nb);
+ return clock_nb;
+ }
+ }
+
+ priv->reset_count = 0;
+ reset_nb = ofnode_count_phandle_with_args(dev_ofnode(dev), "resets",
+ "#reset-cells");
+ if (reset_nb > 0) {
+ priv->resets = devm_kcalloc(dev, reset_nb,
+ sizeof(struct reset_ctl),
+ GFP_KERNEL);
+ if (!priv->resets)
+ return -ENOMEM;
+
+ for (i = 0; i < reset_nb; i++) {
+ err = reset_get_by_index(dev, i, &priv->resets[i]);
+ if (err < 0)
+ break;
+
+ if (reset_deassert(&priv->resets[i])) {
+ error("failed to deassert reset %d\n", i);
+ reset_free(&priv->resets[i]);
+ goto reset_err;
+ }
+ priv->reset_count++;
+ }
+ } else {
+ if (reset_nb != -ENOENT) {
+ error("failed to get reset phandle(%d)\n", reset_nb);
+ goto clk_err;
+ }
}
- for (i = 0; ; i++) {
- struct reset_ctl reset;
- int ret;
+ err = generic_phy_get_by_index(dev, 0, &priv->phy);
+ if (err) {
+ if (err != -ENOENT) {
+ error("failed to get usb phy\n");
+ goto reset_err;
+ }
+ } else {
- ret = reset_get_by_index(dev, i, &reset);
- if (ret < 0)
- break;
- if (reset_deassert(&reset))
- printf("failed to deassert reset %d\n", i);
- reset_free(&reset);
+ err = generic_phy_init(&priv->phy);
+ if (err) {
+ error("failed to init usb phy\n");
+ goto reset_err;
+ }
}
hccr = map_physmem(devfdt_get_addr(dev), 0x100, MAP_NOCACHE);
hcor = (struct ehci_hcor *)((uintptr_t)hccr +
HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
- return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
+ err = ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
+ if (err)
+ goto phy_err;
+
+ return 0;
+
+phy_err:
+ if (generic_phy_valid(&priv->phy)) {
+ ret = generic_phy_exit(&priv->phy);
+ if (ret)
+ error("failed to release phy\n");
+ }
+
+reset_err:
+ ret = reset_release_all(priv->resets, priv->reset_count);
+ if (ret)
+ error("failed to assert all resets\n");
+clk_err:
+ ret = clk_release_all(priv->clocks, priv->clock_count);
+ if (ret)
+ error("failed to disable all clocks\n");
+
+ return err;
+}
+
+static int ehci_usb_remove(struct udevice *dev)
+{
+ struct generic_ehci *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = ehci_deregister(dev);
+ if (ret)
+ return ret;
+
+ if (generic_phy_valid(&priv->phy)) {
+ ret = generic_phy_exit(&priv->phy);
+ if (ret)
+ return ret;
+ }
+
+ ret = reset_release_all(priv->resets, priv->reset_count);
+ if (ret)
+ return ret;
+
+ return clk_release_all(priv->clocks, priv->clock_count);
}
static const struct udevice_id ehci_usb_ids[] = {
.id = UCLASS_USB,
.of_match = ehci_usb_ids,
.probe = ehci_usb_probe,
- .remove = ehci_deregister,
+ .remove = ehci_usb_remove,
.ops = &ehci_usb_ops,
.priv_auto_alloc_size = sizeof(struct generic_ehci),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
0, /* wHubCharacteristics */
10, /* bPwrOn2PwrGood */
0, /* bHubCntrCurrent */
- {}, /* Device removable */
- {} /* at most 7 ports! XXX */
+ { /* Device removable */
+ } /* at most 7 ports! XXX */
},
{
0x12, /* bLength */
static uint32_t *ehci_get_portsc_register(struct ehci_ctrl *ctrl, int port)
{
- if (port < 0 || port >= CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) {
+ int max_ports = HCS_N_PORTS(ehci_readl(&ctrl->hccr->cr_hcsparams));
+
+ if (port < 0 || port >= max_ports) {
/* Printing the message would cause a scan failure! */
- debug("The request port(%u) is not configured\n", port);
+ debug("The request port(%u) exceeds maximum port number\n",
+ port);
return NULL;
}
{
int i, ret = 0;
uint32_t cmd, reg;
+ int max_ports = HCS_N_PORTS(ehci_readl(&ctrl->hccr->cr_hcsparams));
if (!ctrl || !ctrl->hcor)
return -EINVAL;
100 * 1000);
if (!ret) {
- for (i = 0; i < CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS; i++) {
+ for (i = 0; i < max_ports; i++) {
reg = ehci_readl(&ctrl->hcor->or_portsc[i]);
reg |= EHCI_PS_SUSP;
ehci_writel(&ctrl->hcor->or_portsc[i], reg);
return -1;
}
-const struct ehci_ops default_ehci_ops = {
+static const struct ehci_ops default_ehci_ops = {
.set_usb_mode = ehci_set_usbmode,
.get_port_speed = ehci_get_port_speed,
.powerup_fixup = ehci_powerup_fixup,
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/sys_proto.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/sys_proto.h>
#include <dm.h>
#include <asm/mach-types.h>
#include <power/regulator.h>
#include <usb.h>
#include <usb/ulpi.h>
#include <libfdt.h>
-#include <fdtdec.h>
#include "ehci.h"
static int fdt_decode_usb(struct udevice *dev, struct fdt_usb *config)
{
- const void *blob = gd->fdt_blob;
- int node = dev_of_offset(dev);
const char *phy, *mode;
- config->reg = (struct usb_ctlr *)devfdt_get_addr(dev);
- mode = fdt_getprop(blob, node, "dr_mode", NULL);
+ config->reg = (struct usb_ctlr *)dev_read_addr(dev);
+ debug("reg=%p\n", config->reg);
+ mode = dev_read_string(dev, "dr_mode");
if (mode) {
if (0 == strcmp(mode, "host"))
config->dr_mode = DR_MODE_HOST;
config->dr_mode = DR_MODE_HOST;
}
- phy = fdt_getprop(blob, node, "phy_type", NULL);
+ phy = dev_read_string(dev, "phy_type");
config->utmi = phy && 0 == strcmp("utmi", phy);
config->ulpi = phy && 0 == strcmp("ulpi", phy);
- config->enabled = fdtdec_get_is_enabled(blob, node);
- config->has_legacy_mode = fdtdec_get_bool(blob, node,
- "nvidia,has-legacy-mode");
- config->periph_id = clock_decode_periph_id(blob, node);
+ config->has_legacy_mode = dev_read_bool(dev, "nvidia,has-legacy-mode");
+ config->periph_id = clock_decode_periph_id(dev);
if (config->periph_id == PERIPH_ID_NONE) {
debug("%s: Missing/invalid peripheral ID\n", __func__);
return -EINVAL;
}
- gpio_request_by_name_nodev(offset_to_ofnode(node), "nvidia,vbus-gpio",
- 0, &config->vbus_gpio, GPIOD_IS_OUT);
- gpio_request_by_name_nodev(offset_to_ofnode(node),
- "nvidia,phy-reset-gpio", 0,
- &config->phy_reset_gpio, GPIOD_IS_OUT);
- debug("enabled=%d, legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, "
- "vbus=%d, phy_reset=%d, dr_mode=%d\n",
- config->enabled, config->has_legacy_mode, config->utmi,
- config->ulpi, config->periph_id,
- gpio_get_number(&config->vbus_gpio),
- gpio_get_number(&config->phy_reset_gpio), config->dr_mode);
+ gpio_request_by_name(dev, "nvidia,vbus-gpio", 0, &config->vbus_gpio,
+ GPIOD_IS_OUT);
+ gpio_request_by_name(dev, "nvidia,phy-reset-gpio", 0,
+ &config->phy_reset_gpio, GPIOD_IS_OUT);
+ debug("legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, vbus=%d, phy_reset=%d, dr_mode=%d, reg=%p\n",
+ config->has_legacy_mode, config->utmi, config->ulpi,
+ config->periph_id, gpio_get_number(&config->vbus_gpio),
+ gpio_get_number(&config->phy_reset_gpio), config->dr_mode,
+ config->reg);
return 0;
}
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/regs-usbphy.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/regs-usbphy.h>
#include <usb/ehci-ci.h>
#include <libfdt.h>
#include <fdtdec.h>
#include <usb.h>
-#if !defined(CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS)
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
-#endif
+/* Section 2.2.3 - N_PORTS */
+#define MAX_HC_PORTS 15
/*
* Register Space.
uint32_t _reserved_1_[6];
uint32_t or_configflag;
#define FLAG_CF (1 << 0) /* true: we'll support "high speed" */
- uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS];
+ uint32_t or_portsc[MAX_HC_PORTS];
#define PORTSC_PSPD(x) (((x) >> 26) & 0x3)
#define PORTSC_PSPD_FS 0x0
#define PORTSC_PSPD_LS 0x1
*/
#include <common.h>
+#include <clk.h>
#include <dm.h>
+#include <dm/ofnode.h>
+#include <generic-phy.h>
+#include <reset.h>
#include "ohci.h"
#if !defined(CONFIG_USB_OHCI_NEW)
struct generic_ohci {
ohci_t ohci;
+ struct clk *clocks; /* clock list */
+ struct reset_ctl *resets; /* reset list */
+ struct phy phy;
+ int clock_count; /* number of clock in clock list */
+ int reset_count; /* number of reset in reset list */
};
static int ohci_usb_probe(struct udevice *dev)
{
struct ohci_regs *regs = (struct ohci_regs *)devfdt_get_addr(dev);
+ struct generic_ohci *priv = dev_get_priv(dev);
+ int i, err, ret, clock_nb, reset_nb;
- return ohci_register(dev, regs);
+ err = 0;
+ priv->clock_count = 0;
+ clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
+ if (clock_nb > 0) {
+ priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk),
+ GFP_KERNEL);
+ if (!priv->clocks)
+ return -ENOMEM;
+
+ for (i = 0; i < clock_nb; i++) {
+ err = clk_get_by_index(dev, i, &priv->clocks[i]);
+ if (err < 0)
+ break;
+
+ err = clk_enable(&priv->clocks[i]);
+ if (err) {
+ error("failed to enable clock %d\n", i);
+ clk_free(&priv->clocks[i]);
+ goto clk_err;
+ }
+ priv->clock_count++;
+ }
+ } else if (clock_nb != -ENOENT) {
+ error("failed to get clock phandle(%d)\n", clock_nb);
+ return clock_nb;
+ }
+
+ priv->reset_count = 0;
+ reset_nb = dev_count_phandle_with_args(dev, "resets", "#reset-cells");
+ if (reset_nb > 0) {
+ priv->resets = devm_kcalloc(dev, reset_nb,
+ sizeof(struct reset_ctl),
+ GFP_KERNEL);
+ if (!priv->resets)
+ return -ENOMEM;
+
+ for (i = 0; i < reset_nb; i++) {
+ err = reset_get_by_index(dev, i, &priv->resets[i]);
+ if (err < 0)
+ break;
+
+ err = reset_deassert(&priv->resets[i]);
+ if (err) {
+ error("failed to deassert reset %d\n", i);
+ reset_free(&priv->resets[i]);
+ goto reset_err;
+ }
+ priv->reset_count++;
+ }
+ } else if (reset_nb != -ENOENT) {
+ error("failed to get reset phandle(%d)\n", reset_nb);
+ goto clk_err;
+ }
+
+ err = generic_phy_get_by_index(dev, 0, &priv->phy);
+ if (err) {
+ if (err != -ENOENT) {
+ error("failed to get usb phy\n");
+ goto reset_err;
+ }
+ } else {
+
+ err = generic_phy_init(&priv->phy);
+ if (err) {
+ error("failed to init usb phy\n");
+ goto reset_err;
+ }
+ }
+
+ err = ohci_register(dev, regs);
+ if (err)
+ goto phy_err;
+
+ return 0;
+
+phy_err:
+ if (generic_phy_valid(&priv->phy)) {
+ ret = generic_phy_exit(&priv->phy);
+ if (ret)
+ error("failed to release phy\n");
+ }
+
+reset_err:
+ ret = reset_release_all(priv->resets, priv->reset_count);
+ if (ret)
+ error("failed to assert all resets\n");
+clk_err:
+ ret = clk_release_all(priv->clocks, priv->clock_count);
+ if (ret)
+ error("failed to disable all clocks\n");
+
+ return err;
}
static int ohci_usb_remove(struct udevice *dev)
{
- return ohci_deregister(dev);
+ struct generic_ohci *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = ohci_deregister(dev);
+ if (ret)
+ return ret;
+
+ if (generic_phy_valid(&priv->phy)) {
+ ret = generic_phy_exit(&priv->phy);
+ if (ret)
+ return ret;
+ }
+
+ ret = reset_release_all(priv->resets, priv->reset_count);
+ if (ret)
+ return ret;
+
+ return clk_release_all(priv->clocks, priv->clock_count);
}
static const struct udevice_id ohci_usb_ids[] = {
return ops->reset_root_port(bus, udev);
}
+int usb_update_hub_device(struct usb_device *udev)
+{
+ struct udevice *bus = udev->controller_dev;
+ struct dm_usb_ops *ops = usb_get_ops(bus);
+
+ if (!ops->update_hub_device)
+ return -ENOSYS;
+
+ return ops->update_hub_device(bus, udev);
+}
+
int usb_stop(void)
{
struct udevice *bus;
#ifdef CONFIG_USB_STORAGE
usb_stor_reset();
#endif
- usb_hub_reset();
uc_priv->companion_device_count = 0;
usb_started = 0;
int ret;
asynch_allowed = 1;
- usb_hub_reset();
ret = uclass_get(UCLASS_USB, &uc);
if (ret)
}
/* returns 0 if no match, 1 if match */
-int usb_match_device(const struct usb_device_descriptor *desc,
- const struct usb_device_id *id)
+static int usb_match_device(const struct usb_device_descriptor *desc,
+ const struct usb_device_id *id)
{
if ((id->match_flags & USB_DEVICE_ID_MATCH_VENDOR) &&
id->idVendor != le16_to_cpu(desc->idVendor))
}
/* returns 0 if no match, 1 if match */
-int usb_match_one_id_intf(const struct usb_device_descriptor *desc,
- const struct usb_interface_descriptor *int_desc,
- const struct usb_device_id *id)
+static int usb_match_one_id_intf(const struct usb_device_descriptor *desc,
+ const struct usb_interface_descriptor *int_desc,
+ const struct usb_device_id *id)
{
/* The interface class, subclass, protocol and number should never be
* checked for a match if the device class is Vendor Specific,
}
/* returns 0 if no match, 1 if match */
-int usb_match_one_id(struct usb_device_descriptor *desc,
- struct usb_interface_descriptor *int_desc,
- const struct usb_device_id *id)
+static int usb_match_one_id(struct usb_device_descriptor *desc,
+ struct usb_interface_descriptor *int_desc,
+ const struct usb_device_id *id)
{
if (!usb_match_device(desc, id))
return 0;
return change;
}
-int usb_child_post_bind(struct udevice *dev)
+static int usb_child_post_bind(struct udevice *dev)
{
struct usb_dev_platdata *plat = dev_get_parent_platdata(dev);
int val;
*/
#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <generic-phy.h>
+#include <usb.h>
+
+#include "xhci.h"
#include <asm/io.h>
#include <linux/usb/dwc3.h>
+#include <linux/usb/otg.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct xhci_dwc3_platdata {
+ struct phy usb_phy;
+};
void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
{
DWC3_GCTL_PRTCAPDIR(mode));
}
-void dwc3_phy_reset(struct dwc3 *dwc3_reg)
+static void dwc3_phy_reset(struct dwc3 *dwc3_reg)
{
/* Assert USB3 PHY reset */
setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL |
GFLADJ_30MHZ(val));
}
+
+#ifdef CONFIG_DM_USB
+static int xhci_dwc3_probe(struct udevice *dev)
+{
+ struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
+ struct xhci_hcor *hcor;
+ struct xhci_hccr *hccr;
+ struct dwc3 *dwc3_reg;
+ enum usb_dr_mode dr_mode;
+ int ret;
+
+ hccr = (struct xhci_hccr *)((uintptr_t)dev_read_addr(dev));
+ hcor = (struct xhci_hcor *)((uintptr_t)hccr +
+ HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
+
+ ret = generic_phy_get_by_index(dev, 0, &plat->usb_phy);
+ if (ret) {
+ if (ret != -ENOENT) {
+ error("Failed to get USB PHY for %s\n", dev->name);
+ return ret;
+ }
+ } else {
+ ret = generic_phy_init(&plat->usb_phy);
+ if (ret) {
+ error("Can't init USB PHY for %s\n", dev->name);
+ return ret;
+ }
+ }
+
+ dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET);
+
+ dwc3_core_init(dwc3_reg);
+
+ dr_mode = usb_get_dr_mode(dev_of_offset(dev));
+ if (dr_mode == USB_DR_MODE_UNKNOWN)
+ /* by default set dual role mode to HOST */
+ dr_mode = USB_DR_MODE_HOST;
+
+ dwc3_set_mode(dwc3_reg, dr_mode);
+
+ return xhci_register(dev, hccr, hcor);
+}
+
+static int xhci_dwc3_remove(struct udevice *dev)
+{
+ struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
+ int ret;
+
+ if (generic_phy_valid(&plat->usb_phy)) {
+ ret = generic_phy_exit(&plat->usb_phy);
+ if (ret) {
+ error("Can't deinit USB PHY for %s\n", dev->name);
+ return ret;
+ }
+ }
+
+ return xhci_deregister(dev);
+}
+
+static const struct udevice_id xhci_dwc3_ids[] = {
+ { .compatible = "snps,dwc3" },
+ { }
+};
+
+U_BOOT_DRIVER(xhci_dwc3) = {
+ .name = "xhci-dwc3",
+ .id = UCLASS_USB,
+ .of_match = xhci_dwc3_ids,
+ .probe = xhci_dwc3_probe,
+ .remove = xhci_dwc3_remove,
+ .ops = &xhci_usb_ops,
+ .priv_auto_alloc_size = sizeof(struct xhci_ctrl),
+ .platdata_auto_alloc_size = sizeof(struct xhci_dwc3_platdata),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
+#endif
free(ring);
}
+/**
+ * Free the scratchpad buffer array and scratchpad buffers
+ *
+ * @ctrl host controller data structure
+ * @return none
+ */
+static void xhci_scratchpad_free(struct xhci_ctrl *ctrl)
+{
+ if (!ctrl->scratchpad)
+ return;
+
+ ctrl->dcbaa->dev_context_ptrs[0] = 0;
+
+ free((void *)(uintptr_t)ctrl->scratchpad->sp_array[0]);
+ free(ctrl->scratchpad->sp_array);
+ free(ctrl->scratchpad);
+ ctrl->scratchpad = NULL;
+}
+
/**
* frees the "xhci_container_ctx" pointer passed
*
{
xhci_ring_free(ctrl->event_ring);
xhci_ring_free(ctrl->cmd_ring);
+ xhci_scratchpad_free(ctrl);
xhci_free_virt_devices(ctrl);
free(ctrl->erst.entries);
free(ctrl->dcbaa);
return ring;
}
+/**
+ * Set up the scratchpad buffer array and scratchpad buffers
+ *
+ * @ctrl host controller data structure
+ * @return -ENOMEM if buffer allocation fails, 0 on success
+ */
+static int xhci_scratchpad_alloc(struct xhci_ctrl *ctrl)
+{
+ struct xhci_hccr *hccr = ctrl->hccr;
+ struct xhci_hcor *hcor = ctrl->hcor;
+ struct xhci_scratchpad *scratchpad;
+ int num_sp;
+ uint32_t page_size;
+ void *buf;
+ int i;
+
+ num_sp = HCS_MAX_SCRATCHPAD(xhci_readl(&hccr->cr_hcsparams2));
+ if (!num_sp)
+ return 0;
+
+ scratchpad = malloc(sizeof(*scratchpad));
+ if (!scratchpad)
+ goto fail_sp;
+ ctrl->scratchpad = scratchpad;
+
+ scratchpad->sp_array = xhci_malloc(num_sp * sizeof(u64));
+ if (!scratchpad->sp_array)
+ goto fail_sp2;
+ ctrl->dcbaa->dev_context_ptrs[0] =
+ cpu_to_le64((uintptr_t)scratchpad->sp_array);
+
+ page_size = xhci_readl(&hcor->or_pagesize) & 0xffff;
+ for (i = 0; i < 16; i++) {
+ if ((0x1 & page_size) != 0)
+ break;
+ page_size = page_size >> 1;
+ }
+ BUG_ON(i == 16);
+
+ page_size = 1 << (i + 12);
+ buf = memalign(page_size, num_sp * page_size);
+ if (!buf)
+ goto fail_sp3;
+ memset(buf, '\0', num_sp * page_size);
+ xhci_flush_cache((uintptr_t)buf, num_sp * page_size);
+
+ for (i = 0; i < num_sp; i++) {
+ uintptr_t ptr = (uintptr_t)buf + i * page_size;
+ scratchpad->sp_array[i] = cpu_to_le64(ptr);
+ }
+
+ return 0;
+
+fail_sp3:
+ free(scratchpad->sp_array);
+
+fail_sp2:
+ free(scratchpad);
+ ctrl->scratchpad = NULL;
+
+fail_sp:
+ return -ENOMEM;
+}
+
/**
* Allocates the Container context
*
xhci_writeq(&ctrl->ir_set->erst_base, val_64);
+ /* set up the scratchpad buffer array and scratchpad buffers */
+ xhci_scratchpad_alloc(ctrl);
+
/* initializing the virtual devices to NULL */
for (i = 0; i < MAX_HC_SLOTS; ++i)
ctrl->devs[i] = NULL;
* @param udev pointer to the Device Data Structure
* @return returns negative value on failure else 0 on success
*/
-void xhci_setup_addressable_virt_dev(struct xhci_ctrl *ctrl, int slot_id,
- int speed, int hop_portnr)
+void xhci_setup_addressable_virt_dev(struct xhci_ctrl *ctrl,
+ struct usb_device *udev, int hop_portnr)
{
struct xhci_virt_device *virt_dev;
struct xhci_ep_ctx *ep0_ctx;
struct xhci_slot_ctx *slot_ctx;
u32 port_num = 0;
u64 trb_64 = 0;
+ int slot_id = udev->slot_id;
+ int speed = udev->speed;
+ int route = 0;
+#ifdef CONFIG_DM_USB
+ struct usb_device *dev = udev;
+ struct usb_hub_device *hub;
+#endif
virt_dev = ctrl->devs[slot_id];
slot_ctx = xhci_get_slot_ctx(ctrl, virt_dev->in_ctx);
/* Only the control endpoint is valid - one endpoint context */
- slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | 0);
+ slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
+
+#ifdef CONFIG_DM_USB
+ /* Calculate the route string for this device */
+ port_num = dev->portnr;
+ while (!usb_hub_is_root_hub(dev->dev)) {
+ hub = dev_get_uclass_priv(dev->dev);
+ /*
+ * Each hub in the topology is expected to have no more than
+ * 15 ports in order for the route string of a device to be
+ * unique. SuperSpeed hubs are restricted to only having 15
+ * ports, but FS/LS/HS hubs are not. The xHCI specification
+ * says that if the port number the device is greater than 15,
+ * that portion of the route string shall be set to 15.
+ */
+ if (port_num > 15)
+ port_num = 15;
+ route |= port_num << (hub->hub_depth * 4);
+ dev = dev_get_parent_priv(dev->dev);
+ port_num = dev->portnr;
+ dev = dev_get_parent_priv(dev->dev->parent);
+ }
+
+ debug("route string %x\n", route);
+#endif
+ slot_ctx->dev_info |= route;
switch (speed) {
case USB_SPEED_SUPER:
BUG();
}
+#ifdef CONFIG_DM_USB
+ /* Set up TT fields to support FS/LS devices */
+ if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) {
+ dev = dev_get_parent_priv(udev->dev);
+ if (dev->speed == USB_SPEED_HIGH) {
+ hub = dev_get_uclass_priv(udev->dev);
+ if (hub->tt.multi)
+ slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
+ slot_ctx->tt_info |= cpu_to_le32(TT_PORT(udev->portnr));
+ slot_ctx->tt_info |= cpu_to_le32(TT_SLOT(dev->slot_id));
+ }
+ }
+#endif
+
port_num = hop_portnr;
debug("port_num = %d\n", port_num);
#include <common.h>
#include <dm.h>
-#include <errno.h>
#include <pci.h>
#include <usb.h>
-
#include "xhci.h"
-#ifndef CONFIG_DM_USB
-
-/*
- * Create the appropriate control structures to manage a new XHCI host
- * controller.
- */
-int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr,
- struct xhci_hcor **ret_hcor)
-{
- struct xhci_hccr *hccr;
- struct xhci_hcor *hcor;
- pci_dev_t pdev;
- uint32_t cmd;
- int len;
-
- pdev = pci_find_class(PCI_CLASS_SERIAL_USB_XHCI, index);
- if (pdev < 0) {
- printf("XHCI host controller not found\n");
- return -1;
- }
-
- hccr = (struct xhci_hccr *)pci_map_bar(pdev,
- PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
- len = HC_LENGTH(xhci_readl(&hccr->cr_capbase));
- hcor = (struct xhci_hcor *)((uint32_t)hccr + len);
-
- debug("XHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n",
- (uint32_t)hccr, (uint32_t)hcor, len);
-
- *ret_hccr = hccr;
- *ret_hcor = hcor;
-
- /* enable busmaster */
- pci_read_config_dword(pdev, PCI_COMMAND, &cmd);
- cmd |= PCI_COMMAND_MASTER;
- pci_write_config_dword(pdev, PCI_COMMAND, cmd);
-
- return 0;
-}
-
-/*
- * Destroy the appropriate control structures corresponding * to the XHCI host
- * controller
- */
-void xhci_hcd_stop(int index)
-{
-}
-
-#else
-
-struct xhci_pci_priv {
- struct xhci_ctrl ctrl; /* Needs to come first in this struct! */
-};
-
static void xhci_pci_init(struct udevice *dev, struct xhci_hccr **ret_hccr,
struct xhci_hcor **ret_hcor)
{
return xhci_register(dev, hccr, hcor);
}
-static int xhci_pci_remove(struct udevice *dev)
-{
- int ret;
-
- ret = xhci_deregister(dev);
- if (ret)
- return ret;
-
- return 0;
-}
-
static const struct udevice_id xhci_pci_ids[] = {
{ .compatible = "xhci-pci" },
{ }
.name = "xhci_pci",
.id = UCLASS_USB,
.probe = xhci_pci_probe,
- .remove = xhci_pci_remove,
+ .remove = xhci_deregister,
.of_match = xhci_pci_ids,
.ops = &xhci_usb_ops,
.platdata_auto_alloc_size = sizeof(struct usb_platdata),
- .priv_auto_alloc_size = sizeof(struct xhci_pci_priv),
+ .priv_auto_alloc_size = sizeof(struct xhci_ctrl),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
};
U_BOOT_PCI_DEVICE(xhci_pci, xhci_pci_supported);
-
-#endif /* CONFIG_DM_USB */
fields[0] = lower_32_bits(val_64);
fields[1] = upper_32_bits(val_64);
fields[2] = 0;
- fields[3] = TRB_TYPE(cmd) | EP_ID_FOR_TRB(ep_index) |
- SLOT_ID_FOR_TRB(slot_id) | ctrl->cmd_ring->cycle_state;
+ fields[3] = TRB_TYPE(cmd) | SLOT_ID_FOR_TRB(slot_id) |
+ ctrl->cmd_ring->cycle_state;
+
+ /*
+ * Only 'reset endpoint', 'stop endpoint' and 'set TR dequeue pointer'
+ * commands need endpoint id encoded.
+ */
+ if (cmd >= TRB_RESET_EP && cmd <= TRB_SET_DEQ)
+ fields[3] |= EP_ID_FOR_TRB(ep_index);
queue_trb(ctrl, ctrl->cmd_ring, false, fields);
cpu_to_le16(0x8), /* wHubCharacteristics */
10, /* bPwrOn2PwrGood */
0, /* bHubCntrCurrent */
- {}, /* Device removable */
- {} /* at most 7 ports! XXX */
+ { /* Device removable */
+ } /* at most 7 ports! XXX */
},
{
0x12, /* bLength */
* @param hcor pointer to host controller operation registers
* @return -EBUSY if XHCI Controller is not halted else status of handshake
*/
-int xhci_reset(struct xhci_hcor *hcor)
+static int xhci_reset(struct xhci_hcor *hcor)
{
u32 cmd;
u32 state;
ifdesc = &udev->config.if_desc[0];
ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
- /* Zero the input context control */
- ctrl_ctx->add_flags = 0;
+ /* Initialize the input context control */
+ ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
ctrl_ctx->drop_flags = 0;
/* EP_FLAG gives values 1 & 4 for EP1OUT and EP2IN */
* so setting up the slot context.
*/
debug("Setting up addressable devices %p\n", ctrl->dcbaa);
- xhci_setup_addressable_virt_dev(ctrl, udev->slot_id, udev->speed,
- root_portnr);
+ xhci_setup_addressable_virt_dev(ctrl, udev, root_portnr);
ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
* @param udev pointer to the Device Data Structure
* @return Returns 0 on succes else return error code on failure
*/
-int _xhci_alloc_device(struct usb_device *udev)
+static int _xhci_alloc_device(struct usb_device *udev)
{
struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
union xhci_trb *event;
uint32_t reg;
volatile uint32_t *status_reg;
struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
+ struct xhci_hccr *hccr = ctrl->hccr;
struct xhci_hcor *hcor = ctrl->hcor;
+ int max_ports = HCS_MAX_PORTS(xhci_readl(&hccr->cr_hcsparams1));
if ((req->requesttype & USB_RT_PORT) &&
- le16_to_cpu(req->index) > CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS) {
- printf("The request port(%d) is not configured\n",
- le16_to_cpu(req->index) - 1);
+ le16_to_cpu(req->index) > max_ports) {
+ printf("The request port(%d) exceeds maximum port number\n",
+ le16_to_cpu(req->index) - 1);
return -EINVAL;
}
case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
switch (le16_to_cpu(req->value) >> 8) {
case USB_DT_HUB:
+ case USB_DT_SS_HUB:
debug("USB_DT_HUB config\n");
srcptr = &descriptor.hub;
srclen = 0x8;
#endif /* CONFIG_DM_USB */
#ifdef CONFIG_DM_USB
-/*
-static struct usb_device *get_usb_device(struct udevice *dev)
-{
- struct usb_device *udev;
-
- if (device_get_uclass_id(dev) == UCLASS_USB)
- udev = dev_get_uclass_priv(dev);
- else
- udev = dev_get_parent_priv(dev);
-
- return udev;
-}
-*/
-static bool is_root_hub(struct udevice *dev)
-{
- if (device_get_uclass_id(dev->parent) != UCLASS_USB_HUB)
- return true;
-
- return false;
-}
static int xhci_submit_control_msg(struct udevice *dev, struct usb_device *udev,
unsigned long pipe, void *buffer, int length,
hub = udev->dev;
if (device_get_uclass_id(hub) == UCLASS_USB_HUB) {
/* Figure out our port number on the root hub */
- if (is_root_hub(hub)) {
+ if (usb_hub_is_root_hub(hub)) {
root_portnr = udev->portnr;
} else {
- while (!is_root_hub(hub->parent))
+ while (!usb_hub_is_root_hub(hub->parent))
hub = hub->parent;
uhop = dev_get_parent_priv(hub);
root_portnr = uhop->portnr;
return _xhci_alloc_device(udev);
}
+static int xhci_update_hub_device(struct udevice *dev, struct usb_device *udev)
+{
+ struct xhci_ctrl *ctrl = dev_get_priv(dev);
+ struct usb_hub_device *hub = dev_get_uclass_priv(udev->dev);
+ struct xhci_virt_device *virt_dev;
+ struct xhci_input_control_ctx *ctrl_ctx;
+ struct xhci_container_ctx *out_ctx;
+ struct xhci_container_ctx *in_ctx;
+ struct xhci_slot_ctx *slot_ctx;
+ int slot_id = udev->slot_id;
+ unsigned think_time;
+
+ debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
+
+ /* Ignore root hubs */
+ if (usb_hub_is_root_hub(udev->dev))
+ return 0;
+
+ virt_dev = ctrl->devs[slot_id];
+ BUG_ON(!virt_dev);
+
+ out_ctx = virt_dev->out_ctx;
+ in_ctx = virt_dev->in_ctx;
+
+ ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
+ /* Initialize the input context control */
+ ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
+ ctrl_ctx->drop_flags = 0;
+
+ xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size);
+
+ /* slot context */
+ xhci_slot_copy(ctrl, in_ctx, out_ctx);
+ slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx);
+
+ /* Update hub related fields */
+ slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
+ if (hub->tt.multi && udev->speed == USB_SPEED_HIGH)
+ slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
+ slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(udev->maxchild));
+ /*
+ * Set TT think time - convert from ns to FS bit times.
+ * Note 8 FS bit times == (8 bits / 12000000 bps) ~= 666ns
+ *
+ * 0 = 8 FS bit times, 1 = 16 FS bit times,
+ * 2 = 24 FS bit times, 3 = 32 FS bit times.
+ *
+ * This field shall be 0 if the device is not a high-spped hub.
+ */
+ think_time = hub->tt.think_time;
+ if (think_time != 0)
+ think_time = (think_time / 666) - 1;
+ if (udev->speed == USB_SPEED_HIGH)
+ slot_ctx->tt_info |= cpu_to_le32(TT_THINK_TIME(think_time));
+
+ return xhci_configure_endpoints(udev, false);
+}
+
int xhci_register(struct udevice *dev, struct xhci_hccr *hccr,
struct xhci_hcor *hcor)
{
.bulk = xhci_submit_bulk_msg,
.interrupt = xhci_submit_int_msg,
.alloc_device = xhci_alloc_device,
+ .update_hub_device = xhci_update_hub_device,
};
#endif
/* Max number of USB devices for any host controller - limit in section 6.1 */
#define MAX_HC_SLOTS 256
/* Section 5.3.3 - MaxPorts */
-#define MAX_HC_PORTS 127
+#define MAX_HC_PORTS 255
/* Up to 16 ms to halt an HC */
#define XHCI_MAX_HALT_USEC (16*1000)
#define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
/* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
#define HCS_MAX_PORTS_SHIFT 24
-#define HCS_MAX_PORTS_MASK (0x7f << HCS_MAX_PORTS_SHIFT)
-#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
+#define HCS_MAX_PORTS_MASK (0xff << HCS_MAX_PORTS_SHIFT)
+#define HCS_MAX_PORTS(p) (((p) >> 24) & 0xff)
/* HCSPARAMS2 - hcs_params2 - bitmasks */
/* bits 0:3, frames or uframes that SW needs to queue transactions
#define HCS_IST(p) (((p) >> 0) & 0xf)
/* bits 4:7, max number of Event Ring segments */
#define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
+/* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */
/* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
-/* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */
-#define HCS_MAX_SCRATCHPAD(p) (((p) >> 27) & 0x1f)
+/* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */
+#define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f))
/* HCSPARAMS3 - hcs_params3 - bitmasks */
/* bits 0:7, Max U1 to U0 latency for the roothub ports */
volatile uint64_t or_dcbaap;
volatile uint32_t or_config;
volatile uint32_t reserved_2[241];
- struct xhci_hcor_port_regs portregs[CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS];
-
- uint32_t reserved_4[CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS * 254];
+ struct xhci_hcor_port_regs portregs[MAX_HC_PORTS];
};
/* USBCMD - USB command - command bitmasks */
* @type: Type of context. Used to calculated offsets to contained contexts.
* @size: Size of the context data
* @bytes: The raw context data given to HW
- * @dma: dma address of the bytes
*
* Represents either a Device or Input context. Holds a pointer to the raw
- * memory used for the context (bytes) and dma address of it (dma).
+ * memory used for the context (bytes).
*/
struct xhci_container_ctx {
unsigned type;
* The Slot ID of the hub that isolates the high speed signaling from
* this low or full-speed device. '0' if attached to root hub port.
*/
-#define TT_SLOT (0xff)
+#define TT_SLOT(p) (((p) & 0xff) << 0)
/*
* The number of the downstream facing port of the high-speed hub
* '0' if the device is not low or full speed.
*/
-#define TT_PORT (0xff << 8)
+#define TT_PORT(p) (((p) & 0xff) << 8)
#define TT_THINK_TIME(p) (((p) & 0x3) << 16)
/* dev_state bitmasks */
unsigned int erst_size;
};
+struct xhci_scratchpad {
+ u64 *sp_array;
+};
+
/*
* Each segment table entry is 4*32bits long. 1K seems like an ok size:
* (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
struct xhci_intr_reg *ir_set;
struct xhci_erst erst;
struct xhci_erst_entry entry[ERST_NUM_SEGS];
+ struct xhci_scratchpad *scratchpad;
struct xhci_virt_device *devs[MAX_HC_SLOTS];
int rootdev;
};
void xhci_slot_copy(struct xhci_ctrl *ctrl,
struct xhci_container_ctx *in_ctx,
struct xhci_container_ctx *out_ctx);
-void xhci_setup_addressable_virt_dev(struct xhci_ctrl *ctrl, int slot_id,
- int speed, int hop_portnr);
+void xhci_setup_addressable_virt_dev(struct xhci_ctrl *ctrl,
+ struct usb_device *udev, int hop_portnr);
void xhci_queue_command(struct xhci_ctrl *ctrl, u8 *ptr,
u32 slot_id, u32 ep_index, trb_type cmd);
void xhci_acknowledge_event(struct xhci_ctrl *ctrl);
#include <linux/errno.h>
#include <asm/io.h>
-#include <asm/imx-common/dma.h>
+#include <asm/mach-imx/dma.h>
#include "videomodes.h"
#include <errno.h>
#include <display.h>
#include <edid.h>
-#include <fdtdec.h>
#include <lcd.h>
#include <video.h>
#include <asm/gpio.h>
{
struct display_plat *disp_uc_plat;
struct dc_ctlr *dc_ctlr;
- const void *blob = gd->fdt_blob;
struct udevice *dp_dev;
const int href_to_sync = 1, vref_to_sync = 1;
int panel_bpp = 18; /* default 18 bits per pixel */
return ret;
}
- dc_ctlr = (struct dc_ctlr *)fdtdec_get_addr(blob, dev_of_offset(dev),
- "reg");
- if (fdtdec_decode_display_timing(blob, dev_of_offset(dev), 0, timing)) {
+ dc_ctlr = (struct dc_ctlr *)dev_read_addr(dev);
+ if (ofnode_decode_display_timing(dev_ofnode(dev), 0, timing)) {
debug("%s: Failed to decode display timing\n", __func__);
return -EINVAL;
}
debug("dc: failed to update window\n");
return ret;
}
+ debug("%s: ready\n", __func__);
return 0;
}
#include <dm.h>
#include <div64.h>
#include <errno.h>
-#include <fdtdec.h>
#include <video_bridge.h>
#include <asm/io.h>
#include <asm/arch-tegra/dc.h>
{
struct tegra_dp_plat *plat = dev_get_platdata(dev);
- plat->base = devfdt_get_addr(dev);
+ plat->base = dev_read_addr(dev);
return 0;
}
#include <common.h>
#include <dm.h>
#include <errno.h>
-#include <fdtdec.h>
#include <malloc.h>
#include <panel.h>
+#include <syscon.h>
#include <video_bridge.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
const struct display_timing *timing)
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
- const void *blob = gd->fdt_blob;
struct dc_ctlr *disp_ctrl;
u32 reg_val;
- int node;
/* Use the first display controller */
debug("%s\n", __func__);
- node = dev_of_offset(dc_dev);
- disp_ctrl = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg");
+ disp_ctrl = (struct dc_ctlr *)dev_read_addr(dc_dev);
tegra_dc_sor_enable_dc(disp_ctrl);
tegra_dc_sor_config_panel(sor, 0, link_cfg, timing);
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
int dc_reg_ctx[DC_REG_SAVE_SPACE];
- const void *blob = gd->fdt_blob;
struct dc_ctlr *disp_ctrl;
unsigned long dc_int_mask;
- int node;
int ret;
debug("%s\n", __func__);
/* Use the first display controller */
- node = dev_of_offset(dc_dev);
- disp_ctrl = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg");
+ disp_ctrl = (struct dc_ctlr *)dev_read_addr(dev);
/* Sleep mode */
tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ASY_HEAD_OP_SLEEP |
static int tegra_sor_ofdata_to_platdata(struct udevice *dev)
{
struct tegra_dc_sor_data *priv = dev_get_priv(dev);
- const void *blob = gd->fdt_blob;
- int node;
int ret;
- priv->base = (void *)fdtdec_get_addr(blob, dev_of_offset(dev), "reg");
+ priv->base = (void *)dev_read_addr(dev);
- node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_PMC);
- if (node < 0) {
- debug("%s: Cannot find PMC\n", __func__);
- return -ENOENT;
- }
- priv->pmc_base = (void *)fdtdec_get_addr(blob, node, "reg");
+ priv->pmc_base = (void *)syscon_get_first_range(TEGRA_SYSCON_PMC);
+ if (IS_ERR(priv->pmc_base))
+ return PTR_ERR(priv->pmc_base);
ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "nvidia,panel",
&priv->panel);
default y if AM33XX
help
Say Y here to enable the OMAP3+ watchdog driver.
-
+
+config TANGIER_WATCHDOG
+ bool "Intel Tangier watchdog"
+ depends on INTEL_MID
+ select HW_WATCHDOG
+ help
+ This enables support for watchdog controller available on
+ Intel Tangier SoC. If you're using a board with Intel Tangier
+ SoC, say Y here.
+
config ULP_WATCHDOG
bool "i.MX7ULP watchdog"
help
The watchdog timer is stopped when initialized.
It performs full SoC reset.
+config WDT_ORION
+ bool "Orion watchdog timer support"
+ depends on WDT
+ help
+ Select this to enable Orion watchdog timer, which can be found on some
+ Marvell Armada chips.
+
endmenu
obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o
+obj-$(CONFIG_TANGIER_WATCHDOG) += tangier_wdt.o
obj-$(CONFIG_ULP_WATCHDOG) += ulp_wdog.o
obj-$(CONFIG_WDT) += wdt-uclass.o
obj-$(CONFIG_WDT_SANDBOX) += sandbox_wdt.o
obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o
obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o
obj-$(CONFIG_BCM2835_WDT) += bcm2835_wdt.o
+obj-$(CONFIG_WDT_ORION) += orion_wdt.o
--- /dev/null
+/*
+ * drivers/watchdog/orion_wdt.c
+ *
+ * Watchdog driver for Orion/Kirkwood processors
+ *
+ * Authors: Tomas Hlavacek <tmshlvck@gmail.com>
+ * Sylver Bruneau <sylver.bruneau@googlemail.com>
+ * Marek Behun <marek.behun@nic.cz>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <wdt.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct orion_wdt_priv {
+ void __iomem *reg;
+ int wdt_counter_offset;
+ void __iomem *rstout;
+ void __iomem *rstout_mask;
+ u32 timeout;
+};
+
+#define RSTOUT_ENABLE_BIT BIT(8)
+#define RSTOUT_MASK_BIT BIT(10)
+#define WDT_ENABLE_BIT BIT(8)
+
+#define TIMER_CTRL 0x0000
+#define TIMER_A370_STATUS 0x04
+
+#define WDT_AXP_FIXED_ENABLE_BIT BIT(10)
+#define WDT_A370_EXPIRED BIT(31)
+
+static int orion_wdt_reset(struct udevice *dev)
+{
+ struct orion_wdt_priv *priv = dev_get_priv(dev);
+
+ /* Reload watchdog duration */
+ writel(priv->timeout, priv->reg + priv->wdt_counter_offset);
+
+ return 0;
+}
+
+static int orion_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
+{
+ struct orion_wdt_priv *priv = dev_get_priv(dev);
+ u32 reg;
+
+ priv->timeout = (u32) timeout;
+
+ /* Enable the fixed watchdog clock input */
+ reg = readl(priv->reg + TIMER_CTRL);
+ reg |= WDT_AXP_FIXED_ENABLE_BIT;
+ writel(reg, priv->reg + TIMER_CTRL);
+
+ /* Set watchdog duration */
+ writel(priv->timeout, priv->reg + priv->wdt_counter_offset);
+
+ /* Clear the watchdog expiration bit */
+ reg = readl(priv->reg + TIMER_A370_STATUS);
+ reg &= ~WDT_A370_EXPIRED;
+ writel(reg, priv->reg + TIMER_A370_STATUS);
+
+ /* Enable watchdog timer */
+ reg = readl(priv->reg + TIMER_CTRL);
+ reg |= WDT_ENABLE_BIT;
+ writel(reg, priv->reg + TIMER_CTRL);
+
+ /* Enable reset on watchdog */
+ reg = readl(priv->rstout);
+ reg |= RSTOUT_ENABLE_BIT;
+ writel(reg, priv->rstout);
+
+ reg = readl(priv->rstout_mask);
+ reg &= ~RSTOUT_MASK_BIT;
+ writel(reg, priv->rstout_mask);
+
+ return 0;
+}
+
+static int orion_wdt_stop(struct udevice *dev)
+{
+ struct orion_wdt_priv *priv = dev_get_priv(dev);
+ u32 reg;
+
+ /* Disable reset on watchdog */
+ reg = readl(priv->rstout_mask);
+ reg |= RSTOUT_MASK_BIT;
+ writel(reg, priv->rstout_mask);
+
+ reg = readl(priv->rstout);
+ reg &= ~RSTOUT_ENABLE_BIT;
+ writel(reg, priv->rstout);
+
+ /* Disable watchdog timer */
+ reg = readl(priv->reg + TIMER_CTRL);
+ reg &= ~WDT_ENABLE_BIT;
+ writel(reg, priv->reg + TIMER_CTRL);
+
+ return 0;
+}
+
+static inline bool save_reg_from_ofdata(struct udevice *dev, int index,
+ void __iomem **reg, int *offset)
+{
+ fdt_addr_t addr;
+ fdt_size_t off;
+
+ addr = fdtdec_get_addr_size_auto_noparent(
+ gd->fdt_blob, dev_of_offset(dev), "reg", index, &off, true);
+
+ if (addr == FDT_ADDR_T_NONE)
+ return false;
+
+ *reg = (void __iomem *) addr;
+ if (offset)
+ *offset = off;
+
+ return true;
+}
+
+static int orion_wdt_ofdata_to_platdata(struct udevice *dev)
+{
+ struct orion_wdt_priv *priv = dev_get_priv(dev);
+
+ if (!save_reg_from_ofdata(dev, 0, &priv->reg,
+ &priv->wdt_counter_offset))
+ goto err;
+
+ if (!save_reg_from_ofdata(dev, 1, &priv->rstout, NULL))
+ goto err;
+
+ if (!save_reg_from_ofdata(dev, 2, &priv->rstout_mask, NULL))
+ goto err;
+
+ return 0;
+err:
+ debug("%s: Could not determine Orion wdt IO addresses\n", __func__);
+ return -ENXIO;
+}
+
+static int orion_wdt_probe(struct udevice *dev)
+{
+ debug("%s: Probing wdt%u\n", __func__, dev->seq);
+ orion_wdt_stop(dev);
+
+ return 0;
+}
+
+static const struct wdt_ops orion_wdt_ops = {
+ .start = orion_wdt_start,
+ .reset = orion_wdt_reset,
+ .stop = orion_wdt_stop,
+};
+
+static const struct udevice_id orion_wdt_ids[] = {
+ { .compatible = "marvell,armada-380-wdt" },
+ {}
+};
+
+U_BOOT_DRIVER(orion_wdt) = {
+ .name = "orion_wdt",
+ .id = UCLASS_WDT,
+ .of_match = orion_wdt_ids,
+ .probe = orion_wdt_probe,
+ .priv_auto_alloc_size = sizeof(struct orion_wdt_priv),
+ .ofdata_to_platdata = orion_wdt_ofdata_to_platdata,
+ .ops = &orion_wdt_ops,
+};
--- /dev/null
+/*
+ * Copyright (c) 2017 Intel Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <watchdog.h>
+#include <asm/scu.h>
+
+/* Hardware timeout in seconds */
+#define WDT_PRETIMEOUT 15
+#define WDT_TIMEOUT_MIN (1 + WDT_PRETIMEOUT)
+#define WDT_TIMEOUT_MAX 170
+#define WDT_DEFAULT_TIMEOUT 90
+
+#ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
+#define WATCHDOG_HEARTBEAT 60000
+#else
+#define WATCHDOG_HEARTBEAT CONFIG_WATCHDOG_TIMEOUT_MSECS
+#endif
+
+enum {
+ SCU_WATCHDOG_START = 0,
+ SCU_WATCHDOG_STOP = 1,
+ SCU_WATCHDOG_KEEPALIVE = 2,
+ SCU_WATCHDOG_SET_ACTION_ON_TIMEOUT = 3,
+};
+
+void hw_watchdog_reset(void)
+{
+ static unsigned long last;
+ unsigned long now;
+
+ if (gd->timer)
+ now = timer_get_us();
+ else
+ now = rdtsc() / 1000;
+
+ /* Do not flood SCU */
+ if (last > now)
+ last = 0;
+
+ if (unlikely((now - last) > (WDT_PRETIMEOUT / 2) * 1000000)) {
+ last = now;
+ scu_ipc_simple_command(IPCMSG_WATCHDOG_TIMER, SCU_WATCHDOG_KEEPALIVE);
+ }
+}
+
+int hw_watchdog_disable(void)
+{
+ return scu_ipc_simple_command(IPCMSG_WATCHDOG_TIMER, SCU_WATCHDOG_STOP);
+}
+
+void hw_watchdog_init(void)
+{
+ u32 timeout = WATCHDOG_HEARTBEAT / 1000;
+ int in_size;
+ struct ipc_wd_start {
+ u32 pretimeout;
+ u32 timeout;
+ } ipc_wd_start = { timeout - WDT_PRETIMEOUT, timeout };
+
+ /*
+ * SCU expects the input size for watchdog IPC
+ * to be based on 4 bytes
+ */
+ in_size = DIV_ROUND_UP(sizeof(ipc_wd_start), 4);
+
+ scu_ipc_command(IPCMSG_WATCHDOG_TIMER, SCU_WATCHDOG_START,
+ (u32 *)&ipc_wd_start, in_size, NULL, 0);
+}
static int read_nand_cached(u32 off, u32 size, u_char *buf)
{
struct mtdids *id = current_part->dev->id;
+ struct mtd_info *mtd;
u32 bytes_read = 0;
size_t retlen;
int cpy_bytes;
+ mtd = get_nand_dev_by_index(id->num);
+ if (!mtd)
+ return -1;
+
while (bytes_read < size) {
if ((off + bytes_read < nand_cache_off) ||
(off + bytes_read >= nand_cache_off+NAND_CACHE_SIZE)) {
}
retlen = NAND_CACHE_SIZE;
- if (nand_read(nand_info[id->num], nand_cache_off,
- &retlen, nand_cache) != 0 ||
+ if (nand_read(mtd, nand_cache_off,
+ &retlen, nand_cache) != 0 ||
retlen != NAND_CACHE_SIZE) {
printf("read_nand_cached: error reading nand off %#x size %d bytes\n",
nand_cache_off, NAND_CACHE_SIZE);
u32 counterN = 0;
struct mtdids *id = part->dev->id;
- mtd = nand_info[id->num];
+ mtd = get_nand_dev_by_index(id->num);
+ if (!mtd) {
+ error("\nno NAND devices available\n");
+ return 0;
+ }
/* if we are building a list we need to refresh the cache. */
jffs_init_1pass_list(part);
char *mp = NULL;
struct nand_chip *chip;
+ mtd = get_nand_dev_by_index(flash_dev);
+ if (!mtd) {
+ error("\nno NAND devices available\n");
+ return;
+ }
+
dev = calloc(1, sizeof(*dev));
mp = strdup(_mp);
- mtd = nand_info[flash_dev];
-
if (!dev || !mp) {
/* Alloc error */
printf("Failed to allocate memory\n");
#endif
unsigned int timebase_h;
unsigned int timebase_l;
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
unsigned long malloc_base; /* base address of early malloc() */
unsigned long malloc_limit; /* limit address */
unsigned long malloc_ptr; /* current address */
--- /dev/null
+/*
+ * I2C Driver for Atmel ATSHA204 over I2C
+ *
+ * Copyright (C) 2014 Josh Datko, Cryptotronix, jbd@cryptotronix.com
+ * 2016 Tomas Hlavacek, CZ.NIC, tmshlvck@gmail.com
+ * 2017 Marek Behun, CZ.NIC, marek.behun@nic.cz
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef _ATSHA204_I2C_H_
+#define _ATSHA204_I2C_H_
+
+enum atsha204a_zone
+{
+ ATSHA204A_ZONE_CONFIG = 0,
+ ATSHA204A_ZONE_OTP = 1,
+ ATSHA204A_ZONE_DATA = 2,
+};
+
+enum atsha204a_status
+{
+ ATSHA204A_STATUS_SUCCESS = 0x00,
+ ATSHA204A_STATUS_MISCOMPARE = 0x01,
+ ATSHA204A_STATUS_PARSE_ERROR = 0x03,
+ ATSHA204A_STATUS_EXEC_ERROR = 0x0F,
+ ATSHA204A_STATUS_AFTER_WAKE = 0x11,
+ ATSHA204A_STATUS_CRC_ERROR = 0xFF,
+};
+
+enum atsha204a_func
+{
+ ATSHA204A_FUNC_RESET = 0x00,
+ ATSHA204A_FUNC_SLEEP = 0x01,
+ ATSHA204A_FUNC_IDLE = 0x02,
+ ATSHA204A_FUNC_COMMAND = 0x03,
+};
+
+enum atsha204a_cmd
+{
+ ATSHA204A_CMD_READ = 0x02,
+ ATSHA204A_CMD_RANDOM = 0x1B,
+};
+
+struct atsha204a_resp
+{
+ u8 length;
+ u8 code;
+ u8 data[82];
+} __attribute__ ((packed));
+
+struct atsha204a_req
+{
+ u8 function;
+ u8 length;
+ u8 command;
+ u8 param1;
+ u16 param2;
+ u8 data[78];
+} __attribute__ ((packed));
+
+int atsha204a_wakeup(struct udevice *);
+int atsha204a_idle(struct udevice *);
+int atsha204a_sleep(struct udevice *);
+int atsha204a_read(struct udevice *, enum atsha204a_zone, bool, u16, u8 *);
+int atsha204a_get_random(struct udevice *, u8 *, size_t);
+
+#endif /* _ATSHA204_I2C_H_ */
* @return 0 if OK, or a negative error code.
*/
int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk);
+
+/**
+ * clk_release_all() - Disable (turn off)/Free an array of previously
+ * requested clocks.
+ *
+ * For each clock contained in the clock array, this function will check if
+ * clock has been previously requested and then will disable and free it.
+ *
+ * @clk: A clock struct array that was previously successfully
+ * requested by clk_request/get_by_*().
+ * @count Number of clock contained in the array
+ * @return zero on success, or -ve error code.
+ */
+int clk_release_all(struct clk *clk, int count);
+
#else
static inline int clk_get_by_index(struct udevice *dev, int index,
struct clk *clk)
{
return -ENOSYS;
}
+
+static inline int clk_release_all(struct clk *clk, int count)
+{
+ return -ENOSYS;
+}
+
#endif
/**
*/
#define CONFIG_CMD_MFSL /* FSL support for Microblaze */
-#define CONFIG_CMD_MTDPARTS /* mtd parts support */
#define CONFIG_CMD_NAND /* NAND support */
#define CONFIG_CMD_ONENAND /* OneNAND support */
#define CONFIG_CMD_PCI /* pciinfo */
#define CONFIG_CMD_SAVES /* save S record dump */
#define CONFIG_CMD_SDRAM /* SDRAM DIMM SPD info printout */
#define CONFIG_CMD_TERMINAL /* built-in Serial Terminal */
-#define CONFIG_CMD_UBIFS /* UBIFS Support */
#define CONFIG_CMD_UNIVERSE /* Tundra Universe Support */
#define CONFIG_CMD_ZFS /* ZFS Support */
#ifndef __CONFIG_FSL_CHAIN_TRUST_H
#define __CONFIG_FSL_CHAIN_TRUST_H
-/* For secure boot, since ENVIRONMENT in flash/external memories is
- * not verified, undef CONFIG_ENV_xxx and set default env
- * (CONFIG_ENV_IS_NOWHERE)
- */
-#ifdef CONFIG_SECURE_BOOT
-
-#undef CONFIG_ENV_IS_IN_EEPROM
-#undef CONFIG_ENV_IS_IN_NAND
-#undef CONFIG_ENV_IS_IN_MMC
-#undef CONFIG_ENV_IS_IN_SPI_FLASH
-#undef CONFIG_ENV_IS_IN_FLASH
-
-#define CONFIG_ENV_IS_NOWHERE
-
-#endif
-
#ifdef CONFIG_CHAIN_OF_TRUST
#ifndef CONFIG_EXTRA_ENV
* of flash. NOTE: the monitor length must be multiple of sector size
* (which is common practice).
*/
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SIZE 0x10000 /* 64k, 1 sector */
#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
* of flash. NOTE: the monitor length must be multiple of sector size
* (which is common practice).
*/
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SIZE 0x20000 /* 128k, 1 sector */
#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
#define CONFIG_ENV_OVERWRITE
#ifndef CONFIG_MTD_NOR_FLASH
-#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
-#define CONFIG_ENV_IS_NOWHERE
-#endif
#else
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#if defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 10000000
#define CONFIG_ENV_SECT_SIZE 0x10000
#elif defined(CONFIG_SDCARD)
#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_OFFSET (512 * 1097)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-#define CONFIG_ENV_IS_IN_REMOTE
#define CONFIG_ENV_ADDR 0xffe20000
#define CONFIG_ENV_SIZE 0x2000
#elif defined(CONFIG_ENV_IS_NOWHERE)
#define CONFIG_ENV_SIZE 0x2000
#else
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
* Environment
*/
#if defined(CONFIG_RAMBOOT_SPIFLASH)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 10000000
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_SIZE 0x2000
#elif defined(CONFIG_NAND)
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
#elif defined(CONFIG_SYS_RAMBOOT)
-#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#endif
*/
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
-#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT "nand0=ff800000.flash,"
#define MTDPARTS_DEFAULT "mtdparts=ff800000.flash:1m(uboot)," \
"8m(kernel),512k(dtb),-(fs)"
* Environment
*/
#if defined(CONFIG_RAMBOOT_SDCARD)
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_FSL_FIXED_MMC_LOCATION
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
#elif defined(CONFIG_RAMBOOT_SPIFLASH)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 10000000
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_SIZE 0x2000
#elif defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
#elif defined(CONFIG_SYS_RAMBOOT)
-#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#else
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000
#ifdef CONFIG_MTD_NOR_FLASH
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT "nor0=88000000.nor,nand0=ff800000.flash,"
#define MTDPARTS_DEFAULT "mtdparts=88000000.nor:256k(dtb),7m(kernel)," \
*/
#if defined(CONFIG_SYS_RAMBOOT)
#if defined(CONFIG_RAMBOOT_SPIFLASH)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 10000000
#define CONFIG_ENV_SIZE 0x2000
#endif
#elif defined(CONFIG_NAND)
-#define CONFIG_ENV_IS_IN_NAND
#ifdef CONFIG_TPL_BUILD
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
#endif
#define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE
#else
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000
#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 5000
-/* Command line configuration */
-#define CONFIG_CMD_REGINFO
-
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
# define CONFIG_MII 1
#define CONFIG_ENV_OFFSET 0x2000
#define CONFIG_ENV_SIZE 0x1000
#define CONFIG_ENV_SECT_SIZE 0x2000
-#define CONFIG_ENV_IS_IN_FLASH 1
#define LDS_BOARD_TEXT \
. = DEFINED(env_offset) ? env_offset : .; \
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-/* Command line configuration */
-#define CONFIG_CMD_REGINFO
-
#define CONFIG_HOSTNAME M52277EVB
#define CONFIG_SYS_UBOOT_END 0x3FFFF
#define CONFIG_SYS_LOAD_ADDR2 0x40010007
* crc error warning if there is no correct environment on the flash.
*/
#ifdef CONFIG_CF_SBF
-# define CONFIG_ENV_IS_IN_SPI_FLASH
# define CONFIG_ENV_SPI_CS 2
-#else
-# define CONFIG_ENV_IS_IN_FLASH 1
#endif
#define CONFIG_ENV_OVERWRITE 1
/* Command line configuration */
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_REGINFO
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/
-#define CONFIG_ENV_IS_IN_FLASH 1
#define LDS_BOARD_TEXT \
. = DEFINED(env_offset) ? env_offset : .; \
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_ENV_IS_IN_FLASH 1
-
#define LDS_BOARD_TEXT \
. = DEFINED(env_offset) ? env_offset : .; \
common/env_embedded.o (.text);
#ifdef CONFIG_MONITOR_IS_IN_RAM
# define CONFIG_ENV_OFFSET 0x4000
# define CONFIG_ENV_SECT_SIZE 0x1000
-# define CONFIG_ENV_IS_IN_FLASH 1
#else
# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000)
# define CONFIG_ENV_SECT_SIZE 0x1000
-# define CONFIG_ENV_IS_IN_FLASH 1
#endif
#define LDS_BOARD_TEXT \
#ifndef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_ENV_OFFSET 0x4000
#define CONFIG_ENV_SECT_SIZE 0x2000
-#define CONFIG_ENV_IS_IN_FLASH 1
#else
#define CONFIG_ENV_ADDR 0xffe04000
#define CONFIG_ENV_SECT_SIZE 0x2000
-#define CONFIG_ENV_IS_IN_FLASH 1
#endif
#define LDS_BOARD_TEXT \
#ifndef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_ENV_OFFSET 0x4000
#define CONFIG_ENV_SECT_SIZE 0x2000
-#define CONFIG_ENV_IS_IN_FLASH 1
#else
#define CONFIG_ENV_ADDR 0xffe04000
#define CONFIG_ENV_SECT_SIZE 0x2000
-#define CONFIG_ENV_IS_IN_FLASH 1
#endif
#define LDS_BOARD_TEXT \
#ifndef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_ENV_OFFSET 0x4000
#define CONFIG_ENV_SECT_SIZE 0x2000
-#define CONFIG_ENV_IS_IN_FLASH 1
#else
#define CONFIG_ENV_ADDR 0xffe04000
#define CONFIG_ENV_SECT_SIZE 0x2000
-#define CONFIG_ENV_IS_IN_FLASH 1
#endif
#define LDS_BOARD_TEXT \
*/
#define CONFIG_ENV_ADDR 0xffe04000
#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_IS_IN_FLASH 1
#define LDS_BOARD_TEXT \
. = DEFINED(env_offset) ? env_offset : .; \
#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 5000
-/* Command line configuration */
-#define CONFIG_CMD_REGINFO
-
#define CONFIG_SYS_UNIFY_CACHE
#define CONFIG_MCFFEC
#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_BASE + 0x40000)
#define CONFIG_ENV_SIZE 0x1000
#define CONFIG_ENV_SECT_SIZE 0x8000
-#define CONFIG_ENV_IS_IN_FLASH 1
#define LDS_BOARD_TEXT \
. = DEFINED(env_offset) ? env_offset : .; \
#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
-/* Command line configuration */
-#define CONFIG_CMD_REGINFO
-
#ifdef CONFIG_NANDFLASH_SIZE
# define CONFIG_CMD_NAND
#endif
*/
#define CONFIG_ENV_OFFSET 0x4000
#define CONFIG_ENV_SECT_SIZE 0x2000
-#define CONFIG_ENV_IS_IN_FLASH 1
#define LDS_BOARD_TEXT \
. = DEFINED(env_offset) ? env_offset : .; \
#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */
-/* Command line configuration */
-#define CONFIG_CMD_REGINFO
-
#ifdef CONFIG_NANDFLASH_SIZE
# define CONFIG_CMD_NAND
#endif
*/
#define CONFIG_ENV_OFFSET 0x4000
#define CONFIG_ENV_SECT_SIZE 0x2000
-#define CONFIG_ENV_IS_IN_FLASH 1
#define LDS_BOARD_TEXT \
. = DEFINED(env_offset) ? env_offset : .; \
/* Command line configuration */
#undef CONFIG_CMD_NAND
-#define CONFIG_CMD_REGINFO
/*
* NAND FLASH
* Environment is embedded in u-boot in the second sector of the flash
*/
#if !defined(CONFIG_SERIAL_BOOT) /*MRAM boot*/
-#define CONFIG_ENV_IS_IN_MRAM 1
#define CONFIG_ENV_ADDR (0x40000 - 0x1000) /*MRAM size 40000*/
#define CONFIG_ENV_SIZE 0x1000
#endif
#if defined(CONFIG_CF_SBF)
-#define CONFIG_ENV_IS_IN_SPI_FLASH 1
#define CONFIG_ENV_SPI_CS 1
#define CONFIG_ENV_OFFSET 0x40000
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x10000
#endif
#if defined(CONFIG_SYS_NAND_BOOT)
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_OFFSET 0x80000
#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_ENV_SECT_SIZE 0x20000
#ifdef CONFIG_CMD_JFFS2
#define CONFIG_JFFS2_DEV "nand0"
#define CONFIG_JFFS2_PART_OFFSET (0x800000)
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE
#define MTDIDS_DEFAULT "nand0=m54418twr.nand"
#endif
#ifdef CONFIG_CMD_UBI
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE /* needed for mtdparts command */
#define CONFIG_MTD_PARTITIONS /* mtdparts and UBI support */
-#define CONFIG_RBTREE
#define MTDIDS_DEFAULT "nand0=NAND"
#define MTDPARTS_DEFAULT "mtdparts=NAND:1m(u-boot)," \
"-(ubi)"
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-/* Command line configuration */
-#define CONFIG_CMD_REGINFO
-
/* Network configuration */
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
* crc error warning if there is no correct environment on the flash.
*/
#if defined(CONFIG_SYS_STMICRO_BOOT)
-# define CONFIG_ENV_IS_IN_SPI_FLASH 1
# define CONFIG_ENV_SPI_CS 1
# define CONFIG_ENV_OFFSET 0x20000
# define CONFIG_ENV_SIZE 0x2000
# define CONFIG_ENV_SECT_SIZE 0x10000
#else
-# define CONFIG_ENV_IS_IN_FLASH 1
# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
# define CONFIG_ENV_SIZE 0x2000
# define CONFIG_ENV_SECT_SIZE 0x20000
/* Command line configuration */
#undef CONFIG_CMD_PCI
-#define CONFIG_CMD_REGINFO
/* Network configuration */
#define CONFIG_MCFFEC
* crc error warning if there is no correct environment on the flash.
*/
#ifdef CONFIG_CF_SBF
-# define CONFIG_ENV_IS_IN_SPI_FLASH
# define CONFIG_ENV_SPI_CS 1
-#else
-# define CONFIG_ENV_IS_IN_FLASH 1
#endif
#undef CONFIG_ENV_OVERWRITE
/* Command line configuration */
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_REGINFO
#define CONFIG_SLTTMR
*/
#define CONFIG_ENV_OFFSET 0x40000
#define CONFIG_ENV_SECT_SIZE 0x10000
-#define CONFIG_ENV_IS_IN_FLASH 1
/*-----------------------------------------------------------------------
* Cache Configuration
/* Command line configuration */
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_REGINFO
#define CONFIG_SLTTMR
*/
#define CONFIG_ENV_OFFSET 0x40000
#define CONFIG_ENV_SECT_SIZE 0x10000
-#define CONFIG_ENV_IS_IN_FLASH 1
/*-----------------------------------------------------------------------
* Cache Configuration
/* Environment Configuration */
/* environment is in FLASH */
-#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
/*
* Environment
*/
-#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITION
-#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT "nand0=e2800000.flash"
#define MTDPARTS_DEFAULT \
"mtdparts=e2800000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)"
* Environment
*/
#if defined(CONFIG_NAND)
- #define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_OFFSET (512 * 1024)
#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_OFFSET_REDUND \
(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
#elif !defined(CONFIG_SYS_RAMBOOT)
- #define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR \
(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
/* Address and size of Redundant Environment Sector */
#else
- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#endif
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITION
-#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT "nand0=e0600000.flash"
#define MTDPARTS_DEFAULT \
"mtdparts=e0600000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)"
* Environment
*/
#if !defined(CONFIG_SYS_RAMBOOT)
- #define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR \
(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
#define CONFIG_ENV_SIZE 0x2000
#else
- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#endif
* Environment
*/
#ifndef CONFIG_SYS_RAMBOOT
- #define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR \
(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x2000
#else
- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#endif
* Environment
*/
#ifndef CONFIG_SYS_RAMBOOT
- #define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR \
(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x2000
#else
- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#endif
* Environment
*/
#ifndef CONFIG_SYS_RAMBOOT
- #define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR \
(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#else
- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#endif
#define CONFIG_ENV_OVERWRITE
#ifndef CONFIG_SYS_RAMBOOT
- #define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR \
(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */
#define CONFIG_ENV_SIZE 0x2000
#else
#undef CONFIG_FLASH_CFI_DRIVER
- #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#endif
* Environment
*/
#ifndef CONFIG_SYS_RAMBOOT
- #define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR \
(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
#define CONFIG_ENV_SIZE 0x2000
#else
- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#endif
* Environment
*/
#ifndef CONFIG_SYS_RAMBOOT
- #define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR \
(CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */
#define CONFIG_ENV_SIZE 0x4000
#else
- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-0x1000)
#define CONFIG_ENV_SIZE 0x2000
#endif
#if defined(CONFIG_SYS_RAMBOOT)
#if defined(CONFIG_RAMBOOT_SPIFLASH)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 10000000
#define CONFIG_ENV_OFFSET 0xF0000
#define CONFIG_ENV_SECT_SIZE 0x10000
#elif defined(CONFIG_RAMBOOT_SDCARD)
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_FSL_FIXED_MMC_LOCATION
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_SYS_MMC_ENV_DEV 0
#else
- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#endif
#else
- #define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
* Environment
*/
#ifndef CONFIG_SYS_RAMBOOT
- #define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
#define CONFIG_ENV_SIZE 0x2000
#else
- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#endif
/*
* Environment
*/
-#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
#define CONFIG_ENV_SIZE 0x2000
/*
* Environment
*/
-#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */
#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
#define CONFIG_ENV_ADDR 0xfff80000
/*
* Environment
*/
-#define CONFIG_ENV_IS_IN_FLASH 1
#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
#define CONFIG_ENV_ADDR 0xfff80000
#else
/*
* Environment
*/
-#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
#define CONFIG_ENV_SIZE 0x2000
* Environment
*/
#ifndef CONFIG_SYS_RAMBOOT
- #define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
#define CONFIG_ENV_SIZE 0x2000
#else
- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#endif
/*
* Environment
*/
-#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
*/
#if defined(CONFIG_SYS_RAMBOOT)
#else
-#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
#define CONFIG_ENV_SIZE 0x2000
#if defined(CONFIG_SYS_RAMBOOT)
#else
- #define CONFIG_ENV_IS_IN_FLASH 1
#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
#define CONFIG_ENV_ADDR 0xfff80000
#else
#define CONFIG_USB_EHCI_PCI
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_PCI_EHCI_DEVICE 0
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
#endif
#undef CONFIG_WATCHDOG /* watchdog disabled */
* Environment
*/
#ifndef CONFIG_SYS_RAMBOOT
-#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 126k (one sector) for env */
#define CONFIG_ENV_SIZE 0x2000
#else
-#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#endif
* Environment
*/
#ifndef CONFIG_SYS_RAMBOOT
- #define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR \
(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
#else
- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#endif
#define CONFIG_ENV_SIZE 0x2000
#undef CONFIG_SYS_DIRECT_FLASH_TFTP
/* ENV setting */
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITION
-#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT "nand0=ff800000.flash"
#define MTDPARTS_DEFAULT \
"mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
* Environment
*/
#if defined(CONFIG_SDCARD)
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_FSL_FIXED_MMC_LOCATION
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
#elif defined(CONFIG_SPIFLASH)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 10000000
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_SIZE 0x2000
#elif defined(CONFIG_NAND)
-#define CONFIG_ENV_IS_IN_NAND
#ifdef CONFIG_TPL_BUILD
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
#endif
#define CONFIG_ENV_OFFSET (1024 * 1024)
#elif defined(CONFIG_SYS_RAMBOOT)
-#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#else
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
*/
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_FLASH_CFI_MTD
#ifdef CONFIG_PHYS_64BIT
#define MTDIDS_DEFAULT "nor0=fe8000000.nor"
* Environment
*/
#ifdef CONFIG_SPIFLASH
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 10000000
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
#define CONFIG_ENV_SECT_SIZE 0x10000
#elif defined(CONFIG_SDCARD)
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_FSL_FIXED_MMC_LOCATION
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_SYS_MMC_ENV_DEV 0
#else
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#endif
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET (1024 * 1024)
#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
#elif defined(CONFIG_SYS_RAMBOOT)
-#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#else
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
*/
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#define CONFIG_ENV_OVERWRITE
#ifndef CONFIG_MTD_NOR_FLASH
-#if !defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-#define CONFIG_ENV_IS_NOWHERE
-#endif
#else
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#if defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_EXTRA_ENV_RELOC
- #define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 10000000
#define CONFIG_ENV_SECT_SIZE 0x10000
#elif defined(CONFIG_SDCARD)
#define CONFIG_SYS_EXTRA_ENV_RELOC
- #define CONFIG_ENV_IS_IN_MMC
#define CONFIG_FSL_FIXED_MMC_LOCATION
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_OFFSET (512 * 1658)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-#define CONFIG_ENV_IS_IN_REMOTE
#define CONFIG_ENV_ADDR 0xffe20000
#define CONFIG_ENV_SIZE 0x2000
#elif defined(CONFIG_ENV_IS_NOWHERE)
#define CONFIG_ENV_SIZE 0x2000
#else
- #define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \
- CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x2000
#if defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 10000000
#define CONFIG_ENV_SECT_SIZE 0x10000
#elif defined(CONFIG_SDCARD)
#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_OFFSET (512 * 0x800)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-#define CONFIG_ENV_IS_IN_REMOTE
#define CONFIG_ENV_ADDR 0xffe20000
#define CONFIG_ENV_SIZE 0x2000
#elif defined(CONFIG_ENV_IS_NOWHERE)
#define CONFIG_ENV_SIZE 0x2000
#else
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#ifdef CONFIG_MTD_NOR_FLASH
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
"spi0=spife110000.0"
#if defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 10000000
#endif
#elif defined(CONFIG_SDCARD)
#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_OFFSET (512 * 0x800)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE 0x2000
#if defined(CONFIG_TARGET_T1024RDB)
#define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
#endif
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-#define CONFIG_ENV_IS_IN_REMOTE
#define CONFIG_ENV_ADDR 0xffe20000
#define CONFIG_ENV_SIZE 0x2000
#elif defined(CONFIG_ENV_IS_NOWHERE)
#define CONFIG_ENV_SIZE 0x2000
#else
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#ifdef CONFIG_MTD_NOR_FLASH
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
"spi0=spife110000.1"
#define CONFIG_ENV_OVERWRITE
#ifndef CONFIG_MTD_NOR_FLASH
-#define CONFIG_ENV_IS_NOWHERE
#else
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_MTD_NOR_FLASH
#if defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 10000000
#define CONFIG_ENV_SECT_SIZE 0x10000
#elif defined(CONFIG_SDCARD)
#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_OFFSET (512 * 1658)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
#else
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#ifdef CONFIG_MTD_NOR_FLASH
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
"spi0=spife110000.0"
#if defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
#define CONFIG_ENV_SECT_SIZE 0x10000
#elif defined(CONFIG_SDCARD)
#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_OFFSET (512 * 0x800)
#define CONFIG_BOOTSCRIPT_COPY_RAM
#endif
#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
#else
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#ifdef CONFIG_MTD_NOR_FLASH
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
"spi0=spife110000.0"
#if defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 10000000
#define CONFIG_ENV_SECT_SIZE 0x10000
#elif defined(CONFIG_SDCARD)
#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_OFFSET (512 * 0x800)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-#define CONFIG_ENV_IS_IN_REMOTE
#define CONFIG_ENV_ADDR 0xffe20000
#define CONFIG_ENV_SIZE 0x2000
#elif defined(CONFIG_ENV_IS_NOWHERE)
#define CONFIG_ENV_SIZE 0x2000
#else
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#ifdef CONFIG_MTD_NOR_FLASH
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
"spi0=spife110000.0"
#if defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 10000000
#define CONFIG_ENV_SECT_SIZE 0x10000
#elif defined(CONFIG_SDCARD)
#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_OFFSET (512 * 0x800)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-#define CONFIG_ENV_IS_IN_REMOTE
#define CONFIG_ENV_ADDR 0xffe20000
#define CONFIG_ENV_SIZE 0x2000
#elif defined(CONFIG_ENV_IS_NOWHERE)
#define CONFIG_ENV_SIZE 0x2000
#else
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#ifdef CONFIG_MTD_NOR_FLASH
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
"spi0=spife110000.1"
#include "t4qds.h"
#ifndef CONFIG_MTD_NOR_FLASH
-#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
-#define CONFIG_ENV_IS_NOWHERE
-#endif
#else
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#if defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 10000000
#define CONFIG_ENV_SECT_SIZE 0x10000
#elif defined(CONFIG_SDCARD)
#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_OFFSET (512 * 0x800)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-#define CONFIG_ENV_IS_IN_REMOTE
#define CONFIG_ENV_ADDR 0xffe20000
#define CONFIG_ENV_SIZE 0x2000
#elif defined(CONFIG_ENV_IS_NOWHERE)
#define CONFIG_ENV_SIZE 0x2000
#else
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
"bootm 0x01000000 - 0x00f00000"
#ifndef CONFIG_MTD_NOR_FLASH
-#ifndef CONFIG_RAMBOOT_PBL
-#define CONFIG_ENV_IS_NOWHERE
-#endif
#else
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#if defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 10000000
#define CONFIG_ENV_SECT_SIZE 0x10000
#elif defined(CONFIG_SDCARD)
#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_OFFSET (512 * 0x800)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_ENV_IS_NOWHERE)
#define CONFIG_ENV_SIZE 0x2000
#else
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
/*
* Environment
*/
-#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR \
(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */
/*
* Command line configuration.
*/
-#define CONFIG_CMD_REGINFO
-
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#endif
* JFFS2 partitions
*/
/* mtdparts command line support */
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT "nor0=TQM834x-0"
*/
#ifdef CONFIG_ENV_FIT_UCBOOT
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000)
#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#ifdef CONFIG_RAMBOOT_SPIFLASH
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE 0x3000 /* 12KB */
#define CONFIG_ENV_OFFSET 0x2000 /* 8KB */
#define CONFIG_ENV_SECT_SIZE 0x1000
#endif
#elif defined(CONFIG_RAMBOOT_SDCARD)
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_FSL_FIXED_MMC_LOCATION
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_SYS_MMC_ENV_DEV 0
#elif defined(CONFIG_SYS_RAMBOOT)
-#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#else
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_BASE (CONFIG_SYS_FLASH_BASE)
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
#define CONFIG_SYS_MAX_FLASH_SECT 512
/* environments */
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000)
#define CONFIG_ENV_SIZE 8192
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_MAX_FLASH_SECT 512
/* environments */
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000)
#define CONFIG_ENV_SIZE 8192
#define CONFIG_ENV_OVERWRITE
#define __ADVANTECH_DMSBA16_CONFIG_H
#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/gpio.h>
+#include <asm/mach-imx/gpio.h>
#define CONFIG_BOARD_NAME "Advantech DMS-BA16"
/* FLASH and environment organization */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE (8 * 1024)
#define CONFIG_ENV_OFFSET (768 * 1024)
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
#ifndef CONFIG_SPL_BUILD
# define CONFIG_TIMESTAMP
-# define CONFIG_LZO
#endif
#define CONFIG_SYS_BOOTM_LEN (16 << 20)
#ifndef CONFIG_SPL_USBETH_SUPPORT
/* Fastboot */
-#define CONFIG_USB_FUNCTION_FASTBOOT
-#define CONFIG_CMD_FASTBOOT
#define CONFIG_ANDROID_BOOT_IMAGE
-#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
-#define CONFIG_FASTBOOT_BUF_SIZE 0x07000000
#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
#endif
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)
/* Remove other SPL modes. */
-#define CONFIG_ENV_IS_NOWHERE
-#undef CONFIG_ENV_IS_IN_NAND
/* disable host part of MUSB in SPL */
/* disable EFI partitions and partition UUID support */
#endif
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
#define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */
"128k(u-boot-env2),3464k(kernel)," \
"-(rootfs)"
#elif defined(CONFIG_EMMC_BOOT)
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_ENV_OFFSET 0x0
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_SYS_MMC_MAX_DEVICE 2
#elif defined(CONFIG_NOR_BOOT)
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_ENV_OFFSET (512 << 10) /* 512 KiB */
#define CONFIG_ENV_OFFSET_REDUND (768 << 10) /* 768 KiB */
#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#elif !defined(CONFIG_ENV_IS_NOWHERE)
/* Not NAND, SPI, NOR or eMMC env, so put ENV in a file on FAT */
-#define CONFIG_ENV_IS_IN_FAT
#define FAT_ENV_INTERFACE "mmc"
#define FAT_ENV_DEVICE_AND_PART "0:1"
#define FAT_ENV_FILE "uboot.env"
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
-#define CONFIG_RBTREE
-#define CONFIG_LZO
#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(SPL),-(UBI)"
#define CONFIG_SPL_UBI_INFO_ADDR 0x88080000
/* environment organization */
-#define CONFIG_ENV_IS_IN_UBI 1
#define CONFIG_ENV_UBI_PART "UBI"
#define CONFIG_ENV_UBI_VOLUME "config"
#define CONFIG_ENV_UBI_VOLUME_REDUND "config_r"
#ifndef CONFIG_SPL_BUILD
# define CONFIG_TIMESTAMP
-# define CONFIG_LZO
#endif
#define CONFIG_SYS_BOOTM_LEN (16 << 20)
#define V_OSCK 24000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
-#define CONFIG_ENV_IS_IN_MMC 1
-
/*
* in case of SD Card or Network boot we want to have a possibility to
* debrick the shc, therefore do not read environment from eMMC
#define CONFIG_SYS_I2C_SLAVE 1
#define CONFIG_SHOW_BOOT_PROGRESS
-
-#if defined CONFIG_SHC_NETBOOT
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_ENV_IS_NOWHERE
-#undef CONFIG_ENV_IS_IN_MMC
-#endif
-#endif
#endif /* ! __CONFIG_AM335X_SHC_H */
#ifndef CONFIG_SPL_BUILD
# define CONFIG_TIMESTAMP
-# define CONFIG_LZO
#endif
#define CONFIG_SYS_BOOTM_LEN (16 << 20)
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)
/* Remove other SPL modes. */
-#define CONFIG_ENV_IS_NOWHERE
-#undef CONFIG_ENV_IS_IN_NAND
/* disable host part of MUSB in SPL */
#undef CONFIG_MUSB_HOST
/* disable EFI partitions and partition UUID support */
#endif
#if defined(CONFIG_EMMC_BOOT)
-#undef CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_ENV_OFFSET 0x0
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_NAND_OMAP_GPMC
-#define CONFIG_ENV_IS_IN_NAND 1
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB sector */
/* commands to include */
#define CONFIG_CMD_NAND
-#define CONFIG_CMD_MTDPARTS
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_NAND_OMAP_GPMC_PREFETCH
#define CONFIG_BCH
-#define CONFIG_CMD_UBIFS /* Read-only UBI volume operations */
-#define CONFIG_RBTREE /* required by CONFIG_CMD_UBI */
-#define CONFIG_LZO /* required by CONFIG_CMD_UBIFS */
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
/* to access nand */
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
-#define CONFIG_ENV_IS_IN_NAND
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
-#define CONFIG_ENV_IS_IN_FAT
#define FAT_ENV_INTERFACE "mmc"
#define FAT_ENV_DEVICE_AND_PART "0:1"
#define FAT_ENV_FILE "uboot.env"
#if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD)
#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1
#define CONFIG_USB_XHCI_OMAP
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#define CONFIG_OMAP_USB_PHY
#define CONFIG_AM437X_USB2PHY2_HOST
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE CONFIG_ISW_ENTRY_ADDR
#endif
-#undef CONFIG_ENV_IS_IN_FAT
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64 KB sectors */
#define CONFIG_PHYLIB
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ETH_SUPPORT)
-#undef CONFIG_ENV_IS_IN_FAT
-#define CONFIG_ENV_IS_NOWHERE
-#endif
-
#define CONFIG_SYS_RX_ETH_BUFFER 64
/* NAND support */
#define CONFIG_NR_DRAM_BANKS 2
/* MMC ENV related defines */
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1 /* eMMC */
#define CONFIG_SYS_MMC_ENV_PART 0
#define CONFIG_ENV_SIZE SZ_128K
/* USB xHCI HOST */
#define CONFIG_USB_XHCI_OMAP
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#define CONFIG_OMAP_USB_PHY
#define CONFIG_OMAP_USB3PHY1_HOST
#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
-#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SIZE 0x1000
"64k(NVRAM),64k(ART)"
#define CONFIG_ENV_SPI_MAX_HZ 25000000
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET 0x40000
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_SIZE 0x10000
-/*
- * Command
- */
-#define CONFIG_CMD_MTDPARTS
-
/* Miscellaneous configurable options */
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_MAXARGS 16
"64k(ART)"
#define CONFIG_ENV_SPI_MAX_HZ 25000000
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET 0x40000
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_SIZE 0x10000
-/*
- * Command
- */
-#define CONFIG_CMD_MTDPARTS
-
/* Miscellaneous configurable options */
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_MAXARGS 16
#undef CONFIG_SYS_DIRECT_FLASH_TFTP
/* ENV setting */
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* ENV setting */
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
/* Environment in eMMC, before config block at the end of 1st "boot sector" */
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \
CONFIG_TDX_CFG_BLOCK_OFFSET)
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_GENERIC_BOARD
#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/gpio.h>
+#include <asm/mach-imx/gpio.h>
#ifdef CONFIG_SPL
#include "imx6_spl.h"
#define CONFIG_ENV_SIZE (8 * 1024)
-#define CONFIG_ENV_IS_IN_MMC
-
#if defined(CONFIG_ENV_IS_IN_MMC)
/* Environment in eMMC, before config block at the end of 1st "boot sector" */
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \
#define CONFIG_SYS_I2C_TEGRA
/* Environment in eMMC, before config block at the end of 1st "boot sector" */
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \
CONFIG_TDX_CFG_BLOCK_OFFSET)
#define CONFIG_SYS_MMC_ENV_DEV 0
/*
* U-Boot Commands
*/
-#define CONFIG_CMD_MTDPARTS /* MTD partition support */
#define CONFIG_CMD_NAND /* NAND support */
#define CONFIG_CMD_NAND_LOCK_UNLOCK
#define CONFIG_CMD_NAND_TRIMFFS
-#define CONFIG_CMD_UBIFS
/*
* Memory configurations
*/
#define ACFG_MONITOR_OFFSET 0x00000000
#define CONFIG_SYS_MONITOR_LEN 0x00100000 /* 1MiB */
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OVERWRITE
#define CONFIG_ENV_OFFSET 0x00100000 /* NAND offset */
#define CONFIG_ENV_SIZE 0x00020000 /* 128kB */
#define CONFIG_MTD_PARTITIONS
#define CONFIG_SUPPORT_VFAT
-/*
- * UBIFS
- */
-#define CONFIG_RBTREE
-#define CONFIG_LZO
-
/*
* Ethernet (on SOC imx FEC)
*/
/* Environment */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_ENV_IS_IN_NAND
/* Environment is in MMC */
#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC)
/* UBI and NAND partitioning */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_CMD_UBIFS
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_RBTREE
-#define CONFIG_LZO
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define MTDIDS_DEFAULT "nand0=gpmi-nand"
/* Environment organization */
#define CONFIG_ENV_SIZE (12 * 1024)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
#define CONFIG_MXC_USB_FLAGS 0
/* UBI support */
-#define CONFIG_LZO
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
-#define CONFIG_RBTREE
-#define CONFIG_CMD_UBIFS
#define CONFIG_HW_WATCHDOG
#define CONFIG_IMX_WATCHDOG
#define CONFIG_SYS_FLASH_UNLOCK_TOUT 3000
/* ENV setting */
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
/* Miscellaneous configurable options */
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
#define CONFIG_IRAM_STACK 0x02050000
/*
* Environment variables configurations
*/
-#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
#define CONFIG_ENV_SIZE 0x20000 /* 64k */
#endif /* __CONFIG_ASPENITE_H */
#define ENABLE_JFFS 1
#endif
-/* Define which commands should be available at u-boot command prompt */
-
-#define CONFIG_CMD_REGINFO
#define CONFIG_CMDLINE_EDITING
#define CONFIG_MCFRTC
#ifndef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_ENV_OFFSET 0x1FF8000
#define CONFIG_ENV_SECT_SIZE 0x8000
-#define CONFIG_ENV_IS_IN_FLASH 1
#else
/*
* environment in RAM - This is used to use a single PC-based application
*/
#define CONFIG_ENV_ADDR 0x40060000
#define CONFIG_ENV_SECT_SIZE 0x8000
-#define CONFIG_ENV_IS_IN_FLASH 1
#endif
/* here we put our FPGA configuration... */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_FPGA_COUNT 1
-#define CONFIG_FPGA
#define CONFIG_FPGA_XILINX
#define CONFIG_FPGA_SPARTAN3
-#define CONFIG_FPGA_ALTERA
#define CONFIG_FPGA_CYCLON2
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_SYS_FPGA_WAIT 1000
#define CONFIG_SYS_MMC_ENV_DEV 0
#else
/* u-boot env in sd/mmc card */
-#define CONFIG_ENV_IS_IN_FAT
#define FAT_ENV_INTERFACE "mmc"
#define FAT_ENV_DEVICE_AND_PART "0"
#define FAT_ENV_FILE "uboot.env"
#ifdef CONFIG_SYS_USE_NANDFLASH
/* u-boot env in nand flash */
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0xc0000
#define CONFIG_ENV_OFFSET_REDUND 0x100000
#define CONFIG_ENV_SIZE 0x20000
"bootz 0x22000000 - 0x21000000"
#elif CONFIG_SYS_USE_SERIALFLASH
/* u-boot env in serial flash, by default is bus 0 and cs 0 */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET 0x6000
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x1000
/*
* Environment Settings
*/
-#define CONFIG_ENV_IS_IN_FLASH
/*
* after u-boot.bin
#ifdef CONFIG_SYS_USE_DATAFLASH_CS0
/* bootstrap + u-boot + env + linux in dataflash on CS0 */
-#define CONFIG_ENV_IS_IN_DATAFLASH 1
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
#define CONFIG_ENV_OFFSET 0x4200
#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
#elif CONFIG_SYS_USE_DATAFLASH_CS1
/* bootstrap + u-boot + env + linux in dataflash on CS1 */
-#define CONFIG_ENV_IS_IN_DATAFLASH 1
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + 0x8400)
#define CONFIG_ENV_OFFSET 0x4200
#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + CONFIG_ENV_OFFSET)
#elif defined(CONFIG_SYS_USE_NANDFLASH)
/* bootstrap + u-boot + env + linux in nandflash */
-#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_OFFSET 0x120000
#define CONFIG_ENV_OFFSET_REDUND 0x100000
#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
#else /* CONFIG_SYS_USE_MMC */
/* bootstrap + u-boot + env + linux in mmc */
-#define CONFIG_ENV_IS_IN_MMC
/* For FAT system, most cases it should be in the reserved sector */
#define CONFIG_ENV_OFFSET 0x2000
#define CONFIG_ENV_SIZE 0x1000
#ifdef CONFIG_SYS_USE_DATAFLASH_CS0
/* bootstrap + u-boot + env + linux in dataflash on CS0 */
-#define CONFIG_ENV_IS_IN_DATAFLASH
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
#define CONFIG_ENV_OFFSET 0x4200
#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
#elif CONFIG_SYS_USE_DATAFLASH_CS3
/* bootstrap + u-boot + env + linux in dataflash on CS3 */
-#define CONFIG_ENV_IS_IN_DATAFLASH
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 + 0x8400)
#define CONFIG_ENV_OFFSET 0x4200
#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 + CONFIG_ENV_OFFSET)
#else /* CONFIG_SYS_USE_NANDFLASH */
/* bootstrap + u-boot + env + linux in nandflash */
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0xc0000
#define CONFIG_ENV_OFFSET_REDUND 0x100000
#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
#define CONFIG_SYS_MONITOR_SEC 1:0-3
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10)
-#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007E0000)
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE)
#ifdef CONFIG_SYS_USE_DATAFLASH
/* bootstrap + u-boot + env + linux in dataflash on CS0 */
-#define CONFIG_ENV_IS_IN_DATAFLASH 1
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
#define CONFIG_ENV_OFFSET 0x4200
#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
#elif CONFIG_SYS_USE_NANDFLASH
/* bootstrap + u-boot + env + linux in nandflash */
-#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_OFFSET 0x120000
#define CONFIG_ENV_OFFSET_REDUND 0x100000
#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
#ifdef CONFIG_SYS_USE_NANDFLASH
/* bootstrap + u-boot + env in nandflash */
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x120000
#define CONFIG_ENV_OFFSET_REDUND 0x100000
#define CONFIG_ENV_SIZE 0x20000
*/
#define FAT_ENV_DEVICE_AND_PART "0"
#define FAT_ENV_FILE "uboot.env"
-#define CONFIG_ENV_IS_IN_FAT
#define CONFIG_ENV_SIZE 0x4000
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
-#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT "nand0=atmel_nand"
#define MTDPARTS_DEFAULT \
"mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \
#ifdef CONFIG_SYS_USE_SPIFLASH
/* bootstrap + u-boot + env + linux in dataflash on CS0 */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET 0x5000
#define CONFIG_ENV_SIZE 0x3000
#define CONFIG_ENV_SECT_SIZE 0x1000
#elif defined(CONFIG_SYS_USE_NANDFLASH)
/* bootstrap + u-boot + env + linux in nandflash */
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x120000
#define CONFIG_ENV_OFFSET_REDUND 0x100000
#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
#define CONFIG_SYS_MMC_ENV_DEV 0
#else
/* Use file in FAT file to save environment */
-#define CONFIG_ENV_IS_IN_FAT
#define FAT_ENV_INTERFACE "mmc"
#define FAT_ENV_FILE "uboot.env"
#define FAT_ENV_DEVICE_AND_PART "0"
#ifdef CONFIG_SYS_USE_DATAFLASH
/* bootstrap + u-boot + env + linux in dataflash on CS0 */
-#define CONFIG_ENV_IS_IN_DATAFLASH 1
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
#define CONFIG_ENV_OFFSET 0x4200
#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
#elif CONFIG_SYS_USE_NANDFLASH
/* bootstrap + u-boot + env + linux in nandflash */
-#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_OFFSET 0x120000
#define CONFIG_ENV_OFFSET_REDUND 0x100000
#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
#else /* CONFIG_SYS_USE_MMC */
/* bootstrap + u-boot + env + linux in mmc */
-#define CONFIG_ENV_IS_IN_FAT
#define FAT_ENV_INTERFACE "mmc"
#define FAT_ENV_FILE "uboot.env"
#define FAT_ENV_DEVICE_AND_PART "0"
#define CONFIG_CMD_NAND_TRIMFFS
#define CONFIG_MTD_DEVICE
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_PARTITIONS
-#define CONFIG_RBTREE
-#define CONFIG_LZO
-#define CONFIG_CMD_UBIFS
#endif
/* USB */
#ifdef CONFIG_SYS_USE_NANDFLASH
/* bootstrap + u-boot + env + linux in nandflash */
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x120000
#define CONFIG_ENV_OFFSET_REDUND 0x100000
#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
"bootm 0x22000000"
#elif defined(CONFIG_SYS_USE_SPIFLASH)
/* bootstrap + u-boot + env + linux in spi flash */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET 0x5000
#define CONFIG_ENV_SIZE 0x3000
#define CONFIG_ENV_SECT_SIZE 0x1000
"bootm 0x22000000"
#elif defined(CONFIG_SYS_USE_DATAFLASH)
/* bootstrap + u-boot + env + linux in data flash */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET 0x4200
#define CONFIG_ENV_SIZE 0x4200
#define CONFIG_ENV_SECT_SIZE 0x210
"bootm 0x22000000"
#else /* CONFIG_SYS_USE_MMC */
/* bootstrap + u-boot + env + linux in mmc */
-#define CONFIG_ENV_IS_IN_FAT
#define FAT_ENV_INTERFACE "mmc"
#define FAT_ENV_FILE "uboot.env"
#define FAT_ENV_DEVICE_AND_PART "0"
/*
* Environment settings
*/
-#define CONFIG_ENV_IS_IN_FAT
#define CONFIG_ENV_SIZE SZ_16K
#define FAT_ENV_INTERFACE "mmc"
#define FAT_ENV_DEVICE_AND_PART "0:1"
#define CONFIG_SYS_BOOTM_LEN SZ_64M
/* UBI Support */
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
-#define CONFIG_RBTREE
-#define CONFIG_LZO
-#define CONFIG_CMD_UBIFS
/* I2C configuration */
#undef CONFIG_SYS_OMAP24_I2C_SPEED
"128k(SPL.backup3)," \
"1920k(u-boot)," \
"-(UBI)"
-#define CONFIG_ENV_IS_NOWHERE
#endif
#endif
#define __CONFIG_BAV335X_H
#include <configs/ti_am335x_common.h>
-#define CONFIG_ENV_IS_NOWHERE
#ifndef CONFIG_SPL_BUILD
# define CONFIG_TIMESTAMP
-# define CONFIG_LZO
#endif
#define CONFIG_SYS_BOOTM_LEN (16 << 20)
"8m(NAND.kernel)," \
"-(NAND.rootfs)"
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000
-#undef CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x001c0000
#define CONFIG_ENV_OFFSET_REDUND 0x001e0000
#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
#define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */
"128k(u-boot-env2),3464k(kernel)," \
"-(rootfs)"
#elif defined(CONFIG_EMMC_BOOT)
-#undef CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_ENV_OFFSET 0x0
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
/* Reduce SPL size by removing unlikey targets */
#ifdef CONFIG_NOR_BOOT
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_ENV_OFFSET (512 << 10) /* 512 KiB */
#define CONFIG_ENV_OFFSET_REDUND (768 << 10) /* 768 KiB */
#define CONFIG_SYS_NS16550_COM1 0x3e000000
/* must fit into GPT:u-boot-env partition */
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_OFFSET (0x00011a00 * 512)
#define CONFIG_ENV_SIZE (8 * 512)
#define CONFIG_SYS_NS16550_COM1 0x3e000000
/* must fit into GPT:u-boot-env partition */
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_OFFSET (0x00011a00 * 512)
#define CONFIG_ENV_SIZE (8 * 512)
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_IS_NOWHERE
/* console configuration */
#define CONFIG_SYS_CBSIZE 1024 /* Console buffer size */
#define CONFIG_BAUDRATE 115200
#define CONFIG_ENV_SIZE SZ_8K
-#define CONFIG_ENV_IS_NOWHERE
/* console configuration */
#define CONFIG_SYS_CBSIZE SZ_1K
#define CONFIG_SYS_I2C_TEGRA
/* Environment in eMMC, at the end of 2nd "boot sector" */
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
/* Environment */
#define CONFIG_ENV_SIZE (16 * 1024)
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_ENV_IS_NOWHERE
/* FEC Ethernet on SoC */
#ifdef CONFIG_CMD_NET
/* ENV setting */
#if !defined(CONFIG_MTD_NOR_FLASH)
#else
-#undef CONFIG_ENV_IS_IN_SPI_FLASH
#undef CONFIG_ENV_ADDR
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE (256 * 1024)
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
/*
* Environment
*/
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
#ifdef CONFIG_64BIT
*/
#if defined(CONFIG_SPI_BOOT) || defined(CONFIG_NAND)
#define CONFIG_MTD_DEVICE /* Required for mtdparts */
-#define CONFIG_CMD_MTDPARTS
#endif /* CONFIG_SPI_BOOT, ... */
#ifdef CONFIG_SPL_OS_BOOT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
-#undef CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
#define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */
#define CONFIG_ENV_OFFSET_REDUND (896 << 10) /* 896 KiB in */
#elif defined(CONFIG_EMMC_BOOT)
-#undef CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_ENV_OFFSET 0x40000 /* TODO: Adresse definieren */
#elif defined(CONFIG_NAND)
/* No NAND env support in SPL */
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_ENV_IS_NOWHERE
-#else
-#define CONFIG_ENV_IS_IN_NAND
-#endif
#define CONFIG_ENV_OFFSET 0x60000
#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_ENV_SIZE
#else
#define CONFIG_AM335X_USB1
#define CONFIG_AM335X_USB1_MODE MUSB_HOST
-#undef CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_ENV_OFFSET 0x40000 /* TODO: Adresse definieren */
#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_I2C_TEGRA
/* Environment in eMMC, at the end of 2nd "boot sector" */
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_SYS_I2C_TEGRA
/* Environment in eMMC, at the end of 2nd "boot sector" */
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_ENV_SIZE (8 * 1024)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#if defined(CONFIG_ENV_IS_IN_SPI_FLASH)
#define CONFIG_ENV_OFFSET (768 * 1024)
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
#ifndef CONFIG_SPL_BUILD
# define CONFIG_TIMESTAMP
-# define CONFIG_LZO
#endif
/* Clock Defines */
#define CONFIG_ENV_SIZE SZ_128K
#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#else
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_OFFSET SZ_128K
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB env size */
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
#define CONFIG_ENV_OFFSET (768 * 1024)
#define CONFIG_ENV_SPI_MAX_HZ 48000000
/* USB xHCI HOST */
#define CONFIG_USB_XHCI_OMAP
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#define CONFIG_OMAP_USB_PHY
#define CONFIG_OMAP_USB3PHY1_HOST
#define CONFIG_ENV_MIN_ENTRIES 128
/* Environment in MMC */
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SECT_SIZE 0x200
#define CONFIG_ENV_SIZE 0x10000
#define CONFIG_SYS_LITTLE_ENDIAN
#define CONFIG_MACH_TYPE 4273
-/* CMD */
-#define CONFIG_CMD_MTDPARTS
-
/* MMC */
#define CONFIG_SYS_FSL_USDHC_NUM 3
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
"-(reserved)"
/* Environment */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
"1m(u-boot),1m(u-boot-env)," \
"1m(dtb),4m(splash)," \
"6m(kernel),-(rootfs)"
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x300000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_USB_TTY
/* commands to include */
-#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define CONFIG_MTD_PARTITIONS
#define MTDIDS_DEFAULT "nand0=nand"
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-#define CONFIG_ENV_IS_IN_NAND
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
#endif /* CONFIG_USB_MUSB_AM35X */
/* commands to include */
-#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define CONFIG_MTD_PARTITIONS
#define MTDIDS_DEFAULT "nand0=nand"
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-#define CONFIG_ENV_IS_IN_NAND
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
/* USB support */
#define CONFIG_USB_XHCI_OMAP
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#define CONFIG_OMAP_USB_PHY
#define CONFIG_AM437X_USB2PHY2_HOST
#define V_OSCK 24000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
#define CONFIG_ENV_OFFSET (768 * 1024)
#define CONFIG_ENV_SPI_MAX_HZ 48000000
#undef CONFIG_ENV_OFFSET
#undef CONFIG_ENV_SIZE
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
#define CONFIG_SYS_MMC_ENV_PART 0
#define CONFIG_ENV_OFFSET 0xc0000 /* (in bytes) 768 KB */
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
/* USB UHH support options */
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 76 /* HSIC2 HUB #RESET */
#ifndef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_ENV_OFFSET 0x4000
#define CONFIG_ENV_SECT_SIZE 0x2000
-#define CONFIG_ENV_IS_IN_FLASH 1
#else
#define CONFIG_ENV_ADDR 0xffe04000
#define CONFIG_ENV_SECT_SIZE 0x2000
-#define CONFIG_ENV_IS_IN_FLASH 1
#endif
#define LDS_BOARD_TEXT \
#define CONFIG_SYS_GENERIC_BOARD
#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/gpio.h>
+#include <asm/mach-imx/gpio.h>
#ifdef CONFIG_SPL
#include "imx6_spl.h"
/* environment organization */
#define CONFIG_ENV_SIZE (8 * 1024)
-#define CONFIG_ENV_IS_IN_MMC
-
#if defined(CONFIG_ENV_IS_IN_MMC)
/* Environment in eMMC, before config block at the end of 1st "boot sector" */
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* environment organization */
-#define CONFIG_ENV_IS_IN_NAND
#if defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
#define CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES
#define CONFIG_CMD_NAND_TORTURE
-/* UBI stuff */
-#define CONFIG_RBTREE
-#define CONFIG_LZO
-#define CONFIG_CMD_UBIFS /* increases size by almost 60 KB */
-
/* Dynamic MTD partition support */
-#define CONFIG_CMD_MTDPARTS /* Enable 'mtdparts' command line support */
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define MTDIDS_DEFAULT "nand0=gpmi-nand"
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
#define CONFIG_SYS_FLASH_PROTECTION 1
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-
-#else /* No flash */
-#define CONFIG_ENV_IS_NOWHERE
#endif
#define CONFIG_SYS_MONITOR_BASE 0x0
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* Dynamic MTD partition support */
-#define CONFIG_CMD_MTDPARTS /* Enable 'mtdparts' command line support */
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define MTDIDS_DEFAULT "nand0=tegra_nand"
"-(ubi)"
/* Environment in NAND, 64K is a bit excessive but erase block is 512K anyway */
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET (SZ_2M)
#undef CONFIG_ENV_SIZE /* undef size from tegra20-common.h */
#define CONFIG_ENV_SIZE (SZ_64K)
-/* UBI */
-#define CONFIG_CMD_UBIFS /* increases size by almost 60 KB */
-#define CONFIG_LZO
-#define CONFIG_RBTREE
-
-
#define BOARD_EXTRA_ENV_SETTINGS \
"mtdparts=" MTDPARTS_DEFAULT "\0"
#define CONFIG_SYS_I2C_TEGRA
/* Environment in eMMC, before config block at the end of 1st "boot sector" */
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \
CONFIG_TDX_CFG_BLOCK_OFFSET)
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
/* Dynamic MTD partition support */
-#define CONFIG_CMD_MTDPARTS /* Enable 'mtdparts' command line support */
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define MTDIDS_DEFAULT "nand0=vf610_nfc"
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 1
-#define CONFIG_RBTREE
-#define CONFIG_LZO
-#define CONFIG_CMD_UBIFS /* increases size by almost 60 KB */
-
#define CONFIG_FEC_MXC
#define CONFIG_MII
#define IMX_FEC_BASE ENET1_BASE_ADDR
#define CONFIG_REMAKE_ELF
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE (8 * 1024)
#define CONFIG_AUTO_COMPLETE
#define CONFIG_REMAKE_ELF
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE (8 * 1024)
#define CONFIG_AUTO_COMPLETE
#define CONFIG_REMAKE_ELF
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE (8 * 1024)
#define CONFIG_AUTO_COMPLETE
* Environment
*/
#if defined(CONFIG_TRAILBLAZER)
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#elif defined(CONFIG_RAMBOOT_SPIFLASH)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 10000000
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
#define CONFIG_ENV_SECT_SIZE 0x10000
#elif defined(CONFIG_RAMBOOT_SDCARD)
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_FSL_FIXED_MMC_LOCATION
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_EHCI_IS_TDI
/* Environment in SPI NOR flash */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 1
#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
#define CONFIG_ENV_OVERWRITE
#ifndef CONFIG_MTD_NOR_FLASH
-#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
-#define CONFIG_ENV_IS_NOWHERE
-#endif
#else
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#if defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 10000000
#define CONFIG_ENV_SECT_SIZE 0x10000
#elif defined(CONFIG_SDCARD)
#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_FSL_FIXED_MMC_LOCATION
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_OFFSET (512 * 1658)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-#define CONFIG_ENV_IS_IN_REMOTE
#define CONFIG_ENV_ADDR 0xffe20000
#define CONFIG_ENV_SIZE 0x2000
#elif defined(CONFIG_ENV_IS_NOWHERE)
#define CONFIG_ENV_SIZE 0x2000
#else
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#define CONFIG_NET_RETRY_COUNT 20
#define CONFIG_AT91_WANTS_COMMON_PHY
-/* USB */
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
-
-/* USB DFU support */
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_SYS_LOAD_ADDR ATMEL_BASE_CS6
/* bootstrap + u-boot + env in nandflash */
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x100000
#define CONFIG_ENV_OFFSET_REDUND 0x180000
#define CONFIG_ENV_SIZE SZ_128K
#if defined(CONFIG_SDCARD)
#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_FSL_FIXED_MMC_LOCATION
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
* Flash & Environment
*/
#ifdef CONFIG_USE_NAND
-#undef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_NAND_DAVINCI
-#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
#define CONFIG_ENV_SIZE (128 << 10)
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#endif
#ifdef CONFIG_USE_NOR
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#endif
#ifdef CONFIG_USE_SPIFLASH
-#undef CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE (64 << 10)
#define CONFIG_ENV_OFFSET (512 << 10)
#define CONFIG_ENV_SECT_SIZE (64 << 10)
#ifdef CONFIG_USE_NAND
#define CONFIG_CMD_NAND
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
-#define CONFIG_LZO
-#define CONFIG_RBTREE
-#define CONFIG_CMD_UBIFS
#endif
#ifdef CONFIG_USE_SPIFLASH
#if !defined(CONFIG_USE_NAND) && \
!defined(CONFIG_USE_NOR) && \
!defined(CONFIG_USE_SPIFLASH)
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE (16 << 10)
#endif
#define CONFIG_SYS_I2C_TEGRA
/* Environment in eMMC, at the end of 2nd "boot sector" */
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
/* Environment in SPI NOR flash */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
#define CONFIG_EHCI_IS_TDI
/* Environment in SPI NOR flash */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 1
#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
#define CONFIG_EHCI_IS_TDI
/* Environment in SPI NOR flash */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
/* Environment in SPI NOR flash */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
-#define CONFIG_ENV_IS_NOWHERE 1
-
/* Address and size of Primary Environment Sector */
#define CONFIG_ENV_ADDR 0xB0030000
#define CONFIG_ENV_SIZE 0x10000
/*
* Environment
*/
-#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_SIZE SZ_128K
#define CONFIG_ENV_OFFSET 0x000A0000
0x01000000) /* 16MB */
/* NAND and environment organization */
-#define CONFIG_ENV_IS_IN_NAND 1
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
* Environment variables configurations
*/
#ifdef CONFIG_CMD_NAND
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128KB */
-#else
-#define CONFIG_ENV_IS_NOWHERE
#endif
#define CONFIG_ENV_SIZE 0x20000 /* 128KB */
* Environment variables configurations
*/
#ifdef CONFIG_CMD_NAND
-#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
-#else
-#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
#endif
/*
* max 4k env size is enough, but in case of nand
/*
* File system
*/
-#define CONFIG_CMD_UBIFS
-#define CONFIG_RBTREE
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define CONFIG_MTD_PARTITIONS
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_LZO
#endif /* _CONFIG_DOCKSTAR_H */
#ifndef CONFIG_QSPI_BOOT
/* MMC ENV related defines */
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
#define CONFIG_ENV_SIZE (128 << 10)
#define CONFIG_ENV_OFFSET 0x260000
#define CONFIG_SYS_SPI_ARGS_OFFS 0x140000
#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000
#if defined(CONFIG_QSPI_BOOT)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
#define CONFIG_ENV_SIZE (64 << 10)
/* USB xHCI HOST */
#define CONFIG_USB_XHCI_OMAP
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#define CONFIG_OMAP_USB_PHY
#define CONFIG_OMAP_USB2PHY2_HOST
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
/* Reduce SPL size by removing unlikey targets */
#ifdef CONFIG_NOR_BOOT
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE (128 * 1024) /* 128 KiB */
#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:" \
/* Enable that for switching of boot partitions */
/* Disabled by default as some sub-commands can brick eMMC */
/*#define CONFIG_SUPPORT_EMMC_BOOT */
-#define CONFIG_CMD_REGINFO /* Register dump */
#define CONFIG_CMD_TFTP
/* Partition table support */
"pxefile_addr_r=0x90100000\0"\
BOOTENV
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_VARS_UBOOT_CONFIG
* Environment variables configurations
*/
#ifdef CONFIG_SPI_FLASH
-#define CONFIG_ENV_IS_IN_SPI_FLASH 1
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64k */
-#else
-#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
#endif
#ifdef CONFIG_CMD_SF
* Environment variables configurations
*/
#ifdef CONFIG_SPI_FLASH
-#define CONFIG_ENV_IS_IN_SPI_FLASH 1
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64k */
-#else
-#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
#endif
#ifdef CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
/* Environment in SPI NOR flash */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET 0x7E0000 /* RedBoot config partition in DTS */
#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
#if 0
#undef CONFIG_DM_USB
#define CONFIG_USB_XHCI_PCI
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#endif
#if !defined(CONFIG_USB_XHCI_HCD)
#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
/* USB UHH support options */
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
-
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 1
#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 62
/* GPIO */
/* ENV related config options */
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_SYS_I2C_TEGRA
/* Environment in eMMC, at the end of 2nd "boot sector" */
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#endif
#ifdef CONFIG_USE_SPIFLASH
-#undef CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE (8 << 10)
#define CONFIG_ENV_OFFSET 0x80000
#define CONFIG_ENV_SECT_SIZE (64 << 10)
#ifdef CONFIG_SYS_USE_NAND
#define CONFIG_CMD_NAND
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
-#define CONFIG_LZO
-#define CONFIG_RBTREE
-#define CONFIG_CMD_UBIFS
#define CONFIG_NAND_DAVINCI
#define CONFIG_SYS_NAND_PAGE_2K
#if !defined(CONFIG_SYS_USE_NAND) && \
!defined(CONFIG_USE_NOR) && \
!defined(CONFIG_USE_SPIFLASH)
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE (16 << 10)
#endif
#define CONFIG_ENV_ADDR 0xFF040000
#define CONFIG_ENV_SECT_SIZE 0x00020000
-#define CONFIG_ENV_IS_IN_FLASH 1
/*
* BOOTP options
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* ENV setting */
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
#define CONFIG_ENV_OVERWRITE /* Vendor params unprotected */
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR 0x60040000
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
--- /dev/null
+/*
+ * Copyright (c) 2017 Intel Corp.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/ibmpc.h>
+
+/* Boot */
+#define CONFIG_CMD_ZBOOT
+#define CONFIG_BOOTCOMMAND "run bootcmd"
+
+/* DISK Partition support */
+#define CONFIG_RANDOM_UUID
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+
+#define CONFIG_SYS_CBSIZE 2048
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 128
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_AUTO_COMPLETE
+
+/* Memory */
+#define CONFIG_SYS_LOAD_ADDR 0x100000
+#define CONFIG_PHYSMEM
+
+#define CONFIG_NR_DRAM_BANKS 3
+
+#define CONFIG_SYS_STACK_SIZE (32 * 1024)
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+
+#define CONFIG_SYS_MALLOC_LEN (128 * 1024 * 1024)
+
+#define CONFIG_SYS_MEMTEST_START 0x00100000
+#define CONFIG_SYS_MEMTEST_END 0x01000000
+
+/* Environment */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 0
+#define CONFIG_ENV_SIZE (64 * 1024)
+#define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
+#define CONFIG_ENV_OFFSET_REDUND (6 * 1024 * 1024)
+#define CONFIG_SUPPORT_EMMC_BOOT
+
+/* PCI */
+#define CONFIG_CMD_PCI
+
+/* RTC */
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
+#define CONFIG_RTC_MC146818
+
+#endif
/*
* Environment variables configurations
*/
-#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SECT_SIZE 0x2000 /* 16K */
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_OFFSET 0x4000 /* env starts here */
#undef CONFIG_TPM_TIS_BASE_ADDRESS
-#undef CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_IS_NOWHERE
#undef CONFIG_SCSI_AHCI
#undef CONFIG_INTEL_ICH6_GPIO
#undef CONFIG_USB_EHCI_PCI
#define CONFIG_ENV_SIZE (8 * 1024)
-#define CONFIG_ENV_IS_IN_MMC
-
#if defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_SYS_MMC_ENV_DEV 1
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_MXC_UART_BASE UART2_BASE
#define CONSOLE_DEV "ttymxc1"
-#define CONFIG_MMCROOT "/dev/mmcblk1p2"
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
func(PXE, pxe, na) \
func(DHCP, dhcp, na)
+#define CONFIG_BOOTCOMMAND \
+ "run finduuid; " \
+ "run distro_bootcmd"
+
#include <config_distro_bootcmd.h>
#define CONSOLE_STDIN_SETTINGS \
CONSOLE_ENV_SETTINGS \
MEM_LAYOUT_ENV_SETTINGS \
"fdtfile=" CONFIG_FDTFILE "\0" \
+ "finduuid=part uuid mmc 0:1 uuid\0" \
BOOTENV
#endif /* __RIOTBOARD_CONFIG_H */
#define CONFIG_BOARD_COMMON
#define CONFIG_ESPRESSO7420
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_SYS_TEXT_BASE 0x43E00000
/* Use hardware flash sectors protection instead of U-Boot software protection */
#undef CONFIG_SYS_FLASH_PROTECTION
#undef CONFIG_SYS_DIRECT_FLASH_TFTP
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
#define DATAFLASH_TCSS (0x1a << 16)
#define DATAFLASH_TCHS (0x1 << 24)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET 0x3DE000
#define CONFIG_ENV_SECT_SIZE (132 << 10)
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
#define CONFIG_AT91_GPIO
/* Command line configuration */
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_NAND
#ifndef MINIMAL_LOADER
#define CONFIG_CMD_REISER
#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_UBIFS
#endif
/* NAND flash */
#define MTDIDS_DEFAULT "nand0=atmel_nand"
#define MTDPARTS_DEFAULT "mtdparts=atmel_nand:-(root)"
#endif
-#define CONFIG_LZO
-#define CONFIG_RBTREE
/* Boot command */
#define CONFIG_CMDLINE_TAG
/* Memory Info */
#define CONFIG_SYS_LOAD_ADDR 0x83000000
-#define CONFIG_ENV_IS_NOWHERE
-
#define CONFIG_ENV_SIZE 0x20000
#endif /* __CONFIG_H */
#include <configs/rk3368_common.h>
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_CONSOLE_SCROLL_LINES 10
/* Store env in emmc */
#undef CONFIG_ENV_SIZE
#define CONFIG_ENV_SIZE (32 << 10)
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 0
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define ROCKCHIP_DEVICE_SETTINGS
#include <configs/rk3288_common.h>
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#endif
#include <configs/rk3328_common.h>
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1
/*
* SPL @ 32k for ~36k
#include <configs/rk3399_common.h>
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1
/*
* SPL @ 32k for ~36k
#define CONFIG_MMC_DEFAULT_DEV 0
#undef CONFIG_CMD_ONENAND
-#undef CONFIG_CMD_MTDPARTS
/* TIZEN THOR downloader support */
#define CONFIG_CMD_THOR_DOWNLOAD
/* Enable Time Command */
/* USB */
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
-
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_USB_ETHER_SMSC95XX
#define CONFIG_EXYNOS5_DT
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BASE 0x12D30000
#define FLASH_SIZE (4 << 20)
#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_ENV_SECT_SIZE)
#define ROCKCHIP_DEVICE_SETTINGS
#include <configs/rk3288_common.h>
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#endif
#define __CONFIG_H
#define ROCKCHIP_DEVICE_SETTINGS \
- "stdin=serial,cros-ec-keyb\0" \
+ "stdin=serial,usbkbd\0" \
"stdout=serial,vidconsole\0" \
- "stderr=serial,vidconsole\0"
+ "stderr=serial,vidconsole\0" \
+ "preboot=usb start\0"
#include <configs/rk3288_common.h>
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#endif
/*
* MTD Command for mtdparts
*/
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE
#define CONFIG_FLASH_CFI_MTD
#define CONFIG_MTD_PARTITIONS
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_IS_IN_FLASH
-
/*
* CFI FLASH driver setup
*/
#define __GE_BX50V3_CONFIG_H
#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/gpio.h>
+#include <asm/mach-imx/gpio.h>
#define BX50V3_BOOTARGS_EXTRA
#if defined(CONFIG_TARGET_GE_B450V3)
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* environment organization */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE (8 * 1024)
#define CONFIG_ENV_OFFSET (768 * 1024)
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
#include <configs/rk3368_common.h>
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_CONSOLE_SCROLL_LINES 10
* Environment variables configurations
*/
#ifdef CONFIG_CMD_NAND
-#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
-#else
-#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
#endif
/*
* max 4k env size is enough, but in case of nand
/*
* Environment variables configurations
*/
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE 0x4000
#ifdef CONFIG_CMD_USB
* Environment variables configurations
*/
#ifdef CONFIG_CMD_NAND
-#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
-#else
-#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
#endif
/*
* max 4k env size is enough, but in case of nand
#define CONFIG_SUPPORT_EMMC_BOOT
#define CONFIG_SUPPORT_EMMC_RPMB
-/* Filesystem support */
-#define CONFIG_CMD_UBIFS
-
/*
* SATA Configs
*/
/* Various command support */
#define CONFIG_CMD_UNZIP /* gzwrite */
-#define CONFIG_RBTREE
/* Ethernet support */
#define CONFIG_FEC_MXC
/*
* MTD Command for mtdparts
*/
-#define CONFIG_LZO
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#ifdef CONFIG_SPI_FLASH
#endif
/* Persistent Environment Config */
-#ifdef CONFIG_SPI_FLASH
- #define CONFIG_ENV_IS_IN_SPI_FLASH
-#elif defined(CONFIG_SPL_NAND_SUPPORT)
- #define CONFIG_ENV_IS_IN_NAND
-#else
- #define CONFIG_ENV_IS_IN_MMC
-#endif
#if defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 1
#define CONFIG_ENV_SIZE 0x00040000
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* default load address */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* Environment in NAND (which is 512M), aligned to start of last sector */
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sector size */
/* USB Host support */
/* Environment data setup
*/
-#define CONFIG_ENV_IS_IN_NVRAM
#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfff88000 /* NVRAM base address */
#define CONFIG_SYS_NVRAM_SIZE 0x8000 /* NVRAM size */
#define CONFIG_ENV_SIZE 0x2000 /* Size of Environ */
/* Preserve environment on sd card */
#define CONFIG_ENV_SIZE 0x1000
-#define CONFIG_ENV_IS_IN_FAT
#define FAT_ENV_INTERFACE "mmc"
#define FAT_ENV_DEVICE_AND_PART "1:1"
#define FAT_ENV_FILE "uboot.env"
* Environment
*/
#if 1
-#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
#else
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#endif
* Environment settings
*/
#define CONFIG_ENV_SIZE SZ_16K
-#define CONFIG_ENV_IS_IN_FAT
#define FAT_ENV_INTERFACE "mmc"
#define FAT_ENV_DEVICE_AND_PART "0:1"
#define FAT_ENV_FILE "uboot.env"
#define CONFIG_REMAKE_ELF
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE (8 * 1024)
#define CONFIG_AUTO_COMPLETE
* Environment variables configuration
*/
#ifdef CONFIG_CMD_NAND
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SECT_SIZE 0x20000
-#else
-#define CONFIG_ENV_IS_NOWHERE
#endif
#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_ENV_OFFSET 0xe0000
* Compression configuration
*/
#define CONFIG_BZIP2
-#define CONFIG_LZO
/*
* Commands configuration
* Environment variables configuration
*/
#ifdef CONFIG_CMD_NAND
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SECT_SIZE 0x20000
-#else
-#define CONFIG_ENV_IS_NOWHERE
#endif
#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_ENV_OFFSET 0x80000
/*
* File system
*/
-#define CONFIG_CMD_UBIFS
-#define CONFIG_RBTREE
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
-#define CONFIG_CMD_MTDPARTS
#endif /* _CONFIG_ICONNECT_H */
/*
* Environment Configuration
*/
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \
+ CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_JFFS2_DEV "0"
/* mtdparts command line support */
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_FLASH_CFI_MTD
#define CONFIG_MTD_DEVICE
#define MTDIDS_DEFAULT "nor0=ff800000.flash,nand0=e1000000.flash"
/* UBI Support */
#define CONFIG_CMD_NAND_TRIMFFS
-#define CONFIG_CMD_UBIFS
-#define CONFIG_RBTREE
-#define CONFIG_LZO
#define CONFIG_MTD_PARTITIONS
/* bootcount support */
/* -------------------------------------------------
* Environment
*/
-#define CONFIG_ENV_IS_NOWHERE 1
#define CONFIG_ENV_SIZE 0x4000
/* ---------------------------------------------------------------------
/*
* Flash & Environment
*/
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
/* Use buffered writes (~10x faster) */
*/
#define CONFIG_MXC_GPIO
-/*
- * MTD partitions
- */
-#define CONFIG_CMD_MTDPARTS
-
/*
* U-Boot general configuration
*/
/* Monitor at beginning of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_ENV_IS_IN_EEPROM
#define CONFIG_ENV_OFFSET 0x00 /* env. starts here */
#define CONFIG_ENV_SIZE 4096
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
/*
* JFFS2 partitions
*/
-#undef CONFIG_CMD_MTDPARTS
#define CONFIG_JFFS2_DEV "nor0"
/* EET platform additions */
/* MTD device */
# define CONFIG_MTD_DEVICE
-# define CONFIG_CMD_MTDPARTS
# define CONFIG_MTD_PARTITIONS
# define MTDIDS_DEFAULT "nand0=gpmi-nand"
# define MTDPARTS_DEFAULT "mtdparts=gpmi-nand:2m(spl),2m(uboot)," \
"1m(env),8m(kernel),1m(dtb),-(rootfs)"
-/* UBI */
-# define CONFIG_CMD_UBIFS
-# define CONFIG_RBTREE
-# define CONFIG_LZO
-
# define CONFIG_APBH_DMA
# define CONFIG_APBH_DMA_BURST
# define CONFIG_APBH_DMA_BURST8
/* Environment organization */
#define CONFIG_ENV_SIZE (8 * 1024)
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x400000
#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
/* MTD device */
# define CONFIG_MTD_DEVICE
-# define CONFIG_CMD_MTDPARTS
# define CONFIG_MTD_PARTITIONS
# define MTDIDS_DEFAULT "nand0=gpmi-nand"
# define MTDPARTS_DEFAULT "mtdparts=gpmi-nand:4m(uboot)," \
/* Define the payload for FAT/EXT support */
#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
-#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
+# ifdef CONFIG_OF_CONTROL
+# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
+# else
+# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
+# endif
#endif
#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6SL)
/* Flash settings */
#define CONFIG_SYS_FLASH_SIZE 0x02000000 /* 32 MiB */
#define CONFIG_SYS_MAX_FLASH_SECT 128
-#define CONFIG_ENV_IS_NOWHERE 1
#define CONFIG_ENV_SIZE 32768
/*-----------------------------------------------------------------------
*/
#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */
#define CONFIG_SYS_MAX_FLASH_SECT 64
-#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_SYS_MONITOR_LEN 0x00100000
/*
* Flash & Environment
*/
#define CONFIG_NAND_DAVINCI
-#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
#define CONFIG_ENV_SIZE (128 << 10)
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NAND_TRIMFFS
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
-#define CONFIG_LZO
-#define CONFIG_RBTREE
-#define CONFIG_CMD_UBIFS
#define MTDIDS_NAME_STR "davinci_nand.0"
#define MTDIDS_DEFAULT "nand0=" MTDIDS_NAME_STR
#define CONFIG_SYS_I2C_TEGRA
/* Environment in eMMC, at the end of 2nd "boot sector" */
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
/* Platform type */
#define CONFIG_SOC_K2E
+#ifdef CONFIG_TI_SECURE_DEVICE
+#define DEFAULT_SEC_BOOT_ENV \
+ DEFAULT_FIT_TI_ARGS \
+ "findfdt=setenv fdtfile ${name_fdt}\0"
+#else
+#define DEFAULT_SEC_BOOT_ENV
+#endif
+
/* U-Boot general configuration */
#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \
DEFAULT_FW_INITRAMFS_BOOT_ENV \
+ DEFAULT_SEC_BOOT_ENV \
"boot=ubi\0" \
"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \
"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0" \
"name_fs=arago-console-image-k2e-evm.cpio.gz\0"
#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x100000
#include <configs/ti_armv7_keystone2.h>
DEFAULT_MMC_TI_ARGS \
DEFAULT_PMMC_BOOT_ENV \
DEFAULT_FW_INITRAMFS_BOOT_ENV \
+ DEFAULT_FIT_TI_ARGS \
"boot=mmc\0" \
"console=ttyS0,115200n8\0" \
"bootpart=0:2\0" \
"get_mon_mmc=load mmc ${bootpart} ${addr_mon} ${bootdir}/${name_mon}\0"\
"name_fs=arago-base-tisdk-image-k2g-evm.cpio\0"
+#ifndef CONFIG_TI_SECURE_DEVICE
#define CONFIG_BOOTCOMMAND \
+ "run findfdt; " \
"run envboot; " \
- "run set_name_pmmc init_${boot} init_fw_rd_${boot} " \
- "get_pmmc_${boot} run_pmmc get_mon_${boot} run_mon " \
- "findfdt get_fdt_${boot} get_kern_${boot} run_kern"
+ "run init_${boot}; " \
+ "run get_mon_${boot} run_mon; " \
+ "run set_name_pmmc get_pmmc_${boot} run_pmmc; " \
+ "run get_kern_${boot}; " \
+ "run init_fw_rd_${boot}; " \
+ "run get_fdt_${boot}; " \
+ "run run_kern"
+#else
+#define CONFIG_BOOTCOMMAND \
+ "run findfdt; " \
+ "run envboot; " \
+ "run run_mon_hs; " \
+ "run init_${boot}; " \
+ "run set_name_pmmc get_pmmc_${boot} run_pmmc; " \
+ "run get_fit_${boot}; " \
+ "bootm ${fit_loadaddr}#${name_fdt}"
+#endif
/* SPL SPI Loader Configuration */
#define CONFIG_SPL_TEXT_BASE 0x0c080000
#define CONFIG_PHY_MICREL
#define PHY_ANEG_TIMEOUT 10000 /* PHY needs longer aneg time */
-#define CONFIG_ENV_IS_IN_FAT
#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
#define FAT_ENV_INTERFACE "mmc"
#define FAT_ENV_DEVICE_AND_PART "0:1"
/* Platform type */
#define CONFIG_SOC_K2HK
+#ifdef CONFIG_TI_SECURE_DEVICE
+#define DEFAULT_SEC_BOOT_ENV \
+ DEFAULT_FIT_TI_ARGS \
+ "findfdt=setenv fdtfile ${name_fdt}\0"
+#else
+#define DEFAULT_SEC_BOOT_ENV
+#endif
+
/* U-Boot general configuration */
#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \
DEFAULT_FW_INITRAMFS_BOOT_ENV \
+ DEFAULT_SEC_BOOT_ENV \
"boot=ubi\0" \
"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \
"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0" \
"name_fs=arago-console-image-k2hk-evm.cpio.gz\0"
#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x100000
#include <configs/ti_armv7_keystone2.h>
"name_fs=arago-console-image-k2l-evm.cpio.gz\0"
#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x100000
#include <configs/ti_armv7_keystone2.h>
*/
#define CONFIG_ENV_SIZE (128 * 1024)
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BOOTCOUNT_LIMIT
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_MTDPARTS
-
#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
#define CONFIG_BOOTP_HOSTNAME
/* UBI Support for all Keymile boards */
-#define CONFIG_RBTREE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_CONCAT
*/
#ifndef CONFIG_SYS_RAMBOOT
-#define CONFIG_ENV_IS_IN_FLASH
#ifndef CONFIG_ENV_ADDR
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#else /* CFG_SYS_RAMBOOT */
-#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#endif /* CFG_SYS_RAMBOOT */
#define CONFIG_INITRD_TAG /* enable INITRD tag */
#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */
-/*
- * Commands configuration
- */
-#define CONFIG_CMD_MTDPARTS
-
/*
* NAND Flash configuration
*/
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#define CONFIG_KM_COMMON_ETH_INIT /* standard km ethernet_present for piggy */
-/*
- * UBI related stuff
- */
-#define CONFIG_SYS_USE_UBI
-
/*
* I2C related stuff
*/
* Environment variables configurations
*/
#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
-#define CONFIG_ENV_IS_IN_SPI_FLASH /* use SPI-Flash for environment vars */
#define CONFIG_ENV_OFFSET 0xc0000 /* no bracets! */
#define CONFIG_ENV_SIZE 0x02000 /* Size of Environment */
#define CONFIG_ENV_SECT_SIZE 0x10000
CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_TOTAL_SIZE 0x20000 /* no bracets! */
#else
-#define CONFIG_ENV_IS_IN_EEPROM /* use EEPROM for environment vars */
#define CONFIG_SYS_DEF_EEPROM_ADDR 0x50
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_EEPROM_WREN
/* Environment in SPI Flash */
#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 20000000
/* Store env in emmc */
#undef CONFIG_ENV_SIZE
#define CONFIG_ENV_SIZE SZ_32K
-#undef CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0 /* emmc */
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
#undef CONFIG_SYS_FLASH_PROTECTION
#undef CONFIG_SYS_DIRECT_FLASH_TFTP
-#define CONFIG_ENV_IS_IN_FLASH
/* GPIO / PFC */
#define CONFIG_SH_GPIO_PFC
#include "mv-common.h"
/* Remove or override few declarations from mv-common.h */
-#undef CONFIG_RBTREE
#undef CONFIG_ENV_SPI_MAX_HZ
#undef CONFIG_SYS_IDE_MAXBUS
#undef CONFIG_SYS_IDE_MAXDEVICE
/*
* Environment variables configurations
*/
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64KB */
#define CONFIG_ENV_SIZE 0x1000 /* 4KB */
#define CONFIG_ENV_ADDR 0x70000
#define CONFIG_CLOCKS
#endif
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE (16 << 10)
/* additions for new relocation code, must added to all boards */
/* FLASH and environment organization */
#define CONFIG_ENV_SIZE SZ_8K
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (8 * SZ_64K)
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 0
*/
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE 0x40000 /* 256KB */
#define CONFIG_ENV_OFFSET 0x200000 /* 2MB */
#define CONFIG_ENV_SECT_SIZE 0x40000
#ifdef CONFIG_HAS_FSL_XHCI_USB
#define CONFIG_USB_XHCI_FSL
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#endif
#define CONFIG_CMD_MEMINFO
#ifdef CONFIG_HAS_FSL_XHCI_USB
#define CONFIG_USB_XHCI_FSL
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#endif
/* MMC */
#ifdef CONFIG_HAS_FSL_XHCI_USB
#define CONFIG_USB_XHCI_FSL
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#endif
/*
#define CONFIG_USB_XHCI_FSL
#define CONFIG_USB_XHCI_DWC3
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#endif
#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
#if defined(CONFIG_SD_BOOT)
#define CONFIG_ENV_OFFSET 0x100000
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
#elif defined(CONFIG_QSPI_BOOT)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_OFFSET 0x100000
#define CONFIG_ENV_SECT_SIZE 0x10000
#ifdef CONFIG_HAS_FSL_XHCI_USB
#define CONFIG_USB_XHCI_FSL
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#endif
/*
#if defined(CONFIG_SD_BOOT)
#define CONFIG_ENV_OFFSET 0x300000
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
#elif defined(CONFIG_QSPI_BOOT)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
#define CONFIG_ENV_SECT_SIZE 0x10000
#elif defined(CONFIG_NAND_BOOT)
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
#else
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#ifdef CONFIG_HAS_FSL_XHCI_USB
#define CONFIG_USB_XHCI_FSL
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#endif
#define CONFIG_SYS_CLK_FREQ 100000000
#if defined(CONFIG_SD_BOOT)
#define CONFIG_ENV_OFFSET 0x300000
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x20000
#elif defined(CONFIG_QSPI_BOOT)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_OFFSET 0x300000
#define CONFIG_ENV_SECT_SIZE 0x10000
#else
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#ifdef CONFIG_HAS_FSL_XHCI_USB
#define CONFIG_USB_XHCI_FSL
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#endif
/*
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_NAND_BOOT
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_OFFSET (24 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
#elif defined(CONFIG_QSPI_BOOT)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
#define CONFIG_ENV_SECT_SIZE 0x10000
#else
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x20000
#endif
#if defined(CONFIG_NAND_BOOT)
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_OFFSET (24 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
#else
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x20000
#ifdef CONFIG_HAS_FSL_XHCI_USB
#define CONFIG_USB_XHCI_FSL
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#endif
#endif
#define CONFIG_USB_XHCI_FSL
#define CONFIG_USB_XHCI_DWC3
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE
#endif
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_NAND_BOOT
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_OFFSET (24 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
#elif defined(CONFIG_QSPI_BOOT)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
#define CONFIG_ENV_SECT_SIZE 0x10000
#else
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x20000
#endif
#if defined(CONFIG_SD_BOOT)
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
#define CONFIG_ENV_SIZE 0x2000
#else
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */
#define CONFIG_USB_XHCI_FSL
#define CONFIG_USB_XHCI_DWC3
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE
#endif
#endif
#else
#define CONFIG_SYS_TEXT_BASE 0x20100000
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000
/* Store environment at top of flash */
-#define CONFIG_ENV_IS_NOWHERE 1
#define CONFIG_ENV_SIZE 0x1000
#endif /* __LS2_EMU_H */
#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000
/* Store environment at top of flash */
-#define CONFIG_ENV_IS_NOWHERE 1
#define CONFIG_ENV_SIZE 0x1000
#endif /* __LS2_SIMU_H */
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET (896 * 1024)
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024)
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_ENV_OFFSET 0x200000
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x20000
#endif
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
#ifndef CONFIG_QSPI_BOOT
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_HAS_FSL_XHCI_USB
#define CONFIG_USB_XHCI_FSL
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#include <asm/fsl_secure_boot.h>
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET (2048 * 1024)
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_HAS_FSL_XHCI_USB
#define CONFIG_USB_XHCI_FSL
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#undef CONFIG_CMDLINE_EDITING
#include <config_distro_defaults.h>
#ifdef CONFIG_SPI_FLASH
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 8
-#define CONFIG_ENV_IS_IN_SPI_FLASH 1
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K */
-#else
-#define CONFIG_ENV_IS_NOWHERE
#endif
#define CONFIG_ENV_SIZE 0x10000 /* 64k */
/* Environment */
#define CONFIG_ENV_SIZE (16 * 1024)
-#define CONFIG_ENV_IS_IN_NAND
/* Environment is in NAND */
#if defined(CONFIG_CMD_NAND) && defined(CONFIG_ENV_IS_IN_NAND)
#define CONFIG_ENV_OFFSET_REDUND \
(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
-#define CONFIG_CMD_UBIFS
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_RBTREE
-#define CONFIG_LZO
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define MTDIDS_DEFAULT "nand0=gpmi-nand"
"14m(boot)," \
"238m(data)," \
"-@4096k(UBI)"
-#else
-#define CONFIG_ENV_IS_NOWHERE
#endif
/* FEC Ethernet on SoC */
#define CONFIG_SYS_NAND_USE_FLASH_BBT
/* Environment is in NAND */
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
#define CONFIG_ENV_RANGE (4 * CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_OFFSET_REDUND \
(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
-#define CONFIG_CMD_UBIFS
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_RBTREE
-#define CONFIG_LZO
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define MTDIDS_DEFAULT "nand0=mxc_nand"
"14m(boot)," \
"240m(data)," \
"-@2048k(UBI)"
-#else
-#define CONFIG_ENV_IS_NOWHERE
#endif
/*
/*
* Environment
*/
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
#define CONFIG_ENV_SIZE 0x4000
* USB
*/
#ifdef CONFIG_CMD_USB
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
/* USB device */
#define CONFIG_USB_ETHER
/*
* Environment
*/
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_ADDR \
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
/* Environment in SPI NOR flash */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
#define CONFIG_SYS_FLASH_BANKS_SIZES { (32 * SZ_1M) }
/* MTD support */
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_ENV_SIZE (SZ_128K)
/* Envs are stored in NOR flash */
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE (SZ_128K)
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
/* EHCI */
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_USB_ETHER_MCS7830
/* commands to include */
#define CONFIG_CMD_NAND /* NAND support */
-#define CONFIG_CMD_UBIFS
-#define CONFIG_RBTREE
-#define CONFIG_LZO
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_NAND_OMAP_GPMC_PREFETCH
-#define CONFIG_ENV_IS_IN_NAND
#define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */
/* Redundant Environment */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* Environment in NAND, aligned to start of last sector */
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sectors */
/* USB host support */
#ifdef CONFIG_SYS_USE_DATAFLASH
/* bootstrap + u-boot + env in dataflash on CS0 */
-# define CONFIG_ENV_IS_IN_DATAFLASH
# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \
0x8400)
# define CONFIG_ENV_OFFSET 0x4200
#elif CONFIG_SYS_USE_NANDFLASH
/* bootstrap + u-boot + env + linux in nandflash */
-# define CONFIG_ENV_IS_IN_NAND 1
# define CONFIG_ENV_OFFSET 0xC0000
# define CONFIG_ENV_SIZE 0x20000
#define CONFIG_CPU_ARMV8
#define CONFIG_REMAKE_ELF
-#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_NR_DRAM_BANKS 2
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_SYS_MAXARGS 32
#define CONFIG_SYS_MALLOC_LEN (32 << 20)
/* use buffered writes (20x faster) */
# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
# ifdef RAMENV
-# define CONFIG_ENV_IS_NOWHERE 1
# define CONFIG_ENV_SIZE 0x1000
# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
# else /* FLASH && !RAMENV */
-# define CONFIG_ENV_IS_IN_FLASH 1
/* 128K(one sector) for env */
# define CONFIG_ENV_SECT_SIZE 0x20000
# define CONFIG_ENV_ADDR \
# define CONFIG_SF_DEFAULT_CS XILINX_SPI_FLASH_CS
# ifdef RAMENV
-# define CONFIG_ENV_IS_NOWHERE 1
# define CONFIG_ENV_SIZE 0x1000
# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
# else /* SPIFLASH && !RAMENV */
-# define CONFIG_ENV_IS_IN_SPI_FLASH 1
# define CONFIG_ENV_SPI_MODE SPI_MODE_3
# define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
# define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
#else /* !SPIFLASH */
/* ENV in RAM */
-# define CONFIG_ENV_IS_NOWHERE 1
# define CONFIG_ENV_SIZE 0x1000
# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
#endif /* !SPIFLASH */
#define CONFIG_CMD_MFSL
#if defined(FLASH)
-# undef CONFIG_CMD_UBIFS
-
# if !defined(RAMENV)
# define CONFIG_CMD_SAVES
# endif
# if !defined(RAMENV)
# define CONFIG_CMD_SAVES
# endif
-#else
-# undef CONFIG_CMD_UBIFS
#endif
#endif
# define CONFIG_MTD_PARTITIONS
#endif
-#if defined(CONFIG_CMD_UBIFS)
-# define CONFIG_LZO
-#endif
-
#if defined(CONFIG_CMD_UBI)
# define CONFIG_MTD_PARTITIONS
-# define CONFIG_RBTREE
#endif
#if defined(CONFIG_MTD_PARTITIONS)
/* MTD partitions */
-#define CONFIG_CMD_MTDPARTS /* mtdparts command line support */
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT "nor0=flash-0"
#define CONFIG_SYS_MONITOR_LEN (1 << 20)
-#define CONFIG_SMSC_LPC47M
#define CONFIG_MISC_INIT_R
#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,serial\0" \
"stdout=vidconsole,serial\0" \
- "stderr=vidconsole,serial\0"
+ "stderr=vidconsole,serial\0" \
+ "usb_pgood_delay=40\0"
#define CONFIG_SCSI_DEV_LIST \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
#include <configs/rk3288_common.h>
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#endif
/*
* Environment
*/
-#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
#define CONFIG_SYS_MAX_FLASH_SECT 256
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#undef CONFIG_SYS_DIRECT_FLASH_TFTP
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_ENV_SECT_SIZE (8 * 1024)
#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
#undef CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
* File system
*/
#ifdef CONFIG_SYS_MVFS
-#define CONFIG_CMD_UBIFS
-#define CONFIG_RBTREE
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define CONFIG_MTD_PARTITIONS
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_LZO
#endif
#endif /* _MV_COMMON_H */
#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
/* Environment in SPI NOR flash */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET 0x180000 /* as Marvell U-Boot version */
#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
#define CONFIG_NET_RETRY_COUNT 50
#define CONFIG_PHY_MARVELL
-/* USB 2.0 */
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
-
-/* USB 3.0 */
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 3
-
-#define CONFIG_USB_MAX_CONTROLLER_COUNT (CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS + \
- CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS)
+#define CONFIG_USB_MAX_CONTROLLER_COUNT (3 + 3)
/* USB ethernet */
#define CONFIG_USB_HOST_ETHER
/* Environment in SPI NOR flash */
#ifdef CONFIG_MVEBU_SPI_BOOT
-#define CONFIG_ENV_IS_IN_SPI_FLASH
/* Environment in NAND flash */
-#elif defined(CONFIG_MVEBU_NAND_BOOT)
-#define CONFIG_ENV_IS_IN_NAND
#endif
#define CONFIG_ENV_OFFSET 0x180000 /* as Marvell U-Boot version */
#define CONFIG_ARP_TIMEOUT 200
#define CONFIG_NET_RETRY_COUNT 50
-/* USB 2.0 */
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
-
-/* USB 3.0 */
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 3
-
-#define CONFIG_USB_MAX_CONTROLLER_COUNT (CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS + \
- CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS)
+#define CONFIG_USB_MAX_CONTROLLER_COUNT (3 + 3)
/* USB ethernet */
#define CONFIG_USB_HOST_ETHER
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Environment */
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OVERWRITE
/* Environment is in MMC */
/* Environment */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_ENV_IS_IN_MMC
/* Environment is in MMC */
#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_ENV_SIZE (8 * 1024)
#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
/* U-Boot general configuration */
/* UBI and NAND partitioning */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_CMD_UBIFS
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_RBTREE
-#define CONFIG_LZO
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define MTDIDS_DEFAULT "nand0=gpmi-nand"
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256KiB */
-#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
/*
* JFFS2 partitions
*/
-#undef CONFIG_CMD_MTDPARTS
#define CONFIG_JFFS2_DEV "nor0"
#endif /* __CONFIG_H */
/*
* environment organization
*/
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x40000
#define CONFIG_ENV_OFFSET_REDUND 0x60000
#define CONFIG_ENV_SIZE (128 * 1024)
/*
* MTD Command for mtdparts
*/
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE
#define CONFIG_FLASH_CFI_MTD
#define CONFIG_MTD_PARTITIONS
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_IS_IN_FLASH
-
#if defined(CONFIG_FSL_ENV_IN_NAND)
- #define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET (1024 * 1024)
#endif
#define CONFIG_SYS_NAND_LARGEPAGE
/* EHCI driver */
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
#define CONFIG_EHCI_IS_TDI
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_EHCI_MXC
*/
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
#define CONFIG_ENV_SIZE (8 * 1024)
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#endif
/* environment organization */
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
#define CONFIG_ENV_SIZE (8 * 1024)
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define MX53ARD_CS1GCR1 (CSEN | DSZ(2))
#define CONFIG_SYS_TEXT_BASE 0x77800000
#define CONFIG_EXTRA_ENV_SETTINGS \
- "fdt_addr=0x71ff0000\0" \
- "rdaddr=0x72000000\0" \
+ "fdt_addr_r=0x71ff0000\0" \
+ "pxefile_addr_r=0x73000000\0" \
+ "ramdisk_addr_r=0x72000000\0" \
"console=ttymxc1,115200\0" \
"uenv=/boot/uEnv.txt\0" \
"optargs=\0" \
"rootfstype=${mmcrootfstype} " \
"${cmdline}\0" \
"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
- "loadrd=load mmc ${bootpart} ${rdaddr} ${bootdir}/${rdfile};" \
+ "loadpxe=dhcp;setenv kernel_addr_r ${loadaddr};pxe get;pxe boot;\0" \
+ "loadrd=load mmc ${bootpart} ${ramdisk_addr_r} ${bootdir}/${rdfile};" \
"setenv rdsize ${filesize}\0" \
"loadfdt=echo loading ${fdt_path} ...;" \
- "load mmc ${bootpart} ${fdt_addr} ${fdt_path}\0" \
+ "load mmc ${bootpart} ${fdt_addr_r} ${fdt_path}\0" \
"mmcboot=mmc dev ${mmcdev}; " \
"if mmc rescan; then " \
"echo SD/MMC found on device ${mmcdev};" \
"fi;" \
"run mmcargs;" \
"echo debug: [${bootargs}] ... ;" \
- "echo debug: [bootz ${loadaddr} - ${fdt_addr}] ... ;" \
- "bootz ${loadaddr} - ${fdt_addr}; " \
+ "echo debug: [bootz ${loadaddr} - ${fdt_addr_r}];" \
+ "bootz ${loadaddr} - ${fdt_addr_r}; " \
+ "else " \
+ "echo loading from dhcp ...; " \
+ "run loadpxe; " \
"fi;\0"
#define CONFIG_BOOTCOMMAND \
/* environment organization */
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
#define CONFIG_ENV_SIZE (8 * 1024)
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
/* Framebuffer and LCD */
/* environment organization */
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
#define CONFIG_ENV_SIZE (8 * 1024)
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#endif /* __CONFIG_H */
/* environment organization */
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
#define CONFIG_ENV_SIZE (8 * 1024)
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#ifdef CONFIG_CMD_SATA
/* environment organization */
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
#define CONFIG_ENV_SIZE (8 * 1024)
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#endif /* __CONFIG_H */
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/gpio.h>
+#include <asm/mach-imx/gpio.h>
#ifndef CONFIG_MX6
#define CONFIG_MX6
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+/* SATA Configuration */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_DWC_AHSATA
+#define CONFIG_SYS_SATA_MAX_DEVICE 1
+#define CONFIG_DWC_AHSATA_PORT_ID 0
+#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#define CONFIG_LIBATA
+#endif
+
/* Ethernet Configuration */
#define CONFIG_FEC_MXC
#define CONFIG_MII
"console=" CONSOLE_DEV ",115200\0" \
"bootm_size=0x10000000\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+ "finduuid=part uuid mmc 0:1 uuid\0" \
"update_sd_firmware=" \
"if test ${ip_dyn} = yes; then " \
"setenv get_cmd dhcp; " \
#define CONFIG_BOOTCOMMAND \
"run findfdt; " \
+ "run finduuid; " \
"run distro_bootcmd"
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
+ func(SATA, sata, 0) \
func(USB, usb, 0) \
func(PXE, pxe, na) \
func(DHCP, dhcp, na)
/* Environment organization */
#define CONFIG_ENV_SIZE (8 * 1024)
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (8 * 64 * 1024)
#endif /* __MX6CUBOXI_CONFIG_H */
/* Environment organization */
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
#define CONFIG_ENV_SIZE (8 * 1024)
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1
/* USB Configs */
+++ /dev/null
-/*
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
- *
- * Configuration settings for the Freescale i.MX6Q SabreAuto board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __MX6QSABREAUTO_CONFIG_H
-#define __MX6QSABREAUTO_CONFIG_H
-
-#define CONFIG_MACH_TYPE 3529
-#define CONFIG_MXC_UART_BASE UART4_BASE
-#define CONSOLE_DEV "ttymxc3"
-#define CONFIG_MMCROOT "/dev/mmcblk0p2"
-
-/* USB Configs */
-#define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_ASIX
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
-#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CONFIG_MXC_USB_FLAGS 0
-
-#define CONFIG_PCA953X
-#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} }
-
-#include "mx6sabre_common.h"
-
-#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
-#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024)
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
-#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-#if defined(CONFIG_ENV_IS_IN_MMC)
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#endif
-
-/* I2C Configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_SPEED 100000
-
-/* NAND flash command */
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NAND_TRIMFFS
-
-/* NAND stuff */
-#define CONFIG_NAND_MXS
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE 0x40000000
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-/* DMA stuff, needed for GPMI/MXS NAND support */
-#define CONFIG_APBH_DMA
-#define CONFIG_APBH_DMA_BURST
-#define CONFIG_APBH_DMA_BURST8
-
-/* PMIC */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_PFUZE100
-#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
-
-#endif /* __MX6QSABREAUTO_CONFIG_H */
"initrd_high=0xffffffff\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"mmcpart=1\0" \
- "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+ "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
"update_sd_firmware=" \
"if test ${ip_dyn} = yes; then " \
"setenv get_cmd dhcp; " \
"fi\0" \
EMMC_ENV \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
- "root=${mmcroot}\0" \
+ "root=PARTUUID=${uuid} rootwait rw\0" \
"loadbootscript=" \
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"mmcboot=echo Booting from mmc ...; " \
+ "run finduuid; " \
"run mmcargs; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if run loadfdt; then " \
/* Environment organization */
#define CONFIG_ENV_SIZE (8 * 1024)
-#define CONFIG_ENV_IS_IN_MMC
-
#if defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_ENV_OFFSET (768 * 1024)
#endif
--- /dev/null
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6Q SabreAuto board.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __MX6SABREAUTO_CONFIG_H
+#define __MX6SABREAUTO_CONFIG_H
+
+#ifdef CONFIG_SPL
+#include "imx6_spl.h"
+#endif
+
+#define CONFIG_MACH_TYPE 3529
+#define CONFIG_MXC_UART_BASE UART4_BASE
+#define CONSOLE_DEV "ttymxc3"
+
+/* USB Configs */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+
+#define CONFIG_PCA953X
+#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} }
+
+#include "mx6sabre_common.h"
+
+/* Falcon Mode */
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
+#define CONFIG_CMD_SPL
+#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000
+#define CONFIG_CMD_SPL_WRITE_SIZE (128 * SZ_1K)
+
+/* Falcon Mode - MMC support: args@1MB kernel@2MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512)
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */
+#endif
+
+#ifdef CONFIG_MTD_NOR_FLASH
+#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
+#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024)
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
+#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#endif
+
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#endif
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* NAND flash command */
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_TRIMFFS
+
+/* NAND stuff */
+#define CONFIG_NAND_MXS
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* DMA stuff, needed for GPMI/MXS NAND support */
+#define CONFIG_APBH_DMA
+#define CONFIG_APBH_DMA_BURST
+#define CONFIG_APBH_DMA_BURST8
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
+
+#endif /* __MX6SABREAUTO_CONFIG_H */
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __MX6QSABRESD_CONFIG_H
-#define __MX6QSABRESD_CONFIG_H
+#ifndef __MX6SABRESD_CONFIG_H
+#define __MX6SABRESD_CONFIG_H
#ifdef CONFIG_SPL
#include "imx6_spl.h"
#define CONFIG_MACH_TYPE 3980
#define CONFIG_MXC_UART_BASE UART1_BASE
#define CONSOLE_DEV "ttymxc0"
-#define CONFIG_MMCROOT "/dev/mmcblk1p2"
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */
#endif
-#endif /* __MX6QSABRESD_CONFIG_H */
+#endif /* __MX6SABRESD_CONFIG_H */
#define CONFIG_ENV_SIZE SZ_8K
#if defined CONFIG_SPI_BOOT
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET (768 * 1024)
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
#else
#define CONFIG_ENV_OFFSET (8 * SZ_64K)
-#define CONFIG_ENV_IS_IN_MMC
#endif
#ifdef CONFIG_CMD_SF
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
#define CONFIG_ENV_OFFSET (12 * SZ_64K)
-#define CONFIG_ENV_IS_IN_MMC
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
#define CONFIG_ENV_OFFSET (8 * SZ_64K)
#define CONFIG_ENV_SIZE SZ_8K
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_FSL_USDHC_NUM 2
#if defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_ENV_OFFSET (8 * SZ_64K)
#define CONFIG_ENV_SIZE SZ_8K
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_FSL_USDHC_NUM 3
#if defined(CONFIG_ENV_IS_IN_MMC)
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
#include "mx6_common.h"
-#include <asm/imx-common/gpio.h>
+#include <asm/mach-imx/gpio.h>
#define is_mx6ul_9x9_evk() CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK)
/* environment organization */
#define CONFIG_ENV_SIZE SZ_8K
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (8 * SZ_64K)
#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
#include "mx6_common.h"
-#include <asm/imx-common/gpio.h>
+#include <asm/mach-imx/gpio.h>
#ifdef CONFIG_SECURE_BOOT
#ifndef CONFIG_CSF_SIZE
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_SIZE SZ_8K
#define CONFIG_ENV_OFFSET (12 * SZ_64K)
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/gpio.h>
+#include <asm/mach-imx/gpio.h>
#ifndef CONFIG_MX7
#define CONFIG_MX7
/* environment organization */
#define CONFIG_ENV_SIZE SZ_8K
-#define CONFIG_ENV_IS_IN_MMC
/*
* If want to use nand, define CONFIG_NAND_MXS and rework board
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
#define CONFIG_ENV_OFFSET (12 * SZ_64K)
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_SIZE SZ_8K
/* Using ULP WDOG for reset */
* Environment variables configurations
*/
#ifdef CONFIG_CMD_NAND
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SECT_SIZE 0x10000
-#else
-#define CONFIG_ENV_IS_NOWHERE
#endif
#define CONFIG_ENV_SIZE 0x10000
*/
#define CONFIG_JFFS2_NAND
#define CONFIG_JFFS2_LZO
-#define CONFIG_CMD_UBIFS
-#define CONFIG_RBTREE
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define CONFIG_MTD_PARTITIONS
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_LZO
/*
* SATA
#include <configs/bmips_common.h>
#include <configs/bmips_bcm3380.h>
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE (8 * 1024)
#define CONFIG_AUTO_COMPLETE
/* Environment organization */
#define CONFIG_ENV_SIZE (8 * 1024)
-#if defined(CONFIG_SABRELITE)
-#define CONFIG_ENV_IS_IN_MMC
-#else
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#endif
-
#if defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
#define CONFIG_SYS_MMC_ENV_DEV 0
#ifdef ONENAND_SUPPORT
#define CONFIG_CMD_ONENAND /* ONENAND support */
-#define CONFIG_CMD_MTDPARTS /* mtd parts support */
-
-#ifdef UBIFS_SUPPORT
-#define CONFIG_CMD_UBIFS /* UBIFS Support */
-#endif
#endif
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
-#ifdef UBIFS_SUPPORT
-#define CONFIG_RBTREE
-#define CONFIG_LZO
-#endif
-
#define MTDIDS_DEFAULT "onenand0=onenand"
#define MTDPARTS_DEFAULT "mtdparts=onenand:" \
__stringify(PART1_SIZE) PART1_SUFF "(" PART1_NAME ")ro," \
* FLASH and environment organization
*/
-#define CONFIG_ENV_IS_NOWHERE
-
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
* http://homepage.ntlworld.com./jonathan.deboynepollard/FGA/disc-partition-alignment.html
*/
#ifdef CONFIG_CMD_MMC
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_OFFSET (512 * 1024)
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
#define CONFIG_ENV_OFFSET_REDUND \
(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#else
-#define CONFIG_ENV_IS_NOWHERE
#endif
/* Booting Linux */
/* environment variables configuration */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SECT_SIZE 0x20000
-#else
-#define CONFIG_ENV_IS_NOWHERE
#endif
#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_ENV_OFFSET 0xe0000
/*
* Environment settings
*/
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE SZ_512
#define CONFIG_ENV_OFFSET 0
#define CONFIG_SYS_I2C_TEGRA
/* Environment in eMMC, at the end of 2nd "boot sector" */
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MONITOR_BASE 0x00000000
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV
#define CONFIG_ENV_SIZE 4096
#define CONFIG_ENV_OFFSET (SZ_1K * 1280) /* 1.25 MiB offset */
/* USB */
#define CONFIG_USB_EHCI_EXYNOS
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_SMSC95XX
#include "exynos5420-common.h"
#include <configs/exynos5-common.h>
-#undef CONFIG_ENV_IS_IN_SPI_FLASH
-
#define CONFIG_BOARD_COMMON
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_SYS_MEM_TOP_HIDE (22UL << 20UL)
#define CONFIG_TZSW_RESERVED_DRAM_SIZE CONFIG_SYS_MEM_TOP_HIDE
-#define CONFIG_ENV_IS_IN_MMC
-
#undef CONFIG_ENV_SIZE
#undef CONFIG_ENV_OFFSET
#define CONFIG_ENV_SIZE (SZ_1K * 16)
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_USB_ETHER_MCS7830
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
-#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
-#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
#if !defined(CONFIG_ENV_IS_NOWHERE)
#if defined(CONFIG_CMD_NAND)
-#define CONFIG_ENV_IS_IN_NAND
#elif defined(CONFIG_CMD_ONENAND)
-#define CONFIG_ENV_IS_IN_ONENAND
#define CONFIG_ENV_OFFSET ONENAND_ENV_OFFSET
#endif
#endif /* CONFIG_ENV_IS_NOWHERE */
#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
#define CONFIG_USBD_PRODUCT_NAME "IGEP"
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_ONENAND
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SMC911X_BASE 0x2C000000
#endif /* (CONFIG_CMD_NET) */
-#define CONFIG_RBTREE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_SYS_MTDPARTS_RUNTIME
#define CONFIG_SPL_UBI_INFO_ADDR 0x88080000
/* environment organization */
-#define CONFIG_ENV_IS_NOWHERE 1
#define CONFIG_ENV_UBI_PART "UBI"
#define CONFIG_ENV_UBI_VOLUME "config"
#define CONFIG_ENV_UBI_VOLUME_REDUND "config_r"
/* commands to include */
#define CONFIG_CMD_NAND
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
/* I2C */
#ifdef CONFIG_NAND
#define CONFIG_NAND_OMAP_GPMC
-#define CONFIG_CMD_UBIFS /* Read-only UBI volume operations */
-#define CONFIG_RBTREE /* required by CONFIG_CMD_UBI */
-#define CONFIG_LZO /* required by CONFIG_CMD_UBIFS */
-
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
/* to access nand */
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
/* USB EHCI */
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 183
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
/* commands to include */
#ifdef CONFIG_NAND
-#define CONFIG_CMD_UBIFS /* Read-only UBI volume operations */
-
-#define CONFIG_RBTREE /* required by CONFIG_CMD_UBI */
-#define CONFIG_LZO /* required by CONFIG_CMD_UBIFS */
-
#define CONFIG_MTD_PARTITIONS /* required for UBI partition support */
/* NAND block size is 128 KiB. Synchronize these values with
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
-#define CONFIG_ENV_IS_IN_NAND
#define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */
#define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */
#define CONFIG_SYS_NAND_OOBSIZE 64
#ifdef CONFIG_NAND
-#define CONFIG_CMD_UBIFS /* Read-only UBI volume operations */
-
-#define CONFIG_RBTREE /* required by CONFIG_CMD_UBI */
-#define CONFIG_LZO /* required by CONFIG_CMD_UBIFS */
-
#define CONFIG_MTD_PARTITIONS /* required for UBI partition support */
#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_ENV_IS_IN_NAND 1
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
-#define CONFIG_ENV_IS_IN_NAND 1
#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
*/
/* USB UHH support options */
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
-
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 1
#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 62
/* ENV related config options */
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-#define CONFIG_ENV_IS_IN_FAT
#define FAT_ENV_INTERFACE "mmc"
#define FAT_ENV_DEVICE_AND_PART "0:1"
#define FAT_ENV_FILE "uboot.env"
#include <configs/ti_omap4_common.h>
/* ENV related config options */
-#define CONFIG_ENV_IS_IN_MMC 1
#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
#define CONFIG_ENV_OFFSET 0xE0000
#define CONFIG_MISC_INIT_R
/* MMC ENV related defines */
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
#define CONFIG_ENV_SIZE (128 << 10)
#define CONFIG_ENV_OFFSET 0x260000
#define CONFIG_SYS_I2C_TCA642X_ADDR 0x22
/* USB UHH support options */
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 80
* Flash & Environment
*/
#ifdef CONFIG_USE_NAND
-#undef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_NAND_DAVINCI
-#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
#define CONFIG_ENV_SIZE (128 << 9)
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#endif
#ifdef CONFIG_SYS_USE_NOR
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#endif
#ifdef CONFIG_USE_SPIFLASH
-#undef CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE (64 << 10)
#define CONFIG_ENV_OFFSET (256 << 10)
#define CONFIG_ENV_SECT_SIZE (64 << 10)
#ifdef CONFIG_USE_NAND
#define CONFIG_CMD_NAND
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
-#define CONFIG_LZO
-#define CONFIG_RBTREE
-#define CONFIG_CMD_UBIFS
#endif
#if !defined(CONFIG_USE_NAND) && \
!defined(CONFIG_SYS_USE_NOR) && \
!defined(CONFIG_USE_SPIFLASH)
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE (16 << 10)
#endif
/* SD/MMC */
-#ifdef CONFIG_MMC
-#undef CONFIG_ENV_IS_IN_MMC
-#endif
#ifdef CONFIG_ENV_IS_IN_MMC
#undef CONFIG_ENV_SIZE
#undef CONFIG_ENV_OFFSET
#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
#define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */
-#undef CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_IN_NAND
-#undef CONFIG_ENV_IS_IN_SPI_FLASH
#endif
#ifndef CONFIG_DIRECT_NOR_BOOT
* Environment variables configurations
*/
#ifdef CONFIG_CMD_NAND
-#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
-#else
-#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
#endif
/*
* max 4k env size is enough, but in case of nand
#endif
/* Environment is stored in the eMMC boot partition */
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 1
#define CONFIG_ENV_SIZE (10 * 1024)
/* MIU (Memory Interleaving Unit) */
#define CONFIG_MIU_2BIT_21_7_INTERLEAVED
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
#define RESERVE_BLOCK_SIZE (512)
#define CONFIG_PREBOOT ""
+/* Thermal support */
+#define CONFIG_IMX_THERMAL
+
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* Environment organization */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE (64 * 1024) /* 64 kb */
#define CONFIG_ENV_OFFSET (1024 * 1024)
/* M25P16 has an erase size of 64 KiB */
*/
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT "nor0=ec000000.nor"
#define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:128k(dtb),6016k(kernel)," \
*/
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_FLASH_CFI_MTD
#ifdef CONFIG_PHYS_64BIT
#define MTDIDS_DEFAULT "nor0=fef000000.nor"
*/
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_FLASH_CFI_MTD
#ifdef CONFIG_PHYS_64BIT
#define MTDIDS_DEFAULT "nor0=fef000000.nor"
* Environment
*/
#ifdef CONFIG_SPIFLASH
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 10000000
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
#define CONFIG_ENV_SECT_SIZE 0x10000
#elif defined(CONFIG_SDCARD)
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_FSL_FIXED_MMC_LOCATION
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_SYS_MMC_ENV_DEV 0
#else
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#endif
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET (1024 * 1024)
#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
#elif defined(CONFIG_SYS_RAMBOOT)
-#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#else
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
*/
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT "nor0=ec000000.nor"
#define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:256k(vsc7385-firmware)," \
*/
#ifdef CONFIG_SYS_RAMBOOT
#ifdef CONFIG_RAMBOOT_SDCARD
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_SYS_MMC_ENV_DEV 0
#else
-#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#endif
#else
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#define CONFIG_SYS_I2C_TEGRA
/* Environment in eMMC, at the end of 2nd "boot sector" */
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_I2C_TEGRA
/* Environment in eMMC, at the end of 2nd "boot sector" */
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_I2C_TEGRA
/* Environment in eMMC, at the end of 2nd "boot sector" */
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_I2C_TEGRA
/* Environment in eMMC, at the end of 2nd "boot sector" */
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_MACH_TYPE MACH_TYPE_PAZ00
/* Environment in eMMC, at the end of 2nd "boot sector" */
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
-#define CONFIG_ENV_IS_NOWHERE 1
-
/* Address and size of Primary Environment Sector */
#define CONFIG_ENV_ADDR 0xB0030000
#define CONFIG_ENV_SIZE 0x10000
4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 }
/* CPU */
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
#define CONFIG_JFFS2_NAND
-/* UBI */
-#define CONFIG_CMD_UBIFS
-#define CONFIG_RBTREE
-#define CONFIG_LZO
-
/* Dynamic MTD partition support */
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
#define CONFIG_APBH_DMA_BURST8
/* Filesystem support */
-#define CONFIG_LZO
-#define CONFIG_CMD_UBIFS
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
#define MTDIDS_DEFAULT "nand0=nand"
#define MTDPARTS_DEFAULT "mtdparts=nand:16m(uboot),1m(env),-(rootfs)"
-/* Various command support */
-#define CONFIG_RBTREE
-
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_FSL_USDHC_NUM 1
/* Environment organization */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE (16 * 1024)
#define CONFIG_ENV_OFFSET (1024 * SZ_1K)
#define CONFIG_ENV_SECT_SIZE (64 * SZ_1K)
/* #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 */
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
-#define CONFIG_CMD_MTDPARTS
-
#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
/* Size must be a multiple of Nand erase size (524288 b) */
#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(SPL)," \
"512k(SPL.backup3),1536k(u-boot)," \
"512k(u-boot-spl-os)," \
"512k(u-boot-env),5m(kernel),-(rootfs)"
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
/* NAND: SPL falcon mode configs */
#define CONFIG_MACH_TYPE MACH_TYPE_PEPPER
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
func(MMC, mmc, 0) \
func(MMC, mmc, 1)
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1
#endif
/* -------------------------------------------------
* Environment
*/
-#define CONFIG_ENV_IS_NOWHERE 1
#define CONFIG_ENV_SIZE 0x4000
/* ---------------------------------------------------------------------
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
#include "mx6_common.h"
-#include <asm/imx-common/gpio.h>
+#include <asm/mach-imx/gpio.h>
/* Network support */
/* environment organization */
#define CONFIG_ENV_SIZE SZ_8K
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (8 * SZ_64K)
#define CONFIG_SYS_MMC_ENV_DEV 0
/* FLASH and environment organization */
#define CONFIG_ENV_SIZE SZ_8K
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (8 * SZ_64K)
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_RESET_PHY_R
#define CONFIG_AT91_WANTS_COMMON_PHY
-/* USB */
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
-
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
*/
#define FAT_ENV_DEVICE_AND_PART "0"
#define FAT_ENV_FILE "uboot.env"
-#define CONFIG_ENV_IS_IN_FAT
#define CONFIG_ENV_SIZE 0x4000
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
* Console configuration
*/
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NAND_TRIMFFS
-#define CONFIG_CMD_UBIFS
/*
* Hardware configuration
#define CONFIG_APBH_DMA_BURST8
/* Environment in NAND */
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET (16 << 20)
#define CONFIG_ENV_SECT_SIZE (128 << 10)
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
/* Environment in MMC */
#define CONFIG_ENV_SIZE (8 << 10)
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
#define CONFIG_SYS_MMC_ENV_DEV 0
sizeof(CONFIG_SYS_PROMPT) + 16)
/* MTD/UBI/UBIFS config */
-#define CONFIG_LZO
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
-#define CONFIG_RBTREE
#if (CONFIG_SYS_NAND_MAX_CHIPS == 1)
#define MTDIDS_DEFAULT "nand0=gpmi-nand"
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* Environment in NAND, aligned to start of last sector */
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sectors */
/* USB host support */
#ifdef CONFIG_SYS_USE_DATAFLASH_CS0
/* bootstrap + u-boot + env + linux in dataflash on CS0 */
-#define CONFIG_ENV_IS_IN_DATAFLASH 1
#define CONFIG_SYS_MONITOR_BASE \
(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
#define CONFIG_ENV_OFFSET 0x4200
#elif defined(CONFIG_SYS_USE_NANDFLASH) /* CONFIG_SYS_USE_NANDFLASH */
/* bootstrap + u-boot + env + linux in nandflash */
-#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_OFFSET 0x60000
#define CONFIG_ENV_OFFSET_REDUND 0x80000
#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
#elif defined (CONFIG_SYS_USE_FLASH)
-#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_OFFSET 0x40000
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_SIZE 0x10000
#ifdef CONFIG_SYS_USE_DATAFLASH
/* bootstrap + u-boot + env + linux in dataflash on CS0 */
-#define CONFIG_ENV_IS_IN_DATAFLASH
#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
#define CONFIG_ENV_OFFSET 0x4200
#define CONFIG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
#elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */
/* bootstrap + u-boot + env + linux in nandflash */
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x60000
#define CONFIG_ENV_OFFSET_REDUND 0x80000
#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
#elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */
-#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_OFFSET 0x40000
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_SIZE 0x10000
#define CONFIG_SYS_MEMTEST_END CONFIG_AT91SAM9G45_LCD_BASE
/* bootstrap + u-boot + env + linux in nandflash */
-#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_OFFSET 0x60000
#define CONFIG_ENV_OFFSET_REDUND 0x80000
#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
* Environment variables configurations
*/
#ifdef CONFIG_CMD_NAND
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
-#else
-#define CONFIG_ENV_IS_NOWHERE
#endif
#define CONFIG_ENV_SIZE 0x20000 /* 128k */
/*
* File system
*/
-#define CONFIG_CMD_UBIFS
-#define CONFIG_RBTREE
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define CONFIG_MTD_PARTITIONS
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_LZO
#endif /* _CONFIG_POGO_E02_H */
#define CONFIG_PL01X_SERIAL
/* USB configuration */
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_USB_EVENT_POLL
#define CONFIG_USB_HOST_ETHER
/* Command line configuration */
-#define CONFIG_ENV_IS_IN_MMC 1
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_OFFSET (0x780 * 512) /* env_mmc_blknum */
#define CONFIG_ENV_SIZE 0x10000 /* env_mmc_nblks bytes */
#define ROCKCHIP_DEVICE_SETTINGS
#include <configs/rk3288_common.h>
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#endif
#undef CONFIG_ENV_OFFSET
#define CONFIG_ENV_OFFSET (240 * 1024)
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1
#define SDRAM_BANK_SIZE (2UL << 30)
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_ENV_IS_IN_FLASH
-
/* Address and size of Primary Environment Sector */
#define CONFIG_ENV_SIZE 0x8000
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (4 << 20) - CONFIG_ENV_SIZE)
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_ENV_IS_IN_FLASH
-
/* Address and size of Primary Environment Sector */
#define CONFIG_ENV_SIZE 0x8000
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (4 << 20) - CONFIG_ENV_SIZE)
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_ENV_IS_NOWHERE
-
#define CONFIG_HWCONFIG
#define CONFIG_SYS_INIT_RAM_ADDR 0x00100000
#undef CONFIG_INTEL_ICH6_GPIO
/* SPI is not supported */
-#undef CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* ENV setting */
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
#define CONFIG_SYS_MAX_FLASH_SECT 256
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE 0x40000
#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
/* print 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE (256 * 1024)
#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* ENV setting */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_ADDR 0xC0000
/* Common ENV setting */
#include "rockchip-common.h"
#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_MALLOC_LEN (32 << 20)
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
-/* xhci host */
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#endif
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
#if defined(CONFIG_SPL_SPI_SUPPORT)
#define CONFIG_SPL_SPI_LOAD
#endif
#define CONFIG_USB_ETHER_SMSC95XX
#define CONFIG_USB_ETHER_RTL8152
-/* rockchip xhci host driver */
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
-
#endif
#define ROCKCHIP_DEVICE_SETTINGS
#include <configs/rk3188_common.h>
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
#include <configs/rk3288_common.h>
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#endif
#endif
#define CONFIG_RANDOM_UUID
+
+#ifdef CONFIG_ARM64
+#define ROOT_UUID "B921B045-1DF0-41C3-AF44-4C6F280D3FAE;\0"
+#else
+#define ROOT_UUID "69DAD710-2CE4-4E3C-B16C-21A1D49ABED3;\0"
+#endif
#define PARTS_DEFAULT \
"uuid_disk=${uuid_gpt_disk};" \
"name=loader1,start=32K,size=4000K,uuid=${uuid_gpt_loader1};" \
"name=loader2,size=4MB,uuid=${uuid_gpt_loader2};" \
"name=atf,size=4M,uuid=${uuid_gpt_atf};" \
"name=boot,size=112M,bootable,uuid=${uuid_gpt_boot};" \
- "name=rootfs,size=-,uuid=${uuid_gpt_rootfs};\0" \
+ "name=rootfs,size=-,uuid="ROOT_UUID
#endif
/* Environment */
#define CONFIG_ENV_SIZE SZ_16K
-#define CONFIG_ENV_IS_IN_FAT
#define FAT_ENV_INTERFACE "mmc"
#define FAT_ENV_DEVICE_AND_PART "0:1"
#define FAT_ENV_FILE "uboot.env"
#define CONFIG_SYS_MAX_FLASH_SECT 64
#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 512
-#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_OFFSET (128 * 1024)
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 512
-#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_OFFSET (128 * 1024)
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
#include <asm/arch/hardware.h>
#include "rockchip-common.h"
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_MALLOC_LEN (32 << 20)
/* environment organization */
#define CONFIG_ENV_SIZE (8 * 1024)
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (12 * 64 * 1024)
#define CONFIG_SYS_MMC_ENV_DEV 0
/* PWM */
#define CONFIG_PWM 1
-#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_ONENAND
/* USB Composite download gadget - g_dnl */
/* FLASH and environment organization */
#define CONFIG_MMC_DEFAULT_DEV 0
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV
#define CONFIG_ENV_SIZE 4096
#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */
#define CONFIG_BOOTBLOCK "10"
#define CONFIG_UBIBLOCK "9"
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV
#define CONFIG_ENV_SIZE 4096
#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */
#include <configs/bmips_common.h>
#include <configs/bmips_bcm6338.h>
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE (8 * 1024)
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SH_SDHI_FREQ 200000000
/* Environment in eMMC, at the end of 2nd "boot sector" */
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 1
#define CONFIG_SYS_MMC_ENV_PART 2
/* USB */
#define CONFIG_CMD_USB
-#ifdef CONFIG_CMD_USB
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
-#endif
-
/* USB device */
#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_DUALSPEED
#undef CONFIG_ENV_OFFSET_REDUND
#undef CONFIG_BOOTCOMMAND
/* u-boot env in nand flash */
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x200000
#define CONFIG_ENV_OFFSET_REDUND 0x400000
#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0xb80000 0x80000;" \
#define CONFIG_PMECC_CAP 4
#define CONFIG_PMECC_SECTOR_SIZE 512
#define CONFIG_CMD_NAND_TRIMFFS
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
-#define CONFIG_RBTREE
-#define CONFIG_LZO
-#define CONFIG_CMD_UBIFS
#endif
/* USB */
/* override the bootcmd, bootargs and other configuration for nandflash env */
#elif CONFIG_SYS_USE_MMC
/* override the bootcmd, bootargs and other configuration for sd/mmc env */
-#else
-#define CONFIG_ENV_IS_NOWHERE
#endif
/* SPL */
/* override the bootcmd, bootargs and other configuration nandflash env */
#elif CONFIG_SYS_USE_MMC
/* override the bootcmd, bootargs and other configuration for sd/mmc env */
-#else
-#define CONFIG_ENV_IS_NOWHERE
#endif
/* SPL */
#define CONFIG_AUTO_COMPLETE
#define CONFIG_ENV_SIZE 8192
-#define CONFIG_ENV_IS_NOWHERE
/* SPI - enable all SPI flash types for testing purposes */
#define CONFIG_CMD_SF_TEST
#define CONFIG_GZIP_COMPRESSED
#define CONFIG_BZIP2
-#define CONFIG_LZO
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_IDE_MAXBUS 1
/* Environment */
#define CONFIG_ENV_SIZE (16 * 1024)
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_OVERWRITE
/* Booting Linux */
* Environment
*/
#ifndef CONFIG_SYS_RAMBOOT
- #define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#else
- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#endif
/*
* Environment
*/
-#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SIZE 0x2000
#if CONFIG_SYS_TEXT_BASE == 0xfff00000 /* Boot from 64MB SODIMM */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x80000)
/*
* Environment
*/
-#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k(one sector) for env */
#define CONFIG_ENV_SIZE 0x2000
/* Environment */
#define CONFIG_ENV_SIZE (16 * 1024)
-#define CONFIG_ENV_IS_IN_MMC
/* Environment is in MMC */
#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_ENV_OFFSET (256 * 1024)
#define CONFIG_SYS_MMC_ENV_DEV 0
-#else
-#define CONFIG_ENV_IS_NOWHERE
#endif
/* FEC Ethernet on SoC */
#define CONFIG_SYS_I2C_TEGRA
/* Environment in eMMC, at the end of 2nd "boot sector" */
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_REMAKE_ELF
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE (8 * 1024)
#define CONFIG_AUTO_COMPLETE
/* ENV setting */
#define CONFIG_ENV_IS_EMBEDDED
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
#define CONFIG_ENV_ADDR (0x00080000)
#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
/* ENV setting */
#define CONFIG_ENV_IS_EMBEDDED
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
#define CONFIG_ENV_ADDR (0x00080000)
#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
/* ENV setting */
#define CONFIG_ENV_IS_EMBEDDED
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
#define CONFIG_ENV_ADDR (0x00080000)
#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
/* Use hardware flash sectors protection instead of U-Boot software protection */
#undef CONFIG_SYS_FLASH_PROTECTION
#undef CONFIG_SYS_DIRECT_FLASH_TFTP
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
/* ENV setting */
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_ENV_SECT_SIZE (256 * 1024)
#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
#define KERNEL_LOAD_ADDR 0x280000
#define DTB_LOAD_ADDR 0x5600000
#define INITRD_LOAD_ADDR 0x5bf0000
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_CONSOLE_SCROLL_LINES 10
* Environment variables configurations
*/
#ifdef CONFIG_CMD_NAND
-#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
-#else
-#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
#endif
/*
* max 4k env size is enough, but in case of nand
#define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7}
#define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000}
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
#endif
#define CONFIG_ENV_OVERWRITE 1
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING
* 0x442000 - 0x800000 : Userland
*/
#if defined(CONFIG_SPI_BOOT)
-# undef CONFIG_ENV_IS_NOWHERE
-# define CONFIG_ENV_IS_IN_SPI_FLASH
# define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
# define CONFIG_ENV_OFFSET (892 << 10) /* 892 KiB in */
# define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */
/* UBI Support */
#ifndef CONFIG_SPL_BUILD
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
-#define CONFIG_RBTREE
-#define CONFIG_LZO
-#define CONFIG_CMD_UBIFS
#endif
/* Commen environment */
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND
devices */
#if !defined(CONFIG_SPI_BOOT)
-#undef CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
#endif
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE
#define MTDIDS_NAME_STR "atmel_nand"
#define MTDIDS_DEFAULT "nand0=" MTDIDS_NAME_STR
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
/* USB DFU support */
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
/*
* The NAND Flash partitions:
*/
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET (0x100000)
#define CONFIG_ENV_OFFSET_REDUND (0x180000)
#define CONFIG_ENV_RANGE (SZ_512K)
***********************************************************/
#undef CONFIG_CMD_NAND
-#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_ONENAND
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
/*-----------------------------------------------------------------------
* Boot configuration
*/
-#define CONFIG_ENV_IS_IN_ONENAND 1
#define CONFIG_ENV_SIZE (128 << 10) /* 128KiB, 0x20000 */
#define CONFIG_ENV_ADDR (256 << 10) /* 256KiB, 0x40000 */
#define CONFIG_ENV_OFFSET (256 << 10) /* 256KiB, 0x40000 */
/* MIU (Memory Interleaving Unit) */
#define CONFIG_MIU_2BIT_INTERLEAVED
-#define CONFIG_ENV_IS_IN_MMC 1
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
#define RESERVE_BLOCK_SIZE (512)
#define CONFIG_BOOTP_HOSTNAME
/* Environment settings */
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET (512 << 10)
#define CONFIG_ENV_SIZE (256 << 10)
#define CONFIG_ENV_OVERWRITE
#define CONFIG_TFTP_PORT
#define CONFIG_TFTP_TSIZE
-/* USB */
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
-
/* MMC */
#define CONFIG_GENERIC_ATMEL_MCI
#define CONFIG_BOOTP_HOSTNAME
/* Environment settings */
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET (512 << 10)
#define CONFIG_ENV_SIZE (256 << 10)
#define CONFIG_ENV_OVERWRITE
*/
#define CONFIG_ENV_SIZE (128 * 1024)
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_OVERWRITE
/*
* U-Boot environment configurations
*/
-#define CONFIG_ENV_IS_IN_MMC
/*
* arguments passed to the bootz command. The value of
#define CONFIG_PHY_MICREL_KSZ9021
#endif
-#define CONFIG_ENV_IS_IN_MMC
-
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
/*
* FPGA Driver
*/
-#ifdef CONFIG_TARGET_SOCFPGA_GEN5
#ifdef CONFIG_CMD_FPGA
-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA
-#define CONFIG_FPGA_SOCFPGA
#define CONFIG_FPGA_COUNT 1
#endif
-#endif
+
/*
* L4 OSC1 Timer 0
*/
/* Enable multiple SPI NOR flash manufacturers */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SPI_FLASH_MTD
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define MTDIDS_DEFAULT "nor0=ff705000.spi.0"
"-@1536k(UBI)\0"
#endif
-/* UBI and UBIFS support */
-#if defined(CONFIG_CMD_SF) || defined(CONFIG_CMD_NAND)
-#define CONFIG_CMD_UBIFS
-#define CONFIG_RBTREE
-#define CONFIG_LZO
-#endif
-
/*
* SPL
*
#define CONFIG_PHY_MICREL_KSZ9021
#endif
-#define CONFIG_ENV_IS_IN_MMC
-
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
#define CONFIG_PHY_MICREL_KSZ9031
#endif
-#define CONFIG_ENV_IS_IN_MMC
-
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
#define CONFIG_PHY_MICREL_KSZ9031
#endif
-#define CONFIG_ENV_IS_IN_MMC
-
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
#define CONFIG_PHY_MICREL_KSZ9021
#endif
-#define CONFIG_ENV_IS_IN_MMC
-
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_ENV_IS_IN_SPI_FLASH
/* Ethernet on SoC (EMAC) */
#if defined(CONFIG_CMD_NET)
/* Environment is in MMC */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_ENV_IS_IN_MMC
/* Extra Environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CONFIG_PHY_MICREL_KSZ9021
#endif
-#define CONFIG_ENV_IS_IN_MMC
-
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
#define CONFIG_PHY_MICREL_KSZ9021
#endif
-#define CONFIG_ENV_IS_IN_MMC
-
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
#define PHY_ANEG_TIMEOUT 8000
/* Environment */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
/* Enable SPI NOR flash reset, needed for SPI booting */
#define CONFIG_SPI_N25Q256A_RESET
"else echo \"Unsupported boot mode: \"${bootmode} ; " \
"fi\0" \
-#define CONFIG_CMD_UBIFS
-#define CONFIG_RBTREE
-#define CONFIG_LZO
#define MTDPARTS_DEFAULT \
"mtdparts=ff705000.spi.0:" \
"1m(u-boot)," \
"256k(samtec2)," \
"-(rcvrfs);" /* Recovery */ \
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
/*
* Environment
*/
-#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x4000
#define CONFIG_SPEAR_USBTTY
#endif
-#if defined(CONFIG_NAND)
-#define CONFIG_ENV_IS_IN_NAND
-#else
-#define CONFIG_ENV_IS_IN_FLASH
-#endif
-
#include <configs/spear-common.h>
/* Ethernet driver configuration */
#define CONFIG_SPEAR_USBTTY
#endif
-#if defined(CONFIG_NAND)
-#define CONFIG_ENV_IS_IN_NAND
-#else
-#define CONFIG_ENV_IS_IN_FLASH
-#endif
-
#include <configs/spear-common.h>
/* Serial Configuration (PL011) */
"board= B2260" \
"load_addr= #CONFIG_SYS_LOAD_ADDR \0"
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE 0x4000
/* Extra Commands */
#define CONFIG_SYS_MAX_FLASH_SECT 12
#define CONFIG_SYS_MAX_FLASH_BANKS 2
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OFFSET (256 << 10)
#define CONFIG_ENV_SECT_SIZE (128 << 10)
#define CONFIG_ENV_SIZE (8 << 10)
#define CONFIG_SYS_MAX_FLASH_SECT 8
#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE (8 << 10)
#define CONFIG_STM32_FLASH
* Environment
*/
#if 1
-#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
#else
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#endif
#define PHYS_SDRAM_1_SIZE 0x00198000
#define CONFIG_ENV_SIZE 0x10000
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
#define CONFIG_ENV_OFFSET 0x30000
#define CONFIG_ENV_ADDR \
#define CONFIG_USB_OHCI_NEW
#define CONFIG_USB_OHCI_SUNXI
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
#endif
#ifdef CONFIG_USB_MUSB_SUNXI
115200}
/* EHCI */
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
/* commands to include */
#define CONFIG_CMD_NAND /* NAND support */
/* **** PISMO SUPPORT *** */
#define CONFIG_NAND
#define CONFIG_NAND_OMAP_GPMC
-#define CONFIG_ENV_IS_IN_NAND
#define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */
/* Redundant Environment */
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
-#define CONFIG_CMD_UBIFS
-#define CONFIG_RBTREE
-#define CONFIG_LZO
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
-#define CONFIG_CMD_MTDPARTS
/* Setup MTD for NAND on the SOM */
#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
#define CONFIG_ENV_OVERWRITE
/* commands to include */
-#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define MTDIDS_DEFAULT "nand0=nand"
#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
-#define CONFIG_ENV_IS_IN_NAND 1
#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
/* USB EHCI */
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_SMSC95XX
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
/* USB DFU support */
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_SYS_LOAD_ADDR 0x22000000
/* bootstrap in spi flash , u-boot + env + linux in nandflash */
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x100000
#define CONFIG_ENV_OFFSET_REDUND 0x180000
#define CONFIG_ENV_SIZE (SZ_128K) /* 1 sector = 128 kB */
/*
* Environment settings
*/
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE SZ_2K
#define CONFIG_ENV_OFFSET 0
#endif
/* Environment organization */
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 2 /* overwritten on SD boot */
#define CONFIG_SYS_MMC_ENV_PART 1 /* overwritten on SD boot */
#define CONFIG_ENV_SIZE (8 * 1024)
#define CONFIG_SYS_I2C_TEGRA
/* Environment in eMMC, at the end of 2nd "boot sector" */
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* Environment in NAND, aligned to start of last sector */
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sectors */
/* USB host support */
/* For USB EHCI controller */
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
#endif /* _TEGRA114_COMMON_H_ */
/* For USB EHCI controller */
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
/* GPU needs setup */
#define CONFIG_TEGRA_GPU
*/
#define CONFIG_USB_EHCI_TXFIFO_THRESH 10
#define CONFIG_EHCI_IS_TDI
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
#define CONFIG_SYS_NAND_SELF_INIT
#define CONFIG_SYS_NAND_ONFI_DETECTION
/* For USB EHCI controller */
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
/* GPU needs setup */
#define CONFIG_TEGRA_GPU
/* For USB EHCI controller */
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
#endif /* _TEGRA30_COMMON_H_ */
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
/* Environment in SPI NOR flash */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
#define CONFIG_SYS_MEM_TOP_HIDE 0x80000
/* FPGA programming support */
-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA
#define CONFIG_FPGA_STRATIX_V
/*
"root=/dev/sda2 coherent_pool=16M"
/* Do not preserve environment */
-#define CONFIG_ENV_IS_NOWHERE 1
#define CONFIG_ENV_SIZE 0x1000
/* Monitor Command Prompt */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
-#define CONFIG_ENV_IS_NOWHERE
-
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x40300000
"8m(NAND.kernel)," \
"-(NAND.file-system)"
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x001c0000
#define CONFIG_ENV_OFFSET_REDUND 0x001e0000
#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define DEFAULT_FIT_TI_ARGS \
"boot_fit=0\0" \
- "fit_loadaddr=0x88000000\0" \
+ "fit_loadaddr=0x87000000\0" \
"fit_bootfile=fitImage\0" \
"update_to_fit=setenv loadaddr ${fit_loadaddr}; setenv bootfile ${fit_bootfile}\0" \
"loadfit=run args_mmc; bootm ${loadaddr}#${fdtfile};\0" \
*/
#if defined(CONFIG_SPI_BOOT) || defined(CONFIG_NOR) || defined(CONFIG_NAND) || defined(CONFIG_NAND_DAVINCI)
#define CONFIG_MTD_DEVICE /* Required for mtdparts */
-#define CONFIG_CMD_MTDPARTS
#endif
#define CONFIG_SUPPORT_RAW_INITRD
#define CONFIG_SYS_NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
#define CONFIG_MTD_PARTITIONS
-#define CONFIG_RBTREE
-#define CONFIG_LZO
#define MTDIDS_DEFAULT "nand0=davinci_nand.0"
#define MTDPARTS_DEFAULT "mtdparts=davinci_nand.0:" \
"1024k(bootloader)ro,512k(params)ro," \
/* USB Configuration */
#define CONFIG_USB_XHCI_KEYSTONE
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#define CONFIG_USB_SS_BASE KS2_USB_SS_BASE
#define CONFIG_USB_HOST_XHCI_BASE KS2_USB_HOST_XHCI_BASE
#define CONFIG_DEV_USB_PHY_BASE KS2_DEV_USB_PHY_BASE
/* U-Boot command configuration */
#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_UBIFS
/* U-Boot general configuration */
#define CONFIG_MISC_INIT_R
"addr_secdb_key=0xc000000\0" \
"name_kern=zImage\0" \
"addr_mon=0x87000000\0" \
+ "addr_non_sec_mon=0x0c087fc0\0" \
+ "addr_load_sec_bm=0x0c08c000\0" \
"run_mon=mon_install ${addr_mon}\0" \
+ "run_mon_hs=mon_install ${addr_non_sec_mon} " \
+ "${addr_load_sec_bm}\0" \
"run_kern=bootz ${loadaddr} ${rd_spec} ${fdtaddr}\0" \
"init_net=run args_all args_net\0" \
"init_nfs=setenv autoload no; dhcp; run args_all args_net\0" \
"get_kern_ubi=ubifsload ${loadaddr} ${bootdir}/${name_kern}\0" \
"get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \
"get_mon_nfs=nfs ${addr_mon} ${nfs_root}/boot/${name_mon}\0" \
- "get_mon_ubi=ubifsload ${addr_mon} ${bootdir}/${name_mon}\0" \
+ "get_mon_ubi=ubifsload ${addr_mon} ${bootdir}/${name_mon}\0" \
+ "get_fit_net=dhcp ${fit_loadaddr} ${tftp_root}" \
+ "/${fit_bootfile}\0" \
+ "get_fit_nfs=nfs ${fit_loadaddr} ${nfs_root}/boot/${fit_bootfile}\0"\
+ "get_fit_ubi=ubifsload ${fit_loadaddr} ${bootdir}/${fit_bootfile}\0"\
+ "get_fit_mmc=load mmc ${bootpart} ${fit_loadaddr} " \
+ "${bootdir}/${fit_bootfile}\0" \
"get_uboot_net=dhcp ${loadaddr} ${tftp_root}/${name_uboot}\0" \
"get_uboot_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_uboot}\0" \
"burn_uboot_spi=sf probe; sf erase 0 0x80000; " \
"get_fdt_ramfs=dhcp ${fdtaddr} ${tftp_root}/${name_fdt}\0" \
"get_kern_ramfs=dhcp ${loadaddr} ${tftp_root}/${name_kern}\0" \
"get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \
+ "get_fit_ramfs=dhcp ${fit_loadaddr} ${tftp_root}" \
+ "/${fit_bootfile}\0" \
"get_fs_ramfs=dhcp ${rdaddr} ${tftp_root}/${name_fs}\0" \
"get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}\0" \
"get_ubi_nfs=nfs ${addr_ubi} ${nfs_root}/boot/${name_ubi}\0" \
"1024k(bootloader)ro,512k(params)ro,-(ubifs)\0"
#ifndef CONFIG_BOOTCOMMAND
+#ifndef CONFIG_TI_SECURE_DEVICE
#define CONFIG_BOOTCOMMAND \
- "run init_${boot} get_mon_${boot} run_mon init_fw_rd_${boot} " \
- "get_fdt_${boot} get_kern_${boot} run_kern"
+ "run init_${boot}; " \
+ "run get_mon_${boot} run_mon; " \
+ "run get_kern_${boot}; " \
+ "run init_fw_rd_${boot}; " \
+ "run get_fdt_${boot}; " \
+ "run run_kern"
+#else
+#define CONFIG_BOOTCOMMAND \
+ "run run_mon_hs; " \
+ "run init_${boot}; " \
+ "run get_fit_${boot}; " \
+ "bootm ${fit_loadaddr}#${name_fdt}"
+#endif
#endif
#define CONFIG_BOOTARGS \
func(PXE, pxe, na) \
func(DHCP, dchp, na)
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1
#endif
#define CONFIG_APBH_DMA_BURST8
/* Environment in NAND */
-#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET (16 << 20)
#define CONFIG_ENV_SECT_SIZE (128 << 10)
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
/* Environment in MMC */
#define CONFIG_ENV_SIZE (8 << 10)
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
#define CONFIG_SYS_MMC_ENV_DEV 0
#endif /* CONFIG_CMD_NAND */
/* UBI/UBIFS config options */
-#define CONFIG_LZO
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
-#define CONFIG_RBTREE
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_UBIFS
#endif /* __CONFIG_H */
#define CONFIG_ZYNQ_I2C1
/* Speed up boot time by ignoring the environment which we never used */
-#define CONFIG_ENV_IS_NOWHERE
#include "zynq-common.h"
#define CONFIG_BOOTCOMMAND \
"dhcp 192.168.1.1:wdr4300.fit && bootm $loadaddr"
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE 0x10000
/*
#if defined(CONFIG_TQMA6X_MMC_BOOT)
-#define CONFIG_ENV_IS_IN_MMC
#define TQMA6_UBOOT_OFFSET SZ_1K
#define TQMA6_UBOOT_SECTOR_START 0x2
#define TQMA6_UBOOT_SECTOR_COUNT 0x7fe
#define TQMA6_UBOOT_SIZE (TQMA6_UBOOT_SECTOR_SIZE * \
TQMA6_UBOOT_SECTOR_COUNT)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_OFFSET (TQMA6_UBOOT_SIZE)
#define CONFIG_ENV_SECT_SIZE TQMA6_SPI_FLASH_SECTOR_SIZE
#define CONFIG_BOOTBLOCK "10"
#define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}"
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV
#define CONFIG_ENV_SIZE 4096
#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */
#define CONFIG_SYS_MONITOR_BASE 0x00000000
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV
#define CONFIG_ENV_SIZE 4096
#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */
#define CONFIG_SYS_NAND_MAX_ECCPOS 56
/* commands to include */
-#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
#define CONFIG_CMD_NAND /* NAND support */
#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
-#define CONFIG_CMD_UBIFS /* UBIFS commands */
-#define CONFIG_LZO /* LZO is needed for UBIFS */
/* needed for ubi */
-#define CONFIG_RBTREE
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define CONFIG_MTD_PARTITIONS
* which will not be influenced by any data already on the device.
*/
#ifdef CONFIG_FLASHCARD
-
-#define CONFIG_ENV_IS_NOWHERE
-
/* the rdaddr is 16 MiB before the loadaddr */
#define CONFIG_ENV_RDADDR "rdaddr=0x81000000\0"
#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_IS_IN_NAND
-
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_COMMON_ENV_SETTINGS \
"mmcargs=" \
#define CONFIG_SYS_I2C_TEGRA
/* Environment in SPI */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_MAX_HZ 48000000
#define CONFIG_ENV_SPI_MODE SPI_MODE_0
#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
#define CONFIG_ENV_SIZE (8 * 1024)
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#endif
--- /dev/null
+/*
+ * Copyright (C) 2017 Marek Behun <marek.behun@nic.cz>
+ * Copyright (C) 2016 Tomas Hlavacek <tomas.hlavacek@nic.cz>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CONFIG_TURRIS_OMNIA_H
+#define _CONFIG_TURRIS_OMNIA_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+
+#define CONFIG_MISC_INIT_R
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+/*
+ * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
+ * for DDR ECC byte filling in the SPL before loading the main
+ * U-Boot into it.
+ */
+#define CONFIG_SYS_TEXT_BASE 0x00800000
+#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_CMD_PCI
+
+/* I2C support */
+#define CONFIG_DM_I2C
+#define CONFIG_I2C_MUX
+#define CONFIG_I2C_MUX_PCA954x
+#define CONFIG_SPL_I2C_MUX
+#define CONFIG_SYS_I2C_MVTWSI
+
+/* Watchdog support */
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT_ORION)
+# define CONFIG_WATCHDOG
+#endif
+
+/* SPI NOR flash default params, used by sf commands */
+#define CONFIG_SF_DEFAULT_SPEED 1000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+
+/*
+ * SDIO/MMC Card Configuration
+ */
+#define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE
+
+/*
+ * SATA/SCSI/AHCI configuration
+ */
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
+#define CONFIG_SYS_SCSI_MAX_LUN 1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+ CONFIG_SYS_SCSI_MAX_LUN)
+
+/* Additional FS support/configuration */
+#define CONFIG_SUPPORT_VFAT
+
+/* USB/EHCI configuration */
+#define CONFIG_EHCI_IS_TDI
+
+/* Environment in SPI NOR flash */
+#define CONFIG_ENV_OFFSET (3*(1 << 18)) /* 768KiB in */
+#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
+#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
+
+#define CONFIG_PHY_MARVELL /* there is a marvell phy */
+#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
+
+/* PCIe support */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_PCI_MVEBU
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
+#define CONFIG_SYS_ALT_MEMTEST
+
+/* Keep device tree and initrd in lower memory so the kernel can access them */
+#define RELOCATION_LIMITS_ENV_SETTINGS \
+ "fdt_high=0x10000000\0" \
+ "initrd_high=0x10000000\0"
+
+/* Defines for SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_SIZE (140 << 10)
+#define CONFIG_SPL_TEXT_BASE 0x40000030
+#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030)
+
+#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
+#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
+
+#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
+#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+
+#ifdef CONFIG_TURRIS_OMNIA_SPL_BOOT_DEVICE_SPI
+/* SPL related SPI defines */
+# define CONFIG_SPL_SPI_LOAD
+# define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
+# define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
+#endif
+
+#ifdef CONFIG_TURRIS_OMNIA_SPL_BOOT_DEVICE_MMC
+/* SPL related MMC defines */
+# define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10)
+# define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS
+# ifdef CONFIG_SPL_BUILD
+# define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
+# endif
+#endif
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/* Include the common distro boot environment */
+#ifndef CONFIG_SPL_BUILD
+#include <config_distro_defaults.h>
+
+#ifdef CONFIG_MMC
+#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
+#else
+#define BOOT_TARGET_DEVICES_MMC(func)
+#endif
+
+#ifdef CONFIG_USB_STORAGE
+#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
+#else
+#define BOOT_TARGET_DEVICES_USB(func)
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+ BOOT_TARGET_DEVICES_MMC(func) \
+ BOOT_TARGET_DEVICES_USB(func) \
+ func(PXE, pxe, na) \
+ func(DHCP, dhcp, na)
+
+#define KERNEL_ADDR_R __stringify(0x1000000)
+#define FDT_ADDR_R __stringify(0x2000000)
+#define RAMDISK_ADDR_R __stringify(0x2200000)
+#define SCRIPT_ADDR_R __stringify(0x1800000)
+#define PXEFILE_ADDR_R __stringify(0x1900000)
+
+#define LOAD_ADDRESS_ENV_SETTINGS \
+ "kernel_addr_r=" KERNEL_ADDR_R "\0" \
+ "fdt_addr_r=" FDT_ADDR_R "\0" \
+ "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \
+ "scriptaddr=" SCRIPT_ADDR_R "\0" \
+ "pxefile_addr_r=" PXEFILE_ADDR_R "\0"
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ RELOCATION_LIMITS_ENV_SETTINGS \
+ LOAD_ADDRESS_ENV_SETTINGS \
+ "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
+ "console=ttyS0,115200\0" \
+ BOOTENV
+
+#endif /* CONFIG_SPL_BUILD */
+
+#endif /* _CONFIG_TURRIS_OMNIA_H */
/* Environment organization */
#define CONFIG_ENV_SIZE (8 * 1024)
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
#define CONFIG_SYS_MMC_ENV_DEV 0
/* Environment organization */
#define CONFIG_ENV_OFFSET (8 * SZ_64K)
#define CONFIG_ENV_SIZE SZ_8K
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_IMX_THERMAL
#define CONFIG_CONS_INDEX 1
-/* #define CONFIG_ENV_IS_NOWHERE */
-/* #define CONFIG_ENV_IS_IN_NAND */
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET 0x100000
#define CONFIG_ENV_SIZE 0x2000
/* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 1
-#ifdef CONFIG_ARMV8_MULTIENTRY
-#define CPU_RELEASE_ADDR 0x80000000
-#define COUNTER_FREQUENCY 50000000
-#define CONFIG_GICV3
-#define GICD_BASE 0x5fe00000
-#if defined(CONFIG_ARCH_UNIPHIER_LD11)
-#define GICR_BASE 0x5fe40000
-#elif defined(CONFIG_ARCH_UNIPHIER_LD20)
-#define GICR_BASE 0x5fe80000
-#endif
-#elif !defined(CONFIG_ARM64)
+#if !defined(CONFIG_ARM64)
/* Time clock 1MHz */
#define CONFIG_SYS_TIMER_RATE 1000000
#endif
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
-/* USB */
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4
-
/* SD/MMC */
#define CONFIG_SUPPORT_EMMC_BOOT
#define CONFIG_CMDLINE_EDITING /* add command line history */
-#if defined(CONFIG_ARM64) && !defined(CONFIG_ARMV8_MULTIENTRY)
+#if defined(CONFIG_ARM64)
/* ARM Trusted Firmware */
#define BOOT_IMAGES \
"second_image=unph_bl.bin\0" \
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE)
/* only for SPL */
-#if defined(CONFIG_ARM64)
-#define CONFIG_SPL_TEXT_BASE 0x30000000
-#elif defined(CONFIG_ARCH_UNIPHIER_SLD3) || \
+#if defined(CONFIG_ARCH_UNIPHIER_SLD3) || \
defined(CONFIG_ARCH_UNIPHIER_LD4) || \
defined(CONFIG_ARCH_UNIPHIER_SLD8)
#define CONFIG_SPL_TEXT_BASE 0x00040000
#define CONFIG_SPL_TEXT_BASE 0x00100000
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_LD11)
-#define CONFIG_SPL_STACK (0x30014c00)
-#elif defined(CONFIG_ARCH_UNIPHIER_LD20)
-#define CONFIG_SPL_STACK (0x3001c000)
-#else
#define CONFIG_SPL_STACK (0x00100000)
-#endif
#define CONFIG_SPL_FRAMEWORK
-#ifdef CONFIG_ARM64
-#define CONFIG_SPL_BOARD_LOAD_IMAGE
-#endif
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_MAX_FOOTPRINT 0x10000
-#if defined(CONFIG_ARCH_UNIPHIER_LD20)
-#define CONFIG_SPL_MAX_SIZE 0x14000
-#else
#define CONFIG_SPL_MAX_SIZE 0x10000
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_LD11)
-#define CONFIG_SPL_BSS_START_ADDR 0x30012000
-#elif defined(CONFIG_ARCH_UNIPHIER_LD20)
-#define CONFIG_SPL_BSS_START_ADDR 0x30016000
-#endif
#define CONFIG_SPL_BSS_MAX_SIZE 0x2000
#define CONFIG_SPL_PAD_TO 0x20000
#define CONFIG_SYS_MEMTEST_END 0x23e00000
/* bootstrap + u-boot + env in dataflash on CS0 */
-#define CONFIG_ENV_IS_IN_DATAFLASH
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x4000)
#define CONFIG_ENV_OFFSET 0x2000
#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \
/* U-Boot environment */
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
#define CONFIG_ENV_SIZE (8 * 1024)
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
/* U-Boot general configurations */
* FLASH and environment organization
*/
#if defined(CONFIG_VCT_NOR)
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_FLASH_NOT_MEM_MAPPED
/*
#if defined(CONFIG_VCT_ONENAND)
#define CONFIG_USE_ONENAND_BOARD_INIT
-#define CONFIG_ENV_IS_IN_ONENAND
#define CONFIG_SYS_ONENAND_BASE 0x00000000 /* this is not real address */
#define CONFIG_SYS_FLASH_BASE 0x00000000
#define CONFIG_ENV_ADDR (128 << 10) /* after compr. U-Boot image */
* UBI configuration
*/
#if defined(CONFIG_VCT_ONENAND)
-#define CONFIG_SYS_USE_UBI
-#define CONFIG_RBTREE
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define CONFIG_MTD_PARTITIONS
-#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT "onenand0=onenand"
#define MTDPARTS_DEFAULT "mtdparts=onenand:128k(u-boot)," \
* (NOR/OneNAND) usage and Linux kernel booting.
*/
#if defined(CONFIG_VCT_SMALL_IMAGE)
-#undef CONFIG_CMD_REGINFO
#undef CONFIG_CMD_STRINGS
#undef CONFIG_CMD_TERMINAL
/*
* Environment
*/
-#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR \
(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
#define CONFIG_SYS_I2C_TEGRA
/* Environment in eMMC, at the end of 2nd "boot sector" */
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_MACH_TYPE MACH_TYPE_VENTANA
/* Environment in eMMC, at the end of 2nd "boot sector" */
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
#define FLASH_MAX_SECTOR_SIZE 0x00040000
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_IS_IN_FLASH 1
#endif /* __VEXPRESS_AEMV8A_H */
#define CONFIG_ENV_OVERWRITE 1
/* Store environment at top of flash */
-#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_OFFSET (PHYS_FLASH_SIZE - \
(2 * CONFIG_ENV_SECT_SIZE))
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE1 + \
#include <configs/rk3288_common.h>
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SPI_FLASH_GIGADEVICE
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
-/* UBI */
-#define CONFIG_CMD_UBIFS
-#define CONFIG_RBTREE
-#define CONFIG_LZO
-
/* Dynamic MTD partition support */
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
#define MTDIDS_DEFAULT "nand0=fsl_nfc"
#endif
-/* USB */
-
-#ifdef CONFIG_CMD_USB
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
-#endif
-
/* USB device */
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETH_RNDIS
#define CONFIG_ENV_SIZE SZ_8K
#define CONFIG_ENV_OFFSET_REDUND (9 * SZ_64K)
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-#define CONFIG_ENV_IS_IN_MMC
#ifdef CONFIG_ENV_IS_IN_MMC
#define CONFIG_SUPPORT_EMMC_BOOT
* Environment
*/
#ifndef CONFIG_SYS_RAMBOOT
- #define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000)
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#else
- #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#endif
"fdt_addr=0x18000000\0" \
"ip_dyn=yes\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+ "finduuid=part uuid mmc 0:1 uuid\0" \
"update_sd_firmware_filename=u-boot.imx\0" \
"update_sd_firmware=" \
"if test ${ip_dyn} = yes; then " \
#define CONFIG_BOOTCOMMAND \
"run findfdt; " \
+ "run finduuid; " \
"run distro_bootcmd"
#include <config_distro_bootcmd.h>
/* Environment organization */
#define CONFIG_ENV_SIZE (8 * 1024)
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (768 * 1024)
#define CONFIG_SYS_MMC_ENV_DEV 0
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
-#define CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
#define CONFIG_SUPPORT_EMMC_BOOT
#define CONFIG_ENV_OFFSET (6 * SZ_64K)
#define CONFIG_ENV_SIZE SZ_8K
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
/* VDD voltage 1.65 - 1.95 */
"ip_dyn=yes\0" \
"mmcdev=0\0" \
"mmcpart=1\0" \
- "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+ "finduuid=part uuid mmc 0:2 uuid\0" \
"dfu_alt_info=boot raw 0x2 0x400 mmcpart 1\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
- "root=${mmcroot}\0" \
+ "root=PARTUUID=${uuid} rootwait rw\0" \
"loadbootscript=" \
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"mmcboot=echo Booting from mmc ...; " \
+ "run finduuid; " \
"run mmcargs; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if run loadfdt; then " \
/* environment organization */
#define CONFIG_ENV_SIZE SZ_8K
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (8 * SZ_64K)
#define CONFIG_SYS_FSL_USDHC_NUM 1
/*
* MTD Command for mtdparts
*/
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE
#define CONFIG_FLASH_CFI_MTD
#define CONFIG_MTD_PARTITIONS
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_IS_IN_FLASH
-
/*
* CFI FLASH driver setup
*/
* Environment
*/
-#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_SIZE 0x00020000
#define CONFIG_ENV_OFFSET 0x00100000
#define CONFIG_ENV_OFFSET_REDUND 0x00120000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN 0x60000
-#define CONFIG_ENV_IS_IN_FLASH
-
/* Serial Configuration (PL011) */
#define CONFIG_SYS_SERIAL0 0xD0000000
#define CONFIG_SYS_SERIAL1 0xD0080000
/* UBI/UBI config options */
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
-#define CONFIG_RBTREE
/* Ethernet config options */
#define CONFIG_MII
/*
* Command support defines
*/
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_NAND
#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_UBIFS
-#define CONFIG_LZO
/* Filesystem support (for USB key) */
#define CONFIG_SUPPORT_VFAT
#define VIDEO_IO_OFFSET 0
#define CONFIG_X86EMU_RAW_IO
-#undef CONFIG_ENV_IS_NOWHERE
#undef CONFIG_ENV_SIZE
#define CONFIG_ENV_SIZE 0x1000
#define CONFIG_ENV_SECT_SIZE 0x1000
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET 0x003f8000
#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \
#define CONFIG_LMB
-#define CONFIG_LZO
#undef CONFIG_ZLIB
#undef CONFIG_GZIP
#define CONFIG_SYS_BOOTM_LEN (16 << 20)
/*-----------------------------------------------------------------------
* Environment configuration
*/
-#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE 0x01000
/*-----------------------------------------------------------------------
* USB configuration
*/
#define CONFIG_USB_EHCI_PCI
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 12
#define CONFIG_SYS_USB_EVENT_POLL
#define CONFIG_USB_HOST_ETHER
/* Environment */
#define CONFIG_ENV_SIZE (16 * 1024)
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_OVERWRITE
/* Booting Linux */
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
- * This work has been supported by: QTechnology http://qtec.com/
- *
- * (C) Copyright 2008
- * Georg Schardt <schardt@team-ctech.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
-*/
-
-#ifndef __CONFIG_XLX_H
-#define __CONFIG_XLX_H
-
-/*
-#define DEBUG
-#define ET_DEBUG
-*/
-
-/*Mem Map*/
-#define CONFIG_SYS_SDRAM_BASE 0x0
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (192 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
-
-/*Cmd*/
-#define CONFIG_CMD_REGINFO
-#undef CONFIG_CMD_MTDPARTS
-
-/*Misc*/
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256/* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE +\
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16
- /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
- /* Boot Argument Buffer Size */
-#define CONFIG_SYS_MEMTEST_START 0x00400000
- /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00C00000
- /* 4 ... 12 MB in DRAM */
-#define CONFIG_SYS_LOAD_ADDR 0x00400000
- /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1
- /* Extended board_into (bd_t) */
- /* decrementer freq: 1 ms ticks */
-#define CONFIG_CMDLINE_EDITING /* add command line history */
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
-#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
- /* Initial Memory map for Linux */
-
-/*Stack*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0x800000/* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
- - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-/*Speed*/
-#define CONFIG_SYS_CLK_FREQ XPAR_CORE_CLOCK_FREQ_HZ
-
-/*Flash*/
-#ifdef XPAR_FLASH_MEM0_BASEADDR
-#define CONFIG_SYS_FLASH_BASE XPAR_FLASH_MEM0_BASEADDR
-#define CONFIG_SYS_FLASH_CFI 1
-#define CONFIG_FLASH_CFI_DRIVER 1
-#define CONFIG_SYS_FLASH_EMPTY_INFO 1
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
-#define CONFIG_FLASH_CFI_MTD
-#else
-#define CONFIG_ENV_IS_NOWHERE
-#endif
-
-/* The following table includes the supported baudrates */
-# define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-
-#endif /* __CONFIG_H */
# ifndef CONFIG_ZYNQ_SDHCI_MAX_FREQ
# define CONFIG_ZYNQ_SDHCI_MAX_FREQ 200000000
# endif
-# define CONFIG_ENV_IS_IN_FAT
# define FAT_ENV_DEVICE_AND_PART "0:auto"
# define FAT_ENV_FILE "uboot.env"
# define FAT_ENV_INTERFACE "mmc"
#define CONFIG_SYS_LOAD_ADDR 0x8000000
#if defined(CONFIG_ZYNQMP_USB)
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
-
#define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x1800000
#define DFU_DEFAULT_POLL_TIMEOUT 300
#define CONFIG_USB_CABLE_CHECK
#endif
/* Do not preserve environment */
-#if !defined(CONFIG_ENV_IS_IN_FAT)
-#define CONFIG_ENV_IS_NOWHERE 1
-#endif
#define CONFIG_ENV_SIZE 0x8000
/* Monitor Command Prompt */
/*
* Environment Configuration
*/
-#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
#define CONFIG_ENV_SIZE 0x8000
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
/*
* Environment Configuration
*/
-#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
#define CONFIG_ENV_SIZE 0x8000
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
/*
* Environment Configuration
*/
-#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
#define CONFIG_ENV_SIZE 0x8000
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
/*
* Environment Configuration
*/
-#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
#define CONFIG_ENV_SIZE 0x8000
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
#define __XPRESS_CONFIG_H
#include "mx6_common.h"
-#include <asm/imx-common/gpio.h>
+#include <asm/mach-imx/gpio.h>
/* SPL options */
#include "imx6_spl.h"
/* Environment is in stored in the eMMC boot partition */
#define CONFIG_ENV_SIZE (16 << 10)
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (512 << 10)
#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC2 */
#define CONFIG_SYS_MMC_ENV_PART 1 /* boot parition */
* Put environment in top block (64kB)
* Another option would be to put env. in 2nd param block offs 8KB, size 8KB
*/
-#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SIZE - CONFIG_SYS_FLASH_SECT_SZ)
#define CONFIG_ENV_SIZE CONFIG_SYS_FLASH_SECT_SZ
* Environment settings
*/
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR 0x40000
#define CONFIG_ENV_SIZE 0x10000
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
-/*
- * Compressions
- */
-#define CONFIG_LZO
-
/*
* Hardware drivers
*/
#define CONFIG_SYS_MAX_FLASH_SECT 256
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
-#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
#define CONFIG_ENV_SIZE (128 * 1024)
#ifndef CONFIG_ENV_IS_NOWHERE
# ifdef CONFIG_MTD_NOR_FLASH
/* Environment in NOR flash */
-# define CONFIG_ENV_IS_IN_FLASH
# elif defined(CONFIG_ZYNQ_QSPI)
/* Environment in Serial Flash */
-# define CONFIG_ENV_IS_IN_SPI_FLASH
-# elif !defined(CONFIG_MTD_NOR_FLASH)
-# define CONFIG_ENV_IS_NOWHERE
# endif
# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
struct sf_internal_data sf;
} data;
- long (*get_medium_size)(struct dfu_entity *dfu);
+ int (*get_medium_size)(struct dfu_entity *dfu, u64 *size);
int (*read_medium)(struct dfu_entity *dfu,
u64 offset, void *buf, long *len);
u8 *i_buf;
u8 *i_buf_start;
u8 *i_buf_end;
- long r_left;
+ u64 r_left;
long b_left;
u32 bad_skip; /* for nand use */
const char *list_name, const char *cells_name,
int index, struct of_phandle_args *out_args);
+/**
+ * of_count_phandle_with_args() - Count the number of phandle in a list
+ *
+ * @np: pointer to a device tree node containing a list
+ * @list_name: property name that contains a list
+ * @cells_name: property name that specifies phandles' arguments count
+ * @return number of phandle found, -ENOENT if
+ * @list_name does not exist, -EINVAL if a phandle was not found,
+ * @cells_name could not be found, the arguments were truncated or there
+ * were too many arguments.
+ *
+ * Returns number of phandle found on success, on error returns appropriate
+ * errno value.
+ *
+ */
+int of_count_phandle_with_args(const struct device_node *np,
+ const char *list_name, const char *cells_name);
+
/**
* of_alias_scan() - Scan all properties of the 'aliases' node
*
/* Enable checks to protect against invalid calls */
#undef OF_CHECKS
+struct resource;
+
/**
* ofnode - reference to a device tree node
*
int index,
struct ofnode_phandle_args *out_args);
+/**
+ * ofnode_count_phandle_with_args() - Count number of phandle in a list
+ *
+ * This function is useful to count phandles into a list.
+ * Returns number of phandle on success, on error returns appropriate
+ * errno value.
+ *
+ * @node: device tree node containing a list
+ * @list_name: property name that contains a list
+ * @cells_name: property name that specifies phandles' arguments count
+ * @return number of phandle on success, -ENOENT if @list_name does not
+ * exist, -EINVAL if a phandle was not found, @cells_name could not
+ * be found.
+ */
+int ofnode_count_phandle_with_args(ofnode node, const char *list_name,
+ const char *cells_name);
+
/**
* ofnode_path() - find a node by full path
*
*/
bool ofnode_pre_reloc(ofnode node);
+int ofnode_read_resource(ofnode node, uint index, struct resource *res);
+
#endif
+++ /dev/null
-/*
- * (C) Copyright 2016
- * Vikas Manocha, <vikas.manocha@st.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __SERIAL_STM32x7_H
-#define __SERIAL_STM32x7_H
-
-/* Information about a serial port */
-struct stm32x7_serial_platdata {
- struct stm32_usart *base; /* address of registers in physical memory */
- unsigned int clock;
-};
-
-#endif /* __SERIAL_STM32x7_H */
return ofnode_valid(dev_ofnode(dev));
}
-/**
- * dev_read_resource() - obtain an indexed resource from a device.
- *
- * @dev: devuce to examine
- * @index index of the resource to retrieve (0 = first)
- * @res returns the resource
- * @return 0 if ok, negative on error
- */
-int dev_read_resource(struct udevice *dev, uint index, struct resource *res);
-
#ifndef CONFIG_DM_DEV_READ_INLINE
/**
* dev_read_u32_default() - read a 32-bit integer from a device's DT property
int index,
struct ofnode_phandle_args *out_args);
+/**
+ * dev_count_phandle_with_args() - Return phandle number in a list
+ *
+ * This function is usefull to get phandle number contained in a property list.
+ * For example, this allows to allocate the right amount of memory to keep
+ * clock's reference contained into the "clocks" property.
+ *
+ *
+ * @dev: device whose node containing a list
+ * @list_name: property name that contains a list
+ * @cells_name: property name that specifies phandles' arguments count
+ * @Returns number of phandle found on success, on error returns appropriate
+ * errno value.
+ */
+
+int dev_count_phandle_with_args(struct udevice *dev, const char *list_name,
+ const char *cells_name);
+
/**
* dev_read_addr_cells() - Get the number of address cells for a device's node
*
* @lenp: place to put length on success
* @return pointer to property, or NULL if not found
*/
-const u32 *dev_read_prop(struct udevice *dev, const char *propname, int *lenp);
+const void *dev_read_prop(struct udevice *dev, const char *propname, int *lenp);
/**
* dev_read_alias_seq() - Get the alias sequence number of a node
*/
int dev_read_enabled(struct udevice *dev);
+/**
+ * dev_read_resource() - obtain an indexed resource from a device.
+ *
+ * @dev: devuce to examine
+ * @index index of the resource to retrieve (0 = first)
+ * @res returns the resource
+ * @return 0 if ok, negative on error
+ */
+int dev_read_resource(struct udevice *dev, uint index, struct resource *res);
+
#else /* CONFIG_DM_DEV_READ_INLINE is enabled */
static inline int dev_read_u32_default(struct udevice *dev,
out_args);
}
+static inline int dev_count_phandle_with_args(struct udevice *dev,
+ const char *list_name, const char *cells_name)
+{
+ return ofnode_count_phandle_with_args(dev_ofnode(dev), list_name,
+ cells_name);
+}
+
static inline int dev_read_addr_cells(struct udevice *dev)
{
/* NOTE: this call should walk up the parent stack */
return fdt_get_phandle(gd->fdt_blob, dev_of_offset(dev));
}
-static inline const u32 *dev_read_prop(struct udevice *dev,
- const char *propname, int *lenp)
+static inline const void *dev_read_prop(struct udevice *dev,
+ const char *propname, int *lenp)
{
return ofnode_get_property(dev_ofnode(dev), propname, lenp);
}
return fdtdec_get_is_enabled(gd->fdt_blob, dev_of_offset(dev));
}
+static inline int dev_read_resource(struct udevice *dev, uint index,
+ struct resource *res)
+{
+ return ofnode_read_resource(dev_ofnode(dev), index, res);
+}
+
#endif /* CONFIG_DM_DEV_READ_INLINE */
/**
#ifndef __GXBB_CLKC_H
#define __GXBB_CLKC_H
-#define CLKID_CPUCLK 1
#define CLKID_HDMI_PLL 2
#define CLKID_FCLK_DIV2 4
#define CLKID_FCLK_DIV3 5
#define CLKID_FCLK_DIV4 6
+#define CLKID_GP0_PLL 9
#define CLKID_CLK81 12
#define CLKID_MPLL2 15
-#define CLKID_SPI 34
+#define CLKID_SPICC 21
#define CLKID_I2C 22
#define CLKID_SAR_ADC 23
+#define CLKID_RNG0 25
+#define CLKID_UART0 26
+#define CLKID_SPI 34
#define CLKID_ETH 36
+#define CLKID_AIU_GLUE 38
+#define CLKID_IEC958 39
+#define CLKID_I2S_OUT 40
+#define CLKID_MIXER_IFACE 44
+#define CLKID_AIU 47
+#define CLKID_UART1 48
#define CLKID_USB0 50
#define CLKID_USB1 51
#define CLKID_USB 55
#define CLKID_HDMI_PCLK 63
#define CLKID_USB1_DDR_BRIDGE 64
#define CLKID_USB0_DDR_BRIDGE 65
+#define CLKID_UART2 68
#define CLKID_SANA 69
#define CLKID_GCLK_VENCI_INT0 77
+#define CLKID_AOCLK_GATE 80
+#define CLKID_IEC958_GATE 81
#define CLKID_AO_I2C 93
#define CLKID_SD_EMMC_A 94
#define CLKID_SD_EMMC_B 95
#define CLKID_SD_EMMC_C 96
#define CLKID_SAR_ADC_CLK 97
#define CLKID_SAR_ADC_SEL 98
+#define CLKID_MALI_0_SEL 100
+#define CLKID_MALI_0 102
+#define CLKID_MALI_1_SEL 103
+#define CLKID_MALI_1 105
+#define CLKID_MALI 106
+#define CLKID_CTS_AMCLK 107
+#define CLKID_CTS_MCLK_I958 110
+#define CLKID_CTS_I958 113
#endif /* __GXBB_CLKC_H */
--- /dev/null
+/*
+ * stm32fx-clock.h
+ *
+ * Copyright (C) 2016 STMicroelectronics
+ * Author: Gabriel Fernandez for STMicroelectronics.
+ * License terms: GNU General Public License (GPL), version 2
+ */
+
+/*
+ * List of clocks wich are not derived from system clock (SYSCLOCK)
+ *
+ * The index of these clocks is the secondary index of DT bindings
+ * (see Documentatoin/devicetree/bindings/clock/st,stm32-rcc.txt)
+ *
+ * e.g:
+ <assigned-clocks = <&rcc 1 CLK_LSE>;
+*/
+
+#ifndef _DT_BINDINGS_CLK_STMFX_H
+#define _DT_BINDINGS_CLK_STMFX_H
+
+#define SYSTICK 0
+#define FCLK 1
+#define CLK_LSI 2
+#define CLK_LSE 3
+#define CLK_HSE_RTC 4
+#define CLK_RTC 5
+#define PLL_VCO_I2S 6
+#define PLL_VCO_SAI 7
+#define CLK_LCD 8
+#define CLK_I2S 9
+#define CLK_SAI1 10
+#define CLK_SAI2 11
+#define CLK_I2SQ_PDIV 12
+#define CLK_SAIQ_PDIV 13
+
+#define END_PRIMARY_CLK 14
+
+#define CLK_HSI 14
+#define CLK_SYSCLK 15
+#define CLK_HDMI_CEC 16
+#define CLK_SPDIF 17
+#define CLK_USART1 18
+#define CLK_USART2 19
+#define CLK_USART3 20
+#define CLK_UART4 21
+#define CLK_UART5 22
+#define CLK_USART6 23
+#define CLK_UART7 24
+#define CLK_UART8 25
+#define CLK_I2C1 26
+#define CLK_I2C2 27
+#define CLK_I2C3 28
+#define CLK_I2C4 29
+#define CLK_LPTIMER 30
+
+#define END_PRIMARY_CLK_F7 31
+
+#endif
--- /dev/null
+/*
+ * This header provides constants for the STM32F7 RCC IP
+ */
+
+#ifndef _DT_BINDINGS_MFD_STM32F7_RCC_H
+#define _DT_BINDINGS_MFD_STM32F7_RCC_H
+
+/* AHB1 */
+#define STM32F7_RCC_AHB1_GPIOA 0
+#define STM32F7_RCC_AHB1_GPIOB 1
+#define STM32F7_RCC_AHB1_GPIOC 2
+#define STM32F7_RCC_AHB1_GPIOD 3
+#define STM32F7_RCC_AHB1_GPIOE 4
+#define STM32F7_RCC_AHB1_GPIOF 5
+#define STM32F7_RCC_AHB1_GPIOG 6
+#define STM32F7_RCC_AHB1_GPIOH 7
+#define STM32F7_RCC_AHB1_GPIOI 8
+#define STM32F7_RCC_AHB1_GPIOJ 9
+#define STM32F7_RCC_AHB1_GPIOK 10
+#define STM32F7_RCC_AHB1_CRC 12
+#define STM32F7_RCC_AHB1_BKPSRAM 18
+#define STM32F7_RCC_AHB1_DTCMRAM 20
+#define STM32F7_RCC_AHB1_DMA1 21
+#define STM32F7_RCC_AHB1_DMA2 22
+#define STM32F7_RCC_AHB1_DMA2D 23
+#define STM32F7_RCC_AHB1_ETHMAC 25
+#define STM32F7_RCC_AHB1_ETHMACTX 26
+#define STM32F7_RCC_AHB1_ETHMACRX 27
+#define STM32FF_RCC_AHB1_ETHMACPTP 28
+#define STM32F7_RCC_AHB1_OTGHS 29
+#define STM32F7_RCC_AHB1_OTGHSULPI 30
+
+#define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8))
+#define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit)
+
+
+/* AHB2 */
+#define STM32F7_RCC_AHB2_DCMI 0
+#define STM32F7_RCC_AHB2_CRYP 4
+#define STM32F7_RCC_AHB2_HASH 5
+#define STM32F7_RCC_AHB2_RNG 6
+#define STM32F7_RCC_AHB2_OTGFS 7
+
+#define STM32F7_AHB2_RESET(bit) (STM32F7_RCC_AHB2_##bit + (0x14 * 8))
+#define STM32F7_AHB2_CLOCK(bit) (STM32F7_RCC_AHB2_##bit + 0x20)
+
+/* AHB3 */
+#define STM32F7_RCC_AHB3_FMC 0
+#define STM32F7_RCC_AHB3_QSPI 1
+
+#define STM32F7_AHB3_RESET(bit) (STM32F7_RCC_AHB3_##bit + (0x18 * 8))
+#define STM32F7_AHB3_CLOCK(bit) (STM32F7_RCC_AHB3_##bit + 0x40)
+
+/* APB1 */
+#define STM32F7_RCC_APB1_TIM2 0
+#define STM32F7_RCC_APB1_TIM3 1
+#define STM32F7_RCC_APB1_TIM4 2
+#define STM32F7_RCC_APB1_TIM5 3
+#define STM32F7_RCC_APB1_TIM6 4
+#define STM32F7_RCC_APB1_TIM7 5
+#define STM32F7_RCC_APB1_TIM12 6
+#define STM32F7_RCC_APB1_TIM13 7
+#define STM32F7_RCC_APB1_TIM14 8
+#define STM32F7_RCC_APB1_LPTIM1 9
+#define STM32F7_RCC_APB1_WWDG 11
+#define STM32F7_RCC_APB1_SPI2 14
+#define STM32F7_RCC_APB1_SPI3 15
+#define STM32F7_RCC_APB1_SPDIFRX 16
+#define STM32F7_RCC_APB1_UART2 17
+#define STM32F7_RCC_APB1_UART3 18
+#define STM32F7_RCC_APB1_UART4 19
+#define STM32F7_RCC_APB1_UART5 20
+#define STM32F7_RCC_APB1_I2C1 21
+#define STM32F7_RCC_APB1_I2C2 22
+#define STM32F7_RCC_APB1_I2C3 23
+#define STM32F7_RCC_APB1_I2C4 24
+#define STM32F7_RCC_APB1_CAN1 25
+#define STM32F7_RCC_APB1_CAN2 26
+#define STM32F7_RCC_APB1_CEC 27
+#define STM32F7_RCC_APB1_PWR 28
+#define STM32F7_RCC_APB1_DAC 29
+#define STM32F7_RCC_APB1_UART7 30
+#define STM32F7_RCC_APB1_UART8 31
+
+#define STM32F7_APB1_RESET(bit) (STM32F7_RCC_APB1_##bit + (0x20 * 8))
+#define STM32F7_APB1_CLOCK(bit) (STM32F7_RCC_APB1_##bit + 0x80)
+
+/* APB2 */
+#define STM32F7_RCC_APB2_TIM1 0
+#define STM32F7_RCC_APB2_TIM8 1
+#define STM32F7_RCC_APB2_USART1 4
+#define STM32F7_RCC_APB2_USART6 5
+#define STM32F7_RCC_APB2_ADC1 8
+#define STM32F7_RCC_APB2_ADC2 9
+#define STM32F7_RCC_APB2_ADC3 10
+#define STM32F7_RCC_APB2_SDMMC1 11
+#define STM32F7_RCC_APB2_SPI1 12
+#define STM32F7_RCC_APB2_SPI4 13
+#define STM32F7_RCC_APB2_SYSCFG 14
+#define STM32F7_RCC_APB2_TIM9 16
+#define STM32F7_RCC_APB2_TIM10 17
+#define STM32F7_RCC_APB2_TIM11 18
+#define STM32F7_RCC_APB2_SPI5 20
+#define STM32F7_RCC_APB2_SPI6 21
+#define STM32F7_RCC_APB2_SAI1 22
+#define STM32F7_RCC_APB2_SAI2 23
+#define STM32F7_RCC_APB2_LTDC 26
+
+#define STM32F7_APB2_RESET(bit) (STM32F7_RCC_APB2_##bit + (0x24 * 8))
+#define STM32F7_APB2_CLOCK(bit) (STM32F7_RCC_APB2_##bit + 0xA0)
+
+#endif /* _DT_BINDINGS_MFD_STM32F7_RCC_H */
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __DT_STTUCTS
-#define __DT_STTUCTS
+#ifndef __DT_STRUCTS
+#define __DT_STRUCTS
/* These structures may only be used in SPL */
#if CONFIG_IS_ENABLED(OF_PLATDATA)
/* Export from hash table into binary representation */
int env_export(env_t *env_out);
+#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
+/* Select and import one of two redundant environments */
+int env_import_redund(const char *buf1, const char *buf2);
+#endif
+
#endif /* DO_DEPS_ONLY */
#endif /* _ENVIRONMENT_H_ */
COMPAT_NVIDIA_TEGRA20_EMC, /* Tegra20 memory controller */
COMPAT_NVIDIA_TEGRA20_EMC_TABLE, /* Tegra20 memory timing table */
COMPAT_NVIDIA_TEGRA20_NAND, /* Tegra2 NAND controller */
- COMPAT_NVIDIA_TEGRA124_PMC, /* Tegra 124 power mgmt controller */
- COMPAT_NVIDIA_TEGRA186_SDMMC, /* Tegra186 SDMMC controller */
- COMPAT_NVIDIA_TEGRA210_SDMMC, /* Tegra210 SDMMC controller */
- COMPAT_NVIDIA_TEGRA124_SDMMC, /* Tegra124 SDMMC controller */
- COMPAT_NVIDIA_TEGRA30_SDMMC, /* Tegra30 SDMMC controller */
- COMPAT_NVIDIA_TEGRA20_SDMMC, /* Tegra20 SDMMC controller */
COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
/* Tegra124 XUSB pad controller */
COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL,
phys_addr_t esdhc_base;
u32 sdhc_clk;
u8 max_bus_width;
- u8 wp_enable;
+ int wp_enable;
+ int vs18_enable; /* Use 1.8V if set to 1 */
struct mmc_config cfg;
};
int (*power_off)(struct phy *phy);
};
+#ifdef CONFIG_PHY
/**
* generic_phy_init() - initialize the PHY port
int generic_phy_get_by_name(struct udevice *user, const char *phy_name,
struct phy *phy);
+#else /* CONFIG_PHY */
+
+static inline int generic_phy_init(struct phy *phy)
+{
+ return 0;
+}
+
+static inline int generic_phy_exit(struct phy *phy)
+{
+ return 0;
+}
+
+static inline int generic_phy_reset(struct phy *phy)
+{
+ return 0;
+}
+
+static inline int generic_phy_power_on(struct phy *phy)
+{
+ return 0;
+}
+
+static inline int generic_phy_power_off(struct phy *phy)
+{
+ return 0;
+}
+
+static inline int generic_phy_get_by_index(struct udevice *user, int index,
+ struct phy *phy)
+{
+ return 0;
+}
+
+static inline int generic_phy_get_by_name(struct udevice *user, const char *phy_name,
+ struct phy *phy)
+{
+ return 0;
+}
+
+#endif /* CONFIG_PHY */
+
+/**
+ * generic_phy_valid() - check if PHY port is valid
+ *
+ * @phy: the PHY port to check
+ * @return TRUE if valid, or FALSE
+ */
+static inline bool generic_phy_valid(struct phy *phy)
+{
+ return phy->dev != NULL;
+}
+
#endif /*__GENERIC_PHY_H */
/*
- * definitions for MPC8260 I/O Ports
- *
- * (in addition to those provided in <asm/immap_8260.h>)
+ * definitions for MPC8xxx I/O Ports
*
* Murray.Jensen@cmst.csiro.au, 20-Oct-00
*/
/*
* this structure mirrors the layout of the five port registers in
- * the internal memory map - see iop8260_t in <asm/immap_8260.h>
+ * the internal memory map
*/
typedef struct {
unsigned int pdir; /* Port Data Direction Register (35-3) */
/*
* a table that contains configuration information for all 32 pins
- * of all four MPC8260 I/O ports.
*
* NOTE: in the second dimension of this table, index 0 refers to pin 31
* and index 31 refers to pin 0. this made the code in the table look more
#endif
extern int nand_curr_device;
-extern struct mtd_info *nand_info[];
static inline int nand_read(struct mtd_info *info, loff_t ofs, size_t *len,
u_char *buf)
/* platform specific init functions */
void sunxi_nand_init(void);
+/*
+ * get_nand_dev_by_index - Get the nand info based in index.
+ *
+ * @dev - index to the nand device.
+ *
+ * returns pointer to the nand device info structure or NULL on failure.
+ */
+struct mtd_info *get_nand_dev_by_index(int dev);
+
#endif /* _NAND_H_ */
* @base: Base register address
* @reg_shift: Shift size of registers (0=byte, 1=16bit, 2=32bit...)
* @clock: UART base clock speed in Hz
+ *
+ * @buf: Pointer to the RX interrupt buffer
+ * @rd_ptr: Read pointer in the RX interrupt buffer
+ * @wr_ptr: Write pointer in the RX interrupt buffer
*/
struct ns16550_platdata {
unsigned long base;
int clock;
int reg_offset;
u32 fcr;
+
+ int irq;
+
+ char *buf;
+ int rd_ptr;
+ int wr_ptr;
};
struct udevice;
*/
int os_get_filesize(const char *fname, loff_t *size);
-/**
- * Write a character to the controlling OS terminal
- *
- * This bypasses the U-Boot console support and writes directly to the OS
- * stdout file descriptor.
- *
- * @param ch Character to write
- */
-void os_putc(int ch);
-
-/**
- * Write a string to the controlling OS terminal
- *
- * This bypasses the U-Boot console support and writes directly to the OS
- * stdout file descriptor.
- *
- * @param str String to write (note that \n is not appended)
- */
-void os_puts(const char *str);
-
/**
* Write the sandbox RAM buffer to a existing file
*
#ifndef __POWER_AS3722_H__
#define __POWER_AS3722_H__
-#include <asm/types.h>
-
#define AS3722_GPIO_OUTPUT_VDDH (1 << 0)
#define AS3722_GPIO_INVERT (1 << 1)
-struct udevice;
+#define AS3722_DEVICE_ID 0x0c
+#define AS3722_SD_VOLTAGE(n) (0x00 + (n))
+#define AS3722_LDO_VOLTAGE(n) (0x10 + (n))
+#define AS3722_SD_CONTROL 0x4d
+#define AS3722_LDO_CONTROL 0x4e
+#define AS3722_ASIC_ID1 0x90
+#define AS3722_ASIC_ID2 0x91
+
+#define AS3722_GPIO_CONTROL(n) (0x08 + (n))
+#define AS3722_GPIO_SIGNAL_OUT 0x20
+#define AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH (1 << 0)
+#define AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDL (7 << 0)
+#define AS3722_GPIO_CONTROL_INVERT (1 << 7)
-int as3722_init(struct udevice **devp);
-int as3722_sd_enable(struct udevice *pmic, unsigned int sd);
-int as3722_sd_set_voltage(struct udevice *pmic, unsigned int sd, u8 value);
-int as3722_ldo_enable(struct udevice *pmic, unsigned int ldo);
-int as3722_ldo_set_voltage(struct udevice *pmic, unsigned int ldo, u8 value);
-int as3722_gpio_configure(struct udevice *pmic, unsigned int gpio,
- unsigned long flags);
-int as3722_gpio_direction_output(struct udevice *pmic, unsigned int gpio,
- unsigned int level);
-int as3722_read(struct udevice *pmic, u8 reg, u8 *value);
-int as3722_write(struct udevice *pmic, u8 reg, u8 value);
-int as3722_get(struct udevice **devp);
+int as3722_sd_set_voltage(struct udevice *dev, unsigned int sd, u8 value);
#endif /* __POWER_AS3722_H__ */
* @dev - regulator device
* Sets:
* @enable - set true - enable or false - disable
- * @return true/false for get; or 0 / -errno for set.
+ * @return true/false for get or -errno if fail; 0 / -errno for set.
*/
- bool (*get_enable)(struct udevice *dev);
+ int (*get_enable)(struct udevice *dev);
int (*set_enable)(struct udevice *dev, bool enable);
/**
* regulator_get_enable: get regulator device enable state.
*
* @dev - pointer to the regulator device
- * @return - true/false of enable state
+ * @return - true/false of enable state or -errno val if fails
*/
-bool regulator_get_enable(struct udevice *dev);
+int regulator_get_enable(struct udevice *dev);
/**
* regulator_set_enable: set regulator enable state
int reset_get_by_name(struct udevice *dev, const char *name,
struct reset_ctl *reset_ctl);
+/**
+ * reset_request - Request a reset signal.
+ *
+ * @reset_ctl: A reset control struct.
+ *
+ * @return 0 if OK, or a negative error code.
+ */
+int reset_request(struct reset_ctl *reset_ctl);
+
/**
* reset_free - Free a previously requested reset signal.
*
*/
int reset_deassert(struct reset_ctl *reset_ctl);
+/**
+ * reset_release_all - Assert/Free an array of previously requested resets.
+ *
+ * For each reset contained in the reset array, this function will check if
+ * reset has been previously requested and then will assert and free it.
+ *
+ * @reset_ctl: A reset struct array that was previously successfully
+ * requested by reset_get_by_*().
+ * @count Number of reset contained in the array
+ * @return 0 if OK, or a negative error code.
+ */
+int reset_release_all(struct reset_ctl *reset_ctl, int count);
#else
static inline int reset_get_by_index(struct udevice *dev, int index,
struct reset_ctl *reset_ctl)
{
return 0;
}
+
+static inline int reset_release_all(struct reset_ctl *reset_ctl, int count)
+{
+ return 0;
+}
+
#endif
#endif
unsigned short wHubChange;
} __attribute__ ((packed));
+/*
+ * Hub Device descriptor
+ * USB Hub class device protocols
+ */
+#define USB_HUB_PR_FS 0 /* Full speed hub */
+#define USB_HUB_PR_HS_NO_TT 0 /* Hi-speed hub without TT */
+#define USB_HUB_PR_HS_SINGLE_TT 1 /* Hi-speed hub with single TT */
+#define USB_HUB_PR_HS_MULTI_TT 2 /* Hi-speed hub with multiple TT */
+#define USB_HUB_PR_SS 3 /* Super speed hub */
+
+/* Transaction Translator Think Times, in bits */
+#define HUB_TTTT_8_BITS 0x00
+#define HUB_TTTT_16_BITS 0x20
+#define HUB_TTTT_24_BITS 0x40
+#define HUB_TTTT_32_BITS 0x60
/* Hub descriptor */
struct usb_hub_descriptor {
unsigned short wHubCharacteristics;
unsigned char bPwrOn2PwrGood;
unsigned char bHubContrCurrent;
- unsigned char DeviceRemovable[(USB_MAXCHILDREN+1+7)/8];
- unsigned char PortPowerCtrlMask[(USB_MAXCHILDREN+1+7)/8];
- /* DeviceRemovable and PortPwrCtrlMask want to be variable-length
- bitmaps that hold max 255 entries. (bit0 is ignored) */
+ /* 2.0 and 3.0 hubs differ here */
+ union {
+ struct {
+ /* add 1 bit for hub status change; round to bytes */
+ __u8 DeviceRemovable[(USB_MAXCHILDREN + 1 + 7) / 8];
+ __u8 PortPowerCtrlMask[(USB_MAXCHILDREN + 1 + 7) / 8];
+ } __attribute__ ((packed)) hs;
+
+ struct {
+ __u8 bHubHdrDecLat;
+ __le16 wHubDelay;
+ __le16 DeviceRemovable;
+ } __attribute__ ((packed)) ss;
+ } u;
} __attribute__ ((packed));
ulong connect_timeout; /* Device connection timeout in ms */
ulong query_delay; /* Device query delay in ms */
int overcurrent_count[USB_MAXCHILDREN]; /* Over-current counter */
+ int hub_depth; /* USB 3.0 hub depth */
+ struct usb_tt tt; /* Transaction Translator */
};
#ifdef CONFIG_DM_USB
* reset_root_port() - Reset usb root port
*/
int (*reset_root_port)(struct udevice *bus, struct usb_device *udev);
+
+ /**
+ * update_hub_device() - Update HCD's internal representation of hub
+ *
+ * After a hub descriptor is fetched, notify HCD so that its internal
+ * representation of this hub can be updated (xHCI)
+ */
+ int (*update_hub_device)(struct udevice *bus, struct usb_device *udev);
};
#define usb_get_ops(dev) ((struct dm_usb_ops *)(dev)->driver->ops)
int usb_setup_device(struct usb_device *dev, bool do_read,
struct usb_device *parent);
+/**
+ * usb_hub_is_root_hub() - Test whether a hub device is root hub or not
+ *
+ * @hub: USB hub device to test
+ * @return: true if the hub device is root hub, false otherwise.
+ */
+bool usb_hub_is_root_hub(struct udevice *hub);
+
/**
* usb_hub_scan() - Scan a hub and find its devices
*
int usb_hub_probe(struct usb_device *dev, int ifnum);
void usb_hub_reset(void);
-/**
- * legacy_hub_port_reset() - reset a port given its usb_device pointer
- *
- * Reset a hub port and see if a device is present on that port, providing
- * sufficient time for it to show itself. The port status is returned.
- *
- * With driver model this moves to hub_port_reset() and is passed a struct
- * udevice.
- *
- * @dev: USB device to reset
- * @port: Port number to reset (note ports are numbered from 0 here)
- * @portstat: Returns port status
- */
-int legacy_hub_port_reset(struct usb_device *dev, int port,
- unsigned short *portstat);
-
-int hub_port_reset(struct udevice *dev, int port, unsigned short *portstat);
-
/*
* usb_find_usb2_hub_address_port() - Get hub address and port for TT setting
*
int usb_alloc_device(struct usb_device *dev);
+/**
+ * update_hub_device() - Update HCD's internal representation of hub
+ *
+ * After a hub descriptor is fetched, notify HCD so that its internal
+ * representation of this hub can be updated.
+ *
+ * @dev: Hub device
+ * @return 0 if OK, -ve on error
+ */
+int usb_update_hub_device(struct usb_device *dev);
+
/**
* usb_emul_setup_device() - Set up a new USB device emulation
*
* @desc_list: List of points or USB descriptors, terminated by NULL.
* The first entry must be struct usb_device_descriptor,
* and others follow on after that.
- * @return 0 if OK, -ve on error
+ * @return 0 if OK, -ENOSYS if not implemented, other -ve on error
*/
int usb_emul_setup_device(struct udevice *dev, int maxpacketsize,
struct usb_string *strings, void **desc_list);
#define USB_DT_REPORT (USB_TYPE_CLASS | 0x02)
#define USB_DT_PHYSICAL (USB_TYPE_CLASS | 0x03)
#define USB_DT_HUB (USB_TYPE_CLASS | 0x09)
+#define USB_DT_SS_HUB (USB_TYPE_CLASS | 0x0a)
/* Descriptor sizes per descriptor type */
#define USB_DT_DEVICE_SIZE 18
/*
* Changes to wPortStatus bit field in USB 3.0
- * See USB 3.0 spec Table 10-11
+ * See USB 3.0 spec Table 10-10
*/
#define USB_SS_PORT_STAT_LINK_STATE 0x01e0
#define USB_SS_PORT_STAT_POWER 0x0200
#define USB_SS_PORT_STAT_SPEED 0x1c00
#define USB_SS_PORT_STAT_SPEED_5GBPS 0x0000
+/* Bits that are the same from USB 2.0 */
+#define USB_SS_PORT_STAT_MASK (USB_PORT_STAT_CONNECTION | \
+ USB_PORT_STAT_ENABLE | \
+ USB_PORT_STAT_OVERCURRENT | \
+ USB_PORT_STAT_RESET)
/* wPortChange bits */
#define USB_PORT_STAT_C_CONNECTION 0x0001
#define HUB_CHAR_LPSM 0x0003
#define HUB_CHAR_COMPOUND 0x0004
#define HUB_CHAR_OCPM 0x0018
+#define HUB_CHAR_TTTT 0x0060 /* TT Think Time mask */
/*
* Hub Status & Hub Change bit masks
/* Mask for wIndex in get/set port feature */
#define USB_HUB_PORT_MASK 0xf
+/* Hub class request codes */
+#define USB_REQ_SET_HUB_DEPTH 0x0c
+
+/*
+ * As of USB 2.0, full/low speed devices are segregated into trees.
+ * One type grows from USB 1.1 host controllers (OHCI, UHCI etc).
+ * The other type grows from high speed hubs when they connect to
+ * full/low speed devices using "Transaction Translators" (TTs).
+ */
+struct usb_tt {
+ bool multi; /* true means one TT per port */
+ unsigned think_time; /* think time in ns */
+};
+
/*
* CBI style
*/
CONFIG_CMD_LZMADEC which provides a decode command.
config LZO
- bool
+ bool "Enable LZO decompression support"
+ help
+ This enables support for LZO compression algorithm.r
endmenu
config ERRNO_STR
DEFINE(GD_SIZE, sizeof(struct global_data));
DEFINE(GD_BD, offsetof(struct global_data, bd));
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
DEFINE(GD_MALLOC_BASE, offsetof(struct global_data, malloc_base));
#endif
return ret;
memset(gd, '\0', sizeof(*gd));
- gd->malloc_base = (ulong)efi_malloc(priv, CONFIG_SYS_MALLOC_F_LEN,
+ gd->malloc_base = (ulong)efi_malloc(priv, CONFIG_VAL(SYS_MALLOC_F_LEN),
&ret);
if (!gd->malloc_base)
return ret;
COMPAT(NVIDIA_TEGRA20_EMC, "nvidia,tegra20-emc"),
COMPAT(NVIDIA_TEGRA20_EMC_TABLE, "nvidia,tegra20-emc-table"),
COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),
- COMPAT(NVIDIA_TEGRA124_PMC, "nvidia,tegra124-pmc"),
- COMPAT(NVIDIA_TEGRA186_SDMMC, "nvidia,tegra186-sdhci"),
- COMPAT(NVIDIA_TEGRA210_SDMMC, "nvidia,tegra210-sdhci"),
- COMPAT(NVIDIA_TEGRA124_SDMMC, "nvidia,tegra124-sdhci"),
- COMPAT(NVIDIA_TEGRA30_SDMMC, "nvidia,tegra30-sdhci"),
- COMPAT(NVIDIA_TEGRA20_SDMMC, "nvidia,tegra20-sdhci"),
COMPAT(NVIDIA_TEGRA124_XUSB_PADCTL, "nvidia,tegra124-xusb-padctl"),
COMPAT(NVIDIA_TEGRA210_XUSB_PADCTL, "nvidia,tegra210-xusb-padctl"),
COMPAT(SMSC_LAN9215, "smsc,lan9215"),
quiet_cmd_acpi_c_asl= ASL $<
cmd_acpi_c_asl= \
$(CPP) -x assembler-with-cpp -D__ASSEMBLY__ -P $(UBOOTINCLUDE) -o $<.tmp $<; \
- iasl -p $< -tc $<.tmp $(if $(KBUILD_VERBOSE:1=), >/dev/null); \
+ iasl -p $< -tc $<.tmp $(if $(KBUILD_VERBOSE:1=), >/dev/null) && \
mv $(patsubst %.asl,%.hex,$<) $@
$(obj)/dsdt.c: $(src)/dsdt.asl
CONFIG_ENV_FLASHBOOT
CONFIG_ENV_IS_EMBEDDED
CONFIG_ENV_IS_IN_
-CONFIG_ENV_IS_IN_DATAFLASH
-CONFIG_ENV_IS_IN_EEPROM
-CONFIG_ENV_IS_IN_FAT
-CONFIG_ENV_IS_IN_FLASH
-CONFIG_ENV_IS_IN_MRAM
-CONFIG_ENV_IS_IN_NVRAM
-CONFIG_ENV_IS_IN_ONENAND
-CONFIG_ENV_IS_IN_REMOTE
-CONFIG_ENV_IS_IN_SPI_FLASH
CONFIG_ENV_MAX_ENTRIES
CONFIG_ENV_MIN_ENTRIES
CONFIG_ENV_OFFSET_OOB
CONFIG_SYS_FSL_ESDHC_ADDR
CONFIG_SYS_FSL_ESDHC_BE
CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
CONFIG_SYS_FSL_ESDHC_LE
CONFIG_SYS_FSL_ESDHC_NUM
CONFIG_SYS_USBCTRL
CONFIG_SYS_USBD_BASE
CONFIG_SYS_USB_EHCI_CPU_INIT
-CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS
CONFIG_SYS_USB_EHCI_REGS_BASE
CONFIG_SYS_USB_FAT_BOOT_PARTITION
CONFIG_SYS_USB_HOST
CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS
CONFIG_SYS_USB_OHCI_REGS_BASE
CONFIG_SYS_USB_OHCI_SLOT_NAME
-CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS
CONFIG_SYS_USER_SWITCHES_BASE
CONFIG_SYS_USE_BOOT_NORFLASH
CONFIG_SYS_USE_DATAFLASH
CONFIG_USB_XHCI_FSL
CONFIG_USB_XHCI_KEYSTONE
CONFIG_USB_XHCI_OMAP
-CONFIG_USB_XHCI_PCI
CONFIG_USER_LOWLEVEL_INIT
CONFIG_USE_FDT
CONFIG_USE_INTERRUPT
(You may wish to change the group ID instead of setting the permissions wide
open. All that matters is that the user ID running the test can access the
device.)
+
+c) An optional udev rule to give you a persistent value to use in
+host_usb_dev_node. For example:
+
+IMPORT{builtin}="path_id"
+ENV{ID_PATH}=="?*", ENV{.ID_PORT}=="", SYMLINK+="bus/usb/by-path/$env{ID_PATH}"
+ENV{ID_PATH}=="?*", ENV{.ID_PORT}=="?*", SYMLINK+="bus/usb/by-path/$env{ID_PATH}-port$env{.ID_PORT}"
"""
# The set of file sizes to test. These values trigger various edge-cases such
/img2srec
/kwboot
/dumpimage
+/mips-relocs
/mkenvimage
/mkimage
/mkexynosspl
endif
endif
+HOSTCFLAGS_fit_image.o += -DMKIMAGE_DTC=\"$(DTC)\"
+
HOSTLOADLIBES_dumpimage := $(HOSTLOADLIBES_mkimage)
HOSTLOADLIBES_fit_info := $(HOSTLOADLIBES_mkimage)
HOSTLOADLIBES_fit_check_sign := $(HOSTLOADLIBES_mkimage)
hostprogs-y += fdtgrep
fdtgrep-objs += $(LIBFDT_OBJS) fdtgrep.o
+hostprogs-$(CONFIG_MIPS) += mips-relocs
+
# We build some files with extra pedantic flags to try to minimize things
# that won't build on some weird host compiler -- though there are lots of
# exceptions for files that aren't complaint.
rc = flash_write (fd_current, fd_target, dev_target);
+ if (fsync (fd_current)) {
+ fprintf (stderr,
+ "fsync failed on %s: %s\n",
+ DEVNAME (dev_current), strerror (errno));
+ }
+
if (HaveRedundEnv) {
+ if (fsync (fd_target)) {
+ fprintf (stderr,
+ "fsync failed on %s: %s\n",
+ DEVNAME (dev_current), strerror (errno));
+ }
+
if (close (fd_target)) {
fprintf (stderr,
"I/O error on %s: %s\n",
/*
* NOTE: This file must be kept in sync with arch/arm/include/asm/\
- * imx-common/imximage.cfg because tools/imximage.c can not
+ * mach-imx/imximage.cfg because tools/imximage.c can not
* cross-include headers from arch/arm/ and vice-versa.
*/
#define CMD_DATA_STR "DATA"
return csum;
}
+size_t kwbimage_header_size(unsigned char *ptr)
+{
+ if (image_version((void *)ptr) == 0)
+ return sizeof(struct main_hdr_v0);
+ else
+ return KWBHEADER_V1_SIZE((struct main_hdr_v1 *)ptr);
+}
+
+/*
+ * Verify checksum over a complete header that includes the checksum field.
+ * Return 1 when OK, otherwise 0.
+ */
+static int main_hdr_checksum_ok(void *hdr)
+{
+ /* Offsets of checksum in v0 and v1 headers are the same */
+ struct main_hdr_v0 *main_hdr = (struct main_hdr_v0 *)hdr;
+ uint8_t checksum;
+
+ checksum = image_checksum8(hdr, kwbimage_header_size(hdr));
+ /* Calculated checksum includes the header checksum field. Compensate
+ * for that.
+ */
+ checksum -= main_hdr->checksum;
+
+ return checksum == main_hdr->checksum;
+}
+
static uint32_t image_checksum32(void *start, uint32_t len)
{
uint32_t csum = 0;
static int kwbimage_verify_header(unsigned char *ptr, int image_size,
struct image_tool_params *params)
{
- struct main_hdr_v0 *main_hdr;
uint8_t checksum;
- main_hdr = (struct main_hdr_v0 *)ptr;
- checksum = image_checksum8(ptr,
- sizeof(struct main_hdr_v0)
- - sizeof(uint8_t));
- if (checksum != main_hdr->checksum)
+ if (!main_hdr_checksum_ok(ptr))
return -FDT_ERR_BADSTRUCTURE;
/* Only version 0 extended header has checksum */
/* Structure of the main header, version 0 (Kirkwood, Dove) */
struct main_hdr_v0 {
- uint8_t blockid; /*0 */
- uint8_t nandeccmode; /*1 */
- uint16_t nandpagesize; /*2-3 */
- uint32_t blocksize; /*4-7 */
- uint32_t rsvd1; /*8-11 */
- uint32_t srcaddr; /*12-15 */
- uint32_t destaddr; /*16-19 */
- uint32_t execaddr; /*20-23 */
- uint8_t satapiomode; /*24 */
- uint8_t rsvd3; /*25 */
- uint16_t ddrinitdelay; /*26-27 */
- uint16_t rsvd2; /*28-29 */
- uint8_t ext; /*30 */
- uint8_t checksum; /*31 */
+ uint8_t blockid; /* 0x0 */
+ uint8_t nandeccmode; /* 0x1 */
+ uint16_t nandpagesize; /* 0x2-0x3 */
+ uint32_t blocksize; /* 0x4-0x7 */
+ uint32_t rsvd1; /* 0x8-0xB */
+ uint32_t srcaddr; /* 0xC-0xF */
+ uint32_t destaddr; /* 0x10-0x13 */
+ uint32_t execaddr; /* 0x14-0x17 */
+ uint8_t satapiomode; /* 0x18 */
+ uint8_t rsvd3; /* 0x19 */
+ uint16_t ddrinitdelay; /* 0x1A-0x1B */
+ uint16_t rsvd2; /* 0x1C-0x1D */
+ uint8_t ext; /* 0x1E */
+ uint8_t checksum; /* 0x1F */
};
struct ext_hdr_v0_reg {
struct ext_hdr_v0 kwb_exthdr;
};
-/* Structure of the main header, version 1 (Armada 370, Armada XP) */
+/* Structure of the main header, version 1 (Armada 370/38x/XP) */
struct main_hdr_v1 {
- uint8_t blockid; /* 0 */
- uint8_t flags; /* 1 */
- uint16_t reserved2; /* 2-3 */
- uint32_t blocksize; /* 4-7 */
- uint8_t version; /* 8 */
- uint8_t headersz_msb; /* 9 */
- uint16_t headersz_lsb; /* A-B */
- uint32_t srcaddr; /* C-F */
- uint32_t destaddr; /* 10-13 */
- uint32_t execaddr; /* 14-17 */
- uint8_t options; /* 18 */
- uint8_t nandblocksize; /* 19 */
- uint8_t nandbadblklocation; /* 1A */
- uint8_t reserved4; /* 1B */
- uint16_t reserved5; /* 1C-1D */
- uint8_t ext; /* 1E */
- uint8_t checksum; /* 1F */
+ uint8_t blockid; /* 0x0 */
+ uint8_t flags; /* 0x1 */
+ uint16_t reserved2; /* 0x2-0x3 */
+ uint32_t blocksize; /* 0x4-0x7 */
+ uint8_t version; /* 0x8 */
+ uint8_t headersz_msb; /* 0x9 */
+ uint16_t headersz_lsb; /* 0xA-0xB */
+ uint32_t srcaddr; /* 0xC-0xF */
+ uint32_t destaddr; /* 0x10-0x13 */
+ uint32_t execaddr; /* 0x14-0x17 */
+ uint8_t options; /* 0x18 */
+ uint8_t nandblocksize; /* 0x19 */
+ uint8_t nandbadblklocation; /* 0x1A */
+ uint8_t reserved4; /* 0x1B */
+ uint16_t reserved5; /* 0x1C-0x1D */
+ uint8_t ext; /* 0x1E */
+ uint8_t checksum; /* 0x1F */
};
/*
--- /dev/null
+/*
+ * MIPS Relocation Data Generator
+ *
+ * Copyright (c) 2017 Imagination Technologies Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <assert.h>
+#include <elf.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <limits.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <sys/mman.h>
+#include <sys/stat.h>
+#include <unistd.h>
+
+#include <asm/relocs.h>
+
+#define hdr_field(pfx, idx, field) ({ \
+ uint64_t _val; \
+ unsigned int _size; \
+ \
+ if (is_64) { \
+ _val = pfx##hdr64[idx].field; \
+ _size = sizeof(pfx##hdr64[0].field); \
+ } else { \
+ _val = pfx##hdr32[idx].field; \
+ _size = sizeof(pfx##hdr32[0].field); \
+ } \
+ \
+ switch (_size) { \
+ case 1: \
+ break; \
+ case 2: \
+ _val = is_be ? be16toh(_val) : le16toh(_val); \
+ break; \
+ case 4: \
+ _val = is_be ? be32toh(_val) : le32toh(_val); \
+ break; \
+ case 8: \
+ _val = is_be ? be64toh(_val) : le64toh(_val); \
+ break; \
+ } \
+ \
+ _val; \
+})
+
+#define set_hdr_field(pfx, idx, field, val) ({ \
+ uint64_t _val; \
+ unsigned int _size; \
+ \
+ if (is_64) \
+ _size = sizeof(pfx##hdr64[0].field); \
+ else \
+ _size = sizeof(pfx##hdr32[0].field); \
+ \
+ switch (_size) { \
+ case 1: \
+ _val = val; \
+ break; \
+ case 2: \
+ _val = is_be ? htobe16(val) : htole16(val); \
+ break; \
+ case 4: \
+ _val = is_be ? htobe32(val) : htole32(val); \
+ break; \
+ case 8: \
+ _val = is_be ? htobe64(val) : htole64(val); \
+ break; \
+ default: \
+ /* We should never reach here */ \
+ _val = 0; \
+ assert(0); \
+ break; \
+ } \
+ \
+ if (is_64) \
+ pfx##hdr64[idx].field = _val; \
+ else \
+ pfx##hdr32[idx].field = _val; \
+})
+
+#define ehdr_field(field) \
+ hdr_field(e, 0, field)
+#define phdr_field(idx, field) \
+ hdr_field(p, idx, field)
+#define shdr_field(idx, field) \
+ hdr_field(s, idx, field)
+
+#define set_phdr_field(idx, field, val) \
+ set_hdr_field(p, idx, field, val)
+#define set_shdr_field(idx, field, val) \
+ set_hdr_field(s, idx, field, val)
+
+#define shstr(idx) (&shstrtab[idx])
+
+bool is_64, is_be;
+uint64_t text_base;
+
+struct mips_reloc {
+ uint8_t type;
+ uint64_t offset;
+} *relocs;
+size_t relocs_sz, relocs_idx;
+
+static int add_reloc(unsigned int type, uint64_t off)
+{
+ struct mips_reloc *new;
+ size_t new_sz;
+
+ switch (type) {
+ case R_MIPS_NONE:
+ case R_MIPS_LO16:
+ case R_MIPS_PC16:
+ case R_MIPS_HIGHER:
+ case R_MIPS_HIGHEST:
+ case R_MIPS_PC21_S2:
+ case R_MIPS_PC26_S2:
+ /* Skip these relocs */
+ return 0;
+
+ default:
+ break;
+ }
+
+ if (relocs_idx == relocs_sz) {
+ new_sz = relocs_sz ? relocs_sz * 2 : 128;
+ new = realloc(relocs, new_sz * sizeof(*relocs));
+ if (!new) {
+ fprintf(stderr, "Out of memory\n");
+ return -ENOMEM;
+ }
+
+ relocs = new;
+ relocs_sz = new_sz;
+ }
+
+ relocs[relocs_idx++] = (struct mips_reloc){
+ .type = type,
+ .offset = off,
+ };
+
+ return 0;
+}
+
+static int parse_mips32_rel(const void *_rel)
+{
+ const Elf32_Rel *rel = _rel;
+ uint32_t off, type;
+
+ off = is_be ? be32toh(rel->r_offset) : le32toh(rel->r_offset);
+ off -= text_base;
+
+ type = is_be ? be32toh(rel->r_info) : le32toh(rel->r_info);
+ type = ELF32_R_TYPE(type);
+
+ return add_reloc(type, off);
+}
+
+static int parse_mips64_rela(const void *_rel)
+{
+ const Elf64_Rela *rel = _rel;
+ uint64_t off, type;
+
+ off = is_be ? be64toh(rel->r_offset) : le64toh(rel->r_offset);
+ off -= text_base;
+
+ type = rel->r_info >> (64 - 8);
+
+ return add_reloc(type, off);
+}
+
+static void output_uint(uint8_t **buf, uint64_t val)
+{
+ uint64_t tmp;
+
+ do {
+ tmp = val & 0x7f;
+ val >>= 7;
+ tmp |= !!val << 7;
+ *(*buf)++ = tmp;
+ } while (val);
+}
+
+static int compare_relocs(const void *a, const void *b)
+{
+ const struct mips_reloc *ra = a, *rb = b;
+
+ return ra->offset - rb->offset;
+}
+
+int main(int argc, char *argv[])
+{
+ unsigned int i, j, i_rel_shdr, sh_type, sh_entsize, sh_entries;
+ size_t rel_size, rel_actual_size, load_sz;
+ const char *shstrtab, *sh_name, *rel_pfx;
+ int (*parse_fn)(const void *rel);
+ uint8_t *buf_start, *buf;
+ const Elf32_Ehdr *ehdr32;
+ const Elf64_Ehdr *ehdr64;
+ uintptr_t sh_offset;
+ Elf32_Phdr *phdr32;
+ Elf64_Phdr *phdr64;
+ Elf32_Shdr *shdr32;
+ Elf64_Shdr *shdr64;
+ struct stat st;
+ int err, fd;
+ void *elf;
+ bool skip;
+
+ fd = open(argv[1], O_RDWR);
+ if (fd == -1) {
+ fprintf(stderr, "Unable to open input file %s\n", argv[1]);
+ err = errno;
+ goto out_ret;
+ }
+
+ err = fstat(fd, &st);
+ if (err) {
+ fprintf(stderr, "Unable to fstat() input file\n");
+ goto out_close_fd;
+ }
+
+ elf = mmap(NULL, st.st_size, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
+ if (elf == MAP_FAILED) {
+ fprintf(stderr, "Unable to mmap() input file\n");
+ err = errno;
+ goto out_close_fd;
+ }
+
+ ehdr32 = elf;
+ ehdr64 = elf;
+
+ if (memcmp(&ehdr32->e_ident[EI_MAG0], ELFMAG, SELFMAG)) {
+ fprintf(stderr, "Input file is not an ELF\n");
+ err = -EINVAL;
+ goto out_free_relocs;
+ }
+
+ if (ehdr32->e_ident[EI_VERSION] != EV_CURRENT) {
+ fprintf(stderr, "Unrecognised ELF version\n");
+ err = -EINVAL;
+ goto out_free_relocs;
+ }
+
+ switch (ehdr32->e_ident[EI_CLASS]) {
+ case ELFCLASS32:
+ is_64 = false;
+ break;
+ case ELFCLASS64:
+ is_64 = true;
+ break;
+ default:
+ fprintf(stderr, "Unrecognised ELF class\n");
+ err = -EINVAL;
+ goto out_free_relocs;
+ }
+
+ switch (ehdr32->e_ident[EI_DATA]) {
+ case ELFDATA2LSB:
+ is_be = false;
+ break;
+ case ELFDATA2MSB:
+ is_be = true;
+ break;
+ default:
+ fprintf(stderr, "Unrecognised ELF data encoding\n");
+ err = -EINVAL;
+ goto out_free_relocs;
+ }
+
+ if (ehdr_field(e_type) != ET_EXEC) {
+ fprintf(stderr, "Input ELF is not an executable\n");
+ printf("type 0x%lx\n", ehdr_field(e_type));
+ err = -EINVAL;
+ goto out_free_relocs;
+ }
+
+ if (ehdr_field(e_machine) != EM_MIPS) {
+ fprintf(stderr, "Input ELF does not target MIPS\n");
+ err = -EINVAL;
+ goto out_free_relocs;
+ }
+
+ phdr32 = elf + ehdr_field(e_phoff);
+ phdr64 = elf + ehdr_field(e_phoff);
+ shdr32 = elf + ehdr_field(e_shoff);
+ shdr64 = elf + ehdr_field(e_shoff);
+ shstrtab = elf + shdr_field(ehdr_field(e_shstrndx), sh_offset);
+
+ i_rel_shdr = UINT_MAX;
+ for (i = 0; i < ehdr_field(e_shnum); i++) {
+ sh_name = shstr(shdr_field(i, sh_name));
+
+ if (!strcmp(sh_name, ".rel")) {
+ i_rel_shdr = i;
+ continue;
+ }
+
+ if (!strcmp(sh_name, ".text")) {
+ text_base = shdr_field(i, sh_addr);
+ continue;
+ }
+ }
+ if (i_rel_shdr == UINT_MAX) {
+ fprintf(stderr, "Unable to find .rel section\n");
+ err = -EINVAL;
+ goto out_free_relocs;
+ }
+ if (!text_base) {
+ fprintf(stderr, "Unable to find .text base address\n");
+ err = -EINVAL;
+ goto out_free_relocs;
+ }
+
+ rel_pfx = is_64 ? ".rela." : ".rel.";
+
+ for (i = 0; i < ehdr_field(e_shnum); i++) {
+ sh_type = shdr_field(i, sh_type);
+ if ((sh_type != SHT_REL) && (sh_type != SHT_RELA))
+ continue;
+
+ sh_name = shstr(shdr_field(i, sh_name));
+ if (strncmp(sh_name, rel_pfx, strlen(rel_pfx))) {
+ if (strcmp(sh_name, ".rel") && strcmp(sh_name, ".rel.dyn"))
+ fprintf(stderr, "WARNING: Unexpected reloc section name '%s'\n", sh_name);
+ continue;
+ }
+
+ /*
+ * Skip reloc sections which either don't correspond to another
+ * section in the ELF, or whose corresponding section isn't
+ * loaded as part of the U-Boot binary (ie. doesn't have the
+ * alloc flags set).
+ */
+ skip = true;
+ for (j = 0; j < ehdr_field(e_shnum); j++) {
+ if (strcmp(&sh_name[strlen(rel_pfx) - 1], shstr(shdr_field(j, sh_name))))
+ continue;
+
+ skip = !(shdr_field(j, sh_flags) & SHF_ALLOC);
+ break;
+ }
+ if (skip)
+ continue;
+
+ sh_offset = shdr_field(i, sh_offset);
+ sh_entsize = shdr_field(i, sh_entsize);
+ sh_entries = shdr_field(i, sh_size) / sh_entsize;
+
+ if (sh_type == SHT_REL) {
+ if (is_64) {
+ fprintf(stderr, "REL-style reloc in MIPS64 ELF?\n");
+ err = -EINVAL;
+ goto out_free_relocs;
+ } else {
+ parse_fn = parse_mips32_rel;
+ }
+ } else {
+ if (is_64) {
+ parse_fn = parse_mips64_rela;
+ } else {
+ fprintf(stderr, "RELA-style reloc in MIPS32 ELF?\n");
+ err = -EINVAL;
+ goto out_free_relocs;
+ }
+ }
+
+ for (j = 0; j < sh_entries; j++) {
+ err = parse_fn(elf + sh_offset + (j * sh_entsize));
+ if (err)
+ goto out_free_relocs;
+ }
+ }
+
+ /* Sort relocs in ascending order of offset */
+ qsort(relocs, relocs_idx, sizeof(*relocs), compare_relocs);
+
+ /* Make reloc offsets relative to their predecessor */
+ for (i = relocs_idx - 1; i > 0; i--)
+ relocs[i].offset -= relocs[i - 1].offset;
+
+ /* Write the relocations to the .rel section */
+ buf = buf_start = elf + shdr_field(i_rel_shdr, sh_offset);
+ for (i = 0; i < relocs_idx; i++) {
+ output_uint(&buf, relocs[i].type);
+ output_uint(&buf, relocs[i].offset >> 2);
+ }
+
+ /* Write a terminating R_MIPS_NONE (0) */
+ output_uint(&buf, R_MIPS_NONE);
+
+ /* Ensure the relocs didn't overflow the .rel section */
+ rel_size = shdr_field(i_rel_shdr, sh_size);
+ rel_actual_size = buf - buf_start;
+ if (rel_actual_size > rel_size) {
+ fprintf(stderr, "Relocs overflowed .rel section\n");
+ return -ENOMEM;
+ }
+
+ /* Update the .rel section's size */
+ set_shdr_field(i_rel_shdr, sh_size, rel_actual_size);
+
+ /* Shrink the PT_LOAD program header filesz (ie. shrink u-boot.bin) */
+ for (i = 0; i < ehdr_field(e_phnum); i++) {
+ if (phdr_field(i, p_type) != PT_LOAD)
+ continue;
+
+ load_sz = phdr_field(i, p_filesz);
+ load_sz -= rel_size - rel_actual_size;
+ set_phdr_field(i, p_filesz, load_sz);
+ break;
+ }
+
+ /* Make sure data is written back to the file */
+ err = msync(elf, st.st_size, MS_SYNC);
+ if (err) {
+ fprintf(stderr, "Failed to msync: %d\n", errno);
+ goto out_free_relocs;
+ }
+
+out_free_relocs:
+ free(relocs);
+ munmap(elf, st.st_size);
+out_close_fd:
+ close(fd);
+out_ret:
+ return err;
+}
#define MKIMAGE_MAX_TMPFILE_LEN 256
#define MKIMAGE_DEFAULT_DTC_OPTIONS "-I dts -O dtb -p 500"
#define MKIMAGE_MAX_DTC_CMDLINE_LEN 512
-#define MKIMAGE_DTC "dtc" /* assume dtc is in $PATH */
#endif /* _MKIIMAGE_H_ */
Appropriate toolchain are necessary to generate include/autoconf.mk
for all the architectures supported by U-Boot. Most of them are available
-at the kernel.org site, some are not provided by kernel.org.
-
-The default per-arch CROSS_COMPILE used by this tool is specified by
-the list below, CROSS_COMPILE. You may wish to update the list to
-use your own. Instead of modifying the list directly, you can give
-them via environments.
+at the kernel.org site, some are not provided by kernel.org. This tool uses
+the same tools as buildman, so see that tool for setup (e.g. --fetch-arch).
Tips and trips
import time
sys.path.append(os.path.join(os.path.dirname(__file__), 'buildman'))
+sys.path.append(os.path.join(os.path.dirname(__file__), 'patman'))
+import bsettings
import kconfiglib
+import toolchain
SHOW_GNU_MAKE = 'scripts/show-gnu-make'
SLEEP_TIME=0.03
-# Here is the list of cross-tools I use.
-# Most of them are available at kernel.org
-# (https://www.kernel.org/pub/tools/crosstool/files/bin/), except the following:
-# arc: https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases
-# nds32: http://osdk.andestech.com/packages/nds32le-linux-glibc-v1.tgz
-# nios2: https://sourcery.mentor.com/GNUToolchain/subscription42545
-# sh: http://sourcery.mentor.com/public/gnu_toolchain/sh-linux-gnu
-CROSS_COMPILE = {
- 'arc': 'arc-linux-',
- 'aarch64': 'aarch64-linux-',
- 'arm': 'arm-unknown-linux-gnueabi-',
- 'm68k': 'm68k-linux-',
- 'microblaze': 'microblaze-linux-',
- 'mips': 'mips-linux-',
- 'nds32': 'nds32le-linux-',
- 'nios2': 'nios2-linux-gnu-',
- 'powerpc': 'powerpc-linux-',
- 'sh': 'sh-linux-gnu-',
- 'x86': 'i386-linux-',
- 'xtensa': 'xtensa-linux-'
-}
-
STATE_IDLE = 0
STATE_DEFCONFIG = 1
STATE_AUTOCONF = 2
else:
print line,
-def update_cross_compile(color_enabled):
- """Update per-arch CROSS_COMPILE via environment variables
-
- The default CROSS_COMPILE values are available
- in the CROSS_COMPILE list above.
-
- You can override them via environment variables
- CROSS_COMPILE_{ARCH}.
-
- For example, if you want to override toolchain prefixes
- for ARM and PowerPC, you can do as follows in your shell:
-
- export CROSS_COMPILE_ARM=...
- export CROSS_COMPILE_POWERPC=...
-
- Then, this function checks if specified compilers really exist in your
- PATH environment.
- """
- archs = []
-
- for arch in os.listdir('arch'):
- if os.path.exists(os.path.join('arch', arch, 'Makefile')):
- archs.append(arch)
-
- # arm64 is a special case
- archs.append('aarch64')
-
- for arch in archs:
- env = 'CROSS_COMPILE_' + arch.upper()
- cross_compile = os.environ.get(env)
- if not cross_compile:
- cross_compile = CROSS_COMPILE.get(arch, '')
-
- for path in os.environ["PATH"].split(os.pathsep):
- gcc_path = os.path.join(path, cross_compile + 'gcc')
- if os.path.isfile(gcc_path) and os.access(gcc_path, os.X_OK):
- break
- else:
- print >> sys.stderr, color_text(color_enabled, COLOR_YELLOW,
- 'warning: %sgcc: not found in PATH. %s architecture boards will be skipped'
- % (cross_compile, arch))
- cross_compile = None
-
- CROSS_COMPILE[arch] = cross_compile
-
def extend_matched_lines(lines, matched, pre_patterns, post_patterns, extend_pre,
extend_post):
"""Extend matched lines if desired patterns are found before/after already
self.config_autoconf = os.path.join(build_dir, AUTO_CONF_PATH)
self.defconfig = os.path.join(build_dir, 'defconfig')
- def get_cross_compile(self):
- """Parse .config file and return CROSS_COMPILE.
+ def get_arch(self):
+ """Parse .config file and return the architecture.
Returns:
- A string storing the compiler prefix for the architecture.
- Return a NULL string for architectures that do not require
- compiler prefix (Sandbox and native build is the case).
- Return None if the specified compiler is missing in your PATH.
- Caller should distinguish '' and None.
+ Architecture name (e.g. 'arm').
"""
arch = ''
cpu = ''
if arch == 'arm' and cpu == 'armv8':
arch = 'aarch64'
- return CROSS_COMPILE.get(arch, None)
+ return arch
def parse_one_config(self, config, dotconfig_lines, autoconf_lines):
"""Parse .config, defconfig, include/autoconf.mk for one config.
for faster processing.
"""
- def __init__(self, configs, options, progress, devnull, make_cmd,
- reference_src_dir, db_queue):
+ def __init__(self, toolchains, configs, options, progress, devnull,
+ make_cmd, reference_src_dir, db_queue):
"""Create a new process slot.
Arguments:
+ toolchains: Toolchains object containing toolchains.
configs: A list of CONFIGs to move.
options: option flags.
progress: A progress indicator.
source tree.
db_queue: output queue to write config info for the database
"""
+ self.toolchains = toolchains
self.options = options
self.progress = progress
self.build_dir = tempfile.mkdtemp()
def do_autoconf(self):
"""Run 'make AUTO_CONF_PATH'."""
- self.cross_compile = self.parser.get_cross_compile()
- if self.cross_compile is None:
+ arch = self.parser.get_arch()
+ try:
+ toolchain = self.toolchains.Select(arch)
+ except ValueError:
self.log += color_text(self.options.color, COLOR_YELLOW,
- "Compiler is missing. Do nothing.\n")
+ "Tool chain for '%s' is missing. Do nothing.\n % arch")
self.finish(False)
return
+ env = toolchain.MakeEnvironment(False)
cmd = list(self.make_cmd)
- if self.cross_compile:
- cmd.append('CROSS_COMPILE=%s' % self.cross_compile)
cmd.append('KCONFIG_IGNORE_DUPLICATES=1')
cmd.append(AUTO_CONF_PATH)
- self.ps = subprocess.Popen(cmd, stdout=self.devnull,
+ self.ps = subprocess.Popen(cmd, stdout=self.devnull, env=env,
stderr=subprocess.PIPE,
cwd=self.current_src_dir)
self.state = STATE_AUTOCONF
"""Controller of the array of subprocess slots."""
- def __init__(self, configs, options, progress, reference_src_dir, db_queue):
+ def __init__(self, toolchains, configs, options, progress,
+ reference_src_dir, db_queue):
"""Create a new slots controller.
Arguments:
+ toolchains: Toolchains object containing toolchains.
configs: A list of CONFIGs to move.
options: option flags.
progress: A progress indicator.
devnull = get_devnull()
make_cmd = get_make_cmd()
for i in range(options.jobs):
- self.slots.append(Slot(configs, options, progress, devnull,
- make_cmd, reference_src_dir, db_queue))
+ self.slots.append(Slot(toolchains, configs, options, progress,
+ devnull, make_cmd, reference_src_dir,
+ db_queue))
def add(self, defconfig):
"""Add a new subprocess if a vacant slot is found.
return self.src_dir
-def move_config(configs, options, db_queue):
+def move_config(toolchains, configs, options, db_queue):
"""Move config options to defconfig files.
Arguments:
defconfigs = get_all_defconfigs()
progress = Progress(len(defconfigs))
- slots = Slots(configs, options, progress, reference_src_dir, db_queue)
+ slots = Slots(toolchains, configs, options, progress, reference_src_dir,
+ db_queue)
# Main loop to process defconfig files:
# Add a new subprocess into a vacant slot.
if options.imply:
imply_flags = 0
- for flag in options.imply_flags.split():
- if flag == 'help' or flag not in IMPLY_FLAGS:
- print "Imply flags: (separate with ',')"
- for name, info in IMPLY_FLAGS.iteritems():
- print ' %-15s: %s' % (name, info[1])
- parser.print_usage()
- sys.exit(1)
- imply_flags |= IMPLY_FLAGS[flag][0]
+ if options.imply_flags == 'all':
+ imply_flags = -1
+
+ elif options.imply_flags:
+ for flag in options.imply_flags.split(','):
+ bad = flag not in IMPLY_FLAGS
+ if bad:
+ print "Invalid flag '%s'" % flag
+ if flag == 'help' or bad:
+ print "Imply flags: (separate with ',')"
+ for name, info in IMPLY_FLAGS.iteritems():
+ print ' %-15s: %s' % (name, info[1])
+ parser.print_usage()
+ sys.exit(1)
+ imply_flags |= IMPLY_FLAGS[flag][0]
do_imply_config(configs, options.add_imply, imply_flags,
options.skip_added)
if not options.cleanup_headers_only:
check_clean_directory()
- update_cross_compile(options.color)
- move_config(configs, options, db_queue)
+ bsettings.Setup('')
+ toolchains = toolchain.Toolchains()
+ toolchains.GetSettings()
+ toolchains.Scan(verbose=False)
+ move_config(toolchains, configs, options, db_queue)
db_queue.join()
if configs:
projects / u-boot / commitdiff