]> git.sur5r.net Git - u-boot/commitdiff
at91: Introduction of at91sam9g45 SOC.
authorSedji Gaouaou <sedji.gaouaou@atmel.com>
Thu, 9 Jul 2009 08:16:29 +0000 (10:16 +0200)
committerJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Sun, 12 Jul 2009 15:43:34 +0000 (17:43 +0200)
AT91sam9g45 series is an ARM 926ej-s SOC family clocked at 400/133MHz.
It embeds USB high speed host and device, LCD, DDR2 RAM, and a full set of
peripherals.

The first board that embeds at91sam9g45 chip is the AT91SAM9G45-EKES.
On the board you can find 2 USART, USB high speed,
a 480*272 LG lcd, ethernet, gpio/joystick/buttons.

Signed-off-by: Sedji Gaouaou <sedji.gaouaou@atmel.com>
20 files changed:
MAINTAINERS
MAKEALL
Makefile
board/atmel/at91sam9m10g45ek/Makefile [new file with mode: 0644]
board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c [new file with mode: 0644]
board/atmel/at91sam9m10g45ek/config.mk [new file with mode: 0644]
board/atmel/at91sam9m10g45ek/led.c [new file with mode: 0644]
cpu/arm926ejs/at91/Makefile
cpu/arm926ejs/at91/at91sam9m10g45_devices.c [new file with mode: 0644]
cpu/arm926ejs/at91/clock.c
doc/README.at91
drivers/net/macb.c
include/asm-arm/arch-at91/at91_pmc.h
include/asm-arm/arch-at91/at91sam9_matrix.h
include/asm-arm/arch-at91/at91sam9g45.h [new file with mode: 0644]
include/asm-arm/arch-at91/at91sam9g45_matrix.h [new file with mode: 0644]
include/asm-arm/arch-at91/clk.h
include/asm-arm/arch-at91/hardware.h
include/asm-arm/arch-at91/memory-map.h
include/configs/at91sam9m10g45ek.h [new file with mode: 0644]

index 705bac5a77b1fb85606c6998556feaab122ac92c..5a8f12c236f04d6af55a237a15d7c7a509ec21dd 100644 (file)
@@ -547,6 +547,9 @@ Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
 
        meesc           ARM926EJS (AT91SAM9263 SoC)
 
+Sedji Gaouaou<sedji.gaouaou@atmel.com>
+       at91sam9m10g45ek        ARM926EJS (AT91SAM9G45 SoC)
+
 Marius Gröger <mag@sysgo.de>
 
        impa7           ARM720T (EP7211)
diff --git a/MAKEALL b/MAKEALL
index 41f144553e0e579e9467b65557e1fcd3629b1c97..03ef5b45cdfe787531130f7bc49eef05ea87386f 100755 (executable)
--- a/MAKEALL
+++ b/MAKEALL
@@ -578,24 +578,25 @@ LIST_ARM_CORTEX_A8="              \
 ## AT91 Systems
 #########################################################################
 
-LIST_at91="            \
-       afeb9260        \
-       at91cap9adk     \
-       at91rm9200dk    \
-       at91rm9200ek    \
-       at91sam9260ek   \
-       at91sam9261ek   \
-       at91sam9263ek   \
-       at91sam9g20ek   \
-       at91sam9rlek    \
-       cmc_pu2         \
-       csb637          \
-       kb9202          \
-       meesc           \
-       mp2usb          \
-       m501sk          \
-       pm9261          \
-       pm9263          \
+LIST_at91="                    \
+       afeb9260                \
+       at91cap9adk             \
+       at91rm9200dk            \
+       at91rm9200ek            \
+       at91sam9260ek           \
+       at91sam9261ek           \
+       at91sam9263ek           \
+       at91sam9m10g45ek        \
+       at91sam9g20ek           \
+       at91sam9rlek            \
+       cmc_pu2                 \
+       csb637                  \
+       kb9202                  \
+       meesc                   \
+       mp2usb                  \
+       m501sk                  \
+       pm9261                  \
+       pm9263                  \
 "
 
 #########################################################################
index 2a06440249577b5fefae4a6f8dcefa2b010b2f9b..55a9648d78134c31773b62270fae97ae563f031b 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -2800,6 +2800,31 @@ meesc_config     :       unconfig
 pm9261_config  :       unconfig
        @$(MKCONFIG) $(@:_config=) arm arm926ejs pm9261 ronetix at91
 
+at91sam9m10g45ek_nandflash_config \
+at91sam9m10g45ek_dataflash_config \
+at91sam9m10g45ek_dataflash_cs0_config \
+at91sam9m10g45ek_config \
+at91sam9g45ekes_nandflash_config \
+at91sam9g45ekes_dataflash_config \
+at91sam9g45ekes_dataflash_cs0_config \
+at91sam9g45ekes_config :       unconfig
+       @mkdir -p $(obj)include
+               @if [ "$(findstring 9m10,$@)" ] ; then \
+               echo "#define CONFIG_AT91SAM9M10G45EK 1"        >>$(obj)include/config.h ; \
+               $(XECHO) "... 9M10G45 Variant" ; \
+       else \
+               echo "#define CONFIG_AT91SAM9G45EKES 1" >>$(obj)include/config.h ; \
+       fi;
+
+       @if [ "$(findstring _nandflash,$@)" ] ; then \
+               echo "#define CONFIG_SYS_USE_NANDFLASH 1"       >>$(obj)include/config.h ; \
+               $(XECHO) "... with environment variable in NAND FLASH" ; \
+       else \
+               echo "#define CONFIG_ATMEL_SPI 1"       >>$(obj)include/config.h ; \
+               $(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \
+       fi;
+       @$(MKCONFIG) -a at91sam9m10g45ek arm arm926ejs at91sam9m10g45ek atmel at91
+
 pm9263_config  :       unconfig
        @$(MKCONFIG) $(@:_config=) arm arm926ejs pm9263 ronetix at91
 
diff --git a/board/atmel/at91sam9m10g45ek/Makefile b/board/atmel/at91sam9m10g45ek/Makefile
new file mode 100644 (file)
index 0000000..4caf1e4
--- /dev/null
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).a
+
+COBJS-y += at91sam9m10g45ek.o
+COBJS-y += led.o
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS-y))
+SOBJS  := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):        $(obj).depend $(OBJS) $(SOBJS)
+       $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+       rm -f $(SOBJS) $(OBJS)
+
+distclean:     clean
+       rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
new file mode 100644 (file)
index 0000000..45a14a9
--- /dev/null
@@ -0,0 +1,334 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/sizes.h>
+#include <asm/arch/at91sam9g45.h>
+#include <asm/arch/at91sam9_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+#include <asm/arch/hardware.h>
+#include <lcd.h>
+#include <atmel_lcdc.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+static void at91sam9m10g45ek_nand_hw_init(void)
+{
+       unsigned long csa;
+
+       /* Enable CS3 */
+       csa = at91_sys_read(AT91_MATRIX_EBICSA);
+       at91_sys_write(AT91_MATRIX_EBICSA,
+                      csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
+
+       /* Configure SMC CS3 for NAND/SmartMedia */
+       at91_sys_write(AT91_SMC_SETUP(3),
+                      AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
+                      AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
+       at91_sys_write(AT91_SMC_PULSE(3),
+                      AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(3) |
+                      AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(2));
+       at91_sys_write(AT91_SMC_CYCLE(3),
+                      AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(4));
+       at91_sys_write(AT91_SMC_MODE(3),
+                      AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+                      AT91_SMC_EXNWMODE_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+                      AT91_SMC_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+                      AT91_SMC_DBW_8 |
+#endif
+                      AT91_SMC_TDF_(3));
+
+       at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIOC);
+
+       /* Configure RDY/BSY */
+       at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+       /* Enable NandFlash */
+       at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void at91sam9m10g45ek_macb_hw_init(void)
+{
+       unsigned long rstc;
+
+       /* Enable clock */
+       at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_EMAC);
+
+       /*
+        * Disable pull-up on:
+        *      RXDV (PA15) => PHY normal mode (not Test mode)
+        *      ERX0 (PA12) => PHY ADDR0
+        *      ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
+        *
+        * PHY has internal pull-down
+        */
+       writel(pin_to_mask(AT91_PIN_PA15) |
+              pin_to_mask(AT91_PIN_PA12) |
+              pin_to_mask(AT91_PIN_PA13),
+              pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
+
+       rstc = at91_sys_read(AT91_RSTC_MR);
+
+       /* Need to reset PHY -> 500ms reset */
+       at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+                                    (AT91_RSTC_ERSTL & (0x0D << 8)) |
+                                    AT91_RSTC_URSTEN);
+
+       at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
+
+       /* Wait for end hardware reset */
+       while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
+
+       /* Restore NRST value */
+       at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+                                    (rstc) |
+                                    AT91_RSTC_URSTEN);
+
+       /* Re-enable pull-up */
+       writel(pin_to_mask(AT91_PIN_PA15) |
+              pin_to_mask(AT91_PIN_PA12) |
+              pin_to_mask(AT91_PIN_PA13),
+              pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
+
+       at91_macb_hw_init();
+}
+#endif
+
+#ifdef CONFIG_LCD
+
+vidinfo_t panel_info = {
+       vl_col:         480,
+       vl_row:         272,
+       vl_clk:         9000000,
+       vl_sync:        ATMEL_LCDC_INVLINE_NORMAL |
+                       ATMEL_LCDC_INVFRAME_NORMAL,
+       vl_bpix:        3,
+       vl_tft:         1,
+       vl_hsync_len:   45,
+       vl_left_margin: 1,
+       vl_right_margin:1,
+       vl_vsync_len:   1,
+       vl_upper_margin:40,
+       vl_lower_margin:1,
+       mmio:           AT91SAM9G45_LCDC_BASE,
+};
+
+
+void lcd_enable(void)
+{
+       at91_set_A_periph(AT91_PIN_PE6, 1);     /* power up */
+}
+
+void lcd_disable(void)
+{
+       at91_set_A_periph(AT91_PIN_PE6, 0);     /* power down */
+}
+
+static void at91sam9m10g45ek_lcd_hw_init(void)
+{
+       at91_set_A_periph(AT91_PIN_PE0, 0);     /* LCDDPWR */
+       at91_set_A_periph(AT91_PIN_PE2, 0);     /* LCDCC */
+       at91_set_A_periph(AT91_PIN_PE3, 0);     /* LCDVSYNC */
+       at91_set_A_periph(AT91_PIN_PE4, 0);     /* LCDHSYNC */
+       at91_set_A_periph(AT91_PIN_PE5, 0);     /* LCDDOTCK */
+
+       at91_set_A_periph(AT91_PIN_PE7, 0);     /* LCDD0 */
+       at91_set_A_periph(AT91_PIN_PE8, 0);     /* LCDD1 */
+       at91_set_A_periph(AT91_PIN_PE9, 0);     /* LCDD2 */
+       at91_set_A_periph(AT91_PIN_PE10, 0);    /* LCDD3 */
+       at91_set_A_periph(AT91_PIN_PE11, 0);    /* LCDD4 */
+       at91_set_A_periph(AT91_PIN_PE12, 0);    /* LCDD5 */
+       at91_set_A_periph(AT91_PIN_PE13, 0);    /* LCDD6 */
+       at91_set_A_periph(AT91_PIN_PE14, 0);    /* LCDD7 */
+       at91_set_A_periph(AT91_PIN_PE15, 0);    /* LCDD8 */
+       at91_set_A_periph(AT91_PIN_PE16, 0);    /* LCDD9 */
+       at91_set_A_periph(AT91_PIN_PE17, 0);    /* LCDD10 */
+       at91_set_A_periph(AT91_PIN_PE18, 0);    /* LCDD11 */
+       at91_set_A_periph(AT91_PIN_PE19, 0);    /* LCDD12 */
+       at91_set_B_periph(AT91_PIN_PE20, 0);    /* LCDD13 */
+       at91_set_A_periph(AT91_PIN_PE21, 0);    /* LCDD14 */
+       at91_set_A_periph(AT91_PIN_PE22, 0);    /* LCDD15 */
+       at91_set_A_periph(AT91_PIN_PE23, 0);    /* LCDD16 */
+       at91_set_A_periph(AT91_PIN_PE24, 0);    /* LCDD17 */
+       at91_set_A_periph(AT91_PIN_PE25, 0);    /* LCDD18 */
+       at91_set_A_periph(AT91_PIN_PE26, 0);    /* LCDD19 */
+       at91_set_A_periph(AT91_PIN_PE27, 0);    /* LCDD20 */
+       at91_set_B_periph(AT91_PIN_PE28, 0);    /* LCDD21 */
+       at91_set_A_periph(AT91_PIN_PE29, 0);    /* LCDD22 */
+       at91_set_A_periph(AT91_PIN_PE30, 0);    /* LCDD23 */
+
+       at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_LCDC);
+
+       gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
+}
+
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+
+void lcd_show_board_info(void)
+{
+       ulong dram_size, nand_size;
+       int i;
+       char temp[32];
+
+       lcd_printf ("%s\n", U_BOOT_VERSION);
+       lcd_printf ("(C) 2008 ATMEL Corp\n");
+       lcd_printf ("at91support@atmel.com\n");
+       lcd_printf ("%s CPU at %s MHz\n",
+               AT91_CPU_NAME,
+               strmhz(temp, get_cpu_clk_rate()));
+
+       dram_size = 0;
+       for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+               dram_size += gd->bd->bi_dram[i].size;
+       nand_size = 0;
+       for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+               nand_size += nand_info[i].size;
+       lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
+               dram_size >> 20,
+               nand_size >> 20 );
+}
+#endif /* CONFIG_LCD_INFO */
+#endif
+
+int board_init(void)
+{
+       /* Enable Ctrlc */
+       console_init_f();
+
+       /* arch number of AT91SAM9M10G45EK-Board */
+#ifdef CONFIG_AT91SAM9M10G45EK
+       gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK;
+#elif defined CONFIG_AT91SAM9G45EKES
+       gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES;
+#endif
+       /* adress of boot parameters */
+       gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+       at91_serial_hw_init();
+#ifdef CONFIG_CMD_NAND
+       at91sam9m10g45ek_nand_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+       at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_ATMEL_SPI
+       at91_spi0_hw_init(1 << 4);
+#endif
+
+#ifdef CONFIG_MACB
+       at91sam9m10g45ek_macb_hw_init();
+#endif
+
+#ifdef CONFIG_LCD
+       at91sam9m10g45ek_lcd_hw_init();
+#endif
+       return 0;
+}
+
+int dram_init(void)
+{
+       gd->bd->bi_dram[0].start = PHYS_SDRAM;
+       gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+       return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+#ifdef CONFIG_MACB
+       /*
+        * Initialize ethernet HW addr prior to starting Linux,
+        * needed for nfsroot
+        */
+       eth_init(gd->bd);
+#endif
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+       int rc = 0;
+#ifdef CONFIG_MACB
+       rc = macb_eth_initialize(0, (void *)AT91SAM9G45_BASE_EMAC, 0x00);
+#endif
+       return rc;
+}
+
+/* SPI chip select control */
+#ifdef CONFIG_ATMEL_SPI
+#include <spi.h>
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+       return bus == 0 && cs < 2;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+       switch(slave->cs) {
+               case 1:
+                       at91_set_gpio_output(AT91_PIN_PB18, 0);
+                       break;
+               case 0:
+               default:
+                       at91_set_gpio_output(AT91_PIN_PB3, 0);
+                       break;
+       }
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+       switch(slave->cs) {
+               case 1:
+                       at91_set_gpio_output(AT91_PIN_PB18, 1);
+                       break;
+               case 0:
+               default:
+                       at91_set_gpio_output(AT91_PIN_PB3, 1);
+               break;
+       }
+}
+#endif /* CONFIG_ATMEL_SPI */
diff --git a/board/atmel/at91sam9m10g45ek/config.mk b/board/atmel/at91sam9m10g45ek/config.mk
new file mode 100644 (file)
index 0000000..7fe9d03
--- /dev/null
@@ -0,0 +1 @@
+TEXT_BASE = 0x73f00000
diff --git a/board/atmel/at91sam9m10g45ek/led.c b/board/atmel/at91sam9m10g45ek/led.c
new file mode 100644 (file)
index 0000000..ff59a2d
--- /dev/null
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9g45.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+
+void coloured_LED_init(void)
+{
+       /* Enable clock */
+       at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIODE);
+
+       at91_set_gpio_output(CONFIG_RED_LED, 1);
+       at91_set_gpio_output(CONFIG_GREEN_LED, 1);
+
+       at91_set_gpio_value(CONFIG_RED_LED, 0);
+       at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+}
index 3da89f4fba9efd81ff952dc87677bd6dc57e9305..69051c1cd590584b685664ff000058424daa1326 100644 (file)
@@ -31,6 +31,8 @@ COBJS-$(CONFIG_AT91SAM9G20)   += at91sam9260_devices.o
 COBJS-$(CONFIG_AT91SAM9261)    += at91sam9261_devices.o
 COBJS-$(CONFIG_AT91SAM9263)    += at91sam9263_devices.o
 COBJS-$(CONFIG_AT91SAM9RL)     += at91sam9rl_devices.o
+COBJS-$(CONFIG_AT91SAM9M10G45) += at91sam9m10g45_devices.o
+COBJS-$(CONFIG_AT91SAM9G45)    += at91sam9m10g45_devices.o
 COBJS-$(CONFIG_AT91_LED)       += led.o
 COBJS-y += clock.o
 COBJS-y += cpu.o
diff --git a/cpu/arm926ejs/at91/at91sam9m10g45_devices.c b/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
new file mode 100644 (file)
index 0000000..98d90f2
--- /dev/null
@@ -0,0 +1,175 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+
+void at91_serial0_hw_init(void)
+{
+       at91_set_A_periph(AT91_PIN_PB19, 1);    /* TXD0 */
+       at91_set_A_periph(AT91_PIN_PB18, 0);    /* RXD0 */
+       at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US0);
+}
+
+void at91_serial1_hw_init(void)
+{
+       at91_set_A_periph(AT91_PIN_PB4, 1);             /* TXD1 */
+       at91_set_A_periph(AT91_PIN_PB5, 0);             /* RXD1 */
+       at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US1);
+}
+
+void at91_serial2_hw_init(void)
+{
+       at91_set_A_periph(AT91_PIN_PD6, 1);             /* TXD2 */
+       at91_set_A_periph(AT91_PIN_PD7, 0);             /* RXD2 */
+       at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US2);
+}
+
+void at91_serial3_hw_init(void)
+{
+       at91_set_A_periph(AT91_PIN_PB12, 0);    /* DRXD */
+       at91_set_A_periph(AT91_PIN_PB13, 1);    /* DTXD */
+       at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);;
+}
+
+void at91_serial_hw_init(void)
+{
+#ifdef CONFIG_USART0
+       at91_serial0_hw_init();
+#endif
+
+#ifdef CONFIG_USART1
+       at91_serial1_hw_init();
+#endif
+
+#ifdef CONFIG_USART2
+       at91_serial2_hw_init();
+#endif
+
+#ifdef CONFIG_USART3   /* DBGU */
+       at91_serial3_hw_init();
+#endif
+}
+
+#ifdef CONFIG_ATMEL_SPI
+void at91_spi0_hw_init(unsigned long cs_mask)
+{
+       at91_set_A_periph(AT91_PIN_PB0, 0);     /* SPI0_MISO */
+       at91_set_A_periph(AT91_PIN_PB1, 0);     /* SPI0_MOSI */
+       at91_set_A_periph(AT91_PIN_PB2, 0);     /* SPI0_SPCK */
+
+       /* Enable clock */
+       at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_SPI0);
+
+       if (cs_mask & (1 << 0)) {
+               at91_set_A_periph(AT91_PIN_PB3, 0);
+       }
+       if (cs_mask & (1 << 1)) {
+               at91_set_B_periph(AT91_PIN_PB18, 0);
+       }
+       if (cs_mask & (1 << 2)) {
+               at91_set_B_periph(AT91_PIN_PB19, 0);
+       }
+       if (cs_mask & (1 << 3)) {
+               at91_set_B_periph(AT91_PIN_PD27, 0);
+       }
+       if (cs_mask & (1 << 4)) {
+               at91_set_gpio_output(AT91_PIN_PB3, 0);
+       }
+       if (cs_mask & (1 << 5)) {
+               at91_set_gpio_output(AT91_PIN_PB18, 0);
+       }
+       if (cs_mask & (1 << 6)) {
+               at91_set_gpio_output(AT91_PIN_PB19, 0);
+       }
+       if (cs_mask & (1 << 7)) {
+               at91_set_gpio_output(AT91_PIN_PD27, 0);
+       }
+}
+
+void at91_spi1_hw_init(unsigned long cs_mask)
+{
+       at91_set_A_periph(AT91_PIN_PB14, 0);    /* SPI1_MISO */
+       at91_set_A_periph(AT91_PIN_PB15, 0);    /* SPI1_MOSI */
+       at91_set_A_periph(AT91_PIN_PB16, 0);    /* SPI1_SPCK */
+
+       /* Enable clock */
+       at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_SPI1);
+
+       if (cs_mask & (1 << 0)) {
+               at91_set_A_periph(AT91_PIN_PB17, 0);
+       }
+       if (cs_mask & (1 << 1)) {
+               at91_set_B_periph(AT91_PIN_PD28, 0);
+       }
+       if (cs_mask & (1 << 2)) {
+               at91_set_A_periph(AT91_PIN_PD18, 0);
+       }
+       if (cs_mask & (1 << 3)) {
+               at91_set_A_periph(AT91_PIN_PD19, 0);
+       }
+       if (cs_mask & (1 << 4)) {
+               at91_set_gpio_output(AT91_PIN_PB17, 0);
+       }
+       if (cs_mask & (1 << 5)) {
+               at91_set_gpio_output(AT91_PIN_PD28, 0);
+       }
+       if (cs_mask & (1 << 6)) {
+               at91_set_gpio_output(AT91_PIN_PD18, 0);
+       }
+       if (cs_mask & (1 << 7)) {
+               at91_set_gpio_output(AT91_PIN_PD19, 0);
+       }
+
+}
+#endif
+
+#ifdef CONFIG_MACB
+void at91_macb_hw_init(void)
+{
+       at91_set_A_periph(AT91_PIN_PA17, 0);    /* ETXCK_EREFCK */
+       at91_set_A_periph(AT91_PIN_PA15, 0);    /* ERXDV */
+       at91_set_A_periph(AT91_PIN_PA12, 0);    /* ERX0 */
+       at91_set_A_periph(AT91_PIN_PA13, 0);    /* ERX1 */
+       at91_set_A_periph(AT91_PIN_PA16, 0);    /* ERXER */
+       at91_set_A_periph(AT91_PIN_PA14, 0);    /* ETXEN */
+       at91_set_A_periph(AT91_PIN_PA10, 0);    /* ETX0 */
+       at91_set_A_periph(AT91_PIN_PA11, 0);    /* ETX1 */
+       at91_set_A_periph(AT91_PIN_PA19, 0);    /* EMDIO */
+       at91_set_A_periph(AT91_PIN_PA18, 0);    /* EMDC */
+#ifndef CONFIG_RMII
+       at91_set_B_periph(AT91_PIN_PA29, 0);    /* ECRS */
+       at91_set_B_periph(AT91_PIN_PA30, 0);    /* ECOL */
+       at91_set_B_periph(AT91_PIN_PA8,  0);    /* ERX2 */
+       at91_set_B_periph(AT91_PIN_PA9,  0);    /* ERX3 */
+       at91_set_B_periph(AT91_PIN_PA28, 0);    /* ERXCK */
+       at91_set_B_periph(AT91_PIN_PA6,  0);    /* ETX2 */
+       at91_set_B_periph(AT91_PIN_PA7,  0);    /* ETX3 */
+       at91_set_B_periph(AT91_PIN_PA27, 0);    /* ETXER */
+#endif
+}
+#endif
index 9f03468b6c9954efb0f23756a3f443060851303f..574f48824c0e23ddc8a64e2bb272582c6087270f 100644 (file)
@@ -183,15 +183,23 @@ int at91_clock_init(unsigned long main_clock)
         * For now, assume this parentage won't change.
         */
        mckr = at91_sys_read(AT91_PMC_MCKR);
+#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
+       /* plla divisor by 2 */
+       plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
+#endif
        freq = mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_CSS);
+
        freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2));                   /* prescale */
 #if defined(CONFIG_AT91RM9200)
        mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8));       /* mdiv */
 #elif defined(CONFIG_AT91SAM9G20)
        mck_rate_hz = (mckr & AT91_PMC_MDIV) ?
-               freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq;    /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
+               freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq;            /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
        if (mckr & AT91_PMC_PDIV)
-               freq /= 2;              /* processor clock division */
+               freq /= 2;                                              /* processor clock division */
+#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
+       mck_rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
+               freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
 #else
        mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));      /* mdiv */
 #endif
index 4a2c56bd9ed0276aa01fcd52ff1fb0c27eb5099a..269d0729a0e6f0522cec7e62f69778cac23a96f6 100644 (file)
@@ -74,6 +74,26 @@ Environment variables
                make at91sam9263ek_norflash_boot_config - boot from nor falsh
 
 
+------------------------------------------------------------------------------
+AT91SAM9M10G45EK
+------------------------------------------------------------------------------
+
+Memory map
+       0x20000000 - 23FFFFFF   SDRAM (64 MB)
+       0xC0000000 - Cxxxxxxx   Atmel Dataflash card (J12)
+
+Environment variables
+
+       U-Boot environment variables can be stored at different places:
+               - Dataflash on SPI chip select 0 (dataflash card)
+               - Nand flash.
+
+       You can choose your storage location at config step (here for at91sam9m10g45ek) :
+               make at91sam9m10g45ek_config                    - use data flash (spi cs0) (default)
+               make at91sam9m10g45ek_nandflash_config          - use nand flash
+               make at91sam9m10g45ek_dataflash_cs0_config      - use data flash (spi cs0)
+
+
 ------------------------------------------------------------------------------
 AT91SAM9RLEK
 ------------------------------------------------------------------------------
index 6de0a04410aa5e0ee976c344f06dbc5eee6676a9..c1843539f99adb5373fea56b88606b034d0fab1a 100644 (file)
@@ -447,14 +447,16 @@ static int macb_init(struct eth_device *netdev, bd_t *bd)
        /* choose RMII or MII mode. This depends on the board */
 #ifdef CONFIG_RMII
 #if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
-    defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20)
+    defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \
+       defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
        macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
 #else
        macb_writel(macb, USRIO, 0);
 #endif
 #else
 #if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
-    defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20)
+    defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \
+       defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
        macb_writel(macb, USRIO, MACB_BIT(CLKEN));
 #else
        macb_writel(macb, USRIO, MACB_BIT(MII));
index a82955c1bf2e95409810b2a5c511d8314430d4c7..9fe94c7e4cc8791cb13d669d982f29714e730b3c 100644 (file)
@@ -89,6 +89,7 @@
 #define                        AT91SAM9_PMC_MDIV_1             (0 << 8)        /* [SAM9,CAP9 only] */
 #define                        AT91SAM9_PMC_MDIV_2             (1 << 8)
 #define                        AT91SAM9_PMC_MDIV_4             (2 << 8)
+#define                        AT91SAM9_PMC_MDIV_3             (3 << 8)        /* [some SAM9 only] */
 #define                        AT91SAM9_PMC_MDIV_6             (3 << 8)
 #define                AT91_PMC_PDIV           (1 << 12)               /* Processor Clock Division [some SAM9 only] */
 #define                        AT91_PMC_PDIV_1                 (0 << 12)
index 913f37479085d3d6ececae5a5c21d28a375d2a23..6d97189d275f7b76b269ced3f35e36590088deb8 100644 (file)
@@ -21,6 +21,8 @@
 #include <asm/arch/at91sam9rl_matrix.h>
 #elif defined(CONFIG_AT91CAP9)
 #include <asm/arch/at91cap9_matrix.h>
+#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
+#include <asm/arch/at91sam9g45_matrix.h>
 #else
 #error "Unsupported AT91SAM9/CAP9 processor"
 #endif
diff --git a/include/asm-arm/arch-at91/at91sam9g45.h b/include/asm-arm/arch-at91/at91sam9g45.h
new file mode 100644 (file)
index 0000000..0feed9c
--- /dev/null
@@ -0,0 +1,139 @@
+/*
+ * Chip-specific header file for the AT91SAM9M1x family
+ *
+ *  Copyright (C) 2008 Atmel Corporation.
+ *
+ * Common definitions.
+ * Based on AT91SAM9G45 preliminary datasheet.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM9G45_H
+#define AT91SAM9G45_H
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91_ID_FIQ            0       /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS            1       /* System Controller Interrupt */
+#define AT91SAM9G45_ID_PIOA    2       /* Parallel I/O Controller A */
+#define AT91SAM9G45_ID_PIOB    3       /* Parallel I/O Controller B */
+#define AT91SAM9G45_ID_PIOC    4       /* Parallel I/O Controller C */
+#define AT91SAM9G45_ID_PIODE   5       /* Parallel I/O Controller D and E */
+#define AT91SAM9G45_ID_TRNG    6       /* True Random Number Generator */
+#define AT91SAM9G45_ID_US0     7       /* USART 0 */
+#define AT91SAM9G45_ID_US1     8       /* USART 1 */
+#define AT91SAM9G45_ID_US2     9       /* USART 2 */
+#define AT91SAM9G45_ID_US3     10      /* USART 3 */
+#define AT91SAM9G45_ID_MCI0    11      /* High Speed Multimedia Card Interface 0 */
+#define AT91SAM9G45_ID_TWI0    12      /* Two-Wire Interface 0 */
+#define AT91SAM9G45_ID_TWI1    13      /* Two-Wire Interface 1 */
+#define AT91SAM9G45_ID_SPI0    14      /* Serial Peripheral Interface 0 */
+#define AT91SAM9G45_ID_SPI1    15      /* Serial Peripheral Interface 1 */
+#define AT91SAM9G45_ID_SSC0    16      /* Synchronous Serial Controller 0 */
+#define AT91SAM9G45_ID_SSC1    17      /* Synchronous Serial Controller 1 */
+#define AT91SAM9G45_ID_TCB     18      /* Timer Counter 0, 1, 2, 3, 4 and 5 */
+#define AT91SAM9G45_ID_PWMC    19      /* Pulse Width Modulation Controller */
+#define AT91SAM9G45_ID_TSC     20      /* Touch Screen ADC Controller */
+#define AT91SAM9G45_ID_DMA     21      /* DMA Controller */
+#define AT91SAM9G45_ID_UHPHS   22      /* USB Host High Speed */
+#define AT91SAM9G45_ID_LCDC    23      /* LCD Controller */
+#define AT91SAM9G45_ID_AC97C   24      /* AC97 Controller */
+#define AT91SAM9G45_ID_EMAC    25      /* Ethernet MAC */
+#define AT91SAM9G45_ID_ISI     26      /* Image Sensor Interface */
+#define AT91SAM9G45_ID_UDPHS   27      /* USB Device High Speed */
+#define AT91SAM9G45_ID_AESTDESSHA 28   /* AES + T-DES + SHA */
+#define AT91SAM9G45_ID_MCI1    29      /* High Speed Multimedia Card Interface 1 */
+#define AT91SAM9G45_ID_VDEC    30      /* Video Decoder */
+#define AT91SAM9G45_ID_IRQ0    31      /* Advanced Interrupt Controller */
+
+/*
+ * User Peripheral physical base addresses.
+ */
+#define AT91SAM9G45_BASE_UDPHS         0xfff78000
+#define AT91SAM9G45_BASE_TC0           0xfff7c000
+#define AT91SAM9G45_BASE_TC1           0xfff7c040
+#define AT91SAM9G45_BASE_TC2           0xfff7c080
+#define AT91SAM9G45_BASE_MCI0          0xfff80000
+#define AT91SAM9G45_BASE_TWI0          0xfff84000
+#define AT91SAM9G45_BASE_TWI1          0xfff88000
+#define AT91SAM9G45_BASE_US0           0xfff8c000
+#define AT91SAM9G45_BASE_US1           0xfff90000
+#define AT91SAM9G45_BASE_US2           0xfff94000
+#define AT91SAM9G45_BASE_US3           0xfff98000
+#define AT91SAM9G45_BASE_SSC0          0xfff9c000
+#define AT91SAM9G45_BASE_SSC1          0xfffa0000
+#define AT91SAM9G45_BASE_SPI0          0xfffa4000
+#define AT91SAM9G45_BASE_SPI1          0xfffa8000
+#define AT91SAM9G45_BASE_AC97C         0xfffac000
+#define AT91SAM9G45_BASE_TSC           0xfffb0000
+#define AT91SAM9G45_BASE_ISI           0xfffb4000
+#define AT91SAM9G45_BASE_PWMC          0xfffb8000
+#define AT91SAM9G45_BASE_EMAC          0xfffbc000
+#define AT91SAM9G45_BASE_AES           0xfffc0000
+#define AT91SAM9G45_BASE_TDES          0xfffc4000
+#define AT91SAM9G45_BASE_SHA           0xfffc8000
+#define AT91SAM9G45_BASE_TRNG          0xfffcc000
+#define AT91SAM9G45_BASE_MCI1          0xfffd0000
+#define AT91SAM9G45_BASE_TC3           0xfffd4000
+#define AT91SAM9G45_BASE_TC4           0xfffd4040
+#define AT91SAM9G45_BASE_TC5           0xfffd4080
+#define AT91_BASE_SYS                  0xffffe200
+
+/*
+ * System Peripherals (offset from AT91_BASE_SYS)
+ */
+#define AT91_ECC       (0xffffe200 - AT91_BASE_SYS)
+#define AT91_DDRSDRC1  (0xffffe400 - AT91_BASE_SYS)
+#define AT91_DDRSDRC0  (0xffffe600 - AT91_BASE_SYS)
+#define AT91_SMC       (0xffffe800 - AT91_BASE_SYS)
+#define AT91_MATRIX    (0xffffea00 - AT91_BASE_SYS)
+#define AT91_DMA       (0xffffec00 - AT91_BASE_SYS)
+#define AT91_DBGU      (0xffffee00 - AT91_BASE_SYS)
+#define AT91_AIC       (0xfffff000 - AT91_BASE_SYS)
+#define AT91_PIOA      (0xfffff200 - AT91_BASE_SYS)
+#define AT91_PIOB      (0xfffff400 - AT91_BASE_SYS)
+#define AT91_PIOC      (0xfffff600 - AT91_BASE_SYS)
+#define AT91_PIOD      (0xfffff800 - AT91_BASE_SYS)
+#define AT91_PIOE      (0xfffffa00 - AT91_BASE_SYS)
+#define AT91_PMC       (0xfffffc00 - AT91_BASE_SYS)
+#define AT91_RSTC      (0xfffffd00 - AT91_BASE_SYS)
+#define AT91_SHDWC     (0xfffffd10 - AT91_BASE_SYS)
+#define AT91_RTT       (0xfffffd20 - AT91_BASE_SYS)
+#define AT91_PIT       (0xfffffd30 - AT91_BASE_SYS)
+#define AT91_WDT       (0xfffffd40 - AT91_BASE_SYS)
+#define AT91_GPBR      (0xfffffd60 - AT91_BASE_SYS)
+#define AT91_RTC       (0xfffffdb0 - AT91_BASE_SYS)
+
+#define AT91_USART0    AT91SAM9G45_BASE_US0
+#define AT91_USART1    AT91SAM9G45_BASE_US1
+#define AT91_USART2    AT91SAM9G45_BASE_US2
+#define AT91_USART3    AT91SAM9G45_BASE_US3
+
+/*
+ * Internal Memory.
+ */
+#define AT91SAM9G45_SRAM_BASE  0x00300000      /* Internal SRAM base address */
+#define AT91SAM9G45_SRAM_SIZE  SZ_64K          /* Internal SRAM size (64Kb) */
+
+#define AT91SAM9G45_ROM_BASE   0x00400000      /* Internal ROM base address */
+#define AT91SAM9G45_ROM_SIZE   SZ_64K          /* Internal ROM size (64Kb) */
+
+#define AT91SAM9G45_LCDC_BASE  0x00500000      /* LCD Controller */
+#define AT91SAM9G45_UDPHS_FIFO 0x00600000      /* USB Device HS controller */
+#define AT91SAM9G45_HCI_BASE   0x00700000      /* USB Host controller (OHCI) */
+#define AT91SAM9G45_EHCI_BASE  0x00800000      /* USB Host controller (EHCI) */
+#define AT91SAM9G45_VDEC_BASE  0x00900000      /* Video Decoder Controller */
+
+#define CONFIG_DRAM_BASE       AT91_CHIPSELECT_6
+
+/*
+ * Cpu Name
+ */
+#define AT91_CPU_NAME  "AT91SAM9G45"
+
+#endif
diff --git a/include/asm-arm/arch-at91/at91sam9g45_matrix.h b/include/asm-arm/arch-at91/at91sam9g45_matrix.h
new file mode 100644 (file)
index 0000000..1620e1b
--- /dev/null
@@ -0,0 +1,153 @@
+/*
+ * Matrix-centric header file for the AT91SAM9M1x family
+ *
+ *  Copyright (C) 2008 Atmel Corporation.
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ * Based on AT91SAM9G45 preliminary datasheet.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM9G45_MATRIX_H
+#define AT91SAM9G45_MATRIX_H
+
+#define AT91_MATRIX_MCFG0      (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
+#define AT91_MATRIX_MCFG1      (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
+#define AT91_MATRIX_MCFG2      (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
+#define AT91_MATRIX_MCFG3      (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
+#define AT91_MATRIX_MCFG4      (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
+#define AT91_MATRIX_MCFG5      (AT91_MATRIX + 0x14)    /* Master Configuration Register 5 */
+#define AT91_MATRIX_MCFG6      (AT91_MATRIX + 0x18)    /* Master Configuration Register 6 */
+#define AT91_MATRIX_MCFG7      (AT91_MATRIX + 0x1C)    /* Master Configuration Register 7 */
+#define AT91_MATRIX_MCFG8      (AT91_MATRIX + 0x20)    /* Master Configuration Register 8 */
+#define AT91_MATRIX_MCFG9      (AT91_MATRIX + 0x24)    /* Master Configuration Register 9 */
+#define AT91_MATRIX_MCFG10     (AT91_MATRIX + 0x28)    /* Master Configuration Register 10 */
+#define AT91_MATRIX_MCFG11     (AT91_MATRIX + 0x2C)    /* Master Configuration Register 11 */
+#define                AT91_MATRIX_ULBT        (7 << 0)        /* Undefined Length Burst Type */
+#define                        AT91_MATRIX_ULBT_INFINITE       (0 << 0)
+#define                        AT91_MATRIX_ULBT_SINGLE         (1 << 0)
+#define                        AT91_MATRIX_ULBT_FOUR           (2 << 0)
+#define                        AT91_MATRIX_ULBT_EIGHT          (3 << 0)
+#define                        AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
+#define                        AT91_MATRIX_ULBT_THIRTYTWO      (5 << 0)
+#define                        AT91_MATRIX_ULBT_SIXTYFOUR      (6 << 0)
+#define                        AT91_MATRIX_ULBT_128            (7 << 0)
+
+#define AT91_MATRIX_SCFG0      (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1      (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2      (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3      (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4      (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
+#define AT91_MATRIX_SCFG5      (AT91_MATRIX + 0x54)    /* Slave Configuration Register 5 */
+#define AT91_MATRIX_SCFG6      (AT91_MATRIX + 0x58)    /* Slave Configuration Register 6 */
+#define AT91_MATRIX_SCFG7      (AT91_MATRIX + 0x5C)    /* Slave Configuration Register 7 */
+#define                AT91_MATRIX_SLOT_CYCLE          (0x1ff << 0)    /* Maximum Number of Allowed Cycles for a Burst */
+#define                AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
+#define                        AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
+#define                        AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
+#define                        AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
+#define                AT91_MATRIX_FIXED_DEFMSTR       (0xf  << 18)    /* Fixed Index of Default Master */
+
+#define AT91_MATRIX_PRAS0      (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
+#define AT91_MATRIX_PRBS0      (AT91_MATRIX + 0x84)    /* Priority Register B for Slave 0 */
+#define AT91_MATRIX_PRAS1      (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
+#define AT91_MATRIX_PRBS1      (AT91_MATRIX + 0x8C)    /* Priority Register B for Slave 1 */
+#define AT91_MATRIX_PRAS2      (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
+#define AT91_MATRIX_PRBS2      (AT91_MATRIX + 0x94)    /* Priority Register B for Slave 2 */
+#define AT91_MATRIX_PRAS3      (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
+#define AT91_MATRIX_PRBS3      (AT91_MATRIX + 0x9C)    /* Priority Register B for Slave 3 */
+#define AT91_MATRIX_PRAS4      (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
+#define AT91_MATRIX_PRBS4      (AT91_MATRIX + 0xA4)    /* Priority Register B for Slave 4 */
+#define AT91_MATRIX_PRAS5      (AT91_MATRIX + 0xA8)    /* Priority Register A for Slave 5 */
+#define AT91_MATRIX_PRBS5      (AT91_MATRIX + 0xAC)    /* Priority Register B for Slave 5 */
+#define AT91_MATRIX_PRAS6      (AT91_MATRIX + 0xB0)    /* Priority Register A for Slave 6 */
+#define AT91_MATRIX_PRBS6      (AT91_MATRIX + 0xB4)    /* Priority Register B for Slave 6 */
+#define AT91_MATRIX_PRAS7      (AT91_MATRIX + 0xB8)    /* Priority Register A for Slave 7 */
+#define AT91_MATRIX_PRBS7      (AT91_MATRIX + 0xBC)    /* Priority Register B for Slave 7 */
+#define                AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
+#define                AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
+#define                AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
+#define                AT91_MATRIX_M3PR                (3 << 12)       /* Master 3 Priority */
+#define                AT91_MATRIX_M4PR                (3 << 16)       /* Master 4 Priority */
+#define                AT91_MATRIX_M5PR                (3 << 20)       /* Master 5 Priority */
+#define                AT91_MATRIX_M6PR                (3 << 24)       /* Master 6 Priority */
+#define                AT91_MATRIX_M7PR                (3 << 28)       /* Master 7 Priority */
+#define                AT91_MATRIX_M8PR                (3 << 0)        /* Master 8 Priority (in Register B) */
+#define                AT91_MATRIX_M9PR                (3 << 4)        /* Master 9 Priority (in Register B) */
+#define                AT91_MATRIX_M10PR               (3 << 8)        /* Master 10 Priority (in Register B) */
+#define                AT91_MATRIX_M11PR               (3 << 12)       /* Master 11 Priority (in Register B) */
+
+#define AT91_MATRIX_MRCR       (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
+#define                AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define                AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#define                AT91_MATRIX_RCB2                (1 << 2)
+#define                AT91_MATRIX_RCB3                (1 << 3)
+#define                AT91_MATRIX_RCB4                (1 << 4)
+#define                AT91_MATRIX_RCB5                (1 << 5)
+#define                AT91_MATRIX_RCB6                (1 << 6)
+#define                AT91_MATRIX_RCB7                (1 << 7)
+#define                AT91_MATRIX_RCB8                (1 << 8)
+#define                AT91_MATRIX_RCB9                (1 << 9)
+#define                AT91_MATRIX_RCB10               (1 << 10)
+#define                AT91_MATRIX_RCB11               (1 << 11)
+
+#define AT91_MATRIX_TCMR       (AT91_MATRIX + 0x110)   /* TCM Configuration Register */
+#define                AT91_MATRIX_ITCM_SIZE           (0xf << 0)      /* Size of ITCM enabled memory block */
+#define                        AT91_MATRIX_ITCM_0              (0 << 0)
+#define                        AT91_MATRIX_ITCM_32             (6 << 0)
+#define                AT91_MATRIX_DTCM_SIZE           (0xf << 4)      /* Size of DTCM enabled memory block */
+#define                        AT91_MATRIX_DTCM_0              (0 << 4)
+#define                        AT91_MATRIX_DTCM_32             (6 << 4)
+#define                        AT91_MATRIX_DTCM_64             (7 << 4)
+#define                AT91_MATRIX_TCM_NWS             (0x1 << 11)     /* Wait state TCM register */
+#define                        AT91_MATRIX_TCM_NO_WS           (0x0 << 11)
+#define                        AT91_MATRIX_TCM_ONE_WS          (0x1 << 11)
+
+#define AT91_MATRIX_VIDEO      (AT91_MATRIX + 0x118)   /* Video Mode Configuration Register */
+#define                AT91C_VDEC_SEL                  (0x1 <<  0) /* Video Mode Selection */
+#define                        AT91C_VDEC_SEL_OFF              (0 << 0)
+#define                        AT91C_VDEC_SEL_ON               (1 << 0)
+
+#define AT91_MATRIX_EBICSA     (AT91_MATRIX + 0x128)   /* EBI Chip Select Assignment Register */
+#define                AT91_MATRIX_EBI_CS1A            (1 << 1)        /* Chip Select 1 Assignment */
+#define                        AT91_MATRIX_EBI_CS1A_SMC                (0 << 1)
+#define                        AT91_MATRIX_EBI_CS1A_SDRAMC             (1 << 1)
+#define                AT91_MATRIX_EBI_CS3A            (1 << 3)        /* Chip Select 3 Assignment */
+#define                        AT91_MATRIX_EBI_CS3A_SMC                (0 << 3)
+#define                        AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA     (1 << 3)
+#define                AT91_MATRIX_EBI_CS4A            (1 << 4)        /* Chip Select 4 Assignment */
+#define                        AT91_MATRIX_EBI_CS4A_SMC                (0 << 4)
+#define                        AT91_MATRIX_EBI_CS4A_SMC_CF0            (1 << 4)
+#define                AT91_MATRIX_EBI_CS5A            (1 << 5)        /* Chip Select 5 Assignment */
+#define                        AT91_MATRIX_EBI_CS5A_SMC                (0 << 5)
+#define                        AT91_MATRIX_EBI_CS5A_SMC_CF1            (1 << 5)
+#define                AT91_MATRIX_EBI_DBPUC           (1 << 8)        /* Data Bus Pull-up Configuration */
+#define                        AT91_MATRIX_EBI_DBPU_ON                 (0 << 8)
+#define                        AT91_MATRIX_EBI_DBPU_OFF                (1 << 8)
+#define                AT91_MATRIX_EBI_VDDIOMSEL       (1 << 16)       /* Memory voltage selection */
+#define                        AT91_MATRIX_EBI_VDDIOMSEL_1_8V          (0 << 16)
+#define                        AT91_MATRIX_EBI_VDDIOMSEL_3_3V          (1 << 16)
+#define                AT91_MATRIX_EBI_EBI_IOSR        (1 << 17)       /* EBI I/O slew rate selection */
+#define                        AT91_MATRIX_EBI_EBI_IOSR_REDUCED        (0 << 17)
+#define                        AT91_MATRIX_EBI_EBI_IOSR_NORMAL         (1 << 17)
+#define                AT91_MATRIX_EBI_DDR_IOSR        (1 << 18)       /* DDR2 dedicated port I/O slew rate selection */
+#define                        AT91_MATRIX_EBI_DDR_IOSR_REDUCED        (0 << 18)
+#define                        AT91_MATRIX_EBI_DDR_IOSR_NORMAL         (1 << 18)
+
+#define AT91_MATRIX_WPMR       (AT91_MATRIX + 0x1E4)   /* Write Protect Mode Register */
+#define                AT91_MATRIX_WPMR_WPEN           (1 << 0)        /* Write Protect ENable */
+#define                        AT91_MATRIX_WPMR_WP_WPDIS               (0 << 0)
+#define                        AT91_MATRIX_WPMR_WP_WPEN                (1 << 0)
+#define                AT91_MATRIX_WPMR_WPKEY          (0xFFFFFF << 8) /* Write Protect KEY */
+
+#define AT91_MATRIX_WPSR       (AT91_MATRIX + 0x1E8)   /* Write Protect Status Register */
+#define                AT91_MATRIX_WPSR_WPVS           (1 << 0)        /* Write Protect Violation Status */
+#define                        AT91_MATRIX_WPSR_NO_WPV         (0 << 0)
+#define                        AT91_MATRIX_WPSR_WPV            (1 << 0)
+#define                AT91_MATRIX_WPSR_WPVSRC         (0xFFFF << 8)   /* Write Protect Violation Source */
+
+#endif
index 6aaf82eae232688ede4a2d143e3adb19b73ecf95..f642dd99585f4248299c3d3ebfbbe41727d2a34f 100644 (file)
@@ -49,6 +49,11 @@ static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id)
        return get_mck_clk_rate();
 }
 
+static inline unsigned long get_spi_clk_rate(unsigned int dev_id)
+{
+       return get_mck_clk_rate();
+}
+
 static inline unsigned long get_twi_clk_rate(unsigned int dev_id)
 {
        return get_mck_clk_rate();
index 870410645ff5e6233f0b73e89ad38f647a703975..c42709efcc8dd0dd7a11ddcb36f73096eb26376b 100644 (file)
 #include <asm/arch/at91sam9rl.h>
 #define AT91_BASE_SPI  AT91SAM9RL_BASE_SPI
 #define AT91_ID_UHP    AT91SAM9RL_ID_UHP
+#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
+#include <asm/arch/at91sam9g45.h>
+#define AT91_BASE_EMAC  AT91SAM9G45_BASE_EMAC
+#define AT91_BASE_SPI   AT91SAM9G45_BASE_SPI0
+#define AT91_ID_UHP     AT91SAM9G45_ID_UHPHS
+#define AT91_PMC_UHP    AT91SAM926x_PMC_UHP
 #elif defined(CONFIG_AT91CAP9)
 #include <asm/arch/at91cap9.h>
 #define AT91_BASE_SPI  AT91CAP9_BASE_SPI0
index 8015dad6a9c7769e908f68743e6e4755a7b7f805..f605f37fd2c0dca688d72dc5e3924fd2df5633bd 100644 (file)
@@ -30,5 +30,6 @@
 #define USART1_BASE AT91_USART1
 #define USART2_BASE AT91_USART2
 #define USART3_BASE (AT91_BASE_SYS + AT91_DBGU)
+#define SPI0_BASE      AT91_BASE_SPI
 
 #endif /* __ASM_ARM_ARCH_MEMORYMAP_H__ */
diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h
new file mode 100644 (file)
index 0000000..572c45b
--- /dev/null
@@ -0,0 +1,225 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Configuation settings for the AT91SAM9M10G45EK board(and AT91SAM9G45EKES).
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* ARM asynchronous clock */
+#define AT91_MAIN_CLOCK                12000000        /* from 12 MHz crystal */
+#define CONFIG_SYS_HZ          1000
+
+#define CONFIG_ARM926EJS       1       /* This is an ARM926EJS Core    */
+#ifdef CONFIG_AT91SAM9M10G45EK
+#define CONFIG_AT91SAM9M10G45  1       /* It's an Atmel AT91SAM9M10G45 SoC*/
+#else
+#define CONFIG_AT91SAM9G45     1       /* It's an Atmel AT91SAM9G45 SoC*/
+#endif
+#define CONFIG_ARCH_CPU_INIT
+#undef CONFIG_USE_IRQ                  /* we don't need IRQ/FIQ stuff  */
+
+#define CONFIG_CMDLINE_TAG     1       /* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG      1
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_ATMEL_USART     1
+#undef CONFIG_USART0
+#undef CONFIG_USART1
+#undef CONFIG_USART2
+#define CONFIG_USART3          1       /* USART 3 is DBGU */
+
+/* LCD */
+#define CONFIG_LCD                     1
+#define LCD_BPP                                LCD_COLOR8
+#define CONFIG_LCD_LOGO                        1
+#undef LCD_TEST_PATTERN
+#define CONFIG_LCD_INFO                        1
+#define CONFIG_LCD_INFO_BELOW_LOGO     1
+#define CONFIG_SYS_WHITE_ON_BLACK              1
+#define CONFIG_ATMEL_LCD               1
+#define CONFIG_ATMEL_LCD_RGB565                1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV           1
+/* board specific(not enough SRAM) */
+#define CONFIG_AT91SAM9G45_LCD_BASE            0x73E00000
+
+/* LED */
+#define CONFIG_AT91_LED
+#define        CONFIG_RED_LED          AT91_PIN_PD31   /* this is the user1 led */
+#define        CONFIG_GREEN_LED        AT91_PIN_PD0    /* this is the user2 led */
+
+#define CONFIG_BOOTDELAY       3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE      1
+#define CONFIG_BOOTP_BOOTPATH          1
+#define CONFIG_BOOTP_GATEWAY           1
+#define CONFIG_BOOTP_HOSTNAME          1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_LOADS
+
+#define CONFIG_CMD_PING                1
+#define CONFIG_CMD_DHCP                1
+#define CONFIG_CMD_NAND                1
+#define CONFIG_CMD_USB         1
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS           1
+#define PHYS_SDRAM                     0x70000000
+#define PHYS_SDRAM_SIZE                        0x08000000      /* 128 megs */
+
+/* DataFlash */
+#ifdef CONFIG_ATMEL_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_SPI_FLASH               1
+#define CONFIG_SPI_FLASH_ATMEL         1
+#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
+#endif
+
+/* NOR flash, if populated */
+#ifndef CONFIG_CMD_NAND
+#define CONFIG_SYS_NO_FLASH            1
+#else
+#define CONFIG_SYS_FLASH_CFI           1
+#define CONFIG_FLASH_CFI_DRIVER                1
+#define PHYS_FLASH_1                   0x10000000
+#define CONFIG_SYS_FLASH_BASE                  PHYS_FLASH_1
+#define CONFIG_SYS_MAX_FLASH_SECT              256
+#define CONFIG_SYS_MAX_FLASH_BANKS             1
+#endif
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_MAX_CHIPS                  1
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE             1
+#define CONFIG_SYS_NAND_BASE                   0x40000000
+#define CONFIG_SYS_NAND_DBW_8                  1
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE               (1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE               (1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN             AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN              AT91_PIN_PC8
+#endif
+
+/* Ethernet */
+#define CONFIG_MACB                    1
+#define CONFIG_RMII                    1
+#define CONFIG_NET_MULTI               1
+#define CONFIG_NET_RETRY_COUNT         20
+#define CONFIG_RESET_PHY_R             1
+
+/* USB */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_OHCI_NEW            1
+#define CONFIG_DOS_PARTITION           1
+#define CONFIG_SYS_USB_OHCI_CPU_INIT           1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE          0x00700000      /* AT91SAM9G45_UHP_OHCI_BASE */
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME          "at91sam9g45"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS     2
+#define CONFIG_USB_STORAGE             1
+
+#define CONFIG_SYS_LOAD_ADDR                   0x22000000      /* load address */
+
+#define CONFIG_SYS_MEMTEST_START               PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END                 0x23e00000
+
+#ifdef CONFIG_SYS_USE_DATAFLASH
+
+/* bootstrap + u-boot + env + linux in dataflash on CS0 */
+#define CONFIG_ENV_IS_IN_SPI_FLASH     1
+#define CONFIG_SYS_MONITOR_BASE        (0xC0000000 + 0x8400)
+#define CONFIG_ENV_OFFSET              0x4200
+#define CONFIG_ENV_ADDR                (0xC0000000 + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE                0x4200
+#define CONFIG_ENV_SECT_SIZE           0x10000
+#define CONFIG_BOOTCOMMAND     "cp.b 0xC0042000 0x22000000 0x210000; bootm"
+#define CONFIG_BOOTARGS                "console=ttyS0,115200 " \
+                               "root=/dev/mtdblock0 " \
+                               "mtdparts=at91_nand:-(root) "\
+                               "rw rootfstype=jffs2"
+
+#else /* CONFIG_SYS_USE_NANDFLASH */
+
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CONFIG_ENV_IS_IN_NAND  1
+#define CONFIG_ENV_OFFSET              0x60000
+#define CONFIG_ENV_OFFSET_REDUND       0x80000
+#define CONFIG_ENV_SIZE                0x20000         /* 1 sector = 128 kB */
+#define CONFIG_BOOTCOMMAND     "nand read 0x72000000 0x200000 0x200000; bootm"
+#define CONFIG_BOOTARGS                "console=ttyS0,115200 " \
+                               "root=/dev/mtdblock5 " \
+                               "mtdparts=at91_nand:128k(bootstrap)ro, \
+                               256k(uboot)ro,128k(env1)ro,128k(env2)ro, \
+                               2M(linux),-(root) " \
+                               "rw rootfstype=jffs2"
+
+#endif
+
+#define CONFIG_BAUDRATE                115200
+#define CONFIG_SYS_BAUDRATE_TABLE      {115200 , 19200, 38400, 57600, 9600 }
+
+#define CONFIG_SYS_PROMPT              "U-Boot> "
+#define CONFIG_SYS_CBSIZE              256
+#define CONFIG_SYS_MAXARGS             16
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP            1
+#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
+
+#define ROUND(A, B)            (((A) + (B)) & ~((B) - 1))
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN          ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+#define CONFIG_SYS_GBL_DATA_SIZE       128     /* 128 bytes for initial data */
+
+#define CONFIG_STACKSIZE       (32*1024)       /* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif