u32 ctrl;
        struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
 
+       if (host->set_control_reg)
+               host->set_control_reg(host);
+
        if (mmc->clock != host->clock)
                sdhci_set_clock(mmc, mmc->clock);
 
        else
                ctrl &= ~SDHCI_CTRL_HISPD;
 
+       if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
+               ctrl &= ~SDHCI_CTRL_HISPD;
+
        sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 }
 
                mmc->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
        if (caps & SDHCI_CAN_VDD_180)
                mmc->voltages |= MMC_VDD_165_195;
+
+       if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
+               mmc->voltages |= host->voltages;
+
        mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
        if (caps & SDHCI_CAN_DO_8BIT)
                mmc->host_caps |= MMC_MODE_8BIT;
+       if (host->host_caps)
+               mmc->host_caps |= host->host_caps;
 
        sdhci_reset(host, SDHCI_RESET_ALL);
        mmc_register(mmc);
 
 #define SDHCI_QUIRK_32BIT_DMA_ADDR     (1 << 0)
 #define SDHCI_QUIRK_REG32_RW           (1 << 1)
 #define SDHCI_QUIRK_BROKEN_R1B         (1 << 2)
+#define SDHCI_QUIRK_NO_HISPD_BIT       (1 << 3)
+#define SDHCI_QUIRK_BROKEN_VOLTAGE     (1 << 4)
 
 /* to make gcc happy */
 struct sdhci_host;
        char *name;
        void *ioaddr;
        unsigned int quirks;
+       unsigned int host_caps;
        unsigned int version;
        unsigned int clock;
        struct mmc *mmc;
        const struct sdhci_ops *ops;
+
+       void (*set_control_reg)(struct sdhci_host *host);
+       uint    voltages;
 };
 
 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS