imx: mx6ul/sx: Fix issue in LCDIF clock dividers calculation

The checking with max frequency supported is not correct, because the temp
is calculated by max pre and post dividers. We can decrease any divider to
meet the max frequency limitation. Actually, the calculation below the codes
is doing this way to find best pre and post dividers.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 007204dd4d40a9f4b7445137ebae4f6825b56b5f..88380a6cd90714852a9d0f5bb4c75027b2297222 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -638,10 +638,6 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
        }
 
        temp = freq * max_pred * max_postd;
-       if (temp > max) {
-               puts("Please decrease freq, too large!\n");
-               return;
-       }
        if (temp < min) {
                /*
                 * Register: PLL_VIDEO