]> git.sur5r.net Git - u-boot/commitdiff
tegra30: fdt: add SPI SLINK nodes
authorAllen Martin <amartin@nvidia.com>
Tue, 29 Jan 2013 13:51:26 +0000 (13:51 +0000)
committerTom Warren <twarren@nvidia.com>
Mon, 11 Feb 2013 17:35:24 +0000 (10:35 -0700)
Add tegra30 SPI SLINK nodes to fdt.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
arch/arm/dts/tegra30.dtsi
board/nvidia/dts/tegra30-cardhu.dts

index aa7e7ae55ca65cc10c8c31677fc10d35cde57abc..7b8126f7ccd9e5eab577951a0338b37889d3ee9b 100644 (file)
                /* PERIPH_ID_I2C_DVC, CLK_M */
                clocks = <&tegra_car 47>;
        };
+
+       spi@7000d400 {
+               compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+               reg = <0x7000d400 0x200>;
+               interrupts = <0 59 0x04>;
+               nvidia,dma-request-selector = <&apbdma 15>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+               /* PERIPH_ID_SBC1, PLLP_OUT0 */
+               clocks = <&tegra_car 41>;
+       };
+
+       spi@7000d600 {
+               compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+               reg = <0x7000d600 0x200>;
+               interrupts = <0 82 0x04>;
+               nvidia,dma-request-selector = <&apbdma 16>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+               /* PERIPH_ID_SBC2, PLLP_OUT0 */
+               clocks = <&tegra_car 44>;
+       };
+
+       spi@7000d800 {
+               compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+               reg = <0x7000d480 0x200>;
+               interrupts = <0 83 0x04>;
+               nvidia,dma-request-selector = <&apbdma 17>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+               /* PERIPH_ID_SBC3, PLLP_OUT0 */
+               clocks = <&tegra_car 46>;
+       };
+
+       spi@7000da00 {
+               compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+               reg = <0x7000da00 0x200>;
+               interrupts = <0 93 0x04>;
+               nvidia,dma-request-selector = <&apbdma 18>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+               /* PERIPH_ID_SBC4, PLLP_OUT0 */
+               clocks = <&tegra_car 68>;
+       };
+
+       spi@7000dc00 {
+               compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+               reg = <0x7000dc00 0x200>;
+               interrupts = <0 94 0x04>;
+               nvidia,dma-request-selector = <&apbdma 27>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+               /* PERIPH_ID_SBC5, PLLP_OUT0 */
+               clocks = <&tegra_car 104>;
+       };
+
+       spi@7000de00 {
+               compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+               reg = <0x7000de00 0x200>;
+               interrupts = <0 79 0x04>;
+               nvidia,dma-request-selector = <&apbdma 28>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+               /* PERIPH_ID_SBC6, PLLP_OUT0 */
+               clocks = <&tegra_car 105>;
+       };
 };
index 3223ed4c21b288fbc97089eb4ac34fe715a651e7..f9f80c5218c6349c1b3f004801a5c937d5108f5a 100644 (file)
@@ -39,4 +39,9 @@
        i2c@7000d000 {
                clock-frequency = <100000>;
        };
+
+       spi@7000da00 {
+               status = "okay";
+               spi-max-frequency = <25000000>;
+       };
 };