net: zynq: Fix mdc clock division setting for 100Mbit/s

Using set and clear macro is incorrect because it is not overwritting
origin mdc clock division setup.
For example origin setup is 8(0b001) and new setup is 64(0b100) which
means 0b101 is setup which is 96 divider.
Using writel to rewrite all setting like for 1000Mbit/s case.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 56651e94bb81a48283410c61ee55ae5ad81cfe4a..9d69c8408dacc614714e74893932957832112191 100644 (file)
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -410,8 +410,8 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
                clk_rate = ZYNQ_GEM_FREQUENCY_1000;
                break;
        case SPEED_100:
-               clrsetbits_le32(&regs->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000,
-                               ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100);
+               writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100,
+                      &regs->nwcfg);
                clk_rate = ZYNQ_GEM_FREQUENCY_100;
                break;
        case SPEED_10: