]> git.sur5r.net Git - u-boot/commitdiff
powerpc/corenet: CPC1 speculation disable
authorDave Liu <daveliu@freescale.com>
Thu, 28 Nov 2013 06:58:08 +0000 (14:58 +0800)
committerYork Sun <yorksun@freescale.com>
Wed, 4 Dec 2013 22:54:10 +0000 (14:54 -0800)
In PBL RAMBOOT(SPI/SD/NAND boot) mode, CPC1 used as SRAM, should disable
CPC1 speculation and keep it till relocation. Otherwise, speculation
transactions will go to DDR controller, it will cause problem.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
arch/powerpc/cpu/mpc85xx/start.S

index 6a81fa73e4bed59f306da48696ae99ec55d536c8..db84d10c5bf2a9ad695a9a5644df3812f20d1fa8 100644 (file)
@@ -886,7 +886,11 @@ delete_ccsr_l2_tlb:
        erratum_set_dcsr 0xb0008 0x00900000
        erratum_set_dcsr 0xb0e40 0xe00a0000
        erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
+#ifdef  CONFIG_RAMBOOT_PBL
+       erratum_set_ccsr 0x10f00 0x495e5000
+#else
        erratum_set_ccsr 0x10f00 0x415e5000
+#endif
        erratum_set_ccsr 0x11f00 0x415e5000
 
        /* Make temp mapping uncacheable again, if it was initially */