LIB = $(obj)lib$(VENDOR).a
-COBJS-${CONFIG_PQ_MDS_PIB} += pq-mds-pib.o
-COBJS-${CONFIG_ID_EEPROM} += sys_eeprom.o
+COBJS-${CONFIG_FSL_CADMUS} += cadmus.o
+COBJS-${CONFIG_FSL_CDS_EEPROM} += cds_eeprom.o
+COBJS-${CONFIG_FSL_VIA} += cds_via.o
COBJS-${CONFIG_FSL_DIU_FB} += fsl_diu_fb.o fsl_logo_bmp.o
COBJS-${CONFIG_FSL_PIXIS} += pixis.o
+COBJS-${CONFIG_PQ_MDS_PIB} += pq-mds-pib.o
+COBJS-${CONFIG_ID_EEPROM} += sys_eeprom.o
+
+COBJS-${CONFIG_MPC8541CDS} += cds_pci_ft.o
+COBJS-${CONFIG_MPC8548CDS} += cds_pci_ft.o
+COBJS-${CONFIG_MPC8555CDS} += cds_pci_ft.o
+
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <i2c.h>
+
+#include "eeprom.h"
+
+
+typedef struct {
+ char idee_pcbid[4]; /* "CCID" for CDC v1.X */
+ u8 idee_major;
+ u8 idee_minor;
+ char idee_serial[10];
+ char idee_errata[2];
+ char idee_date[8]; /* yyyymmdd */
+ /* The rest of the EEPROM space is reserved */
+} id_eeprom_t;
+
+
+unsigned int
+get_cpu_board_revision(void)
+{
+ uint major = 0;
+ uint minor = 0;
+
+ id_eeprom_t id_eeprom;
+
+ i2c_read(CFG_I2C_EEPROM_ADDR, 0, 2,
+ (uchar *) &id_eeprom, sizeof(id_eeprom));
+
+ major = id_eeprom.idee_major;
+ minor = id_eeprom.idee_minor;
+
+ if (major == 0xff && minor == 0xff) {
+ major = minor = 0;
+ }
+
+ return MPC85XX_CPU_BOARD_REV(major,minor);
+}
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include "cadmus.h"
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+static void cds_pci_fixup(void *blob)
+{
+ int node, tmp[2];
+ const char *path;
+ int len, slot, i;
+ u32 *map = NULL;
+
+ node = fdt_path_offset(blob, "/aliases");
+ tmp[0] = 0;
+ if (node >= 0) {
+ path = fdt_getprop(blob, node, "pci0", NULL);
+ if (path) {
+ node = fdt_path_offset(blob, path);
+ if (node >= 0) {
+ map = fdt_getprop_w(blob, node, "interrupt-map", &len);
+ }
+ }
+ }
+
+ if (map) {
+ len /= sizeof(u32);
+
+ slot = get_pci_slot();
+
+ for (i=0;i<len;i+=7) {
+ /* We rotate the interrupt pins so that the mapping
+ * changes depending on the slot the carrier card is in.
+ */
+ map[3] = ((map[3] + slot - 2) % 4) + 1;
+ map+=7;
+ }
+ }
+}
+
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
+ cds_pci_fixup(blob);
+#endif
+}
+#endif
--- /dev/null
+/*
+ * Copyright 2006 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+
+/* Config the VIA chip */
+void mpc85xx_config_via(struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *tab)
+{
+ pci_dev_t bridge;
+ unsigned int cmdstat;
+
+ /* Enable USB and IDE functions */
+ pci_hose_write_config_byte(hose, dev, 0x48, 0x08);
+
+ pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
+ cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY| PCI_COMMAND_MASTER;
+ pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
+ pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+ pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
+
+ /*
+ * Force the backplane P2P bridge to have a window
+ * open from 0x00000000-0x00001fff in PCI I/O space.
+ * This allows legacy I/O (i8259, etc) on the VIA
+ * southbridge to be accessed.
+ */
+ bridge = PCI_BDF(0,BRIDGE_ID,0);
+ pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0);
+ pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0);
+ pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10);
+ pci_hose_write_config_word(hose, bridge, PCI_IO_LIMIT_UPPER16, 0);
+}
+
+/* Function 1, IDE */
+void mpc85xx_config_via_usbide(struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *tab)
+{
+ pciauto_config_device(hose, dev);
+ /*
+ * Since the P2P window was forced to cover the fixed
+ * legacy I/O addresses, it is necessary to manually
+ * place the base addresses for the IDE and USB functions
+ * within this window.
+ */
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1ff8);
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1ff4);
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1fe8);
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_3, 0x1fe4);
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fd0);
+}
+
+/* Function 2, USB ports 0-1 */
+void mpc85xx_config_via_usb(struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *tab)
+{
+ pciauto_config_device(hose, dev);
+
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fa0);
+}
+
+/* Function 3, USB ports 2-3 */
+void mpc85xx_config_via_usb2(struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *tab)
+{
+ pciauto_config_device(hose, dev);
+
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1f80);
+}
+
+/* Function 5, Power Management */
+void mpc85xx_config_via_power(struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *tab)
+{
+ pciauto_config_device(hose, dev);
+
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1e00);
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1dfc);
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1df8);
+}
+
+/* Function 6, AC97 Interface */
+void mpc85xx_config_via_ac97(struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *tab)
+{
+ pciauto_config_device(hose, dev);
+
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1c00);
+}
+++ /dev/null
-/*
- * Copyright 2004 Freescale Semiconductor.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <common.h>
-#include <i2c.h>
-
-#include "eeprom.h"
-
-
-typedef struct {
- char idee_pcbid[4]; /* "CCID" for CDC v1.X */
- u8 idee_major;
- u8 idee_minor;
- char idee_serial[10];
- char idee_errata[2];
- char idee_date[8]; /* yyyymmdd */
- /* The rest of the EEPROM space is reserved */
-} id_eeprom_t;
-
-
-unsigned int
-get_cpu_board_revision(void)
-{
- uint major = 0;
- uint minor = 0;
-
- id_eeprom_t id_eeprom;
-
- i2c_read(CFG_I2C_EEPROM_ADDR, 0, 2,
- (uchar *) &id_eeprom, sizeof(id_eeprom));
-
- major = id_eeprom.idee_major;
- minor = id_eeprom.idee_minor;
-
- if (major == 0xff && minor == 0xff) {
- major = minor = 0;
- }
-
- return MPC85XX_CPU_BOARD_REV(major,minor);
-}
+++ /dev/null
-/*
- * Copyright 2004 Freescale Semiconductor.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include "cadmus.h"
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-static void cds_pci_fixup(void *blob)
-{
- int node, tmp[2];
- const char *path;
- int len, slot, i;
- u32 *map = NULL;
-
- node = fdt_path_offset(blob, "/aliases");
- tmp[0] = 0;
- if (node >= 0) {
- path = fdt_getprop(blob, node, "pci0", NULL);
- if (path) {
- node = fdt_path_offset(blob, path);
- if (node >= 0) {
- map = fdt_getprop_w(blob, node, "interrupt-map", &len);
- }
- }
- }
-
- if (map) {
- len /= sizeof(u32);
-
- slot = get_pci_slot();
-
- for (i=0;i<len;i+=7) {
- /* We rotate the interrupt pins so that the mapping
- * changes depending on the slot the carrier card is in.
- */
- map[3] = ((map[3] + slot - 2) % 4) + 1;
- map+=7;
- }
- }
-}
-
-void
-ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
- cds_pci_fixup(blob);
-#endif
-}
-#endif
+++ /dev/null
-/*
- * Copyright 2006 Freescale Semiconductor.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <pci.h>
-
-/* Config the VIA chip */
-void mpc85xx_config_via(struct pci_controller *hose,
- pci_dev_t dev, struct pci_config_table *tab)
-{
- pci_dev_t bridge;
- unsigned int cmdstat;
-
- /* Enable USB and IDE functions */
- pci_hose_write_config_byte(hose, dev, 0x48, 0x08);
-
- pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
- cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY| PCI_COMMAND_MASTER;
- pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
- pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
- pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
-
- /*
- * Force the backplane P2P bridge to have a window
- * open from 0x00000000-0x00001fff in PCI I/O space.
- * This allows legacy I/O (i8259, etc) on the VIA
- * southbridge to be accessed.
- */
- bridge = PCI_BDF(0,BRIDGE_ID,0);
- pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0);
- pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0);
- pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10);
- pci_hose_write_config_word(hose, bridge, PCI_IO_LIMIT_UPPER16, 0);
-}
-
-/* Function 1, IDE */
-void mpc85xx_config_via_usbide(struct pci_controller *hose,
- pci_dev_t dev, struct pci_config_table *tab)
-{
- pciauto_config_device(hose, dev);
- /*
- * Since the P2P window was forced to cover the fixed
- * legacy I/O addresses, it is necessary to manually
- * place the base addresses for the IDE and USB functions
- * within this window.
- */
- pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1ff8);
- pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1ff4);
- pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1fe8);
- pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_3, 0x1fe4);
- pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fd0);
-}
-
-/* Function 2, USB ports 0-1 */
-void mpc85xx_config_via_usb(struct pci_controller *hose,
- pci_dev_t dev, struct pci_config_table *tab)
-{
- pciauto_config_device(hose, dev);
-
- pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fa0);
-}
-
-/* Function 3, USB ports 2-3 */
-void mpc85xx_config_via_usb2(struct pci_controller *hose,
- pci_dev_t dev, struct pci_config_table *tab)
-{
- pciauto_config_device(hose, dev);
-
- pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1f80);
-}
-
-/* Function 5, Power Management */
-void mpc85xx_config_via_power(struct pci_controller *hose,
- pci_dev_t dev, struct pci_config_table *tab)
-{
- pciauto_config_device(hose, dev);
-
- pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1e00);
- pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1dfc);
- pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1df8);
-}
-
-/* Function 6, AC97 Interface */
-void mpc85xx_config_via_ac97(struct pci_controller *hose,
- pci_dev_t dev, struct pci_config_table *tab)
-{
- pciauto_config_device(hose, dev);
-
- pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1c00);
-}
#
include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o law.o tlb.o \
- ../common/cadmus.o \
- ../common/eeprom.o \
- ../common/ft_board.o \
- ../common/via.o
+COBJS-y += $(BOARD).o
+COBJS-y += law.o
+COBJS-y += tlb.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#
include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o law.o tlb.o \
- ../common/cadmus.o \
- ../common/eeprom.o \
- ../common/ft_board.o \
- ../common/via.o
+COBJS-y += $(BOARD).o
+COBJS-y += law.o
+COBJS-y += tlb.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#
include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o law.o tlb.o \
- ../common/cadmus.o \
- ../common/eeprom.o \
- ../common/ft_board.o \
- ../common/via.o
+COBJS-y += $(BOARD).o
+COBJS-y += law.o
+COBJS-y += tlb.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#
include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
LIB = $(obj)lib$(BOARD).a
include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
LIB = $(obj)lib$(BOARD).a
COBJS := $(BOARD).o law.o
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
+#define CONFIG_FSL_VIA
+#define CONFIG_FSL_CDS_EEPROM
+
/*
* When initializing flash, if we cannot find the manufacturer ID,
* assume this is the AMD flash associated with the CDS board.
* 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
*/
+#define CONFIG_FSL_CADMUS
+
#define CADMUS_BASE_ADDR 0xf8000000
#define CFG_BR3_PRELIM 0xf8000801
#define CFG_OR3_PRELIM 0xfff00ff7
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
+#define CONFIG_FSL_VIA
+#define CONFIG_FSL_CDS_EEPROM
+
/*
* When initializing flash, if we cannot find the manufacturer ID,
* assume this is the AMD flash associated with the CDS board.
* 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
*/
+#define CONFIG_FSL_CADMUS
+
#define CADMUS_BASE_ADDR 0xf8000000
#define CFG_BR3_PRELIM 0xf8000801
#define CFG_OR3_PRELIM 0xfff00ff7
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
+#define CONFIG_FSL_VIA
+#define CONFIG_FSL_CDS_EEPROM
+
/*
* When initializing flash, if we cannot find the manufacturer ID,
* assume this is the AMD flash associated with the CDS board.
* 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
*/
+#define CONFIG_FSL_CADMUS
+
#define CADMUS_BASE_ADDR 0xf8000000
#define CFG_BR3_PRELIM 0xf8000801
#define CFG_OR3_PRELIM 0xfff00ff7
projects / u-boot / commitdiff