/*
* DDR Setup
*/
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
* Manually set up DDR parameters, as this board does not
* seem to have the SPD connected to I2C.
*/
-#define CONFIG_SYS_DDR_SIZE 128 /* MB */
-#define CONFIG_SYS_DDR_CONFIG ( CSCONFIG_EN \
- | 0x00010000 /* TODO */ \
- | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
+#define CONFIG_SYS_DDR_SIZE 128 /* MB */
+#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN \
+ | 0x00010000 /* TODO */ \
+ | CSCONFIG_ROW_BIT_13 \
+ | CSCONFIG_COL_BIT_10)
/* 0x80010102 */
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
- | ( 0 << TIMING_CFG0_WRT_SHIFT ) \
- | ( 0 << TIMING_CFG0_RRT_SHIFT ) \
- | ( 0 << TIMING_CFG0_WWT_SHIFT ) \
- | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
- | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
- | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
- | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
+#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
+ | (0 << TIMING_CFG0_WRT_SHIFT) \
+ | (0 << TIMING_CFG0_RRT_SHIFT) \
+ | (0 << TIMING_CFG0_WWT_SHIFT) \
+ | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+ | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+ | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+ | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
/* 0x00220802 */
-#define CONFIG_SYS_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
- | ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
- | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
- | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
- | (10 << TIMING_CFG1_REFREC_SHIFT ) \
- | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \
- | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
- | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
+#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
+ | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+ | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
+ | (5 << TIMING_CFG1_CASLAT_SHIFT) \
+ | (10 << TIMING_CFG1_REFREC_SHIFT) \
+ | (3 << TIMING_CFG1_WRREC_SHIFT) \
+ | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+ | (2 << TIMING_CFG1_WRTORD_SHIFT))
/* 0x3835a322 */
-#define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
- | ( 5 << TIMING_CFG2_CPO_SHIFT ) \
- | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
- | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
- | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
- | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
- | ( 6 << TIMING_CFG2_FOUR_ACT_SHIFT) )
+#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
+ | (5 << TIMING_CFG2_CPO_SHIFT) \
+ | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+ | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+ | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+ | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+ | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
/* 0x129048c6 */ /* P9-45,may need tuning */
-#define CONFIG_SYS_DDR_INTERVAL ( ( 1296 << SDRAM_INTERVAL_REFINT_SHIFT ) \
- | ( 1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
+#define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
+ | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
/* 0x05100500 */
#if defined(CONFIG_DDR_2T_TIMING)
-#define CONFIG_SYS_SDRAM_CFG ( SDRAM_CFG_SREN \
+#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
| SDRAM_CFG_2T_EN \
- | SDRAM_CFG_DBW_32 )
+ | SDRAM_CFG_DBW_32)
#else
-#define CONFIG_SYS_SDRAM_CFG ( SDRAM_CFG_SREN \
+#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
- | SDRAM_CFG_32_BE )
+ | SDRAM_CFG_32_BE)
/* 0x43080000 */
#endif
#define CONFIG_SYS_SDRAM_CFG2 0x00401000
/* set burst length to 8 for 32-bit data path */
-#define CONFIG_SYS_DDR_MODE ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \
- | ( 0x0632 << SDRAM_MODE_SD_SHIFT ) )
+#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
+ | (0x0632 << SDRAM_MODE_SD_SHIFT))
/* 0x44480632 */
-#define CONFIG_SYS_DDR_MODE_2 0x8000C000
+#define CONFIG_SYS_DDR_MODE_2 0x8000C000
#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
/*0x02000000*/
-#define CONFIG_SYS_DDRCDR_VALUE ( DDRCDR_EN \
+#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
| DDRCDR_PZ_NOMZ \
| DDRCDR_NZ_NOMZ \
- | DDRCDR_M_ODR )
+ | DDRCDR_M_ODR)
/*
* FLASH on the Local Bus
*/
-#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
-#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
-
-#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE | /* flash Base address */ \
- (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
- BR_V) /* valid */
-#define CONFIG_SYS_NOR_OR_PRELIM ( 0xFF800000 /* 8 MByte */ \
+#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
+#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
+#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
+
+#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
+ | (2 << BR_PS_SHIFT) /* 16 bit port */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_NOR_OR_PRELIM (0xFF800000 /* 8 MByte */ \
| OR_GPCM_XACS \
| OR_GPCM_SCY_9 \
| OR_GPCM_EHTR \
- | OR_GPCM_EAD )
+ | OR_GPCM_EAD)
/* 0xFF006FF7 TODO SLOW 16 MB flash size */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* window base at flash base */
+ /* window base at flash base */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000017 /* 16 MB window size */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && !defined(CONFIG_NAND_SPL)
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
+ !defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_RAMBOOT
#endif
#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
/*
* Local Bus LCRR and LBCR regs
*/
#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
-#define CONFIG_SYS_LBC_LBCR ( 0x00040000 /* TODO */ \
- | (0xFF << LBCR_BMT_SHIFT) \
- | 0xF ) /* 0x0004ff0f */
+#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
+ | (0xFF << LBCR_BMT_SHIFT) \
+ | 0xF) /* 0x0004ff0f */
-#define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */
+ /* LB refresh timer prescal, 266MHz/32 */
+#define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */
/* drivers/mtd/nand/nand.c */
#ifdef CONFIG_NAND_SPL
#define CONFIG_MTD_PARTITION
#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT "nand0=e2800000.flash"
-#define MTDPARTS_DEFAULT \
+#define MTDPARTS_DEFAULT \
"mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)"
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
-#define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \
+#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8 bit */ \
+ | BR_PS_8 /* 8 bit port */ \
| BR_MS_FCM /* MSEL = FCM */ \
- | BR_V ) /* valid */
-#define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFF8000 /* length 32K */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFF8000 /* length 32K */ \
| OR_FCM_CSCT \
| OR_FCM_CST \
| OR_FCM_CHT \
| OR_FCM_SCY_1 \
| OR_FCM_TRLX \
- | OR_FCM_EHTR )
+ | OR_FCM_EHTR)
/* 0xFFFF8396 */
#ifdef CONFIG_NAND_U_BOOT
#ifdef CONFIG_VSC7385_ENET
-#define CONFIG_SYS_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */
-#define CONFIG_SYS_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/
-#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE/* Access window base at VSC7385 base */
-#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* Access window size 128K */
+ /* VSC7385 Base address */
+#define CONFIG_SYS_BR2_PRELIM 0xf0000801
+ /* VSC7385, 128K bytes*/
+#define CONFIG_SYS_OR2_PRELIM 0xfffe09ff
+ /* Access window base at VSC7385 base */
+#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
+ /* Access window size 128K */
+#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010
#endif
#define CONFIG_HARD_I2C /* I2C with hardware support*/
#define CONFIG_FSL_I2C
#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C2_OFFSET 0x3100
/*
* General PCI
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
#define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
- #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
+ #define CONFIG_ENV_OFFSET_REDUND \
+ (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
#elif !defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_ENV_IS_IN_FLASH 1
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+ #define CONFIG_ENV_ADDR \
+ (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
+ /* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+ /* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
/*
* For booting Linux, the board info and command line data
* have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
+ /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
/* System IO Config */
#define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
-#define CONFIG_SYS_SICRL SICRL_USBDR_10 /* Enable Internal USB Phy */
+#define CONFIG_SYS_SICRL SICRL_USBDR_10 /* Enable Internal USB Phy */
#define CONFIG_SYS_HID0_INIT 0x000000000
#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
/* DDR @ 0x00000000 */
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
/* PCI @ 0x80000000 */
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
/* PCI2 not supported on 8313 */
#define CONFIG_SYS_IBAT3L (0)
#define CONFIG_SYS_IBAT4U (0)
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE)
*/
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_NETDEV eth1
+#define CONFIG_NETDEV "eth1"
#define CONFIG_HOSTNAME mpc8313erdb
#define CONFIG_ROOTPATH "/nfs/root/path"
#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
-#define CONFIG_FDTFILE mpc8313erdb.dtb
+ /* U-Boot image on TFTP server */
+#define CONFIG_UBOOTPATH "u-boot.bin"
+#define CONFIG_FDTFILE "mpc8313erdb.dtb"
-#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
+ /* default location for tftp and bootm */
+#define CONFIG_LOADADDR 800000
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
#define CONFIG_BAUDRATE 115200
#define MK_STR(x) XMK_STR(x)
#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
+ "netdev=" CONFIG_NETDEV "\0" \
"ethprime=TSEC1\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "uboot=" CONFIG_UBOOTPATH "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
+ "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\
+ "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "\
+ "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\
+ "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"\
"fdtaddr=780000\0" \
- "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
+ "fdtfile=" CONFIG_FDTFILE "\0" \
"console=ttyS0\0" \
"setbootargs=setenv bootargs " \
"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
+ "$netdev:off " \
"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
#define CONFIG_NFSBOOTCOMMAND \
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