CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
+CONFIG_DAVINCI_SPI=y
# CONFIG_FAT_WRITE is not set
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
+CONFIG_DAVINCI_SPI=y
# CONFIG_FAT_WRITE is not set
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
+CONFIG_DAVINCI_SPI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NS16550=y
+CONFIG_DAVINCI_SPI=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
+CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
+CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
+CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
+CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
+CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
+CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
+CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NS16550=y
+CONFIG_DAVINCI_SPI=y
CONFIG_OF_LIBFDT=y
# CONFIG_EFI_LOADER is not set
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
+CONFIG_DAVINCI_SPI=y
CONFIG_OF_LIBFDT=y
used to access the SPI flash on AE3XX and AE250 platforms embedding
this Andestech IP core.
+config DAVINCI_SPI
+ bool "Davinci & Keystone SPI driver"
+ depends on ARCH_DAVINCI || ARCH_KEYSTONE
+ help
+ Enable the Davinci SPI driver
+
config TI_QSPI
bool "TI QSPI driver"
help
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
#define CONFIG_SPI
-#define CONFIG_DAVINCI_SPI
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
#define CONFIG_SPI
-#define CONFIG_DAVINCI_SPI
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
#define CONFIG_SPI
-#define CONFIG_DAVINCI_SPI
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI0_BASE
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID)
#define CONFIG_SF_DEFAULT_SPEED 50000000
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_SPI
-#define CONFIG_DAVINCI_SPI
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
#define CONFIG_SF_DEFAULT_SPEED 30000000
#endif
/* SPI Configuration */
-#define CONFIG_DAVINCI_SPI
#define CONFIG_SYS_SPI_CLK ks_clk_get_rate(KS2_CLK1_6)
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
CONFIG_DA850_EVM_MAX_CPU_CLK
CONFIG_DA850_LOWLEVEL
CONFIG_DA8XX_GPIO
-CONFIG_DAVINCI_SPI
CONFIG_DBAU1000
CONFIG_DBAU1X00
CONFIG_DBGU