]> git.sur5r.net Git - u-boot/commitdiff
ARM: UniPhier: enable output of system bus
authorMasahiro Yamada <yamada.m@jp.panasonic.com>
Tue, 6 Jan 2015 05:20:04 +0000 (14:20 +0900)
committerMasahiro Yamada <yamada.m@jp.panasonic.com>
Thu, 8 Jan 2015 14:01:45 +0000 (23:01 +0900)
For NAND boot on PH1-LD4, PH1-sLD8, and some other SoCs,
the output of the system bus is disabled by default.
It must be enabled by software to have access to the system bus.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c
arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c
arch/arm/include/asm/arch-uniphier/sbc-regs.h

index a37ed1674f0e834af412400ec9ff447fcfe32aa6..4839c943c7f199895f5eeec414ef130eedec16d0 100644 (file)
 
 void sbc_init(void)
 {
+       u32 tmp;
+
+       /* system bus output enable */
+       tmp = readl(PC0CTRL);
+       tmp &= 0xfffffcff;
+       writel(tmp, PC0CTRL);
+
        /* XECS1: sub/boot memory (boot swap = off/on) */
        writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
        writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
index af44dee4f62b05cc111c3a7c530fcfcdb93d6acd..5efee9c505ce9a58c4e1d4da4d55ab30dde8ee80 100644 (file)
 
 void sbc_init(void)
 {
+       u32 tmp;
+
+       /* system bus output enable */
+       tmp = readl(PC0CTRL);
+       tmp &= 0xfffffcff;
+       writel(tmp, PC0CTRL);
+
 #if !defined(CONFIG_SPL_BUILD)
        /* XECS0 : dummy */
        writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
index 8e410788eff0fc08014b379935ca4c1dadc2a7c8..efb68e8564944216b6e1abc5c4935d66f239cd3a 100644 (file)
@@ -95,6 +95,7 @@
 #define SBCTRL1_ADMULTIPLX_MEM_VALUE   0x03005500
 #define SBCTRL2_ADMULTIPLX_MEM_VALUE   0x14000010
 
+#define PC0CTRL                                0x598000c0
 #define ROM_BOOT_ROMRSV2               0x59801208
 
 #ifndef __ASSEMBLY__