struct uniphier_initdata {
enum uniphier_soc_id soc_id;
bool nand_2cs;
+ void (*sbc_init)(void);
void (*pll_init)(void);
void (*clk_init)(void);
void (*misc_init)(void);
{
.soc_id = SOC_UNIPHIER_SLD3,
.nand_2cs = true,
+ .sbc_init = uniphier_sbc_init_admulti,
.pll_init = uniphier_sld3_pll_init,
.clk_init = uniphier_ld4_clk_init,
},
{
.soc_id = SOC_UNIPHIER_LD4,
.nand_2cs = true,
+ .sbc_init = uniphier_ld4_sbc_init,
.pll_init = uniphier_ld4_pll_init,
.clk_init = uniphier_ld4_clk_init,
},
{
.soc_id = SOC_UNIPHIER_PRO4,
.nand_2cs = false,
+ .sbc_init = uniphier_sbc_init_savepin,
.pll_init = uniphier_pro4_pll_init,
.clk_init = uniphier_pro4_clk_init,
},
{
.soc_id = SOC_UNIPHIER_SLD8,
.nand_2cs = true,
+ .sbc_init = uniphier_ld4_sbc_init,
.pll_init = uniphier_ld4_pll_init,
.clk_init = uniphier_ld4_clk_init,
},
{
.soc_id = SOC_UNIPHIER_PRO5,
.nand_2cs = true,
+ .sbc_init = uniphier_sbc_init_savepin,
.clk_init = uniphier_pro5_clk_init,
},
#endif
{
.soc_id = SOC_UNIPHIER_PXS2,
.nand_2cs = true,
+ .sbc_init = uniphier_pxs2_sbc_init,
.clk_init = uniphier_pxs2_clk_init,
},
#endif
{
.soc_id = SOC_UNIPHIER_LD6B,
.nand_2cs = true,
+ .sbc_init = uniphier_pxs2_sbc_init,
.clk_init = uniphier_pxs2_clk_init,
},
#endif
{
.soc_id = SOC_UNIPHIER_LD11,
.nand_2cs = false,
+ .sbc_init = uniphier_ld11_sbc_init,
.pll_init = uniphier_ld11_pll_init,
.clk_init = uniphier_ld11_clk_init,
.misc_init = uniphier_ld11_misc_init,
{
.soc_id = SOC_UNIPHIER_LD20,
.nand_2cs = false,
+ .sbc_init = uniphier_ld11_sbc_init,
.pll_init = uniphier_ld20_pll_init,
.misc_init = uniphier_ld20_misc_init,
},
return -EINVAL;
}
+ initdata->sbc_init();
+
+ support_card_init();
+
+ led_puts("U0");
+
if (IS_ENABLED(CONFIG_NAND_DENALI)) {
ret = uniphier_pin_init(initdata->nand_2cs ?
"nand2cs_grp" : "nand_grp");
enum uniphier_soc_id soc_id;
void (*bcu_init)(const struct uniphier_board_data *bd);
void (*early_clk_init)(void);
- void (*sbc_init)(void);
int (*dpll_init)(const struct uniphier_board_data *bd);
int (*memconf_init)(const struct uniphier_board_data *bd);
void (*dram_clk_init)(void);
.soc_id = SOC_UNIPHIER_SLD3,
.bcu_init = uniphier_sld3_bcu_init,
.early_clk_init = uniphier_sld3_early_clk_init,
- .sbc_init = uniphier_sbc_init_admulti,
.dpll_init = uniphier_sld3_dpll_init,
.memconf_init = uniphier_memconf_3ch_no_disbit_init,
.dram_clk_init = uniphier_sld3_dram_clk_init,
.soc_id = SOC_UNIPHIER_LD4,
.bcu_init = uniphier_ld4_bcu_init,
.early_clk_init = uniphier_sld3_early_clk_init,
- .sbc_init = uniphier_ld4_sbc_init,
.dpll_init = uniphier_ld4_dpll_init,
.memconf_init = uniphier_memconf_2ch_init,
.dram_clk_init = uniphier_sld3_dram_clk_init,
{
.soc_id = SOC_UNIPHIER_PRO4,
.early_clk_init = uniphier_sld3_early_clk_init,
- .sbc_init = uniphier_sbc_init_savepin,
.dpll_init = uniphier_pro4_dpll_init,
.memconf_init = uniphier_memconf_2ch_init,
.dram_clk_init = uniphier_sld3_dram_clk_init,
.soc_id = SOC_UNIPHIER_SLD8,
.bcu_init = uniphier_ld4_bcu_init,
.early_clk_init = uniphier_sld3_early_clk_init,
- .sbc_init = uniphier_ld4_sbc_init,
.dpll_init = uniphier_sld8_dpll_init,
.memconf_init = uniphier_memconf_2ch_init,
.dram_clk_init = uniphier_sld3_dram_clk_init,
{
.soc_id = SOC_UNIPHIER_PRO5,
.early_clk_init = uniphier_sld3_early_clk_init,
- .sbc_init = uniphier_sbc_init_savepin,
.dpll_init = uniphier_pro5_dpll_init,
.memconf_init = uniphier_memconf_2ch_init,
.dram_clk_init = uniphier_pro5_dram_clk_init,
{
.soc_id = SOC_UNIPHIER_PXS2,
.early_clk_init = uniphier_sld3_early_clk_init,
- .sbc_init = uniphier_pxs2_sbc_init,
.dpll_init = uniphier_pxs2_dpll_init,
.memconf_init = uniphier_memconf_3ch_init,
.dram_clk_init = uniphier_pxs2_dram_clk_init,
{
.soc_id = SOC_UNIPHIER_LD6B,
.early_clk_init = uniphier_sld3_early_clk_init,
- .sbc_init = uniphier_pxs2_sbc_init,
.dpll_init = uniphier_pxs2_dpll_init,
.memconf_init = uniphier_memconf_3ch_init,
.dram_clk_init = uniphier_pxs2_dram_clk_init,
{
.soc_id = SOC_UNIPHIER_LD11,
.early_clk_init = uniphier_ld11_early_clk_init,
- .sbc_init = uniphier_ld11_sbc_init,
.dpll_init = uniphier_ld11_dpll_init,
.memconf_init = uniphier_memconf_2ch_init,
.dram_clk_init = uniphier_ld11_dram_clk_init,
{
.soc_id = SOC_UNIPHIER_LD20,
.early_clk_init = uniphier_ld11_early_clk_init,
- .sbc_init = uniphier_ld11_sbc_init,
.dpll_init = uniphier_ld20_dpll_init,
.memconf_init = uniphier_memconf_3ch_init,
.dram_clk_init = uniphier_ld20_dram_clk_init,
if (initdata->bcu_init)
initdata->bcu_init(bd);
- initdata->sbc_init();
initdata->early_clk_init();
- support_card_init();
-
- led_puts("L0");
#ifdef CONFIG_SPL_SERIAL_SUPPORT
preloader_console_init();
#endif
- led_puts("L1");
-
ret = initdata->dpll_init(bd);
if (ret) {
pr_err("failed to init DPLL\n");
hang();
}
- led_puts("L2");
-
ret = initdata->memconf_init(bd);
if (ret) {
pr_err("failed to init MEMCONF\n");
hang();
}
- led_puts("L3");
-
initdata->dram_clk_init();
- led_puts("L4");
-
ret = initdata->umc_init(bd);
if (ret) {
pr_err("failed to init DRAM\n");
hang();
}
-
- led_puts("L5");
}