]> git.sur5r.net Git - u-boot/commitdiff
powerpc: T4240: Remove macro CONFIG_PPC_T4240
authorYork Sun <york.sun@nxp.com>
Mon, 21 Nov 2016 21:35:41 +0000 (13:35 -0800)
committerYork Sun <york.sun@nxp.com>
Thu, 24 Nov 2016 07:42:15 +0000 (23:42 -0800)
Use CONFIG_ARCH_T4240 from Kconfig instead.

Signed-off-by: York Sun <york.sun@nxp.com>
18 files changed:
arch/powerpc/cpu/mpc85xx/Kconfig
arch/powerpc/cpu/mpc85xx/Makefile
arch/powerpc/cpu/mpc85xx/fdt.c
arch/powerpc/cpu/mpc85xx/speed.c
arch/powerpc/cpu/mpc85xx/t4240_serdes.c
arch/powerpc/include/asm/config_mpc85xx.h
arch/powerpc/include/asm/immap_85xx.h
configs/T4240QDS_NAND_defconfig
configs/T4240QDS_SDCARD_defconfig
configs/T4240QDS_SECURE_BOOT_defconfig
configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
configs/T4240QDS_defconfig
configs/T4240RDB_SDCARD_defconfig
configs/T4240RDB_defconfig
drivers/net/fm/Makefile
include/configs/T4240QDS.h
include/configs/T4240RDB.h
scripts/config_whitelist.txt

index 991127d6c8d9aa79f188878c596e32e552b8438b..83dd1e0f761215913d14f9514ada8f2b1f767e58 100644 (file)
@@ -274,11 +274,13 @@ config TARGET_T4160RDB
 
 config TARGET_T4240QDS
        bool "Support T4240QDS"
+       select ARCH_T4240
        select SUPPORT_SPL
        select PHYS_64BIT
 
 config TARGET_T4240RDB
        bool "Support T4240RDB"
+       select ARCH_T4240
        select SUPPORT_SPL
        select PHYS_64BIT
 
@@ -424,6 +426,9 @@ config ARCH_T2081
 config ARCH_T4160
        bool
 
+config ARCH_T4240
+       bool
+
 source "board/freescale/b4860qds/Kconfig"
 source "board/freescale/bsc9131rdb/Kconfig"
 source "board/freescale/bsc9132qds/Kconfig"
index cf2aaa199b5c066d612303407439f6ac1c871ae5..e5b45e1eb01758c503daee1dde85e1be27743c7a 100644 (file)
@@ -44,7 +44,7 @@ obj-$(CONFIG_ARCH_P3041) += p3041_ids.o
 obj-$(CONFIG_ARCH_P4080) += p4080_ids.o
 obj-$(CONFIG_ARCH_P5020) += p5020_ids.o
 obj-$(CONFIG_ARCH_P5040) += p5040_ids.o
-obj-$(CONFIG_PPC_T4240) += t4240_ids.o
+obj-$(CONFIG_ARCH_T4240) += t4240_ids.o
 obj-$(CONFIG_ARCH_T4160) += t4240_ids.o
 obj-$(CONFIG_PPC_T4080) += t4240_ids.o
 obj-$(CONFIG_ARCH_B4420) += b4860_ids.o
@@ -86,7 +86,7 @@ obj-$(CONFIG_ARCH_P3041) += p3041_serdes.o
 obj-$(CONFIG_ARCH_P4080) += p4080_serdes.o
 obj-$(CONFIG_ARCH_P5020) += p5020_serdes.o
 obj-$(CONFIG_ARCH_P5040) += p5040_serdes.o
-obj-$(CONFIG_PPC_T4240) += t4240_serdes.o
+obj-$(CONFIG_ARCH_T4240) += t4240_serdes.o
 obj-$(CONFIG_ARCH_T4160) += t4240_serdes.o
 obj-$(CONFIG_PPC_T4080) += t4240_serdes.o
 obj-$(CONFIG_ARCH_B4420) += b4860_serdes.o
index 9fab8ed341821e698a3b6486907bdce78afac756..9d81873583746997efbb10e7417efea01ca39563 100644 (file)
@@ -511,7 +511,7 @@ static void fdt_fixup_usb(void *fdt)
 #define fdt_fixup_usb(x)
 #endif
 
-#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_PPC_T4240) || \
+#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T4240) || \
        defined(CONFIG_ARCH_T4160) || defined(CONFIG_PPC_T4080)
 void fdt_fixup_dma3(void *blob)
 {
@@ -529,7 +529,7 @@ void fdt_fixup_dma3(void *blob)
        case 0x29:
        case 0x2d:
        case 0x2e:
-#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_ARCH_T4160) || \
+#elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \
        defined(CONFIG_PPC_T4080)
        u32 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
                                    FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
index e4feb3f689c5014b17910ef928c52c44b6dd908e..7f10ed0878122b6a259ff3a5b68951f326a65368 100644 (file)
@@ -130,7 +130,7 @@ void get_sys_info(sys_info_t *sys_info)
         * it uses 6.
         * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0
         */
-#if defined(CONFIG_PPC_T4240) || defined(CONFIG_ARCH_T4160) || \
+#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \
        defined(CONFIG_PPC_T4080) || defined(CONFIG_ARCH_T2080) || \
        defined(CONFIG_ARCH_T2081)
        svr = get_svr();
index 4b73e760a136b304607083862018770a11fd12e2..1a5bcb13e7232269038205c305bb3820c151d732 100644 (file)
@@ -15,7 +15,7 @@ struct serdes_config {
        u8 lanes[SRDS_MAX_LANES];
 };
 
-#ifdef CONFIG_PPC_T4240
+#ifdef CONFIG_ARCH_T4240
 static const struct serdes_config serdes1_cfg_tbl[] = {
        /* SerDes 1 */
        {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
index fc8e0117cecb01ab7190c8b4295705dd02993d3c..0d8eb4686cde5c37059972fe3d2cbf5090d05f4d 100644 (file)
 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
 #define CONFIG_ESDHC_HC_BLK_ADDR
 
-#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_ARCH_T4160) || \
+#elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \
        defined(CONFIG_PPC_T4080)
 #define CONFIG_E6500
 #define CONFIG_SYS_PPC64               /* 64-bit core */
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2  /* Freescale Chassis generation 2 */
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
 #define CONFIG_SYS_FSL_QMAN_V3         /* QMAN version 3 */
-#ifdef CONFIG_PPC_T4240
+#ifdef CONFIG_ARCH_T4240
 #define CONFIG_MAX_CPUS                        12
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS   { 1, 1, 4 }
 #define CONFIG_SYS_NUM_FM1_DTSEC       8
index 19ce7f3488b7ff202f1dcb4bc4f410c5e440c47c..75868fa9f0ca6bb5ed5bc40d959e5c260614c2f1 100644 (file)
@@ -1759,7 +1759,7 @@ typedef struct ccsr_gur {
 /* use reserved bits 18~23 as scratch space to host DDR PLL ratio */
 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT      8
 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK    0x3f
-#if defined(CONFIG_PPC_T4240) || defined(CONFIG_ARCH_T4160) || \
+#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \
        defined(CONFIG_PPC_T4080)
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL                0xfc000000
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT  26
@@ -1875,7 +1875,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII          0x00100000
 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE         0x00180000
 #endif
-#if defined(CONFIG_PPC_T4240) || defined(CONFIG_ARCH_T4160) || \
+#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \
        defined(CONFIG_PPC_T4080)
 #define FSL_CORENET_RCWSR13_EC1                        0x60000000 /* bits 417..418 */
 #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII       0x00000000
index 4cdbeb42db5b1b96eb868fcdf50b2d1b17848f33..493f3c1baf036b025b2ee502e3e6e751626a4e66 100644 (file)
@@ -12,7 +12,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_BOOTDELAY=10
 CONFIG_SPL=y
 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
index 8f8837c88e7ab20d64107347ac38d991defdb57f..2357d829d5372c9e4ef7ebc59f9b9da7b36167e6 100644 (file)
@@ -12,7 +12,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
 CONFIG_BOOTDELAY=10
 CONFIG_SPL=y
 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
index 85ca4960b3c52f31f65b42aa01b91ed823d4ba97..ed2d093a9cd0e70e17b273527030f7dab9ec437f 100644 (file)
@@ -6,7 +6,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
 CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
index 91cd3cf6ce1df77671e6ebf081ee2f29c1d60b72..7e9b97e04612b8c8f3777de8c0b1346bd39cc019 100644 (file)
@@ -5,7 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
index a9c263e5bdff70f6550f736dce2cfb397e08fb7b..559da713f055ad66837b1403fcae540160151f43 100644 (file)
@@ -5,7 +5,6 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240"
 CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
index 2104a95af52f79bfc7dc612ff818aecbdd7f6573..ef299aa52fe757d2b5e90bf0363435db0c1ac09e 100644 (file)
@@ -12,7 +12,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
 CONFIG_BOOTDELAY=10
 CONFIG_SPL=y
 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
index b688a575b5fd423b864f7bf5aa406947782a5dee..bf357622fd7b1a53a2071c6abb090c6f7e03f301 100644 (file)
@@ -5,7 +5,6 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240"
 CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
index 43d6406584238d65c75adbe326326fe012e20479..4bfadaae5a6607fdb3eb10e99814e28e9278d062 100644 (file)
@@ -32,7 +32,7 @@ obj-$(CONFIG_ARCH_T1023) += t1024.o
 obj-$(CONFIG_ARCH_T1024) += t1024.o
 obj-$(CONFIG_ARCH_T2080) += t2080.o
 obj-$(CONFIG_ARCH_T2081) += t2080.o
-obj-$(CONFIG_PPC_T4240) += t4240.o
+obj-$(CONFIG_ARCH_T4240) += t4240.o
 obj-$(CONFIG_ARCH_T4160) += t4240.o
 obj-$(CONFIG_PPC_T4080) += t4240.o
 obj-$(CONFIG_ARCH_B4420) += b4860.o
index 1217cd0aefde94c2c64c5a8745a144f11ca15db2..1d18316a4129dc51387c10cf925dbd9aa2f62ab6 100644 (file)
@@ -542,7 +542,7 @@ unsigned long get_board_ddr_clk(void);
  * interleaving. It can be cacheline, page, bank, superbank.
  * See doc/README.fsl-ddr for details.
  */
-#ifdef CONFIG_PPC_T4240
+#ifdef CONFIG_ARCH_T4240
 #define CTRL_INTLV_PREFERED 3way_4KB
 #else
 #define CTRL_INTLV_PREFERED cacheline
index da536f008469dfac2232240f066a84773bfe96e6..6c743e3ccc59c47a0606f93fad1af1c5058be225 100644 (file)
@@ -732,7 +732,7 @@ unsigned long get_board_ddr_clk(void);
  * interleaving. It can be cacheline, page, bank, superbank.
  * See doc/README.fsl-ddr for details.
  */
-#ifdef CONFIG_PPC_T4240
+#ifdef CONFIG_ARCH_T4240
 #define CTRL_INTLV_PREFERED 3way_4KB
 #else
 #define CTRL_INTLV_PREFERED cacheline
index 46b4ae38f3d185c32e86f234b98f144a941d5778..e8a3c674b24f07c01ac9ea8d93360e47527d5210 100644 (file)
@@ -3640,7 +3640,6 @@ CONFIG_PPC4xx_EMAC
 CONFIG_PPC64BRIDGE
 CONFIG_PPC_CLUSTER_START
 CONFIG_PPC_SPINTABLE_COMPATIBLE
-CONFIG_PPC_T4240
 CONFIG_PQ_MDS_PIB
 CONFIG_PQ_MDS_PIB_ATM
 CONFIG_PRAM