#########################################################################
LIST_blackfin=" \
- bf533-ezkit bf533-stamp \
+ bf533-ezkit bf533-stamp bf537-stamp \
"
#-----------------------------------------------------------------------
OBJS += cpu/$(CPU)/start1.o cpu/$(CPU)/interrupt.o cpu/$(CPU)/cache.o
OBJS += cpu/$(CPU)/flush.o cpu/$(CPU)/init_sdram.o
endif
+ifeq ($(CPU),bf537)
+OBJS += cpu/$(CPU)/start1.o cpu/$(CPU)/interrupt.o cpu/$(CPU)/cache.o
+OBJS += cpu/$(CPU)/flush.o cpu/$(CPU)/init_sdram.o
+endif
OBJS := $(addprefix $(obj),$(OBJS))
bf533-stamp_config: unconfig
@$(MKCONFIG) $(@:_config=) blackfin bf533 bf533-stamp
+bf537-stamp_config: unconfig
+ @$(MKCONFIG) $(@:_config=) blackfin bf537 bf537-stamp
+
#========================================================================
# AVR32
#========================================================================
rm -f $(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom
rm -f $(obj)board/integratorap/u-boot.lds $(obj)board/integratorcp/u-boot.lds
rm -f $(obj)board/bf533-ezkit/u-boot.lds $(obj)board/bf533-stamp/u-boot.lds
+ rm -f $(obj)board/bf537-stamp/u-boot.lds
rm -f $(obj)include/bmp_logo.h
rm -f $(obj)nand_spl/u-boot-spl $(obj)nand_spl/u-boot-spl.map
--- /dev/null
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2007 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o flash.o ether_bf537.o post-memory.o stm_m25p64.o cmd_bf537led.o nand.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS) u-boot.lds
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+u-boot.lds: u-boot.lds.S
+ $(CPP) $(CPPFLAGS) -P -Ubfin $^ > $@.tmp
+ mv -f $@.tmp $@
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * U-boot - BF537.c
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <asm/blackfin.h>
+#include <asm/io.h>
+#include "ether_bf537.h"
+
+#define POST_WORD_ADDR 0xFF903FFC
+
+/*
+ * the bootldr command loads an address, checks to see if there
+ * is a Boot stream that the on-chip BOOTROM can understand,
+ * and loads it via the BOOTROM Callback. It is possible
+ * to also add booting from SPI, or TWI, but this function does
+ * not currently support that.
+ */
+int do_bootldr(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ ulong addr, entry;
+ ulong *data;
+
+ /* Get the address */
+ if (argc < 2) {
+ addr = load_addr;
+ } else {
+ addr = simple_strtoul(argv[1], NULL, 16);
+ }
+
+ /* Check if it is a LDR file */
+ data = (ulong *) addr;
+ if (*data == 0xFF800060 || *data == 0xFF800040 || *data == 0xFF800020) {
+ /* We want to boot from FLASH or SDRAM */
+ entry = _BOOTROM_BOOT_DXE_FLASH;
+ printf("## Booting ldr image at 0x%08lx ...\n", addr);
+ if (icache_status())
+ icache_disable();
+ if (dcache_status())
+ dcache_disable();
+
+ __asm__("R7=%[a];\n" "P0=%[b];\n" "JUMP (P0);\n":
+ :[a] "d"(addr),[b] "a"(entry)
+ :"R7", "P0");
+
+ } else {
+ printf("## No ldr image at address 0x%08lx\n", addr);
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(bootldr, 2, 0, do_bootldr,
+ "bootldr - boot ldr image from memory\n",
+ "[addr]\n - boot ldr image stored in memory\n");
+
+int checkboard(void)
+{
+#if (BFIN_CPU == ADSP_BF534)
+ printf("CPU: ADSP BF534 Rev.: 0.%d\n", *pCHIPID >> 28);
+#elif (BFIN_CPU == ADSP_BF536)
+ printf("CPU: ADSP BF536 Rev.: 0.%d\n", *pCHIPID >> 28);
+#else
+ printf("CPU: ADSP BF537 Rev.: 0.%d\n", *pCHIPID >> 28);
+#endif
+ printf("Board: ADI BF537 stamp board\n");
+ printf(" Support: http://blackfin.uclinux.org/\n");
+ return 0;
+}
+
+#if defined(CONFIG_BFIN_IDE)
+
+void cf_outb(unsigned char val, volatile unsigned char *addr)
+{
+ *(addr) = val;
+ sync();
+}
+
+unsigned char cf_inb(volatile unsigned char *addr)
+{
+ volatile unsigned char c;
+
+ c = *(addr);
+ sync();
+
+ return c;
+}
+
+void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
+{
+ int i;
+
+ for (i = 0; i < words; i++)
+ *(sect_buf + i) = *(addr);
+ sync();
+}
+
+void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
+{
+ int i;
+
+ for (i = 0; i < words; i++)
+ *(addr) = *(sect_buf + i);
+ sync();
+}
+#endif /* CONFIG_BFIN_IDE */
+
+long int initdram(int board_type)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+#ifdef DEBUG
+ int brate;
+ char *tmp = getenv("baudrate");
+ brate = simple_strtoul(tmp, NULL, 16);
+ printf("Serial Port initialized with Baud rate = %x\n", brate);
+ printf("SDRAM attributes:\n");
+ printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles"
+ "tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n",
+ 3, 3, 6, 2, 3);
+ printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
+ printf("Bank size = %d MB\n", CFG_MAX_RAM_SIZE >> 20);
+#endif
+ gd->bd->bi_memstart = CFG_SDRAM_BASE;
+ gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
+ return CFG_MAX_RAM_SIZE;
+}
+
+#if defined(CONFIG_MISC_INIT_R)
+/* miscellaneous platform dependent initialisations */
+int misc_init_r(void)
+{
+#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
+ char nid[32];
+ unsigned char *pMACaddr = (unsigned char *)0x203F0000;
+ u8 SrcAddr[6] = { 0x02, 0x80, 0xAD, 0x20, 0x31, 0xB8 };
+
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+ /* The 0xFF check here is to make sure we don't use the address
+ * in flash if it's simply been erased (aka all 0xFF values) */
+ if (getenv("ethaddr") == NULL && is_valid_ether_addr(pMACaddr)) {
+ sprintf(nid, "%02x:%02x:%02x:%02x:%02x:%02x",
+ pMACaddr[0], pMACaddr[1],
+ pMACaddr[2], pMACaddr[3], pMACaddr[4], pMACaddr[5]);
+ setenv("ethaddr", nid);
+ }
+ if (getenv("ethaddr")) {
+ SetupMacAddr(SrcAddr);
+ }
+#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
+#endif /* BFIN_BOOT_MODE == BF537_BYPASS_BOOT */
+
+#if defined(CONFIG_BFIN_IDE)
+#if defined(CONFIG_BFIN_TRUE_IDE)
+ /* Enable ATASEL when in True IDE mode */
+ printf("Using CF True IDE Mode\n");
+ cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_ENA);
+ udelay(1000);
+#elif defined(CONFIG_BFIN_CF_IDE)
+ /* Disable ATASEL when we're in Common Memory Mode */
+ printf("Using CF Common Memory Mode\n");
+ cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_DIS);
+ udelay(1000);
+#elif defined(CONFIG_BFIN_HDD_IDE)
+ printf("Using HDD IDE Mode\n");
+#endif
+ ide_init();
+#endif /* CONFIG_BFIN_IDE */
+ return 0;
+}
+#endif /* CONFIG_MISC_INIT_R */
+
+#ifdef CONFIG_POST
+#if (BFIN_BOOT_MODE != BF537_BYPASS_BOOT)
+/* Using sw10-PF5 as the hotkey */
+int post_hotkeys_pressed(void)
+{
+ return 0;
+}
+#else
+/* Using sw10-PF5 as the hotkey */
+int post_hotkeys_pressed(void)
+{
+ int delay = 3;
+ int i;
+ unsigned short value;
+
+ *pPORTF_FER &= ~PF5;
+ *pPORTFIO_DIR &= ~PF5;
+ *pPORTFIO_INEN |= PF5;
+
+ printf("########Press SW10 to enter Memory POST########: %2d ", delay);
+ while (delay--) {
+ for (i = 0; i < 100; i++) {
+ value = *pPORTFIO & PF5;
+ if (value != 0) {
+ break;
+ }
+ udelay(10000);
+ }
+ printf("\b\b\b%2d ", delay);
+ }
+ printf("\b\b\b 0");
+ printf("\n");
+ if (value == 0)
+ return 0;
+ else {
+ printf("Hotkey has been pressed, Enter POST . . . . . .\n");
+ return 1;
+ }
+}
+#endif
+#endif
+
+#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
+void post_word_store(ulong a)
+{
+ volatile ulong *save_addr = (volatile ulong *)POST_WORD_ADDR;
+ *save_addr = a;
+}
+
+ulong post_word_load(void)
+{
+ volatile ulong *save_addr = (volatile ulong *)POST_WORD_ADDR;
+ return *save_addr;
+}
+#endif
+
+#ifdef CONFIG_POST
+int uart_post_test(int flags)
+{
+ return 0;
+}
+
+#define BLOCK_SIZE 0x10000
+#define VERIFY_ADDR 0x2000000
+extern int erase_block_flash(int);
+extern int write_data(long lStart, long lCount, uchar * pnData);
+int flash_post_test(int flags)
+{
+ unsigned short *pbuf, *temp;
+ int offset, n, i;
+ int value = 0;
+ int result = 0;
+ printf("\n");
+ pbuf = (unsigned short *)VERIFY_ADDR;
+ temp = pbuf;
+ for (n = FLASH_START_POST_BLOCK; n < FLASH_END_POST_BLOCK; n++) {
+ offset = (n - 7) * BLOCK_SIZE;
+ printf("--------Erase block:%2d..", n);
+ erase_block_flash(n);
+ printf("OK\r");
+ printf("--------Program block:%2d...", n);
+ write_data(CFG_FLASH_BASE + offset, BLOCK_SIZE, pbuf);
+ printf("OK\r");
+ printf("--------Verify block:%2d...", n);
+ for (i = 0; i < BLOCK_SIZE; i += 2) {
+ if (*(unsigned short *)(CFG_FLASH_BASE + offset + i) !=
+ *temp++) {
+ value = 1;
+ result = 1;
+ }
+ }
+ if (value)
+ printf("failed\n");
+ else
+ printf("OK %3d%%\r",
+ (int)(
+ (n + 1 -
+ FLASH_START_POST_BLOCK) *
+ 100 / (FLASH_END_POST_BLOCK -
+ FLASH_START_POST_BLOCK)));
+
+ temp = pbuf;
+ value = 0;
+ }
+ printf("\n");
+ if (result)
+ return -1;
+ else
+ return 0;
+}
+
+/****************************************************
+ * LED1 ---- PF6 LED2 ---- PF7 *
+ * LED3 ---- PF8 LED4 ---- PF9 *
+ * LED5 ---- PF10 LED6 ---- PF11 *
+ ****************************************************/
+int led_post_test(int flags)
+{
+ *pPORTF_FER &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
+ *pPORTFIO_DIR |= PF6 | PF7 | PF8 | PF9 | PF10 | PF11;
+ *pPORTFIO_INEN &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
+ *pPORTFIO &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
+ udelay(1000000);
+ printf("LED1 on");
+ *pPORTFIO |= PF6;
+ udelay(1000000);
+ printf("\b\b\b\b\b\b\b");
+ printf("LED2 on");
+ *pPORTFIO |= PF7;
+ udelay(1000000);
+ printf("\b\b\b\b\b\b\b");
+ printf("LED3 on");
+ *pPORTFIO |= PF8;
+ udelay(1000000);
+ printf("\b\b\b\b\b\b\b");
+ printf("LED4 on");
+ *pPORTFIO |= PF9;
+ udelay(1000000);
+ printf("\b\b\b\b\b\b\b");
+ printf("LED5 on");
+ *pPORTFIO |= PF10;
+ udelay(1000000);
+ printf("\b\b\b\b\b\b\b");
+ printf("lED6 on");
+ *pPORTFIO |= PF11;
+ printf("\b\b\b\b\b\b\b ");
+ return 0;
+}
+
+/************************************************
+ * SW10 ---- PF5 SW11 ---- PF4 *
+ * SW12 ---- PF3 SW13 ---- PF2 *
+ ************************************************/
+int button_post_test(int flags)
+{
+ int i, delay = 5;
+ unsigned short value = 0;
+ int result = 0;
+
+ *pPORTF_FER &= ~(PF5 | PF4 | PF3 | PF2);
+ *pPORTFIO_DIR &= ~(PF5 | PF4 | PF3 | PF2);
+ *pPORTFIO_INEN |= (PF5 | PF4 | PF3 | PF2);
+
+ printf("\n--------Press SW10: %2d ", delay);
+ while (delay--) {
+ for (i = 0; i < 100; i++) {
+ value = *pPORTFIO & PF5;
+ if (value != 0) {
+ break;
+ }
+ udelay(10000);
+ }
+ printf("\b\b\b%2d ", delay);
+ }
+ if (value != 0)
+ printf("\b\bOK");
+ else {
+ result = -1;
+ printf("\b\bfailed");
+ }
+
+ delay = 5;
+ printf("\n--------Press SW11: %2d ", delay);
+ while (delay--) {
+ for (i = 0; i < 100; i++) {
+ value = *pPORTFIO & PF4;
+ if (value != 0) {
+ break;
+ }
+ udelay(10000);
+ }
+ printf("\b\b\b%2d ", delay);
+ }
+ if (value != 0)
+ printf("\b\bOK");
+ else {
+ result = -1;
+ printf("\b\bfailed");
+ }
+
+ delay = 5;
+ printf("\n--------Press SW12: %2d ", delay);
+ while (delay--) {
+ for (i = 0; i < 100; i++) {
+ value = *pPORTFIO & PF3;
+ if (value != 0) {
+ break;
+ }
+ udelay(10000);
+ }
+ printf("\b\b\b%2d ", delay);
+ }
+ if (value != 0)
+ printf("\b\bOK");
+ else {
+ result = -1;
+ printf("\b\bfailed");
+ }
+
+ delay = 5;
+ printf("\n--------Press SW13: %2d ", delay);
+ while (delay--) {
+ for (i = 0; i < 100; i++) {
+ value = *pPORTFIO & PF2;
+ if (value != 0) {
+ break;
+ }
+ udelay(10000);
+ }
+ printf("\b\b\b%2d ", delay);
+ }
+ if (value != 0)
+ printf("\b\bOK");
+ else {
+ result = -1;
+ printf("\b\bfailed");
+ }
+ printf("\n");
+ return result;
+}
+#endif
--- /dev/null
+/*
+ * U-boot - cmd_bf537led.c
+ *
+ * Copyright (C) 2006 Aaron Gage, Ocean Optics Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <asm/blackfin.h>
+#include <asm-blackfin/string.h>
+#ifdef CONFIG_BF537_STAMP_LEDCMD
+
+/* Define the command usage in a reusable way */
+#define USAGE_LONG \
+ "led <number> <action>\n" \
+ " <number> - Index (0-5) of LED to change, or \"all\"\n" \
+ " <action> - Must be one of:\n" \
+ " on off toggle\n"
+
+/* Number of LEDs supported by the board */
+#define NUMBER_LEDS 6
+/* The BF537 stamp has 6 LEDs. This mask indicates that all should be lit. */
+#define LED_ALL_MASK 0x003F
+
+void show_cmd_usage(void);
+void set_led_state(int index, int state);
+void configure_GPIO_to_output(int index);
+
+/* Map of LEDs according to their GPIO ports. This can be rearranged or
+ * otherwise changed to account for different GPIO configurations.
+ */
+int led_ports[] = { PF6, PF7, PF8, PF9, PF10, PF11 };
+
+#define ACTION_TOGGLE -1
+#define ACTION_OFF 0
+#define ACTION_ON 1
+
+#define LED_STATE_OFF 0
+#define LED_STATE_ON 1
+
+/* This is a trivial atoi implementation since we don't have one available */
+int atoi(char *string)
+{
+ int length;
+ int retval = 0;
+ int i;
+ int sign = 1;
+
+ length = strlen(string);
+ for (i = 0; i < length; i++) {
+ if (0 == i && string[0] == '-') {
+ sign = -1;
+ continue;
+ }
+ if (string[i] > '9' || string[i] < '0') {
+ break;
+ }
+ retval *= 10;
+ retval += string[i] - '0';
+ }
+ retval *= sign;
+ return retval;
+}
+
+int do_bf537led(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ int led_mask = 0;
+ int led_current_state = 0;
+ int action = ACTION_OFF;
+ int temp;
+
+ if (3 != argc) {
+ /* Not enough arguments, so just show usage information */
+ show_cmd_usage();
+ return 1;
+ }
+
+ if (strcmp(argv[1], "all") == 0) {
+ led_mask = LED_ALL_MASK;
+ } else {
+ temp = atoi(argv[1]);
+ if (temp < 0 || temp >= NUMBER_LEDS) {
+ printf("Invalid LED number [%s]\n", argv[1]);
+ show_cmd_usage();
+ return 2;
+ }
+ led_mask |= (1 << temp);
+ }
+
+ if (strcmp(argv[2], "off") == 0) {
+ action = ACTION_OFF;
+ } else if (strcmp(argv[2], "on") == 0) {
+ action = ACTION_ON;
+ } else if (strcmp(argv[2], "toggle") == 0) {
+ action = ACTION_TOGGLE;
+ } else {
+ printf("Invalid action [%s]\n", argv[2]);
+ show_cmd_usage();
+ return 3;
+ }
+
+ for (temp = 0; temp < NUMBER_LEDS; temp++) {
+ if ((led_mask & (1 << temp)) > 0) {
+ /*
+ * It is possible that the user has wired one of PF6-PF11 to
+ * something other than an LED, so this will only change a pin
+ * to output if the user has indicated a state change. This may
+ * happen a lot, but this way is safer than just setting all pins
+ * to output.
+ */
+ configure_GPIO_to_output(temp);
+
+ led_current_state =
+ ((*pPORTFIO & led_ports[temp]) >
+ 0) ? LED_STATE_ON : LED_STATE_OFF;
+ /*
+ printf("LED state for index %d (%x) is %d\n", temp, led_ports[temp],
+ led_current_state);
+ printf("*pPORTFIO is %x\n", *pPORTFIO);
+ */
+ if (ACTION_ON == action
+ || (ACTION_TOGGLE == action
+ && 0 == led_current_state)) {
+ printf("Turning LED %d on\n", temp);
+ set_led_state(temp, LED_STATE_ON);
+ } else {
+ printf("Turning LED %d off\n", temp);
+ set_led_state(temp, LED_STATE_OFF);
+ }
+ }
+ }
+
+ return 0;
+}
+
+/*
+ * The GPIO pins that go to the LEDs on the BF537 stamp must be configured
+ * as output. This function simply configures them that way. This could
+ * be done to all of the GPIO lines at once, but if a user is using a
+ * custom board, this will try to be nice and only change the GPIO lines
+ * that the user specifically names.
+ */
+void configure_GPIO_to_output(int index)
+{
+ int port;
+
+ port = led_ports[index];
+
+ /* Clear the Port F Function Enable Register */
+ *pPORTF_FER &= ~port;
+ /* Set the Port F I/O direction register */
+ *pPORTFIO_DIR |= port;
+ /* Clear the Port F I/O Input Enable Register */
+ *pPORTFIO_INEN &= ~port;
+}
+
+/* Enforce the given state on the GPIO line for the indicated LED */
+void set_led_state(int index, int state)
+{
+ int port;
+
+ port = led_ports[index];
+
+ if (LED_STATE_OFF == state) {
+ /* Clear the bit to turn off the LED */
+ *pPORTFIO &= ~port;
+ } else {
+ /* Set the bit to turn on the LED */
+ *pPORTFIO |= port;
+ }
+}
+
+/* Display usage information */
+void show_cmd_usage()
+{
+ printf("Usage:\n%s", USAGE_LONG);
+}
+
+/* Register information for u-boot to find this command */
+U_BOOT_CMD(led, 3, 1, do_bf537led,
+ "led- Control BF537 stamp LEDs\n", USAGE_LONG);
+
+#endif
--- /dev/null
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# TEXT_BASE should be defined as the MAX_SDRAM Address - 256k bytes
+# 256k is defined as CFG_MONITOR_LEN in ./include/configs/<board>.h
+TEXT_BASE = 0x03FC0000
--- /dev/null
+/*
+ * ADI Blackfin 537 MAC Ethernet
+ *
+ * Copyright (c) 2005 Analog Device, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/blackfin.h>
+#include <net.h>
+#include <command.h>
+#include <malloc.h>
+#include "ether_bf537.h"
+
+#ifdef CONFIG_POST
+#include <post.h>
+#endif
+
+#undef DEBUG_ETHERNET
+
+#ifdef DEBUG_ETHERNET
+#define DEBUGF(fmt,args...) printf(fmt,##args)
+#else
+#define DEBUGF(fmt,args...)
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+
+#define RXBUF_BASE_ADDR 0xFF900000
+#define TXBUF_BASE_ADDR 0xFF800000
+#define TX_BUF_CNT 1
+
+#define TOUT_LOOP 1000000
+
+ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT];
+ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX];
+static u16 txIdx; /* index of the current RX buffer */
+static u16 rxIdx; /* index of the current TX buffer */
+
+u8 SrcAddr[6];
+u16 PHYregs[NO_PHY_REGS]; /* u16 PHYADDR; */
+
+/* DMAx_CONFIG values at DMA Restart */
+const ADI_DMA_CONFIG_REG rxdmacfg = { 1, 1, 2, 0, 0, 0, 0, 5, 7 };
+
+#if 0
+ rxdmacfg.b_DMA_EN = 1; /* enabled */
+ rxdmacfg.b_WNR = 1; /* write to memory */
+ rxdmacfg.b_WDSIZE = 2; /* wordsize is 32 bits */
+ rxdmacfg.b_DMA2D = 0; /* N/A */
+ rxdmacfg.b_RESTART= 0; /* N/A */
+ rxdmacfg.b_DI_SEL = 0; /* N/A */
+ rxdmacfg.b_DI_EN = 0; /* no interrupt */
+ rxdmacfg.b_NDSIZE = 5; /* 5 half words is desc size. */
+ rxdmacfg.b_FLOW = 7; /* large desc flow */
+#endif
+
+const ADI_DMA_CONFIG_REG txdmacfg = { 1, 0, 2, 0, 0, 0, 0, 5, 7 };
+
+#if 0
+ txdmacfg.b_DMA_EN = 1; /* enabled */
+ txdmacfg.b_WNR = 0; /* read from memory */
+ txdmacfg.b_WDSIZE = 2; /* wordsize is 32 bits */
+ txdmacfg.b_DMA2D = 0; /* N/A */
+ txdmacfg.b_RESTART= 0; /* N/A */
+ txdmacfg.b_DI_SEL = 0; /* N/A */
+ txdmacfg.b_DI_EN = 0; /* no interrupt */
+ txdmacfg.b_NDSIZE = 5; /* 5 half words is desc size. */
+ txdmacfg.b_FLOW = 7; /* large desc flow */
+#endif
+
+ADI_ETHER_BUFFER *SetupRxBuffer(int no);
+ADI_ETHER_BUFFER *SetupTxBuffer(int no);
+
+static int bfin_EMAC_init(struct eth_device *dev, bd_t * bd);
+static void bfin_EMAC_halt(struct eth_device *dev);
+static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet,
+ int length);
+static int bfin_EMAC_recv(struct eth_device *dev);
+
+int bfin_EMAC_initialize(bd_t * bis)
+{
+ struct eth_device *dev;
+ dev = (struct eth_device *)malloc(sizeof(*dev));
+ if (dev == NULL)
+ hang();
+
+ memset(dev, 0, sizeof(*dev));
+ sprintf(dev->name, "BF537 ETHERNET");
+
+ dev->iobase = 0;
+ dev->priv = 0;
+ dev->init = bfin_EMAC_init;
+ dev->halt = bfin_EMAC_halt;
+ dev->send = bfin_EMAC_send;
+ dev->recv = bfin_EMAC_recv;
+
+ eth_register(dev);
+
+ return 1;
+}
+
+static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet,
+ int length)
+{
+ int i;
+ int result = 0;
+ unsigned int *buf;
+ buf = (unsigned int *)packet;
+
+ if (length <= 0) {
+ printf("Ethernet: bad packet size: %d\n", length);
+ goto out;
+ }
+
+ if ((*pDMA2_IRQ_STATUS & DMA_ERR) != 0) {
+ printf("Ethernet: tx DMA error\n");
+ goto out;
+ }
+
+ for (i = 0; (*pDMA2_IRQ_STATUS & DMA_RUN) != 0; i++) {
+ if (i > TOUT_LOOP) {
+ puts("Ethernet: tx time out\n");
+ goto out;
+ }
+ }
+ txbuf[txIdx]->FrmData->NoBytes = length;
+ memcpy(txbuf[txIdx]->FrmData->Dest, (void *)packet, length);
+ txbuf[txIdx]->Dma[0].START_ADDR = (u32) txbuf[txIdx]->FrmData;
+ *pDMA2_NEXT_DESC_PTR = &txbuf[txIdx]->Dma[0];
+ *pDMA2_CONFIG = *(u16 *) (void *)(&txdmacfg);
+ *pEMAC_OPMODE |= TE;
+
+ for (i = 0; (txbuf[txIdx]->StatusWord & TX_COMP) == 0; i++) {
+ if (i > TOUT_LOOP) {
+ puts("Ethernet: tx error\n");
+ goto out;
+ }
+ }
+ result = txbuf[txIdx]->StatusWord;
+ txbuf[txIdx]->StatusWord = 0;
+ if ((txIdx + 1) >= TX_BUF_CNT)
+ txIdx = 0;
+ else
+ txIdx++;
+ out:
+ DEBUGF("BFIN EMAC send: length = %d\n", length);
+ return result;
+}
+
+static int bfin_EMAC_recv(struct eth_device *dev)
+{
+ int length = 0;
+
+ for (;;) {
+ if ((rxbuf[rxIdx]->StatusWord & RX_COMP) == 0) {
+ length = -1;
+ break;
+ }
+ if ((rxbuf[rxIdx]->StatusWord & RX_DMAO) != 0) {
+ printf("Ethernet: rx dma overrun\n");
+ break;
+ }
+ if ((rxbuf[rxIdx]->StatusWord & RX_OK) == 0) {
+ printf("Ethernet: rx error\n");
+ break;
+ }
+ length = rxbuf[rxIdx]->StatusWord & 0x000007FF;
+ if (length <= 4) {
+ printf("Ethernet: bad frame\n");
+ break;
+ }
+ NetRxPackets[rxIdx] =
+ (volatile uchar *)(rxbuf[rxIdx]->FrmData->Dest);
+ NetReceive(NetRxPackets[rxIdx], length - 4);
+ *pDMA1_IRQ_STATUS |= DMA_DONE | DMA_ERR;
+ rxbuf[rxIdx]->StatusWord = 0x00000000;
+ if ((rxIdx + 1) >= PKTBUFSRX)
+ rxIdx = 0;
+ else
+ rxIdx++;
+ }
+
+ return length;
+}
+
+/**************************************************************
+ *
+ * Ethernet Initialization Routine
+ *
+ *************************************************************/
+
+static int bfin_EMAC_init(struct eth_device *dev, bd_t * bd)
+{
+ u32 opmode;
+ int dat;
+ int i;
+ DEBUGF("Eth_init: ......\n");
+
+ txIdx = 0;
+ rxIdx = 0;
+
+/* Initialize System Register */
+ if (SetupSystemRegs(&dat) < 0)
+ return -1;
+
+/* Initialize EMAC address */
+ SetupMacAddr(SrcAddr);
+
+/* Initialize TX and RX buffer */
+ for (i = 0; i < PKTBUFSRX; i++) {
+ rxbuf[i] = SetupRxBuffer(i);
+ if (i > 0) {
+ rxbuf[i - 1]->Dma[1].NEXT_DESC_PTR =
+ &(rxbuf[i]->Dma[0]);
+ if (i == (PKTBUFSRX - 1))
+ rxbuf[i]->Dma[1].NEXT_DESC_PTR =
+ &(rxbuf[0]->Dma[0]);
+ }
+ }
+ for (i = 0; i < TX_BUF_CNT; i++) {
+ txbuf[i] = SetupTxBuffer(i);
+ if (i > 0) {
+ txbuf[i - 1]->Dma[1].NEXT_DESC_PTR =
+ &(txbuf[i]->Dma[0]);
+ if (i == (TX_BUF_CNT - 1))
+ txbuf[i]->Dma[1].NEXT_DESC_PTR =
+ &(txbuf[0]->Dma[0]);
+ }
+ }
+
+ /* Set RX DMA */
+ *pDMA1_NEXT_DESC_PTR = &rxbuf[0]->Dma[0];
+ *pDMA1_CONFIG = *((u16 *) (void *)&rxbuf[0]->Dma[0].CONFIG);
+
+ /* Wait MII done */
+ PollMdcDone();
+
+ /* We enable only RX here */
+ /* ASTP : Enable Automatic Pad Stripping
+ PR : Promiscuous Mode for test
+ PSF : Receive frames with total length less than 64 bytes.
+ FDMODE : Full Duplex Mode
+ LB : Internal Loopback for test
+ RE : Receiver Enable */
+ if (dat == FDMODE)
+ opmode = ASTP | FDMODE | PSF;
+ else
+ opmode = ASTP | PSF;
+ opmode |= RE;
+#ifdef CONFIG_BFIN_MAC_RMII
+ opmode |= TE | RMII;
+#endif
+ /* Turn on the EMAC */
+ *pEMAC_OPMODE = opmode;
+ return 0;
+}
+
+static void bfin_EMAC_halt(struct eth_device *dev)
+{
+ DEBUGF("Eth_halt: ......\n");
+ /* Turn off the EMAC */
+ *pEMAC_OPMODE = 0x00000000;
+ /* Turn off the EMAC RX DMA */
+ *pDMA1_CONFIG = 0x0000;
+ *pDMA2_CONFIG = 0x0000;
+
+}
+
+void SetupMacAddr(u8 * MACaddr)
+{
+ char *tmp, *end;
+ int i;
+ /* this depends on a little-endian machine */
+ tmp = getenv("ethaddr");
+ if (tmp) {
+ for (i = 0; i < 6; i++) {
+ MACaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
+ if (tmp)
+ tmp = (*end) ? end + 1 : end;
+ }
+
+#ifndef CONFIG_NETCONSOLE
+ printf("Using MAC Address %02X:%02X:%02X:%02X:%02X:%02X\n",
+ MACaddr[0], MACaddr[1],
+ MACaddr[2], MACaddr[3], MACaddr[4], MACaddr[5]);
+#endif
+ *pEMAC_ADDRLO = MACaddr[0] | MACaddr[1] << 8 |
+ MACaddr[2] << 16 | MACaddr[3] << 24;
+ *pEMAC_ADDRHI = MACaddr[4] | MACaddr[5] << 8;
+ }
+}
+
+void PollMdcDone(void)
+{
+ /* poll the STABUSY bit */
+ while (*pEMAC_STAADD & STABUSY) ;
+}
+
+void WrPHYReg(u16 PHYAddr, u16 RegAddr, u16 Data)
+{
+ PollMdcDone();
+
+ *pEMAC_STADAT = Data;
+
+ *pEMAC_STAADD = SET_PHYAD(PHYAddr) | SET_REGAD(RegAddr) |
+ STAOP | STAIE | STABUSY;
+}
+
+/*********************************************************************************
+ * Read an off-chip register in a PHY through the MDC/MDIO port *
+ *********************************************************************************/
+u16 RdPHYReg(u16 PHYAddr, u16 RegAddr)
+{
+ u16 Data;
+
+ PollMdcDone();
+
+ *pEMAC_STAADD = SET_PHYAD(PHYAddr) | SET_REGAD(RegAddr) |
+ STAIE | STABUSY;
+
+ PollMdcDone();
+
+ Data = (u16) * pEMAC_STADAT;
+
+ PHYregs[RegAddr] = Data; /* save shadow copy */
+
+ return Data;
+}
+
+void SoftResetPHY(void)
+{
+ u16 phydat;
+ /* set the reset bit */
+ WrPHYReg(PHYADDR, PHY_MODECTL, PHY_RESET);
+ /* and clear it again */
+ WrPHYReg(PHYADDR, PHY_MODECTL, 0x0000);
+ do {
+ /* poll until reset is complete */
+ phydat = RdPHYReg(PHYADDR, PHY_MODECTL);
+ } while ((phydat & PHY_RESET) != 0);
+}
+
+int SetupSystemRegs(int *opmode)
+{
+ u16 sysctl, phydat;
+ int count = 0;
+ /* Enable PHY output */
+ *pVR_CTL |= PHYCLKOE;
+ /* MDC = 2.5 MHz */
+ sysctl = SET_MDCDIV(24);
+ /* Odd word alignment for Receive Frame DMA word */
+ /* Configure checksum support and rcve frame word alignment */
+ sysctl |= RXDWA | RXCKS;
+ *pEMAC_SYSCTL = sysctl;
+ /* auto negotiation on */
+ /* full duplex */
+ /* 100 Mbps */
+ phydat = PHY_ANEG_EN | PHY_DUPLEX | PHY_SPD_SET;
+ WrPHYReg(PHYADDR, PHY_MODECTL, phydat);
+ do {
+ udelay(1000);
+ phydat = RdPHYReg(PHYADDR, PHY_MODESTAT);
+ if (count > 3000) {
+ printf
+ ("Link is down, please check your network connection\n");
+ return -1;
+ }
+ count++;
+ } while (!(phydat & 0x0004));
+
+ phydat = RdPHYReg(PHYADDR, PHY_ANLPAR);
+
+ if ((phydat & 0x0100) || (phydat & 0x0040))
+ *opmode = FDMODE;
+ else
+ *opmode = 0;
+
+ *pEMAC_MMC_CTL = RSTC | CROLL;
+
+ /* Initialize the TX DMA channel registers */
+ *pDMA2_X_COUNT = 0;
+ *pDMA2_X_MODIFY = 4;
+ *pDMA2_Y_COUNT = 0;
+ *pDMA2_Y_MODIFY = 0;
+
+ /* Initialize the RX DMA channel registers */
+ *pDMA1_X_COUNT = 0;
+ *pDMA1_X_MODIFY = 4;
+ *pDMA1_Y_COUNT = 0;
+ *pDMA1_Y_MODIFY = 0;
+ return 0;
+}
+
+ADI_ETHER_BUFFER *SetupRxBuffer(int no)
+{
+ ADI_ETHER_FRAME_BUFFER *frmbuf;
+ ADI_ETHER_BUFFER *buf;
+ int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
+ int total_size = nobytes_buffer + RECV_BUFSIZE;
+
+ buf = (ADI_ETHER_BUFFER *) (RXBUF_BASE_ADDR + no * total_size);
+ frmbuf =
+ (ADI_ETHER_FRAME_BUFFER *) (RXBUF_BASE_ADDR + no * total_size +
+ nobytes_buffer);
+
+ memset(buf, 0x00, nobytes_buffer);
+ buf->FrmData = frmbuf;
+ memset(frmbuf, 0xfe, RECV_BUFSIZE);
+
+ /* set up first desc to point to receive frame buffer */
+ buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
+ buf->Dma[0].START_ADDR = (u32) buf->FrmData;
+ buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
+ buf->Dma[0].CONFIG.b_WNR = 1; /* Write to memory */
+ buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
+ buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
+ buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
+
+ /* set up second desc to point to status word */
+ buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
+ buf->Dma[1].START_ADDR = (u32) & buf->IPHdrChksum;
+ buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
+ buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
+ buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
+ buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
+ buf->Dma[1].CONFIG.b_NDSIZE = 5; /* must be 0 when FLOW is 0 */
+ buf->Dma[1].CONFIG.b_FLOW = 7; /* stop */
+
+ return buf;
+}
+
+ADI_ETHER_BUFFER *SetupTxBuffer(int no)
+{
+ ADI_ETHER_FRAME_BUFFER *frmbuf;
+ ADI_ETHER_BUFFER *buf;
+ int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
+ int total_size = nobytes_buffer + RECV_BUFSIZE;
+
+ buf = (ADI_ETHER_BUFFER *) (TXBUF_BASE_ADDR + no * total_size);
+ frmbuf =
+ (ADI_ETHER_FRAME_BUFFER *) (TXBUF_BASE_ADDR + no * total_size +
+ nobytes_buffer);
+
+ memset(buf, 0x00, nobytes_buffer);
+ buf->FrmData = frmbuf;
+ memset(frmbuf, 0x00, RECV_BUFSIZE);
+
+ /* set up first desc to point to receive frame buffer */
+ buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
+ buf->Dma[0].START_ADDR = (u32) buf->FrmData;
+ buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
+ buf->Dma[0].CONFIG.b_WNR = 0; /* Read to memory */
+ buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
+ buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
+ buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
+
+ /* set up second desc to point to status word */
+ buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
+ buf->Dma[1].START_ADDR = (u32) & buf->StatusWord;
+ buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
+ buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
+ buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
+ buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
+ buf->Dma[1].CONFIG.b_NDSIZE = 0; /* must be 0 when FLOW is 0 */
+ buf->Dma[1].CONFIG.b_FLOW = 0; /* stop */
+
+ return buf;
+}
+
+#if defined(CONFIG_POST) && defined(CFG_POST_ETHER)
+int ether_post_test(int flags)
+{
+ uchar buf[64];
+ int i, value = 0;
+ int length;
+
+ printf("\n--------");
+ bfin_EMAC_init(NULL, NULL);
+ /* construct the package */
+ buf[0] = buf[6] = (unsigned char)(*pEMAC_ADDRLO & 0xFF);
+ buf[1] = buf[7] = (unsigned char)((*pEMAC_ADDRLO & 0xFF00) >> 8);
+ buf[2] = buf[8] = (unsigned char)((*pEMAC_ADDRLO & 0xFF0000) >> 16);
+ buf[3] = buf[9] = (unsigned char)((*pEMAC_ADDRLO & 0xFF000000) >> 24);
+ buf[4] = buf[10] = (unsigned char)(*pEMAC_ADDRHI & 0xFF);
+ buf[5] = buf[11] = (unsigned char)((*pEMAC_ADDRHI & 0xFF00) >> 8);
+ buf[12] = 0x08; /* Type: ARP */
+ buf[13] = 0x06;
+ buf[14] = 0x00; /* Hardware type: Ethernet */
+ buf[15] = 0x01;
+ buf[16] = 0x08; /* Protocal type: IP */
+ buf[17] = 0x00;
+ buf[18] = 0x06; /* Hardware size */
+ buf[19] = 0x04; /* Protocol size */
+ buf[20] = 0x00; /* Opcode: request */
+ buf[21] = 0x01;
+
+ for (i = 0; i < 42; i++)
+ buf[i + 22] = i;
+ printf("--------Send 64 bytes......\n");
+ bfin_EMAC_send(NULL, (volatile void *)buf, 64);
+ for (i = 0; i < 100; i++) {
+ udelay(10000);
+ if ((rxbuf[rxIdx]->StatusWord & RX_COMP) != 0) {
+ value = 1;
+ break;
+ }
+ }
+ if (value == 0) {
+ printf("--------EMAC can't receive any data\n");
+ eth_halt();
+ return -1;
+ }
+ length = rxbuf[rxIdx]->StatusWord & 0x000007FF - 4;
+ for (i = 0; i < length; i++) {
+ if (rxbuf[rxIdx]->FrmData->Dest[i] != buf[i]) {
+ printf("--------EMAC receive error data!\n");
+ eth_halt();
+ return -1;
+ }
+ }
+ printf("--------receive %d bytes, matched\n", length);
+ bfin_EMAC_halt(NULL);
+ return 0;
+}
+#endif
+#endif /* CFG_CMD_NET */
--- /dev/null
+#define PHYADDR 0x01
+#define NO_PHY_REGS 0x20
+
+#define DEFAULT_PHY_PHYID1 0x0007
+#define DEFAULT_PHY_PHYID2 0xC0A3
+#define PHY_MODECTL 0x00
+#define PHY_MODESTAT 0x01
+#define PHY_PHYID1 0x02
+#define PHY_PHYID2 0x03
+#define PHY_ANAR 0x04
+#define PHY_ANLPAR 0x05
+#define PHY_ANER 0x06
+
+#define PHY_RESET 0x8000
+#define PHY_ANEG_EN 0x1000
+#define PHY_DUPLEX 0x0100
+#define PHY_SPD_SET 0x2000
+
+#define RECV_BUFSIZE (0x614)
+
+typedef volatile u32 reg32;
+typedef volatile u16 reg16;
+
+typedef struct ADI_DMA_CONFIG_REG {
+ u16 b_DMA_EN:1; /* 0 Enabled */
+ u16 b_WNR:1; /* 1 Direction */
+ u16 b_WDSIZE:2; /* 2:3 Transfer word size */
+ u16 b_DMA2D:1; /* 4 DMA mode */
+ u16 b_RESTART:1; /* 5 Retain FIFO */
+ u16 b_DI_SEL:1; /* 6 Data interrupt timing select */
+ u16 b_DI_EN:1; /* 7 Data interrupt enabled */
+ u16 b_NDSIZE:4; /* 8:11 Flex descriptor size */
+ u16 b_FLOW:3; /* 12:14Flow */
+} ADI_DMA_CONFIG_REG;
+
+typedef struct adi_ether_frame_buffer {
+ u16 NoBytes; /* the no. of following bytes */
+ u8 Dest[6]; /* destination MAC address */
+ u8 Srce[6]; /* source MAC address */
+ u16 LTfield; /* length/type field */
+ u8 Data[0]; /* payload bytes */
+} ADI_ETHER_FRAME_BUFFER;
+/* 16 bytes/struct */
+
+typedef struct dma_descriptor {
+ struct dma_descriptor *NEXT_DESC_PTR;
+ u32 START_ADDR;
+ ADI_DMA_CONFIG_REG CONFIG;
+} DMA_DESCRIPTOR;
+/* 10 bytes/struct in 12 bytes */
+
+typedef struct adi_ether_buffer {
+ DMA_DESCRIPTOR Dma[2]; /* first for the frame, second for the status */
+ ADI_ETHER_FRAME_BUFFER *FrmData;/* pointer to data */
+ struct adi_ether_buffer *pNext; /* next buffer */
+ struct adi_ether_buffer *pPrev; /* prev buffer */
+ u16 IPHdrChksum; /* the IP header checksum */
+ u16 IPPayloadChksum; /* the IP header and payload checksum */
+ volatile u32 StatusWord; /* the frame status word */
+} ADI_ETHER_BUFFER;
+/* 40 bytes/struct in 44 bytes */
+
+void SetupMacAddr(u8 * MACaddr);
+
+void PollMdcDone(void);
+void WrPHYReg(u16 PHYAddr, u16 RegAddr, u16 Data);
+u16 RdPHYReg(u16 PHYAddr, u16 RegAddr);
+void SoftResetPHY(void);
+void DumpPHYRegs(void);
+
+int SetupSystemRegs(int *opmode);
+
+/**
+ * is_zero_ether_addr - Determine if give Ethernet address is all zeros.
+ * @addr: Pointer to a six-byte array containing the Ethernet address
+ *
+ * Return true if the address is all zeroes.
+ */
+static inline int is_zero_ether_addr(const u8 * addr)
+{
+ return !(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]);
+}
+
+/**
+ * is_multicast_ether_addr - Determine if the Ethernet address is a multicast.
+ * @addr: Pointer to a six-byte array containing the Ethernet address
+ *
+ * Return true if the address is a multicast address.
+ * By definition the broadcast address is also a multicast address.
+ */
+static inline int is_multicast_ether_addr(const u8 * addr)
+{
+ return (0x01 & addr[0]);
+}
+
+/**
+ * is_valid_ether_addr - Determine if the given Ethernet address is valid
+ * @addr: Pointer to a six-byte array containing the Ethernet address
+ *
+ * Check that the Ethernet address (MAC) is not 00:00:00:00:00:00, is not
+ * a multicast address, and is not FF:FF:FF:FF:FF:FF.
+ *
+ * Return true if the address is valid.
+ */
+static inline int is_valid_ether_addr(const u8 * addr)
+{
+ /* FF:FF:FF:FF:FF:FF is a multicast address so we don't need to
+ * explicitly check for it here. */
+ return !is_multicast_ether_addr(addr) && !is_zero_ether_addr(addr);
+}
--- /dev/null
+/*
+ * U-boot - flash-defines.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __FLASHDEFINES_H__
+#define __FLASHDEFINES_H__
+
+#include <common.h>
+
+#define V_ULONG(a) (*(volatile unsigned long *)( a ))
+#define V_BYTE(a) (*(volatile unsigned char *)( a ))
+#define TRUE 0x1
+#define FALSE 0x0
+#define BUFFER_SIZE 0x80000
+#define NO_COMMAND 0
+#define GET_CODES 1
+#define RESET 2
+#define WRITE 3
+#define FILL 4
+#define ERASE_ALL 5
+#define ERASE_SECT 6
+#define READ 7
+#define GET_SECTNUM 8
+#define FLASH_START_L 0x0000
+#define FLASH_START_H 0x2000
+#define FLASH_MAN_ST 2
+#define RESET_VAL 0xF0
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+int get_codes(void);
+int poll_toggle_bit(long lOffset);
+void reset_flash(void);
+int erase_flash(void);
+int erase_block_flash(int);
+void unlock_flash(long lOffset);
+int write_data(long lStart, long lCount, uchar * pnData);
+int read_flash(long nOffset, int *pnValue);
+int write_flash(long nOffset, int nValue);
+void get_sector_number(long lOffset, int *pnSector);
+int GetSectorProtectionStatus(flash_info_t * info, int nSector);
+int GetOffset(int nBlock);
+int AFP_NumSectors = 71;
+long AFP_SectorSize2 = 0x10000;
+int AFP_SectorSize1 = 0x2000;
+
+#define NUM_SECTORS 71
+
+#define WRITESEQ1 0x0AAA
+#define WRITESEQ2 0x0554
+#define WRITESEQ3 0x0AAA
+#define WRITESEQ4 0x0AAA
+#define WRITESEQ5 0x0554
+#define WRITESEQ6 0x0AAA
+#define WRITEDATA1 0xaa
+#define WRITEDATA2 0x55
+#define WRITEDATA3 0x80
+#define WRITEDATA4 0xaa
+#define WRITEDATA5 0x55
+#define WRITEDATA6 0x10
+#define PriFlashABegin 0
+#define SecFlashABegin 8
+#define SecFlashBBegin 36
+#define PriFlashAOff 0x0
+#define PriFlashBOff 0x100000
+#define SecFlashAOff 0x10000
+#define SecFlashBOff 0x280000
+#define INVALIDLOCNSTART 0x20270000
+#define INVALIDLOCNEND 0x20280000
+#define BlockEraseVal 0x30
+#define UNLOCKDATA1 0xaa
+#define UNLOCKDATA2 0x55
+#define UNLOCKDATA3 0xa0
+#define GETCODEDATA1 0xaa
+#define GETCODEDATA2 0x55
+#define GETCODEDATA3 0x90
+#define SecFlashASec1Off 0x200000
+#define SecFlashASec2Off 0x204000
+#define SecFlashASec3Off 0x206000
+#define SecFlashASec4Off 0x208000
+#define SecFlashAEndOff 0x210000
+#define SecFlashBSec1Off 0x280000
+#define SecFlashBSec2Off 0x284000
+#define SecFlashBSec3Off 0x286000
+#define SecFlashBSec4Off 0x288000
+#define SecFlashBEndOff 0x290000
+
+#define SECT32 32
+#define SECT33 33
+#define SECT34 34
+#define SECT35 35
+#define SECT36 36
+#define SECT37 37
+#define SECT38 38
+#define SECT39 39
+
+#define FLASH_SUCCESS 0
+#define FLASH_FAIL -1
+
+#endif
--- /dev/null
+/*
+ * U-boot - flash.c Flash driver for PSD4256GV
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ * This file is based on BF533EzFlash.c originally written by Analog Devices, Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <malloc.h>
+#include <config.h>
+#include <asm/io.h>
+#include "flash-defines.h"
+
+void flash_reset(void)
+{
+ reset_flash();
+}
+
+unsigned long flash_get_size(ulong baseaddr, flash_info_t * info, int bank_flag)
+{
+ int id = 0, i = 0;
+ static int FlagDev = 1;
+
+ id = get_codes();
+ if (FlagDev) {
+ FlagDev = 0;
+ }
+ info->flash_id = id;
+ switch (bank_flag) {
+ case 0:
+ for (i = PriFlashABegin; i < SecFlashABegin; i++)
+ info->start[i] = (baseaddr + (i * AFP_SectorSize1));
+ for (i = SecFlashABegin; i < NUM_SECTORS; i++)
+ info->start[i] =
+ (baseaddr + SecFlashAOff +
+ ((i - SecFlashABegin) * AFP_SectorSize2));
+ info->size = 0x400000;
+ info->sector_count = NUM_SECTORS;
+ break;
+ case 1:
+ info->start[0] = baseaddr + SecFlashASec1Off;
+ info->start[1] = baseaddr + SecFlashASec2Off;
+ info->start[2] = baseaddr + SecFlashASec3Off;
+ info->start[3] = baseaddr + SecFlashASec4Off;
+ info->size = 0x10000;
+ info->sector_count = 4;
+ break;
+ case 2:
+ info->start[0] = baseaddr + SecFlashBSec1Off;
+ info->start[1] = baseaddr + SecFlashBSec2Off;
+ info->start[2] = baseaddr + SecFlashBSec3Off;
+ info->start[3] = baseaddr + SecFlashBSec4Off;
+ info->size = 0x10000;
+ info->sector_count = 4;
+ break;
+ }
+ return (info->size);
+}
+
+unsigned long flash_init(void)
+{
+ unsigned long size_b;
+ int i;
+
+ size_b = 0;
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ size_b = flash_get_size(CFG_FLASH_BASE, &flash_info[0], 0);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b == 0) {
+ printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b, size_b >> 20);
+ }
+
+ /* flash_protect (int flag, ulong from, ulong to, flash_info_t *info) */
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_FLASH_BASE,
+ (flash_info[0].start[2] - 1), &flash_info[0]);
+#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
+ (void)flash_protect(FLAG_PROTECT_SET, 0x203F0000, 0x203FFFFF,
+ &flash_info[0]);
+#endif
+
+ return (size_b);
+}
+
+void flash_print_info(flash_info_t * info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id) {
+ case (STM_ID_29W320EB & 0xFFFF):
+ case (STM_ID_29W320DB & 0xFFFF):
+ printf("ST Microelectronics ");
+ break;
+ default:
+ printf("Unknown Vendor: (0x%08X) ", info->flash_id);
+ break;
+ }
+ for (i = 0; i < info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf("\n ");
+ printf(" %08lX%s",
+ info->start[i], info->protect[i] ? " (RO)" : " ");
+ }
+ printf("\n");
+ return;
+}
+
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+ int cnt = 0, i;
+ int prot, sect;
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect])
+ prot++;
+ }
+ if (prot)
+ printf("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ else
+ printf("\n");
+
+ cnt = s_last - s_first + 1;
+
+#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
+ printf("Erasing Flash locations, Please Wait\n");
+ for (i = s_first; i <= s_last; i++) {
+ if (info->protect[i] == 0) { /* not protected */
+ if (erase_block_flash(i) < 0) {
+ printf("Error Sector erasing \n");
+ return FLASH_FAIL;
+ }
+ }
+ }
+#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
+ if (cnt == FLASH_TOT_SECT) {
+ printf("Erasing flash, Please Wait \n");
+ if (erase_flash() < 0) {
+ printf("Erasing flash failed \n");
+ return FLASH_FAIL;
+ }
+ } else {
+ printf("Erasing Flash locations, Please Wait\n");
+ for (i = s_first; i <= s_last; i++) {
+ if (info->protect[i] == 0) { /* not protected */
+ if (erase_block_flash(i) < 0) {
+ printf("Error Sector erasing \n");
+ return FLASH_FAIL;
+ }
+ }
+ }
+ }
+#endif
+ printf("\n");
+ return FLASH_SUCCESS;
+}
+
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ int d;
+ if (addr % 2) {
+ read_flash(addr - 1 - CFG_FLASH_BASE, &d);
+ d = (int)((d & 0x00FF) | (*src++ << 8));
+ write_data(addr - 1, 2, (uchar *) & d);
+ write_data(addr + 1, cnt - 1, src);
+ } else
+ write_data(addr, cnt, src);
+ return FLASH_SUCCESS;
+}
+
+int write_data(long lStart, long lCount, uchar * pnData)
+{
+ long i = 0;
+ unsigned long ulOffset = lStart - CFG_FLASH_BASE;
+ int d;
+ int nSector = 0;
+ int flag = 0;
+
+ if (lCount % 2) {
+ flag = 1;
+ lCount = lCount - 1;
+ }
+
+ for (i = 0; i < lCount - 1; i += 2, ulOffset += 2) {
+ get_sector_number(ulOffset, &nSector);
+ read_flash(ulOffset, &d);
+ if (d != 0xffff) {
+ printf
+ ("Flash not erased at offset 0x%x Please erase to reprogram \n",
+ ulOffset);
+ return FLASH_FAIL;
+ }
+ unlock_flash(ulOffset);
+ d = (int)(pnData[i] | pnData[i + 1] << 8);
+ write_flash(ulOffset, d);
+ if (poll_toggle_bit(ulOffset) < 0) {
+ printf("Error programming the flash \n");
+ return FLASH_FAIL;
+ }
+ if ((i > 0) && (!(i % AFP_SectorSize2)))
+ printf(".");
+ }
+ if (flag) {
+ get_sector_number(ulOffset, &nSector);
+ read_flash(ulOffset, &d);
+ if (d != 0xffff) {
+ printf
+ ("Flash not erased at offset 0x%x Please erase to reprogram \n",
+ ulOffset);
+ return FLASH_FAIL;
+ }
+ unlock_flash(ulOffset);
+ d = (int)(pnData[i] | (d & 0xFF00));
+ write_flash(ulOffset, d);
+ if (poll_toggle_bit(ulOffset) < 0) {
+ printf("Error programming the flash \n");
+ return FLASH_FAIL;
+ }
+ }
+ return FLASH_SUCCESS;
+}
+
+int write_flash(long nOffset, int nValue)
+{
+ long addr;
+
+ addr = (CFG_FLASH_BASE + nOffset);
+ *(unsigned volatile short *)addr = nValue;
+ sync();
+#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
+ if (icache_status())
+ udelay(CONFIG_CCLK_HZ / 1000000);
+#endif
+ return FLASH_SUCCESS;
+}
+
+int read_flash(long nOffset, int *pnValue)
+{
+ unsigned short *pFlashAddr =
+ (unsigned short *)(CFG_FLASH_BASE + nOffset);
+
+ *pnValue = *pFlashAddr;
+
+ return TRUE;
+}
+
+int poll_toggle_bit(long lOffset)
+{
+ unsigned int u1, u2;
+ volatile unsigned long *FB =
+ (volatile unsigned long *)(CFG_FLASH_BASE + lOffset);
+ while (1) {
+ u1 = *(volatile unsigned short *)FB;
+ u2 = *(volatile unsigned short *)FB;
+ u1 ^= u2;
+ if (!(u1 & 0x0040))
+ break;
+ if (!(u2 & 0x0020))
+ continue;
+ else {
+ u1 = *(volatile unsigned short *)FB;
+ u2 = *(volatile unsigned short *)FB;
+ u1 ^= u2;
+ if (!(u1 & 0x0040))
+ break;
+ else {
+ reset_flash();
+ return FLASH_FAIL;
+ }
+ }
+ }
+ return FLASH_SUCCESS;
+}
+
+void reset_flash(void)
+{
+ write_flash(WRITESEQ1, RESET_VAL);
+ /* Wait for 10 micro seconds */
+ udelay(10);
+}
+
+int erase_flash(void)
+{
+ write_flash(WRITESEQ1, WRITEDATA1);
+ write_flash(WRITESEQ2, WRITEDATA2);
+ write_flash(WRITESEQ3, WRITEDATA3);
+ write_flash(WRITESEQ4, WRITEDATA4);
+ write_flash(WRITESEQ5, WRITEDATA5);
+ write_flash(WRITESEQ6, WRITEDATA6);
+
+ if (poll_toggle_bit(0x0000) < 0)
+ return FLASH_FAIL;
+
+ return FLASH_SUCCESS;
+}
+
+int erase_block_flash(int nBlock)
+{
+ long ulSectorOff = 0x0;
+
+ if ((nBlock < 0) || (nBlock > AFP_NumSectors))
+ return FALSE;
+
+ // figure out the offset of the block in flash
+ if ((nBlock >= 0) && (nBlock < SecFlashABegin))
+ ulSectorOff = nBlock * AFP_SectorSize1;
+
+ else if ((nBlock >= SecFlashABegin) && (nBlock < NUM_SECTORS))
+ ulSectorOff =
+ SecFlashAOff + (nBlock - SecFlashABegin) * AFP_SectorSize2;
+ // no such sector
+ else
+ return FLASH_FAIL;
+
+ write_flash((WRITESEQ1 | ulSectorOff), WRITEDATA1);
+ write_flash((WRITESEQ2 | ulSectorOff), WRITEDATA2);
+ write_flash((WRITESEQ3 | ulSectorOff), WRITEDATA3);
+ write_flash((WRITESEQ4 | ulSectorOff), WRITEDATA4);
+ write_flash((WRITESEQ5 | ulSectorOff), WRITEDATA5);
+
+ write_flash(ulSectorOff, BlockEraseVal);
+
+ if (poll_toggle_bit(ulSectorOff) < 0)
+ return FLASH_FAIL;
+ printf(".");
+
+ return FLASH_SUCCESS;
+}
+
+void unlock_flash(long ulOffset)
+{
+ unsigned long ulOffsetAddr = ulOffset;
+ ulOffsetAddr &= 0xFFFF0000;
+
+ write_flash((WRITESEQ1 | ulOffsetAddr), UNLOCKDATA1);
+ write_flash((WRITESEQ2 | ulOffsetAddr), UNLOCKDATA2);
+ write_flash((WRITESEQ3 | ulOffsetAddr), UNLOCKDATA3);
+}
+
+int get_codes()
+{
+ int dev_id = 0;
+
+ write_flash(WRITESEQ1, GETCODEDATA1);
+ write_flash(WRITESEQ2, GETCODEDATA2);
+ write_flash(WRITESEQ3, GETCODEDATA3);
+
+ read_flash(0x0402, &dev_id);
+ dev_id &= 0x0000FFFF;
+
+ reset_flash();
+
+ return dev_id;
+}
+
+void get_sector_number(long ulOffset, int *pnSector)
+{
+ int nSector = 0;
+ long lMainEnd = 0x400000;
+ long lBootEnd = 0x10000;
+
+ // sector numbers for the FLASH A boot sectors
+ if (ulOffset < lBootEnd) {
+ nSector = (int)ulOffset / AFP_SectorSize1;
+ }
+ // sector numbers for the FLASH B boot sectors
+ else if ((ulOffset >= lBootEnd) && (ulOffset < lMainEnd)) {
+ nSector = ((ulOffset / (AFP_SectorSize2)) + 7);
+ }
+ // if it is a valid sector, set it
+ if ((nSector >= 0) && (nSector < AFP_NumSectors))
+ *pnSector = nSector;
+
+}
--- /dev/null
+/*
+ * (C) Copyright 2006 Aubrey.Li, aubrey.li@analog.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#include <nand.h>
+
+#define CONCAT(a,b,c,d) a ## b ## c ## d
+#define PORT(a,b) CONCAT(pPORT,a,b,)
+
+#ifndef CONFIG_NAND_GPIO_PORT
+#define CONFIG_NAND_GPIO_PORT F
+#endif
+
+/*
+ * hardware specific access to control-lines
+ */
+static void bfin_hwcontrol(struct mtd_info *mtd, int cmd)
+{
+ register struct nand_chip *this = mtd->priv;
+
+ switch (cmd) {
+
+ case NAND_CTL_SETCLE:
+ this->IO_ADDR_W = CFG_NAND_BASE + BFIN_NAND_CLE;
+ break;
+ case NAND_CTL_CLRCLE:
+ this->IO_ADDR_W = CFG_NAND_BASE;
+ break;
+
+ case NAND_CTL_SETALE:
+ this->IO_ADDR_W = CFG_NAND_BASE + BFIN_NAND_ALE;
+ break;
+ case NAND_CTL_CLRALE:
+ this->IO_ADDR_W = CFG_NAND_BASE;
+ break;
+ case NAND_CTL_SETNCE:
+ case NAND_CTL_CLRNCE:
+ break;
+ }
+
+ this->IO_ADDR_R = this->IO_ADDR_W;
+
+ /* Drain the writebuffer */
+ sync();
+}
+
+int bfin_device_ready(struct mtd_info *mtd)
+{
+ int ret = (*PORT(CONFIG_NAND_GPIO_PORT, IO) & BFIN_NAND_READY) ? 1 : 0;
+ sync();
+ return ret;
+}
+
+/*
+ * Board-specific NAND initialization. The following members of the
+ * argument are board-specific (per include/linux/mtd/nand.h):
+ * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
+ * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
+ * - hwcontrol: hardwarespecific function for accesing control-lines
+ * - dev_ready: hardwarespecific function for accesing device ready/busy line
+ * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
+ * only be provided if a hardware ECC is available
+ * - eccmode: mode of ecc, see defines
+ * - chip_delay: chip dependent delay for transfering data from array to
+ * read regs (tR)
+ * - options: various chip options. They can partly be set to inform
+ * nand_scan about special functionality. See the defines for further
+ * explanation
+ * Members with a "?" were not set in the merged testing-NAND branch,
+ * so they are not set here either.
+ */
+void board_nand_init(struct nand_chip *nand)
+{
+ *PORT(CONFIG_NAND_GPIO_PORT, _FER) &= ~BFIN_NAND_READY;
+ *PORT(CONFIG_NAND_GPIO_PORT, IO_DIR) &= ~BFIN_NAND_READY;
+ *PORT(CONFIG_NAND_GPIO_PORT, IO_INEN) |= BFIN_NAND_READY;
+
+ nand->hwcontrol = bfin_hwcontrol;
+ nand->eccmode = NAND_ECC_SOFT;
+ nand->dev_ready = bfin_device_ready;
+ nand->chip_delay = 30;
+}
+#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
--- /dev/null
+#include <common.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_POST
+
+#include <post.h>
+#include <watchdog.h>
+
+#if CONFIG_POST & CFG_POST_MEMORY
+#define CLKIN 25000000
+#define PATTERN1 0x5A5A5A5A
+#define PATTERN2 0xAAAAAAAA
+
+#define CCLK_NUM 4
+#define SCLK_NUM 3
+
+void post_out_buff(char *buff);
+int post_key_pressed(void);
+void post_init_pll(int mult, int div);
+int post_init_sdram(int sclk);
+void post_init_uart(int sclk);
+
+const int pll[CCLK_NUM][SCLK_NUM][2] = {
+ {{20, 4}, {20, 5}, {20, 10}}, /* CCLK = 500M */
+ {{16, 4}, {16, 5}, {16, 8}}, /* CCLK = 400M */
+ {{8, 2}, {8, 4}, {8, 5}}, /* CCLK = 200M */
+ {{4, 1}, {4, 2}, {4, 4}} /* CCLK = 100M */
+};
+const char *const log[CCLK_NUM][SCLK_NUM] = {
+ {"CCLK-500Mhz SCLK-125Mhz: Writing...\0",
+ "CCLK-500Mhz SCLK-100Mhz: Writing...\0",
+ "CCLK-500Mhz SCLK- 50Mhz: Writing...\0",},
+ {"CCLK-400Mhz SCLK-100Mhz: Writing...\0",
+ "CCLK-400Mhz SCLK- 80Mhz: Writing...\0",
+ "CCLK-400Mhz SCLK- 50Mhz: Writing...\0",},
+ {"CCLK-200Mhz SCLK-100Mhz: Writing...\0",
+ "CCLK-200Mhz SCLK- 50Mhz: Writing...\0",
+ "CCLK-200Mhz SCLK- 40Mhz: Writing...\0",},
+ {"CCLK-100Mhz SCLK-100Mhz: Writing...\0",
+ "CCLK-100Mhz SCLK- 50Mhz: Writing...\0",
+ "CCLK-100Mhz SCLK- 25Mhz: Writing...\0",},
+};
+
+int memory_post_test(int flags)
+{
+ int addr;
+ int m, n;
+ int sclk, sclk_temp;
+ int ret = 1;
+
+ sclk_temp = CLKIN / 1000000;
+ sclk_temp = sclk_temp * CONFIG_VCO_MULT;
+ for (sclk = 0; sclk_temp > 0; sclk++)
+ sclk_temp -= CONFIG_SCLK_DIV;
+ sclk = sclk * 1000000;
+ post_init_uart(sclk);
+ if (post_key_pressed() == 0)
+ return 0;
+
+ for (m = 0; m < CCLK_NUM; m++) {
+ for (n = 0; n < SCLK_NUM; n++) {
+ /* Calculate the sclk */
+ sclk_temp = CLKIN / 1000000;
+ sclk_temp = sclk_temp * pll[m][n][0];
+ for (sclk = 0; sclk_temp > 0; sclk++)
+ sclk_temp -= pll[m][n][1];
+ sclk = sclk * 1000000;
+
+ post_init_pll(pll[m][n][0], pll[m][n][1]);
+ post_init_sdram(sclk);
+ post_init_uart(sclk);
+ post_out_buff("\n\r\0");
+ post_out_buff(log[m][n]);
+ for (addr = 0x0; addr < CFG_MAX_RAM_SIZE; addr += 4)
+ *(unsigned long *)addr = PATTERN1;
+ post_out_buff("Reading...\0");
+ for (addr = 0x0; addr < CFG_MAX_RAM_SIZE; addr += 4) {
+ if ((*(unsigned long *)addr) != PATTERN1) {
+ post_out_buff("Error\n\r\0");
+ ret = 0;
+ }
+ }
+ post_out_buff("OK\n\r\0");
+ }
+ }
+ if (ret)
+ post_out_buff("memory POST passed\n\r\0");
+ else
+ post_out_buff("memory POST failed\n\r\0");
+
+ post_out_buff("\n\r\n\r\0");
+ return 1;
+}
+
+void post_init_uart(int sclk)
+{
+ int divisor;
+
+ for (divisor = 0; sclk > 0; divisor++)
+ sclk -= 57600 * 16;
+
+ *pPORTF_FER = 0x000F;
+ *pPORTH_FER = 0xFFFF;
+
+ *pUART_GCTL = 0x00;
+ *pUART_LCR = 0x83;
+ sync();
+ *pUART_DLL = (divisor & 0xFF);
+ sync();
+ *pUART_DLH = ((divisor >> 8) & 0xFF);
+ sync();
+ *pUART_LCR = 0x03;
+ sync();
+ *pUART_GCTL = 0x01;
+ sync();
+}
+
+void post_out_buff(char *buff)
+{
+
+ int i = 0;
+ for (i = 0; i < 0x80000; i++) ;
+ i = 0;
+ while ((buff[i] != '\0') && (i != 100)) {
+ while (!(*pUART_LSR & 0x20)) ;
+ *pUART_THR = buff[i];
+ sync();
+ i++;
+ }
+ for (i = 0; i < 0x80000; i++) ;
+}
+
+/* Using sw10-PF5 as the hotkey */
+#define KEY_LOOP 0x80000
+#define KEY_DELAY 0x80
+int post_key_pressed(void)
+{
+ int i, n;
+ unsigned short value;
+
+ *pPORTF_FER &= ~PF5;
+ *pPORTFIO_DIR &= ~PF5;
+ *pPORTFIO_INEN |= PF5;
+ sync();
+
+ post_out_buff("########Press SW10 to enter Memory POST########: 3\0");
+ for (i = 0; i < KEY_LOOP; i++) {
+ value = *pPORTFIO & PF5;
+ if (*pUART0_RBR == 0x0D) {
+ value = 0;
+ goto key_pressed;
+ }
+ if (value != 0) {
+ goto key_pressed;
+ }
+ for (n = 0; n < KEY_DELAY; n++)
+ asm("nop");
+ }
+ post_out_buff("\b2\0");
+
+ for (i = 0; i < KEY_LOOP; i++) {
+ value = *pPORTFIO & PF5;
+ if (*pUART0_RBR == 0x0D) {
+ value = 0;
+ goto key_pressed;
+ }
+ if (value != 0) {
+ goto key_pressed;
+ }
+ for (n = 0; n < KEY_DELAY; n++)
+ asm("nop");
+ }
+ post_out_buff("\b1\0");
+
+ for (i = 0; i < KEY_LOOP; i++) {
+ value = *pPORTFIO & PF5;
+ if (*pUART0_RBR == 0x0D) {
+ value = 0;
+ goto key_pressed;
+ }
+ if (value != 0) {
+ goto key_pressed;
+ }
+ for (n = 0; n < KEY_DELAY; n++)
+ asm("nop");
+ }
+ key_pressed:
+ post_out_buff("\b0");
+ post_out_buff("\n\r\0");
+ if (value == 0)
+ return 0;
+ post_out_buff("Hotkey has been pressed, Enter POST . . . . . .\n\r\0");
+ return 1;
+}
+
+void post_init_pll(int mult, int div)
+{
+
+ *pSIC_IWR = 0x01;
+ *pPLL_CTL = (mult << 9);
+ *pPLL_DIV = div;
+ asm("CLI R2;");
+ asm("IDLE;");
+ asm("STI R2;");
+ while (!(*pPLL_STAT & 0x20)) ;
+}
+
+int post_init_sdram(int sclk)
+{
+ int SDRAM_tRP, SDRAM_tRP_num, SDRAM_tRAS, SDRAM_tRAS_num, SDRAM_tRCD,
+ SDRAM_tWR;
+ int SDRAM_Tref, SDRAM_NRA, SDRAM_CL, SDRAM_SIZE, SDRAM_WIDTH,
+ mem_SDGCTL, mem_SDBCTL, mem_SDRRC;
+
+ if ((sclk > 119402985)) {
+ SDRAM_tRP = TRP_2;
+ SDRAM_tRP_num = 2;
+ SDRAM_tRAS = TRAS_7;
+ SDRAM_tRAS_num = 7;
+ SDRAM_tRCD = TRCD_2;
+ SDRAM_tWR = TWR_2;
+ } else if ((sclk > 104477612) && (sclk <= 119402985)) {
+ SDRAM_tRP = TRP_2;
+ SDRAM_tRP_num = 2;
+ SDRAM_tRAS = TRAS_6;
+ SDRAM_tRAS_num = 6;
+ SDRAM_tRCD = TRCD_2;
+ SDRAM_tWR = TWR_2;
+ } else if ((sclk > 89552239) && (sclk <= 104477612)) {
+ SDRAM_tRP = TRP_2;
+ SDRAM_tRP_num = 2;
+ SDRAM_tRAS = TRAS_5;
+ SDRAM_tRAS_num = 5;
+ SDRAM_tRCD = TRCD_2;
+ SDRAM_tWR = TWR_2;
+ } else if ((sclk > 74626866) && (sclk <= 89552239)) {
+ SDRAM_tRP = TRP_2;
+ SDRAM_tRP_num = 2;
+ SDRAM_tRAS = TRAS_4;
+ SDRAM_tRAS_num = 4;
+ SDRAM_tRCD = TRCD_2;
+ SDRAM_tWR = TWR_2;
+ } else if ((sclk > 66666667) && (sclk <= 74626866)) {
+ SDRAM_tRP = TRP_2;
+ SDRAM_tRP_num = 2;
+ SDRAM_tRAS = TRAS_3;
+ SDRAM_tRAS_num = 3;
+ SDRAM_tRCD = TRCD_2;
+ SDRAM_tWR = TWR_2;
+ } else if ((sclk > 59701493) && (sclk <= 66666667)) {
+ SDRAM_tRP = TRP_1;
+ SDRAM_tRP_num = 1;
+ SDRAM_tRAS = TRAS_4;
+ SDRAM_tRAS_num = 4;
+ SDRAM_tRCD = TRCD_1;
+ SDRAM_tWR = TWR_2;
+ } else if ((sclk > 44776119) && (sclk <= 59701493)) {
+ SDRAM_tRP = TRP_1;
+ SDRAM_tRP_num = 1;
+ SDRAM_tRAS = TRAS_3;
+ SDRAM_tRAS_num = 3;
+ SDRAM_tRCD = TRCD_1;
+ SDRAM_tWR = TWR_2;
+ } else if ((sclk > 29850746) && (sclk <= 44776119)) {
+ SDRAM_tRP = TRP_1;
+ SDRAM_tRP_num = 1;
+ SDRAM_tRAS = TRAS_2;
+ SDRAM_tRAS_num = 2;
+ SDRAM_tRCD = TRCD_1;
+ SDRAM_tWR = TWR_2;
+ } else if (sclk <= 29850746) {
+ SDRAM_tRP = TRP_1;
+ SDRAM_tRP_num = 1;
+ SDRAM_tRAS = TRAS_1;
+ SDRAM_tRAS_num = 1;
+ SDRAM_tRCD = TRCD_1;
+ SDRAM_tWR = TWR_2;
+ } else {
+ SDRAM_tRP = TRP_1;
+ SDRAM_tRP_num = 1;
+ SDRAM_tRAS = TRAS_1;
+ SDRAM_tRAS_num = 1;
+ SDRAM_tRCD = TRCD_1;
+ SDRAM_tWR = TWR_2;
+ }
+ /*SDRAM INFORMATION: */
+ SDRAM_Tref = 64; /* Refresh period in milliseconds */
+ SDRAM_NRA = 4096; /* Number of row addresses in SDRAM */
+ SDRAM_CL = CL_3; /* 2 */
+
+ SDRAM_SIZE = EBSZ_64;
+ SDRAM_WIDTH = EBCAW_10;
+
+ mem_SDBCTL = SDRAM_WIDTH | SDRAM_SIZE | EBE;
+
+ /* Equation from section 17 (p17-46) of BF533 HRM */
+ mem_SDRRC =
+ (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) -
+ (SDRAM_tRAS_num + SDRAM_tRP_num);
+
+ /* Enable SCLK Out */
+ mem_SDGCTL =
+ (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR
+ | PSS);
+
+ sync();
+
+ *pEBIU_SDGCTL |= 0x1000000;
+ /* Set the SDRAM Refresh Rate control register based on SSCLK value */
+ *pEBIU_SDRRC = mem_SDRRC;
+
+ /* SDRAM Memory Bank Control Register */
+ *pEBIU_SDBCTL = mem_SDBCTL;
+
+ /* SDRAM Memory Global Control Register */
+ *pEBIU_SDGCTL = mem_SDGCTL;
+ sync();
+ return mem_SDRRC;
+}
+
+#endif /* CONFIG_POST & CFG_POST_MEMORY */
+#endif /* CONFIG_POST */
--- /dev/null
+/****************************************************************************
+ * SPI flash driver for M25P64
+ ****************************************************************************/
+#include <common.h>
+#include <linux/ctype.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_SPI)
+
+/* Application definitions */
+
+#define NUM_SECTORS 128 /* number of sectors */
+#define SECTOR_SIZE 0x10000
+#define NOP_NUM 1000
+
+#define COMMON_SPI_SETTINGS (SPE|MSTR|CPHA|CPOL) /* Settings to the SPI_CTL */
+#define TIMOD01 (0x01) /* stes the SPI to work with core instructions */
+
+/* Flash commands */
+#define SPI_WREN (0x06) /*Set Write Enable Latch */
+#define SPI_WRDI (0x04) /*Reset Write Enable Latch */
+#define SPI_RDSR (0x05) /*Read Status Register */
+#define SPI_WRSR (0x01) /*Write Status Register */
+#define SPI_READ (0x03) /*Read data from memory */
+#define SPI_FAST_READ (0x0B) /*Read data from memory */
+#define SPI_PP (0x02) /*Program Data into memory */
+#define SPI_SE (0xD8) /*Erase one sector in memory */
+#define SPI_BE (0xC7) /*Erase all memory */
+#define WIP (0x1) /*Check the write in progress bit of the SPI status register */
+#define WEL (0x2) /*Check the write enable bit of the SPI status register */
+
+#define TIMEOUT 350000000
+
+typedef enum {
+ NO_ERR,
+ POLL_TIMEOUT,
+ INVALID_SECTOR,
+ INVALID_BLOCK,
+} ERROR_CODE;
+
+void spi_init_f(void);
+void spi_init_r(void);
+ssize_t spi_read(uchar *, int, uchar *, int);
+ssize_t spi_write(uchar *, int, uchar *, int);
+
+char ReadStatusRegister(void);
+void Wait_For_SPIF(void);
+void SetupSPI(const int spi_setting);
+void SPI_OFF(void);
+void SendSingleCommand(const int iCommand);
+
+ERROR_CODE GetSectorNumber(unsigned long ulOffset, int *pnSector);
+ERROR_CODE EraseBlock(int nBlock);
+ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData);
+ERROR_CODE WriteData(unsigned long ulStart, long lCount, int *pnData);
+ERROR_CODE Wait_For_Status(char Statusbit);
+ERROR_CODE Wait_For_WEL(void);
+
+/*
+ * Function: spi_init_f
+ * Description: Init SPI-Controller (ROM part)
+ * return: ---
+ */
+void spi_init_f(void)
+{
+}
+
+/*
+ * Function: spi_init_r
+ * Description: Init SPI-Controller (RAM part) -
+ * The malloc engine is ready and we can move our buffers to
+ * normal RAM
+ * return: ---
+ */
+void spi_init_r(void)
+{
+ return;
+}
+
+/*
+ * Function: spi_write
+ */
+ssize_t spi_write(uchar * addr, int alen, uchar * buffer, int len)
+{
+ unsigned long offset;
+ int start_block, end_block;
+ int start_byte, end_byte;
+ ERROR_CODE result = NO_ERR;
+ uchar temp[SECTOR_SIZE];
+ int i, num;
+
+ offset = addr[0] << 16 | addr[1] << 8 | addr[2];
+ /* Get the start block number */
+ result = GetSectorNumber(offset, &start_block);
+ if (result == INVALID_SECTOR) {
+ printf("Invalid sector! ");
+ return 0;
+ }
+ /* Get the end block number */
+ result = GetSectorNumber(offset + len - 1, &end_block);
+ if (result == INVALID_SECTOR) {
+ printf("Invalid sector! ");
+ return 0;
+ }
+
+ for (num = start_block; num <= end_block; num++) {
+ ReadData(num * SECTOR_SIZE, SECTOR_SIZE, (int *)temp);
+ start_byte = num * SECTOR_SIZE;
+ end_byte = (num + 1) * SECTOR_SIZE - 1;
+ if (start_byte < offset)
+ start_byte = offset;
+ if (end_byte > (offset + len))
+ end_byte = (offset + len - 1);
+ for (i = start_byte; i <= end_byte; i++)
+ temp[i - num * SECTOR_SIZE] = buffer[i - offset];
+ EraseBlock(num);
+ result = WriteData(num * SECTOR_SIZE, SECTOR_SIZE, (int *)temp);
+ if (result != NO_ERR)
+ return 0;
+ printf(".");
+ }
+ return len;
+}
+
+/*
+ * Function: spi_read
+ */
+ssize_t spi_read(uchar * addr, int alen, uchar * buffer, int len)
+{
+ unsigned long offset;
+ offset = addr[0] << 16 | addr[1] << 8 | addr[2];
+ ReadData(offset, len, (int *)buffer);
+ return len;
+}
+
+void SendSingleCommand(const int iCommand)
+{
+ unsigned short dummy;
+
+ /* turns on the SPI in single write mode */
+ SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
+
+ /* sends the actual command to the SPI TX register */
+ *pSPI_TDBR = iCommand;
+ sync();
+
+ /* The SPI status register will be polled to check the SPIF bit */
+ Wait_For_SPIF();
+
+ dummy = *pSPI_RDBR;
+
+ /* The SPI will be turned off */
+ SPI_OFF();
+
+}
+
+void SetupSPI(const int spi_setting)
+{
+
+ if (icache_status() || dcache_status())
+ udelay(CONFIG_CCLK_HZ / 50000000);
+ /*sets up the PF10 to be the slave select of the SPI */
+ *pPORTF_FER |= (PF10 | PF11 | PF12 | PF13);
+ *pSPI_FLG = 0xFF02;
+ *pSPI_BAUD = CONFIG_SPI_BAUD;
+ *pSPI_CTL = spi_setting;
+ sync();
+
+ *pSPI_FLG = 0xFD02;
+ sync();
+}
+
+void SPI_OFF(void)
+{
+
+ *pSPI_CTL = 0x0400; /* disable SPI */
+ *pSPI_FLG = 0;
+ *pSPI_BAUD = 0;
+ sync();
+ udelay(CONFIG_CCLK_HZ / 50000000);
+
+}
+
+void Wait_For_SPIF(void)
+{
+ unsigned short dummyread;
+ while ((*pSPI_STAT & TXS)) ;
+ while (!(*pSPI_STAT & SPIF)) ;
+ while (!(*pSPI_STAT & RXS)) ;
+ /* Read dummy to empty the receive register */
+ dummyread = *pSPI_RDBR;
+}
+
+ERROR_CODE Wait_For_WEL(void)
+{
+ int i;
+ char status_register = 0;
+ ERROR_CODE ErrorCode = NO_ERR;
+
+ for (i = 0; i < TIMEOUT; i++) {
+ status_register = ReadStatusRegister();
+ if ((status_register & WEL)) {
+ ErrorCode = NO_ERR;
+ break;
+ }
+ ErrorCode = POLL_TIMEOUT; /* Time out error */
+ };
+
+ return ErrorCode;
+}
+
+ERROR_CODE Wait_For_Status(char Statusbit)
+{
+ int i;
+ char status_register = 0xFF;
+ ERROR_CODE ErrorCode = NO_ERR;
+
+ for (i = 0; i < TIMEOUT; i++) {
+ status_register = ReadStatusRegister();
+ if (!(status_register & Statusbit)) {
+ ErrorCode = NO_ERR;
+ break;
+ }
+ ErrorCode = POLL_TIMEOUT; /* Time out error */
+ };
+
+ return ErrorCode;
+}
+
+char ReadStatusRegister(void)
+{
+ char status_register = 0;
+
+ SetupSPI((COMMON_SPI_SETTINGS | TIMOD01)); /* Turn on the SPI */
+
+ *pSPI_TDBR = SPI_RDSR; /* send instruction to read status register */
+ sync();
+ Wait_For_SPIF(); /*wait until the instruction has been sent */
+ *pSPI_TDBR = 0; /*send dummy to receive the status register */
+ sync();
+ Wait_For_SPIF(); /*wait until the data has been sent */
+ status_register = *pSPI_RDBR; /*read the status register */
+
+ SPI_OFF(); /* Turn off the SPI */
+
+ return status_register;
+}
+
+ERROR_CODE GetSectorNumber(unsigned long ulOffset, int *pnSector)
+{
+ int nSector = 0;
+ ERROR_CODE ErrorCode = NO_ERR;
+
+ if (ulOffset > (NUM_SECTORS * 0x10000 - 1)) {
+ ErrorCode = INVALID_SECTOR;
+ return ErrorCode;
+ }
+
+ nSector = (int)ulOffset / 0x10000;
+ *pnSector = nSector;
+
+ return ErrorCode;
+}
+
+ERROR_CODE EraseBlock(int nBlock)
+{
+ unsigned long ulSectorOff = 0x0, ShiftValue;
+ ERROR_CODE ErrorCode = NO_ERR;
+
+ /* if the block is invalid just return */
+ if ((nBlock < 0) || (nBlock > NUM_SECTORS)) {
+ ErrorCode = INVALID_BLOCK;
+ return ErrorCode;
+ }
+ /* figure out the offset of the block in flash */
+ if ((nBlock >= 0) && (nBlock < NUM_SECTORS)) {
+ ulSectorOff = (nBlock * SECTOR_SIZE);
+
+ } else {
+ ErrorCode = INVALID_BLOCK;
+ return ErrorCode;
+ }
+
+ /* A write enable instruction must previously have been executed */
+ SendSingleCommand(SPI_WREN);
+
+ /* The status register will be polled to check the write enable latch "WREN" */
+ ErrorCode = Wait_For_WEL();
+
+ if (POLL_TIMEOUT == ErrorCode) {
+ printf("SPI Erase block error\n");
+ return ErrorCode;
+ } else
+
+ /* Turn on the SPI to send single commands */
+ SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
+
+ /*
+ * Send the erase block command to the flash followed by the 24 address
+ * to point to the start of a sector
+ */
+ *pSPI_TDBR = SPI_SE;
+ sync();
+ Wait_For_SPIF();
+ /* Send the highest byte of the 24 bit address at first */
+ ShiftValue = (ulSectorOff >> 16);
+ *pSPI_TDBR = ShiftValue;
+ sync();
+ /* Wait until the instruction has been sent */
+ Wait_For_SPIF();
+ /* Send the middle byte of the 24 bit address at second */
+ ShiftValue = (ulSectorOff >> 8);
+ *pSPI_TDBR = ShiftValue;
+ sync();
+ /* Wait until the instruction has been sent */
+ Wait_For_SPIF();
+ /* Send the lowest byte of the 24 bit address finally */
+ *pSPI_TDBR = ulSectorOff;
+ sync();
+ /* Wait until the instruction has been sent */
+ Wait_For_SPIF();
+
+ /* Turns off the SPI */
+ SPI_OFF();
+
+ /* Poll the status register to check the Write in Progress bit */
+ /* Sector erase takes time */
+ ErrorCode = Wait_For_Status(WIP);
+
+ /* block erase should be complete */
+ return ErrorCode;
+}
+
+/*
+ * ERROR_CODE ReadData()
+ * Read a value from flash for verify purpose
+ * Inputs: unsigned long ulStart - holds the SPI start address
+ * int pnData - pointer to store value read from flash
+ * long lCount - number of elements to read
+ */
+ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData)
+{
+ unsigned long ShiftValue;
+ char *cnData;
+ int i;
+
+ /* Pointer cast to be able to increment byte wise */
+
+ cnData = (char *)pnData;
+ /* Start SPI interface */
+ SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
+
+#ifdef CONFIG_SPI_FLASH_FAST_READ
+ /* Send the read command to SPI device */
+ *pSPI_TDBR = SPI_FAST_READ;
+#else
+ /* Send the read command to SPI device */
+ *pSPI_TDBR = SPI_READ;
+#endif
+ sync();
+ /* Wait until the instruction has been sent */
+ Wait_For_SPIF();
+ /* Send the highest byte of the 24 bit address at first */
+ ShiftValue = (ulStart >> 16);
+ /* Send the byte to the SPI device */
+ *pSPI_TDBR = ShiftValue;
+ sync();
+ /* Wait until the instruction has been sent */
+ Wait_For_SPIF();
+ /* Send the middle byte of the 24 bit address at second */
+ ShiftValue = (ulStart >> 8);
+ /* Send the byte to the SPI device */
+ *pSPI_TDBR = ShiftValue;
+ sync();
+ /* Wait until the instruction has been sent */
+ Wait_For_SPIF();
+ /* Send the lowest byte of the 24 bit address finally */
+ *pSPI_TDBR = ulStart;
+ sync();
+ /* Wait until the instruction has been sent */
+ Wait_For_SPIF();
+
+#ifdef CONFIG_SPI_FLASH_FAST_READ
+ /* Send dummy for FAST_READ */
+ *pSPI_TDBR = 0;
+ sync();
+ /* Wait until the instruction has been sent */
+ Wait_For_SPIF();
+#endif
+
+ /* After the SPI device address has been placed on the MOSI pin the data can be */
+ /* received on the MISO pin. */
+ for (i = 0; i < lCount; i++) {
+ *pSPI_TDBR = 0;
+ sync();
+ while (!(*pSPI_STAT & RXS)) ;
+ *cnData++ = *pSPI_RDBR;
+
+ if ((i >= SECTOR_SIZE) && (i % SECTOR_SIZE == 0))
+ printf(".");
+ }
+
+ /* Turn off the SPI */
+ SPI_OFF();
+
+ return NO_ERR;
+}
+
+ERROR_CODE WriteFlash(unsigned long ulStartAddr, long lTransferCount,
+ int *iDataSource, long *lWriteCount)
+{
+
+ unsigned long ulWAddr;
+ long lWTransferCount = 0;
+ int i;
+ char iData;
+ char *temp = (char *)iDataSource;
+ ERROR_CODE ErrorCode = NO_ERR;
+
+ /* First, a Write Enable Command must be sent to the SPI. */
+ SendSingleCommand(SPI_WREN);
+
+ /*
+ * Second, the SPI Status Register will be tested whether the
+ * Write Enable Bit has been set
+ */
+ ErrorCode = Wait_For_WEL();
+ if (POLL_TIMEOUT == ErrorCode) {
+ printf("SPI Write Time Out\n");
+ return ErrorCode;
+ } else
+ /* Third, the 24 bit address will be shifted out
+ * the SPI MOSI bytewise.
+ * Turns the SPI on
+ */
+ SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
+ *pSPI_TDBR = SPI_PP;
+ sync();
+ /*wait until the instruction has been sent */
+ Wait_For_SPIF();
+ ulWAddr = (ulStartAddr >> 16);
+ *pSPI_TDBR = ulWAddr;
+ sync();
+ /*wait until the instruction has been sent */
+ Wait_For_SPIF();
+ ulWAddr = (ulStartAddr >> 8);
+ *pSPI_TDBR = ulWAddr;
+ sync();
+ /*wait until the instruction has been sent */
+ Wait_For_SPIF();
+ ulWAddr = ulStartAddr;
+ *pSPI_TDBR = ulWAddr;
+ sync();
+ /*wait until the instruction has been sent */
+ Wait_For_SPIF();
+ /*
+ * Fourth, maximum number of 256 bytes will be taken from the Buffer
+ * and sent to the SPI device.
+ */
+ for (i = 0; (i < lTransferCount) && (i < 256); i++, lWTransferCount++) {
+ iData = *temp;
+ *pSPI_TDBR = iData;
+ sync();
+ /*wait until the instruction has been sent */
+ Wait_For_SPIF();
+ temp++;
+ }
+
+ /* Turns the SPI off */
+ SPI_OFF();
+
+ /*
+ * Sixth, the SPI Write in Progress Bit must be toggled to ensure the
+ * programming is done before start of next transfer
+ */
+ ErrorCode = Wait_For_Status(WIP);
+
+ if (POLL_TIMEOUT == ErrorCode) {
+ printf("SPI Program Time out!\n");
+ return ErrorCode;
+ } else
+
+ *lWriteCount = lWTransferCount;
+
+ return ErrorCode;
+}
+
+ERROR_CODE WriteData(unsigned long ulStart, long lCount, int *pnData)
+{
+
+ unsigned long ulWStart = ulStart;
+ long lWCount = lCount, lWriteCount;
+ long *pnWriteCount = &lWriteCount;
+
+ ERROR_CODE ErrorCode = NO_ERR;
+
+ while (lWCount != 0) {
+ ErrorCode = WriteFlash(ulWStart, lWCount, pnData, pnWriteCount);
+
+ /*
+ * After each function call of WriteFlash the counter
+ * must be adjusted
+ */
+ lWCount -= *pnWriteCount;
+
+ /* Also, both address pointers must be recalculated. */
+ ulWStart += *pnWriteCount;
+ pnData += *pnWriteCount / 4;
+ }
+
+ /* return the appropriate error code */
+ return ErrorCode;
+}
+
+#endif /* CONFIG_SPI */
--- /dev/null
+/*
+ * U-boot - u-boot.lds.S
+ *
+ * Copyright (c) 2005-2007 Analog Device Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+OUTPUT_ARCH(bfin)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+MEMORY
+ {
+ ram : ORIGIN = (CFG_MONITOR_BASE), LENGTH = (256 * 1024)
+ l1_code : ORIGIN = 0xFFA00000, LENGTH = 0xC000
+ l1_data : ORIGIN = 0xFF900000, LENGTH = 0x4000
+ }
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS; /*0x1000;*/
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ . = CFG_MONITOR_BASE;
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector before the environment sector. If it throws */
+ /* an error during compilation remove an object here to get */
+ /* it linked after the configuration sector. */
+
+ cpu/bf537/start.o (.text)
+ cpu/bf537/start1.o (.text)
+ cpu/bf537/traps.o (.text)
+ cpu/bf537/interrupt.o (.text)
+ cpu/bf537/serial.o (.text)
+ common/dlmalloc.o (.text)
+/* lib_blackfin/bf533_string.o (.text) */
+/* lib_generic/vsprintf.o (.text) */
+ lib_generic/crc32.o (.text)
+/* lib_generic/zlib.o (.text) */
+/* board/bf537-stamp/bf537-stamp.o (.text) */
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/environment.o (.text)
+
+ *(EXCLUDE_FILE (board/bf537-stamp/post-memory.o) .text)
+ *(.fixup)
+ *(.got1)
+ } > ram
+ _etext = .;
+ PROVIDE (etext = .);
+ .text_l1 :
+ {
+ . = ALIGN(4) ;
+ _text_l1 = .;
+ PROVIDE (text_l1 = .);
+ board/bf537-stamp/post-memory.o (.text)
+ . = ALIGN(4) ;
+ _etext_l1 = .;
+ PROVIDE (etext_l1 = .);
+ } > l1_code AT > ram
+
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(EXCLUDE_FILE (board/bf537-stamp/post-memory.o) .rodata)
+ *(EXCLUDE_FILE (board/bf537-stamp/post-memory.o) .rodata1)
+ *(EXCLUDE_FILE (board/bf537-stamp/post-memory.o) .rodata.str1.4)
+ *(.eh_frame)
+ . = ALIGN(4);
+ } > ram
+
+ . = ALIGN(4);
+ _erodata = .;
+ PROVIDE (erodata = .);
+ .rodata_l1 :
+ {
+ . = ALIGN(4) ;
+ _rodata_l1 = .;
+ PROVIDE (rodata_l1 = .);
+ board/bf537-stamp/post-memory.o (.rodata)
+ board/bf537-stamp/post-memory.o (.rodata1)
+ board/bf537-stamp/post-memory.o (.rodata.str1.4)
+ . = ALIGN(4) ;
+ _erodata_l1 = .;
+ PROVIDE(erodata_l1 = .);
+ } > l1_data AT > ram
+
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ } > ram
+ _edata = .;
+ PROVIDE (edata = .);
+
+ ___u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) } > ram
+ ___u_boot_cmd_end = .;
+
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ .bss :
+ {
+ __bss_start = .;
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ } > ram
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+# U-boot - Makefile
+#
+# Copyright (c) 2005 blackfin.uclinux.org
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(CPU).a
+
+START = start.o start1.o interrupt.o cache.o flush.o init_sdram.o
+COBJS = cpu.o traps.o ints.o serial.o interrupts.o video.o i2c.o
+
+EXTRA = init_sdram_bootrom_initblock.o
+
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB) $(obj).depend $(EXTRA)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#define ASSEMBLY
+#include <asm/linkage.h>
+#include <config.h>
+#include <asm/blackfin.h>
+
+.text
+.align 2
+ENTRY(_blackfin_icache_flush_range)
+ R2 = -32;
+ R2 = R0 & R2;
+ P0 = R2;
+ P1 = R1;
+ CSYNC;
+ 1:
+ IFLUSH[P0++];
+ CC = P0 < P1(iu);
+ IF CC JUMP 1b(bp);
+ IFLUSH[P0];
+ SSYNC;
+ RTS;
+
+ENTRY(_blackfin_dcache_flush_range)
+ R2 = -32;
+ R2 = R0 & R2;
+ P0 = R2;
+ P1 = R1;
+ CSYNC;
+1:
+ FLUSH[P0++];
+ CC = P0 < P1(iu);
+ IF CC JUMP 1b(bp);
+ FLUSH[P0];
+ SSYNC;
+ RTS;
+
+ENTRY(_icache_invalidate)
+ENTRY(_invalidate_entire_icache)
+ [--SP] = (R7:5);
+
+ P0.L = (IMEM_CONTROL & 0xFFFF);
+ P0.H = (IMEM_CONTROL >> 16);
+ R7 =[P0];
+
+ /*
+ * Clear the IMC bit , All valid bits in the instruction
+ * cache are set to the invalid state
+ */
+ BITCLR(R7, IMC_P);
+ CLI R6;
+ /* SSYNC required before invalidating cache. */
+ SSYNC;
+ .align 8;
+ [P0] = R7;
+ SSYNC;
+ STI R6;
+
+ /* Configures the instruction cache agian */
+ R6 = (IMC | ENICPLB);
+ R7 = R7 | R6;
+
+ CLI R6;
+ SSYNC;
+ .align 8;
+ [P0] = R7;
+ SSYNC;
+ STI R6;
+
+ (R7:5) =[SP++];
+ RTS;
+
+/*
+ * Invalidate the Entire Data cache by
+ * clearing DMC[1:0] bits
+ */
+ENTRY(_invalidate_entire_dcache)
+ENTRY(_dcache_invalidate)
+ [--SP] = (R7:6);
+
+ P0.L = (DMEM_CONTROL & 0xFFFF);
+ P0.H = (DMEM_CONTROL >> 16);
+ R7 =[P0];
+
+ /*
+ * Clear the DMC[1:0] bits, All valid bits in the data
+ * cache are set to the invalid state
+ */
+ BITCLR(R7, DMC0_P);
+ BITCLR(R7, DMC1_P);
+ CLI R6;
+ SSYNC;
+ .align 8;
+ [P0] = R7;
+ SSYNC;
+ STI R6;
+ /* Configures the data cache again */
+
+ R6 = (ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
+ R7 = R7 | R6;
+
+ CLI R6;
+ SSYNC;
+ .align 8;
+ [P0] = R7;
+ SSYNC;
+ STI R6;
+
+ (R7:6) =[SP++];
+ RTS;
+
+ENTRY(_blackfin_dcache_invalidate_range)
+ R2 = -32;
+ R2 = R0 & R2;
+ P0 = R2;
+ P1 = R1;
+ CSYNC;
+1:
+ FLUSHINV[P0++];
+ CC = P0 < P1(iu);
+ IF CC JUMP 1b(bp);
+
+ /*
+ * If the data crosses a cache line, then we'll be pointing to
+ * the last cache line, but won't have flushed/invalidated it yet, so do
+ * one more.
+ */
+ FLUSHINV[P0];
+ SSYNC;
+ RTS;
--- /dev/null
+# U-boot - config.mk
+#
+# Copyright (c) 2005 blackfin.uclinux.org
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_RELFLAGS += -mcpu=bf537 -ffixed-P5
--- /dev/null
+/*
+ * U-boot - cpu.c CPU specific functions
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/blackfin.h>
+#include <command.h>
+#include <asm/entry.h>
+#include <asm/cplb.h>
+#include <asm/io.h>
+
+#define CACHE_ON 1
+#define CACHE_OFF 0
+
+extern unsigned int icplb_table[page_descriptor_table_size][2];
+extern unsigned int dcplb_table[page_descriptor_table_size][2];
+
+int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ __asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_ISRAM)
+ );
+
+ return 0;
+}
+
+/* These functions are just used to satisfy the linker */
+int cpu_init(void)
+{
+ return 0;
+}
+
+int cleanup_before_linux(void)
+{
+ return 0;
+}
+
+void icache_enable(void)
+{
+ unsigned int *I0, *I1;
+ int i, j = 0;
+
+ if ((*pCHIPID >> 28) < 2)
+ return;
+
+ /* Before enable icache, disable it first */
+ icache_disable();
+ I0 = (unsigned int *)ICPLB_ADDR0;
+ I1 = (unsigned int *)ICPLB_DATA0;
+
+ /* make sure the locked ones go in first */
+ for (i = 0; i < page_descriptor_table_size; i++) {
+ if (CPLB_LOCK & icplb_table[i][1]) {
+ debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
+ icplb_table[i][0], icplb_table[i][1]);
+ *I0++ = icplb_table[i][0];
+ *I1++ = icplb_table[i][1];
+ j++;
+ }
+ }
+
+ for (i = 0; i < page_descriptor_table_size; i++) {
+ if (!(CPLB_LOCK & icplb_table[i][1])) {
+ debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
+ icplb_table[i][0], icplb_table[i][1]);
+ *I0++ = icplb_table[i][0];
+ *I1++ = icplb_table[i][1];
+ j++;
+ if (j == 16) {
+ break;
+ }
+ }
+ }
+
+ /* Fill the rest with invalid entry */
+ if (j <= 15) {
+ for (; j < 16; j++) {
+ debug("filling %i with 0", j);
+ *I1++ = 0x0;
+ }
+
+ }
+
+ cli();
+ sync();
+ asm(" .align 8; ");
+ *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
+ sync();
+ sti();
+}
+
+void icache_disable(void)
+{
+ if ((*pCHIPID >> 28) < 2)
+ return;
+ cli();
+ sync();
+ asm(" .align 8; ");
+ *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
+ sync();
+ sti();
+}
+
+int icache_status(void)
+{
+ unsigned int value;
+ value = *(unsigned int *)IMEM_CONTROL;
+
+ if (value & (IMC | ENICPLB))
+ return CACHE_ON;
+ else
+ return CACHE_OFF;
+}
+
+void dcache_enable(void)
+{
+ unsigned int *I0, *I1;
+ unsigned int temp;
+ int i, j = 0;
+
+ /* Before enable dcache, disable it first */
+ dcache_disable();
+ I0 = (unsigned int *)DCPLB_ADDR0;
+ I1 = (unsigned int *)DCPLB_DATA0;
+
+ /* make sure the locked ones go in first */
+ for (i = 0; i < page_descriptor_table_size; i++) {
+ if (CPLB_LOCK & dcplb_table[i][1]) {
+ debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
+ dcplb_table[i][0], dcplb_table[i][1]);
+ *I0++ = dcplb_table[i][0];
+ *I1++ = dcplb_table[i][1];
+ j++;
+ } else {
+ debug("skip %02i %02i 0x%08x 0x%08x\n", i, j,
+ dcplb_table[i][0], dcplb_table[i][1]);
+ }
+ }
+
+ for (i = 0; i < page_descriptor_table_size; i++) {
+ if (!(CPLB_LOCK & dcplb_table[i][1])) {
+ debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
+ dcplb_table[i][0], dcplb_table[i][1]);
+ *I0++ = dcplb_table[i][0];
+ *I1++ = dcplb_table[i][1];
+ j++;
+ if (j == 16) {
+ break;
+ }
+ }
+ }
+
+ /* Fill the rest with invalid entry */
+ if (j <= 15) {
+ for (; j < 16; j++) {
+ debug("filling %i with 0", j);
+ *I1++ = 0x0;
+ }
+ }
+
+ cli();
+ temp = *(unsigned int *)DMEM_CONTROL;
+ sync();
+ asm(" .align 8; ");
+ *(unsigned int *)DMEM_CONTROL =
+ ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp;
+ sync();
+ sti();
+}
+
+void dcache_disable(void)
+{
+ unsigned int *I0, *I1;
+ int i;
+
+ cli();
+ sync();
+ asm(" .align 8; ");
+ *(unsigned int *)DMEM_CONTROL &=
+ ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
+ sync();
+ sti();
+
+ /* after disable dcache,
+ * clear it so we don't confuse the next application
+ */
+ I0 = (unsigned int *)DCPLB_ADDR0;
+ I1 = (unsigned int *)DCPLB_DATA0;
+
+ for (i = 0; i < 16; i++) {
+ *I0++ = 0x0;
+ *I1++ = 0x0;
+ }
+}
+
+int dcache_status(void)
+{
+ unsigned int value;
+ value = *(unsigned int *)DMEM_CONTROL;
+
+ if (value & (ENDCPLB))
+ return CACHE_ON;
+ else
+ return CACHE_OFF;
+}
--- /dev/null
+/*
+ * U-boot - cpu.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _CPU_H_
+#define _CPU_H_
+
+#include <command.h>
+
+#define INTERNAL_IRQS (32)
+#define NUM_IRQ_NODES 16
+#define DEF_INTERRUPT_FLAGS 1
+#define MAX_TIM_LOAD 0xFFFFFFFF
+
+void blackfin_irq_panic(int reason, struct pt_regs *reg);
+extern void dump(struct pt_regs *regs);
+void display_excp(void);
+asmlinkage void evt_nmi(void);
+asmlinkage void evt_exception(void);
+asmlinkage void trap(void);
+asmlinkage void evt_ivhw(void);
+asmlinkage void evt_rst(void);
+asmlinkage void evt_timer(void);
+asmlinkage void evt_evt7(void);
+asmlinkage void evt_evt8(void);
+asmlinkage void evt_evt9(void);
+asmlinkage void evt_evt10(void);
+asmlinkage void evt_evt11(void);
+asmlinkage void evt_evt12(void);
+asmlinkage void evt_evt13(void);
+asmlinkage void evt_soft_int1(void);
+asmlinkage void evt_system_call(void);
+void blackfin_irq_panic(int reason, struct pt_regs *regs);
+void blackfin_free_irq(unsigned int irq, void *dev_id);
+void call_isr(int irq, struct pt_regs *fp);
+void blackfin_do_irq(int vec, struct pt_regs *fp);
+void blackfin_init_IRQ(void);
+void blackfin_enable_irq(unsigned int irq);
+void blackfin_disable_irq(unsigned int irq);
+extern int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]);
+int blackfin_request_irq(unsigned int irq,
+ void (*handler) (int, void *, struct pt_regs *),
+ unsigned long flags, const char *devname,
+ void *dev_id);
+void timer_init(void);
+#endif
--- /dev/null
+/* Copyright (C) 2003 Analog Devices, Inc. All Rights Reserved.
+ * Copyright (C) 2004 LG SOft India. All Rights Reserved.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.
+ */
+#define ASSEMBLY
+
+#include <asm/linkage.h>
+#include <asm/cplb.h>
+#include <config.h>
+#include <asm/blackfin.h>
+
+.text
+
+/* This is an external function being called by the user
+ * application through __flush_cache_all. Currently this function
+ * serves the purpose of flushing all the pending writes in
+ * in the instruction cache.
+ */
+
+ENTRY(_flush_instruction_cache)
+ [--SP] = ( R7:6, P5:4 );
+ LINK 12;
+ SP += -12;
+ P5.H = (ICPLB_ADDR0 >> 16);
+ P5.L = (ICPLB_ADDR0 & 0xFFFF);
+ P4.H = (ICPLB_DATA0 >> 16);
+ P4.L = (ICPLB_DATA0 & 0xFFFF);
+ R7 = CPLB_VALID | CPLB_L1_CHBL;
+ R6 = 16;
+inext: R0 = [P5++];
+ R1 = [P4++];
+ [--SP] = RETS;
+ CALL _icplb_flush; /* R0 = page, R1 = data*/
+ RETS = [SP++];
+iskip: R6 += -1;
+ CC = R6;
+ IF CC JUMP inext;
+ SSYNC;
+ SP += 12;
+ UNLINK;
+ ( R7:6, P5:4 ) = [SP++];
+ RTS;
+
+/* This is an internal function to flush all pending
+ * writes in the cache associated with a particular ICPLB.
+ *
+ * R0 - page's start address
+ * R1 - CPLB's data field.
+ */
+
+.align 2
+ENTRY(_icplb_flush)
+ [--SP] = ( R7:0, P5:0 );
+ [--SP] = LC0;
+ [--SP] = LT0;
+ [--SP] = LB0;
+ [--SP] = LC1;
+ [--SP] = LT1;
+ [--SP] = LB1;
+
+ /* If it's a 1K or 4K page, then it's quickest to
+ * just systematically flush all the addresses in
+ * the page, regardless of whether they're in the
+ * cache, or dirty. If it's a 1M or 4M page, there
+ * are too many addresses, and we have to search the
+ * cache for lines corresponding to the page.
+ */
+
+ CC = BITTST(R1, 17); /* 1MB or 4MB */
+ IF !CC JUMP iflush_whole_page;
+
+ /* We're only interested in the page's size, so extract
+ * this from the CPLB (bits 17:16), and scale to give an
+ * offset into the page_size and page_prefix tables.
+ */
+
+ R1 <<= 14;
+ R1 >>= 30;
+ R1 <<= 2;
+
+ /* We can also determine the sub-bank used, because this is
+ * taken from bits 13:12 of the address.
+ */
+
+ R3 = ((12<<8)|2); /* Extraction pattern */
+ nop; /* Anamoly 05000209 */
+ R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits */
+
+ /* Save in extraction pattern for later deposit. */
+ R3.H = R4.L << 0;
+
+ /* So:
+ * R0 = Page start
+ * R1 = Page length (actually, offset into size/prefix tables)
+ * R3 = sub-bank deposit values
+ *
+ * The cache has 2 Ways, and 64 sets, so we iterate through
+ * the sets, accessing the tag for each Way, for our Bank and
+ * sub-bank, looking for dirty, valid tags that match our
+ * address prefix.
+ */
+
+ P5.L = (ITEST_COMMAND & 0xFFFF);
+ P5.H = (ITEST_COMMAND >> 16);
+ P4.L = (ITEST_DATA0 & 0xFFFF);
+ P4.H = (ITEST_DATA0 >> 16);
+
+ P0.L = page_prefix_table;
+ P0.H = page_prefix_table;
+ P1 = R1;
+ R5 = 0; /* Set counter*/
+ P0 = P1 + P0;
+ R4 = [P0]; /* This is the address prefix*/
+
+ /* We're reading (bit 1==0) the tag (bit 2==0), and we
+ * don't care about which double-word, since we're only
+ * fetching tags, so we only have to set Set, Bank,
+ * Sub-bank and Way.
+ */
+
+ P2 = 4;
+ LSETUP (ifs1, ife1) LC1 = P2;
+ifs1: P0 = 32; /* iterate over all sets*/
+ LSETUP (ifs0, ife0) LC0 = P0;
+ifs0: R6 = R5 << 5; /* Combine set*/
+ R6.H = R3.H << 0 ; /* and sub-bank*/
+ [P5] = R6; /* Issue Command*/
+ SSYNC; /* CSYNC will not work here :(*/
+ R7 = [P4]; /* and read Tag.*/
+ CC = BITTST(R7, 0); /* Check if valid*/
+ IF !CC JUMP ifskip; /* and skip if not.*/
+
+ /* Compare against the page address. First, plant bits 13:12
+ * into the tag, since those aren't part of the returned data.
+ */
+
+ R7 = DEPOSIT(R7, R3); /* set 13:12*/
+ R1 = R7 & R4; /* Mask off lower bits*/
+ CC = R1 == R0; /* Compare against page start.*/
+ IF !CC JUMP ifskip; /* Skip it if it doesn't match.*/
+
+ /* Tag address matches against page, so this is an entry
+ * we must flush.
+ */
+
+ R7 >>= 10; /* Mask off the non-address bits*/
+ R7 <<= 10;
+ P3 = R7;
+ IFLUSH [P3]; /* And flush the entry*/
+ifskip:
+ife0: R5 += 1; /* Advance to next Set*/
+ife1: NOP;
+
+ifinished:
+ SSYNC; /* Ensure the data gets out to mem.*/
+
+ /*Finished. Restore context.*/
+ LB1 = [SP++];
+ LT1 = [SP++];
+ LC1 = [SP++];
+ LB0 = [SP++];
+ LT0 = [SP++];
+ LC0 = [SP++];
+ ( R7:0, P5:0 ) = [SP++];
+ RTS;
+
+iflush_whole_page:
+ /* It's a 1K or 4K page, so quicker to just flush the
+ * entire page.
+ */
+
+ P1 = 32; /* For 1K pages*/
+ P2 = P1 << 2; /* For 4K pages*/
+ P0 = R0; /* Start of page*/
+ CC = BITTST(R1, 16); /* Whether 1K or 4K*/
+ IF CC P1 = P2;
+ P1 += -1; /* Unroll one iteration*/
+ SSYNC;
+ IFLUSH [P0++]; /* because CSYNC can't end loops.*/
+ LSETUP (isall, ieall) LC0 = P1;
+isall:IFLUSH [P0++];
+ieall: NOP;
+ SSYNC;
+ JUMP ifinished;
+
+/* This is an external function being called by the user
+ * application through __flush_cache_all. Currently this function
+ * serves the purpose of flushing all the pending writes in
+ * in the data cache.
+ */
+
+ENTRY(_flush_data_cache)
+ [--SP] = ( R7:6, P5:4 );
+ LINK 12;
+ SP += -12;
+ P5.H = (DCPLB_ADDR0 >> 16);
+ P5.L = (DCPLB_ADDR0 & 0xFFFF);
+ P4.H = (DCPLB_DATA0 >> 16);
+ P4.L = (DCPLB_DATA0 & 0xFFFF);
+ R7 = CPLB_VALID | CPLB_L1_CHBL | CPLB_DIRTY (Z);
+ R6 = 16;
+next: R0 = [P5++];
+ R1 = [P4++];
+ CC = BITTST(R1, 14); /* Is it write-through?*/
+ IF CC JUMP skip; /* If so, ignore it.*/
+ R2 = R1 & R7; /* Is it a dirty, cached page?*/
+ CC = R2;
+ IF !CC JUMP skip; /* If not, ignore it.*/
+ [--SP] = RETS;
+ CALL _dcplb_flush; /* R0 = page, R1 = data*/
+ RETS = [SP++];
+skip: R6 += -1;
+ CC = R6;
+ IF CC JUMP next;
+ SSYNC;
+ SP += 12;
+ UNLINK;
+ ( R7:6, P5:4 ) = [SP++];
+ RTS;
+
+/* This is an internal function to flush all pending
+ * writes in the cache associated with a particular DCPLB.
+ *
+ * R0 - page's start address
+ * R1 - CPLB's data field.
+ */
+
+.align 2
+ENTRY(_dcplb_flush)
+ [--SP] = ( R7:0, P5:0 );
+ [--SP] = LC0;
+ [--SP] = LT0;
+ [--SP] = LB0;
+ [--SP] = LC1;
+ [--SP] = LT1;
+ [--SP] = LB1;
+
+ /* If it's a 1K or 4K page, then it's quickest to
+ * just systematically flush all the addresses in
+ * the page, regardless of whether they're in the
+ * cache, or dirty. If it's a 1M or 4M page, there
+ * are too many addresses, and we have to search the
+ * cache for lines corresponding to the page.
+ */
+
+ CC = BITTST(R1, 17); /* 1MB or 4MB */
+ IF !CC JUMP dflush_whole_page;
+
+ /* We're only interested in the page's size, so extract
+ * this from the CPLB (bits 17:16), and scale to give an
+ * offset into the page_size and page_prefix tables.
+ */
+
+ R1 <<= 14;
+ R1 >>= 30;
+ R1 <<= 2;
+
+ /* The page could be mapped into Bank A or Bank B, depending
+ * on (a) whether both banks are configured as cache, and
+ * (b) on whether address bit A[x] is set. x is determined
+ * by DCBS in DMEM_CONTROL
+ */
+
+ R2 = 0; /* Default to Bank A (Bank B would be 1)*/
+
+ P0.L = (DMEM_CONTROL & 0xFFFF);
+ P0.H = (DMEM_CONTROL >> 16);
+
+ R3 = [P0]; /* If Bank B is not enabled as cache*/
+ CC = BITTST(R3, 2); /* then Bank A is our only option.*/
+ IF CC JUMP bank_chosen;
+
+ R4 = 1<<14; /* If DCBS==0, use A[14].*/
+ R5 = R4 << 7; /* If DCBS==1, use A[23];*/
+ CC = BITTST(R3, 4);
+ IF CC R4 = R5; /* R4 now has either bit 14 or bit 23 set.*/
+ R5 = R0 & R4; /* Use it to test the Page address*/
+ CC = R5; /* and if that bit is set, we use Bank B,*/
+ R2 = CC; /* else we use Bank A.*/
+ R2 <<= 23; /* The Bank selection's at posn 23.*/
+
+bank_chosen:
+
+ /* We can also determine the sub-bank used, because this is
+ * taken from bits 13:12 of the address.
+ */
+
+ R3 = ((12<<8)|2); /* Extraction pattern */
+ nop; /*Anamoly 05000209*/
+ R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits*/
+ /* Save in extraction pattern for later deposit.*/
+ R3.H = R4.L << 0;
+
+ /* So:
+ * R0 = Page start
+ * R1 = Page length (actually, offset into size/prefix tables)
+ * R2 = Bank select mask
+ * R3 = sub-bank deposit values
+ *
+ * The cache has 2 Ways, and 64 sets, so we iterate through
+ * the sets, accessing the tag for each Way, for our Bank and
+ * sub-bank, looking for dirty, valid tags that match our
+ * address prefix.
+ */
+
+ P5.L = (DTEST_COMMAND & 0xFFFF);
+ P5.H = (DTEST_COMMAND >> 16);
+ P4.L = (DTEST_DATA0 & 0xFFFF);
+ P4.H = (DTEST_DATA0 >> 16);
+
+ P0.L = page_prefix_table;
+ P0.H = page_prefix_table;
+ P1 = R1;
+ R5 = 0; /* Set counter*/
+ P0 = P1 + P0;
+ R4 = [P0]; /* This is the address prefix*/
+
+
+ /* We're reading (bit 1==0) the tag (bit 2==0), and we
+ * don't care about which double-word, since we're only
+ * fetching tags, so we only have to set Set, Bank,
+ * Sub-bank and Way.
+ */
+
+ P2 = 2;
+ LSETUP (fs1, fe1) LC1 = P2;
+fs1: P0 = 64; /* iterate over all sets*/
+ LSETUP (fs0, fe0) LC0 = P0;
+fs0: R6 = R5 << 5; /* Combine set*/
+ R6.H = R3.H << 0 ; /* and sub-bank*/
+ R6 = R6 | R2; /* and Bank. Leave Way==0 at first.*/
+ BITSET(R6,14);
+ [P5] = R6; /* Issue Command*/
+ SSYNC;
+ R7 = [P4]; /* and read Tag.*/
+ CC = BITTST(R7, 0); /* Check if valid*/
+ IF !CC JUMP fskip; /* and skip if not.*/
+ CC = BITTST(R7, 1); /* Check if dirty*/
+ IF !CC JUMP fskip; /* and skip if not.*/
+
+ /* Compare against the page address. First, plant bits 13:12
+ * into the tag, since those aren't part of the returned data.
+ */
+
+ R7 = DEPOSIT(R7, R3); /* set 13:12*/
+ R1 = R7 & R4; /* Mask off lower bits*/
+ CC = R1 == R0; /* Compare against page start.*/
+ IF !CC JUMP fskip; /* Skip it if it doesn't match.*/
+
+ /* Tag address matches against page, so this is an entry
+ * we must flush.
+ */
+
+ R7 >>= 10; /* Mask off the non-address bits*/
+ R7 <<= 10;
+ P3 = R7;
+ SSYNC;
+ FLUSHINV [P3]; /* And flush the entry*/
+fskip:
+fe0: R5 += 1; /* Advance to next Set*/
+fe1: BITSET(R2, 26); /* Go to next Way.*/
+
+dfinished:
+ SSYNC; /* Ensure the data gets out to mem.*/
+
+ /*Finished. Restore context.*/
+ LB1 = [SP++];
+ LT1 = [SP++];
+ LC1 = [SP++];
+ LB0 = [SP++];
+ LT0 = [SP++];
+ LC0 = [SP++];
+ ( R7:0, P5:0 ) = [SP++];
+ RTS;
+
+dflush_whole_page:
+
+ /* It's a 1K or 4K page, so quicker to just flush the
+ * entire page.
+ */
+
+ P1 = 32; /* For 1K pages*/
+ P2 = P1 << 2; /* For 4K pages*/
+ P0 = R0; /* Start of page*/
+ CC = BITTST(R1, 16); /* Whether 1K or 4K*/
+ IF CC P1 = P2;
+ P1 += -1; /* Unroll one iteration*/
+ SSYNC;
+ FLUSHINV [P0++]; /* because CSYNC can't end loops.*/
+ LSETUP (eall, eall) LC0 = P1;
+eall: FLUSHINV [P0++];
+ SSYNC;
+ JUMP dfinished;
+
+.align 4;
+page_prefix_table:
+.byte4 0xFFFFFC00; /* 1K */
+.byte4 0xFFFFF000; /* 4K */
+.byte4 0xFFF00000; /* 1M */
+.byte4 0xFFC00000; /* 4M */
+.page_prefix_table.end:
--- /dev/null
+/****************************************************************
+ * $ID: i2c.c 24 Oct 2006 12:00:00 +0800 $ *
+ * *
+ * Description: *
+ * *
+ * Maintainer: sonicz <sonic.zhang@analog.com> *
+ * *
+ * CopyRight (c) 2006 Analog Device *
+ * All rights reserved. *
+ * *
+ * This file is free software; *
+ * you are free to modify and/or redistribute it *
+ * under the terms of the GNU General Public Licence (GPL).*
+ * *
+ ****************************************************************/
+
+#include <common.h>
+
+#ifdef CONFIG_HARD_I2C
+
+#include <asm/blackfin.h>
+#include <i2c.h>
+#include <asm/io.h>
+
+#define bfin_read16(addr) ({ unsigned __v; \
+ __asm__ __volatile__ (\
+ "%0 = w[%1] (z);\n\t"\
+ : "=d"(__v) : "a"(addr)); (unsigned short)__v; })
+
+#define bfin_write16(addr,val) ({\
+ __asm__ __volatile__ (\
+ "w[%0] = %1;\n\t"\
+ : : "a"(addr) , "d"(val) : "memory");})
+
+/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
+#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV)
+#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV,val)
+#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL)
+#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL,val)
+#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL)
+#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL,val)
+#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT)
+#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT,val)
+#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR)
+#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR,val)
+#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL)
+#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL,val)
+#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT)
+#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT,val)
+#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR)
+#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR,val)
+#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT)
+#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT,val)
+#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK)
+#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK,val)
+#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL)
+#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL,val)
+#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT)
+#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT,val)
+#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8)
+#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8,val)
+#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16)
+#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16,val)
+#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8)
+#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8,val)
+#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16)
+#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16,val)
+
+#ifdef DEBUG_I2C
+#define PRINTD(fmt,args...) do { \
+ DECLARE_GLOBAL_DATA_PTR; \
+ if (gd->have_console) \
+ printf(fmt ,##args); \
+ } while (0)
+#else
+#define PRINTD(fmt,args...)
+#endif
+
+#ifndef CONFIG_TWICLK_KHZ
+#define CONFIG_TWICLK_KHZ 50
+#endif
+
+/* All transfers are described by this data structure */
+struct i2c_msg {
+ u16 addr; /* slave address */
+ u16 flags;
+#define I2C_M_STOP 0x2
+#define I2C_M_RD 0x1
+ u16 len; /* msg length */
+ u8 *buf; /* pointer to msg data */
+};
+
+/**
+ * i2c_reset: - reset the host controller
+ *
+ */
+
+static void i2c_reset(void)
+{
+ /* Disable TWI */
+ bfin_write_TWI_CONTROL(0);
+ sync();
+
+ /* Set TWI internal clock as 10MHz */
+ bfin_write_TWI_CONTROL(((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F);
+
+ /* Set Twi interface clock as specified */
+ if (CONFIG_TWICLK_KHZ > 400)
+ bfin_write_TWI_CLKDIV(((5 * 1024 / 400) << 8) | ((5 * 1024 /
+ 400) & 0xFF));
+ else
+ bfin_write_TWI_CLKDIV(((5 * 1024 /
+ CONFIG_TWICLK_KHZ) << 8) | ((5 * 1024 /
+ CONFIG_TWICLK_KHZ)
+ & 0xFF));
+
+ /* Enable TWI */
+ bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() | TWI_ENA);
+ sync();
+}
+
+int wait_for_completion(struct i2c_msg *msg, int timeout_count)
+{
+ unsigned short twi_int_stat;
+ unsigned short mast_stat;
+ int i;
+
+ for (i = 0; i < timeout_count; i++) {
+ twi_int_stat = bfin_read_TWI_INT_STAT();
+ mast_stat = bfin_read_TWI_MASTER_STAT();
+
+ if (XMTSERV & twi_int_stat) {
+ /* Transmit next data */
+ if (msg->len > 0) {
+ bfin_write_TWI_XMT_DATA8(*(msg->buf++));
+ msg->len--;
+ } else if (msg->flags & I2C_M_STOP)
+ bfin_write_TWI_MASTER_CTL
+ (bfin_read_TWI_MASTER_CTL() | STOP);
+ sync();
+ /* Clear status */
+ bfin_write_TWI_INT_STAT(XMTSERV);
+ sync();
+ i = 0;
+ }
+ if (RCVSERV & twi_int_stat) {
+ if (msg->len > 0) {
+ /* Receive next data */
+ *(msg->buf++) = bfin_read_TWI_RCV_DATA8();
+ msg->len--;
+ } else if (msg->flags & I2C_M_STOP) {
+ bfin_write_TWI_MASTER_CTL
+ (bfin_read_TWI_MASTER_CTL() | STOP);
+ sync();
+ }
+ /* Clear interrupt source */
+ bfin_write_TWI_INT_STAT(RCVSERV);
+ sync();
+ i = 0;
+ }
+ if (MERR & twi_int_stat) {
+ bfin_write_TWI_INT_STAT(MERR);
+ bfin_write_TWI_INT_MASK(0);
+ bfin_write_TWI_MASTER_STAT(0x3e);
+ bfin_write_TWI_MASTER_CTL(0);
+ sync();
+ /*
+ * if both err and complete int stats are set,
+ * return proper results.
+ */
+ if (MCOMP & twi_int_stat) {
+ bfin_write_TWI_INT_STAT(MCOMP);
+ bfin_write_TWI_INT_MASK(0);
+ bfin_write_TWI_MASTER_CTL(0);
+ sync();
+ /*
+ * If it is a quick transfer,
+ * only address bug no data, not an err.
+ */
+ if (msg->len == 0 && mast_stat & BUFRDERR)
+ return 0;
+ /*
+ * If address not acknowledged return -3,
+ * else return 0.
+ */
+ else if (!(mast_stat & ANAK))
+ return 0;
+ else
+ return -3;
+ }
+ return -1;
+ }
+ if (MCOMP & twi_int_stat) {
+ bfin_write_TWI_INT_STAT(MCOMP);
+ sync();
+ bfin_write_TWI_INT_MASK(0);
+ bfin_write_TWI_MASTER_CTL(0);
+ sync();
+ return 0;
+ }
+ }
+ if (msg->flags & I2C_M_RD)
+ return -4;
+ else
+ return -2;
+}
+
+/**
+ * i2c_transfer: - Transfer one byte over the i2c bus
+ *
+ * This function can tranfer a byte over the i2c bus in both directions.
+ * It is used by the public API functions.
+ *
+ * @return: 0: transfer successful
+ * -1: transfer fail
+ * -2: transmit timeout
+ * -3: ACK missing
+ * -4: receive timeout
+ * -5: controller not ready
+ */
+int i2c_transfer(struct i2c_msg *msg)
+{
+ int ret = 0;
+ int timeout_count = 10000;
+ int len = msg->len;
+
+ if (!(bfin_read_TWI_CONTROL() & TWI_ENA)) {
+ ret = -5;
+ goto transfer_error;
+ }
+
+ while (bfin_read_TWI_MASTER_STAT() & BUSBUSY) ;
+
+ /* Set Transmit device address */
+ bfin_write_TWI_MASTER_ADDR(msg->addr);
+
+ /*
+ * FIFO Initiation.
+ * Data in FIFO should be discarded before start a new operation.
+ */
+ bfin_write_TWI_FIFO_CTL(0x3);
+ sync();
+ bfin_write_TWI_FIFO_CTL(0);
+ sync();
+
+ if (!(msg->flags & I2C_M_RD)) {
+ /* Transmit first data */
+ if (msg->len > 0) {
+ PRINTD("1 in i2c_transfer: buf=%d, len=%d\n", *msg->buf,
+ len);
+ bfin_write_TWI_XMT_DATA8(*(msg->buf++));
+ msg->len--;
+ sync();
+ }
+ }
+
+ /* clear int stat */
+ bfin_write_TWI_INT_STAT(MERR | MCOMP | XMTSERV | RCVSERV);
+
+ /* Interrupt mask . Enable XMT, RCV interrupt */
+ bfin_write_TWI_INT_MASK(MCOMP | MERR |
+ ((msg->flags & I2C_M_RD) ? RCVSERV : XMTSERV));
+ sync();
+
+ if (len > 0 && len <= 255)
+ bfin_write_TWI_MASTER_CTL((len << 6));
+ else if (msg->len > 255) {
+ bfin_write_TWI_MASTER_CTL((0xff << 6));
+ msg->flags &= I2C_M_STOP;
+ } else
+ bfin_write_TWI_MASTER_CTL(0);
+
+ /* Master enable */
+ bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | MEN |
+ ((msg->flags & I2C_M_RD)
+ ? MDIR : 0) | ((CONFIG_TWICLK_KHZ >
+ 100) ? FAST : 0));
+ sync();
+
+ ret = wait_for_completion(msg, timeout_count);
+ PRINTD("3 in i2c_transfer: ret=%d\n", ret);
+
+transfer_error:
+ switch (ret) {
+ case 1:
+ PRINTD(("i2c_transfer: error: transfer fail\n"));
+ break;
+ case 2:
+ PRINTD(("i2c_transfer: error: transmit timeout\n"));
+ break;
+ case 3:
+ PRINTD(("i2c_transfer: error: ACK missing\n"));
+ break;
+ case 4:
+ PRINTD(("i2c_transfer: error: receive timeout\n"));
+ break;
+ case 5:
+ PRINTD(("i2c_transfer: error: controller not ready\n"));
+ i2c_reset();
+ break;
+ default:
+ break;
+ }
+ return ret;
+
+}
+
+/* ---------------------------------------------------------------------*/
+/* API Functions */
+/* ---------------------------------------------------------------------*/
+
+void i2c_init(int speed, int slaveaddr)
+{
+ i2c_reset();
+}
+
+/**
+ * i2c_probe: - Test if a chip answers for a given i2c address
+ *
+ * @chip: address of the chip which is searched for
+ * @return: 0 if a chip was found, -1 otherwhise
+ */
+
+int i2c_probe(uchar chip)
+{
+ struct i2c_msg msg;
+ u8 probebuf;
+
+ i2c_reset();
+
+ probebuf = 0;
+ msg.addr = chip;
+ msg.flags = 0;
+ msg.len = 1;
+ msg.buf = &probebuf;
+ if (i2c_transfer(&msg))
+ return -1;
+
+ msg.addr = chip;
+ msg.flags = I2C_M_RD;
+ msg.len = 1;
+ msg.buf = &probebuf;
+ if (i2c_transfer(&msg))
+ return -1;
+
+ return 0;
+}
+
+/**
+ * i2c_read: - Read multiple bytes from an i2c device
+ *
+ * chip: I2C chip address, range 0..127
+ * addr: Memory (register) address within the chip
+ * alen: Number of bytes to use for addr (typically 1, 2 for larger
+ * memories, 0 for register type devices with only one
+ * register)
+ * buffer: Where to read/write the data
+ * len: How many bytes to read/write
+ *
+ * Returns: 0 on success, not 0 on failure
+ */
+
+int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len)
+{
+ struct i2c_msg msg;
+ u8 addr_bytes[3]; /* lowest...highest byte of data address */
+
+ PRINTD("i2c_read: chip=0x%x, addr=0x%x, alen=0x%x, len=0x%x\n", chip,
+ addr, alen, len);
+
+ if (alen > 0) {
+ addr_bytes[0] = (u8) ((addr >> 0) & 0x000000FF);
+ addr_bytes[1] = (u8) ((addr >> 8) & 0x000000FF);
+ addr_bytes[2] = (u8) ((addr >> 16) & 0x000000FF);
+ msg.addr = chip;
+ msg.flags = 0;
+ msg.len = alen;
+ msg.buf = addr_bytes;
+ if (i2c_transfer(&msg))
+ return -1;
+ }
+
+ /* start read sequence */
+ PRINTD(("i2c_read: start read sequence\n"));
+ msg.addr = chip;
+ msg.flags = I2C_M_RD;
+ msg.len = len;
+ msg.buf = buffer;
+ if (i2c_transfer(&msg))
+ return -1;
+
+ return 0;
+}
+
+/**
+ * i2c_write: - Write multiple bytes to an i2c device
+ *
+ * chip: I2C chip address, range 0..127
+ * addr: Memory (register) address within the chip
+ * alen: Number of bytes to use for addr (typically 1, 2 for larger
+ * memories, 0 for register type devices with only one
+ * register)
+ * buffer: Where to read/write the data
+ * len: How many bytes to read/write
+ *
+ * Returns: 0 on success, not 0 on failure
+ */
+
+int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len)
+{
+ struct i2c_msg msg;
+ u8 addr_bytes[3]; /* lowest...highest byte of data address */
+
+ PRINTD
+ ("i2c_write: chip=0x%x, addr=0x%x, alen=0x%x, len=0x%x, buf0=0x%x\n",
+ chip, addr, alen, len, buffer[0]);
+
+ /* chip address write */
+ if (alen > 0) {
+ addr_bytes[0] = (u8) ((addr >> 0) & 0x000000FF);
+ addr_bytes[1] = (u8) ((addr >> 8) & 0x000000FF);
+ addr_bytes[2] = (u8) ((addr >> 16) & 0x000000FF);
+ msg.addr = chip;
+ msg.flags = 0;
+ msg.len = alen;
+ msg.buf = addr_bytes;
+ if (i2c_transfer(&msg))
+ return -1;
+ }
+
+ /* start read sequence */
+ PRINTD(("i2c_write: start write sequence\n"));
+ msg.addr = chip;
+ msg.flags = 0;
+ msg.len = len;
+ msg.buf = buffer;
+ if (i2c_transfer(&msg))
+ return -1;
+
+ return 0;
+
+}
+
+uchar i2c_reg_read(uchar chip, uchar reg)
+{
+ uchar buf;
+
+ PRINTD("i2c_reg_read: chip=0x%02x, reg=0x%02x\n", chip, reg);
+ i2c_read(chip, reg, 0, &buf, 1);
+ return (buf);
+}
+
+void i2c_reg_write(uchar chip, uchar reg, uchar val)
+{
+ PRINTD("i2c_reg_write: chip=0x%02x, reg=0x%02x, val=0x%02x\n", chip,
+ reg, val);
+ i2c_write(chip, reg, 0, &val, 1);
+}
+
+#endif /* CONFIG_HARD_I2C */
--- /dev/null
+#define ASSEMBLY
+
+#include <linux/config.h>
+#include <config.h>
+#include <asm/blackfin.h>
+#include <asm/mem_init.h>
+.global init_sdram;
+
+#if (BFIN_BOOT_MODE != BF537_UART_BOOT)
+#if (CONFIG_CCLK_DIV == 1)
+#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
+#endif
+#if (CONFIG_CCLK_DIV == 2)
+#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
+#endif
+#if (CONFIG_CCLK_DIV == 4)
+#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
+#endif
+#if (CONFIG_CCLK_DIV == 8)
+#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
+#endif
+#ifndef CONFIG_CCLK_ACT_DIV
+#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
+#endif
+#endif
+
+init_sdram:
+ [--SP] = ASTAT;
+ [--SP] = RETS;
+ [--SP] = (R7:0);
+ [--SP] = (P5:0);
+
+#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
+ p0.h = hi(SIC_IWR);
+ p0.l = lo(SIC_IWR);
+ r0.l = 0x1;
+ w[p0] = r0.l;
+ SSYNC;
+
+ p0.h = hi(SPI_BAUD);
+ p0.l = lo(SPI_BAUD);
+ r0.l = CONFIG_SPI_BAUD;
+ w[p0] = r0.l;
+ SSYNC;
+#endif
+
+#if (BFIN_BOOT_MODE != BF537_UART_BOOT)
+
+#ifdef CONFIG_BF537
+ /* Enable PHY CLK buffer output */
+ p0.h = hi(VR_CTL);
+ p0.l = lo(VR_CTL);
+ r0.l = w[p0];
+ bitset(r0, 14);
+ w[p0] = r0.l;
+ ssync;
+#endif
+ /*
+ * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
+ */
+ p0.h = hi(PLL_LOCKCNT);
+ p0.l = lo(PLL_LOCKCNT);
+ r0 = 0x300(Z);
+ w[p0] = r0.l;
+ ssync;
+
+ /*
+ * Put SDRAM in self-refresh, incase anything is running
+ */
+ P2.H = hi(EBIU_SDGCTL);
+ P2.L = lo(EBIU_SDGCTL);
+ R0 = [P2];
+ BITSET (R0, 24);
+ [P2] = R0;
+ SSYNC;
+
+ /*
+ * Set PLL_CTL with the value that we calculate in R0
+ * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
+ * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
+ * - [7] = output delay (add 200ps of delay to mem signals)
+ * - [6] = input delay (add 200ps of input delay to mem signals)
+ * - [5] = PDWN : 1=All Clocks off
+ * - [3] = STOPCK : 1=Core Clock off
+ * - [1] = PLL_OFF : 1=Disable Power to PLL
+ * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
+ * all other bits set to zero
+ */
+
+ r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
+ r0 = r0 << 9; /* Shift it over */
+ r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
+ r0 = r1 | r0;
+ r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
+ r1 = r1 << 8; /* Shift it over */
+ r0 = r1 | r0; /* add them all together */
+
+ p0.h = hi(PLL_CTL);
+ p0.l = lo(PLL_CTL); /* Load the address */
+ cli r2; /* Disable interrupts */
+ ssync;
+ w[p0] = r0.l; /* Set the value */
+ idle; /* Wait for the PLL to stablize */
+ sti r2; /* Enable interrupts */
+
+check_again:
+ p0.h = hi(PLL_STAT);
+ p0.l = lo(PLL_STAT);
+ R0 = W[P0](Z);
+ CC = BITTST(R0,5);
+ if ! CC jump check_again;
+
+ /* Configure SCLK & CCLK Dividers */
+ r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
+ p0.h = hi(PLL_DIV);
+ p0.l = lo(PLL_DIV);
+ w[p0] = r0.l;
+ ssync;
+#endif
+
+ /*
+ * Now, Initialize the SDRAM,
+ * start with the SDRAM Refresh Rate Control Register
+ */
+ p0.l = lo(EBIU_SDRRC);
+ p0.h = hi(EBIU_SDRRC);
+ r0 = mem_SDRRC;
+ w[p0] = r0.l;
+ ssync;
+
+ /*
+ * SDRAM Memory Bank Control Register - bank specific parameters
+ */
+ p0.l = (EBIU_SDBCTL & 0xFFFF);
+ p0.h = (EBIU_SDBCTL >> 16);
+ r0 = mem_SDBCTL;
+ w[p0] = r0.l;
+ ssync;
+
+ /*
+ * SDRAM Global Control Register - global programmable parameters
+ * Disable self-refresh
+ */
+ P2.H = hi(EBIU_SDGCTL);
+ P2.L = lo(EBIU_SDGCTL);
+ R0 = [P2];
+ BITCLR (R0, 24);
+
+ /*
+ * Check if SDRAM is already powered up, if it is, enable self-refresh
+ */
+ p0.h = hi(EBIU_SDSTAT);
+ p0.l = lo(EBIU_SDSTAT);
+ r2.l = w[p0];
+ cc = bittst(r2,3);
+ if !cc jump skip;
+ NOP;
+ BITSET (R0, 23);
+skip:
+ [P2] = R0;
+ SSYNC;
+
+ /* Write in the new value in the register */
+ R0.L = lo(mem_SDGCTL);
+ R0.H = hi(mem_SDGCTL);
+ [P2] = R0;
+ SSYNC;
+ nop;
+
+ (P5:0) = [SP++];
+ (R7:0) = [SP++];
+ RETS = [SP++];
+ ASTAT = [SP++];
+ RTS;
--- /dev/null
+#define ASSEMBLY
+
+#include <linux/config.h>
+#include <config.h>
+#include <asm/blackfin.h>
+#include <asm/mem_init.h>
+.global init_sdram;
+
+#if (BFIN_BOOT_MODE != BF537_UART_BOOT)
+#if (CONFIG_CCLK_DIV == 1)
+#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
+#endif
+#if (CONFIG_CCLK_DIV == 2)
+#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
+#endif
+#if (CONFIG_CCLK_DIV == 4)
+#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
+#endif
+#if (CONFIG_CCLK_DIV == 8)
+#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
+#endif
+#ifndef CONFIG_CCLK_ACT_DIV
+#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
+#endif
+#endif
+
+init_sdram:
+ [--SP] = ASTAT;
+ [--SP] = RETS;
+ [--SP] = (R7:0);
+ [--SP] = (P5:0);
+
+#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
+ p0.h = hi(SIC_IWR);
+ p0.l = lo(SIC_IWR);
+ r0.l = 0x1;
+ w[p0] = r0.l;
+ SSYNC;
+
+ p0.h = hi(SPI_BAUD);
+ p0.l = lo(SPI_BAUD);
+ r0.l = CONFIG_SPI_BAUD_INITBLOCK;
+ w[p0] = r0.l;
+ SSYNC;
+#endif
+
+#if (BFIN_BOOT_MODE != BF537_UART_BOOT)
+
+#ifdef CONFIG_BF537
+ /* Enable PHY CLK buffer output */
+ p0.h = hi(VR_CTL);
+ p0.l = lo(VR_CTL);
+ r0.l = w[p0];
+ bitset(r0, 14);
+ w[p0] = r0.l;
+ ssync;
+#endif
+ /*
+ * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
+ */
+ p0.h = hi(PLL_LOCKCNT);
+ p0.l = lo(PLL_LOCKCNT);
+ r0 = 0x300(Z);
+ w[p0] = r0.l;
+ ssync;
+
+ /*
+ * Put SDRAM in self-refresh, incase anything is running
+ */
+ P2.H = hi(EBIU_SDGCTL);
+ P2.L = lo(EBIU_SDGCTL);
+ R0 = [P2];
+ BITSET (R0, 24);
+ [P2] = R0;
+ SSYNC;
+
+ /*
+ * Set PLL_CTL with the value that we calculate in R0
+ * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
+ * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
+ * - [7] = output delay (add 200ps of delay to mem signals)
+ * - [6] = input delay (add 200ps of input delay to mem signals)
+ * - [5] = PDWN : 1=All Clocks off
+ * - [3] = STOPCK : 1=Core Clock off
+ * - [1] = PLL_OFF : 1=Disable Power to PLL
+ * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
+ * all other bits set to zero
+ */
+
+ r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
+ r0 = r0 << 9; /* Shift it over */
+ r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
+ r0 = r1 | r0;
+ r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
+ r1 = r1 << 8; /* Shift it over */
+ r0 = r1 | r0; /* add them all together */
+
+ p0.h = hi(PLL_CTL);
+ p0.l = lo(PLL_CTL); /* Load the address */
+ cli r2; /* Disable interrupts */
+ ssync;
+ w[p0] = r0.l; /* Set the value */
+ idle; /* Wait for the PLL to stablize */
+ sti r2; /* Enable interrupts */
+
+check_again:
+ p0.h = hi(PLL_STAT);
+ p0.l = lo(PLL_STAT);
+ R0 = W[P0](Z);
+ CC = BITTST(R0,5);
+ if ! CC jump check_again;
+
+ /* Configure SCLK & CCLK Dividers */
+ r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
+ p0.h = hi(PLL_DIV);
+ p0.l = lo(PLL_DIV);
+ w[p0] = r0.l;
+ ssync;
+#endif
+
+ /*
+ * We now are running at speed, time to set the Async mem bank wait states
+ * This will speed up execution, since we are normally running from FLASH.
+ */
+
+ p2.h = (EBIU_AMBCTL1 >> 16);
+ p2.l = (EBIU_AMBCTL1 & 0xFFFF);
+ r0.h = (AMBCTL1VAL >> 16);
+ r0.l = (AMBCTL1VAL & 0xFFFF);
+ [p2] = r0;
+ ssync;
+
+ p2.h = (EBIU_AMBCTL0 >> 16);
+ p2.l = (EBIU_AMBCTL0 & 0xFFFF);
+ r0.h = (AMBCTL0VAL >> 16);
+ r0.l = (AMBCTL0VAL & 0xFFFF);
+ [p2] = r0;
+ ssync;
+
+ p2.h = (EBIU_AMGCTL >> 16);
+ p2.l = (EBIU_AMGCTL & 0xffff);
+ r0 = AMGCTLVAL;
+ w[p2] = r0;
+ ssync;
+
+ /*
+ * Now, Initialize the SDRAM,
+ * start with the SDRAM Refresh Rate Control Register
+ */
+ p0.l = lo(EBIU_SDRRC);
+ p0.h = hi(EBIU_SDRRC);
+ r0 = mem_SDRRC;
+ w[p0] = r0.l;
+ ssync;
+
+ /*
+ * SDRAM Memory Bank Control Register - bank specific parameters
+ */
+ p0.l = (EBIU_SDBCTL & 0xFFFF);
+ p0.h = (EBIU_SDBCTL >> 16);
+ r0 = mem_SDBCTL;
+ w[p0] = r0.l;
+ ssync;
+
+ /*
+ * SDRAM Global Control Register - global programmable parameters
+ * Disable self-refresh
+ */
+ P2.H = hi(EBIU_SDGCTL);
+ P2.L = lo(EBIU_SDGCTL);
+ R0 = [P2];
+ BITCLR (R0, 24);
+
+ /*
+ * Check if SDRAM is already powered up, if it is, enable self-refresh
+ */
+ p0.h = hi(EBIU_SDSTAT);
+ p0.l = lo(EBIU_SDSTAT);
+ r2.l = w[p0];
+ cc = bittst(r2,3);
+ if !cc jump skip;
+ NOP;
+ BITSET (R0, 23);
+skip:
+ [P2] = R0;
+ SSYNC;
+
+ /* Write in the new value in the register */
+ R0.L = lo(mem_SDGCTL);
+ R0.H = hi(mem_SDGCTL);
+ [P2] = R0;
+ SSYNC;
+ nop;
+
+ (P5:0) = [SP++];
+ (R7:0) = [SP++];
+ RETS = [SP++];
+ ASTAT = [SP++];
+ RTS;
--- /dev/null
+/*
+ * U-boot - interrupt.S Processing of interrupts and exception handling
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * This file is based on interrupt.S
+ *
+ * Copyright (C) 2003 Metrowerks, Inc. <mwaddel@metrowerks.com>
+ * Copyright (C) 2002 Arcturus Networks Ltd. Ted Ma <mated@sympatico.ca>
+ * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
+ * Kenneth Albanowski <kjahds@kjahds.com>,
+ * The Silver Hammer Group, Ltd.
+ *
+ * (c) 1995, Dionne & Associates
+ * (c) 1995, DKG Display Tech.
+ *
+ * This file is also based on exception.asm
+ * (C) Copyright 2001-2005 - Analog Devices, Inc. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define ASSEMBLY
+#include <config.h>
+#include <asm/blackfin.h>
+#include <asm/hw_irq.h>
+#include <asm/entry.h>
+#include <asm/blackfin_defs.h>
+
+.global _blackfin_irq_panic;
+
+.text
+.align 2
+
+#ifndef CONFIG_KGDB
+.global _evt_emulation
+_evt_emulation:
+ SAVE_CONTEXT
+ r0 = IRQ_EMU;
+ r1 = seqstat;
+ sp += -12;
+ call _blackfin_irq_panic;
+ sp += 12;
+ rte;
+#endif
+
+.global _evt_nmi
+_evt_nmi:
+ SAVE_CONTEXT
+ r0 = IRQ_NMI;
+ r1 = RETN;
+ sp += -12;
+ call _blackfin_irq_panic;
+ sp += 12;
+
+_evt_nmi_exit:
+ rtn;
+
+.global _trap
+_trap:
+ SAVE_ALL_SYS
+ r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
+ sp += -12;
+ call _trap_c
+ sp += 12;
+ RESTORE_ALL_SYS
+ rtx;
+
+.global _evt_rst
+_evt_rst:
+ SAVE_CONTEXT
+ r0 = IRQ_RST;
+ r1 = RETN;
+ sp += -12;
+ call _do_reset;
+ sp += 12;
+
+_evt_rst_exit:
+ rtn;
+
+irq_panic:
+ r0 = IRQ_EVX;
+ r1 = sp;
+ sp += -12;
+ call _blackfin_irq_panic;
+ sp += 12;
+
+.global _evt_ivhw
+_evt_ivhw:
+ SAVE_CONTEXT
+ RAISE 14;
+
+_evt_ivhw_exit:
+ rti;
+
+.global _evt_timer
+_evt_timer:
+ SAVE_CONTEXT
+ r0 = IRQ_CORETMR;
+ sp += -12;
+ /* Polling method used now. */
+ /* call timer_int; */
+ sp += 12;
+ RESTORE_CONTEXT
+ rti;
+ nop;
+
+.global _evt_evt7
+_evt_evt7:
+ SAVE_CONTEXT
+ r0 = 7;
+ sp += -12;
+ call _process_int;
+ sp += 12;
+
+evt_evt7_exit:
+ RESTORE_CONTEXT
+ rti;
+
+.global _evt_evt8
+_evt_evt8:
+ SAVE_CONTEXT
+ r0 = 8;
+ sp += -12;
+ call _process_int;
+ sp += 12;
+
+evt_evt8_exit:
+ RESTORE_CONTEXT
+ rti;
+
+.global _evt_evt9
+_evt_evt9:
+ SAVE_CONTEXT
+ r0 = 9;
+ sp += -12;
+ call _process_int;
+ sp += 12;
+
+evt_evt9_exit:
+ RESTORE_CONTEXT
+ rti;
+
+.global _evt_evt10
+_evt_evt10:
+ SAVE_CONTEXT
+ r0 = 10;
+ sp += -12;
+ call _process_int;
+ sp += 12;
+
+evt_evt10_exit:
+ RESTORE_CONTEXT
+ rti;
+
+.global _evt_evt11
+_evt_evt11:
+ SAVE_CONTEXT
+ r0 = 11;
+ sp += -12;
+ call _process_int;
+ sp += 12;
+
+evt_evt11_exit:
+ RESTORE_CONTEXT
+ rti;
+
+.global _evt_evt12
+_evt_evt12:
+ SAVE_CONTEXT
+ r0 = 12;
+ sp += -12;
+ call _process_int;
+ sp += 12;
+evt_evt12_exit:
+ RESTORE_CONTEXT
+ rti;
+
+.global _evt_evt13
+_evt_evt13:
+ SAVE_CONTEXT
+ r0 = 13;
+ sp += -12;
+ call _process_int;
+ sp += 12;
+
+evt_evt13_exit:
+ RESTORE_CONTEXT
+ rti;
+
+.global _evt_system_call
+_evt_system_call:
+ [--sp] = r0;
+ [--SP] = RETI;
+ r0 = [sp++];
+ r0 += 2;
+ [--sp] = r0;
+ RETI = [SP++];
+ r0 = [SP++];
+ SAVE_CONTEXT
+ sp += -12;
+ call _exception_handle;
+ sp += 12;
+ RESTORE_CONTEXT
+ RTI;
+
+evt_system_call_exit:
+ rti;
+
+.global _evt_soft_int1
+_evt_soft_int1:
+ [--sp] = r0;
+ [--SP] = RETI;
+ r0 = [sp++];
+ r0 += 2;
+ [--sp] = r0;
+ RETI = [SP++];
+ r0 = [SP++];
+ SAVE_CONTEXT
+ sp += -12;
+ call _exception_handle;
+ sp += 12;
+ RESTORE_CONTEXT
+ RTI;
+
+evt_soft_int1_exit:
+ rti;
--- /dev/null
+/*
+ * U-boot - interrupts.c Interrupt related routines
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on interrupts.c
+ * Copyright 1996 Roman Zippel
+ * Copyright 1999 D. Jeff Dionne <jeff@uclinux.org>
+ * Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
+ * Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
+ * Copyright 2003 Metrowerks/Motorola
+ * Copyright 2003 Bas Vermeulen <bas@buyways.nl>,
+ * BuyWays B.V. (www.buyways.nl)
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/machdep.h>
+#include <asm/irq.h>
+#include <config.h>
+#include <asm/blackfin.h>
+#include "cpu.h"
+
+static ulong timestamp;
+static ulong last_time;
+static int int_flag;
+
+int irq_flags; /* needed by asm-blackfin/system.h */
+
+/* Functions just to satisfy the linker */
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On BF533 it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On BF533 it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+ ulong tbclk;
+
+ tbclk = CFG_HZ;
+ return tbclk;
+}
+
+void enable_interrupts(void)
+{
+ restore_flags(int_flag);
+}
+
+int disable_interrupts(void)
+{
+ save_and_cli(int_flag);
+ return 1;
+}
+
+int interrupt_init(void)
+{
+ return (0);
+}
+
+void udelay(unsigned long usec)
+{
+ unsigned long delay, start, stop;
+ unsigned long cclk;
+ cclk = (CONFIG_CCLK_HZ);
+
+ while (usec > 1) {
+ /*
+ * how many clock ticks to delay?
+ * - request(in useconds) * clock_ticks(Hz) / useconds/second
+ */
+ if (usec < 1000) {
+ delay = (usec * (cclk / 244)) >> 12;
+ usec = 0;
+ } else {
+ delay = (1000 * (cclk / 244)) >> 12;
+ usec -= 1000;
+ }
+
+ asm volatile (" %0 = CYCLES;":"=r" (start));
+ do {
+ asm volatile (" %0 = CYCLES; ":"=r" (stop));
+ } while (stop - start < delay);
+ }
+
+ return;
+}
+
+void timer_init(void)
+{
+ *pTCNTL = 0x1;
+ *pTSCALE = 0x0;
+ *pTCOUNT = MAX_TIM_LOAD;
+ *pTPERIOD = MAX_TIM_LOAD;
+ *pTCNTL = 0x7;
+ asm("CSYNC;");
+
+ timestamp = 0;
+ last_time = 0;
+}
+
+/* Any network command or flash
+ * command is started get_timer shall
+ * be called before TCOUNT gets reset,
+ * to implement the accurate timeouts.
+ *
+ * How ever milliconds doesn't return
+ * the number that has been elapsed from
+ * the last reset.
+ *
+ * As get_timer is used in the u-boot
+ * only for timeouts this should be
+ * sufficient
+ */
+ulong get_timer(ulong base)
+{
+ ulong milisec;
+
+ /* Number of clocks elapsed */
+ ulong clocks = (MAX_TIM_LOAD - (*pTCOUNT));
+
+ /**
+ * Find if the TCOUNT is reset
+ * timestamp gives the number of times
+ * TCOUNT got reset
+ */
+ if (clocks < last_time)
+ timestamp++;
+ last_time = clocks;
+
+ /* Get the number of milliseconds */
+ milisec = clocks / (CONFIG_CCLK_HZ / 1000);
+
+ /**
+ * Find the number of millisonds
+ * that got elapsed before this TCOUNT cycle
+ */
+ milisec += timestamp * (MAX_TIM_LOAD / (CONFIG_CCLK_HZ / 1000));
+
+ return (milisec - base);
+}
+
+void reset_timer (void)
+{
+ timestamp = 0;
+}
--- /dev/null
+/*
+ * U-boot - ints.c Interrupt related routines
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on ints.c
+ *
+ * Apr18 2003, Changed by HuTao to support interrupt cascading for Blackfin
+ * drivers
+ *
+ * Copyright 1996 Roman Zippel
+ * Copyright 1999 D. Jeff Dionne <jeff@uclinux.org>
+ * Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
+ * Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
+ * Copyright 2003 Metrowerks/Motorola
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/stddef.h>
+#include <asm/system.h>
+#include <asm/irq.h>
+#include <asm/traps.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/machdep.h>
+#include <asm/setup.h>
+#include <asm/blackfin.h>
+#include "cpu.h"
+
+void blackfin_irq_panic(int reason, struct pt_regs *regs)
+{
+ printf("\n\nException: IRQ 0x%x entered\n", reason);
+ printf("code=[0x%x], ", (unsigned int)(regs->seqstat & 0x3f));
+ printf("stack frame=0x%x, ", (unsigned int)regs);
+ printf("bad PC=0x%04x\n", (unsigned int)regs->pc);
+ dump(regs);
+ printf("Unhandled IRQ or exceptions!\n");
+ printf("Please reset the board \n");
+}
+
+void blackfin_init_IRQ(void)
+{
+ *(unsigned volatile long *)(SIC_IMASK) = SIC_UNMASK_ALL;
+ cli();
+#ifndef CONFIG_KGDB
+ *(unsigned volatile long *)(EVT_EMULATION_ADDR) = 0x0;
+#endif
+ *(unsigned volatile long *)(EVT_NMI_ADDR) =
+ (unsigned volatile long)evt_nmi;
+ *(unsigned volatile long *)(EVT_EXCEPTION_ADDR) =
+ (unsigned volatile long)trap;
+ *(unsigned volatile long *)(EVT_HARDWARE_ERROR_ADDR) =
+ (unsigned volatile long)evt_ivhw;
+ *(unsigned volatile long *)(EVT_RESET_ADDR) =
+ (unsigned volatile long)evt_rst;
+ *(unsigned volatile long *)(EVT_TIMER_ADDR) =
+ (unsigned volatile long)evt_timer;
+ *(unsigned volatile long *)(EVT_IVG7_ADDR) =
+ (unsigned volatile long)evt_evt7;
+ *(unsigned volatile long *)(EVT_IVG8_ADDR) =
+ (unsigned volatile long)evt_evt8;
+ *(unsigned volatile long *)(EVT_IVG9_ADDR) =
+ (unsigned volatile long)evt_evt9;
+ *(unsigned volatile long *)(EVT_IVG10_ADDR) =
+ (unsigned volatile long)evt_evt10;
+ *(unsigned volatile long *)(EVT_IVG11_ADDR) =
+ (unsigned volatile long)evt_evt11;
+ *(unsigned volatile long *)(EVT_IVG12_ADDR) =
+ (unsigned volatile long)evt_evt12;
+ *(unsigned volatile long *)(EVT_IVG13_ADDR) =
+ (unsigned volatile long)evt_evt13;
+ *(unsigned volatile long *)(EVT_IVG14_ADDR) =
+ (unsigned volatile long)evt_system_call;
+ *(unsigned volatile long *)(EVT_IVG15_ADDR) =
+ (unsigned volatile long)evt_soft_int1;
+ *(volatile unsigned long *)ILAT = 0;
+ asm("csync;");
+ sti();
+ *(volatile unsigned long *)IMASK = 0xffbf;
+ asm("csync;");
+}
+
+void exception_handle(void)
+{
+#if defined (CONFIG_PANIC_HANG)
+ display_excp();
+#else
+ udelay(100000); /* allow messages to go out */
+ do_reset(NULL, 0, 0, NULL);
+#endif
+}
+
+void display_excp(void)
+{
+ printf("Exception!\n");
+}
--- /dev/null
+/*
+ * U-boot - serial.c Serial driver for BF537
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on
+ * bf537_serial.c: Serial driver for BlackFin BF537 internal UART.
+ * Copyright (c) 2003 Bas Vermeulen <bas@buyways.nl>,
+ * BuyWays B.V. (www.buyways.nl)
+ *
+ * Based heavily on blkfinserial.c
+ * blkfinserial.c: Serial driver for BlackFin DSP internal USRTs.
+ * Copyright(c) 2003 Metrowerks <mwaddel@metrowerks.com>
+ * Copyright(c) 2001 Tony Z. Kou <tonyko@arcturusnetworks.com>
+ * Copyright(c) 2001-2002 Arcturus Networks Inc. <www.arcturusnetworks.com>
+ *
+ * Based on code from 68328 version serial driver imlpementation which was:
+ * Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu>
+ * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>
+ * Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org>
+ * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/segment.h>
+#include <asm/bitops.h>
+#include <asm/delay.h>
+#include <asm/uaccess.h>
+#include <asm/io.h>
+#include "serial.h"
+
+unsigned long pll_div_fact;
+
+void calc_baud(void)
+{
+ unsigned char i;
+ int temp;
+ u_long sclk = get_sclk();
+
+ for (i = 0; i < sizeof(baud_table) / sizeof(int); i++) {
+ temp = sclk / (baud_table[i] * 8);
+ if ((temp & 0x1) == 1) {
+ temp++;
+ }
+ temp = temp / 2;
+ hw_baud_table[i].dl_high = (temp >> 8) & 0xFF;
+ hw_baud_table[i].dl_low = (temp) & 0xFF;
+ }
+}
+
+void serial_setbrg(void)
+{
+ int i;
+ DECLARE_GLOBAL_DATA_PTR;
+
+ calc_baud();
+
+ for (i = 0; i < sizeof(baud_table) / sizeof(int); i++) {
+ if (gd->baudrate == baud_table[i])
+ break;
+ }
+
+ /* Enable UART */
+ *pUART_GCTL |= UART_GCTL_UCEN;
+ sync();
+
+ /* Set DLAB in LCR to Access DLL and DLH */
+ ACCESS_LATCH;
+ sync();
+
+ *pUART_DLL = hw_baud_table[i].dl_low;
+ sync();
+ *pUART_DLH = hw_baud_table[i].dl_high;
+ sync();
+
+ /* Clear DLAB in LCR to Access THR RBR IER */
+ ACCESS_PORT_IER;
+ sync();
+
+ /* Enable ERBFI and ELSI interrupts
+ * to poll SIC_ISR register*/
+ *pUART_IER = UART_IER_ELSI | UART_IER_ERBFI | UART_IER_ETBEI;
+ sync();
+
+ /* Set LCR to Word Lengh 8-bit word select */
+ *pUART_LCR = UART_LCR_WLS8;
+ sync();
+
+ return;
+}
+
+int serial_init(void)
+{
+ serial_setbrg();
+ return (0);
+}
+
+void serial_putc(const char c)
+{
+ if ((*pUART_LSR) & UART_LSR_TEMT) {
+ if (c == '\n')
+ serial_putc('\r');
+
+ local_put_char(c);
+ }
+
+ while (!((*pUART_LSR) & UART_LSR_TEMT))
+ SYNC_ALL;
+
+ return;
+}
+
+int serial_tstc(void)
+{
+ if (*pUART_LSR & UART_LSR_DR)
+ return 1;
+ else
+ return 0;
+}
+
+int serial_getc(void)
+{
+ unsigned short uart_lsr_val, uart_rbr_val;
+ unsigned long isr_val;
+ int ret;
+
+ /* Poll for RX Interrupt */
+ while (!((isr_val =
+ *(volatile unsigned long *)SIC_ISR) & IRQ_UART_RX_BIT)) ;
+ asm("csync;");
+
+ uart_lsr_val = *pUART_LSR; /* Clear status bit */
+ uart_rbr_val = *pUART_RBR; /* getc() */
+
+ if (isr_val & IRQ_UART_ERROR_BIT) {
+ ret = -1;
+ } else {
+ ret = uart_rbr_val & 0xff;
+ }
+
+ return ret;
+}
+
+void serial_puts(const char *s)
+{
+ while (*s) {
+ serial_putc(*s++);
+ }
+}
+
+static void local_put_char(char ch)
+{
+ int flags = 0;
+ unsigned long isr_val;
+
+ save_and_cli(flags);
+
+ /* Poll for TX Interruput */
+ while (!((isr_val = *pSIC_ISR) & IRQ_UART_TX_BIT)) ;
+ asm("csync;");
+
+ *pUART_THR = ch; /* putc() */
+
+ if (isr_val & IRQ_UART_ERROR_BIT) {
+ printf("?");
+ }
+
+ restore_flags(flags);
+
+ return;
+}
--- /dev/null
+/*
+ * U-boot - bf537_serial.h Serial Driver defines
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on
+ * bf533_serial.h: Definitions for the BlackFin BF533 DSP serial driver.
+ * Copyright (C) 2003 Bas Vermeulen <bas@buyways.nl>
+ * BuyWays B.V. (www.buyways.nl)
+ *
+ * Based heavily on:
+ * blkfinserial.h: Definitions for the BlackFin DSP serial driver.
+ *
+ * Copyright (C) 2001 Tony Z. Kou tonyko@arcturusnetworks.com
+ * Copyright (C) 2001 Arcturus Networks Inc. <www.arcturusnetworks.com>
+ *
+ * Based on code from 68328serial.c which was:
+ * Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu>
+ * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>
+ * Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org>
+ * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _Bf537_SERIAL_H
+#define _Bf537_SERIAL_H
+
+#include <linux/config.h>
+#include <asm/blackfin.h>
+
+#define SYNC_ALL __asm__ __volatile__ ("ssync;\n")
+#define ACCESS_LATCH *pUART_LCR |= UART_LCR_DLAB;
+#define ACCESS_PORT_IER *pUART_LCR &= (~UART_LCR_DLAB);
+
+void serial_setbrg(void);
+static void local_put_char(char ch);
+void calc_baud(void);
+void serial_setbrg(void);
+int serial_init(void);
+void serial_putc(const char c);
+int serial_tstc(void);
+int serial_getc(void);
+void serial_puts(const char *s);
+static void local_put_char(char ch);
+
+int baud_table[5] = { 9600, 19200, 38400, 57600, 115200 };
+
+struct {
+ unsigned char dl_high;
+ unsigned char dl_low;
+} hw_baud_table[5];
+
+#ifdef CONFIG_STAMP
+extern unsigned long pll_div_fact;
+#endif
+
+#endif
--- /dev/null
+/*
+ * U-boot - start.S Startup file of u-boot for BF537
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on head.S
+ * Copyright (c) 2003 Metrowerks/Motorola
+ * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
+ * Kenneth Albanowski <kjahds@kjahds.com>,
+ * The Silver Hammer Group, Ltd.
+ * (c) 1995, Dionne & Associates
+ * (c) 1995, DKG Display Tech.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Note: A change in this file subsequently requires a change in
+ * board/$(board_name)/config.mk for a valid u-boot.bin
+ */
+
+#define ASSEMBLY
+
+#include <linux/config.h>
+#include <config.h>
+#include <asm/blackfin.h>
+
+.global _stext;
+.global __bss_start;
+.global start;
+.global _start;
+.global _rambase;
+.global _ramstart;
+.global _ramend;
+.global _bf533_data_dest;
+.global _bf533_data_size;
+.global edata;
+.global _initialize;
+.global _exit;
+.global flashdataend;
+.global init_sdram;
+.global _icache_enable;
+.global _dcache_enable;
+#if defined(CONFIG_BF537)&&defined(CONFIG_POST)
+.global _memory_post_test;
+.global _post_flag;
+#endif
+
+#if (BFIN_BOOT_MODE == BF537_UART_BOOT)
+#if (CONFIG_CCLK_DIV == 1)
+#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
+#endif
+#if (CONFIG_CCLK_DIV == 2)
+#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
+#endif
+#if (CONFIG_CCLK_DIV == 4)
+#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
+#endif
+#if (CONFIG_CCLK_DIV == 8)
+#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
+#endif
+#ifndef CONFIG_CCLK_ACT_DIV
+#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
+#endif
+#endif
+
+.text
+_start:
+start:
+_stext:
+
+ R0 = 0x32;
+ SYSCFG = R0;
+ SSYNC;
+
+ /* As per HW reference manual DAG registers,
+ * DATA and Address resgister shall be zero'd
+ * in initialization, after a reset state
+ */
+ r1 = 0; /* Data registers zero'd */
+ r2 = 0;
+ r3 = 0;
+ r4 = 0;
+ r5 = 0;
+ r6 = 0;
+ r7 = 0;
+
+ p0 = 0; /* Address registers zero'd */
+ p1 = 0;
+ p2 = 0;
+ p3 = 0;
+ p4 = 0;
+ p5 = 0;
+
+ i0 = 0; /* DAG Registers zero'd */
+ i1 = 0;
+ i2 = 0;
+ i3 = 0;
+ m0 = 0;
+ m1 = 0;
+ m3 = 0;
+ m3 = 0;
+ l0 = 0;
+ l1 = 0;
+ l2 = 0;
+ l3 = 0;
+ b0 = 0;
+ b1 = 0;
+ b2 = 0;
+ b3 = 0;
+
+ /* Set loop counters to zero, to make sure that
+ * hw loops are disabled.
+ */
+ r0 = 0;
+ lc0 = r0;
+ lc1 = r0;
+
+ SSYNC;
+
+ /* Check soft reset status */
+ p0.h = SWRST >> 16;
+ p0.l = SWRST & 0xFFFF;
+ r0.l = w[p0];
+
+ cc = bittst(r0, 15);
+ if !cc jump no_soft_reset;
+
+ /* Clear Soft reset */
+ r0 = 0x0000;
+ w[p0] = r0;
+ ssync;
+
+no_soft_reset:
+ nop;
+
+ /* Clear EVT registers */
+ p0.h = (EVT_EMULATION_ADDR >> 16);
+ p0.l = (EVT_EMULATION_ADDR & 0xFFFF);
+ p0 += 8;
+ p1 = 14;
+ r1 = 0;
+ LSETUP(4,4) lc0 = p1;
+ [ p0 ++ ] = r1;
+
+#if (BFIN_BOOT_MODE != BF537_SPI_MASTER_BOOT)
+ p0.h = hi(SIC_IWR);
+ p0.l = lo(SIC_IWR);
+ r0.l = 0x1;
+ w[p0] = r0.l;
+ SSYNC;
+#endif
+
+#if (BFIN_BOOT_MODE == BF537_UART_BOOT)
+
+ p0.h = hi(SIC_IWR);
+ p0.l = lo(SIC_IWR);
+ r0.l = 0x1;
+ w[p0] = r0.l;
+ SSYNC;
+
+ /*
+ * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
+ */
+ p0.h = hi(PLL_LOCKCNT);
+ p0.l = lo(PLL_LOCKCNT);
+ r0 = 0x300(Z);
+ w[p0] = r0.l;
+ ssync;
+
+ /*
+ * Put SDRAM in self-refresh, incase anything is running
+ */
+ P2.H = hi(EBIU_SDGCTL);
+ P2.L = lo(EBIU_SDGCTL);
+ R0 = [P2];
+ BITSET (R0, 24);
+ [P2] = R0;
+ SSYNC;
+
+ /*
+ * Set PLL_CTL with the value that we calculate in R0
+ * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
+ * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
+ * - [7] = output delay (add 200ps of delay to mem signals)
+ * - [6] = input delay (add 200ps of input delay to mem signals)
+ * - [5] = PDWN : 1=All Clocks off
+ * - [3] = STOPCK : 1=Core Clock off
+ * - [1] = PLL_OFF : 1=Disable Power to PLL
+ * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
+ * all other bits set to zero
+ */
+
+ r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
+ r0 = r0 << 9; /* Shift it over, */
+ r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
+ r0 = r1 | r0;
+ r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
+ r1 = r1 << 8; /* Shift it over */
+ r0 = r1 | r0; /* add them all together */
+
+ p0.h = hi(PLL_CTL);
+ p0.l = lo(PLL_CTL); /* Load the address */
+ cli r2; /* Disable interrupts */
+ ssync;
+ w[p0] = r0.l; /* Set the value */
+ idle; /* Wait for the PLL to stablize */
+ sti r2; /* Enable interrupts */
+
+check_again:
+ p0.h = hi(PLL_STAT);
+ p0.l = lo(PLL_STAT);
+ R0 = W[P0](Z);
+ CC = BITTST(R0,5);
+ if ! CC jump check_again;
+
+ /* Configure SCLK & CCLK Dividers */
+ r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
+ p0.h = hi(PLL_DIV);
+ p0.l = lo(PLL_DIV);
+ w[p0] = r0.l;
+ ssync;
+#endif
+
+ /*
+ * We now are running at speed, time to set the Async mem bank wait states
+ * This will speed up execution, since we are normally running from FLASH.
+ * we need to read MAC address from FLASH
+ */
+ p2.h = (EBIU_AMBCTL1 >> 16);
+ p2.l = (EBIU_AMBCTL1 & 0xFFFF);
+ r0.h = (AMBCTL1VAL >> 16);
+ r0.l = (AMBCTL1VAL & 0xFFFF);
+ [p2] = r0;
+ ssync;
+
+ p2.h = (EBIU_AMBCTL0 >> 16);
+ p2.l = (EBIU_AMBCTL0 & 0xFFFF);
+ r0.h = (AMBCTL0VAL >> 16);
+ r0.l = (AMBCTL0VAL & 0xFFFF);
+ [p2] = r0;
+ ssync;
+
+ p2.h = (EBIU_AMGCTL >> 16);
+ p2.l = (EBIU_AMGCTL & 0xffff);
+ r0 = AMGCTLVAL;
+ w[p2] = r0;
+ ssync;
+
+#if ((BFIN_BOOT_MODE != BF537_SPI_MASTER_BOOT) && (BFIN_BOOT_MODE != BF537_UART_BOOT))
+ sp.l = (0xffb01000 & 0xFFFF);
+ sp.h = (0xffb01000 >> 16);
+
+ call init_sdram;
+#endif
+
+
+#if defined(CONFIG_BF537)&&defined(CONFIG_POST)
+ /* DMA POST code to Hi of L1 SRAM */
+postcopy:
+ /* P1 Points to the beginning of SYSTEM MMR Space */
+ P1.H = hi(SYSMMR_BASE);
+ P1.L = lo(SYSMMR_BASE);
+
+ R0.H = _text_l1;
+ R0.L = _text_l1;
+ R1.H = _etext_l1;
+ R1.L = _etext_l1;
+ R2 = R1 - R0; /* Count */
+ R0.H = _etext;
+ R0.L = _etext;
+ R1.H = (CFG_MONITOR_BASE >> 16);
+ R1.L = (CFG_MONITOR_BASE & 0xFFFF);
+ R0 = R0 - R1;
+ R1.H = (CFG_FLASH_BASE >> 16);
+ R1.L = (CFG_FLASH_BASE & 0xFFFF);
+ R0 = R0 + R1; /* Source Address */
+ R1.H = hi(L1_ISRAM); /* Destination Address (high) */
+ R1.L = lo(L1_ISRAM); /* Destination Address (low) */
+ R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
+ /* Destination DMAConfig Value (8-bit words) */
+ R4.L = (DI_EN | WNR | DMAEN);
+
+ R6 = 0x1 (Z);
+ W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
+ W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
+
+ [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
+ W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
+ /* Set Source DMAConfig = DMA Enable,
+ Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
+ W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
+
+ [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
+ W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
+ /* Set Destination DMAConfig = DMA Enable,
+ Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
+ W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
+
+POST_DMA_DONE:
+ p0.h = hi(MDMA_D0_IRQ_STATUS);
+ p0.l = lo(MDMA_D0_IRQ_STATUS);
+ R0 = W[P0](Z);
+ CC = BITTST(R0, 0);
+ if ! CC jump POST_DMA_DONE
+
+ R0 = 0x1;
+ W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
+
+ /* DMA POST data to Hi of L1 SRAM */
+ R0.H = _rodata_l1;
+ R0.L = _rodata_l1;
+ R1.H = _erodata_l1;
+ R1.L = _erodata_l1;
+ R2 = R1 - R0; /* Count */
+ R0.H = _erodata;
+ R0.L = _erodata;
+ R1.H = (CFG_MONITOR_BASE >> 16);
+ R1.L = (CFG_MONITOR_BASE & 0xFFFF);
+ R0 = R0 - R1;
+ R1.H = (CFG_FLASH_BASE >> 16);
+ R1.L = (CFG_FLASH_BASE & 0xFFFF);
+ R0 = R0 + R1; /* Source Address */
+ R1.H = hi(DATA_BANKB_SRAM); /* Destination Address (high) */
+ R1.L = lo(DATA_BANKB_SRAM); /* Destination Address (low) */
+ R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
+ R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */
+
+ R6 = 0x1 (Z);
+ W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
+ W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
+
+ [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
+ W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
+ /* Set Source DMAConfig = DMA Enable,
+ Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
+ W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
+
+ [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
+ W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
+ /* Set Destination DMAConfig = DMA Enable,
+ Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
+ W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
+
+POST_DATA_DMA_DONE:
+ p0.h = hi(MDMA_D0_IRQ_STATUS);
+ p0.l = lo(MDMA_D0_IRQ_STATUS);
+ R0 = W[P0](Z);
+ CC = BITTST(R0, 0);
+ if ! CC jump POST_DATA_DMA_DONE
+
+ R0 = 0x1;
+ W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
+
+ p0.l = _memory_post_test;
+ p0.h = _memory_post_test;
+ r0 = 0x0;
+ call (p0);
+ r7 = r0; /* save return value */
+
+ call init_sdram;
+#endif
+
+ /* relocate into to RAM */
+ call get_pc;
+offset:
+ r2.l = offset;
+ r2.h = offset;
+ r3.l = start;
+ r3.h = start;
+ r1 = r2 - r3;
+
+ r0 = r0 - r1;
+ p1 = r0;
+
+ p2.l = (CFG_MONITOR_BASE & 0xffff);
+ p2.h = (CFG_MONITOR_BASE >> 16);
+
+ p3 = 0x04;
+ p4.l = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) & 0xffff);
+ p4.h = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) >> 16);
+loop1:
+ r1 = [p1 ++ p3];
+ [p2 ++ p3] = r1;
+ cc=p2==p4;
+ if !cc jump loop1;
+ /*
+ * configure STACK
+ */
+ r0.h = (CONFIG_STACKBASE >> 16);
+ r0.l = (CONFIG_STACKBASE & 0xFFFF);
+ sp = r0;
+ fp = sp;
+
+ /*
+ * This next section keeps the processor in supervisor mode
+ * during kernel boot. Switches to user mode at end of boot.
+ * See page 3-9 of Hardware Reference manual for documentation.
+ */
+
+ /* To keep ourselves in the supervisor mode */
+ p0.l = (EVT_IVG15_ADDR & 0xFFFF);
+ p0.h = (EVT_IVG15_ADDR >> 16);
+
+ p1.l = _real_start;
+ p1.h = _real_start;
+ [p0] = p1;
+
+ p0.l = (IMASK & 0xFFFF);
+ p0.h = (IMASK >> 16);
+ r0.l = LO(IVG15_POS);
+ r0.h = HI(IVG15_POS);
+ [p0] = r0;
+ raise 15;
+ p0.l = WAIT_HERE;
+ p0.h = WAIT_HERE;
+ reti = p0;
+ rti;
+
+WAIT_HERE:
+ jump WAIT_HERE;
+
+.global _real_start;
+_real_start:
+ [ -- sp ] = reti;
+
+#ifdef CONFIG_BF537
+/* Initialise General-Purpose I/O Modules on BF537
+ * Rev 0.0 Anomaly 05000212 - PORTx_FER,
+ * PORT_MUX Registers Do Not accept "writes" correctly
+ */
+ p0.h = hi(PORTF_FER);
+ p0.l = lo(PORTF_FER);
+ R0.L = W[P0]; /* Read */
+ nop;
+ nop;
+ nop;
+ ssync;
+ R0 = 0x000F(Z);
+ W[P0] = R0.L; /* Write */
+ nop;
+ nop;
+ nop;
+ ssync;
+ W[P0] = R0.L; /* Enable peripheral function of PORTF for UART0 and UART1 */
+ nop;
+ nop;
+ nop;
+ ssync;
+
+ p0.h = hi(PORTH_FER);
+ p0.l = lo(PORTH_FER);
+ R0.L = W[P0]; /* Read */
+ nop;
+ nop;
+ nop;
+ ssync;
+ R0 = 0xFFFF(Z);
+ W[P0] = R0.L; /* Write */
+ nop;
+ nop;
+ nop;
+ ssync;
+ W[P0] = R0.L; /* Enable peripheral function of PORTH for MAC */
+ nop;
+ nop;
+ nop;
+ ssync;
+
+#endif
+
+ /* DMA reset code to Hi of L1 SRAM */
+copy:
+ P1.H = hi(SYSMMR_BASE); /* P1 Points to the beginning of SYSTEM MMR Space */
+ P1.L = lo(SYSMMR_BASE);
+
+ R0.H = reset_start; /* Source Address (high) */
+ R0.L = reset_start; /* Source Address (low) */
+ R1.H = reset_end;
+ R1.L = reset_end;
+ R2 = R1 - R0; /* Count */
+ R1.H = hi(L1_ISRAM); /* Destination Address (high) */
+ R1.L = lo(L1_ISRAM); /* Destination Address (low) */
+ R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
+ R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */
+
+DMA:
+ R6 = 0x1 (Z);
+ W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
+ W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
+
+ [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
+ W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
+ /* Set Source DMAConfig = DMA Enable,
+ Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
+ W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
+
+ [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
+ W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
+ /* Set Destination DMAConfig = DMA Enable,
+ Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
+ W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
+
+WAIT_DMA_DONE:
+ p0.h = hi(MDMA_D0_IRQ_STATUS);
+ p0.l = lo(MDMA_D0_IRQ_STATUS);
+ R0 = W[P0](Z);
+ CC = BITTST(R0, 0);
+ if ! CC jump WAIT_DMA_DONE
+
+ R0 = 0x1;
+ W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
+
+ /* Initialize BSS Section with 0 s */
+ p1.l = __bss_start;
+ p1.h = __bss_start;
+ p2.l = _end;
+ p2.h = _end;
+ r1 = p1;
+ r2 = p2;
+ r3 = r2 - r1;
+ r3 = r3 >> 2;
+ p3 = r3;
+ lsetup (_clear_bss, _clear_bss_end ) lc1 = p3;
+ CC = p2<=p1;
+ if CC jump _clear_bss_skip;
+ r0 = 0;
+_clear_bss:
+_clear_bss_end:
+ [p1++] = r0;
+_clear_bss_skip:
+
+#if defined(CONFIG_BF537)&&defined(CONFIG_POST)
+ p0.l = _post_flag;
+ p0.h = _post_flag;
+ r0 = r7;
+ [p0] = r0;
+#endif
+
+ p0.l = _start1;
+ p0.h = _start1;
+ jump (p0);
+
+reset_start:
+ p0.h = WDOG_CNT >> 16;
+ p0.l = WDOG_CNT & 0xffff;
+ r0 = 0x0010;
+ w[p0] = r0;
+ p0.h = WDOG_CTL >> 16;
+ p0.l = WDOG_CTL & 0xffff;
+ r0 = 0x0000;
+ w[p0] = r0;
+reset_wait:
+ jump reset_wait;
+
+reset_end:
+ nop;
+
+_exit:
+ jump.s _exit;
+get_pc:
+ r0 = rets;
+ rts;
--- /dev/null
+/*
+ * U-boot - start1.S Code running out of RAM after relocation
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define ASSEMBLY
+#include <linux/config.h>
+#include <config.h>
+#include <asm/blackfin.h>
+
+.global start1;
+.global _start1;
+
+.text
+_start1:
+start1:
+ sp += -12;
+ call _board_init_f;
+ sp += 12;
--- /dev/null
+/*
+ * U-boot - traps.c Routines related to interrupts and exceptions
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on
+ * No original Copyright holder listed,
+ * Probabily original (C) Roman Zippel (assigned DJD, 1999)
+ *
+ * Copyright 2003 Metrowerks - for Blackfin
+ * Copyright 2000-2001 Lineo, Inc. D. Jeff Dionne <jeff@lineo.ca>
+ * Copyright 1999-2000 D. Jeff Dionne, <jeff@uclinux.org>
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/types.h>
+#include <asm/errno.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/traps.h>
+#include <asm/page.h>
+#include <asm/machdep.h>
+#include "cpu.h"
+#include <asm/arch/anomaly.h>
+#include <asm/cplb.h>
+#include <asm/io.h>
+
+void init_IRQ(void)
+{
+ blackfin_init_IRQ();
+ return;
+}
+
+void process_int(unsigned long vec, struct pt_regs *fp)
+{
+ printf("interrupt\n");
+ return;
+}
+
+extern unsigned int icplb_table[page_descriptor_table_size][2];
+extern unsigned int dcplb_table[page_descriptor_table_size][2];
+
+unsigned long last_cplb_fault_retx;
+
+static unsigned int cplb_sizes[4] =
+ { 1024, 4 * 1024, 1024 * 1024, 4 * 1024 * 1024 };
+
+void trap_c(struct pt_regs *regs)
+{
+ unsigned int addr;
+ unsigned long trapnr = (regs->seqstat) & SEQSTAT_EXCAUSE;
+ unsigned int i, j, size, *I0, *I1;
+ unsigned short data = 0;
+
+ switch (trapnr) {
+ /* 0x26 - Data CPLB Miss */
+ case VEC_CPLB_M:
+
+#ifdef ANOMALY_05000261
+ /*
+ * Work around an anomaly: if we see a new DCPLB fault,
+ * return without doing anything. Then,
+ * if we get the same fault again, handle it.
+ */
+ addr = last_cplb_fault_retx;
+ last_cplb_fault_retx = regs->retx;
+ printf("this time, curr = 0x%08x last = 0x%08x\n",
+ addr, last_cplb_fault_retx);
+ if (addr != last_cplb_fault_retx)
+ goto trap_c_return;
+#endif
+ data = 1;
+
+ case VEC_CPLB_I_M:
+
+ if (data) {
+ addr = *pDCPLB_FAULT_ADDR;
+ } else {
+ addr = *pICPLB_FAULT_ADDR;
+ }
+ for (i = 0; i < page_descriptor_table_size; i++) {
+ if (data) {
+ size = cplb_sizes[dcplb_table[i][1] >> 16];
+ j = dcplb_table[i][0];
+ } else {
+ size = cplb_sizes[icplb_table[i][1] >> 16];
+ j = icplb_table[i][0];
+ }
+ if ((j <= addr) && ((j + size) > addr)) {
+ debug("found %i 0x%08x\n", i, j);
+ break;
+ }
+ }
+ if (i == page_descriptor_table_size) {
+ printf("something is really wrong\n");
+ do_reset(NULL, 0, 0, NULL);
+ }
+
+ /* Turn the cache off */
+ if (data) {
+ sync();
+ asm(" .align 8; ");
+ *(unsigned int *)DMEM_CONTROL &=
+ ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
+ sync();
+ } else {
+ sync();
+ asm(" .align 8; ");
+ *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
+ sync();
+ }
+
+ if (data) {
+ I0 = (unsigned int *)DCPLB_ADDR0;
+ I1 = (unsigned int *)DCPLB_DATA0;
+ } else {
+ I0 = (unsigned int *)ICPLB_ADDR0;
+ I1 = (unsigned int *)ICPLB_DATA0;
+ }
+
+ j = 0;
+ while (*I1 & CPLB_LOCK) {
+ debug("skipping %i %08p - %08x\n", j, I1, *I1);
+ *I0++;
+ *I1++;
+ j++;
+ }
+
+ debug("remove %i 0x%08x 0x%08x\n", j, *I0, *I1);
+
+ for (; j < 15; j++) {
+ debug("replace %i 0x%08x 0x%08x\n", j, I0, I0 + 1);
+ *I0++ = *(I0 + 1);
+ *I1++ = *(I1 + 1);
+ }
+
+ if (data) {
+ *I0 = dcplb_table[i][0];
+ *I1 = dcplb_table[i][1];
+ I0 = (unsigned int *)DCPLB_ADDR0;
+ I1 = (unsigned int *)DCPLB_DATA0;
+ } else {
+ *I0 = icplb_table[i][0];
+ *I1 = icplb_table[i][1];
+ I0 = (unsigned int *)ICPLB_ADDR0;
+ I1 = (unsigned int *)ICPLB_DATA0;
+ }
+
+ for (j = 0; j < 16; j++) {
+ debug("%i 0x%08x 0x%08x\n", j, *I0++, *I1++);
+ }
+
+ /* Turn the cache back on */
+ if (data) {
+ j = *(unsigned int *)DMEM_CONTROL;
+ sync();
+ asm(" .align 8; ");
+ *(unsigned int *)DMEM_CONTROL =
+ ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j;
+ sync();
+ } else {
+ sync();
+ asm(" .align 8; ");
+ *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
+ sync();
+ }
+
+ break;
+ default:
+ /* All traps come here */
+ printf("code=[0x%x], ", (unsigned int)(regs->seqstat & 0x3f));
+ printf("stack frame=0x%x, ", (unsigned int)regs);
+ printf("bad PC=0x%04x\n", (unsigned int)regs->pc);
+ dump(regs);
+ printf("\n\n");
+
+ printf("Unhandled IRQ or exceptions!\n");
+ printf("Please reset the board \n");
+ do_reset(NULL, 0, 0, NULL);
+ }
+
+trap_c_return:
+ return;
+
+}
+
+void dump(struct pt_regs *fp)
+{
+ debug("RETE: %08lx RETN: %08lx RETX: %08lx RETS: %08lx\n",
+ fp->rete, fp->retn, fp->retx, fp->rets);
+ debug("IPEND: %04lx SYSCFG: %04lx\n", fp->ipend, fp->syscfg);
+ debug("SEQSTAT: %08lx SP: %08lx\n", (long)fp->seqstat, (long)fp);
+ debug("R0: %08lx R1: %08lx R2: %08lx R3: %08lx\n",
+ fp->r0, fp->r1, fp->r2, fp->r3);
+ debug("R4: %08lx R5: %08lx R6: %08lx R7: %08lx\n",
+ fp->r4, fp->r5, fp->r6, fp->r7);
+ debug("P0: %08lx P1: %08lx P2: %08lx P3: %08lx\n",
+ fp->p0, fp->p1, fp->p2, fp->p3);
+ debug("P4: %08lx P5: %08lx FP: %08lx\n",
+ fp->p4, fp->p5, fp->fp);
+ debug("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
+ fp->a0w, fp->a0x, fp->a1w, fp->a1x);
+
+ debug("LB0: %08lx LT0: %08lx LC0: %08lx\n",
+ fp->lb0, fp->lt0, fp->lc0);
+ debug("LB1: %08lx LT1: %08lx LC1: %08lx\n",
+ fp->lb1, fp->lt1, fp->lc1);
+ debug("B0: %08lx L0: %08lx M0: %08lx I0: %08lx\n",
+ fp->b0, fp->l0, fp->m0, fp->i0);
+ debug("B1: %08lx L1: %08lx M1: %08lx I1: %08lx\n",
+ fp->b1, fp->l1, fp->m1, fp->i1);
+ debug("B2: %08lx L2: %08lx M2: %08lx I2: %08lx\n",
+ fp->b2, fp->l2, fp->m2, fp->i2);
+ debug("B3: %08lx L3: %08lx M3: %08lx I3: %08lx\n",
+ fp->b3, fp->l3, fp->m3, fp->i3);
+
+ debug("DCPLB_FAULT_ADDR=%p\n", *pDCPLB_FAULT_ADDR);
+ debug("ICPLB_FAULT_ADDR=%p\n", *pICPLB_FAULT_ADDR);
+
+}
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
+ * (C) Copyright 2002
+ * Wolfgang Denk, wd@denx.de
+ * (C) Copyright 2006
+ * Aubrey Li, aubrey.li@analog.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <stdarg.h>
+#include <common.h>
+#include <config.h>
+#include <asm/blackfin.h>
+#include <i2c.h>
+#include <linux/types.h>
+#include <devices.h>
+
+#ifdef CONFIG_VIDEO
+#define NTSC_FRAME_ADDR 0x06000000
+#include "video.h"
+
+/* NTSC OUTPUT SIZE 720 * 240 */
+#define VERTICAL 2
+#define HORIZONTAL 4
+
+int is_vblank_line(const int line)
+{
+ /*
+ * This array contains a single bit for each line in
+ * an NTSC frame.
+ */
+ if ((line <= 18) || (line >= 264 && line <= 281) || (line == 528))
+ return true;
+
+ return false;
+}
+
+int NTSC_framebuffer_init(char *base_address)
+{
+ const int NTSC_frames = 1;
+ const int NTSC_lines = 525;
+ char *dest = base_address;
+ int frame_num, line_num;
+
+ for (frame_num = 0; frame_num < NTSC_frames; ++frame_num) {
+ for (line_num = 1; line_num <= NTSC_lines; ++line_num) {
+ unsigned int code;
+ int offset = 0;
+ int i;
+
+ if (is_vblank_line(line_num))
+ offset++;
+
+ if (line_num > 266 || line_num < 3)
+ offset += 2;
+
+ /* Output EAV code */
+ code = SystemCodeMap[offset].EAV;
+ write_dest_byte((char)(code >> 24) & 0xff);
+ write_dest_byte((char)(code >> 16) & 0xff);
+ write_dest_byte((char)(code >> 8) & 0xff);
+ write_dest_byte((char)(code) & 0xff);
+
+ /* Output horizontal blanking */
+ for (i = 0; i < 67 * 2; ++i) {
+ write_dest_byte(0x80);
+ write_dest_byte(0x10);
+ }
+
+ /* Output SAV */
+ code = SystemCodeMap[offset].SAV;
+ write_dest_byte((char)(code >> 24) & 0xff);
+ write_dest_byte((char)(code >> 16) & 0xff);
+ write_dest_byte((char)(code >> 8) & 0xff);
+ write_dest_byte((char)(code) & 0xff);
+
+ /* Output empty horizontal data */
+ for (i = 0; i < 360 * 2; ++i) {
+ write_dest_byte(0x80);
+ write_dest_byte(0x10);
+ }
+ }
+ }
+
+ return dest - base_address;
+}
+
+void fill_frame(char *Frame, int Value)
+{
+ int *OddPtr32;
+ int OddLine;
+ int *EvenPtr32;
+ int EvenLine;
+ int i;
+ int *data;
+ int m, n;
+
+ /* fill odd and even frames */
+ for (OddLine = 22, EvenLine = 285; OddLine < 263; OddLine++, EvenLine++) {
+ OddPtr32 = (int *)((Frame + (OddLine * 1716)) + 276);
+ EvenPtr32 = (int *)((Frame + (EvenLine * 1716)) + 276);
+ for (i = 0; i < 360; i++, OddPtr32++, EvenPtr32++) {
+ *OddPtr32 = Value;
+ *EvenPtr32 = Value;
+ }
+ }
+
+ for (m = 0; m < VERTICAL; m++) {
+ data = (int *)u_boot_logo.data;
+ for (OddLine = (22 + m), EvenLine = (285 + m);
+ OddLine < (u_boot_logo.height * VERTICAL) + (22 + m);
+ OddLine += VERTICAL, EvenLine += VERTICAL) {
+ OddPtr32 = (int *)((Frame + ((OddLine) * 1716)) + 276);
+ EvenPtr32 =
+ (int *)((Frame + ((EvenLine) * 1716)) + 276);
+ for (i = 0; i < u_boot_logo.width / 2; i++) {
+ /* enlarge one pixel to m x n */
+ for (n = 0; n < HORIZONTAL; n++) {
+ *OddPtr32++ = *data;
+ *EvenPtr32++ = *data;
+ }
+ data++;
+ }
+ }
+ }
+}
+
+void video_putc(const char c)
+{
+}
+
+void video_puts(const char *s)
+{
+}
+
+static int video_init(void)
+{
+ char *NTSCFrame;
+ NTSCFrame = (char *)NTSC_FRAME_ADDR;
+ NTSC_framebuffer_init(NTSCFrame);
+ fill_frame(NTSCFrame, BLUE);
+
+ *pPPI_CONTROL = 0x0082;
+ *pPPI_FRAME = 0x020D;
+
+ *pDMA0_START_ADDR = NTSCFrame;
+ *pDMA0_X_COUNT = 0x035A;
+ *pDMA0_X_MODIFY = 0x0002;
+ *pDMA0_Y_COUNT = 0x020D;
+ *pDMA0_Y_MODIFY = 0x0002;
+ *pDMA0_CONFIG = 0x1015;
+ *pPPI_CONTROL = 0x0083;
+ return 0;
+}
+
+int drv_video_init(void)
+{
+ int error, devices = 1;
+
+ device_t videodev;
+
+ video_init(); /* Video initialization */
+
+ memset(&videodev, 0, sizeof(videodev));
+
+ strcpy(videodev.name, "video");
+ videodev.ext = DEV_EXT_VIDEO; /* Video extensions */
+ videodev.flags = DEV_FLAGS_OUTPUT; /* Output only */
+ videodev.putc = video_putc; /* 'putc' function */
+ videodev.puts = video_puts; /* 'puts' function */
+
+ error = device_register(&videodev);
+
+ return (error == 0) ? devices : error;
+}
+#endif
--- /dev/null
+#include <video_logo.h>
+#define write_dest_byte(val) {*dest++=val;}
+#define BLACK (0x01800180) /* black pixel pattern */
+#define BLUE (0x296E29F0) /* blue pixel pattern */
+#define RED (0x51F0515A) /* red pixel pattern */
+#define MAGENTA (0x6ADE6ACA) /* magenta pixel pattern*/
+#define GREEN (0x91229136) /* green pixel pattern */
+#define CYAN (0xAA10AAA6) /* cyan pixel pattern */
+#define YELLOW (0xD292D210) /* yellow pixel pattern */
+#define WHITE (0xFE80FE80) /* white pixel pattern */
+
+#define true 1
+#define false 0
+
+typedef struct {
+ unsigned int SAV;
+ unsigned int EAV;
+} SystemCodeType;
+
+const SystemCodeType SystemCodeMap[4] = {
+ {0xFF000080, 0xFF00009D},
+ {0xFF0000AB, 0xFF0000B6},
+ {0xFF0000C7, 0xFF0000DA},
+ {0xFF0000EC, 0xFF0000F1}
+};
endif
ifeq ($(ARCH),blackfin)
+ifneq ($(BOARD),bf537-stamp)
+ifneq ($(BOARD),bf537-pnav)
ELF += smc91111_eeprom
SREC += smc91111_eeprom.srec
BIN += smc91111_eeprom.bin
endif
+endif
+endif
# The following example is pretty 8xx specific...
ifeq ($(CPU),mpc8xx)
--- /dev/null
+/*
+ * File: include/asm-blackfin/arch-bf537/anomaly.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+/* This file shoule be up to date with:
+ * - Revision J, June 1, 2006; ADSP-BF537 Blackfin Processor Anomaly List
+ * - Revision I, June 1, 2006; ADSP-BF536 Blackfin Processor Anomaly List
+ * - Revision J, June 1, 2006; ADSP-BF534 Blackfin Processor Anomaly List
+ */
+
+#ifndef _MACH_ANOMALY_H_
+#define _MACH_ANOMALY_H_
+
+/* We do not support 0.1 silicon - sorry */
+#if (defined(CONFIG_BF_REV_0_1))
+#error Kernel will not work on BF537/6/4 Version 0.1
+#endif
+
+#if (defined(CONFIG_BF_REV_0_3) || defined(CONFIG_BF_REV_0_2))
+#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
+ slot1 and store of a P register in slot 2 is not
+ supported */
+#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
+ Channel DMA stops */
+#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
+ registers. */
+#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
+ upper bits */
+#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
+ syncs */
+#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
+#define ANOMALY_05000247 /* CLKIN Buffer Output Enable Reset Behavior Is
+ Changed */
+#endif
+#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
+ SPORT external receive and transmit clocks. */
+#define ANOMALY_05000272 /* Certain data cache write through modes fail for
+ VDDint <=0.9V */
+#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */
+#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
+ an edge is detected may clear interrupt */
+#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
+ not restored */
+#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
+ control */
+#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
+ killed in a particular stage */
+#endif
+
+#if defined(CONFIG_BF_REV_0_2)
+#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or
+ IDLE around a Change of Control causes
+ unpredictable results */
+#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
+ (TDM) */
+#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
+#define ANOMALY_05000252 /* EMAC Tx DMA error after an early frame abort */
+#endif
+#define ANOMALY_05000253 /* Maximum external clock speed for Timers */
+#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
+ interrupt not functional */
+#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
+#define ANOMALY_05000256 /* EMAC MDIO input latched on wrong MDC edge */
+#endif
+#define ANOMALY_05000257 /* An interrupt or exception during short Hardware
+ loops may cause the instruction fetch unit to
+ malfunction */
+#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of
+ the ICPLB Data registers differ */
+#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
+#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
+#define ANOMALY_05000262 /* Stores to data cache may be lost */
+#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */
+#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE
+ instruction will cause an infinite stall in the
+ second to last instruction in a hardware loop */
+#define ANOMALY_05000268 /* Memory DMA error when peripheral DMA is running
+ and non-zero DEB_TRAFFIC_PERIOD value */
+#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the
+ internal voltage regulator (VDDint) to decrease */
+#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
+ an edge is detected may clear interrupt */
+#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
+ DMA system instability */
+#define ANOMALY_05000280 /* SPI Master boot mode does not work well with
+ Atmel Dataflash devices */
+
+#endif /* CONFIG_BF_REV_0_2 */
+
+#endif /* _MACH_ANOMALY_H_ */
--- /dev/null
+/*
+ * U-boot bf537_serial.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BF537_SERIAL_H_
+#define _BF537_SERIAL_H_
+
+#define BYTE_REF(addr) (*((volatile char*)addr))
+#define HALFWORD_REF(addr) (*((volatile short*)addr))
+#define WORD_REF(addr) (*((volatile long*)addr))
+
+#define UART_THR_LO HALFWORD_REF(UART_THR)
+#define UART_RBR_LO HALFWORD_REF(UART_RBR)
+#define UART_DLL_LO HALFWORD_REF(UART_DLL)
+#define UART_IER_LO HALFWORD_REF(UART_IER)
+#define UART_IER_ERBFI 0x01
+#define UART_IER_ETBEI 0x02
+#define UART_IER_ELSI 0x04
+#define UART_IER_EDDSI 0x08
+
+#define UART_DLH_LO HALFWORD_REF(UART_DLH)
+#define UART_IIR_LO HALFWORD_REF(UART_IIR)
+#define UART_IIR_NOINT 0x01
+#define UART_IIR_STATUS 0x06
+#define UART_IIR_LSR 0x06
+#define UART_IIR_RBR 0x04
+#define UART_IIR_THR 0x02
+#define UART_IIR_MSR 0x00
+
+#define UART_LCR_LO HALFWORD_REF(UART_LCR)
+#define UART_LCR_WLS5 0
+#define UART_LCR_WLS6 0x01
+#define UART_LCR_WLS7 0x02
+#define UART_LCR_WLS8 0x03
+#define UART_LCR_STB 0x04
+#define UART_LCR_PEN 0x08
+#define UART_LCR_EPS 0x10
+#define UART_LCR_SP 0x20
+#define UART_LCR_SB 0x40
+#define UART_LCR_DLAB 0x80
+
+#define UART_MCR_LO HALFWORD_REF(UART_MCR)
+
+#define UART_LSR_LO HALFWORD_REF(UART_LSR)
+#define UART_LSR_DR 0x01
+#define UART_LSR_OE 0x02
+#define UART_LSR_PE 0x04
+#define UART_LSR_FE 0x08
+#define UART_LSR_BI 0x10
+#define UART_LSR_THRE 0x20
+#define UART_LSR_TEMT 0x40
+
+#define UART_MSR_LO HALFWORD_REF(UART_MSR)
+#define UART_SCR_LO HALFWORD_REF(UART_SCR)
+#define UART_GCTL_LO HALFWORD_REF(UART_GCTL)
+#define UART_GCTL_UCEN 0x01
+
+#endif
--- /dev/null
+/*
+ * U-boot - bf537_rtc.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BF537_RTC_H_
+#define _BF537_RTC_H_
+
+void rtc_init(void);
+void wait_for_complete(void);
+void rtc_reset(void);
+
+#define MIN_TO_SECS(_x_) (60 * _x_)
+#define HRS_TO_SECS(_x_) (60 * 60 * _x_)
+#define DAYS_TO_SECS(_x_) (24 * 60 * 60 * _x_)
+
+#define NUM_SECS_IN_DAY (24 * 3600)
+#define NUM_SECS_IN_HOUR (3600)
+#define NUM_SECS_IN_MIN (60)
+
+/* Shift values for RTC_STAT register */
+#define DAY_BITS_OFF 17
+#define HOUR_BITS_OFF 12
+#define MIN_BITS_OFF 6
+#define SEC_BITS_OFF 0
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2005 Analog Devices Inc., All Rights Reserved.
+ *
+ ***********************************************************************************
+ *
+ * This include file contains a list of macro "defines" to enable the programmer
+ * to use symbolic names for register-access.
+ *
+ * ----------------------------
+ * revision 0.1
+ * date: 2005/01/27 14:31:01; author: joeb
+ * Initial revision
+ */
+
+/*
+ * System MMR Register Map
+ */
+
+#ifndef _CDEF_BF534_H
+#define _CDEF_BF534_H
+
+/* Include all Core registers and bit definitions */
+#include <asm/arch-bf537/defBF534.h>
+
+/* Include core specific register pointer definitions */
+#include <asm/arch-common/cdef_LPBlackfin.h>
+
+#define pCHIPID ((volatile unsigned long *)CHIPID)
+
+/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
+#define pPLL_CTL ((volatile unsigned short *)PLL_CTL)
+#define pPLL_DIV ((volatile unsigned short *)PLL_DIV)
+#define pVR_CTL ((volatile unsigned short *)VR_CTL)
+#define pPLL_STAT ((volatile unsigned short *)PLL_STAT)
+#define pPLL_LOCKCNT ((volatile unsigned short *)PLL_LOCKCNT)
+
+/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
+#define pSWRST ((volatile unsigned short *)SWRST)
+#define pSYSCR ((volatile unsigned short *)SYSCR)
+#define pSIC_RVECT ((void * volatile *)SIC_RVECT)
+#define pSIC_IMASK ((volatile unsigned long *)SIC_IMASK)
+#define pSIC_IAR0 ((volatile unsigned long *)SIC_IAR0)
+#define pSIC_IAR1 ((volatile unsigned long *)SIC_IAR1)
+#define pSIC_IAR2 ((volatile unsigned long *)SIC_IAR2)
+#define pSIC_IAR3 ((volatile unsigned long *)SIC_IAR3)
+#define pSIC_ISR ((volatile unsigned long *)SIC_ISR)
+#define pSIC_IWR ((volatile unsigned long *)SIC_IWR)
+
+/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
+#define pWDOG_CTL ((volatile unsigned short *)WDOG_CTL)
+#define pWDOG_CNT ((volatile unsigned long *)WDOG_CNT)
+#define pWDOG_STAT ((volatile unsigned long *)WDOG_STAT)
+
+/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
+#define pRTC_STAT ((volatile unsigned long *)RTC_STAT)
+#define pRTC_ICTL ((volatile unsigned short *)RTC_ICTL)
+#define pRTC_ISTAT ((volatile unsigned short *)RTC_ISTAT)
+#define pRTC_SWCNT ((volatile unsigned short *)RTC_SWCNT)
+#define pRTC_ALARM ((volatile unsigned long *)RTC_ALARM)
+#define pRTC_FAST ((volatile unsigned short *)RTC_FAST)
+#define pRTC_PREN ((volatile unsigned short *)RTC_PREN)
+
+/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
+#define pUART0_THR ((volatile unsigned short *)UART0_THR)
+#define pUART0_RBR ((volatile unsigned short *)UART0_RBR)
+#define pUART0_DLL ((volatile unsigned short *)UART0_DLL)
+#define pUART0_IER ((volatile unsigned short *)UART0_IER)
+#define pUART0_DLH ((volatile unsigned short *)UART0_DLH)
+#define pUART0_IIR ((volatile unsigned short *)UART0_IIR)
+#define pUART0_LCR ((volatile unsigned short *)UART0_LCR)
+#define pUART0_MCR ((volatile unsigned short *)UART0_MCR)
+#define pUART0_LSR ((volatile unsigned short *)UART0_LSR)
+#define pUART0_MSR ((volatile unsigned short *)UART0_LSR)
+#define pUART0_SCR ((volatile unsigned short *)UART0_SCR)
+#define pUART0_GCTL ((volatile unsigned short *)UART0_GCTL)
+
+/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
+#define pSPI_CTL ((volatile unsigned short *)SPI_CTL)
+#define pSPI_FLG ((volatile unsigned short *)SPI_FLG)
+#define pSPI_STAT ((volatile unsigned short *)SPI_STAT)
+#define pSPI_TDBR ((volatile unsigned short *)SPI_TDBR)
+#define pSPI_RDBR ((volatile unsigned short *)SPI_RDBR)
+#define pSPI_BAUD ((volatile unsigned short *)SPI_BAUD)
+#define pSPI_SHADOW ((volatile unsigned short *)SPI_SHADOW)
+
+/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
+#define pTIMER0_CONFIG ((volatile unsigned short *)TIMER0_CONFIG)
+#define pTIMER0_COUNTER ((volatile unsigned long *)TIMER0_COUNTER)
+#define pTIMER0_PERIOD ((volatile unsigned long *)TIMER0_PERIOD)
+#define pTIMER0_WIDTH ((volatile unsigned long *)TIMER0_WIDTH)
+
+#define pTIMER1_CONFIG ((volatile unsigned short *)TIMER1_CONFIG)
+#define pTIMER1_COUNTER ((volatile unsigned long *)TIMER1_COUNTER)
+#define pTIMER1_PERIOD ((volatile unsigned long *)TIMER1_PERIOD)
+#define pTIMER1_WIDTH ((volatile unsigned long *)TIMER1_WIDTH)
+
+#define pTIMER2_CONFIG ((volatile unsigned short *)TIMER2_CONFIG)
+#define pTIMER2_COUNTER ((volatile unsigned long *)TIMER2_COUNTER)
+#define pTIMER2_PERIOD ((volatile unsigned long *)TIMER2_PERIOD)
+#define pTIMER2_WIDTH ((volatile unsigned long *)TIMER2_WIDTH)
+
+#define pTIMER3_CONFIG ((volatile unsigned short *)TIMER3_CONFIG)
+#define pTIMER3_COUNTER ((volatile unsigned long *)TIMER3_COUNTER)
+#define pTIMER3_PERIOD ((volatile unsigned long *)TIMER3_PERIOD)
+#define pTIMER3_WIDTH ((volatile unsigned long *)TIMER3_WIDTH)
+
+#define pTIMER4_CONFIG ((volatile unsigned short *)TIMER4_CONFIG)
+#define pTIMER4_COUNTER ((volatile unsigned long *)TIMER4_COUNTER)
+#define pTIMER4_PERIOD ((volatile unsigned long *)TIMER4_PERIOD)
+#define pTIMER4_WIDTH ((volatile unsigned long *)TIMER4_WIDTH)
+
+#define pTIMER5_CONFIG ((volatile unsigned short *)TIMER5_CONFIG)
+#define pTIMER5_COUNTER ((volatile unsigned long *)TIMER5_COUNTER)
+#define pTIMER5_PERIOD ((volatile unsigned long *)TIMER5_PERIOD)
+#define pTIMER5_WIDTH ((volatile unsigned long *)TIMER5_WIDTH)
+
+#define pTIMER6_CONFIG ((volatile unsigned short *)TIMER6_CONFIG)
+#define pTIMER6_COUNTER ((volatile unsigned long *)TIMER6_COUNTER)
+#define pTIMER6_PERIOD ((volatile unsigned long *)TIMER6_PERIOD)
+#define pTIMER6_WIDTH ((volatile unsigned long *)TIMER6_WIDTH)
+
+#define pTIMER7_CONFIG ((volatile unsigned short *)TIMER7_CONFIG)
+#define pTIMER7_COUNTER ((volatile unsigned long *)TIMER7_COUNTER)
+#define pTIMER7_PERIOD ((volatile unsigned long *)TIMER7_PERIOD)
+#define pTIMER7_WIDTH ((volatile unsigned long *)TIMER7_WIDTH)
+
+#define pTIMER_ENABLE ((volatile unsigned short *)TIMER_ENABLE)
+#define pTIMER_DISABLE ((volatile unsigned short *)TIMER_DISABLE)
+#define pTIMER_STATUS ((volatile unsigned long *)TIMER_STATUS)
+
+/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
+#define pPORTFIO ((volatile unsigned short *)PORTFIO)
+#define pPORTFIO_CLEAR ((volatile unsigned short *)PORTFIO_CLEAR)
+#define pPORTFIO_SET ((volatile unsigned short *)PORTFIO_SET)
+#define pPORTFIO_TOGGLE ((volatile unsigned short *)PORTFIO_TOGGLE)
+#define pPORTFIO_MASKA ((volatile unsigned short *)PORTFIO_MASKA)
+#define pPORTFIO_MASKA_CLEAR ((volatile unsigned short *)PORTFIO_MASKA_CLEAR)
+#define pPORTFIO_MASKA_SET ((volatile unsigned short *)PORTFIO_MASKA_SET)
+#define pPORTFIO_MASKA_TOGGLE ((volatile unsigned short *)PORTFIO_MASKA_TOGGLE)
+#define pPORTFIO_MASKB ((volatile unsigned short *)PORTFIO_MASKB)
+#define pPORTFIO_MASKB_CLEAR ((volatile unsigned short *)PORTFIO_MASKB_CLEAR)
+#define pPORTFIO_MASKB_SET ((volatile unsigned short *)PORTFIO_MASKB_SET)
+#define pPORTFIO_MASKB_TOGGLE ((volatile unsigned short *)PORTFIO_MASKB_TOGGLE)
+#define pPORTFIO_DIR ((volatile unsigned short *)PORTFIO_DIR)
+#define pPORTFIO_POLAR ((volatile unsigned short *)PORTFIO_POLAR)
+#define pPORTFIO_EDGE ((volatile unsigned short *)PORTFIO_EDGE)
+#define pPORTFIO_BOTH ((volatile unsigned short *)PORTFIO_BOTH)
+#define pPORTFIO_INEN ((volatile unsigned short *)PORTFIO_INEN)
+
+#define pFIO_DIR pPORTFIO_DIR
+#define pFIO_FLAG_C pPORTFIO_CLEAR
+#define pFIO_FLAG_S pPORTFIO_SET
+#define pFIO_INEN pPORTFIO_INEN
+#define pFIO_FLAG_D pPORTFIO
+
+/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
+#define pSPORT0_TCR1 ((volatile unsigned short *)SPORT0_TCR1)
+#define pSPORT0_TCR2 ((volatile unsigned short *)SPORT0_TCR2)
+#define pSPORT0_TCLKDIV ((volatile unsigned short *)SPORT0_TCLKDIV)
+#define pSPORT0_TFSDIV ((volatile unsigned short *)SPORT0_TFSDIV)
+#define pSPORT0_TX ((volatile unsigned long *)SPORT0_TX)
+#define pSPORT0_RX ((volatile unsigned long *)SPORT0_RX)
+#define pSPORT0_TX32 ((volatile unsigned long *)SPORT0_TX)
+#define pSPORT0_RX32 ((volatile unsigned long *)SPORT0_RX)
+#define pSPORT0_TX16 ((volatile unsigned short *)SPORT0_TX)
+#define pSPORT0_RX16 ((volatile unsigned short *)SPORT0_RX)
+#define pSPORT0_RCR1 ((volatile unsigned short *)SPORT0_RCR1)
+#define pSPORT0_RCR2 ((volatile unsigned short *)SPORT0_RCR2)
+#define pSPORT0_RCLKDIV ((volatile unsigned short *)SPORT0_RCLKDIV)
+#define pSPORT0_RFSDIV ((volatile unsigned short *)SPORT0_RFSDIV)
+#define pSPORT0_STAT ((volatile unsigned short *)SPORT0_STAT)
+#define pSPORT0_CHNL ((volatile unsigned short *)SPORT0_CHNL)
+#define pSPORT0_MCMC1 ((volatile unsigned short *)SPORT0_MCMC1)
+#define pSPORT0_MCMC2 ((volatile unsigned short *)SPORT0_MCMC2)
+#define pSPORT0_MTCS0 ((volatile unsigned long *)SPORT0_MTCS0)
+#define pSPORT0_MTCS1 ((volatile unsigned long *)SPORT0_MTCS1)
+#define pSPORT0_MTCS2 ((volatile unsigned long *)SPORT0_MTCS2)
+#define pSPORT0_MTCS3 ((volatile unsigned long *)SPORT0_MTCS3)
+#define pSPORT0_MRCS0 ((volatile unsigned long *)SPORT0_MRCS0)
+#define pSPORT0_MRCS1 ((volatile unsigned long *)SPORT0_MRCS1)
+#define pSPORT0_MRCS2 ((volatile unsigned long *)SPORT0_MRCS2)
+#define pSPORT0_MRCS3 ((volatile unsigned long *)SPORT0_MRCS3)
+
+/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
+#define pSPORT1_TCR1 ((volatile unsigned short *)SPORT1_TCR1)
+#define pSPORT1_TCR2 ((volatile unsigned short *)SPORT1_TCR2)
+#define pSPORT1_TCLKDIV ((volatile unsigned short *)SPORT1_TCLKDIV)
+#define pSPORT1_TFSDIV ((volatile unsigned short *)SPORT1_TFSDIV)
+#define pSPORT1_TX ((volatile unsigned long *)SPORT1_TX)
+#define pSPORT1_RX ((volatile unsigned long *)SPORT1_RX)
+#define pSPORT1_TX32 ((volatile unsigned long *)SPORT1_TX)
+#define pSPORT1_RX32 ((volatile unsigned long *)SPORT1_RX)
+#define pSPORT1_TX16 ((volatile unsigned short *)SPORT1_TX)
+#define pSPORT1_RX16 ((volatile unsigned short *)SPORT1_RX)
+#define pSPORT1_RCR1 ((volatile unsigned short *)SPORT1_RCR1)
+#define pSPORT1_RCR2 ((volatile unsigned short *)SPORT1_RCR2)
+#define pSPORT1_RCLKDIV ((volatile unsigned short *)SPORT1_RCLKDIV)
+#define pSPORT1_RFSDIV ((volatile unsigned short *)SPORT1_RFSDIV)
+#define pSPORT1_STAT ((volatile unsigned short *)SPORT1_STAT)
+#define pSPORT1_CHNL ((volatile unsigned short *)SPORT1_CHNL)
+#define pSPORT1_MCMC1 ((volatile unsigned short *)SPORT1_MCMC1)
+#define pSPORT1_MCMC2 ((volatile unsigned short *)SPORT1_MCMC2)
+#define pSPORT1_MTCS0 ((volatile unsigned long *)SPORT1_MTCS0)
+#define pSPORT1_MTCS1 ((volatile unsigned long *)SPORT1_MTCS1)
+#define pSPORT1_MTCS2 ((volatile unsigned long *)SPORT1_MTCS2)
+#define pSPORT1_MTCS3 ((volatile unsigned long *)SPORT1_MTCS3)
+#define pSPORT1_MRCS0 ((volatile unsigned long *)SPORT1_MRCS0)
+#define pSPORT1_MRCS1 ((volatile unsigned long *)SPORT1_MRCS1)
+#define pSPORT1_MRCS2 ((volatile unsigned long *)SPORT1_MRCS2)
+#define pSPORT1_MRCS3 ((volatile unsigned long *)SPORT1_MRCS3)
+
+/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
+#define pEBIU_AMGCTL ((volatile unsigned short *)EBIU_AMGCTL)
+#define pEBIU_AMBCTL0 ((volatile unsigned long *)EBIU_AMBCTL0)
+#define pEBIU_AMBCTL1 ((volatile unsigned long *)EBIU_AMBCTL1)
+#define pEBIU_SDGCTL ((volatile unsigned long *)EBIU_SDGCTL)
+#define pEBIU_SDBCTL ((volatile unsigned short *)EBIU_SDBCTL)
+#define pEBIU_SDRRC ((volatile unsigned short *)EBIU_SDRRC)
+#define pEBIU_SDSTAT ((volatile unsigned short *)EBIU_SDSTAT)
+
+/* DMA Traffic Control Registers */
+#define pDMA_TCPER ((volatile unsigned short *)DMA_TCPER)
+#define pDMA_TCCNT ((volatile unsigned short *)DMA_TCCNT)
+
+/* DMA Controller */
+#define pDMA0_CONFIG ((volatile unsigned short *)DMA0_CONFIG)
+#define pDMA0_NEXT_DESC_PTR ((void * volatile *)DMA0_NEXT_DESC_PTR)
+#define pDMA0_START_ADDR ((void * volatile *)DMA0_START_ADDR)
+#define pDMA0_X_COUNT ((volatile unsigned short *)DMA0_X_COUNT)
+#define pDMA0_Y_COUNT ((volatile unsigned short *)DMA0_Y_COUNT)
+#define pDMA0_X_MODIFY ((volatile signed short *)DMA0_X_MODIFY)
+#define pDMA0_Y_MODIFY ((volatile signed short *)DMA0_Y_MODIFY)
+#define pDMA0_CURR_DESC_PTR ((void * volatile *)DMA0_CURR_DESC_PTR)
+#define pDMA0_CURR_ADDR ((void * volatile *)DMA0_CURR_ADDR)
+#define pDMA0_CURR_X_COUNT ((volatile unsigned short *)DMA0_CURR_X_COUNT)
+#define pDMA0_CURR_Y_COUNT ((volatile unsigned short *)DMA0_CURR_Y_COUNT)
+#define pDMA0_IRQ_STATUS ((volatile unsigned short *)DMA0_IRQ_STATUS)
+#define pDMA0_PERIPHERAL_MAP ((volatile unsigned short *)DMA0_PERIPHERAL_MAP)
+
+#define pDMA1_CONFIG ((volatile unsigned short *)DMA1_CONFIG)
+#define pDMA1_NEXT_DESC_PTR ((void * volatile *)DMA1_NEXT_DESC_PTR)
+#define pDMA1_START_ADDR ((void * volatile *)DMA1_START_ADDR)
+#define pDMA1_X_COUNT ((volatile unsigned short *)DMA1_X_COUNT)
+#define pDMA1_Y_COUNT ((volatile unsigned short *)DMA1_Y_COUNT)
+#define pDMA1_X_MODIFY ((volatile signed short *)DMA1_X_MODIFY)
+#define pDMA1_Y_MODIFY ((volatile signed short *)DMA1_Y_MODIFY)
+#define pDMA1_CURR_DESC_PTR ((void * volatile *)DMA1_CURR_DESC_PTR)
+#define pDMA1_CURR_ADDR ((void * volatile *)DMA1_CURR_ADDR)
+#define pDMA1_CURR_X_COUNT ((volatile unsigned short *)DMA1_CURR_X_COUNT)
+#define pDMA1_CURR_Y_COUNT ((volatile unsigned short *)DMA1_CURR_Y_COUNT)
+#define pDMA1_IRQ_STATUS ((volatile unsigned short *)DMA1_IRQ_STATUS)
+#define pDMA1_PERIPHERAL_MAP ((volatile unsigned short *)DMA1_PERIPHERAL_MAP)
+
+#define pDMA2_CONFIG ((volatile unsigned short *)DMA2_CONFIG)
+#define pDMA2_NEXT_DESC_PTR ((void * volatile *)DMA2_NEXT_DESC_PTR)
+#define pDMA2_START_ADDR ((void * volatile *)DMA2_START_ADDR)
+#define pDMA2_X_COUNT ((volatile unsigned short *)DMA2_X_COUNT)
+#define pDMA2_Y_COUNT ((volatile unsigned short *)DMA2_Y_COUNT)
+#define pDMA2_X_MODIFY ((volatile signed short *)DMA2_X_MODIFY)
+#define pDMA2_Y_MODIFY ((volatile signed short *)DMA2_Y_MODIFY)
+#define pDMA2_CURR_DESC_PTR ((void * volatile *)DMA2_CURR_DESC_PTR)
+#define pDMA2_CURR_ADDR ((void * volatile *)DMA2_CURR_ADDR)
+#define pDMA2_CURR_X_COUNT ((volatile unsigned short *)DMA2_CURR_X_COUNT)
+#define pDMA2_CURR_Y_COUNT ((volatile unsigned short *)DMA2_CURR_Y_COUNT)
+#define pDMA2_IRQ_STATUS ((volatile unsigned short *)DMA2_IRQ_STATUS)
+#define pDMA2_PERIPHERAL_MAP ((volatile unsigned short *)DMA2_PERIPHERAL_MAP)
+
+#define pDMA3_CONFIG ((volatile unsigned short *)DMA3_CONFIG)
+#define pDMA3_NEXT_DESC_PTR ((void * volatile *)DMA3_NEXT_DESC_PTR)
+#define pDMA3_START_ADDR ((void * volatile *)DMA3_START_ADDR)
+#define pDMA3_X_COUNT ((volatile unsigned short *)DMA3_X_COUNT)
+#define pDMA3_Y_COUNT ((volatile unsigned short *)DMA3_Y_COUNT)
+#define pDMA3_X_MODIFY ((volatile signed short *)DMA3_X_MODIFY)
+#define pDMA3_Y_MODIFY ((volatile signed short *)DMA3_Y_MODIFY)
+#define pDMA3_CURR_DESC_PTR ((void * volatile *)DMA3_CURR_DESC_PTR)
+#define pDMA3_CURR_ADDR ((void * volatile *)DMA3_CURR_ADDR)
+#define pDMA3_CURR_X_COUNT ((volatile unsigned short *)DMA3_CURR_X_COUNT)
+#define pDMA3_CURR_Y_COUNT ((volatile unsigned short *)DMA3_CURR_Y_COUNT)
+#define pDMA3_IRQ_STATUS ((volatile unsigned short *)DMA3_IRQ_STATUS)
+#define pDMA3_PERIPHERAL_MAP ((volatile unsigned short *)DMA3_PERIPHERAL_MAP)
+
+#define pDMA4_CONFIG ((volatile unsigned short *)DMA4_CONFIG)
+#define pDMA4_NEXT_DESC_PTR ((void * volatile *)DMA4_NEXT_DESC_PTR)
+#define pDMA4_START_ADDR ((void * volatile *)DMA4_START_ADDR)
+#define pDMA4_X_COUNT ((volatile unsigned short *)DMA4_X_COUNT)
+#define pDMA4_Y_COUNT ((volatile unsigned short *)DMA4_Y_COUNT)
+#define pDMA4_X_MODIFY ((volatile signed short *)DMA4_X_MODIFY)
+#define pDMA4_Y_MODIFY ((volatile signed short *)DMA4_Y_MODIFY)
+#define pDMA4_CURR_DESC_PTR ((void * volatile *)DMA4_CURR_DESC_PTR)
+#define pDMA4_CURR_ADDR ((void * volatile *)DMA4_CURR_ADDR)
+#define pDMA4_CURR_X_COUNT ((volatile unsigned short *)DMA4_CURR_X_COUNT)
+#define pDMA4_CURR_Y_COUNT ((volatile unsigned short *)DMA4_CURR_Y_COUNT)
+#define pDMA4_IRQ_STATUS ((volatile unsigned short *)DMA4_IRQ_STATUS)
+#define pDMA4_PERIPHERAL_MAP ((volatile unsigned short *)DMA4_PERIPHERAL_MAP)
+
+#define pDMA5_CONFIG ((volatile unsigned short *)DMA5_CONFIG)
+#define pDMA5_NEXT_DESC_PTR ((void * volatile *)DMA5_NEXT_DESC_PTR)
+#define pDMA5_START_ADDR ((void * volatile *)DMA5_START_ADDR)
+#define pDMA5_X_COUNT ((volatile unsigned short *)DMA5_X_COUNT)
+#define pDMA5_Y_COUNT ((volatile unsigned short *)DMA5_Y_COUNT)
+#define pDMA5_X_MODIFY ((volatile signed short *)DMA5_X_MODIFY)
+#define pDMA5_Y_MODIFY ((volatile signed short *)DMA5_Y_MODIFY)
+#define pDMA5_CURR_DESC_PTR ((void * volatile *)DMA5_CURR_DESC_PTR)
+#define pDMA5_CURR_ADDR ((void * volatile *)DMA5_CURR_ADDR)
+#define pDMA5_CURR_X_COUNT ((volatile unsigned short *)DMA5_CURR_X_COUNT)
+#define pDMA5_CURR_Y_COUNT ((volatile unsigned short *)DMA5_CURR_Y_COUNT)
+#define pDMA5_IRQ_STATUS ((volatile unsigned short *)DMA5_IRQ_STATUS)
+#define pDMA5_PERIPHERAL_MAP ((volatile unsigned short *)DMA5_PERIPHERAL_MAP)
+
+#define pDMA6_CONFIG ((volatile unsigned short *)DMA6_CONFIG)
+#define pDMA6_NEXT_DESC_PTR ((void * volatile *)DMA6_NEXT_DESC_PTR)
+#define pDMA6_START_ADDR ((void * volatile *)DMA6_START_ADDR)
+#define pDMA6_X_COUNT ((volatile unsigned short *)DMA6_X_COUNT)
+#define pDMA6_Y_COUNT ((volatile unsigned short *)DMA6_Y_COUNT)
+#define pDMA6_X_MODIFY ((volatile signed short *)DMA6_X_MODIFY)
+#define pDMA6_Y_MODIFY ((volatile signed short *)DMA6_Y_MODIFY)
+#define pDMA6_CURR_DESC_PTR ((void * volatile *)DMA6_CURR_DESC_PTR)
+#define pDMA6_CURR_ADDR ((void * volatile *)DMA6_CURR_ADDR)
+#define pDMA6_CURR_X_COUNT ((volatile unsigned short *)DMA6_CURR_X_COUNT)
+#define pDMA6_CURR_Y_COUNT ((volatile unsigned short *)DMA6_CURR_Y_COUNT)
+#define pDMA6_IRQ_STATUS ((volatile unsigned short *)DMA6_IRQ_STATUS)
+#define pDMA6_PERIPHERAL_MAP ((volatile unsigned short *)DMA6_PERIPHERAL_MAP)
+
+#define pDMA7_CONFIG ((volatile unsigned short *)DMA7_CONFIG)
+#define pDMA7_NEXT_DESC_PTR ((void * volatile *)DMA7_NEXT_DESC_PTR)
+#define pDMA7_START_ADDR ((void * volatile *)DMA7_START_ADDR)
+#define pDMA7_X_COUNT ((volatile unsigned short *)DMA7_X_COUNT)
+#define pDMA7_Y_COUNT ((volatile unsigned short *)DMA7_Y_COUNT)
+#define pDMA7_X_MODIFY ((volatile signed short *)DMA7_X_MODIFY)
+#define pDMA7_Y_MODIFY ((volatile signed short *)DMA7_Y_MODIFY)
+#define pDMA7_CURR_DESC_PTR ((void * volatile *)DMA7_CURR_DESC_PTR)
+#define pDMA7_CURR_ADDR ((void * volatile *)DMA7_CURR_ADDR)
+#define pDMA7_CURR_X_COUNT ((volatile unsigned short *)DMA7_CURR_X_COUNT)
+#define pDMA7_CURR_Y_COUNT ((volatile unsigned short *)DMA7_CURR_Y_COUNT)
+#define pDMA7_IRQ_STATUS ((volatile unsigned short *)DMA7_IRQ_STATUS)
+#define pDMA7_PERIPHERAL_MAP ((volatile unsigned short *)DMA7_PERIPHERAL_MAP)
+
+#define pDMA8_CONFIG ((volatile unsigned short *)DMA8_CONFIG)
+#define pDMA8_NEXT_DESC_PTR ((void * volatile *)DMA8_NEXT_DESC_PTR)
+#define pDMA8_START_ADDR ((void * volatile *)DMA8_START_ADDR)
+#define pDMA8_X_COUNT ((volatile unsigned short *)DMA8_X_COUNT)
+#define pDMA8_Y_COUNT ((volatile unsigned short *)DMA8_Y_COUNT)
+#define pDMA8_X_MODIFY ((volatile signed short *)DMA8_X_MODIFY)
+#define pDMA8_Y_MODIFY ((volatile signed short *)DMA8_Y_MODIFY)
+#define pDMA8_CURR_DESC_PTR ((void * volatile *)DMA8_CURR_DESC_PTR)
+#define pDMA8_CURR_ADDR ((void * volatile *)DMA8_CURR_ADDR)
+#define pDMA8_CURR_X_COUNT ((volatile unsigned short *)DMA8_CURR_X_COUNT)
+#define pDMA8_CURR_Y_COUNT ((volatile unsigned short *)DMA8_CURR_Y_COUNT)
+#define pDMA8_IRQ_STATUS ((volatile unsigned short *)DMA8_IRQ_STATUS)
+#define pDMA8_PERIPHERAL_MAP ((volatile unsigned short *)DMA8_PERIPHERAL_MAP)
+
+#define pDMA9_CONFIG ((volatile unsigned short *)DMA9_CONFIG)
+#define pDMA9_NEXT_DESC_PTR ((void * volatile *)DMA9_NEXT_DESC_PTR)
+#define pDMA9_START_ADDR ((void * volatile *)DMA9_START_ADDR)
+#define pDMA9_X_COUNT ((volatile unsigned short *)DMA9_X_COUNT)
+#define pDMA9_Y_COUNT ((volatile unsigned short *)DMA9_Y_COUNT)
+#define pDMA9_X_MODIFY ((volatile signed short *)DMA9_X_MODIFY)
+#define pDMA9_Y_MODIFY ((volatile signed short *)DMA9_Y_MODIFY)
+#define pDMA9_CURR_DESC_PTR ((void * volatile *)DMA9_CURR_DESC_PTR)
+#define pDMA9_CURR_ADDR ((void * volatile *)DMA9_CURR_ADDR)
+#define pDMA9_CURR_X_COUNT ((volatile unsigned short *)DMA9_CURR_X_COUNT)
+#define pDMA9_CURR_Y_COUNT ((volatile unsigned short *)DMA9_CURR_Y_COUNT)
+#define pDMA9_IRQ_STATUS ((volatile unsigned short *)DMA9_IRQ_STATUS)
+#define pDMA9_PERIPHERAL_MAP ((volatile unsigned short *)DMA9_PERIPHERAL_MAP)
+
+#define pDMA10_CONFIG ((volatile unsigned short *)DMA10_CONFIG)
+#define pDMA10_NEXT_DESC_PTR ((void * volatile *)DMA10_NEXT_DESC_PTR)
+#define pDMA10_START_ADDR ((void * volatile *)DMA10_START_ADDR)
+#define pDMA10_X_COUNT ((volatile unsigned short *)DMA10_X_COUNT)
+#define pDMA10_Y_COUNT ((volatile unsigned short *)DMA10_Y_COUNT)
+#define pDMA10_X_MODIFY ((volatile signed short *)DMA10_X_MODIFY)
+#define pDMA10_Y_MODIFY ((volatile signed short *)DMA10_Y_MODIFY)
+#define pDMA10_CURR_DESC_PTR ((void * volatile *)DMA10_CURR_DESC_PTR)
+#define pDMA10_CURR_ADDR ((void * volatile *)DMA10_CURR_ADDR)
+#define pDMA10_CURR_X_COUNT ((volatile unsigned short *)DMA10_CURR_X_COUNT)
+#define pDMA10_CURR_Y_COUNT ((volatile unsigned short *)DMA10_CURR_Y_COUNT)
+#define pDMA10_IRQ_STATUS ((volatile unsigned short *)DMA10_IRQ_STATUS)
+#define pDMA10_PERIPHERAL_MAP ((volatile unsigned short *)DMA10_PERIPHERAL_MAP)
+
+#define pDMA11_CONFIG ((volatile unsigned short *)DMA11_CONFIG)
+#define pDMA11_NEXT_DESC_PTR ((void * volatile *)DMA11_NEXT_DESC_PTR)
+#define pDMA11_START_ADDR ((void * volatile *)DMA11_START_ADDR)
+#define pDMA11_X_COUNT ((volatile unsigned short *)DMA11_X_COUNT)
+#define pDMA11_Y_COUNT ((volatile unsigned short *)DMA11_Y_COUNT)
+#define pDMA11_X_MODIFY ((volatile signed short *)DMA11_X_MODIFY)
+#define pDMA11_Y_MODIFY ((volatile signed short *)DMA11_Y_MODIFY)
+#define pDMA11_CURR_DESC_PTR ((void * volatile *)DMA11_CURR_DESC_PTR)
+#define pDMA11_CURR_ADDR ((void * volatile *)DMA11_CURR_ADDR)
+#define pDMA11_CURR_X_COUNT ((volatile unsigned short *)DMA11_CURR_X_COUNT)
+#define pDMA11_CURR_Y_COUNT ((volatile unsigned short *)DMA11_CURR_Y_COUNT)
+#define pDMA11_IRQ_STATUS ((volatile unsigned short *)DMA11_IRQ_STATUS)
+#define pDMA11_PERIPHERAL_MAP ((volatile unsigned short *)DMA11_PERIPHERAL_MAP)
+
+#define pMDMA_D0_CONFIG ((volatile unsigned short *)MDMA_D0_CONFIG)
+#define pMDMA_D0_NEXT_DESC_PTR ((void * volatile *)MDMA_D0_NEXT_DESC_PTR)
+#define pMDMA_D0_START_ADDR ((void * volatile *)MDMA_D0_START_ADDR)
+#define pMDMA_D0_X_COUNT ((volatile unsigned short *)MDMA_D0_X_COUNT)
+#define pMDMA_D0_Y_COUNT ((volatile unsigned short *)MDMA_D0_Y_COUNT)
+#define pMDMA_D0_X_MODIFY ((volatile signed short *)MDMA_D0_X_MODIFY)
+#define pMDMA_D0_Y_MODIFY ((volatile signed short *)MDMA_D0_Y_MODIFY)
+#define pMDMA_D0_CURR_DESC_PTR ((void * volatile *)MDMA_D0_CURR_DESC_PTR)
+#define pMDMA_D0_CURR_ADDR ((void * volatile *)MDMA_D0_CURR_ADDR)
+#define pMDMA_D0_CURR_X_COUNT ((volatile unsigned short *)MDMA_D0_CURR_X_COUNT)
+#define pMDMA_D0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D0_CURR_Y_COUNT)
+#define pMDMA_D0_IRQ_STATUS ((volatile unsigned short *)MDMA_D0_IRQ_STATUS)
+#define pMDMA_D0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D0_PERIPHERAL_MAP)
+
+#define pMDMA_S0_CONFIG ((volatile unsigned short *)MDMA_S0_CONFIG)
+#define pMDMA_S0_NEXT_DESC_PTR ((void * volatile *)MDMA_S0_NEXT_DESC_PTR)
+#define pMDMA_S0_START_ADDR ((void * volatile *)MDMA_S0_START_ADDR)
+#define pMDMA_S0_X_COUNT ((volatile unsigned short *)MDMA_S0_X_COUNT)
+#define pMDMA_S0_Y_COUNT ((volatile unsigned short *)MDMA_S0_Y_COUNT)
+#define pMDMA_S0_X_MODIFY ((volatile signed short *)MDMA_S0_X_MODIFY)
+#define pMDMA_S0_Y_MODIFY ((volatile signed short *)MDMA_S0_Y_MODIFY)
+#define pMDMA_S0_CURR_DESC_PTR ((void * volatile *)MDMA_S0_CURR_DESC_PTR)
+#define pMDMA_S0_CURR_ADDR ((void * volatile *)MDMA_S0_CURR_ADDR)
+#define pMDMA_S0_CURR_X_COUNT ((volatile unsigned short *)MDMA_S0_CURR_X_COUNT)
+#define pMDMA_S0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S0_CURR_Y_COUNT)
+#define pMDMA_S0_IRQ_STATUS ((volatile unsigned short *)MDMA_S0_IRQ_STATUS)
+#define pMDMA_S0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S0_PERIPHERAL_MAP)
+
+#define pMDMA_D1_CONFIG ((volatile unsigned short *)MDMA_D1_CONFIG)
+#define pMDMA_D1_NEXT_DESC_PTR ((void * volatile *)MDMA_D1_NEXT_DESC_PTR)
+#define pMDMA_D1_START_ADDR ((void * volatile *)MDMA_D1_START_ADDR)
+#define pMDMA_D1_X_COUNT ((volatile unsigned short *)MDMA_D1_X_COUNT)
+#define pMDMA_D1_Y_COUNT ((volatile unsigned short *)MDMA_D1_Y_COUNT)
+#define pMDMA_D1_X_MODIFY ((volatile signed short *)MDMA_D1_X_MODIFY)
+#define pMDMA_D1_Y_MODIFY ((volatile signed short *)MDMA_D1_Y_MODIFY)
+#define pMDMA_D1_CURR_DESC_PTR ((void * volatile *)MDMA_D1_CURR_DESC_PTR)
+#define pMDMA_D1_CURR_ADDR ((void * volatile *)MDMA_D1_CURR_ADDR)
+#define pMDMA_D1_CURR_X_COUNT ((volatile unsigned short *)MDMA_D1_CURR_X_COUNT)
+#define pMDMA_D1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D1_CURR_Y_COUNT)
+#define pMDMA_D1_IRQ_STATUS ((volatile unsigned short *)MDMA_D1_IRQ_STATUS)
+#define pMDMA_D1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D1_PERIPHERAL_MAP)
+
+#define pMDMA_S1_CONFIG ((volatile unsigned short *)MDMA_S1_CONFIG)
+#define pMDMA_S1_NEXT_DESC_PTR ((void * volatile *)MDMA_S1_NEXT_DESC_PTR)
+#define pMDMA_S1_START_ADDR ((void * volatile *)MDMA_S1_START_ADDR)
+#define pMDMA_S1_X_COUNT ((volatile unsigned short *)MDMA_S1_X_COUNT)
+#define pMDMA_S1_Y_COUNT ((volatile unsigned short *)MDMA_S1_Y_COUNT)
+#define pMDMA_S1_X_MODIFY ((volatile signed short *)MDMA_S1_X_MODIFY)
+#define pMDMA_S1_Y_MODIFY ((volatile signed short *)MDMA_S1_Y_MODIFY)
+#define pMDMA_S1_CURR_DESC_PTR ((void * volatile *)MDMA_S1_CURR_DESC_PTR)
+#define pMDMA_S1_CURR_ADDR ((void * volatile *)MDMA_S1_CURR_ADDR)
+#define pMDMA_S1_CURR_X_COUNT ((volatile unsigned short *)MDMA_S1_CURR_X_COUNT)
+#define pMDMA_S1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S1_CURR_Y_COUNT)
+#define pMDMA_S1_IRQ_STATUS ((volatile unsigned short *)MDMA_S1_IRQ_STATUS)
+#define pMDMA_S1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S1_PERIPHERAL_MAP)
+
+/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
+#define pPPI_CONTROL ((volatile unsigned short *)PPI_CONTROL)
+#define pPPI_STATUS ((volatile unsigned short *)PPI_STATUS)
+#define pPPI_DELAY ((volatile unsigned short *)PPI_DELAY)
+#define pPPI_COUNT ((volatile unsigned short *)PPI_COUNT)
+#define pPPI_FRAME ((volatile unsigned short *)PPI_FRAME)
+
+/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
+#define pTWI_CLKDIV ((volatile unsigned short *)TWI_CLKDIV)
+#define pTWI_CONTROL ((volatile unsigned short *)TWI_CONTROL)
+#define pTWI_SLAVE_CTL ((volatile unsigned short *)TWI_SLAVE_CTL)
+#define pTWI_SLAVE_STAT ((volatile unsigned short *)TWI_SLAVE_STAT)
+#define pTWI_SLAVE_ADDR ((volatile unsigned short *)TWI_SLAVE_ADDR)
+#define pTWI_MASTER_CTL ((volatile unsigned short *)TWI_MASTER_CTL)
+#define pTWI_MASTER_STAT ((volatile unsigned short *)TWI_MASTER_STAT)
+#define pTWI_MASTER_ADDR ((volatile unsigned short *)TWI_MASTER_ADDR)
+#define pTWI_INT_STAT ((volatile unsigned short *)TWI_INT_STAT)
+#define pTWI_INT_MASK ((volatile unsigned short *)TWI_INT_MASK)
+#define pTWI_FIFO_CTL ((volatile unsigned short *)TWI_FIFO_CTL)
+#define pTWI_FIFO_STAT ((volatile unsigned short *)TWI_FIFO_STAT)
+#define pTWI_XMT_DATA8 ((volatile unsigned short *)TWI_XMT_DATA8)
+#define pTWI_XMT_DATA16 ((volatile unsigned short *)TWI_XMT_DATA16)
+#define pTWI_RCV_DATA8 ((volatile unsigned short *)TWI_RCV_DATA8)
+#define pTWI_RCV_DATA16 ((volatile unsigned short *)TWI_RCV_DATA16)
+
+/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
+#define pPORTGIO ((volatile unsigned short *)PORTGIO)
+#define pPORTGIO_CLEAR ((volatile unsigned short *)PORTGIO_CLEAR)
+#define pPORTGIO_SET ((volatile unsigned short *)PORTGIO_SET)
+#define pPORTGIO_TOGGLE ((volatile unsigned short *)PORTGIO_TOGGLE)
+#define pPORTGIO_MASKA ((volatile unsigned short *)PORTGIO_MASKA)
+#define pPORTGIO_MASKA_CLEAR ((volatile unsigned short *)PORTGIO_MASKA_CLEAR)
+#define pPORTGIO_MASKA_SET ((volatile unsigned short *)PORTGIO_MASKA_SET)
+#define pPORTGIO_MASKA_TOGGLE ((volatile unsigned short *)PORTGIO_MASKA_TOGGLE)
+#define pPORTGIO_MASKB ((volatile unsigned short *)PORTGIO_MASKB)
+#define pPORTGIO_MASKB_CLEAR ((volatile unsigned short *)PORTGIO_MASKB_CLEAR)
+#define pPORTGIO_MASKB_SET ((volatile unsigned short *)PORTGIO_MASKB_SET)
+#define pPORTGIO_MASKB_TOGGLE ((volatile unsigned short *)PORTGIO_MASKB_TOGGLE)
+#define pPORTGIO_DIR ((volatile unsigned short *)PORTGIO_DIR)
+#define pPORTGIO_POLAR ((volatile unsigned short *)PORTGIO_POLAR)
+#define pPORTGIO_EDGE ((volatile unsigned short *)PORTGIO_EDGE)
+#define pPORTGIO_BOTH ((volatile unsigned short *)PORTGIO_BOTH)
+#define pPORTGIO_INEN ((volatile unsigned short *)PORTGIO_INEN)
+
+/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
+#define pPORTHIO ((volatile unsigned short *)PORTHIO)
+#define pPORTHIO_CLEAR ((volatile unsigned short *)PORTHIO_CLEAR)
+#define pPORTHIO_SET ((volatile unsigned short *)PORTHIO_SET)
+#define pPORTHIO_TOGGLE ((volatile unsigned short *)PORTHIO_TOGGLE)
+#define pPORTHIO_MASKA ((volatile unsigned short *)PORTHIO_MASKA)
+#define pPORTHIO_MASKA_CLEAR ((volatile unsigned short *)PORTHIO_MASKA_CLEAR)
+#define pPORTHIO_MASKA_SET ((volatile unsigned short *)PORTHIO_MASKA_SET)
+#define pPORTHIO_MASKA_TOGGLE ((volatile unsigned short *)PORTHIO_MASKA_TOGGLE)
+#define pPORTHIO_MASKB ((volatile unsigned short *)PORTHIO_MASKB)
+#define pPORTHIO_MASKB_CLEAR ((volatile unsigned short *)PORTHIO_MASKB_CLEAR)
+#define pPORTHIO_MASKB_SET ((volatile unsigned short *)PORTHIO_MASKB_SET)
+#define pPORTHIO_MASKB_TOGGLE ((volatile unsigned short *)PORTHIO_MASKB_TOGGLE)
+#define pPORTHIO_DIR ((volatile unsigned short *)PORTHIO_DIR)
+#define pPORTHIO_POLAR ((volatile unsigned short *)PORTHIO_POLAR)
+#define pPORTHIO_EDGE ((volatile unsigned short *)PORTHIO_EDGE)
+#define pPORTHIO_BOTH ((volatile unsigned short *)PORTHIO_BOTH)
+#define pPORTHIO_INEN ((volatile unsigned short *)PORTHIO_INEN)
+
+/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
+#define pUART1_THR ((volatile unsigned short *)UART1_THR)
+#define pUART1_RBR ((volatile unsigned short *)UART1_RBR)
+#define pUART1_DLL ((volatile unsigned short *)UART1_DLL)
+#define pUART1_IER ((volatile unsigned short *)UART1_IER)
+#define pUART1_DLH ((volatile unsigned short *)UART1_DLH)
+#define pUART1_IIR ((volatile unsigned short *)UART1_IIR)
+#define pUART1_LCR ((volatile unsigned short *)UART1_LCR)
+#define pUART1_MCR ((volatile unsigned short *)UART1_MCR)
+#define pUART1_LSR ((volatile unsigned short *)UART1_LSR)
+#define pUART1_MSR ((volatile unsigned short *)UART1_LSR)
+#define pUART1_SCR ((volatile unsigned short *)UART1_SCR)
+#define pUART1_GCTL ((volatile unsigned short *)UART1_GCTL)
+
+/* default UART controller */
+#if (CONFIG_UART_CONSOLE==1)
+
+#define pUART_THR pUART1_THR
+#define pUART_RBR pUART1_RBR
+#define pUART_DLL pUART1_DLL
+#define pUART_IER pUART1_IER
+#define pUART_DLH pUART1_DLH
+#define pUART_IIR pUART1_IIR
+#define pUART_LCR pUART1_LCR
+#define pUART_MCR pUART1_MCR
+#define pUART_LSR pUART1_LSR
+#define pUART_MSR pUART1_MSR
+#define pUART_SCR pUART1_SCR
+#define pUART_GCTL pUART1_GCTL
+
+#else
+
+#define pUART_THR pUART0_THR
+#define pUART_RBR pUART0_RBR
+#define pUART_DLL pUART0_DLL
+#define pUART_IER pUART0_IER
+#define pUART_DLH pUART0_DLH
+#define pUART_IIR pUART0_IIR
+#define pUART_LCR pUART0_LCR
+#define pUART_MCR pUART0_MCR
+#define pUART_LSR pUART0_LSR
+#define pUART_MSR pUART0_MSR
+#define pUART_SCR pUART0_SCR
+#define pUART_GCTL pUART0_GCTL
+
+#endif
+
+/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */
+/* For Mailboxes 0-15 */
+#define pCAN_MC1 ((volatile unsigned short *)CAN_MC1)
+#define pCAN_MD1 ((volatile unsigned short *)CAN_MD1)
+#define pCAN_TRS1 ((volatile unsigned short *)CAN_TRS1)
+#define pCAN_TRR1 ((volatile unsigned short *)CAN_TRR1)
+#define pCAN_TA1 ((volatile unsigned short *)CAN_TA1)
+#define pCAN_AA1 ((volatile unsigned short *)CAN_AA1)
+#define pCAN_RMP1 ((volatile unsigned short *)CAN_RMP1)
+#define pCAN_RML1 ((volatile unsigned short *)CAN_RML1)
+#define pCAN_MBTIF1 ((volatile unsigned short *)CAN_MBTIF1)
+#define pCAN_MBRIF1 ((volatile unsigned short *)CAN_MBRIF1)
+#define pCAN_MBIM1 ((volatile unsigned short *)CAN_MBIM1)
+#define pCAN_RFH1 ((volatile unsigned short *)CAN_RFH1)
+#define pCAN_OPSS1 ((volatile unsigned short *)CAN_OPSS1)
+
+/* For Mailboxes 16-31 */
+#define pCAN_MC2 ((volatile unsigned short *)CAN_MC2)
+#define pCAN_MD2 ((volatile unsigned short *)CAN_MD2)
+#define pCAN_TRS2 ((volatile unsigned short *)CAN_TRS2)
+#define pCAN_TRR2 ((volatile unsigned short *)CAN_TRR2)
+#define pCAN_TA2 ((volatile unsigned short *)CAN_TA2)
+#define pCAN_AA2 ((volatile unsigned short *)CAN_AA2)
+#define pCAN_RMP2 ((volatile unsigned short *)CAN_RMP2)
+#define pCAN_RML2 ((volatile unsigned short *)CAN_RML2)
+#define pCAN_MBTIF2 ((volatile unsigned short *)CAN_MBTIF2)
+#define pCAN_MBRIF2 ((volatile unsigned short *)CAN_MBRIF2)
+#define pCAN_MBIM2 ((volatile unsigned short *)CAN_MBIM2)
+#define pCAN_RFH2 ((volatile unsigned short *)CAN_RFH2)
+#define pCAN_OPSS2 ((volatile unsigned short *)CAN_OPSS2)
+
+#define pCAN_CLOCK ((volatile unsigned short *)CAN_CLOCK)
+#define pCAN_TIMING ((volatile unsigned short *)CAN_TIMING)
+#define pCAN_DEBUG ((volatile unsigned short *)CAN_DEBUG)
+#define pCAN_STATUS ((volatile unsigned short *)CAN_STATUS)
+#define pCAN_CEC ((volatile unsigned short *)CAN_CEC)
+#define pCAN_GIS ((volatile unsigned short *)CAN_GIS)
+#define pCAN_GIM ((volatile unsigned short *)CAN_GIM)
+#define pCAN_GIF ((volatile unsigned short *)CAN_GIF)
+#define pCAN_CONTROL ((volatile unsigned short *)CAN_CONTROL)
+#define pCAN_INTR ((volatile unsigned short *)CAN_INTR)
+#define pCAN_SFCMVER ((volatile unsigned short *)CAN_SFCMVER)
+#define pCAN_MBTD ((volatile unsigned short *)CAN_MBTD)
+#define pCAN_EWR ((volatile unsigned short *)CAN_EWR)
+#define pCAN_ESR ((volatile unsigned short *)CAN_ESR)
+#define pCAN_UCREG ((volatile unsigned short *)CAN_UCREG)
+#define pCAN_UCCNT ((volatile unsigned short *)CAN_UCCNT)
+#define pCAN_UCRC ((volatile unsigned short *)CAN_UCRC)
+#define pCAN_UCCNF ((volatile unsigned short *)CAN_UCCNF)
+#define pCAN_SFCMVER2 ((volatile unsigned short *)CAN_SFCMVER2)
+
+/* Mailbox Acceptance Masks */
+#define pCAN_AM00L ((volatile unsigned short *)CAN_AM00L)
+#define pCAN_AM00H ((volatile unsigned short *)CAN_AM00H)
+#define pCAN_AM01L ((volatile unsigned short *)CAN_AM01L)
+#define pCAN_AM01H ((volatile unsigned short *)CAN_AM01H)
+#define pCAN_AM02L ((volatile unsigned short *)CAN_AM02L)
+#define pCAN_AM02H ((volatile unsigned short *)CAN_AM02H)
+#define pCAN_AM03L ((volatile unsigned short *)CAN_AM03L)
+#define pCAN_AM03H ((volatile unsigned short *)CAN_AM03H)
+#define pCAN_AM04L ((volatile unsigned short *)CAN_AM04L)
+#define pCAN_AM04H ((volatile unsigned short *)CAN_AM04H)
+#define pCAN_AM05L ((volatile unsigned short *)CAN_AM05L)
+#define pCAN_AM05H ((volatile unsigned short *)CAN_AM05H)
+#define pCAN_AM06L ((volatile unsigned short *)CAN_AM06L)
+#define pCAN_AM06H ((volatile unsigned short *)CAN_AM06H)
+#define pCAN_AM07L ((volatile unsigned short *)CAN_AM07L)
+#define pCAN_AM07H ((volatile unsigned short *)CAN_AM07H)
+#define pCAN_AM08L ((volatile unsigned short *)CAN_AM08L)
+#define pCAN_AM08H ((volatile unsigned short *)CAN_AM08H)
+#define pCAN_AM09L ((volatile unsigned short *)CAN_AM09L)
+#define pCAN_AM09H ((volatile unsigned short *)CAN_AM09H)
+#define pCAN_AM10L ((volatile unsigned short *)CAN_AM10L)
+#define pCAN_AM10H ((volatile unsigned short *)CAN_AM10H)
+#define pCAN_AM11L ((volatile unsigned short *)CAN_AM11L)
+#define pCAN_AM11H ((volatile unsigned short *)CAN_AM11H)
+#define pCAN_AM12L ((volatile unsigned short *)CAN_AM12L)
+#define pCAN_AM12H ((volatile unsigned short *)CAN_AM12H)
+#define pCAN_AM13L ((volatile unsigned short *)CAN_AM13L)
+#define pCAN_AM13H ((volatile unsigned short *)CAN_AM13H)
+#define pCAN_AM14L ((volatile unsigned short *)CAN_AM14L)
+#define pCAN_AM14H ((volatile unsigned short *)CAN_AM14H)
+#define pCAN_AM15L ((volatile unsigned short *)CAN_AM15L)
+#define pCAN_AM15H ((volatile unsigned short *)CAN_AM15H)
+
+#define pCAN_AM16L ((volatile unsigned short *)CAN_AM16L)
+#define pCAN_AM16H ((volatile unsigned short *)CAN_AM16H)
+#define pCAN_AM17L ((volatile unsigned short *)CAN_AM17L)
+#define pCAN_AM17H ((volatile unsigned short *)CAN_AM17H)
+#define pCAN_AM18L ((volatile unsigned short *)CAN_AM18L)
+#define pCAN_AM18H ((volatile unsigned short *)CAN_AM18H)
+#define pCAN_AM19L ((volatile unsigned short *)CAN_AM19L)
+#define pCAN_AM19H ((volatile unsigned short *)CAN_AM19H)
+#define pCAN_AM20L ((volatile unsigned short *)CAN_AM20L)
+#define pCAN_AM20H ((volatile unsigned short *)CAN_AM20H)
+#define pCAN_AM21L ((volatile unsigned short *)CAN_AM21L)
+#define pCAN_AM21H ((volatile unsigned short *)CAN_AM21H)
+#define pCAN_AM22L ((volatile unsigned short *)CAN_AM22L)
+#define pCAN_AM22H ((volatile unsigned short *)CAN_AM22H)
+#define pCAN_AM23L ((volatile unsigned short *)CAN_AM23L)
+#define pCAN_AM23H ((volatile unsigned short *)CAN_AM23H)
+#define pCAN_AM24L ((volatile unsigned short *)CAN_AM24L)
+#define pCAN_AM24H ((volatile unsigned short *)CAN_AM24H)
+#define pCAN_AM25L ((volatile unsigned short *)CAN_AM25L)
+#define pCAN_AM25H ((volatile unsigned short *)CAN_AM25H)
+#define pCAN_AM26L ((volatile unsigned short *)CAN_AM26L)
+#define pCAN_AM26H ((volatile unsigned short *)CAN_AM26H)
+#define pCAN_AM27L ((volatile unsigned short *)CAN_AM27L)
+#define pCAN_AM27H ((volatile unsigned short *)CAN_AM27H)
+#define pCAN_AM28L ((volatile unsigned short *)CAN_AM28L)
+#define pCAN_AM28H ((volatile unsigned short *)CAN_AM28H)
+#define pCAN_AM29L ((volatile unsigned short *)CAN_AM29L)
+#define pCAN_AM29H ((volatile unsigned short *)CAN_AM29H)
+#define pCAN_AM30L ((volatile unsigned short *)CAN_AM30L)
+#define pCAN_AM30H ((volatile unsigned short *)CAN_AM30H)
+#define pCAN_AM31L ((volatile unsigned short *)CAN_AM31L)
+#define pCAN_AM31H ((volatile unsigned short *)CAN_AM31H)
+
+/* CAN Acceptance Mask Area Macros */
+#define pCAN_AM_L(x) ((volatile unsigned short *)CAN_AM_L(x))
+#define pCAN_AM_H(x) ((volatile unsigned short *)CAN_AM_H(x))
+
+/* Mailbox Registers */
+#define pCAN_MB00_ID1 ((volatile unsigned short *)CAN_MB00_ID1)
+#define pCAN_MB00_ID0 ((volatile unsigned short *)CAN_MB00_ID0)
+#define pCAN_MB00_TIMESTAMP ((volatile unsigned short *)CAN_MB00_TIMESTAMP)
+#define pCAN_MB00_LENGTH ((volatile unsigned short *)CAN_MB00_LENGTH)
+#define pCAN_MB00_DATA3 ((volatile unsigned short *)CAN_MB00_DATA3)
+#define pCAN_MB00_DATA2 ((volatile unsigned short *)CAN_MB00_DATA2)
+#define pCAN_MB00_DATA1 ((volatile unsigned short *)CAN_MB00_DATA1)
+#define pCAN_MB00_DATA0 ((volatile unsigned short *)CAN_MB00_DATA0)
+
+#define pCAN_MB01_ID1 ((volatile unsigned short *)CAN_MB01_ID1)
+#define pCAN_MB01_ID0 ((volatile unsigned short *)CAN_MB01_ID0)
+#define pCAN_MB01_TIMESTAMP ((volatile unsigned short *)CAN_MB01_TIMESTAMP)
+#define pCAN_MB01_LENGTH ((volatile unsigned short *)CAN_MB01_LENGTH)
+#define pCAN_MB01_DATA3 ((volatile unsigned short *)CAN_MB01_DATA3)
+#define pCAN_MB01_DATA2 ((volatile unsigned short *)CAN_MB01_DATA2)
+#define pCAN_MB01_DATA1 ((volatile unsigned short *)CAN_MB01_DATA1)
+#define pCAN_MB01_DATA0 ((volatile unsigned short *)CAN_MB01_DATA0)
+
+#define pCAN_MB02_ID1 ((volatile unsigned short *)CAN_MB02_ID1)
+#define pCAN_MB02_ID0 ((volatile unsigned short *)CAN_MB02_ID0)
+#define pCAN_MB02_TIMESTAMP ((volatile unsigned short *)CAN_MB02_TIMESTAMP)
+#define pCAN_MB02_LENGTH ((volatile unsigned short *)CAN_MB02_LENGTH)
+#define pCAN_MB02_DATA3 ((volatile unsigned short *)CAN_MB02_DATA3)
+#define pCAN_MB02_DATA2 ((volatile unsigned short *)CAN_MB02_DATA2)
+#define pCAN_MB02_DATA1 ((volatile unsigned short *)CAN_MB02_DATA1)
+#define pCAN_MB02_DATA0 ((volatile unsigned short *)CAN_MB02_DATA0)
+
+#define pCAN_MB03_ID1 ((volatile unsigned short *)CAN_MB03_ID1)
+#define pCAN_MB03_ID0 ((volatile unsigned short *)CAN_MB03_ID0)
+#define pCAN_MB03_TIMESTAMP ((volatile unsigned short *)CAN_MB03_TIMESTAMP)
+#define pCAN_MB03_LENGTH ((volatile unsigned short *)CAN_MB03_LENGTH)
+#define pCAN_MB03_DATA3 ((volatile unsigned short *)CAN_MB03_DATA3)
+#define pCAN_MB03_DATA2 ((volatile unsigned short *)CAN_MB03_DATA2)
+#define pCAN_MB03_DATA1 ((volatile unsigned short *)CAN_MB03_DATA1)
+#define pCAN_MB03_DATA0 ((volatile unsigned short *)CAN_MB03_DATA0)
+
+#define pCAN_MB04_ID1 ((volatile unsigned short *)CAN_MB04_ID1)
+#define pCAN_MB04_ID0 ((volatile unsigned short *)CAN_MB04_ID0)
+#define pCAN_MB04_TIMESTAMP ((volatile unsigned short *)CAN_MB04_TIMESTAMP)
+#define pCAN_MB04_LENGTH ((volatile unsigned short *)CAN_MB04_LENGTH)
+#define pCAN_MB04_DATA3 ((volatile unsigned short *)CAN_MB04_DATA3)
+#define pCAN_MB04_DATA2 ((volatile unsigned short *)CAN_MB04_DATA2)
+#define pCAN_MB04_DATA1 ((volatile unsigned short *)CAN_MB04_DATA1)
+#define pCAN_MB04_DATA0 ((volatile unsigned short *)CAN_MB04_DATA0)
+
+#define pCAN_MB05_ID1 ((volatile unsigned short *)CAN_MB05_ID1)
+#define pCAN_MB05_ID0 ((volatile unsigned short *)CAN_MB05_ID0)
+#define pCAN_MB05_TIMESTAMP ((volatile unsigned short *)CAN_MB05_TIMESTAMP)
+#define pCAN_MB05_LENGTH ((volatile unsigned short *)CAN_MB05_LENGTH)
+#define pCAN_MB05_DATA3 ((volatile unsigned short *)CAN_MB05_DATA3)
+#define pCAN_MB05_DATA2 ((volatile unsigned short *)CAN_MB05_DATA2)
+#define pCAN_MB05_DATA1 ((volatile unsigned short *)CAN_MB05_DATA1)
+#define pCAN_MB05_DATA0 ((volatile unsigned short *)CAN_MB05_DATA0)
+
+#define pCAN_MB06_ID1 ((volatile unsigned short *)CAN_MB06_ID1)
+#define pCAN_MB06_ID0 ((volatile unsigned short *)CAN_MB06_ID0)
+#define pCAN_MB06_TIMESTAMP ((volatile unsigned short *)CAN_MB06_TIMESTAMP)
+#define pCAN_MB06_LENGTH ((volatile unsigned short *)CAN_MB06_LENGTH)
+#define pCAN_MB06_DATA3 ((volatile unsigned short *)CAN_MB06_DATA3)
+#define pCAN_MB06_DATA2 ((volatile unsigned short *)CAN_MB06_DATA2)
+#define pCAN_MB06_DATA1 ((volatile unsigned short *)CAN_MB06_DATA1)
+#define pCAN_MB06_DATA0 ((volatile unsigned short *)CAN_MB06_DATA0)
+
+#define pCAN_MB07_ID1 ((volatile unsigned short *)CAN_MB07_ID1)
+#define pCAN_MB07_ID0 ((volatile unsigned short *)CAN_MB07_ID0)
+#define pCAN_MB07_TIMESTAMP ((volatile unsigned short *)CAN_MB07_TIMESTAMP)
+#define pCAN_MB07_LENGTH ((volatile unsigned short *)CAN_MB07_LENGTH)
+#define pCAN_MB07_DATA3 ((volatile unsigned short *)CAN_MB07_DATA3)
+#define pCAN_MB07_DATA2 ((volatile unsigned short *)CAN_MB07_DATA2)
+#define pCAN_MB07_DATA1 ((volatile unsigned short *)CAN_MB07_DATA1)
+#define pCAN_MB07_DATA0 ((volatile unsigned short *)CAN_MB07_DATA0)
+
+#define pCAN_MB08_ID1 ((volatile unsigned short *)CAN_MB08_ID1)
+#define pCAN_MB08_ID0 ((volatile unsigned short *)CAN_MB08_ID0)
+#define pCAN_MB08_TIMESTAMP ((volatile unsigned short *)CAN_MB08_TIMESTAMP)
+#define pCAN_MB08_LENGTH ((volatile unsigned short *)CAN_MB08_LENGTH)
+#define pCAN_MB08_DATA3 ((volatile unsigned short *)CAN_MB08_DATA3)
+#define pCAN_MB08_DATA2 ((volatile unsigned short *)CAN_MB08_DATA2)
+#define pCAN_MB08_DATA1 ((volatile unsigned short *)CAN_MB08_DATA1)
+#define pCAN_MB08_DATA0 ((volatile unsigned short *)CAN_MB08_DATA0)
+
+#define pCAN_MB09_ID1 ((volatile unsigned short *)CAN_MB09_ID1)
+#define pCAN_MB09_ID0 ((volatile unsigned short *)CAN_MB09_ID0)
+#define pCAN_MB09_TIMESTAMP ((volatile unsigned short *)CAN_MB09_TIMESTAMP)
+#define pCAN_MB09_LENGTH ((volatile unsigned short *)CAN_MB09_LENGTH)
+#define pCAN_MB09_DATA3 ((volatile unsigned short *)CAN_MB09_DATA3)
+#define pCAN_MB09_DATA2 ((volatile unsigned short *)CAN_MB09_DATA2)
+#define pCAN_MB09_DATA1 ((volatile unsigned short *)CAN_MB09_DATA1)
+#define pCAN_MB09_DATA0 ((volatile unsigned short *)CAN_MB09_DATA0)
+
+#define pCAN_MB10_ID1 ((volatile unsigned short *)CAN_MB10_ID1)
+#define pCAN_MB10_ID0 ((volatile unsigned short *)CAN_MB10_ID0)
+#define pCAN_MB10_TIMESTAMP ((volatile unsigned short *)CAN_MB10_TIMESTAMP)
+#define pCAN_MB10_LENGTH ((volatile unsigned short *)CAN_MB10_LENGTH)
+#define pCAN_MB10_DATA3 ((volatile unsigned short *)CAN_MB10_DATA3)
+#define pCAN_MB10_DATA2 ((volatile unsigned short *)CAN_MB10_DATA2)
+#define pCAN_MB10_DATA1 ((volatile unsigned short *)CAN_MB10_DATA1)
+#define pCAN_MB10_DATA0 ((volatile unsigned short *)CAN_MB10_DATA0)
+
+#define pCAN_MB11_ID1 ((volatile unsigned short *)CAN_MB11_ID1)
+#define pCAN_MB11_ID0 ((volatile unsigned short *)CAN_MB11_ID0)
+#define pCAN_MB11_TIMESTAMP ((volatile unsigned short *)CAN_MB11_TIMESTAMP)
+#define pCAN_MB11_LENGTH ((volatile unsigned short *)CAN_MB11_LENGTH)
+#define pCAN_MB11_DATA3 ((volatile unsigned short *)CAN_MB11_DATA3)
+#define pCAN_MB11_DATA2 ((volatile unsigned short *)CAN_MB11_DATA2)
+#define pCAN_MB11_DATA1 ((volatile unsigned short *)CAN_MB11_DATA1)
+#define pCAN_MB11_DATA0 ((volatile unsigned short *)CAN_MB11_DATA0)
+
+#define pCAN_MB12_ID1 ((volatile unsigned short *)CAN_MB12_ID1)
+#define pCAN_MB12_ID0 ((volatile unsigned short *)CAN_MB12_ID0)
+#define pCAN_MB12_TIMESTAMP ((volatile unsigned short *)CAN_MB12_TIMESTAMP)
+#define pCAN_MB12_LENGTH ((volatile unsigned short *)CAN_MB12_LENGTH)
+#define pCAN_MB12_DATA3 ((volatile unsigned short *)CAN_MB12_DATA3)
+#define pCAN_MB12_DATA2 ((volatile unsigned short *)CAN_MB12_DATA2)
+#define pCAN_MB12_DATA1 ((volatile unsigned short *)CAN_MB12_DATA1)
+#define pCAN_MB12_DATA0 ((volatile unsigned short *)CAN_MB12_DATA0)
+
+#define pCAN_MB13_ID1 ((volatile unsigned short *)CAN_MB13_ID1)
+#define pCAN_MB13_ID0 ((volatile unsigned short *)CAN_MB13_ID0)
+#define pCAN_MB13_TIMESTAMP ((volatile unsigned short *)CAN_MB13_TIMESTAMP)
+#define pCAN_MB13_LENGTH ((volatile unsigned short *)CAN_MB13_LENGTH)
+#define pCAN_MB13_DATA3 ((volatile unsigned short *)CAN_MB13_DATA3)
+#define pCAN_MB13_DATA2 ((volatile unsigned short *)CAN_MB13_DATA2)
+#define pCAN_MB13_DATA1 ((volatile unsigned short *)CAN_MB13_DATA1)
+#define pCAN_MB13_DATA0 ((volatile unsigned short *)CAN_MB13_DATA0)
+
+#define pCAN_MB14_ID1 ((volatile unsigned short *)CAN_MB14_ID1)
+#define pCAN_MB14_ID0 ((volatile unsigned short *)CAN_MB14_ID0)
+#define pCAN_MB14_TIMESTAMP ((volatile unsigned short *)CAN_MB14_TIMESTAMP)
+#define pCAN_MB14_LENGTH ((volatile unsigned short *)CAN_MB14_LENGTH)
+#define pCAN_MB14_DATA3 ((volatile unsigned short *)CAN_MB14_DATA3)
+#define pCAN_MB14_DATA2 ((volatile unsigned short *)CAN_MB14_DATA2)
+#define pCAN_MB14_DATA1 ((volatile unsigned short *)CAN_MB14_DATA1)
+#define pCAN_MB14_DATA0 ((volatile unsigned short *)CAN_MB14_DATA0)
+
+#define pCAN_MB15_ID1 ((volatile unsigned short *)CAN_MB15_ID1)
+#define pCAN_MB15_ID0 ((volatile unsigned short *)CAN_MB15_ID0)
+#define pCAN_MB15_TIMESTAMP ((volatile unsigned short *)CAN_MB15_TIMESTAMP)
+#define pCAN_MB15_LENGTH ((volatile unsigned short *)CAN_MB15_LENGTH)
+#define pCAN_MB15_DATA3 ((volatile unsigned short *)CAN_MB15_DATA3)
+#define pCAN_MB15_DATA2 ((volatile unsigned short *)CAN_MB15_DATA2)
+#define pCAN_MB15_DATA1 ((volatile unsigned short *)CAN_MB15_DATA1)
+#define pCAN_MB15_DATA0 ((volatile unsigned short *)CAN_MB15_DATA0)
+
+#define pCAN_MB16_ID1 ((volatile unsigned short *)CAN_MB16_ID1)
+#define pCAN_MB16_ID0 ((volatile unsigned short *)CAN_MB16_ID0)
+#define pCAN_MB16_TIMESTAMP ((volatile unsigned short *)CAN_MB16_TIMESTAMP)
+#define pCAN_MB16_LENGTH ((volatile unsigned short *)CAN_MB16_LENGTH)
+#define pCAN_MB16_DATA3 ((volatile unsigned short *)CAN_MB16_DATA3)
+#define pCAN_MB16_DATA2 ((volatile unsigned short *)CAN_MB16_DATA2)
+#define pCAN_MB16_DATA1 ((volatile unsigned short *)CAN_MB16_DATA1)
+#define pCAN_MB16_DATA0 ((volatile unsigned short *)CAN_MB16_DATA0)
+
+#define pCAN_MB17_ID1 ((volatile unsigned short *)CAN_MB17_ID1)
+#define pCAN_MB17_ID0 ((volatile unsigned short *)CAN_MB17_ID0)
+#define pCAN_MB17_TIMESTAMP ((volatile unsigned short *)CAN_MB17_TIMESTAMP)
+#define pCAN_MB17_LENGTH ((volatile unsigned short *)CAN_MB17_LENGTH)
+#define pCAN_MB17_DATA3 ((volatile unsigned short *)CAN_MB17_DATA3)
+#define pCAN_MB17_DATA2 ((volatile unsigned short *)CAN_MB17_DATA2)
+#define pCAN_MB17_DATA1 ((volatile unsigned short *)CAN_MB17_DATA1)
+#define pCAN_MB17_DATA0 ((volatile unsigned short *)CAN_MB17_DATA0)
+
+#define pCAN_MB18_ID1 ((volatile unsigned short *)CAN_MB18_ID1)
+#define pCAN_MB18_ID0 ((volatile unsigned short *)CAN_MB18_ID0)
+#define pCAN_MB18_TIMESTAMP ((volatile unsigned short *)CAN_MB18_TIMESTAMP)
+#define pCAN_MB18_LENGTH ((volatile unsigned short *)CAN_MB18_LENGTH)
+#define pCAN_MB18_DATA3 ((volatile unsigned short *)CAN_MB18_DATA3)
+#define pCAN_MB18_DATA2 ((volatile unsigned short *)CAN_MB18_DATA2)
+#define pCAN_MB18_DATA1 ((volatile unsigned short *)CAN_MB18_DATA1)
+#define pCAN_MB18_DATA0 ((volatile unsigned short *)CAN_MB18_DATA0)
+
+#define pCAN_MB19_ID1 ((volatile unsigned short *)CAN_MB19_ID1)
+#define pCAN_MB19_ID0 ((volatile unsigned short *)CAN_MB19_ID0)
+#define pCAN_MB19_TIMESTAMP ((volatile unsigned short *)CAN_MB19_TIMESTAMP)
+#define pCAN_MB19_LENGTH ((volatile unsigned short *)CAN_MB19_LENGTH)
+#define pCAN_MB19_DATA3 ((volatile unsigned short *)CAN_MB19_DATA3)
+#define pCAN_MB19_DATA2 ((volatile unsigned short *)CAN_MB19_DATA2)
+#define pCAN_MB19_DATA1 ((volatile unsigned short *)CAN_MB19_DATA1)
+#define pCAN_MB19_DATA0 ((volatile unsigned short *)CAN_MB19_DATA0)
+
+#define pCAN_MB20_ID1 ((volatile unsigned short *)CAN_MB20_ID1)
+#define pCAN_MB20_ID0 ((volatile unsigned short *)CAN_MB20_ID0)
+#define pCAN_MB20_TIMESTAMP ((volatile unsigned short *)CAN_MB20_TIMESTAMP)
+#define pCAN_MB20_LENGTH ((volatile unsigned short *)CAN_MB20_LENGTH)
+#define pCAN_MB20_DATA3 ((volatile unsigned short *)CAN_MB20_DATA3)
+#define pCAN_MB20_DATA2 ((volatile unsigned short *)CAN_MB20_DATA2)
+#define pCAN_MB20_DATA1 ((volatile unsigned short *)CAN_MB20_DATA1)
+#define pCAN_MB20_DATA0 ((volatile unsigned short *)CAN_MB20_DATA0)
+
+#define pCAN_MB21_ID1 ((volatile unsigned short *)CAN_MB21_ID1)
+#define pCAN_MB21_ID0 ((volatile unsigned short *)CAN_MB21_ID0)
+#define pCAN_MB21_TIMESTAMP ((volatile unsigned short *)CAN_MB21_TIMESTAMP)
+#define pCAN_MB21_LENGTH ((volatile unsigned short *)CAN_MB21_LENGTH)
+#define pCAN_MB21_DATA3 ((volatile unsigned short *)CAN_MB21_DATA3)
+#define pCAN_MB21_DATA2 ((volatile unsigned short *)CAN_MB21_DATA2)
+#define pCAN_MB21_DATA1 ((volatile unsigned short *)CAN_MB21_DATA1)
+#define pCAN_MB21_DATA0 ((volatile unsigned short *)CAN_MB21_DATA0)
+
+#define pCAN_MB22_ID1 ((volatile unsigned short *)CAN_MB22_ID1)
+#define pCAN_MB22_ID0 ((volatile unsigned short *)CAN_MB22_ID0)
+#define pCAN_MB22_TIMESTAMP ((volatile unsigned short *)CAN_MB22_TIMESTAMP)
+#define pCAN_MB22_LENGTH ((volatile unsigned short *)CAN_MB22_LENGTH)
+#define pCAN_MB22_DATA3 ((volatile unsigned short *)CAN_MB22_DATA3)
+#define pCAN_MB22_DATA2 ((volatile unsigned short *)CAN_MB22_DATA2)
+#define pCAN_MB22_DATA1 ((volatile unsigned short *)CAN_MB22_DATA1)
+#define pCAN_MB22_DATA0 ((volatile unsigned short *)CAN_MB22_DATA0)
+
+#define pCAN_MB23_ID1 ((volatile unsigned short *)CAN_MB23_ID1)
+#define pCAN_MB23_ID0 ((volatile unsigned short *)CAN_MB23_ID0)
+#define pCAN_MB23_TIMESTAMP ((volatile unsigned short *)CAN_MB23_TIMESTAMP)
+#define pCAN_MB23_LENGTH ((volatile unsigned short *)CAN_MB23_LENGTH)
+#define pCAN_MB23_DATA3 ((volatile unsigned short *)CAN_MB23_DATA3)
+#define pCAN_MB23_DATA2 ((volatile unsigned short *)CAN_MB23_DATA2)
+#define pCAN_MB23_DATA1 ((volatile unsigned short *)CAN_MB23_DATA1)
+#define pCAN_MB23_DATA0 ((volatile unsigned short *)CAN_MB23_DATA0)
+
+#define pCAN_MB24_ID1 ((volatile unsigned short *)CAN_MB24_ID1)
+#define pCAN_MB24_ID0 ((volatile unsigned short *)CAN_MB24_ID0)
+#define pCAN_MB24_TIMESTAMP ((volatile unsigned short *)CAN_MB24_TIMESTAMP)
+#define pCAN_MB24_LENGTH ((volatile unsigned short *)CAN_MB24_LENGTH)
+#define pCAN_MB24_DATA3 ((volatile unsigned short *)CAN_MB24_DATA3)
+#define pCAN_MB24_DATA2 ((volatile unsigned short *)CAN_MB24_DATA2)
+#define pCAN_MB24_DATA1 ((volatile unsigned short *)CAN_MB24_DATA1)
+#define pCAN_MB24_DATA0 ((volatile unsigned short *)CAN_MB24_DATA0)
+
+#define pCAN_MB25_ID1 ((volatile unsigned short *)CAN_MB25_ID1)
+#define pCAN_MB25_ID0 ((volatile unsigned short *)CAN_MB25_ID0)
+#define pCAN_MB25_TIMESTAMP ((volatile unsigned short *)CAN_MB25_TIMESTAMP)
+#define pCAN_MB25_LENGTH ((volatile unsigned short *)CAN_MB25_LENGTH)
+#define pCAN_MB25_DATA3 ((volatile unsigned short *)CAN_MB25_DATA3)
+#define pCAN_MB25_DATA2 ((volatile unsigned short *)CAN_MB25_DATA2)
+#define pCAN_MB25_DATA1 ((volatile unsigned short *)CAN_MB25_DATA1)
+#define pCAN_MB25_DATA0 ((volatile unsigned short *)CAN_MB25_DATA0)
+
+#define pCAN_MB26_ID1 ((volatile unsigned short *)CAN_MB26_ID1)
+#define pCAN_MB26_ID0 ((volatile unsigned short *)CAN_MB26_ID0)
+#define pCAN_MB26_TIMESTAMP ((volatile unsigned short *)CAN_MB26_TIMESTAMP)
+#define pCAN_MB26_LENGTH ((volatile unsigned short *)CAN_MB26_LENGTH)
+#define pCAN_MB26_DATA3 ((volatile unsigned short *)CAN_MB26_DATA3)
+#define pCAN_MB26_DATA2 ((volatile unsigned short *)CAN_MB26_DATA2)
+#define pCAN_MB26_DATA1 ((volatile unsigned short *)CAN_MB26_DATA1)
+#define pCAN_MB26_DATA0 ((volatile unsigned short *)CAN_MB26_DATA0)
+
+#define pCAN_MB27_ID1 ((volatile unsigned short *)CAN_MB27_ID1)
+#define pCAN_MB27_ID0 ((volatile unsigned short *)CAN_MB27_ID0)
+#define pCAN_MB27_TIMESTAMP ((volatile unsigned short *)CAN_MB27_TIMESTAMP)
+#define pCAN_MB27_LENGTH ((volatile unsigned short *)CAN_MB27_LENGTH)
+#define pCAN_MB27_DATA3 ((volatile unsigned short *)CAN_MB27_DATA3)
+#define pCAN_MB27_DATA2 ((volatile unsigned short *)CAN_MB27_DATA2)
+#define pCAN_MB27_DATA1 ((volatile unsigned short *)CAN_MB27_DATA1)
+#define pCAN_MB27_DATA0 ((volatile unsigned short *)CAN_MB27_DATA0)
+
+#define pCAN_MB28_ID1 ((volatile unsigned short *)CAN_MB28_ID1)
+#define pCAN_MB28_ID0 ((volatile unsigned short *)CAN_MB28_ID0)
+#define pCAN_MB28_TIMESTAMP ((volatile unsigned short *)CAN_MB28_TIMESTAMP)
+#define pCAN_MB28_LENGTH ((volatile unsigned short *)CAN_MB28_LENGTH)
+#define pCAN_MB28_DATA3 ((volatile unsigned short *)CAN_MB28_DATA3)
+#define pCAN_MB28_DATA2 ((volatile unsigned short *)CAN_MB28_DATA2)
+#define pCAN_MB28_DATA1 ((volatile unsigned short *)CAN_MB28_DATA1)
+#define pCAN_MB28_DATA0 ((volatile unsigned short *)CAN_MB28_DATA0)
+
+#define pCAN_MB29_ID1 ((volatile unsigned short *)CAN_MB29_ID1)
+#define pCAN_MB29_ID0 ((volatile unsigned short *)CAN_MB29_ID0)
+#define pCAN_MB29_TIMESTAMP ((volatile unsigned short *)CAN_MB29_TIMESTAMP)
+#define pCAN_MB29_LENGTH ((volatile unsigned short *)CAN_MB29_LENGTH)
+#define pCAN_MB29_DATA3 ((volatile unsigned short *)CAN_MB29_DATA3)
+#define pCAN_MB29_DATA2 ((volatile unsigned short *)CAN_MB29_DATA2)
+#define pCAN_MB29_DATA1 ((volatile unsigned short *)CAN_MB29_DATA1)
+#define pCAN_MB29_DATA0 ((volatile unsigned short *)CAN_MB29_DATA0)
+
+#define pCAN_MB30_ID1 ((volatile unsigned short *)CAN_MB30_ID1)
+#define pCAN_MB30_ID0 ((volatile unsigned short *)CAN_MB30_ID0)
+#define pCAN_MB30_TIMESTAMP ((volatile unsigned short *)CAN_MB30_TIMESTAMP)
+#define pCAN_MB30_LENGTH ((volatile unsigned short *)CAN_MB30_LENGTH)
+#define pCAN_MB30_DATA3 ((volatile unsigned short *)CAN_MB30_DATA3)
+#define pCAN_MB30_DATA2 ((volatile unsigned short *)CAN_MB30_DATA2)
+#define pCAN_MB30_DATA1 ((volatile unsigned short *)CAN_MB30_DATA1)
+#define pCAN_MB30_DATA0 ((volatile unsigned short *)CAN_MB30_DATA0)
+
+#define pCAN_MB31_ID1 ((volatile unsigned short *)CAN_MB31_ID1)
+#define pCAN_MB31_ID0 ((volatile unsigned short *)CAN_MB31_ID0)
+#define pCAN_MB31_TIMESTAMP ((volatile unsigned short *)CAN_MB31_TIMESTAMP)
+#define pCAN_MB31_LENGTH ((volatile unsigned short *)CAN_MB31_LENGTH)
+#define pCAN_MB31_DATA3 ((volatile unsigned short *)CAN_MB31_DATA3)
+#define pCAN_MB31_DATA2 ((volatile unsigned short *)CAN_MB31_DATA2)
+#define pCAN_MB31_DATA1 ((volatile unsigned short *)CAN_MB31_DATA1)
+#define pCAN_MB31_DATA0 ((volatile unsigned short *)CAN_MB31_DATA0)
+
+/* CAN Mailbox Area Macros */
+#define pCAN_MB_ID1(x) ((volatile unsigned short *)CAN_MB_ID1(x))
+#define pCAN_MB_ID0(x) ((volatile unsigned short *)CAN_MB_ID0(x))
+#define pCAN_MB_TIMESTAMP(x) ((volatile unsigned short *)CAN_MB_TIMESTAMP(x))
+#define pCAN_MB_LENGTH(x) ((volatile unsigned short *)CAN_MB_LENGTH(x))
+#define pCAN_MB_DATA3(x) ((volatile unsigned short *)CAN_MB_DATA3(x))
+#define pCAN_MB_DATA2(x) ((volatile unsigned short *)CAN_MB_DATA2(x))
+#define pCAN_MB_DATA1(x) ((volatile unsigned short *)CAN_MB_DATA1(x))
+#define pCAN_MB_DATA0(x) ((volatile unsigned short *)CAN_MB_DATA0(x))
+
+/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
+#define pPORTF_FER ((volatile unsigned short *)PORTF_FER)
+#define pPORTG_FER ((volatile unsigned short *)PORTG_FER)
+#define pPORTH_FER ((volatile unsigned short *)PORTH_FER)
+#define pPORT_MUX ((volatile unsigned short *)PORT_MUX)
+
+#define PORTF_UART0_TX 0x0001
+#define PORTF_UART0_RX 0x0002
+
+#define PORT_MUX_PFDE 0x0040 /* 0: Enable UART0 RX, UART0 TX; 1: Enable DMAR0, DMAr1 */
+
+/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
+#define pHMDMA0_CONTROL ((volatile unsigned short *)HMDMA0_CONTROL)
+#define pHMDMA0_ECINIT ((volatile unsigned short *)HMDMA0_ECINIT)
+#define pHMDMA0_BCINIT ((volatile unsigned short *)HMDMA0_BCINIT)
+#define pHMDMA0_ECURGENT ((volatile unsigned short *)HMDMA0_ECURGENT)
+#define pHMDMA0_ECOVERFLOW ((volatile unsigned short *)HMDMA0_ECOVERFLOW)
+#define pHMDMA0_ECOUNT ((volatile unsigned short *)HMDMA0_ECOUNT)
+#define pHMDMA0_BCOUNT ((volatile unsigned short *)HMDMA0_BCOUNT)
+
+#define pHMDMA1_CONTROL ((volatile unsigned short *)HMDMA1_CONTROL)
+#define pHMDMA1_ECINIT ((volatile unsigned short *)HMDMA1_ECINIT)
+#define pHMDMA1_BCINIT ((volatile unsigned short *)HMDMA1_BCINIT)
+#define pHMDMA1_ECURGENT ((volatile unsigned short *)HMDMA1_ECURGENT)
+#define pHMDMA1_ECOVERFLOW ((volatile unsigned short *)HMDMA1_ECOVERFLOW)
+#define pHMDMA1_ECOUNT ((volatile unsigned short *)HMDMA1_ECOUNT)
+#define pHMDMA1_BCOUNT ((volatile unsigned short *)HMDMA1_BCOUNT)
+
+#endif /* _CDEF_BF534_H */
--- /dev/null
+/*
+ * Copyright (C) 2004 Analog Devices Inc., All Rights Reserved.
+ *
+ ***********************************************************************************
+ *
+ * This include file contains a list of macro "defines" to enable the programmer
+ * to use symbolic names for register-access.
+ *
+ * ----------------------------
+ * revision 0.1
+ * date: 2004/03/01 21:23:01; author: joeb
+ * Initial revision
+ *
+ * ----------------------------
+ * revision 0.2
+ * date: 2004/05/15 16:30:00; author: joeb
+ * comments: removed I2C/IIC references to TWI, changed GPIO sections
+ *
+ * ----------------------------
+ * revision 0.3
+ * date: 2004/06/08 12:25:00; author: joeb
+ * comments: renamed some TWI and GPIO registers
+ *
+ * ----------------------------
+ * revision 0.4
+ * date: 2004/06/09 14:25:00; author: joeb
+ * comments: changed Timer status register to 32-bit, renamed EMAC count registers
+ *
+ * ----------------------------
+ * revision 0.5
+ * date: 2004/08/10 10:25:00; author: joeb
+ * comments: Renamed EMAC wake-up registers, changed bit-names in EMAC registers
+ *
+ * ----------------------------
+ * revision 0.6
+ * date: 2004/08/17 16:25:00; author: joeb
+ * comments: Renamed TWI_INT_ENABLE to TWI_INT_MASK
+ *
+ * ----------------------------
+ * revision 0.7
+ * date: 2004/08/18 13:21:00; author: joeb
+ * comments: Renamed GPIO registers to remove _D, _S, _C, _T suffixes
+ *
+ * ----------------------------
+ * revision 0.8
+ * date: 2004/08/20 10:27:00; author: joeb
+ * comments: Renamed External DMA to Handshake DMA
+ *
+ * ----------------------------
+ * revision 0.9
+ * date: 2004/08/23 13:42:00; author: joeb
+ * comments: Renamed Handshake DMA Register Set
+ *
+ * ----------------------------
+ * revision 0.10
+ * date: 2004/10/28 15:40:00; author: joeb
+ * comments: Shortened EMAC Count Register Names
+ *
+ * ----------------------------
+ * revision 0.11
+ * date: 2004/12/13 11:05:00; author: joeb
+ * comments: Fixed address pointers - (volatile void **) to (void * volatile *)
+ *
+ * ----------------------------
+ * revision 0.12
+ * date: 2004/12/17 14:25:00; author: joeb
+ * comments: Replaced C++ Single-Line Comments w/C-standard Comments
+ * Changed EMAC EQ1024 TX/RX References to GE1024
+ *
+ * ----------------------------
+ * revision 0.13
+ * date: 2005/01/05 10:50:00; author: joeb
+ * comments: Removed excess white space in CAN_AM section
+ * Added support for CAN Macros to Index AM and Mailbox Areas
+ *
+ * ----------------------------
+ * revision 0.14
+ * date: 2005/01/26 14:10:00; author: joeb
+ * comments: Fixed Typo In EMAC_RXC_PAUSE register
+ *
+ * ----------------------------
+ * revision 0.15
+ * date: 2005/01/27 14:41:00; author: joeb
+ * comments: Moved Common MMRs to cdefBF534.h
+ */
+
+/*
+ * System MMR Register Map
+ */
+
+#ifndef _CDEF_BF537_H
+#define _CDEF_BF537_H
+
+/* Include MMRs Common to BF534 */
+#include <asm/arch-bf537/cdefBF534.h>
+
+/* Include all Core registers and bit definitions */
+#include <asm/arch-bf537/defBF537.h>
+
+/* Include Macro "Defines" For EMAC (Unique to BF536/BF537 */
+/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
+#define pEMAC_OPMODE ((volatile unsigned long *)EMAC_OPMODE)
+#define pEMAC_ADDRLO ((volatile unsigned long *)EMAC_ADDRLO)
+#define pEMAC_ADDRHI ((volatile unsigned long *)EMAC_ADDRHI)
+#define pEMAC_HASHLO ((volatile unsigned long *)EMAC_HASHLO)
+#define pEMAC_HASHHI ((volatile unsigned long *)EMAC_HASHHI)
+#define pEMAC_STAADD ((volatile unsigned long *)EMAC_STAADD)
+#define pEMAC_STADAT ((volatile unsigned long *)EMAC_STADAT)
+#define pEMAC_FLC ((volatile unsigned long *)EMAC_FLC)
+#define pEMAC_VLAN1 ((volatile unsigned long *)EMAC_VLAN1)
+#define pEMAC_VLAN2 ((volatile unsigned long *)EMAC_VLAN2)
+#define pEMAC_WKUP_CTL ((volatile unsigned long *)EMAC_WKUP_CTL)
+#define pEMAC_WKUP_FFMSK0 ((volatile unsigned long *)EMAC_WKUP_FFMSK0)
+#define pEMAC_WKUP_FFMSK1 ((volatile unsigned long *)EMAC_WKUP_FFMSK1)
+#define pEMAC_WKUP_FFMSK2 ((volatile unsigned long *)EMAC_WKUP_FFMSK2)
+#define pEMAC_WKUP_FFMSK3 ((volatile unsigned long *)EMAC_WKUP_FFMSK3)
+#define pEMAC_WKUP_FFCMD ((volatile unsigned long *)EMAC_WKUP_FFCMD)
+#define pEMAC_WKUP_FFOFF ((volatile unsigned long *)EMAC_WKUP_FFOFF)
+#define pEMAC_WKUP_FFCRC0 ((volatile unsigned long *)EMAC_WKUP_FFCRC0)
+#define pEMAC_WKUP_FFCRC1 ((volatile unsigned long *)EMAC_WKUP_FFCRC1)
+
+#define pEMAC_SYSCTL ((volatile unsigned long *)EMAC_SYSCTL)
+#define pEMAC_SYSTAT ((volatile unsigned long *)EMAC_SYSTAT)
+#define pEMAC_RX_STAT ((volatile unsigned long *)EMAC_RX_STAT)
+#define pEMAC_RX_STKY ((volatile unsigned long *)EMAC_RX_STKY)
+#define pEMAC_RX_IRQE ((volatile unsigned long *)EMAC_RX_IRQE)
+#define pEMAC_TX_STAT ((volatile unsigned long *)EMAC_TX_STAT)
+#define pEMAC_TX_STKY ((volatile unsigned long *)EMAC_TX_STKY)
+#define pEMAC_TX_IRQE ((volatile unsigned long *)EMAC_TX_IRQE)
+
+#define pEMAC_MMC_CTL ((volatile unsigned long *)EMAC_MMC_CTL)
+#define pEMAC_MMC_RIRQS ((volatile unsigned long *)EMAC_MMC_RIRQS)
+#define pEMAC_MMC_RIRQE ((volatile unsigned long *)EMAC_MMC_RIRQE)
+#define pEMAC_MMC_TIRQS ((volatile unsigned long *)EMAC_MMC_TIRQS)
+#define pEMAC_MMC_TIRQE ((volatile unsigned long *)EMAC_MMC_TIRQE)
+
+#define pEMAC_RXC_OK ((volatile unsigned long *)EMAC_RXC_OK)
+#define pEMAC_RXC_FCS ((volatile unsigned long *)EMAC_RXC_FCS)
+#define pEMAC_RXC_ALIGN ((volatile unsigned long *)EMAC_RXC_ALIGN)
+#define pEMAC_RXC_OCTET ((volatile unsigned long *)EMAC_RXC_OCTET)
+#define pEMAC_RXC_DMAOVF ((volatile unsigned long *)EMAC_RXC_DMAOVF)
+#define pEMAC_RXC_UNICST ((volatile unsigned long *)EMAC_RXC_UNICST)
+#define pEMAC_RXC_MULTI ((volatile unsigned long *)EMAC_RXC_MULTI)
+#define pEMAC_RXC_BROAD ((volatile unsigned long *)EMAC_RXC_BROAD)
+#define pEMAC_RXC_LNERRI ((volatile unsigned long *)EMAC_RXC_LNERRI)
+#define pEMAC_RXC_LNERRO ((volatile unsigned long *)EMAC_RXC_LNERRO)
+#define pEMAC_RXC_LONG ((volatile unsigned long *)EMAC_RXC_LONG)
+#define pEMAC_RXC_MACCTL ((volatile unsigned long *)EMAC_RXC_MACCTL)
+#define pEMAC_RXC_OPCODE ((volatile unsigned long *)EMAC_RXC_OPCODE)
+#define pEMAC_RXC_PAUSE ((volatile unsigned long *)EMAC_RXC_PAUSE)
+#define pEMAC_RXC_ALLFRM ((volatile unsigned long *)EMAC_RXC_ALLFRM)
+#define pEMAC_RXC_ALLOCT ((volatile unsigned long *)EMAC_RXC_ALLOCT)
+#define pEMAC_RXC_TYPED ((volatile unsigned long *)EMAC_RXC_TYPED)
+#define pEMAC_RXC_SHORT ((volatile unsigned long *)EMAC_RXC_SHORT)
+#define pEMAC_RXC_EQ64 ((volatile unsigned long *)EMAC_RXC_EQ64)
+#define pEMAC_RXC_LT128 ((volatile unsigned long *)EMAC_RXC_LT128)
+#define pEMAC_RXC_LT256 ((volatile unsigned long *)EMAC_RXC_LT256)
+#define pEMAC_RXC_LT512 ((volatile unsigned long *)EMAC_RXC_LT512)
+#define pEMAC_RXC_LT1024 ((volatile unsigned long *)EMAC_RXC_LT1024)
+#define pEMAC_RXC_GE1024 ((volatile unsigned long *)EMAC_RXC_GE1024)
+
+#define pEMAC_TXC_OK ((volatile unsigned long *)EMAC_TXC_OK)
+#define pEMAC_TXC_1COL ((volatile unsigned long *)EMAC_TXC_1COL)
+#define pEMAC_TXC_GT1COL ((volatile unsigned long *)EMAC_TXC_GT1COL)
+#define pEMAC_TXC_OCTET ((volatile unsigned long *)EMAC_TXC_OCTET)
+#define pEMAC_TXC_DEFER ((volatile unsigned long *)EMAC_TXC_DEFER)
+#define pEMAC_TXC_LATECL ((volatile unsigned long *)EMAC_TXC_LATECL)
+#define pEMAC_TXC_XS_COL ((volatile unsigned long *)EMAC_TXC_XS_COL)
+#define pEMAC_TXC_DMAUND ((volatile unsigned long *)EMAC_TXC_DMAUND)
+#define pEMAC_TXC_CRSERR ((volatile unsigned long *)EMAC_TXC_CRSERR)
+#define pEMAC_TXC_UNICST ((volatile unsigned long *)EMAC_TXC_UNICST)
+#define pEMAC_TXC_MULTI ((volatile unsigned long *)EMAC_TXC_MULTI)
+#define pEMAC_TXC_BROAD ((volatile unsigned long *)EMAC_TXC_BROAD)
+#define pEMAC_TXC_XS_DFR ((volatile unsigned long *)EMAC_TXC_XS_DFR)
+#define pEMAC_TXC_MACCTL ((volatile unsigned long *)EMAC_TXC_MACCTL)
+#define pEMAC_TXC_ALLFRM ((volatile unsigned long *)EMAC_TXC_ALLFRM)
+#define pEMAC_TXC_ALLOCT ((volatile unsigned long *)EMAC_TXC_ALLOCT)
+#define pEMAC_TXC_EQ64 ((volatile unsigned long *)EMAC_TXC_EQ64)
+#define pEMAC_TXC_LT128 ((volatile unsigned long *)EMAC_TXC_LT128)
+#define pEMAC_TXC_LT256 ((volatile unsigned long *)EMAC_TXC_LT256)
+#define pEMAC_TXC_LT512 ((volatile unsigned long *)EMAC_TXC_LT512)
+#define pEMAC_TXC_LT1024 ((volatile unsigned long *)EMAC_TXC_LT1024)
+#define pEMAC_TXC_GE1024 ((volatile unsigned long *)EMAC_TXC_GE1024)
+#define pEMAC_TXC_ABORT ((volatile unsigned long *)EMAC_TXC_ABORT)
+
+#endif /* _CDEF_BF537_H */
--- /dev/null
+/*This file is subject to the terms and conditions of the GNU General Public
+ * License.
+ *
+ * Blackfin BF533/2.6 support : LG Soft India
+ * Updated : Ashutosh Singh / Jahid Khan : Rrap Software Pvt Ltd
+ * Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's
+ * shouldn't be victimized. cplbmgr.S search logic is corrected
+ * to findout the appropriate victim.
+ * 2. SDRAM_IGENERIC in dpdt_table is replaced with SDRAM_DGENERIC
+ * : LG Soft India
+ */
+#include <config.h>
+
+#ifndef __ARCH_BFINNOMMU_CPLBTAB_H
+#define __ARCH_BFINNOMMU_CPLBTAB_H
+
+/*
+ * ICPLB TABLE
+ */
+
+.data
+/* This table is configurable */
+ .align 4;
+
+/* Data Attibutes*/
+
+#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
+#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
+#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
+#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
+
+/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
+
+#define ANOMALY_05000158 0x200
+#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
+#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
+#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
+
+#else /*Write Through */
+#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
+#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
+#endif
+
+.align 4;
+.global _ipdt_table _ipdt_table:.byte4 0x00000000;
+.byte4(SDRAM_IKERNEL); /*SDRAM_Page0 */
+.byte4 0x00400000;
+.byte4(SDRAM_IKERNEL); /*SDRAM_Page1 */
+.byte4 0x00800000;
+.byte4(SDRAM_IGENERIC); /*SDRAM_Page2 */
+.byte4 0x00C00000;
+.byte4(SDRAM_IGENERIC); /*SDRAM_Page3 */
+.byte4 0x01000000;
+.byte4(SDRAM_IGENERIC); /*SDRAM_Page4 */
+.byte4 0x01400000;
+.byte4(SDRAM_IGENERIC); /*SDRAM_Page5 */
+.byte4 0x01800000;
+.byte4(SDRAM_IGENERIC); /*SDRAM_Page6 */
+.byte4 0x01C00000;
+.byte4(SDRAM_IGENERIC); /*SDRAM_Page7 */
+.byte4 0x02000000;
+.byte4(SDRAM_IGENERIC); /*SDRAM_Page8 */
+.byte4 0x02400000;
+.byte4(SDRAM_IGENERIC); /*SDRAM_Page9 */
+.byte4 0x02800000;
+.byte4(SDRAM_IGENERIC); /*SDRAM_Page10 */
+.byte4 0x02C00000;
+.byte4(SDRAM_IGENERIC); /*SDRAM_Page11 */
+.byte4 0x03000000;
+.byte4(SDRAM_IGENERIC); /*SDRAM_Page12 */
+.byte4 0x03400000;
+.byte4(SDRAM_IGENERIC); /*SDRAM_Page13 */
+.byte4 0x03800000;
+.byte4(SDRAM_IGENERIC); /*SDRAM_Page14 */
+.byte4 0x03C00000;
+.byte4(SDRAM_IGENERIC); /*SDRAM_Page15 */
+.byte4 0x20000000;
+.byte4(SDRAM_EBIU); /* Async Memory Bank 2 (Secnd) */
+
+.byte4 0xffffffff; /* end of section - termination */
+
+/*
+ * PAGE DESCRIPTOR TABLE
+ *
+ */
+
+/*
+ * Till here we are discussing about the static memory management model.
+ * However, the operating envoronments commonly define more CPLB
+ * descriptors to cover the entire addressable memory than will fit into
+ * the available on-chip 16 CPLB MMRs. When this happens, the below table
+ * will be used which will hold all the potentially required CPLB descriptors
+ *
+ * This is how Page descriptor Table is implemented in uClinux/Blackfin.
+ */
+.global _dpdt_table _dpdt_table:.byte4 0x00000000;
+.byte4(SDRAM_DKERNEL); /*SDRAM_Page0 */
+.byte4 0x00400000;
+.byte4(SDRAM_DKERNEL); /*SDRAM_Page1 */
+.byte4 0x00800000;
+.byte4(SDRAM_DGENERIC); /*SDRAM_Page2 */
+.byte4 0x00C00000;
+.byte4(SDRAM_DGENERIC); /*SDRAM_Page3 */
+.byte4 0x01000000;
+.byte4(SDRAM_DGENERIC); /*SDRAM_Page4 */
+.byte4 0x01400000;
+.byte4(SDRAM_DGENERIC); /*SDRAM_Page5 */
+.byte4 0x01800000;
+.byte4(SDRAM_DGENERIC); /*SDRAM_Page6 */
+.byte4 0x01C00000;
+.byte4(SDRAM_DGENERIC); /*SDRAM_Page7 */
+.byte4 0x02000000;
+.byte4(SDRAM_DGENERIC); /*SDRAM_Page8 */
+.byte4 0x02400000;
+.byte4(SDRAM_DGENERIC); /*SDRAM_Page9 */
+.byte4 0x02800000;
+.byte4(SDRAM_DGENERIC); /*SDRAM_Page10 */
+.byte4 0x02C00000;
+.byte4(SDRAM_DGENERIC); /*SDRAM_Page11 */
+.byte4 0x03000000;
+.byte4(SDRAM_DGENERIC); /*SDRAM_Page12 */
+.byte4 0x03400000;
+.byte4(SDRAM_DGENERIC); /*SDRAM_Page13 */
+.byte4 0x03800000;
+.byte4(SDRAM_DGENERIC); /*SDRAM_Page14 */
+.byte4 0x03C00000;
+.byte4(SDRAM_DGENERIC); /*SDRAM_Page15 */
+.byte4 0x20000000;
+.byte4(SDRAM_EBIU); /* Async Memory Bank 0 (Prim A) */
+
+#if ((BFIN_CPU == ADSP_BF534) || (BFIN_CPU == ADSP_BF537))
+.byte4 0xFF800000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF801000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF802000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF803000;
+.byte4(L1_DMEMORY);
+#endif
+.byte4 0xFF804000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF805000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF806000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF807000;
+.byte4(L1_DMEMORY);
+#if ((BFIN_CPU == ADSP_BF534) || (BFIN_CPU == ADSP_BF537))
+.byte4 0xFF900000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF901000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF902000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF903000;
+.byte4(L1_DMEMORY);
+#endif
+.byte4 0xFF904000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF905000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF906000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF907000;
+.byte4(L1_DMEMORY);
+
+.byte4 0xFFB00000;
+.byte4(L1_DMEMORY);
+
+.byte4 0xffffffff; /*end of section - termination */
+
+#ifdef CONFIG_CPLB_INFO
+.global _ipdt_swapcount_table; /* swapin count first, then swapout count */
+_ipdt_swapcount_table:
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 10 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 20 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 30 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 40 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 50 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 60 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 70 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 80 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 90 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 100 */
+
+.global _dpdt_swapcount_table; /* swapin count first, then swapout count */
+_dpdt_swapcount_table:
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 10 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 20 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 30 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 40 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 50 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 60 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 70 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 80 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 80 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 100 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 110 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000; /* 120 */
+
+#endif
+
+#endif /*__ARCH_BFINNOMMU_CPLBTAB_H*/
--- /dev/null
+/*
+ * Copyright (C) 2004 Analog Devices Inc., All Rights Reserved.
+ *
+ ***********************************************************************************
+ *
+ * This include file contains a list of macro "defines" to enable the programmer
+ * to use symbolic names for register-access and bit-manipulation.
+ *
+ * ----------------------------
+ * revision 0.1
+ * date: 2004/03/01 21:23:01; author: joeb
+ * Initial revision
+ *
+ */
+#ifndef _DEF_BF534_H
+#define _DEF_BF534_H
+
+/* Include all Core registers and bit definitions */
+#include <asm/arch-common/def_LPBlackfin.h>
+
+#define LO(con32) ((con32) & 0xFFFF)
+#define lo(con32) ((con32) & 0xFFFF)
+#define HI(con32) (((con32) >> 16) & 0xFFFF)
+#define hi(con32) (((con32) >> 16) & 0xFFFF)
+
+/*
+ * System MMR Register Map
+ */
+/* Clock and System Control (0xFFC00000 - 0xFFC000FF)*/
+#define PLL_CTL 0xFFC00000 /* PLL Control Register */
+#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
+#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
+#define CHIPID 0xFFC00014 /* Chip ID register (32-bit) */
+#define PLL_STAT 0xFFC0000C /* PLL Status Register */
+#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
+
+/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
+#define SWRST 0xFFC00100 /* Software Reset Register */
+#define SYSCR 0xFFC00104 /* System Configuration Register */
+#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
+#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
+#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
+#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
+#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
+#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
+#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */
+#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */
+
+/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
+#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
+#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
+#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
+
+/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
+#define RTC_STAT 0xFFC00300 /* RTC Status Register */
+#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
+#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
+#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
+#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
+#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
+#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */
+
+/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
+#define UART0_THR 0xFFC00400 /* Transmit Holding register */
+#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
+#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
+#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
+#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
+#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
+#define UART0_LCR 0xFFC0040C /* Line Control Register */
+#define UART0_MCR 0xFFC00410 /* Modem Control Register */
+#define UART0_LSR 0xFFC00414 /* Line Status Register */
+#define UART0_MSR 0xFFC00418 /* Modem Status Register */
+#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
+#define UART0_GCTL 0xFFC00424 /* Global Control Register */
+
+/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
+#define SPI_CTL 0xFFC00500 /* SPI Control Register */
+#define SPI_FLG 0xFFC00504 /* SPI Flag register */
+#define SPI_STAT 0xFFC00508 /* SPI Status register */
+#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
+#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
+#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
+#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
+
+/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
+#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
+#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
+#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
+#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
+
+#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
+#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
+#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
+#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
+
+#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
+#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
+#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
+#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
+
+#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
+#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
+#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
+#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
+
+#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
+#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
+#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
+#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
+
+#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
+#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
+#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
+#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
+
+#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
+#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
+#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
+#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */
+
+#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
+#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
+#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
+#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
+
+#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
+#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
+#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
+
+/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
+#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
+#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
+#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
+#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
+#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
+#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
+#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
+#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
+#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
+#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
+#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
+#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
+#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
+#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
+#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
+#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
+#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
+
+/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
+#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
+#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
+#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
+#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
+#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
+#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
+#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
+#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
+#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
+#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
+#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
+#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
+#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
+#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
+#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
+#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
+#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
+#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
+
+/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
+#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
+#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
+#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
+#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
+#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
+#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
+#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
+#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
+#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
+#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
+#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
+#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
+#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
+#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
+#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
+#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
+#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
+#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
+
+/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
+#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
+#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
+#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
+#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
+#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
+#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
+#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
+
+/* DMA Traffic Control Registers */
+#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
+#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
+
+/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
+#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
+#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
+#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
+#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
+#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
+#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
+#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
+#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
+#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
+#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
+#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
+#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
+#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
+
+#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
+#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
+#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
+#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
+#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
+#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
+#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
+#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
+#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
+#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
+#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
+#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
+#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
+
+#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
+#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
+#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
+#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
+#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
+#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
+#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
+#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
+#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
+#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
+#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
+#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
+#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
+
+#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
+#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
+#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
+#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
+#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
+#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
+#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
+#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
+#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
+#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
+#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
+#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
+#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
+
+#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
+#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
+#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
+#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
+#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
+#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
+#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
+#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
+#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
+#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
+#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
+#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
+#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
+
+#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
+#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
+#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
+#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
+#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
+#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
+#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
+#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
+#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
+#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
+#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
+#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
+#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
+
+#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
+#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
+#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
+#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
+#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
+#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
+#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
+#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
+#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
+#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
+#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
+#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
+#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
+
+#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
+#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
+#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
+#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
+#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
+#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
+#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
+#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
+#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
+#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
+#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
+#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
+#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
+
+#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
+#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
+#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
+#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
+#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
+#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
+#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
+#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
+#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
+#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
+#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
+#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
+#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
+
+#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
+#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
+#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
+#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
+#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
+#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
+#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
+#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
+#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
+#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
+#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
+#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
+#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
+
+#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
+#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
+#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
+#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
+#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
+#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
+#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
+#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
+#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
+#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
+#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
+#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
+#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
+
+#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
+#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
+#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
+#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
+#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
+#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
+#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
+#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
+#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
+#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
+#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
+#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
+#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
+
+#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
+#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
+#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
+#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
+#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
+#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
+#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
+#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
+#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
+#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
+#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
+#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
+#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
+
+#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
+#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
+#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
+#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
+#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
+#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
+#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
+#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
+#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
+#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
+#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
+#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
+#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
+
+#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
+#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
+#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
+#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
+#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
+#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
+#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
+#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
+#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
+#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
+#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
+#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
+#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
+
+#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
+#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
+#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
+#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
+#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
+#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
+#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
+#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
+#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
+#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
+#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
+#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
+#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
+
+/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
+#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
+#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
+#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
+#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
+#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
+
+/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
+#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
+#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */
+#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
+#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
+#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
+#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
+#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
+#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
+#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
+#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
+#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
+#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
+#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
+#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
+#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
+#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
+
+/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
+#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
+#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
+#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
+#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
+#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
+#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
+#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
+#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
+#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
+#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
+#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
+#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
+#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
+#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
+#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
+#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
+#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
+
+/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
+#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
+#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
+#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
+#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
+#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
+#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
+#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
+#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
+#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
+#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
+#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
+#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
+#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
+#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
+#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
+#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
+#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
+
+/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
+#define UART1_THR 0xFFC02000 /* Transmit Holding register */
+#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
+#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
+#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
+#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
+#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
+#define UART1_LCR 0xFFC0200C /* Line Control Register */
+#define UART1_MCR 0xFFC02010 /* Modem Control Register */
+#define UART1_LSR 0xFFC02014 /* Line Status Register */
+#define UART1_MSR 0xFFC02018 /* Modem Status Register */
+#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
+#define UART1_GCTL 0xFFC02024 /* Global Control Register */
+
+/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */
+/* For Mailboxes 0-15 */
+#define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */
+#define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */
+#define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */
+#define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */
+#define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */
+#define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */
+#define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */
+#define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */
+#define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */
+#define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */
+#define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */
+#define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */
+#define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmit reg 1 */
+
+/* For Mailboxes 16-31 */
+#define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */
+#define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */
+#define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */
+#define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */
+#define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */
+#define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */
+#define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */
+#define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */
+#define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */
+#define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */
+#define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */
+#define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */
+#define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmit reg 2 */
+
+/* CAN Configuration, Control, and Status Registers */
+#define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */
+#define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */
+#define CAN_DEBUG 0xFFC02A88 /* Debug Register */
+#define CAN_STATUS 0xFFC02A8C /* Global Status Register */
+#define CAN_CEC 0xFFC02A90 /* Error Counter Register */
+#define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */
+#define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */
+#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */
+#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */
+#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */
+#define CAN_SFCMVER 0xFFC02AA8 /* Version Code Register */
+#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */
+#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */
+#define CAN_ESR 0xFFC02AB4 /* Error Status Register */
+#define CAN_UCREG 0xFFC02AC0 /* Universal Counter Register/Capture Register */
+#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */
+#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Force Reload Register */
+#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */
+
+/* Mailbox Acceptance Masks */
+#define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */
+#define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */
+#define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */
+#define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */
+#define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */
+#define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */
+#define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */
+#define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */
+#define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */
+#define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */
+#define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */
+#define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */
+#define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */
+#define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */
+#define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */
+#define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */
+#define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */
+#define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */
+#define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */
+#define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */
+#define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */
+#define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */
+#define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */
+#define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */
+#define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */
+#define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */
+#define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */
+#define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */
+#define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */
+#define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */
+#define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */
+#define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */
+
+#define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */
+#define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */
+#define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */
+#define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */
+#define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */
+#define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */
+#define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */
+#define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */
+#define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */
+#define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */
+#define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */
+#define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */
+#define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */
+#define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */
+#define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */
+#define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */
+#define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */
+#define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */
+#define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */
+#define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */
+#define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */
+#define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */
+#define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */
+#define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */
+#define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */
+#define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */
+#define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */
+#define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */
+#define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */
+#define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */
+#define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */
+#define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */
+
+/* CAN Acceptance Mask Macros */
+#define CAN_AM_L(x) (CAN_AM00L+((x)*0x8))
+#define CAN_AM_H(x) (CAN_AM00H+((x)*0x8))
+
+/* Mailbox Registers */
+#define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */
+#define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */
+#define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */
+#define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */
+#define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */
+#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */
+#define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */
+#define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */
+
+#define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */
+#define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */
+#define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */
+#define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */
+#define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */
+#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */
+#define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */
+#define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */
+
+#define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */
+#define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */
+#define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */
+#define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */
+#define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */
+#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */
+#define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */
+#define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */
+
+#define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */
+#define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */
+#define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */
+#define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */
+#define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */
+#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */
+#define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */
+#define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */
+
+#define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */
+#define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */
+#define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */
+#define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */
+#define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */
+#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */
+#define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */
+#define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */
+
+#define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */
+#define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */
+#define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */
+#define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */
+#define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */
+#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */
+#define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */
+#define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */
+
+#define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */
+#define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */
+#define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */
+#define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */
+#define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */
+#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */
+#define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */
+#define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */
+
+#define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */
+#define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */
+#define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */
+#define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */
+#define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */
+#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */
+#define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */
+#define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */
+
+#define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */
+#define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */
+#define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */
+#define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */
+#define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */
+#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */
+#define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */
+#define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */
+
+#define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */
+#define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */
+#define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */
+#define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */
+#define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */
+#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */
+#define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */
+#define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */
+
+#define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */
+#define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */
+#define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */
+#define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */
+#define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */
+#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */
+#define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */
+#define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */
+
+#define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */
+#define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */
+#define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */
+#define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */
+#define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */
+#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */
+#define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */
+#define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */
+
+#define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */
+#define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */
+#define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */
+#define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */
+#define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */
+#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */
+#define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */
+#define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */
+
+#define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */
+#define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */
+#define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */
+#define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */
+#define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */
+#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */
+#define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */
+#define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */
+
+#define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */
+#define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */
+#define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */
+#define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */
+#define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */
+#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */
+#define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */
+#define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */
+
+#define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */
+#define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */
+#define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */
+#define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */
+#define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */
+#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */
+#define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */
+#define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */
+
+#define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */
+#define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */
+#define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */
+#define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */
+#define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */
+#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */
+#define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */
+#define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */
+
+#define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */
+#define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */
+#define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */
+#define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */
+#define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */
+#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */
+#define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */
+#define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */
+
+#define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */
+#define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */
+#define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */
+#define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */
+#define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */
+#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */
+#define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */
+#define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */
+
+#define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */
+#define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */
+#define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */
+#define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */
+#define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */
+#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */
+#define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */
+#define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */
+
+#define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */
+#define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */
+#define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */
+#define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */
+#define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */
+#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */
+#define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */
+#define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */
+
+#define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */
+#define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */
+#define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */
+#define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */
+#define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */
+#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */
+#define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */
+#define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */
+
+#define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */
+#define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */
+#define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */
+#define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */
+#define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */
+#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */
+#define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */
+#define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */
+
+#define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */
+#define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */
+#define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */
+#define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */
+#define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */
+#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */
+#define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */
+#define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */
+
+#define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */
+#define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */
+#define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */
+#define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */
+#define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */
+#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */
+#define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */
+#define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */
+
+#define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */
+#define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */
+#define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */
+#define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */
+#define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */
+#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */
+#define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */
+#define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */
+
+#define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */
+#define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */
+#define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */
+#define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */
+#define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */
+#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */
+#define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */
+#define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */
+
+#define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */
+#define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */
+#define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */
+#define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */
+#define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */
+#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */
+#define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */
+#define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */
+
+#define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */
+#define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */
+#define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */
+#define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */
+#define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */
+#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */
+#define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */
+#define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */
+
+#define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */
+#define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */
+#define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */
+#define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */
+#define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */
+#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */
+#define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */
+#define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */
+
+#define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */
+#define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */
+#define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */
+#define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */
+#define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */
+#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */
+#define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */
+#define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */
+
+#define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */
+#define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */
+#define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */
+#define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */
+#define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */
+#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */
+#define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */
+#define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */
+
+/* CAN Mailbox Area Macros */
+#define CAN_MB_ID1(x) (CAN_MB00_ID1+((x)*0x20))
+#define CAN_MB_ID0(x) (CAN_MB00_ID0+((x)*0x20))
+#define CAN_MB_TIMESTAMP(x) (CAN_MB00_TIMESTAMP+((x)*0x20))
+#define CAN_MB_LENGTH(x) (CAN_MB00_LENGTH+((x)*0x20))
+#define CAN_MB_DATA3(x) (CAN_MB00_DATA3+((x)*0x20))
+#define CAN_MB_DATA2(x) (CAN_MB00_DATA2+((x)*0x20))
+#define CAN_MB_DATA1(x) (CAN_MB00_DATA1+((x)*0x20))
+#define CAN_MB_DATA0(x) (CAN_MB00_DATA0+((x)*0x20))
+
+/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
+#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
+#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
+#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
+#define PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */
+
+/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
+#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
+#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
+#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
+#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */
+#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
+#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
+#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
+
+#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
+#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
+#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
+#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */
+#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
+#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
+#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
+
+/*
+ * System MMR Register Bits And Macros
+ *
+ * Disclaimer: All macros are intended to make C and Assembly code more readable.
+ * Use these macros carefully, as any that do left shifts for field
+ * depositing will result in the lower order bits being destroyed. Any
+ * macro that shifts left to properly position the bit-field should be
+ * used as part of an OR to initialize a register and NOT as a dynamic
+ * modifier UNLESS the lower order bits are saved and ORed back in when
+ * the macro is used.
+ */
+/*
+ * PLL AND RESET MASKS
+ * PLL_CTL Masks
+ */
+#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
+#define PLL_OFF 0x0002 /* PLL Not Powered */
+#define STOPCK 0x0008 /* Core Clock Off */
+#define PDWN 0x0020 /* Enter Deep Sleep Mode */
+#define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
+#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
+#define BYPASS 0x0100 /* Bypass the PLL */
+#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
+/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
+#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
+
+/* PLL_DIV Masks */
+#define SSEL 0x000F /* System Select */
+#define CSEL 0x0030 /* Core Select */
+#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
+#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
+#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
+#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
+
+#define CCLK_DIV1 CSEL_DIV1
+#define CCLK_DIV2 CSEL_DIV2
+#define CCLK_DIV4 CSEL_DIV4
+#define CCLK_DIV8 CSEL_DIV8
+/* PLL_DIV Macros */
+#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
+
+/* VR_CTL Masks */
+#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
+#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
+#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
+#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
+#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
+
+#define GAIN 0x000C /* Voltage Level Gain */
+#define GAIN_5 0x0000 /* GAIN = 5 */
+#define GAIN_10 0x0004 /* GAIN = 10 */
+#define GAIN_20 0x0008 /* GAIN = 20 */
+#define GAIN_50 0x000C /* GAIN = 50 */
+
+#define VLEV 0x00F0 /* Internal Voltage Level */
+#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
+#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
+#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
+#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
+#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
+#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
+#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
+#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
+#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
+#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
+
+#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
+#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */
+#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
+#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
+#define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */
+#define CKELOW 0x8000 /* Enable Drive CKE Low During Reset */
+
+/* PLL_STAT Masks */
+#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
+#define FULL_ON 0x0002 /* Processor In Full On Mode */
+#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
+#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
+
+/* SWRST Masks */
+#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
+#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
+#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
+#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
+#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
+
+/* SYSCR Masks */
+#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
+#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
+
+/*
+ * SYSTEM INTERRUPT CONTROLLER MASKS
+ */
+/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
+#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */
+#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
+#define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
+#define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */
+#define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */
+#define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */
+#define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */
+#define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */
+
+#define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */
+#define IRQ_TWI 0x00000200 /* TWI Interrupt */
+#define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */
+#define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */
+#define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */
+#define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */
+#define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */
+#define IRQ_CAN_RX 0x00008000 /* CAN Receive Interrupt */
+
+#define IRQ_CAN_TX 0x00010000 /* CAN Transmit Interrupt */
+#define IRQ_DMA1 0x00020000 /* DMA Channel 1 (Ethernet RX) Interrupt */
+#define IRQ_PFA_PORTH 0x00020000 /* PF Port H (PF47:32) Interrupt A */
+#define IRQ_DMA2 0x00040000 /* DMA Channel 2 (Ethernet TX) Interrupt */
+#define IRQ_PFB_PORTH 0x00040000 /* PF Port H (PF47:32) Interrupt B */
+#define IRQ_TIMER0 0x00080000 /* Timer 0 Interrupt */
+#define IRQ_TIMER1 0x00100000 /* Timer 1 Interrupt */
+#define IRQ_TIMER2 0x00200000 /* Timer 2 Interrupt */
+#define IRQ_TIMER3 0x00400000 /* Timer 3 Interrupt */
+#define IRQ_TIMER4 0x00800000 /* Timer 4 Interrupt */
+
+#define IRQ_TIMER5 0x01000000 /* Timer 5 Interrupt */
+#define IRQ_TIMER6 0x02000000 /* Timer 6 Interrupt */
+#define IRQ_TIMER7 0x04000000 /* Timer 7 Interrupt */
+#define IRQ_PFA_PORTFG 0x08000000 /* PF Ports F&G (PF31:0) Interrupt A */
+#define IRQ_PFB_PORTF 0x80000000 /* PF Port F (PF15:0) Interrupt B */
+#define IRQ_DMA12 0x20000000 /* DMA Channels 12 (MDMA1 Source) RX Interrupt */
+#define IRQ_DMA13 0x20000000 /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
+#define IRQ_DMA14 0x40000000 /* DMA Channels 14 (MDMA0 Source) RX Interrupt */
+#define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
+#define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */
+#define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */
+
+/* SIC_IAR0 Macros */
+#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
+#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
+#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
+#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
+#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
+#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
+#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
+#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
+
+/* SIC_IAR1 Macros */
+#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
+#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
+#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
+#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */
+#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
+#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
+#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
+#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
+
+/* SIC_IAR2 Macros */
+#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */
+#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
+#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
+#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */
+#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
+#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
+#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
+#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
+
+/* SIC_IAR3 Macros */
+#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */
+#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */
+#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */
+#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */
+#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */
+#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */
+#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */
+#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */
+
+/* SIC_IMASK Masks */
+#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
+#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
+#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
+#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
+
+/* SIC_IWR Masks */
+#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
+#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
+#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
+#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
+
+/* ********* WATCHDOG TIMER MASKS ******************** */
+
+/* Watchdog Timer WDOG_CTL Register Masks */
+
+#define WDEV(x) ((x<<1) & 0x0006) /* event generated on roll over */
+#define WDEV_RESET 0x0000 /* generate reset event on roll over */
+#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
+#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
+#define WDEV_NONE 0x0006 /* no event on roll over */
+#define WDEN 0x0FF0 /* enable watchdog */
+#define WDDIS 0x0AD0 /* disable watchdog */
+#define WDRO 0x8000 /* watchdog rolled over latch */
+
+/* depreciated WDOG_CTL Register Masks for legacy code */
+
+#define ICTL WDEV
+#define ENABLE_RESET WDEV_RESET
+#define WDOG_RESET WDEV_RESET
+#define ENABLE_NMI WDEV_NMI
+#define WDOG_NMI WDEV_NMI
+#define ENABLE_GPI WDEV_GPI
+#define WDOG_GPI WDEV_GPI
+#define DISABLE_EVT WDEV_NONE
+#define WDOG_NONE WDEV_NONE
+
+#define TMR_EN WDEN
+#define TMR_DIS WDDIS
+#define TRO WDRO
+#define ICTL_P0 0x01
+#define ICTL_P1 0x02
+#define TRO_P 0x0F
+
+/*
+ * REAL TIME CLOCK MASKS
+ */
+/* RTC_STAT and RTC_ALARM Masks */
+#define RTC_SEC 0x0000003F /* Real-Time Clock Seconds */
+#define RTC_MIN 0x00000FC0 /* Real-Time Clock Minutes */
+#define RTC_HR 0x0001F000 /* Real-Time Clock Hours */
+#define RTC_DAY 0xFFFE0000 /* Real-Time Clock Days */
+
+/*
+ * RTC_ALARM Macro
+ * z=day y=hr x=min w=sec
+ */
+#define SET_ALARM(z,y,x,w) ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
+
+/* RTC_ICTL and RTC_ISTAT Masks */
+#define STOPWATCH 0x0001 /* Stopwatch Interrupt Enable */
+#define ALARM 0x0002 /* Alarm Interrupt Enable */
+#define SECOND 0x0004 /* Seconds (1 Hz) Interrupt Enable */
+#define MINUTE 0x0008 /* Minutes Interrupt Enable */
+#define HOUR 0x0010 /* Hours Interrupt Enable */
+#define DAY 0x0020 /* 24 Hours (Days) Interrupt Enable */
+#define DAY_ALARM 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
+#define WRITE_PENDING 0x4000 /* Write Pending Status */
+#define WRITE_COMPLETE 0x8000 /* Write Complete Interrupt Enable */
+
+/* RTC_FAST / RTC_PREN Mask */
+#define PREN 0x0001 /* Enable Prescaler, RTC Runs @1 Hz */
+
+/*
+ * UART CONTROLLER MASKS
+ */
+/* UARTx_LCR Masks */
+#define WLS(x) ((((x)&0x3)-5) & 0x03) /* Word Length Select */
+#define STB 0x04 /* Stop Bits */
+#define PEN 0x08 /* Parity Enable */
+#define EPS 0x10 /* Even Parity Select */
+#define STP 0x20 /* Stick Parity */
+#define SB 0x40 /* Set Break */
+#define DLAB 0x80 /* Divisor Latch Access */
+
+/* UARTx_MCR Mask */
+#define LOOP 0x10 /* Loopback Mode Enable */
+
+/* UARTx_LSR Masks */
+#define DR 0x01 /* Data Ready */
+#define OE 0x02 /* Overrun Error */
+#define PE 0x04 /* Parity Error */
+#define FE 0x08 /* Framing Error */
+#define BI 0x10 /* Break Interrupt */
+#define THRE 0x20 /* THR Empty */
+#define TEMT 0x40 /* TSR and UART_THR Empty */
+
+/* UARTx_IER Masks */
+#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
+#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
+#define ELSI 0x04 /* Enable RX Status Interrupt */
+
+/* UARTx_IIR Masks */
+#define NINT 0x01 /* Pending Interrupt */
+#define STATUS 0x06 /* Highest Priority Pending Interrupt */
+
+/* UARTx_GCTL Masks */
+#define UCEN 0x01 /* Enable UARTx Clocks */
+#define IREN 0x02 /* Enable IrDA Mode */
+#define TPOLC 0x04 /* IrDA TX Polarity Change */
+#define RPOLC 0x08 /* IrDA RX Polarity Change */
+#define FPE 0x10 /* Force Parity Error On Transmit */
+#define FFE 0x20 /* Force Framing Error On Transmit */
+
+/*
+ * SERIAL PERIPHERAL INTERFACE (SPI) MASKS
+ */
+/* SPI_CTL Masks */
+#define TIMOD 0x0003 /* Transfer Initiate Mode */
+#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
+#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
+#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
+#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
+#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */
+#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
+#define PSSE 0x0010 /* Slave-Select Input Enable */
+#define EMISO 0x0020 /* Enable MISO As Output */
+#define SIZE 0x0100 /* Size of Words (16/8* Bits) */
+#define LSBF 0x0200 /* LSB First */
+#define CPHA 0x0400 /* Clock Phase */
+#define CPOL 0x0800 /* Clock Polarity */
+#define MSTR 0x1000 /* Master/Slave* */
+#define WOM 0x2000 /* Write Open Drain Master */
+#define SPE 0x4000 /* SPI Enable */
+
+/* SPI_FLG Masks */
+#define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */
+#define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */
+#define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */
+#define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */
+#define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */
+#define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */
+#define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */
+#define FLG1 0xFDFF /* Activates SPI_FLOUT1 */
+#define FLG2 0xFBFF /* Activates SPI_FLOUT2 */
+#define FLG3 0xF7FF /* Activates SPI_FLOUT3 */
+#define FLG4 0xEFFF /* Activates SPI_FLOUT4 */
+#define FLG5 0xDFFF /* Activates SPI_FLOUT5 */
+#define FLG6 0xBFFF /* Activates SPI_FLOUT6 */
+#define FLG7 0x7FFF /* Activates SPI_FLOUT7 */
+
+/* SPI_STAT Masks */
+#define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */
+#define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */
+#define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */
+#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */
+#define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */
+#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */
+#define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */
+
+/*
+ * GENERAL PURPOSE TIMER MASKS
+ */
+/* TIMER_ENABLE Masks */
+#define TIMEN0 0x0001 /* Enable Timer 0 */
+#define TIMEN1 0x0002 /* Enable Timer 1 */
+#define TIMEN2 0x0004 /* Enable Timer 2 */
+#define TIMEN3 0x0008 /* Enable Timer 3 */
+#define TIMEN4 0x0010 /* Enable Timer 4 */
+#define TIMEN5 0x0020 /* Enable Timer 5 */
+#define TIMEN6 0x0040 /* Enable Timer 6 */
+#define TIMEN7 0x0080 /* Enable Timer 7 */
+
+/* TIMER_DISABLE Masks */
+#define TIMDIS0 TIMEN0 /* Disable Timer 0 */
+#define TIMDIS1 TIMEN1 /* Disable Timer 1 */
+#define TIMDIS2 TIMEN2 /* Disable Timer 2 */
+#define TIMDIS3 TIMEN3 /* Disable Timer 3 */
+#define TIMDIS4 TIMEN4 /* Disable Timer 4 */
+#define TIMDIS5 TIMEN5 /* Disable Timer 5 */
+#define TIMDIS6 TIMEN6 /* Disable Timer 6 */
+#define TIMDIS7 TIMEN7 /* Disable Timer 7 */
+
+/* TIMER_STATUS Masks */
+#define TIMIL0 0x00000001 /* Timer 0 Interrupt */
+#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
+#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
+#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
+#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
+#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
+#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
+#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
+#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
+#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
+#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
+#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */
+#define TIMIL4 0x00010000 /* Timer 4 Interrupt */
+#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
+#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
+#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
+#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
+#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
+#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
+#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
+#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
+#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
+#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
+#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
+
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define TOVL_ERR0 TOVF_ERR0
+#define TOVL_ERR1 TOVF_ERR1
+#define TOVL_ERR2 TOVF_ERR2
+#define TOVL_ERR3 TOVF_ERR3
+#define TOVL_ERR4 TOVF_ERR4
+#define TOVL_ERR5 TOVF_ERR5
+#define TOVL_ERR6 TOVF_ERR6
+#define TOVL_ERR7 TOVF_ERR7
+
+/* TIMERx_CONFIG Masks */
+#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
+#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
+#define EXT_CLK 0x0003 /* External Clock Mode */
+#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */
+#define PERIOD_CNT 0x0008 /* Period Count */
+#define IRQ_ENA 0x0010 /* Interrupt Request Enable */
+#define TIN_SEL 0x0020 /* Timer Input Select */
+#define OUT_DIS 0x0040 /* Output Pad Disable */
+#define CLK_SEL 0x0080 /* Timer Clock Select */
+#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */
+#define EMU_RUN 0x0200 /* Emulation Behavior Select */
+#define ERR_TYP 0xC000 /* Error Type */
+
+/*
+ * GPIO PORTS F, G, H MASKS
+ * General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks
+ */
+/* Port F Masks */
+#define PF0 0x0001
+#define PF1 0x0002
+#define PF2 0x0004
+#define PF3 0x0008
+#define PF4 0x0010
+#define PF5 0x0020
+#define PF6 0x0040
+#define PF7 0x0080
+#define PF8 0x0100
+#define PF9 0x0200
+#define PF10 0x0400
+#define PF11 0x0800
+#define PF12 0x1000
+#define PF13 0x2000
+#define PF14 0x4000
+#define PF15 0x8000
+
+/* Port G Masks */
+#define PG0 0x0001
+#define PG1 0x0002
+#define PG2 0x0004
+#define PG3 0x0008
+#define PG4 0x0010
+#define PG5 0x0020
+#define PG6 0x0040
+#define PG7 0x0080
+#define PG8 0x0100
+#define PG9 0x0200
+#define PG10 0x0400
+#define PG11 0x0800
+#define PG12 0x1000
+#define PG13 0x2000
+#define PG14 0x4000
+#define PG15 0x8000
+
+/* Port H Masks */
+#define PH0 0x0001
+#define PH1 0x0002
+#define PH2 0x0004
+#define PH3 0x0008
+#define PH4 0x0010
+#define PH5 0x0020
+#define PH6 0x0040
+#define PH7 0x0080
+#define PH8 0x0100
+#define PH9 0x0200
+#define PH10 0x0400
+#define PH11 0x0800
+#define PH12 0x1000
+#define PH13 0x2000
+#define PH14 0x4000
+#define PH15 0x8000
+
+/*
+ * SERIAL PORT MASKS
+ */
+/* SPORTx_TCR1 Masks */
+#define TSPEN 0x0001 /* Transmit Enable */
+#define ITCLK 0x0002 /* Internal Transmit Clock Select */
+#define DTYPE_NORM 0x0004 /* Data Format Normal */
+#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
+#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
+#define TLSBIT 0x0010 /* Transmit Bit Order */
+#define ITFS 0x0200 /* Internal Transmit Frame Sync Select */
+#define TFSR 0x0400 /* Transmit Frame Sync Required Select */
+#define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */
+#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
+#define LATFS 0x2000 /* Late Transmit Frame Sync Select */
+#define TCKFE 0x4000 /* Clock Falling Edge Select */
+
+/* SPORTx_TCR2 Masks and Macro */
+#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
+#define TXSE 0x0100 /* TX Secondary Enable */
+#define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */
+#define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */
+
+/* SPORTx_RCR1 Masks */
+#define RSPEN 0x0001 /* Receive Enable */
+#define IRCLK 0x0002 /* Internal Receive Clock Select */
+#define DTYPE_NORM 0x0004 /* Data Format Normal */
+#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
+#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
+#define RLSBIT 0x0010 /* Receive Bit Order */
+#define IRFS 0x0200 /* Internal Receive Frame Sync Select */
+#define RFSR 0x0400 /* Receive Frame Sync Required Select */
+#define LRFS 0x1000 /* Low Receive Frame Sync Select */
+#define LARFS 0x2000 /* Late Receive Frame Sync Select */
+#define RCKFE 0x4000 /* Clock Falling Edge Select */
+
+/* SPORTx_RCR2 Masks */
+#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
+#define RXSE 0x0100 /* RX Secondary Enable */
+#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
+#define RRFST 0x0400 /* Right-First Data Order */
+
+/* SPORTx_STAT Masks */
+#define RXNE 0x0001 /* Receive FIFO Not Empty Status */
+#define RUVF 0x0002 /* Sticky Receive Underflow Status */
+#define ROVF 0x0004 /* Sticky Receive Overflow Status */
+#define TXF 0x0008 /* Transmit FIFO Full Status */
+#define TUVF 0x0010 /* Sticky Transmit Underflow Status */
+#define TOVF 0x0020 /* Sticky Transmit Overflow Status */
+#define TXHRE 0x0040 /* Transmit Hold Register Empty */
+
+/* SPORTx_MCMC1 Macros */
+#define WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
+
+/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
+#define WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
+
+/* SPORTx_MCMC2 Masks */
+#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
+#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
+#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
+#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
+#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
+#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
+#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
+#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
+#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
+#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
+#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
+#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
+#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
+#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
+#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
+#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
+#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
+#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
+#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
+#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
+#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
+#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
+#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
+
+/*
+ * ASYNCHRONOUS MEMORY CONTROLLER MASKS
+ */
+/* EBIU_AMGCTL Masks */
+#define AMCKEN 0x0001 /* Enable CLKOUT */
+#define AMBEN_NONE 0x0000 /* All Banks Disabled */
+#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
+#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
+#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
+#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
+
+/* EBIU_AMBCTL0 Masks */
+#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */
+#define B0RDYPOL 0x00000002 /* B0 RDY Active High */
+#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */
+#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
+#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
+#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
+#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
+#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
+#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
+#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
+#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
+#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
+#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
+#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
+#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */
+#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
+#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
+#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
+#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
+#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
+#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
+#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
+#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
+#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
+#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
+#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
+#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
+#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
+#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
+#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */
+#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
+#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
+#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
+#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
+#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
+#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
+#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
+#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
+#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
+#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
+#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
+#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
+#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
+#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
+
+#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */
+#define B1RDYPOL 0x00020000 /* B1 RDY Active High */
+#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */
+#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
+#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
+#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
+#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */
+#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
+#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
+#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
+#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
+#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
+#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
+#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
+#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */
+#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
+#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
+#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
+#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
+#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
+#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
+#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
+#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
+#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
+#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
+#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
+#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
+#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
+#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
+#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */
+#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
+#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
+#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
+#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
+#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
+#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
+#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
+#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
+#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
+#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
+#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
+#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
+#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
+#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
+
+/* EBIU_AMBCTL1 Masks */
+#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
+#define B2RDYPOL 0x00000002 /* B2 RDY Active High */
+#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
+#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
+#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
+#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
+#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
+#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
+#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
+#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
+#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
+#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
+#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
+#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
+#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
+#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
+#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
+#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
+#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
+#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
+#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
+#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
+#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
+#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
+#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
+#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
+#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
+#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
+#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
+#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
+#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
+#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
+#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
+#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
+#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
+#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
+#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
+#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
+#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
+#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
+#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
+#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
+#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
+#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
+
+#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */
+#define B3RDYPOL 0x00020000 /* B3 RDY Active High */
+#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */
+#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
+#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
+#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
+#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */
+#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
+#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
+#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
+#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
+#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
+#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
+#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
+#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */
+#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
+#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
+#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
+#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
+#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
+#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
+#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
+#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
+#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
+#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
+#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
+#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
+#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
+#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
+#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */
+#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
+#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
+#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
+#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
+#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
+#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
+#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
+#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
+#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
+#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
+#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
+#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
+#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
+#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
+
+/*
+ * SDRAM CONTROLLER MASKS
+ */
+/* EBIU_SDGCTL Masks */
+#define SCTLE 0x00000001 /* Enable SDRAM Signals */
+#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
+#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
+#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
+#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
+#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
+#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
+#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
+#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
+#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
+#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
+#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
+#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
+#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
+#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
+#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
+#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
+#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
+#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
+#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
+#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
+#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
+#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
+#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
+#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
+#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
+#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
+#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
+#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
+#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
+#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
+#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
+#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
+#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
+#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
+#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
+#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
+#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
+#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
+#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
+#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
+#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */
+#define EBUFE 0x02000000 /* Enable External Buffering Timing */
+#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
+#define EMREN 0x10000000 /* Extended Mode Register Enable */
+#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
+#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */
+
+/* EBIU_SDBCTL Masks */
+#define EBE 0x0001 /* Enable SDRAM External Bank */
+#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */
+#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
+#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
+#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
+#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
+#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
+#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
+#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
+
+/* EBIU_SDSTAT Masks */
+#define SDCI 0x0001 /* SDRAM Controller Idle */
+#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
+#define SDPUA 0x0004 /* SDRAM Power-Up Active */
+#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
+#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */
+#define BGSTAT 0x0020 /* Bus Grant Status */
+
+/*
+ * DMA CONTROLLER MASKS
+ */
+/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
+#define DMAEN 0x0001 /* DMA Channel Enable */
+#define WNR 0x0002 /* Channel Direction (W/R*) */
+#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
+#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
+#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
+#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
+#define RESTART 0x0020 /* DMA Buffer Clear */
+#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
+#define DI_EN 0x0080 /* Data Interrupt Enable */
+#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
+#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
+#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
+#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
+#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
+#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
+#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
+#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
+#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
+#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
+#define FLOW_STOP 0x0000 /* Stop Mode */
+#define FLOW_AUTO 0x1000 /* Autobuffer Mode */
+#define FLOW_ARRAY 0x4000 /* Descriptor Array Mode */
+#define FLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
+#define FLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
+
+/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
+#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
+#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
+#define PMAP_PPI 0x0000 /* PPI Port DMA */
+#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */
+#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */
+#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */
+#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */
+#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */
+#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */
+#define PMAP_SPI 0x7000 /* SPI Port DMA */
+#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */
+#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
+#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
+#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
+
+/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
+#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
+#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
+#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
+#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
+
+/*
+ * PARALLEL PERIPHERAL INTERFACE (PPI) MASKS
+ */
+/* PPI_CONTROL Masks */
+#define PORT_EN 0x0001 /* PPI Port Enable */
+#define PORT_DIR 0x0002 /* PPI Port Direction */
+#define XFR_TYPE 0x000C /* PPI Transfer Type */
+#define PORT_CFG 0x0030 /* PPI Port Configuration */
+#define FLD_SEL 0x0040 /* PPI Active Field Select */
+#define PACK_EN 0x0080 /* PPI Packing Mode */
+#define DMA32 0x0100 /* PPI 32-bit DMA Enable */
+#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
+#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
+#define DLEN_8 0x0000 /* Data Length = 8 Bits */
+#define DLEN_10 0x0800 /* Data Length = 10 Bits */
+#define DLEN_11 0x1000 /* Data Length = 11 Bits */
+#define DLEN_12 0x1800 /* Data Length = 12 Bits */
+#define DLEN_13 0x2000 /* Data Length = 13 Bits */
+#define DLEN_14 0x2800 /* Data Length = 14 Bits */
+#define DLEN_15 0x3000 /* Data Length = 15 Bits */
+#define DLEN_16 0x3800 /* Data Length = 16 Bits */
+#define POLC 0x4000 /* PPI Clock Polarity */
+#define POLS 0x8000 /* PPI Frame Sync Polarity */
+
+/* PPI_STATUS Masks */
+#define FLD 0x0400 /* Field Indicator */
+#define FT_ERR 0x0800 /* Frame Track Error */
+#define OVR 0x1000 /* FIFO Overflow Error */
+#define UNDR 0x2000 /* FIFO Underrun Error */
+#define ERR_DET 0x4000 /* Error Detected Indicator */
+#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
+
+/*
+ * TWO-WIRE INTERFACE (TWI) MASKS
+ */
+/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
+#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
+#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
+
+/* TWI_PRESCALE Masks */
+#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
+#define TWI_ENA 0x0080 /* TWI Enable */
+#define SCCB 0x0200 /* SCCB Compatibility Enable */
+
+/* TWI_SLAVE_CTRL Masks */
+#define SEN 0x0001 /* Slave Enable */
+#define SADD_LEN 0x0002 /* Slave Address Length */
+#define STDVAL 0x0004 /* Slave Transmit Data Valid */
+#define TSC_NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
+#define GEN 0x0010 /* General Call Adrress Matching Enabled */
+
+/* TWI_SLAVE_STAT Masks */
+#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
+#define GCALL 0x0002 /* General Call Indicator */
+
+/* TWI_MASTER_CTRL Masks */
+#define MEN 0x0001 /* Master Mode Enable */
+#define MADD_LEN 0x0002 /* Master Address Length */
+#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
+#define FAST 0x0008 /* Use Fast Mode Timing Specs */
+#define STOP 0x0010 /* Issue Stop Condition */
+#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
+#define DCNT 0x3FC0 /* Data Bytes To Transfer */
+#define SDAOVR 0x4000 /* Serial Data Override */
+#define SCLOVR 0x8000 /* Serial Clock Override */
+
+/* TWI_MASTER_STAT Masks */
+#define MPROG 0x0001 /* Master Transfer In Progress */
+#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
+#define ANAK 0x0004 /* Address Not Acknowledged */
+#define DNAK 0x0008 /* Data Not Acknowledged */
+#define BUFRDERR 0x0010 /* Buffer Read Error */
+#define BUFWRERR 0x0020 /* Buffer Write Error */
+#define SDASEN 0x0040 /* Serial Data Sense */
+#define SCLSEN 0x0080 /* Serial Clock Sense */
+#define BUSBUSY 0x0100 /* Bus Busy Indicator */
+
+/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
+#define SINIT 0x0001 /* Slave Transfer Initiated */
+#define SCOMP 0x0002 /* Slave Transfer Complete */
+#define SERR 0x0004 /* Slave Transfer Error */
+#define SOVF 0x0008 /* Slave Overflow */
+#define MCOMP 0x0010 /* Master Transfer Complete */
+#define MERR 0x0020 /* Master Transfer Error */
+#define XMTSERV 0x0040 /* Transmit FIFO Service */
+#define RCVSERV 0x0080 /* Receive FIFO Service */
+
+/* TWI_FIFO_CTRL Masks */
+#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
+#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
+#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
+#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
+
+/* TWI_FIFO_STAT Masks */
+#define XMTSTAT 0x0003 /* Transmit FIFO Status */
+#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
+#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
+#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
+
+#define RCVSTAT 0x000C /* Receive FIFO Status */
+#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
+#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
+#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
+
+/*
+ * CONTROLLER AREA NETWORK (CAN) MASKS
+ */
+/* CAN_CONTROL Masks */
+#define SRS 0x0001 /* Software Reset */
+#define DNM 0x0002 /* Device Net Mode */
+#define ABO 0x0004 /* Auto-Bus On Enable */
+#define TXPRIO 0x0008 /* TX Priority (Priority/Mailbox*) */
+#define WBA 0x0010 /* Wake-Up On CAN Bus Activity Enable */
+#define SMR 0x0020 /* Sleep Mode Request */
+#define CSR 0x0040 /* CAN Suspend Mode Request */
+#define CCR 0x0080 /* CAN Configuration Mode Request */
+
+/* CAN_STATUS Masks */
+#define WT 0x0001 /* TX Warning Flag */
+#define WR 0x0002 /* RX Warning Flag */
+#define EP 0x0004 /* Error Passive Mode */
+#define EBO 0x0008 /* Error Bus Off Mode */
+#define SMA 0x0020 /* Sleep Mode Acknowledge */
+#define CSA 0x0040 /* Suspend Mode Acknowledge */
+#define CCA 0x0080 /* Configuration Mode Acknowledge */
+#define MBPTR 0x1F00 /* Mailbox Pointer */
+#define TRM 0x4000 /* Transmit Mode */
+#define REC 0x8000 /* Receive Mode */
+
+/* CAN_CLOCK Masks */
+#define BRP 0x03FF /* Bit-Rate Pre-Scaler */
+
+/* CAN_TIMING Masks */
+#define TSEG1 0x000F /* Time Segment 1 */
+#define TSEG2 0x0070 /* Time Segment 2 */
+#define SAM 0x0080 /* Sampling */
+#define SJW 0x0300 /* Synchronization Jump Width */
+
+/* CAN_DEBUG Masks */
+#define DEC 0x0001 /* Disable CAN Error Counters */
+#define DRI 0x0002 /* Disable CAN RX Input */
+#define DTO 0x0004 /* Disable CAN TX Output */
+#define DIL 0x0008 /* Disable CAN Internal Loop */
+#define MAA 0x0010 /* Mode Auto-Acknowledge Enable */
+#define MRB 0x0020 /* Mode Read Back Enable */
+#define CDE 0x8000 /* CAN Debug Enable */
+
+/* CAN_CEC Masks */
+#define RXECNT 0x00FF /* Receive Error Counter */
+#define TXECNT 0xFF00 /* Transmit Error Counter */
+
+/* CAN_INTR Masks */
+#define MBRIF 0x0001 /* Mailbox Receive Interrupt */
+#define MBTIF 0x0002 /* Mailbox Transmit Interrupt */
+#define GIRQ 0x0004 /* Global Interrupt */
+#define SMACK 0x0008 /* Sleep Mode Acknowledge */
+#define CANTX 0x0040 /* CAN TX Bus Value */
+#define CANRX 0x0080 /* CAN RX Bus Value */
+
+/* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks */
+#define DFC 0xFFFF /* Data Filtering Code (If Enabled) (ID0) */
+#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (ID0) */
+#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (ID1) */
+#define BASEID 0x1FFC /* Base Identifier */
+#define IDE 0x2000 /* Identifier Extension */
+#define RTR 0x4000 /* Remote Frame Transmission Request */
+#define AME 0x8000 /* Acceptance Mask Enable */
+
+/* CAN_MBxx_TIMESTAMP Masks */
+#define TSV 0xFFFF /* Timestamp */
+
+/* CAN_MBxx_LENGTH Masks */
+#define DLC 0x000F /* Data Length Code */
+
+/* CAN_AMxxH and CAN_AMxxL Masks */
+#define DFM 0xFFFF /* Data Field Mask (If Enabled) (CAN_AMxxL) */
+#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (CAN_AMxxL) */
+#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (CAN_AMxxH) */
+#define BASEID 0x1FFC /* Base Identifier */
+#define AMIDE 0x2000 /* Acceptance Mask ID Extension Enable */
+#define FMD 0x4000 /* Full Mask Data Field Enable */
+#define FDF 0x8000 /* Filter On Data Field Enable */
+
+/* CAN_MC1 Masks */
+#define MC0 0x0001 /* Enable Mailbox 0 */
+#define MC1 0x0002 /* Enable Mailbox 1 */
+#define MC2 0x0004 /* Enable Mailbox 2 */
+#define MC3 0x0008 /* Enable Mailbox 3 */
+#define MC4 0x0010 /* Enable Mailbox 4 */
+#define MC5 0x0020 /* Enable Mailbox 5 */
+#define MC6 0x0040 /* Enable Mailbox 6 */
+#define MC7 0x0080 /* Enable Mailbox 7 */
+#define MC8 0x0100 /* Enable Mailbox 8 */
+#define MC9 0x0200 /* Enable Mailbox 9 */
+#define MC10 0x0400 /* Enable Mailbox 10 */
+#define MC11 0x0800 /* Enable Mailbox 11 */
+#define MC12 0x1000 /* Enable Mailbox 12 */
+#define MC13 0x2000 /* Enable Mailbox 13 */
+#define MC14 0x4000 /* Enable Mailbox 14 */
+#define MC15 0x8000 /* Enable Mailbox 15 */
+
+/* CAN_MC2 Masks */
+#define MC16 0x0001 /* Enable Mailbox 16 */
+#define MC17 0x0002 /* Enable Mailbox 17 */
+#define MC18 0x0004 /* Enable Mailbox 18 */
+#define MC19 0x0008 /* Enable Mailbox 19 */
+#define MC20 0x0010 /* Enable Mailbox 20 */
+#define MC21 0x0020 /* Enable Mailbox 21 */
+#define MC22 0x0040 /* Enable Mailbox 22 */
+#define MC23 0x0080 /* Enable Mailbox 23 */
+#define MC24 0x0100 /* Enable Mailbox 24 */
+#define MC25 0x0200 /* Enable Mailbox 25 */
+#define MC26 0x0400 /* Enable Mailbox 26 */
+#define MC27 0x0800 /* Enable Mailbox 27 */
+#define MC28 0x1000 /* Enable Mailbox 28 */
+#define MC29 0x2000 /* Enable Mailbox 29 */
+#define MC30 0x4000 /* Enable Mailbox 30 */
+#define MC31 0x8000 /* Enable Mailbox 31 */
+
+/* CAN_MD1 Masks */
+#define MD0 0x0001 /* Enable Mailbox 0 For Receive */
+#define MD1 0x0002 /* Enable Mailbox 1 For Receive */
+#define MD2 0x0004 /* Enable Mailbox 2 For Receive */
+#define MD3 0x0008 /* Enable Mailbox 3 For Receive */
+#define MD4 0x0010 /* Enable Mailbox 4 For Receive */
+#define MD5 0x0020 /* Enable Mailbox 5 For Receive */
+#define MD6 0x0040 /* Enable Mailbox 6 For Receive */
+#define MD7 0x0080 /* Enable Mailbox 7 For Receive */
+#define MD8 0x0100 /* Enable Mailbox 8 For Receive */
+#define MD9 0x0200 /* Enable Mailbox 9 For Receive */
+#define MD10 0x0400 /* Enable Mailbox 10 For Receive */
+#define MD11 0x0800 /* Enable Mailbox 11 For Receive */
+#define MD12 0x1000 /* Enable Mailbox 12 For Receive */
+#define MD13 0x2000 /* Enable Mailbox 13 For Receive */
+#define MD14 0x4000 /* Enable Mailbox 14 For Receive */
+#define MD15 0x8000 /* Enable Mailbox 15 For Receive */
+
+/* CAN_MD2 Masks */
+#define MD16 0x0001 /* Enable Mailbox 16 For Receive */
+#define MD17 0x0002 /* Enable Mailbox 17 For Receive */
+#define MD18 0x0004 /* Enable Mailbox 18 For Receive */
+#define MD19 0x0008 /* Enable Mailbox 19 For Receive */
+#define MD20 0x0010 /* Enable Mailbox 20 For Receive */
+#define MD21 0x0020 /* Enable Mailbox 21 For Receive */
+#define MD22 0x0040 /* Enable Mailbox 22 For Receive */
+#define MD23 0x0080 /* Enable Mailbox 23 For Receive */
+#define MD24 0x0100 /* Enable Mailbox 24 For Receive */
+#define MD25 0x0200 /* Enable Mailbox 25 For Receive */
+#define MD26 0x0400 /* Enable Mailbox 26 For Receive */
+#define MD27 0x0800 /* Enable Mailbox 27 For Receive */
+#define MD28 0x1000 /* Enable Mailbox 28 For Receive */
+#define MD29 0x2000 /* Enable Mailbox 29 For Receive */
+#define MD30 0x4000 /* Enable Mailbox 30 For Receive */
+#define MD31 0x8000 /* Enable Mailbox 31 For Receive */
+
+/* CAN_RMP1 Masks */
+#define RMP0 0x0001 /* RX Message Pending In Mailbox 0 */
+#define RMP1 0x0002 /* RX Message Pending In Mailbox 1 */
+#define RMP2 0x0004 /* RX Message Pending In Mailbox 2 */
+#define RMP3 0x0008 /* RX Message Pending In Mailbox 3 */
+#define RMP4 0x0010 /* RX Message Pending In Mailbox 4 */
+#define RMP5 0x0020 /* RX Message Pending In Mailbox 5 */
+#define RMP6 0x0040 /* RX Message Pending In Mailbox 6 */
+#define RMP7 0x0080 /* RX Message Pending In Mailbox 7 */
+#define RMP8 0x0100 /* RX Message Pending In Mailbox 8 */
+#define RMP9 0x0200 /* RX Message Pending In Mailbox 9 */
+#define RMP10 0x0400 /* RX Message Pending In Mailbox 10 */
+#define RMP11 0x0800 /* RX Message Pending In Mailbox 11 */
+#define RMP12 0x1000 /* RX Message Pending In Mailbox 12 */
+#define RMP13 0x2000 /* RX Message Pending In Mailbox 13 */
+#define RMP14 0x4000 /* RX Message Pending In Mailbox 14 */
+#define RMP15 0x8000 /* RX Message Pending In Mailbox 15 */
+
+/* CAN_RMP2 Masks */
+#define RMP16 0x0001 /* RX Message Pending In Mailbox 16 */
+#define RMP17 0x0002 /* RX Message Pending In Mailbox 17 */
+#define RMP18 0x0004 /* RX Message Pending In Mailbox 18 */
+#define RMP19 0x0008 /* RX Message Pending In Mailbox 19 */
+#define RMP20 0x0010 /* RX Message Pending In Mailbox 20 */
+#define RMP21 0x0020 /* RX Message Pending In Mailbox 21 */
+#define RMP22 0x0040 /* RX Message Pending In Mailbox 22 */
+#define RMP23 0x0080 /* RX Message Pending In Mailbox 23 */
+#define RMP24 0x0100 /* RX Message Pending In Mailbox 24 */
+#define RMP25 0x0200 /* RX Message Pending In Mailbox 25 */
+#define RMP26 0x0400 /* RX Message Pending In Mailbox 26 */
+#define RMP27 0x0800 /* RX Message Pending In Mailbox 27 */
+#define RMP28 0x1000 /* RX Message Pending In Mailbox 28 */
+#define RMP29 0x2000 /* RX Message Pending In Mailbox 29 */
+#define RMP30 0x4000 /* RX Message Pending In Mailbox 30 */
+#define RMP31 0x8000 /* RX Message Pending In Mailbox 31 */
+
+/* CAN_RML1 Masks */
+#define RML0 0x0001 /* RX Message Lost In Mailbox 0 */
+#define RML1 0x0002 /* RX Message Lost In Mailbox 1 */
+#define RML2 0x0004 /* RX Message Lost In Mailbox 2 */
+#define RML3 0x0008 /* RX Message Lost In Mailbox 3 */
+#define RML4 0x0010 /* RX Message Lost In Mailbox 4 */
+#define RML5 0x0020 /* RX Message Lost In Mailbox 5 */
+#define RML6 0x0040 /* RX Message Lost In Mailbox 6 */
+#define RML7 0x0080 /* RX Message Lost In Mailbox 7 */
+#define RML8 0x0100 /* RX Message Lost In Mailbox 8 */
+#define RML9 0x0200 /* RX Message Lost In Mailbox 9 */
+#define RML10 0x0400 /* RX Message Lost In Mailbox 10 */
+#define RML11 0x0800 /* RX Message Lost In Mailbox 11 */
+#define RML12 0x1000 /* RX Message Lost In Mailbox 12 */
+#define RML13 0x2000 /* RX Message Lost In Mailbox 13 */
+#define RML14 0x4000 /* RX Message Lost In Mailbox 14 */
+#define RML15 0x8000 /* RX Message Lost In Mailbox 15 */
+
+/* CAN_RML2 Masks */
+#define RML16 0x0001 /* RX Message Lost In Mailbox 16 */
+#define RML17 0x0002 /* RX Message Lost In Mailbox 17 */
+#define RML18 0x0004 /* RX Message Lost In Mailbox 18 */
+#define RML19 0x0008 /* RX Message Lost In Mailbox 19 */
+#define RML20 0x0010 /* RX Message Lost In Mailbox 20 */
+#define RML21 0x0020 /* RX Message Lost In Mailbox 21 */
+#define RML22 0x0040 /* RX Message Lost In Mailbox 22 */
+#define RML23 0x0080 /* RX Message Lost In Mailbox 23 */
+#define RML24 0x0100 /* RX Message Lost In Mailbox 24 */
+#define RML25 0x0200 /* RX Message Lost In Mailbox 25 */
+#define RML26 0x0400 /* RX Message Lost In Mailbox 26 */
+#define RML27 0x0800 /* RX Message Lost In Mailbox 27 */
+#define RML28 0x1000 /* RX Message Lost In Mailbox 28 */
+#define RML29 0x2000 /* RX Message Lost In Mailbox 29 */
+#define RML30 0x4000 /* RX Message Lost In Mailbox 30 */
+#define RML31 0x8000 /* RX Message Lost In Mailbox 31 */
+
+/* CAN_OPSS1 Masks */
+#define OPSS0 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0 */
+#define OPSS1 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1 */
+#define OPSS2 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2 */
+#define OPSS3 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3 */
+#define OPSS4 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4 */
+#define OPSS5 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5 */
+#define OPSS6 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6 */
+#define OPSS7 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7 */
+#define OPSS8 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8 */
+#define OPSS9 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9 */
+#define OPSS10 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10 */
+#define OPSS11 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11 */
+#define OPSS12 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12 */
+#define OPSS13 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13 */
+#define OPSS14 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14 */
+#define OPSS15 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15 */
+
+/* CAN_OPSS2 Masks */
+#define OPSS16 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16 */
+#define OPSS17 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17 */
+#define OPSS18 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18 */
+#define OPSS19 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19 */
+#define OPSS20 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20 */
+#define OPSS21 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21 */
+#define OPSS22 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22 */
+#define OPSS23 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23 */
+#define OPSS24 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24 */
+#define OPSS25 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25 */
+#define OPSS26 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26 */
+#define OPSS27 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27 */
+#define OPSS28 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28 */
+#define OPSS29 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29 */
+#define OPSS30 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30 */
+#define OPSS31 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31 */
+
+/* CAN_TRR1 Masks */
+#define TRR0 0x0001 /* Deny But Don't Lock Access To Mailbox 0 */
+#define TRR1 0x0002 /* Deny But Don't Lock Access To Mailbox 1 */
+#define TRR2 0x0004 /* Deny But Don't Lock Access To Mailbox 2 */
+#define TRR3 0x0008 /* Deny But Don't Lock Access To Mailbox 3 */
+#define TRR4 0x0010 /* Deny But Don't Lock Access To Mailbox 4 */
+#define TRR5 0x0020 /* Deny But Don't Lock Access To Mailbox 5 */
+#define TRR6 0x0040 /* Deny But Don't Lock Access To Mailbox 6 */
+#define TRR7 0x0080 /* Deny But Don't Lock Access To Mailbox 7 */
+#define TRR8 0x0100 /* Deny But Don't Lock Access To Mailbox 8 */
+#define TRR9 0x0200 /* Deny But Don't Lock Access To Mailbox 9 */
+#define TRR10 0x0400 /* Deny But Don't Lock Access To Mailbox 10 */
+#define TRR11 0x0800 /* Deny But Don't Lock Access To Mailbox 11 */
+#define TRR12 0x1000 /* Deny But Don't Lock Access To Mailbox 12 */
+#define TRR13 0x2000 /* Deny But Don't Lock Access To Mailbox 13 */
+#define TRR14 0x4000 /* Deny But Don't Lock Access To Mailbox 14 */
+#define TRR15 0x8000 /* Deny But Don't Lock Access To Mailbox 15 */
+
+/* CAN_TRR2 Masks */
+#define TRR16 0x0001 /* Deny But Don't Lock Access To Mailbox 16 */
+#define TRR17 0x0002 /* Deny But Don't Lock Access To Mailbox 17 */
+#define TRR18 0x0004 /* Deny But Don't Lock Access To Mailbox 18 */
+#define TRR19 0x0008 /* Deny But Don't Lock Access To Mailbox 19 */
+#define TRR20 0x0010 /* Deny But Don't Lock Access To Mailbox 20 */
+#define TRR21 0x0020 /* Deny But Don't Lock Access To Mailbox 21 */
+#define TRR22 0x0040 /* Deny But Don't Lock Access To Mailbox 22 */
+#define TRR23 0x0080 /* Deny But Don't Lock Access To Mailbox 23 */
+#define TRR24 0x0100 /* Deny But Don't Lock Access To Mailbox 24 */
+#define TRR25 0x0200 /* Deny But Don't Lock Access To Mailbox 25 */
+#define TRR26 0x0400 /* Deny But Don't Lock Access To Mailbox 26 */
+#define TRR27 0x0800 /* Deny But Don't Lock Access To Mailbox 27 */
+#define TRR28 0x1000 /* Deny But Don't Lock Access To Mailbox 28 */
+#define TRR29 0x2000 /* Deny But Don't Lock Access To Mailbox 29 */
+#define TRR30 0x4000 /* Deny But Don't Lock Access To Mailbox 30 */
+#define TRR31 0x8000 /* Deny But Don't Lock Access To Mailbox 31 */
+
+/* CAN_TRS1 Masks */
+#define TRS0 0x0001 /* Remote Frame Request For Mailbox 0 */
+#define TRS1 0x0002 /* Remote Frame Request For Mailbox 1 */
+#define TRS2 0x0004 /* Remote Frame Request For Mailbox 2 */
+#define TRS3 0x0008 /* Remote Frame Request For Mailbox 3 */
+#define TRS4 0x0010 /* Remote Frame Request For Mailbox 4 */
+#define TRS5 0x0020 /* Remote Frame Request For Mailbox 5 */
+#define TRS6 0x0040 /* Remote Frame Request For Mailbox 6 */
+#define TRS7 0x0080 /* Remote Frame Request For Mailbox 7 */
+#define TRS8 0x0100 /* Remote Frame Request For Mailbox 8 */
+#define TRS9 0x0200 /* Remote Frame Request For Mailbox 9 */
+#define TRS10 0x0400 /* Remote Frame Request For Mailbox 10 */
+#define TRS11 0x0800 /* Remote Frame Request For Mailbox 11 */
+#define TRS12 0x1000 /* Remote Frame Request For Mailbox 12 */
+#define TRS13 0x2000 /* Remote Frame Request For Mailbox 13 */
+#define TRS14 0x4000 /* Remote Frame Request For Mailbox 14 */
+#define TRS15 0x8000 /* Remote Frame Request For Mailbox 15 */
+
+/* CAN_TRS2 Masks */
+#define TRS16 0x0001 /* Remote Frame Request For Mailbox 16 */
+#define TRS17 0x0002 /* Remote Frame Request For Mailbox 17 */
+#define TRS18 0x0004 /* Remote Frame Request For Mailbox 18 */
+#define TRS19 0x0008 /* Remote Frame Request For Mailbox 19 */
+#define TRS20 0x0010 /* Remote Frame Request For Mailbox 20 */
+#define TRS21 0x0020 /* Remote Frame Request For Mailbox 21 */
+#define TRS22 0x0040 /* Remote Frame Request For Mailbox 22 */
+#define TRS23 0x0080 /* Remote Frame Request For Mailbox 23 */
+#define TRS24 0x0100 /* Remote Frame Request For Mailbox 24 */
+#define TRS25 0x0200 /* Remote Frame Request For Mailbox 25 */
+#define TRS26 0x0400 /* Remote Frame Request For Mailbox 26 */
+#define TRS27 0x0800 /* Remote Frame Request For Mailbox 27 */
+#define TRS28 0x1000 /* Remote Frame Request For Mailbox 28 */
+#define TRS29 0x2000 /* Remote Frame Request For Mailbox 29 */
+#define TRS30 0x4000 /* Remote Frame Request For Mailbox 30 */
+#define TRS31 0x8000 /* Remote Frame Request For Mailbox 31 */
+
+/* CAN_AA1 Masks */
+#define AA0 0x0001 /* Aborted Message In Mailbox 0 */
+#define AA1 0x0002 /* Aborted Message In Mailbox 1 */
+#define AA2 0x0004 /* Aborted Message In Mailbox 2 */
+#define AA3 0x0008 /* Aborted Message In Mailbox 3 */
+#define AA4 0x0010 /* Aborted Message In Mailbox 4 */
+#define AA5 0x0020 /* Aborted Message In Mailbox 5 */
+#define AA6 0x0040 /* Aborted Message In Mailbox 6 */
+#define AA7 0x0080 /* Aborted Message In Mailbox 7 */
+#define AA8 0x0100 /* Aborted Message In Mailbox 8 */
+#define AA9 0x0200 /* Aborted Message In Mailbox 9 */
+#define AA10 0x0400 /* Aborted Message In Mailbox 10 */
+#define AA11 0x0800 /* Aborted Message In Mailbox 11 */
+#define AA12 0x1000 /* Aborted Message In Mailbox 12 */
+#define AA13 0x2000 /* Aborted Message In Mailbox 13 */
+#define AA14 0x4000 /* Aborted Message In Mailbox 14 */
+#define AA15 0x8000 /* Aborted Message In Mailbox 15 */
+
+/* CAN_AA2 Masks */
+#define AA16 0x0001 /* Aborted Message In Mailbox 16 */
+#define AA17 0x0002 /* Aborted Message In Mailbox 17 */
+#define AA18 0x0004 /* Aborted Message In Mailbox 18 */
+#define AA19 0x0008 /* Aborted Message In Mailbox 19 */
+#define AA20 0x0010 /* Aborted Message In Mailbox 20 */
+#define AA21 0x0020 /* Aborted Message In Mailbox 21 */
+#define AA22 0x0040 /* Aborted Message In Mailbox 22 */
+#define AA23 0x0080 /* Aborted Message In Mailbox 23 */
+#define AA24 0x0100 /* Aborted Message In Mailbox 24 */
+#define AA25 0x0200 /* Aborted Message In Mailbox 25 */
+#define AA26 0x0400 /* Aborted Message In Mailbox 26 */
+#define AA27 0x0800 /* Aborted Message In Mailbox 27 */
+#define AA28 0x1000 /* Aborted Message In Mailbox 28 */
+#define AA29 0x2000 /* Aborted Message In Mailbox 29 */
+#define AA30 0x4000 /* Aborted Message In Mailbox 30 */
+#define AA31 0x8000 /* Aborted Message In Mailbox 31 */
+
+/* CAN_TA1 Masks */
+#define TA0 0x0001 /* Transmit Successful From Mailbox 0 */
+#define TA1 0x0002 /* Transmit Successful From Mailbox 1 */
+#define TA2 0x0004 /* Transmit Successful From Mailbox 2 */
+#define TA3 0x0008 /* Transmit Successful From Mailbox 3 */
+#define TA4 0x0010 /* Transmit Successful From Mailbox 4 */
+#define TA5 0x0020 /* Transmit Successful From Mailbox 5 */
+#define TA6 0x0040 /* Transmit Successful From Mailbox 6 */
+#define TA7 0x0080 /* Transmit Successful From Mailbox 7 */
+#define TA8 0x0100 /* Transmit Successful From Mailbox 8 */
+#define TA9 0x0200 /* Transmit Successful From Mailbox 9 */
+#define TA10 0x0400 /* Transmit Successful From Mailbox 10 */
+#define TA11 0x0800 /* Transmit Successful From Mailbox 11 */
+#define TA12 0x1000 /* Transmit Successful From Mailbox 12 */
+#define TA13 0x2000 /* Transmit Successful From Mailbox 13 */
+#define TA14 0x4000 /* Transmit Successful From Mailbox 14 */
+#define TA15 0x8000 /* Transmit Successful From Mailbox 15 */
+
+/* CAN_TA2 Masks */
+#define TA16 0x0001 /* Transmit Successful From Mailbox 16 */
+#define TA17 0x0002 /* Transmit Successful From Mailbox 17 */
+#define TA18 0x0004 /* Transmit Successful From Mailbox 18 */
+#define TA19 0x0008 /* Transmit Successful From Mailbox 19 */
+#define TA20 0x0010 /* Transmit Successful From Mailbox 20 */
+#define TA21 0x0020 /* Transmit Successful From Mailbox 21 */
+#define TA22 0x0040 /* Transmit Successful From Mailbox 22 */
+#define TA23 0x0080 /* Transmit Successful From Mailbox 23 */
+#define TA24 0x0100 /* Transmit Successful From Mailbox 24 */
+#define TA25 0x0200 /* Transmit Successful From Mailbox 25 */
+#define TA26 0x0400 /* Transmit Successful From Mailbox 26 */
+#define TA27 0x0800 /* Transmit Successful From Mailbox 27 */
+#define TA28 0x1000 /* Transmit Successful From Mailbox 28 */
+#define TA29 0x2000 /* Transmit Successful From Mailbox 29 */
+#define TA30 0x4000 /* Transmit Successful From Mailbox 30 */
+#define TA31 0x8000 /* Transmit Successful From Mailbox 31 */
+
+/* CAN_MBTD Masks */
+#define TDPTR 0x001F /* Mailbox To Temporarily Disable */
+#define TDA 0x0040 /* Temporary Disable Acknowledge */
+#define TDR 0x0080 /* Temporary Disable Request */
+
+/* CAN_RFH1 Masks */
+#define RFH0 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 0 */
+#define RFH1 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 1 */
+#define RFH2 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 2 */
+#define RFH3 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 3 */
+#define RFH4 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 4 */
+#define RFH5 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 5 */
+#define RFH6 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 6 */
+#define RFH7 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 7 */
+#define RFH8 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 8 */
+#define RFH9 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 9 */
+#define RFH10 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 10 */
+#define RFH11 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 11 */
+#define RFH12 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 12 */
+#define RFH13 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 13 */
+#define RFH14 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 14 */
+#define RFH15 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 15 */
+
+/* CAN_RFH2 Masks */
+#define RFH16 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 16 */
+#define RFH17 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 17 */
+#define RFH18 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 18 */
+#define RFH19 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 19 */
+#define RFH20 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 20 */
+#define RFH21 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 21 */
+#define RFH22 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 22 */
+#define RFH23 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 23 */
+#define RFH24 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 24 */
+#define RFH25 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 25 */
+#define RFH26 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 26 */
+#define RFH27 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 27 */
+#define RFH28 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 28 */
+#define RFH29 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 29 */
+#define RFH30 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 30 */
+#define RFH31 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 31 */
+
+/* CAN_MBTIF1 Masks */
+#define MBTIF0 0x0001 /* TX Interrupt Active In Mailbox 0 */
+#define MBTIF1 0x0002 /* TX Interrupt Active In Mailbox 1 */
+#define MBTIF2 0x0004 /* TX Interrupt Active In Mailbox 2 */
+#define MBTIF3 0x0008 /* TX Interrupt Active In Mailbox 3 */
+#define MBTIF4 0x0010 /* TX Interrupt Active In Mailbox 4 */
+#define MBTIF5 0x0020 /* TX Interrupt Active In Mailbox 5 */
+#define MBTIF6 0x0040 /* TX Interrupt Active In Mailbox 6 */
+#define MBTIF7 0x0080 /* TX Interrupt Active In Mailbox 7 */
+#define MBTIF8 0x0100 /* TX Interrupt Active In Mailbox 8 */
+#define MBTIF9 0x0200 /* TX Interrupt Active In Mailbox 9 */
+#define MBTIF10 0x0400 /* TX Interrupt Active In Mailbox 10 */
+#define MBTIF11 0x0800 /* TX Interrupt Active In Mailbox 11 */
+#define MBTIF12 0x1000 /* TX Interrupt Active In Mailbox 12 */
+#define MBTIF13 0x2000 /* TX Interrupt Active In Mailbox 13 */
+#define MBTIF14 0x4000 /* TX Interrupt Active In Mailbox 14 */
+#define MBTIF15 0x8000 /* TX Interrupt Active In Mailbox 15 */
+
+/* CAN_MBTIF2 Masks */
+#define MBTIF16 0x0001 /* TX Interrupt Active In Mailbox 16 */
+#define MBTIF17 0x0002 /* TX Interrupt Active In Mailbox 17 */
+#define MBTIF18 0x0004 /* TX Interrupt Active In Mailbox 18 */
+#define MBTIF19 0x0008 /* TX Interrupt Active In Mailbox 19 */
+#define MBTIF20 0x0010 /* TX Interrupt Active In Mailbox 20 */
+#define MBTIF21 0x0020 /* TX Interrupt Active In Mailbox 21 */
+#define MBTIF22 0x0040 /* TX Interrupt Active In Mailbox 22 */
+#define MBTIF23 0x0080 /* TX Interrupt Active In Mailbox 23 */
+#define MBTIF24 0x0100 /* TX Interrupt Active In Mailbox 24 */
+#define MBTIF25 0x0200 /* TX Interrupt Active In Mailbox 25 */
+#define MBTIF26 0x0400 /* TX Interrupt Active In Mailbox 26 */
+#define MBTIF27 0x0800 /* TX Interrupt Active In Mailbox 27 */
+#define MBTIF28 0x1000 /* TX Interrupt Active In Mailbox 28 */
+#define MBTIF29 0x2000 /* TX Interrupt Active In Mailbox 29 */
+#define MBTIF30 0x4000 /* TX Interrupt Active In Mailbox 30 */
+#define MBTIF31 0x8000 /* TX Interrupt Active In Mailbox 31 */
+
+/* CAN_MBRIF1 Masks */
+#define MBRIF0 0x0001 /* RX Interrupt Active In Mailbox 0 */
+#define MBRIF1 0x0002 /* RX Interrupt Active In Mailbox 1 */
+#define MBRIF2 0x0004 /* RX Interrupt Active In Mailbox 2 */
+#define MBRIF3 0x0008 /* RX Interrupt Active In Mailbox 3 */
+#define MBRIF4 0x0010 /* RX Interrupt Active In Mailbox 4 */
+#define MBRIF5 0x0020 /* RX Interrupt Active In Mailbox 5 */
+#define MBRIF6 0x0040 /* RX Interrupt Active In Mailbox 6 */
+#define MBRIF7 0x0080 /* RX Interrupt Active In Mailbox 7 */
+#define MBRIF8 0x0100 /* RX Interrupt Active In Mailbox 8 */
+#define MBRIF9 0x0200 /* RX Interrupt Active In Mailbox 9 */
+#define MBRIF10 0x0400 /* RX Interrupt Active In Mailbox 10 */
+#define MBRIF11 0x0800 /* RX Interrupt Active In Mailbox 11 */
+#define MBRIF12 0x1000 /* RX Interrupt Active In Mailbox 12 */
+#define MBRIF13 0x2000 /* RX Interrupt Active In Mailbox 13 */
+#define MBRIF14 0x4000 /* RX Interrupt Active In Mailbox 14 */
+#define MBRIF15 0x8000 /* RX Interrupt Active In Mailbox 15 */
+
+/* CAN_MBRIF2 Masks */
+#define MBRIF16 0x0001 /* RX Interrupt Active In Mailbox 16 */
+#define MBRIF17 0x0002 /* RX Interrupt Active In Mailbox 17 */
+#define MBRIF18 0x0004 /* RX Interrupt Active In Mailbox 18 */
+#define MBRIF19 0x0008 /* RX Interrupt Active In Mailbox 19 */
+#define MBRIF20 0x0010 /* RX Interrupt Active In Mailbox 20 */
+#define MBRIF21 0x0020 /* RX Interrupt Active In Mailbox 21 */
+#define MBRIF22 0x0040 /* RX Interrupt Active In Mailbox 22 */
+#define MBRIF23 0x0080 /* RX Interrupt Active In Mailbox 23 */
+#define MBRIF24 0x0100 /* RX Interrupt Active In Mailbox 24 */
+#define MBRIF25 0x0200 /* RX Interrupt Active In Mailbox 25 */
+#define MBRIF26 0x0400 /* RX Interrupt Active In Mailbox 26 */
+#define MBRIF27 0x0800 /* RX Interrupt Active In Mailbox 27 */
+#define MBRIF28 0x1000 /* RX Interrupt Active In Mailbox 28 */
+#define MBRIF29 0x2000 /* RX Interrupt Active In Mailbox 29 */
+#define MBRIF30 0x4000 /* RX Interrupt Active In Mailbox 30 */
+#define MBRIF31 0x8000 /* RX Interrupt Active In Mailbox 31 */
+
+/* CAN_MBIM1 Masks */
+#define MBIM0 0x0001 /* Enable Interrupt For Mailbox 0 */
+#define MBIM1 0x0002 /* Enable Interrupt For Mailbox 1 */
+#define MBIM2 0x0004 /* Enable Interrupt For Mailbox 2 */
+#define MBIM3 0x0008 /* Enable Interrupt For Mailbox 3 */
+#define MBIM4 0x0010 /* Enable Interrupt For Mailbox 4 */
+#define MBIM5 0x0020 /* Enable Interrupt For Mailbox 5 */
+#define MBIM6 0x0040 /* Enable Interrupt For Mailbox 6 */
+#define MBIM7 0x0080 /* Enable Interrupt For Mailbox 7 */
+#define MBIM8 0x0100 /* Enable Interrupt For Mailbox 8 */
+#define MBIM9 0x0200 /* Enable Interrupt For Mailbox 9 */
+#define MBIM10 0x0400 /* Enable Interrupt For Mailbox 10 */
+#define MBIM11 0x0800 /* Enable Interrupt For Mailbox 11 */
+#define MBIM12 0x1000 /* Enable Interrupt For Mailbox 12 */
+#define MBIM13 0x2000 /* Enable Interrupt For Mailbox 13 */
+#define MBIM14 0x4000 /* Enable Interrupt For Mailbox 14 */
+#define MBIM15 0x8000 /* Enable Interrupt For Mailbox 15 */
+
+/* CAN_MBIM2 Masks */
+#define MBIM16 0x0001 /* Enable Interrupt For Mailbox 16 */
+#define MBIM17 0x0002 /* Enable Interrupt For Mailbox 17 */
+#define MBIM18 0x0004 /* Enable Interrupt For Mailbox 18 */
+#define MBIM19 0x0008 /* Enable Interrupt For Mailbox 19 */
+#define MBIM20 0x0010 /* Enable Interrupt For Mailbox 20 */
+#define MBIM21 0x0020 /* Enable Interrupt For Mailbox 21 */
+#define MBIM22 0x0040 /* Enable Interrupt For Mailbox 22 */
+#define MBIM23 0x0080 /* Enable Interrupt For Mailbox 23 */
+#define MBIM24 0x0100 /* Enable Interrupt For Mailbox 24 */
+#define MBIM25 0x0200 /* Enable Interrupt For Mailbox 25 */
+#define MBIM26 0x0400 /* Enable Interrupt For Mailbox 26 */
+#define MBIM27 0x0800 /* Enable Interrupt For Mailbox 27 */
+#define MBIM28 0x1000 /* Enable Interrupt For Mailbox 28 */
+#define MBIM29 0x2000 /* Enable Interrupt For Mailbox 29 */
+#define MBIM30 0x4000 /* Enable Interrupt For Mailbox 30 */
+#define MBIM31 0x8000 /* Enable Interrupt For Mailbox 31 */
+
+/* CAN_GIM Masks */
+#define EWTIM 0x0001 /* Enable TX Error Count Interrupt */
+#define EWRIM 0x0002 /* Enable RX Error Count Interrupt */
+#define EPIM 0x0004 /* Enable Error-Passive Mode Interrupt */
+#define BOIM 0x0008 /* Enable Bus Off Interrupt */
+#define WUIM 0x0010 /* Enable Wake-Up Interrupt */
+#define UIAIM 0x0020 /* Enable Access To Unimplemented Address Interrupt */
+#define AAIM 0x0040 /* Enable Abort Acknowledge Interrupt */
+#define RMLIM 0x0080 /* Enable RX Message Lost Interrupt */
+#define UCEIM 0x0100 /* Enable Universal Counter Overflow Interrupt */
+#define EXTIM 0x0200 /* Enable External Trigger Output Interrupt */
+#define ADIM 0x0400 /* Enable Access Denied Interrupt */
+
+/* CAN_GIS Masks */
+#define EWTIS 0x0001 /* TX Error Count IRQ Status */
+#define EWRIS 0x0002 /* RX Error Count IRQ Status */
+#define EPIS 0x0004 /* Error-Passive Mode IRQ Status */
+#define BOIS 0x0008 /* Bus Off IRQ Status */
+#define WUIS 0x0010 /* Wake-Up IRQ Status */
+#define UIAIS 0x0020 /* Access To Unimplemented Address IRQ Status */
+#define AAIS 0x0040 /* Abort Acknowledge IRQ Status */
+#define RMLIS 0x0080 /* RX Message Lost IRQ Status */
+#define UCEIS 0x0100 /* Universal Counter Overflow IRQ Status */
+#define EXTIS 0x0200 /* External Trigger Output IRQ Status */
+#define ADIS 0x0400 /* Access Denied IRQ Status */
+
+/* CAN_GIF Masks */
+#define EWTIF 0x0001 /* TX Error Count IRQ Flag */
+#define EWRIF 0x0002 /* RX Error Count IRQ Flag */
+#define EPIF 0x0004 /* Error-Passive Mode IRQ Flag */
+#define BOIF 0x0008 /* Bus Off IRQ Flag */
+#define WUIF 0x0010 /* Wake-Up IRQ Flag */
+#define UIAIF 0x0020 /* Access To Unimplemented Address IRQ Flag */
+#define AAIF 0x0040 /* Abort Acknowledge IRQ Flag */
+#define RMLIF 0x0080 /* RX Message Lost IRQ Flag */
+#define UCEIF 0x0100 /* Universal Counter Overflow IRQ Flag */
+#define EXTIF 0x0200 /* External Trigger Output IRQ Flag */
+#define ADIF 0x0400 /* Access Denied IRQ Flag */
+
+/* CAN_UCCNF Masks */
+#define UCCNF 0x000F /* Universal Counter Mode */
+#define UC_STAMP 0x0001 /* Timestamp Mode */
+#define UC_WDOG 0x0002 /* Watchdog Mode */
+#define UC_AUTOTX 0x0003 /* Auto-Transmit Mode */
+#define UC_ERROR 0x0006 /* CAN Error Frame Count */
+#define UC_OVER 0x0007 /* CAN Overload Frame Count */
+#define UC_LOST 0x0008 /* Arbitration Lost During TX Count */
+#define UC_AA 0x0009 /* TX Abort Count */
+#define UC_TA 0x000A /* TX Successful Count */
+#define UC_REJECT 0x000B /* RX Message Rejected Count */
+#define UC_RML 0x000C /* RX Message Lost Count */
+#define UC_RX 0x000D /* Total Successful RX Messages Count */
+#define UC_RMP 0x000E /* Successful RX W/Matching ID Count */
+#define UC_ALL 0x000F /* Correct Message On CAN Bus Line Count */
+#define UCRC 0x0020 /* Universal Counter Reload/Clear */
+#define UCCT 0x0040 /* Universal Counter CAN Trigger */
+#define UCE 0x0080 /* Universal Counter Enable */
+
+/* CAN_ESR Masks */
+#define ACKE 0x0004 /* Acknowledge Error */
+#define SER 0x0008 /* Stuff Error */
+#define CRCE 0x0010 /* CRC Error */
+#define SA0 0x0020 /* Stuck At Dominant Error */
+#define BEF 0x0040 /* Bit Error Flag */
+#define FER 0x0080 /* Form Error Flag */
+
+/* CAN_EWR Masks */
+#define EWLREC 0x00FF /* RX Error Count Limit (For EWRIS) */
+#define EWLTEC 0xFF00 /* TX Error Count Limit (For EWTIS) */
+
+/*
+ * PIN CONTROL REGISTER MASKS
+ */
+/* PORT_MUX Masks */
+#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
+#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */
+#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */
+
+#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
+#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */
+#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
+#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
+
+#define PFDE 0x0008 /* Port F DMA Request Enable */
+#define PGDE_UART 0x0000 /* Enable UART0 RX/TX */
+#define PGDE_DMA 0x0008 /* Enable DMAR1:0 */
+
+#define PFTE 0x0010 /* Port F Timer Enable */
+#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
+#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */
+
+#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
+#define PFS6E_TIMER 0x0000 /* Enable TMR5 */
+#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */
+
+#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
+#define PFS5E_TIMER 0x0000 /* Enable TMR4 */
+#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */
+
+#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
+#define PFS4E_TIMER 0x0000 /* Enable TMR3 */
+#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */
+
+#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */
+#define PFFE_TIMER 0x0000 /* Enable TMR2 */
+#define PFFE_PPI 0x0100 /* Enable PPI FS3 */
+
+#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */
+#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */
+#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */
+
+#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */
+#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */
+#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */
+
+#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */
+#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
+#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
+
+/*
+ * HANDSHAKE DMA (HDMA) MASKS
+ */
+/* HDMAx_CTL Masks */
+#define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */
+#define REP 0x0002 /* HDMA Request Polarity */
+#define UTE 0x0004 /* Urgency Threshold Enable */
+#define OIE 0x0010 /* Overflow Interrupt Enable */
+#define BDIE 0x0020 /* Block Done Interrupt Enable */
+#define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */
+#define DRQ 0x0300 /* HDMA Request Type */
+#define DRQ_NONE 0x0000 /* No Request */
+#define DRQ_SINGLE 0x0100 /* Channels Request Single */
+#define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */
+#define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */
+#define RBC 0x1000 /* Reload BCNT With IBCNT */
+#define PS 0x2000 /* HDMA Pin Status */
+#define OI 0x4000 /* Overflow Interrupt Generated */
+#define BDI 0x8000 /* Block Done Interrupt Generated */
+
+/* entry addresses of the user-callable Boot ROM functions */
+
+#define _BOOTROM_RESET 0xEF000000
+#define _BOOTROM_FINAL_INIT 0xEF000002
+#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
+#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
+#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
+#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
+#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
+#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
+#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
+
+#endif /* _DEF_BF534_H */
--- /dev/null
+/*
+ * Copyright (C) 2004-2005 Analog Devices Inc., All Rights Reserved.
+ *
+ ***********************************************************************************
+ *
+ * This include file contains a list of macro "defines" to enable the programmer
+ * to use symbolic names for register-access and bit-manipulation.
+ *
+ * ----------------------------
+ * revision 0.1
+ * date: 2004/03/01 21:23:01; author: joeb
+ * Initial revision
+ *
+ * ----------------------------
+ * revision 0.2
+ * date: 2004/05/15 16:30:00; author: joeb
+ * comments: removed I2C/IIC references, changed GPIO sections
+ *
+ * ----------------------------
+ * revision 0.3
+ * date: 2004/06/08 12:25:00; author: joeb
+ * comments: fixed mis-mapped TIMER registers, changed TWI register names, fixed
+ * FLAG references in GPIO register names
+ *
+ * ----------------------------
+ * revision 0.4
+ * date: 2004/06/09 2:25:00; author: joeb
+ * comments: fixed bit-defines for EMAC section, renamed EMAC count registers,
+ * combined 2 Timer status registers into one
+ *
+ * ----------------------------
+ * revision 0.5
+ * date: 2004/08/10 10:25:00; author: joeb
+ * comments: Renamed EMAC wake-up registers, changed bit-names in EMAC registers
+ *
+ * ----------------------------
+ * revision 0.6
+ * date: 2004/08/17 16:25:00; author: joeb
+ * comments: Renamed TWI_INT_ENABLE to TWI_INT_MASK
+ *
+ * ----------------------------
+ * revision 0.7
+ * date: 2004/08/18 13:21:00; author: joeb
+ * comments: Renamed GPIO registers to remove _D, _S, _C, _T suffixes
+ *
+ * ----------------------------
+ * revision 0.8
+ * date: 2004/08/20 10:24:00; author: joeb
+ * comments: Renamed External DMA to Handshake MDMA
+ *
+ * ----------------------------
+ * revision 0.9
+ * date: 2004/08/23 13:42:00; author: joeb
+ * comments: Renamed Handshake DMA Register Set
+ *
+ * ----------------------------
+ * revision 0.10
+ * date: 2004/09/07 11:21:00; author: joeb
+ * comments: Fixed EMAC TX/RX DMA Priority (DMA and SIC Bit Names)
+ *
+ * ----------------------------
+ * revision 0.11
+ * date: 2004/09/28 15:14:00; author: joeb
+ * comments: Fixed CAN Mailbox Area
+ *
+ * ----------------------------
+ * revision 0.12
+ * date: 2004/10/27 13:18:00; author: joeb
+ * comments: Added IEEE EMAC Register Support
+ *
+ * ----------------------------
+ * revision 0.13
+ * date: 2004/10/28 15:40:00; author: joeb
+ * comments: Shortened EMAC Count Register Names
+ *
+ * ----------------------------
+ * revision 0.14
+ * date: 2004/11/09 10:45:00; author: joeb
+ * comments: Fixed WDSIZE macros
+ *
+ * ----------------------------
+ * revision 0.15
+ * date: 2004/11/18 07:45:00; author: joeb
+ * comments: Fixed TIMER_STATUS register, added EMAC macros
+ *
+ * ----------------------------
+ * revision 0.16
+ * date: 2004/12/13 11:05:00; author: joeb
+ * comments: Removed HI/LO macros (now Assembler mnemonics)
+ * Renamed enable bit for HMDMA from EN to HMDMAEN
+ *
+ * ----------------------------
+ * revision 0.17
+ * date: 2004/12/17 14:25:00; author: joeb
+ * comments: Replaced C++ Single-Line Comments w/C-standard Comments
+ * Changed EMAC EQ1024 TX/RX References to GE1024
+ *
+ * ----------------------------
+ * revision 0.18
+ * date: 2005/01/05 10:50:00; author: joeb
+ * comments: Added CAN Macros To Index Mailbox Area and Acceptance Masks
+ * Added mask values for field deposit protection
+ *
+ * ----------------------------
+ * revision 0.19
+ * date: 2005/01/10 10:30:00; author: joeb
+ * comments: Made all Macro argument syntax compliant to MISRA-C 2004 rule 19.10.
+ *
+ * ----------------------------
+ * revision 0.20
+ * date: 2005/01/27 14:25:15; author: joeb
+ * comments: Moved MMRs common to BF534 to BF534 header.
+ */
+#ifndef _DEF_BF537_H
+#define _DEF_BF537_H
+
+/* Include all Core registers and bit definitions */
+#include <asm/arch-common/def_LPBlackfin.h>
+
+/* Include all MMR and bit defines common to BF534 */
+#include <asm/arch-bf537/defBF534.h>
+
+/*
+ * Define EMAC Section Unique to BF536/BF537
+ */
+
+/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
+#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
+#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
+#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
+#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
+#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
+#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
+#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
+#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
+#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
+#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
+#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
+#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
+#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
+#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
+#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
+#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
+#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
+#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
+#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
+
+#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
+#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
+#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
+#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
+#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
+#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
+#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
+#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
+
+#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
+#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
+#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
+#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
+#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
+
+#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
+#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
+#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
+#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
+#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
+#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
+#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
+#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
+#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
+#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
+#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
+#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
+#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
+#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
+#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
+#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
+#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
+#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
+#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
+#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 <= x < 128 */
+#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
+#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
+#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
+#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
+
+#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
+#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
+#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
+#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
+#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
+#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
+#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
+#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
+#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
+#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
+#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
+#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
+#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
+#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
+#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
+#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
+#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
+#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 <= x < 128 */
+#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
+#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
+#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
+#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
+#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
+
+/* Listing for IEEE-Supported Count Registers */
+#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
+#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
+#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
+#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
+#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
+#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
+#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
+#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
+#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
+#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
+#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
+#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
+#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
+#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
+#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
+#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
+#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
+#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
+#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
+#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 <= x < 128 */
+#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
+#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
+#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
+#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
+
+#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
+#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
+#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
+#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
+#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
+#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
+#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
+#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
+#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
+#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
+#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
+#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
+#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
+#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
+#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
+#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
+#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
+#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 <= x < 128 */
+#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
+#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
+#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
+#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
+#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
+
+/*
+ * System MMR Register Bits And Macros
+ *
+ * Disclaimer: All macros are intended to make C and Assembly code more readable.
+ * Use these macros carefully, as any that do left shifts for field
+ * depositing will result in the lower order bits being destroyed. Any
+ * macro that shifts left to properly position the bit-field should be
+ * used as part of an OR to initialize a register and NOT as a dynamic
+ * modifier UNLESS the lower order bits are saved and ORed back in when
+ * the macro is used.
+ */
+/*
+ * ETHERNET 10/100 CONTROLLER MASKS
+ */
+/* EMAC_OPMODE Masks */
+#define RE 0x00000001 /* Receiver Enable */
+#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
+#define HU 0x00000010 /* Hash Filter Unicast Address */
+#define HM 0x00000020 /* Hash Filter Multicast Address */
+#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
+#define PR 0x00000080 /* Promiscuous Mode Enable */
+#define IFE 0x00000100 /* Inverse Filtering Enable */
+#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
+#define PBF 0x00000400 /* Pass Bad Frames Enable */
+#define PSF 0x00000800 /* Pass Short Frames Enable */
+#define RAF 0x00001000 /* Receive-All Mode */
+#define TE 0x00010000 /* Transmitter Enable */
+#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
+#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
+#define DC 0x00080000 /* Deferral Check */
+#define BOLMT 0x00300000 /* Back-Off Limit */
+#define BOLMT_10 0x00000000 /* 10-bit range */
+#define BOLMT_8 0x00100000 /* 8-bit range */
+#define BOLMT_4 0x00200000 /* 4-bit range */
+#define BOLMT_1 0x00300000 /* 1-bit range */
+#define DRTY 0x00400000 /* Disable TX Retry On Collision */
+#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
+#define RMII 0x01000000 /* RMII/MII* Mode */
+#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
+#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
+#define LB 0x08000000 /* Internal Loopback Enable */
+#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
+
+/* EMAC_STAADD Masks */
+#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
+#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
+#define STADISPRE 0x00000004 /* Disable Preamble Generation */
+#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
+#define REGAD 0x000007C0 /* STA Register Address */
+#define PHYAD 0x0000F800 /* PHY Device Address */
+
+#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
+#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
+
+/* EMAC_STADAT Mask */
+#define STADATA 0x0000FFFF /* Station Management Data */
+
+/* EMAC_FLC Masks */
+#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
+#define FLCE 0x00000002 /* Flow Control Enable */
+#define PCF 0x00000004 /* Pass Control Frames */
+#define BKPRSEN 0x00000008 /* Enable Backpressure */
+#define FLCPAUSE 0xFFFF0000 /* Pause Time */
+
+#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
+
+/* EMAC_WKUP_CTL Masks */
+#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
+#define MPKE 0x00000002 /* Magic Packet Enable */
+#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
+#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
+#define MPKS 0x00000020 /* Magic Packet Received Status */
+#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
+
+/* EMAC_WKUP_FFCMD Masks */
+#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
+#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
+#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
+#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
+#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
+#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
+#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
+#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
+
+/* EMAC_WKUP_FFOFF Masks */
+#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
+#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
+#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
+#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
+
+#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
+#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
+#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
+#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
+/* Set ALL Offsets */
+#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
+
+/* EMAC_WKUP_FFCRC0 Masks */
+#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
+#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
+
+#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0) /* Set Wake-Up Filter 0 Target CRC */
+#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16) /* Set Wake-Up Filter 1 Target CRC */
+
+/* EMAC_WKUP_FFCRC1 Masks */
+#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
+#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
+
+#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0) /* Set Wake-Up Filter 2 Target CRC */
+#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16) /* Set Wake-Up Filter 3 Target CRC */
+
+/* EMAC_SYSCTL Masks */
+#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
+#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
+#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
+#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
+
+#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
+
+/* EMAC_SYSTAT Masks */
+#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
+#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
+#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
+#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
+#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
+#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
+#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
+#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
+
+/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
+#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
+#define RX_COMP 0x00001000 /* RX Frame Complete */
+#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
+#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
+#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
+#define RX_CRC 0x00010000 /* RX Frame CRC Error */
+#define RX_LEN 0x00020000 /* RX Frame Length Error */
+#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
+#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
+#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
+#define RX_PHY 0x00200000 /* RX Frame PHY Error */
+#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
+#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
+#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
+#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
+#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
+#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
+#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
+#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
+#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
+#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
+
+/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
+#define TX_COMP 0x00000001 /* TX Frame Complete */
+#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
+#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
+#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
+#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
+#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
+#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
+#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
+#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
+#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
+#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
+#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
+#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
+#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
+#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
+
+/* EMAC_MMC_CTL Masks */
+#define RSTC 0x00000001 /* Reset All Counters */
+#define CROLL 0x00000002 /* Counter Roll-Over Enable */
+#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
+#define MMCE 0x00000008 /* Enable MMC Counter Operation */
+
+/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
+#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
+#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
+#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
+#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
+#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
+#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
+#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
+#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
+#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
+#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
+#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
+#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
+#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
+#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
+#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
+#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
+#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
+#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
+#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
+#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
+#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
+#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
+#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
+#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
+
+/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
+#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
+#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
+#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
+#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
+#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
+#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
+#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
+#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
+#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
+#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
+#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
+#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
+#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
+#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
+#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
+#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
+#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
+#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
+#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
+#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
+#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
+#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
+#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
+
+#endif /* _DEF_BF537_H */
--- /dev/null
+/*
+ * defBF537_extn.h
+ *
+ * This file is subject to the terms and conditions of the GNU Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Non-GPL License also available as part of VisualDSP++
+ *
+ * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
+ *
+ * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
+ *
+ * This file under source code control, please send bugs or changes to:
+ * dsptools.support@analog.com
+ *
+ */
+
+#ifndef _DEF_BF537_EXTN_H
+#define _DEF_BF537_EXTN_H
+
+#define OFFSET_( x ) ((x) & 0x0000FFFF) /* define macro for offset */
+/* Delay inserted for PLL transition */
+#define PLL_DELAY 0x1000
+
+#define L1_ISRAM 0xFFA00000
+#define L1_ISRAM_END 0xFFA10000
+#define DATA_BANKA_SRAM 0xFF800000
+#define DATA_BANKA_SRAM_END 0xFF808000
+#define DATA_BANKB_SRAM 0xFF900000
+#define DATA_BANKB_SRAM_END 0xFF908000
+#define SYSMMR_BASE 0xFFC00000
+#define WDSIZE16 0x00000004
+
+/* Event Vector Table Address */
+#define EVT_EMULATION_ADDR 0xffe02000
+#define EVT_RESET_ADDR 0xffe02004
+#define EVT_NMI_ADDR 0xffe02008
+#define EVT_EXCEPTION_ADDR 0xffe0200c
+#define EVT_GLOBAL_INT_ENB_ADDR 0xffe02010
+#define EVT_HARDWARE_ERROR_ADDR 0xffe02014
+#define EVT_TIMER_ADDR 0xffe02018
+#define EVT_IVG7_ADDR 0xffe0201c
+#define EVT_IVG8_ADDR 0xffe02020
+#define EVT_IVG9_ADDR 0xffe02024
+#define EVT_IVG10_ADDR 0xffe02028
+#define EVT_IVG11_ADDR 0xffe0202c
+#define EVT_IVG12_ADDR 0xffe02030
+#define EVT_IVG13_ADDR 0xffe02034
+#define EVT_IVG14_ADDR 0xffe02038
+#define EVT_IVG15_ADDR 0xffe0203c
+#define EVT_OVERRIDE_ADDR 0xffe02100
+
+/* IMASK Bit values */
+#define IVG15_POS 0x00008000
+#define IVG14_POS 0x00004000
+#define IVG13_POS 0x00002000
+#define IVG12_POS 0x00001000
+#define IVG11_POS 0x00000800
+#define IVG10_POS 0x00000400
+#define IVG9_POS 0x00000200
+#define IVG8_POS 0x00000100
+#define IVG7_POS 0x00000080
+#define IVGTMR_POS 0x00000040
+#define IVGHW_POS 0x00000020
+
+#define WDOG_TMR_DISABLE (0xAD << 4)
+#define ICTL_RST 0x00000000
+#define ICTL_NMI 0x00000002
+#define ICTL_GP 0x00000004
+#define ICTL_DISABLE 0x00000003
+
+/* Watch Dog timer values setup */
+#define WATCHDOG_DISABLE WDOG_TMR_DISABLE | ICTL_DISABLE
+
+#endif /* _DEF_BF537_EXTN_H */
--- /dev/null
+/*
+ * U-boot bf537_irq.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on
+ * linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c
+ * Changed by HuTao Apr18, 2003
+ *
+ * Copyright was missing when I got the code so took from MIPS arch ...MaTed---
+ * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
+ * Copyright (C) 1995, 96, 97, 98, 99, 2000, 2001 by Ralf Baechle
+ *
+ * Adapted for BlackFin (ADI) by Ted Ma <mated@sympatico.ca>
+ * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com)
+ * Copyright (c) 2002 Lineo, Inc. <mattw@lineo.com>
+ *
+ * Adapted for BlackFin BF537 by Bas Vermeulen <bas@buyways.nl>
+ * Copyright (c) 2003 BuyWays B.V. (www.buyways.nl)
+
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BF537_IRQ_H_
+#define _BF537_IRQ_H_
+
+/*
+ * Interrupt source definitions
+ * Event Source Core Event Name Number
+ * EMU 0
+ * Reset RST 1
+ * NMI NMI 2
+ * Exception EVX 3
+ * Reserved -- 4
+ * Hardware Error IVHW 5
+ * Core Timer IVTMR 6
+ * PLL Wakeup Interrupt IVG7 7
+ * DMA Error (generic) IVG7 8
+ * PPI Error Interrupt IVG7 9
+ * SPORT0 Error Interrupt IVG7 10
+ * SPORT1 Error Interrupt IVG7 11
+ * SPI Error Interrupt IVG7 12
+ * UART Error Interrupt IVG7 13
+ * RTC Interrupt IVG8 14
+ * DMA0 Interrupt (PPI) IVG8 15
+ * DMA1 (SPORT0 RX) IVG9 16
+ * DMA2 (SPORT0 TX) IVG9 17
+ * DMA3 (SPORT1 RX) IVG9 18
+ * DMA4 (SPORT1 TX) IVG9 19
+ * DMA5 (PPI) IVG10 20
+ * DMA6 (UART RX) IVG10 21
+ * DMA7 (UART TX) IVG10 22
+ * Timer0 IVG11 23
+ * Timer1 IVG11 24
+ * Timer2 IVG11 25
+ * PF Interrupt A IVG12 26
+ * PF Interrupt B IVG12 27
+ * DMA8/9 Interrupt IVG13 28
+ * DMA10/11 Interrupt IVG13 29
+ * Watchdog Timer IVG13 30
+ * Software Interrupt 1 IVG14 31
+ * Software Interrupt 2 --
+ * (lowest priority) IVG15 32
+ */
+
+#define IRQ_EMU 0 /* Emulation */
+#define IRQ_RST 1 /* reset */
+#define IRQ_NMI 2 /* Non Maskable */
+#define IRQ_EVX 3 /* Exception */
+#define IRQ_UNUSED 4 /* - unused interrupt */
+#define IRQ_HWERR 5 /* Hardware Error */
+#define IRQ_CORETMR 6 /* Core timer */
+
+#define IRQ_UART_RX_BIT 0x0800
+#define IRQ_UART_TX_BIT 0x1000
+#define IRQ_UART_ERROR_BIT 0x40
+
+#endif
--- /dev/null
+/*
+ * U-boot - Configuration file for BF537 STAMP board
+ */
+
+#ifndef __CONFIG_BF537_H__
+#define __CONFIG_BF537_H__
+
+#define CFG_LONGHELP 1
+#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_BAUDRATE 57600
+/* Set default serial console for bf537 */
+#define CONFIG_UART_CONSOLE 0
+#define CONFIG_BF537 1
+#define CONFIG_BOOTDELAY 5
+/* define CONFIG_BF537_STAMP_LEDCMD to enable LED command*/
+/*#define CONFIG_BF537_STAMP_LEDCMD 1*/
+
+/*
+ * Boot Mode Set
+ * Blackfin can support several boot modes
+ */
+#define BF537_BYPASS_BOOT 0x0011 /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */
+#define BF537_PARA_BOOT 0x0012 /* Bootmode 1: Boot from 8-bit or 16-bit flash */
+#define BF537_SPI_MASTER_BOOT 0x0014 /* Bootmode 3: SPI master mode boot from SPI flash */
+#define BF537_SPI_SLAVE_BOOT 0x0015 /* Bootmode 4: SPI slave mode boot from SPI flash */
+#define BF537_TWI_MASTER_BOOT 0x0016 /* Bootmode 5: TWI master mode boot from EEPROM */
+#define BF537_TWI_SLAVE_BOOT 0x0017 /* Bootmode 6: TWI slave mode boot from EEPROM */
+#define BF537_UART_BOOT 0x0018 /* Bootmode 7: UART slave mdoe boot via UART host */
+/* Define the boot mode */
+#define BFIN_BOOT_MODE BF537_BYPASS_BOOT
+
+#define CONFIG_PANIC_HANG 1
+
+#define ADSP_BF534 0x34
+#define ADSP_BF536 0x36
+#define ADSP_BF537 0x37
+#define BFIN_CPU ADSP_BF537
+
+/* This sets the default state of the cache on U-Boot's boot */
+#define CONFIG_ICACHE_ON
+#define CONFIG_DCACHE_ON
+
+/* Define if want to do post memory test */
+#undef CONFIG_POST_TEST
+
+/* Define where the uboot will be loaded by on-chip boot rom */
+#define APP_ENTRY 0x00001000
+
+#define CONFIG_RTC_BFIN 1
+#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
+
+/* CONFIG_CLKIN_HZ is any value in Hz */
+#define CONFIG_CLKIN_HZ 25000000
+/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
+/* 1=CLKIN/2 */
+#define CONFIG_CLKIN_HALF 0
+/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
+/* 1=bypass PLL*/
+#define CONFIG_PLL_BYPASS 0
+/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
+/* Values can range from 1-64 */
+#define CONFIG_VCO_MULT 20
+/* CONFIG_CCLK_DIV controls what the core clock divider is */
+/* Values can be 1, 2, 4, or 8 ONLY */
+#define CONFIG_CCLK_DIV 1
+/* CONFIG_SCLK_DIV controls what the peripheral clock divider is*/
+/* Values can range from 1-15 */
+#define CONFIG_SCLK_DIV 5
+/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
+/* Values can range from 2-65535 */
+/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
+#define CONFIG_SPI_BAUD 2
+#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
+#define CONFIG_SPI_BAUD_INITBLOCK 4
+#endif
+
+#if ( CONFIG_CLKIN_HALF == 0 )
+#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
+#else
+#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
+#endif
+
+#if (CONFIG_PLL_BYPASS == 0)
+#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
+#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
+#else
+#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
+#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
+#endif
+
+#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
+#if (CONFIG_SCLK_HZ / (2*CONFIG_SPI_BAUD) > 20000000)
+#define CONFIG_SPI_FLASH_FAST_READ 1 /* Needed if SPI_CLK > 20 MHz */
+#else
+#undef CONFIG_SPI_FLASH_FAST_READ
+#endif
+#endif
+
+#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */
+#define CONFIG_MEM_ADD_WDTH 10 /* 8, 9, 10, 11 */
+#define CONFIG_MEM_MT48LC32M8A2_75 1
+
+#define CONFIG_LOADS_ECHO 1
+
+/*
+ * rarpb, bootp or dhcp commands will perform only a
+ * configuration lookup from the BOOTP/DHCP server
+ * but not try to load any image using TFTP
+ */
+#define CFG_AUTOLOAD "no"
+
+/*
+ * Network Settings
+ */
+/* network support */
+#if (BFIN_CPU != ADSP_BF534)
+#define CONFIG_IPADDR 192.168.0.15
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_GATEWAYIP 192.168.0.1
+#define CONFIG_SERVERIP 192.168.0.2
+#define CONFIG_HOSTNAME BF537
+#endif
+
+#define CONFIG_ROOTPATH /romfs
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
+/* This is the routine that copies the MAC in Flash to the 'ethaddr' setting */
+
+#define CFG_LONGHELP 1
+#define CONFIG_BOOTDELAY 5
+#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
+#define CONFIG_BOOTCOMMAND "run ramboot"
+
+#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) && defined(CONFIG_POST_TEST)
+/* POST support */
+#define CONFIG_POST ( CFG_POST_MEMORY | \
+ CFG_POST_UART | \
+ CFG_POST_FLASH | \
+ CFG_POST_ETHER | \
+ CFG_POST_LED | \
+ CFG_POST_BUTTON)
+#else
+#undef CONFIG_POST
+#endif
+
+#ifdef CONFIG_POST
+#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
+#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */
+#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
+#else
+#define CFG_CMD_POST_DIAG 0
+#endif
+
+/* CF-CARD IDE-HDD Support */
+
+/* #define CONFIG_BFIN_TRUE_IDE */ /* Add CF flash card support */
+/* #define CONFIG_BFIN_CF_IDE */ /* Add CF flash card support */
+/* #define CONFIG_BFIN_HDD_IDE */ /* Add IDE Disk Drive (HDD) support */
+
+#if defined(CONFIG_BFIN_CF_IDE) || defined(CONFIG_BFIN_HDD_IDE) || defined(CONFIG_BFIN_TRUE_IDE)
+# define CONFIG_BFIN_IDE 1
+# define ADD_IDE_CMD CFG_CMD_IDE
+#else
+# define ADD_IDE_CMD 0
+#endif
+
+/*#define CONFIG_BF537_NAND */ /* Add nand flash support */
+
+#ifdef CONFIG_BF537_NAND
+# define ADD_NAND_CMD CFG_CMD_NAND
+#else
+# define ADD_NAND_CMD 0
+#endif
+
+#define CONFIG_NETCONSOLE 1
+#define CONFIG_NET_MULTI 1
+
+#if (BFIN_CPU == ADSP_BF534)
+#define CONFIG_BFIN_CMD (CONFIG_CMD_DFL & ~CFG_CMD_NET)
+#else
+#define CONFIG_BFIN_CMD (CONFIG_CMD_DFL | CFG_CMD_PING)
+#endif
+
+#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
+#define CONFIG_COMMANDS (CONFIG_BFIN_CMD| \
+ CFG_CMD_ELF | \
+ CFG_CMD_I2C | \
+ CFG_CMD_CACHE | \
+ CFG_CMD_JFFS2 | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_DHCP | \
+ ADD_IDE_CMD | \
+ ADD_NAND_CMD | \
+ CFG_CMD_POST_DIAG | \
+ CFG_CMD_DATE)
+#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
+#define CONFIG_COMMANDS (CONFIG_BFIN_CMD| \
+ CFG_CMD_ELF | \
+ CFG_CMD_I2C | \
+ CFG_CMD_CACHE | \
+ CFG_CMD_JFFS2 | \
+ CFG_CMD_EEPROM | \
+ ADD_IDE_CMD | \
+ CFG_CMD_DATE)
+#endif
+
+#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
+#define CONFIG_LOADADDR 0x1000000
+
+#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
+#if (BFIN_CPU != ADSP_BF534)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$(serverip):$(rootpath) console=ttyBF0,57600\0"\
+ "addip=setenv bootargs $(bootargs) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
+ ":$(hostname):eth0:off\0" \
+ "ramboot=tftpboot $(loadaddr) linux;" \
+ "run ramargs;run addip;bootelf\0" \
+ "nfsboot=tftpboot $(loadaddr) linux;" \
+ "run nfsargs;run addip;bootelf\0" \
+ "flashboot=bootm 0x20100000\0" \
+ "update=tftpboot $(loadaddr) u-boot.bin;" \
+ "protect off 0x20000000 0x2007FFFF;" \
+ "erase 0x20000000 0x2007FFFF;cp.b 0x1000000 0x20000000 $(filesize)\0" \
+ ""
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
+ "flashboot=bootm 0x20100000\0" \
+ ""
+#endif
+#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
+#if (BFIN_CPU != ADSP_BF534)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$(serverip):$(rootpath) console=ttyBF0,57600\0"\
+ "addip=setenv bootargs $(bootargs) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
+ ":$(hostname):eth0:off\0" \
+ "ramboot=tftpboot $(loadaddr) linux;" \
+ "run ramargs;run addip;bootelf\0" \
+ "nfsboot=tftpboot $(loadaddr) linux;" \
+ "run nfsargs;run addip;bootelf\0" \
+ "flashboot=bootm 0x20100000\0" \
+ "update=tftpboot $(loadaddr) u-boot.ldr;" \
+ "eeprom write $(loadaddr) 0x0 $(filesize);\0" \
+ ""
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
+ "flashboot=bootm 0x20100000\0" \
+ ""
+#endif
+#endif
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
+#if (BFIN_CPU == ADSP_BF534)
+#define CFG_PROMPT "serial_bf534> " /* Monitor Command Prompt */
+#elif (BFIN_CPU == ADSP_BF536)
+#define CFG_PROMPT "serial_bf536> " /* Monitor Command Prompt */
+#else
+#define CFG_PROMPT "serial_bf537> " /* Monitor Command Prompt */
+#endif
+#else
+#if (BFIN_CPU == ADSP_BF534)
+#define CFG_PROMPT "bf534> " /* Monitor Command Prompt */
+#elif (BFIN_CPU == ADSP_BF536)
+#define CFG_PROMPT "bf536> " /* Monitor Command Prompt */
+#else
+#define CFG_PROMPT "bf537> " /* Monitor Command Prompt */
+#endif
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024*1024)
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_MEMTEST_START 0x0 /* memtest works on */
+#define CFG_MEMTEST_END ( (CONFIG_MEM_SIZE - 1) * 1024*1024) /* 1 ... 63 MB in DRAM */
+#define CFG_LOAD_ADDR CONFIG_LOADADDR /* default load address */
+#define CFG_HZ 1000 /* decrementer freq: 10 ms ticks */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CFG_SDRAM_BASE 0x00000000
+
+#define CFG_FLASH_BASE 0x20000000
+
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
+#define CFG_GBL_DATA_SIZE 0x4000
+#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
+#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4)
+
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
+
+#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) || (BFIN_BOOT_MODE == BF537_UART_BOOT)
+/* for bf537-stamp, usrt boot mode still store env in flash */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR 0x20004000
+#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
+#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
+#define CFG_ENV_IS_IN_EEPROM 1
+#define CFG_ENV_OFFSET 0x4000
+#define CFG_ENV_HEADER (CFG_ENV_OFFSET + 0x16e) /* 0x12A is the length of LDR file header */
+#endif
+#define CFG_ENV_SIZE 0x2000
+#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
+/* #if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) */
+#define ENV_IS_EMBEDDED
+/* #endif */
+
+/* JFFS Partition offset set */
+#define CFG_JFFS2_FIRST_BANK 0
+#define CFG_JFFS2_NUM_BANKS 1
+/* 512k reserved for u-boot */
+#define CFG_JFFS2_FIRST_SECTOR 15
+
+#define CONFIG_SPI
+
+/*
+ * Stack sizes
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+
+#define POLL_MODE 1
+#define FLASH_TOT_SECT 71
+#define FLASH_SIZE 0x400000
+#define CFG_FLASH_SIZE 0x400000
+
+/*
+ * Board NAND Infomation
+ */
+
+#define CFG_NAND_ADDR 0x20212000
+#define CFG_NAND_BASE CFG_NAND_ADDR
+#define CFG_MAX_NAND_DEVICE 1
+#define SECTORSIZE 512
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+#define NAND_ChipID_UNKNOWN 0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+#define BFIN_NAND_READY PF3
+
+#define NAND_WAIT_READY(nand) \
+ do { \
+ int timeout = 0; \
+ while(!(*pPORTFIO & PF3)) \
+ if (timeout++ > 100000) \
+ break; \
+ } while (0)
+
+#define BFIN_NAND_CLE (1<<2) /* A2 -> Command Enable */
+#define BFIN_NAND_ALE (1<<1) /* A1 -> Address Enable */
+
+#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_CLE) = (__u8)(d); } while(0)
+#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_ALE) = (__u8)(d); } while(0)
+#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
+#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+
+/*
+ * Initialize PSD4256 registers for using I2C
+ */
+#define CONFIG_MISC_INIT_R
+
+#define CFG_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */
+
+/*
+ * I2C settings
+ * By default PF1 is used as SDA and PF0 as SCL on the Stamp board
+ */
+/* #define CONFIG_SOFT_I2C 1*/ /* I2C bit-banged */
+#define CONFIG_HARD_I2C 1 /* I2C TWI */
+#if defined CONFIG_HARD_I2C
+#define CONFIG_TWICLK_KHZ 50
+#endif
+
+#if defined CONFIG_SOFT_I2C
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PF_SCL PF0
+#define PF_SDA PF1
+
+#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;")
+#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
+#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
+#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
+#define I2C_SDA(bit) if(bit) { \
+ *pFIO_FLAG_S = PF_SDA; \
+ asm("ssync;"); \
+ } \
+ else { \
+ *pFIO_FLAG_C = PF_SDA; \
+ asm("ssync;"); \
+ }
+#define I2C_SCL(bit) if(bit) { \
+ *pFIO_FLAG_S = PF_SCL; \
+ asm("ssync;"); \
+ } \
+ else { \
+ *pFIO_FLAG_C = PF_SCL; \
+ asm("ssync;"); \
+ }
+#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
+#endif
+
+#define CFG_I2C_SPEED 50000
+#define CFG_I2C_SLAVE 0xFE
+
+/* 0xFF, 0x7BB07BB0, 0x22547BB0 */
+/* #define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
+#define AMBCTL0VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \
+ ~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN)
+#define AMBCTL1VAL (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \
+ B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN)
+*/
+
+#define AMGCTLVAL 0xFF
+#define AMBCTL0VAL 0x7BB07BB0
+#define AMBCTL1VAL 0xFFC27BB0
+
+#define CONFIG_VDSP 1
+
+#ifdef CONFIG_VDSP
+#define ET_EXEC_VDSP 0x8
+#define SHT_STRTAB_VDSP 0x1
+#define ELFSHDRSIZE_VDSP 0x2C
+#define VDSP_ENTRY_ADDR 0xFFA00000
+#endif
+
+#if defined(CONFIG_BFIN_IDE)
+
+#define CONFIG_DOS_PARTITION 1
+/*
+ * IDE/ATA stuff
+ */
+#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
+#undef CONFIG_IDE_LED /* no led for ide supported */
+#undef CONFIG_IDE_RESET /* no reset for ide supported */
+
+#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
+#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+
+#undef AMBCTL1VAL
+#define AMBCTL1VAL 0xFFC3FFC3
+
+#define CONFIG_CF_ATASEL_DIS 0x20311800
+#define CONFIG_CF_ATASEL_ENA 0x20311802
+
+#if defined(CONFIG_BFIN_TRUE_IDE)
+/*
+ * Note that these settings aren't for the most part used in include/ata.h
+ * when all of the ATA registers are setup
+ */
+#define CFG_ATA_BASE_ADDR 0x2031C000
+#define CFG_ATA_IDE0_OFFSET 0x0000
+#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
+#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
+#define CFG_ATA_ALT_OFFSET 0x001C /* Offset for alternate registers */
+#define CFG_ATA_STRIDE 2 /* CF.A0 --> Blackfin.Ax */
+#endif /* CONFIG_BFIN_TRUE_IDE */
+
+#if defined(CONFIG_BFIN_CF_IDE) /* USE CompactFlash Storage Card in the common memory space */
+#define CFG_ATA_BASE_ADDR 0x20211800
+#define CFG_ATA_IDE0_OFFSET 0x0000
+#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
+#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
+#define CFG_ATA_ALT_OFFSET 0x000E /* Offset for alternate registers */
+#define CFG_ATA_STRIDE 1 /* CF.A0 --> Blackfin.Ax */
+#endif /* CONFIG_BFIN_CF_IDE */
+
+#if defined(CONFIG_BFIN_HDD_IDE) /* USE TRUE IDE */
+#define CFG_ATA_BASE_ADDR 0x20314000
+#define CFG_ATA_IDE0_OFFSET 0x0000
+#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
+#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
+#define CFG_ATA_ALT_OFFSET 0x001C /* Offset for alternate registers */
+#define CFG_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A1 */
+
+#undef CONFIG_SCLK_DIV
+#define CONFIG_SCLK_DIV 8
+#endif /* CONFIG_BFIN_HDD_IDE */
+
+#endif /*CONFIG_BFIN_IDE */
+
+#endif
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