]> git.sur5r.net Git - u-boot/commitdiff
usb: xhci: omap: Remove common dwc3 drv functions calls
authorRamneek Mehresh <ramneek.mehresh@freescale.com>
Fri, 29 May 2015 09:17:17 +0000 (14:47 +0530)
committerMarek Vasut <marex@denx.de>
Wed, 22 Jul 2015 06:55:44 +0000 (08:55 +0200)
Remove all redundant dwc3 driver function calls that
are defined by dwc3 driver

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
drivers/usb/host/xhci-omap.c
drivers/usb/phy/omap_usb_phy.c
include/configs/am43xx_evm.h
include/configs/beagle_x15.h
include/configs/dra7xx_evm.h

index 912b2bd8d582258c1898e3272a98e3510dd7873c..3a5520838447d75102e383ffb771e5ab0cab6213 100644 (file)
@@ -34,66 +34,6 @@ inline int __board_usb_init(int index, enum usb_init_type init)
 int board_usb_init(int index, enum usb_init_type init)
        __attribute__((weak, alias("__board_usb_init")));
 
-static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
-{
-       clrsetbits_le32(&dwc3_reg->g_ctl,
-                       DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
-                       DWC3_GCTL_PRTCAPDIR(mode));
-}
-
-static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
-{
-       /* Before Resetting PHY, put Core in Reset */
-       setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
-
-       omap_reset_usb_phy(dwc3_reg);
-
-       /* After PHYs are stable we can take Core out of reset state */
-       clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
-}
-
-static int dwc3_core_init(struct dwc3 *dwc3_reg)
-{
-       u32 reg;
-       u32 revision;
-       unsigned int dwc3_hwparams1;
-
-       revision = readl(&dwc3_reg->g_snpsid);
-       /* This should read as U3 followed by revision number */
-       if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
-               puts("this is not a DesignWare USB3 DRD Core\n");
-               return -1;
-       }
-
-       dwc3_core_soft_reset(dwc3_reg);
-
-       dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
-
-       reg = readl(&dwc3_reg->g_ctl);
-       reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
-       reg &= ~DWC3_GCTL_DISSCRAMBLE;
-       switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
-       case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
-               reg &= ~DWC3_GCTL_DSBLCLKGTNG;
-               break;
-       default:
-               debug("No power optimization available\n");
-       }
-
-       /*
-        * WORKAROUND: DWC3 revisions <1.90a have a bug
-        * where the device can fail to connect at SuperSpeed
-        * and falls back to high-speed mode which causes
-        * the device to enter a Connect/Disconnect loop
-        */
-       if ((revision & DWC3_REVISION_MASK) < 0x190a)
-               reg |= DWC3_GCTL_U2RSTECN;
-
-       writel(reg, &dwc3_reg->g_ctl);
-
-       return 0;
-}
-
 static int omap_xhci_core_init(struct omap_xhci *omap)
 {
        int ret = 0;
index 63d930168112fb4a692ed4f80578695996c0e90e..f9069c7f9c36ae8a16790bbab91e7d23b67b8eae 100644 (file)
@@ -223,24 +223,6 @@ void usb_phy_power(int on)
 }
 #endif /* CONFIG_AM437X_USB2PHY2_HOST */
 
-void omap_reset_usb_phy(struct dwc3 *dwc3_reg)
-{
-       /* Assert USB3 PHY reset */
-       setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
-
-       /* Assert USB2 PHY reset */
-       setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
-
-       mdelay(100);
-
-       /* Clear USB3 PHY reset */
-       clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
-
-       /* Clear USB2 PHY reset */
-       clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
-
-}
-
 void omap_enable_phy(struct omap_xhci *omap)
 {
 #ifdef CONFIG_OMAP_USB2PHY2_HOST
index 33e534a76583e8cedb16c149cfc69e5d8c2c0cf3..ccdfb9c160c52b920fb0998293cd4fe4bec691ec 100644 (file)
 #define CONFIG_CMD_USB
 #define CONFIG_USB_HOST
 #define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_XHCI_OMAP
 #define CONFIG_USB_STORAGE
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
index 17fdded138bd7e8eee535b83884107f01f7a0cf8..d38b7b55cf0bd6459aa7bdbc871ef0ada568d46d 100644 (file)
@@ -68,6 +68,7 @@
 /* USB xHCI HOST */
 #define CONFIG_CMD_USB
 #define CONFIG_USB_HOST
+#define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_XHCI
 #define CONFIG_USB_XHCI_OMAP
 #define CONFIG_USB_STORAGE
index d84427d1d8bc27d1ff3de503c81034457aa3fe48..0323c727e552d7331c571d9363eef267e7976a4d 100644 (file)
 #define CONFIG_CMD_USB
 #define CONFIG_USB_HOST
 #define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_XHCI_OMAP
 #define CONFIG_USB_STORAGE
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2