Need to gate ENET clock when switching to a new clock parent, because
the mux is not glitchless.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye.Li <ye.li@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
        writel(reg, &anatop->pll_enet);
 
 #ifdef CONFIG_MX6SX
+       /* Disable enet system clcok before switching clock parent */
+       reg = readl(&imx_ccm->CCGR3);
+       reg &= ~MXC_CCM_CCGR3_ENET_MASK;
+       writel(reg, &imx_ccm->CCGR3);
+
        /*
         * Set enet ahb clock to 200MHz
         * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB