#include <asm/io.h>
#include "fpga.h"
#include "mvbc_p.h"
+#include "../common/mv_common.h"
#define SDRAM_MODE 0x00CD0000
#define SDRAM_CONTROL 0x504F0000
printf("sint_gpioe : 0x%08x\n", gpio->sint_gpioe);
}
-void reset_environment(void)
-{
- char *s, sernr[64];
-
- printf("\n*** RESET ENVIRONMENT ***\n");
- memset(sernr, 0, sizeof(sernr));
- s = getenv("serial#");
- if (s) {
- printf("found serial# : %s\n", s);
- strncpy(sernr, s, 64);
- }
- gd->env_valid = 0;
- env_relocate();
- if (s)
- setenv("serial#", sernr);
-}
-
int misc_init_r(void)
{
char *s = getenv("reset_env");
return 0;
}
printf(" === FACTORY RESET ===\n");
- reset_environment();
+ mv_reset_environment();
saveenv();
return -1;
void pci_mvbc_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
{
unsigned char line = 0xff;
+ char *s = getenv("pci_latency");
u32 base;
+ u8 val = 0;
+
+ if (s)
+ val = simple_strtoul(s, NULL, 16);
if (PCI_BUS(dev) == 0) {
switch (PCI_DEV (dev)) {
case 0xa: /* FPGA */
line = 3;
pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &base);
- printf("found FPA - enable arbitration\n");
+ printf("found FPGA - enable arbitration\n");
writel(0x03, (u32*)(base + 0x80c0));
writel(0xf0, (u32*)(base + 0x8080));
+ if (val)
+ pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, val);
break;
case 0xb: /* LAN */
line = 2;
+ if (val)
+ pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, val);
break;
case 0x1a:
break;
fixup_irq:pci_mvbc_fixup_irq
};
-int mvbc_p_load_fpga(void)
-{
- size_t data_size = 0;
- void *fpga_data = NULL;
- char *datastr = getenv("fpgadata");
- char *sizestr = getenv("fpgadatasize");
-
- if (datastr)
- fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
- if (sizestr)
- data_size = (size_t)simple_strtoul(sizestr, NULL, 16);
-
- return fpga_load(0, fpga_data, data_size);
-}
-
extern void pci_mpc5xxx_init(struct pci_controller *);
void pci_init_board(void)
{
- char *s;
- int load_fpga = 1;
-
mvbc_p_init_fpga();
- s = getenv("skip_fpga");
- if (s) {
- printf("found 'skip_fpga' -> FPGA _not_ loaded !\n");
- load_fpga = 0;
- }
- if (load_fpga) {
- printf("loading FPGA ... ");
- mvbc_p_load_fpga();
- printf("done\n");
- }
+ mv_load_fpga();
pci_mpc5xxx_init(&hose);
}
-u8 *dhcp_vendorex_prep(u8 *e)
-{
- char *ptr;
-
- /* DHCP vendor-class-identifier = 60 */
- if ((ptr = getenv("dhcp_vendor-class-identifier"))) {
- *e++ = 60;
- *e++ = strlen(ptr);
- while (*ptr)
- *e++ = *ptr++;
- }
- /* DHCP_CLIENT_IDENTIFIER = 61 */
- if ((ptr = getenv("dhcp_client_id"))) {
- *e++ = 61;
- *e++ = strlen(ptr);
- while (*ptr)
- *e++ = *ptr++;
- }
-
- return e;
-}
-
-u8 *dhcp_vendorex_proc (u8 *popt)
-{
- return NULL;
-}
-
void show_boot_progress(int val)
{
struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
switch(val) {
case 0: /* FPGA ok */
- setbits_be32(&gpio->simple_dvo, 0x80);
+ setbits_be32(&gpio->simple_dvo, LED_G0);
break;
- case 1:
- setbits_be32(&gpio->simple_dvo, 0x40);
+ case 65:
+ setbits_be32(&gpio->simple_dvo, LED_G1);
break;
case 12:
- setbits_be32(&gpio->simple_dvo, 0x20);
+ setbits_be32(&gpio->simple_dvo, LED_Y);
break;
case 15:
- setbits_be32(&gpio->simple_dvo, 0x10);
+ setbits_be32(&gpio->simple_dvo, LED_R);
break;
default:
break;
#define SIMPLE_DDR (LED_G0 | LED_G1 | LED_Y | LED_R | \
FPGA_DIN | FPGA_CCLK | FPGA_CONFIG | WD_WDI)
#define SIMPLE_DVO (FPGA_CONFIG)
-#define SIMPLE_ODE (FPGA_CONFIG)
+#define SIMPLE_ODE (FPGA_CONFIG | LED_G0 | LED_G1 | LED_Y | LED_R)
#define SIMPLE_GPIOEN (LED_G0 | LED_G1 | LED_Y | LED_R | \
FPGA_DIN | FPGA_CCLK | FPGA_CONF_DONE | FPGA_CONFIG |\
WD_WDI | COP_PRESENT)
setenv ramkernel setenv kernel_boot \${loadaddr}
setenv flashkernel setenv kernel_boot \${mv_kernel_addr}
setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length}
-setenv bootfromflash run flashkernel cpird ramparam addcons e1000para bootdtb
+setenv bootfromflash run flashkernel cpird ramparam addcons e1000para addprofile bootdtb
setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name}
setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000
setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup
else
setenv addcons setenv bootargs \${bootargs} console=tty0
fi
-setenv e1000para setenv bootargs \${bootargs} e1000.TxDescriptors=1500 e1000.SmartPowerDownEnable=1
+setenv e1000para setenv bootargs \${bootargs} e1000.TxDescriptors=256 e1000.SmartPowerDownEnable=1
setenv set_static_ip setenv ipaddr \${static_ipaddr}
setenv set_static_nm setenv netmask \${static_netmask}
setenv set_static_gw setenv gatewayip \${static_gateway}
setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask}
setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs
+if test ${oprofile} = yes;
+then
+setenv addprofile setenv bootargs \${bootargs} profile=\${profile}
+fi
if test ${autoscr_boot} != no;
then
if test ${netboot} = yes;
then
echo "=== bootp succeeded -> netboot ==="
run set_ip
- run getdtb rundtb bootfromnet ramparam addcons e1000para bootdtb
+ run getdtb rundtb bootfromnet ramparam addcons e1000para addprofile bootdtb
else
echo "=== netboot failed ==="
fi
u32 msize = 0;
u32 ddr_size;
u32 ddr_size_log2;
+ char *s = getenv("ddr_size");
msize = CONFIG_SYS_DDR_SIZE;
+ if (s) {
+ u32 env_ddr_size = simple_strtoul(s, NULL, 10);
+ if (env_ddr_size == 512)
+ msize = 512;
+ }
+
for (ddr_size = msize << 20, ddr_size_log2 = 0;
(ddr_size > 1);
ddr_size = ddr_size >> 1, ddr_size_log2++) {
im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+ im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
- im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
+ im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
- udelay(300);
+ asm("sync;isync");
+ udelay(600);
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
- return CONFIG_SYS_DDR_SIZE;
+ asm("sync;isync");
+ udelay(500);
+
+ return msize;
}
phys_size_t initdram(int board_type)
return msize * 1024 * 1024;
}
-int checkboard(void)
+int misc_init_r(void)
{
- puts("Board: Matrix Vision mvBlueLYNX-M7\n");
-
- return 0;
-}
+ char *s = getenv("reset_env");
-u8 *dhcp_vendorex_prep(u8 *e)
-{
- char *ptr;
-
- /* DHCP vendor-class-identifier = 60 */
- ptr = getenv("dhcp_vendor-class-identifier");
- if (ptr) {
- *e++ = 60;
- *e++ = strlen(ptr);
- while (*ptr)
- *e++ = *ptr++;
- }
- /* DHCP_CLIENT_IDENTIFIER = 61 */
- ptr = getenv("dhcp_client_id");
- if (ptr) {
- *e++ = 61;
- *e++ = strlen(ptr);
- while (*ptr)
- *e++ = *ptr++;
+ if (s) {
+ mv_reset_environment();
}
- return e;
+ return 0;
}
-u8 *dhcp_vendorex_proc(u8 *popt)
+int checkboard(void)
{
- return NULL;
+ puts("Board: Matrix Vision mvBlueLYNX-M7\n");
+
+ return 0;
}
#ifdef CONFIG_HARD_SPI
#define FPGA_DIN 0x20000000
#define FPGA_STATUS 0x10000000
#define FPGA_CONF_DONE 0x08000000
-#define MMC_CS 0x04000000
#define WD_WDI 0x00400000
#define WD_TS 0x00200000
#define MAN_RST 0x00100000
#define MV_GPIO_DAT (WD_TS)
-#define MV_GPIO_OUT (FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|WD_TS|WD_WDI|MMC_CS)
+#define MV_GPIO_OUT (FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|MVBLM7_MMC_CS)
#define MV_GPIO_ODE (FPGA_CONFIG|MAN_RST)
#endif
#include <fpga.h>
#include "mvblm7.h"
#include "fpga.h"
+#include "../common/mv_common.h"
DECLARE_GLOBAL_DATA_PTR;
-int mvblm7_load_fpga(void)
-{
- size_t data_size = 0;
- void *fpga_data = NULL;
- char *datastr = getenv("fpgadata");
- char *sizestr = getenv("fpgadatasize");
-
- if (datastr)
- fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
- if (sizestr)
- data_size = (size_t)simple_strtoul(sizestr, NULL, 16);
-
- return fpga_load(0, fpga_data, data_size);
-}
-
static struct pci_region pci_regions[] = {
{
bus_start: CONFIG_SYS_PCI1_MEM_BASE,
void pci_init_board(void)
{
- char *s;
int i;
int warmboot;
- int load_fpga;
volatile immap_t *immr;
volatile pcictrl83xx_t *pci_ctrl;
volatile gpio83xx_t *gpio;
volatile law83xx_t *pci_law;
struct pci_region *reg[] = { pci_regions };
- load_fpga = 1;
immr = (immap_t *) CONFIG_SYS_IMMR;
clk = (clk83xx_t *) &immr->clk;
pci_ctrl = immr->pci_ctrl;
pci_law = immr->sysconf.pcilaw;
gpio = (volatile gpio83xx_t *)&immr->gpio[0];
- s = getenv("skip_fpga");
- if (s) {
- printf("found 'skip_fpga' -> FPGA _not_ loaded !\n");
- load_fpga = 0;
- }
-
gpio->dat = MV_GPIO_DAT;
gpio->odr = MV_GPIO_ODE;
- if (load_fpga)
- gpio->dir = MV_GPIO_OUT;
- else
- gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK);
+ gpio->dir = MV_GPIO_OUT;
printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh,
immr->sysconf.sicrl);
mvblm7_init_fpga();
- if (load_fpga)
- mvblm7_load_fpga();
+ mv_load_fpga();
+
+ gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK);
/* Enable PCI_CLK_OUTPUTs 0 and 1 with 1:1 clocking */
clk->occr = 0xc0000000;
#define MV_CI mvBlueCOUGAR-P
#define MV_VCI mvBlueCOUGAR-P
#define MV_FPGA_DATA 0xff860000
-#define MV_FPGA_SIZE 0x0003c886
+#define MV_FPGA_SIZE 0
#define MV_KERNEL_ADDR 0xffd00000
#define MV_INITRD_ADDR 0xff900000
#define MV_INITRD_LENGTH 0x00400000
#define CONFIG_MPC8XXX_SPI
#define CONFIG_HARD_SPI
#define MVBLM7_MMC_CS 0x04000000
+#define CONFIG_MISC_INIT_R
/* I2C */
-#undef CONFIG_SOFT_I2C
-
#define CONFIG_FSL_I2C
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_I2C_OFFSET 0x3000
/*
* DDR Setup
*/
+#undef CONFIG_SPD_EEPROM
+
#define CONFIG_SYS_DDR_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_83XX_DDR_USES_CS0 1
#define CONFIG_SYS_MEMTEST_START (60<<20)
#define CONFIG_SYS_MEMTEST_END (70<<20)
+#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
- DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
-
-#define CONFIG_SYS_DDR_SIZE 256
+#define CONFIG_SYS_DDRCDR 0x22000001
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
-/* HC, 75Ohm, DDR-II, DRQ */
-#define CONFIG_SYS_DDRCDR 0x80000001
-/* EN, ODT_WR, 3BA, 14row, 10col */
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014102
-#define CONFIG_SYS_DDR_CS1_CONFIG 0x0
-#define CONFIG_SYS_DDR_CS2_CONFIG 0x0
-#define CONFIG_SYS_DDR_CS3_CONFIG 0x0
+#define CONFIG_SYS_DDR_SIZE 512
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
-#define CONFIG_SYS_DDR_CS1_BNDS 0x0
-#define CONFIG_SYS_DDR_CS2_BNDS 0x0
-#define CONFIG_SYS_DDR_CS3_BNDS 0x0
+#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
-#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
+#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
-#define CONFIG_SYS_DDR_TIMING_0 0x00260802
-#define CONFIG_SYS_DDR_TIMING_1 0x2625b221
-#define CONFIG_SYS_DDR_TIMING_2 0x1f9820c7
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
+#define CONFIG_SYS_DDR_TIMING_0 0x00260802
+#define CONFIG_SYS_DDR_TIMING_1 0x3837c322
+#define CONFIG_SYS_DDR_TIMING_2 0x0f9848c6
+#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-/* ~MEM_EN, SREN, DDR-II, 32_BE */
-#define CONFIG_SYS_DDR_SDRAM_CFG 0x43080000
+#define CONFIG_SYS_DDR_SDRAM_CFG 0x43080008
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
-#define CONFIG_SYS_DDR_INTERVAL 0x04060100
+#define CONFIG_SYS_DDR_INTERVAL 0x02000100
-#define CONFIG_SYS_DDR_MODE 0x078e0232
+#define CONFIG_SYS_DDR_MODE 0x04040242
+#define CONFIG_SYS_DDR_MODE2 0x00800000
/* Flash */
#define CONFIG_SYS_FLASH_CFI
#define MV_CI mvBL-M7
#define MV_VCI mvBL-M7
-#define MV_FPGA_DATA 0xfff80000
-#define MV_FPGA_SIZE 0x00076ca2
+#define MV_FPGA_DATA 0xfff40000
+#define MV_FPGA_SIZE 0
#define MV_KERNEL_ADDR 0xff810000
#define MV_INITRD_ADDR 0xffb00000
#define MV_SOURCE_ADDR 0xff804000
"static_ipaddr=192.168.90.10\0" \
"static_netmask=255.255.255.0\0" \
"static_gateway=0.0.0.0\0" \
- "initrd_name=uInitrd.mvblm7-xenorfs\0" \
+ "initrd_name=uInitrd.mvBL-M7-rfs\0" \
"zcip=no\0" \
"netboot=yes\0" \
"mvtest=Ff\0" \
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