struct armdfec_device *darmdfec = to_darmdfec(dev);
        struct armdfec_reg *regs = darmdfec->regs;
        int phy_adr;
+       u32 temp;
 
        armdfec_init_rx_desc_ring(darmdfec);
 
        update_hash_table_mac_address(darmdfec, NULL, dev->enetaddr);
 
        /* Update TX and RX queue descriptor register */
-       writel((u32)darmdfec->p_txdesc, ®s->txcdp[TXQ]);
-       writel((u32)darmdfec->p_rxdesc, ®s->rxfdp[RXQ]);
-       writel((u32)darmdfec->p_rxdesc_curr, ®s->rxcdp[RXQ]);
+       temp = (u32)®s->txcdp[TXQ];
+       writel((u32)darmdfec->p_txdesc, temp);
+       temp = (u32)®s->rxfdp[RXQ];
+       writel((u32)darmdfec->p_rxdesc, temp);
+       temp = (u32)®s->rxcdp[RXQ];
+       writel((u32)darmdfec->p_rxdesc_curr, temp);
 
        /* Enable Interrupts */
        writel(ALL_INTS, ®s->im);
        struct rx_desc *p_rxdesc_curr = darmdfec->p_rxdesc_curr;
        u32 cmd_sts;
        u32 timeout = 0;
+       u32 temp;
 
        /* wait untill rx packet available or timeout */
        do {
        p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
        p_rxdesc_curr->byte_cnt = 0;
 
-       writel((u32)p_rxdesc_curr->nxtdesc_p, (u32)&darmdfec->p_rxdesc_curr);
+       temp = (u32)&darmdfec->p_rxdesc_curr;
+       writel((u32)p_rxdesc_curr->nxtdesc_p, temp);
 
        return 0;
 }