ppc4xx: Add DDR1/2 macros in ppc4xx-sdram.h for non-405EX as well

This patch adds some DDR(2) macros to all PPC4xx's equipped with
this IBM DDR1/2 controller.

Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/arch/powerpc/include/asm/ppc4xx-sdram.h b/arch/powerpc/include/asm/ppc4xx-sdram.h
index 66cf50902d06f84a72ee7a20bd3812f96f8869be..d9506e27c1fde792c8c4a2915484cc7c9245549f 100644 (file)
--- a/arch/powerpc/include/asm/ppc4xx-sdram.h
+++ b/arch/powerpc/include/asm/ppc4xx-sdram.h
@@ -344,6 +344,9 @@
 #define SDRAM_RXBAS_SDSZ_2048          SDRAM_RXBAS_SDSZ_2048MB
 #define SDRAM_RXBAS_SDSZ_4096          SDRAM_RXBAS_SDSZ_4096MB
 #define SDRAM_RXBAS_SDSZ_8192          SDRAM_RXBAS_SDSZ_8192MB
+#endif /* CONFIG_405EX */
+
+/* The mode definitions are the same for all PPC4xx variants */
 #define SDRAM_RXBAS_SDAM_MODE0         PPC_REG_VAL(23, 0x0)
 #define SDRAM_RXBAS_SDAM_MODE1         PPC_REG_VAL(23, 0x1)
 #define SDRAM_RXBAS_SDAM_MODE2         PPC_REG_VAL(23, 0x2)
@@ -356,7 +359,6 @@
 #define SDRAM_RXBAS_SDAM_MODE9         PPC_REG_VAL(23, 0x9)
 #define SDRAM_RXBAS_SDBE_DISABLE       PPC_REG_VAL(31, 0x0)
 #define SDRAM_RXBAS_SDBE_ENABLE                PPC_REG_VAL(31, 0x1)
-#endif /* CONFIG_405EX */
 
 /*
  * Memory controller registers