powerpc/corenet_ds: Slave module for boot from SRIO

For the powerpc processors with SRIO interface, boot location can be configured
from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash
for u-boot image. The image can be fetched from another processor's memory
space by SRIO link connected between them.

The processor boots from SRIO is slave, the processor boots from normal flash
memory space and can help slave to boot from its memory space is master.
They are different environments and requirements:

master:
	1. NOR flash for its own u-boot image, ucode and ENV space.
	2. Slave's u-boot image in master NOR flash.
	3. Normally boot from local NOR flash.
	4. Configure SRIO switch system if needed.
slave:
	1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
	2. Boot location should be set to SRIO1 or SRIO2 by RCW.
	3. RCW should configure the SerDes, SRIO interfaces correctly.
	4. Slave must be powered on after master's boot.
	5. Must define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE because of no ucode
	   locally.

For the slave module, need to finish these processes:
	1. Set the boot location to SRIO1 or SRIO2 by RCW.
    2. Set a specific TLB entry for the boot process.
	3. Set a LAW entry with the TargetID SRIO1 or SRIO2 for the boot.
	4. Slave's u-boot image should be generated specifically by
	   make xxxx_SRIOBOOT_SLAVE_config.
	   This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>

diff --git a/README b/README
index 43074cf65f8327e98f1c007f889fe9c69a6869b8..da15105617eb0a6ad58f906d087e9f8ab6a0d148 100644 (file)
--- a/README
+++ b/README
@@ -3462,6 +3462,12 @@ within that device.
        Specifies that QE/FMAN firmware is located on the primary SPI
        device.  CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device.
 
+- CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
+       Specifies that QE/FMAN firmware is located in the remote (master)
+       memory space.   CONFIG_SYS_FMAN_FW_ADDR is a virtual address which
+       can be mapped from slave TLB->slave LAW->slave SRIO outbound window
+       ->master inbound window->master LAW->the ucode address in master's
+       NOR flash.
 
 Building the Software:
 ======================

diff --git a/board/freescale/common/p_corenet/law.c b/board/freescale/common/p_corenet/law.c
index 09ef5615d26e1db1b9599d89f945b68a05382d56..1fbab4d9684894551971b8387ff8ac5a9ad03fb7 100644 (file)
--- a/board/freescale/common/p_corenet/law.c
+++ b/board/freescale/common/p_corenet/law.c
@@ -48,6 +48,15 @@ struct law_entry law_table[] = {
 #ifdef CONFIG_SYS_NAND_BASE_PHYS
        SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
 #endif
+#ifdef CONFIG_SRIOBOOT_SLAVE
+#if defined(CONFIG_SRIOBOOT_SLAVE_PORT0)
+       SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
+                               LAW_SIZE_1M, LAW_TRGT_IF_RIO_1),
+#elif defined(CONFIG_SRIOBOOT_SLAVE_PORT1)
+       SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
+                               LAW_SIZE_1M, LAW_TRGT_IF_RIO_2),
+#endif
+#endif
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);

diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c
index 6a0026a2cf7b5a7955a79eb212d0f28f25bd28ce..a8c8b3c3a869465060a0747d1a326a72bbde1ecf 100644 (file)
--- a/board/freescale/common/p_corenet/tlb.c
+++ b/board/freescale/common/p_corenet/tlb.c
@@ -66,6 +66,15 @@ struct fsl_e_tlb_entry tlb_table[] = {
        SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                        0, 0, BOOKE_PAGESZ_1M, 1),
+#elif defined(CONFIG_SRIOBOOT_SLAVE)
+       /*
+        * SRIOBOOT-SLAVE. When slave boot, the address of the
+        * space is at 0xfff00000, it covered the 0xfffff000.
+        */
+       SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_SLAVE_ADDR,
+                       CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
+                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+                       0, 0, BOOKE_PAGESZ_1M, 1),
 #else
        SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,

diff --git a/boards.cfg b/boards.cfg
index 4821dfb27dfa90e88c7b8f96089f0c101c78c631..7194e08960673dafdfc515d5570280f6f0ae8b95 100644 (file)
--- a/boards.cfg
+++ b/boards.cfg
@@ -752,6 +752,7 @@ P3041DS_SDCARD                   powerpc     mpc85xx     corenet_ds          freescale
 P3041DS_SECURE_BOOT          powerpc     mpc85xx     corenet_ds          freescale      -           P3041DS:SECURE_BOOT
 P3041DS_SPIFLASH            powerpc     mpc85xx     corenet_ds          freescale      -           P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
 P3041DS_SRIOBOOT_MASTER                     powerpc     mpc85xx     corenet_ds          freescale      -           P3041DS:SRIOBOOT_MASTER
+P3041DS_SRIOBOOT_SLAVE          powerpc     mpc85xx     corenet_ds          freescale      -           P3041DS:SRIOBOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
 P3060QDS                    powerpc     mpc85xx     p3060qds            freescale
 P3060QDS_NAND               powerpc     mpc85xx     p3060qds            freescale      -           P3060QDS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
 P3060QDS_SECURE_BOOT         powerpc     mpc85xx     p3060qds            freescale      -           P3060QDS:SECURE_BOOT
@@ -760,12 +761,14 @@ P4080DS_SDCARD                 powerpc     mpc85xx     corenet_ds          freescale
 P4080DS_SECURE_BOOT          powerpc     mpc85xx     corenet_ds          freescale      -           P4080DS:SECURE_BOOT
 P4080DS_SPIFLASH            powerpc     mpc85xx     corenet_ds          freescale      -           P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
 P4080DS_SRIOBOOT_MASTER                     powerpc     mpc85xx     corenet_ds          freescale      -           P4080DS:SRIOBOOT_MASTER
+P4080DS_SRIOBOOT_SLAVE          powerpc     mpc85xx     corenet_ds          freescale      -           P4080DS:SRIOBOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
 P5020DS                      powerpc     mpc85xx     corenet_ds          freescale
 P5020DS_NAND                powerpc     mpc85xx     corenet_ds          freescale      -           P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
 P5020DS_SDCARD              powerpc     mpc85xx     corenet_ds          freescale      -           P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
 P5020DS_SECURE_BOOT          powerpc     mpc85xx     corenet_ds          freescale      -           P5020DS:SECURE_BOOT
 P5020DS_SPIFLASH            powerpc     mpc85xx     corenet_ds          freescale      -           P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
 P5020DS_SRIOBOOT_MASTER                     powerpc     mpc85xx     corenet_ds          freescale      -           P5020DS:SRIOBOOT_MASTER
+P5020DS_SRIOBOOT_SLAVE          powerpc     mpc85xx     corenet_ds          freescale      -           P5020DS:SRIOBOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
 stxgp3                       powerpc     mpc85xx     stxgp3              stx
 stxssa                       powerpc     mpc85xx     stxssa              stx            -           stxssa
 stxssa_4M                    powerpc     mpc85xx     stxssa              stx            -           stxssa:STXSSA_4M

diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index 0b8c33fb7a34eed43a3a32fd6c0c527fef818414..49c74c278ae668644e67f88e023ec17380eb996f 100644 (file)
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -408,6 +408,8 @@ int fm_init_common(int index, struct ccsr_fman *reg)
                /* flush cache after read */
                flush_cache((ulong)addr, cnt * 512);
        }
+#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_REMOTE)
+       void *addr = (void *)CONFIG_SYS_QE_FMAN_FW_ADDR;
 #endif
 
        /* Upload the Fman microcode if it's present */

diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index a31ccc294644943d14b73a2e487e16f945df137e..8ff1408c6078456920837651c97711db9b813819 100644 (file)
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -33,6 +33,15 @@
 #define CONFIG_RESET_VECTOR_ADDRESS    0xfffffffc
 #endif
 
+#ifdef CONFIG_SRIOBOOT_SLAVE
+/* Set 1M boot space */
+#define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS \
+               (0x300000000ull | CONFIG_SYS_SRIOBOOT_SLAVE_ADDR)
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_SYS_NO_FLASH
+#endif
+
 /* High Level Configuration Options */
 #define CONFIG_BOOKE
 #define CONFIG_E500                    /* BOOKE e500 family */
@@ -392,6 +401,15 @@
 #define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2 0x3fff80000ull
 #endif
 
+/*
+ * SRIOBOOT - SLAVE
+ */
+#ifdef CONFIG_SRIOBOOT_SLAVE
+/* slave port for srioboot */
+#define CONFIG_SRIOBOOT_SLAVE_PORT0
+/* #define CONFIG_SRIOBOOT_SLAVE_PORT1 */
+#endif
+
 /*
  * eSPI - Enhanced SPI
  */
@@ -512,6 +530,16 @@
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_QE_FMAN_FW_ADDR     (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIOBOOT_SLAVE)
+/*
+ * Slave has no ucode locally, it can fetch this from remote. When implementing
+ * in two corenet boards, slave's ucode could be stored in master's memory
+ * space, the address can be mapped from slave TLB->slave LAW->
+ * slave SRIO outbound window->master inbound window->master LAW->
+ * the ucode address in master's NOR flash.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
+#define CONFIG_SYS_QE_FMAN_FW_ADDR     NULL
 #else
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_QE_FMAN_FW_ADDR             0xEF000000