]> git.sur5r.net Git - u-boot/commitdiff
Tegra: Change Tegra20 to Tegra in common code, prep for T30
authorTom Warren <twarren@nvidia.com>
Wed, 5 Sep 2012 00:00:24 +0000 (17:00 -0700)
committerTom Warren <twarren@nvidia.com>
Mon, 10 Sep 2012 20:01:24 +0000 (13:01 -0700)
Convert TEGRA20_ defines to either TEGRA_ or NV_PA_ where appropriate.
Convert tegra20_ source file and function names to tegra_, also.

Upcoming Tegra30 port will use common code/defines/names where possible.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
39 files changed:
arch/arm/cpu/arm720t/tegra20/cpu.c
arch/arm/cpu/armv7/tegra20/cmd_enterrcm.c
arch/arm/cpu/tegra20-common/Makefile
arch/arm/cpu/tegra20-common/ap20.c
arch/arm/cpu/tegra20-common/board.c
arch/arm/cpu/tegra20-common/warmboot.c
arch/arm/cpu/tegra20-common/warmboot_avp.c
arch/arm/include/asm/arch-tegra20/ap20.h
arch/arm/include/asm/arch-tegra20/mmc.h
arch/arm/include/asm/arch-tegra20/sys_proto.h
arch/arm/include/asm/arch-tegra20/tegra20.h
arch/arm/include/asm/arch-tegra20/tegra_mmc.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra20/tegra_spi.h
arch/arm/include/asm/arch-tegra20/timer.h
board/avionic-design/common/tamonten.c
board/compal/paz00/paz00.c
board/compulab/trimslice/trimslice.c
board/nvidia/common/board.c
board/nvidia/harmony/harmony.c
board/nvidia/seaboard/seaboard.c
board/nvidia/whistler/whistler.c
drivers/gpio/tegra_gpio.c
drivers/i2c/tegra_i2c.c
drivers/input/Makefile
drivers/mmc/tegra_mmc.c
drivers/mmc/tegra_mmc.h [deleted file]
drivers/spi/tegra_spi.c
include/configs/harmony.h
include/configs/medcom.h
include/configs/paz00.h
include/configs/plutux.h
include/configs/seaboard.h
include/configs/tec.h
include/configs/tegra-common-post.h [new file with mode: 0644]
include/configs/tegra20-common-post.h [deleted file]
include/configs/tegra20-common.h
include/configs/trimslice.h
include/configs/ventana.h
include/configs/whistler.h

index 6d4d66bced059ca0cffcd56c089d1cfbf1e5e81d..ddf8d979f448c6dd4f356492340510aa789e2e96 100644 (file)
@@ -105,14 +105,14 @@ static void enable_cpu_clock(int enable)
 
 static int is_cpu_powered(void)
 {
-       struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+       struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
 
        return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
 }
 
 static void remove_cpu_io_clamps(void)
 {
-       struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+       struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
        u32 reg;
 
        /* Remove the clamps on the CPU I/O signals */
@@ -126,7 +126,7 @@ static void remove_cpu_io_clamps(void)
 
 static void powerup_cpu(void)
 {
-       struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+       struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
        u32 reg;
        int timeout = IO_STABILIZATION_DELAY;
 
@@ -157,7 +157,7 @@ static void powerup_cpu(void)
 
 static void enable_cpu_power_rail(void)
 {
-       struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+       struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
        u32 reg;
 
        reg = readl(&pmc->pmc_cntrl);
index 75cadb03ec7f05370cb5aee58e476254e773416c..925f8414c4df7f6cfdb4418bb9c5b81eb0a55ebb 100644 (file)
@@ -46,7 +46,7 @@
 static int do_enterrcm(cmd_tbl_t *cmdtp, int flag, int argc,
                       char * const argv[])
 {
-       struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+       struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
 
        puts("Entering RCM...\n");
        udelay(50000);
index 43c96c6864314e6615bc278caf70829c1f8abbe9..9e91e5cb8ca0efd2ffd84cae49b41fa706369124 100644 (file)
@@ -33,7 +33,7 @@ LIB   = $(obj)lib$(SOC)-common.o
 
 SOBJS += lowlevel_init.o
 COBJS-y        += ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o
-COBJS-$(CONFIG_TEGRA20_LP0) += warmboot.o crypto.o warmboot_avp.o
+COBJS-$(CONFIG_TEGRA_LP0) += warmboot.o crypto.o warmboot_avp.o
 COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
 COBJS-$(CONFIG_TEGRA_PMU) += pmu.o
 
index 00588dae527095ff077955bb322145e859d69758..c0ca6eb379e4733de3fea5fcd81b58139f4dbe2b 100644 (file)
@@ -32,7 +32,7 @@
 int tegra_get_chip_type(void)
 {
        struct apb_misc_gp_ctlr *gp;
-       struct fuse_regs *fuse = (struct fuse_regs *)TEGRA20_FUSE_BASE;
+       struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
        uint tegra_sku_id, rev;
 
        /*
@@ -40,7 +40,7 @@ int tegra_get_chip_type(void)
         * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
         * Tegra30
         */
-       gp = (struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE;
+       gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
        rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
 
        tegra_sku_id = readl(&fuse->sku_info) & 0xff;
@@ -101,7 +101,7 @@ static u32 get_odmdata(void)
 
 static void init_pmc_scratch(void)
 {
-       struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+       struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
        u32 odmdata;
        int i;
 
index 598023aba9a1885f8075a632734896324162bf52..8a8d3384ac4b4ba51731c53552df4b8b0e170311 100644 (file)
@@ -47,7 +47,7 @@ enum {
 
 unsigned int query_sdram_size(void)
 {
-       struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+       struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
        u32 reg;
 
        reg = readl(&pmc->pmc_scratch20);
@@ -81,11 +81,11 @@ int checkboard(void)
 #endif /* CONFIG_DISPLAY_BOARDINFO */
 
 static int uart_configs[] = {
-#if defined(CONFIG_TEGRA20_UARTA_UAA_UAB)
+#if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
        FUNCMUX_UART1_UAA_UAB,
-#elif defined(CONFIG_TEGRA20_UARTA_GPU)
+#elif defined(CONFIG_TEGRA_UARTA_GPU)
        FUNCMUX_UART1_GPU,
-#elif defined(CONFIG_TEGRA20_UARTA_SDIO1)
+#elif defined(CONFIG_TEGRA_UARTA_SDIO1)
        FUNCMUX_UART1_SDIO1,
 #else
        FUNCMUX_UART1_IRRX_IRTX,
@@ -125,13 +125,13 @@ void board_init_uart_f(void)
 {
        int uart_ids = 0;       /* bit mask of which UART ids to enable */
 
-#ifdef CONFIG_TEGRA20_ENABLE_UARTA
+#ifdef CONFIG_TEGRA_ENABLE_UARTA
        uart_ids |= UARTA;
 #endif
-#ifdef CONFIG_TEGRA20_ENABLE_UARTB
+#ifdef CONFIG_TEGRA_ENABLE_UARTB
        uart_ids |= UARTB;
 #endif
-#ifdef CONFIG_TEGRA20_ENABLE_UARTD
+#ifdef CONFIG_TEGRA_ENABLE_UARTD
        uart_ids |= UARTD;
 #endif
        setup_uarts(uart_ids);
index 809ea0133ebaa6871d64db8186282546b6fb29b2..6ce995ef02948fa2a5f4c99a6be5e3c36f324217 100644 (file)
@@ -39,7 +39,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifndef CONFIG_TEGRA_CLOCK_SCALING
-#error "You must enable CONFIG_TEGRA_CLOCK_SCALING to use CONFIG_TEGRA20_LP0"
+#error "You must enable CONFIG_TEGRA_CLOCK_SCALING to use CONFIG_TEGRA_LP0"
 #endif
 
 /*
@@ -139,9 +139,9 @@ int warmboot_save_sdram_params(void)
        u32 ram_code;
        struct sdram_params sdram;
        struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+       struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
        struct apb_misc_gp_ctlr *gp =
-                       (struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE;
+                       (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
        struct emc_ctlr *emc = emc_get_controller(gd->fdt_blob);
        union scratch2_reg scratch2;
        union scratch4_reg scratch4;
@@ -205,7 +205,7 @@ static u32 get_major_version(void)
 {
        u32 major_id;
        struct apb_misc_gp_ctlr *gp =
-               (struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE;
+               (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
 
        major_id = (readl(&gp->hidrev) & HIDREV_MAJORPREV_MASK) >>
                        HIDREV_MAJORPREV_SHIFT;
@@ -229,7 +229,7 @@ static int is_failure_analysis_mode(struct fuse_regs *fuse)
 
 static int ap20_is_odm_production_mode(void)
 {
-       struct fuse_regs *fuse = (struct fuse_regs *)TEGRA20_FUSE_BASE;
+       struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
 
        if (!is_failure_analysis_mode(fuse) &&
            is_odm_production_mode_fuse_set(fuse))
@@ -240,7 +240,7 @@ static int ap20_is_odm_production_mode(void)
 
 static int ap20_is_production_mode(void)
 {
-       struct fuse_regs *fuse = (struct fuse_regs *)TEGRA20_FUSE_BASE;
+       struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
 
        if (get_major_version() == 0)
                return 1;
@@ -257,7 +257,7 @@ static enum fuse_operating_mode fuse_get_operation_mode(void)
 {
        u32 chip_id;
        struct apb_misc_gp_ctlr *gp =
-               (struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE;
+               (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
 
        chip_id = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >>
                        HIDREV_CHIPID_SHIFT;
index cd01908a462e604693089abbe8ea2148dbece308..80a5a15decf6e0082d1fa109cbae006ba94b4008 100644 (file)
@@ -38,7 +38,7 @@
 void wb_start(void)
 {
        struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+       struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
        struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
        struct clk_rst_ctlr *clkrst =
                        (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
index c84d22f97bd7519222998f68ee23484d863c8160..70d94c50417390c6ad8705c0c3d480edb89c27ec 100644 (file)
@@ -95,9 +95,6 @@
 #define HALT_COP_EVENT_IRQ_1           (1 << 11)
 #define HALT_COP_EVENT_FIQ_1           (1 << 9)
 
-/* Start up the tegra20 SOC */
-void tegra20_start(void);
-
 /* This is the main entry into U-Boot, used by the Cortex-A9 */
 extern void _start(void);
 
index 916a353a97d6a0e7163213152b304da7b3efe207..5c95047998c6d030c1a2f50a91010313ff89c6fd 100644 (file)
@@ -19,9 +19,9 @@
  * MA 02111-1307 USA
  */
 
-#ifndef _TEGRA20_MMC_H_
-#define _TEGRA20_MMC_H_
+#ifndef _TEGRA_MMC_H_
+#define _TEGRA_MMC_H_
 
-int tegra20_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio);
+int tegra_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio);
 
-#endif /* TEGRA20_MMC_H_ */
+#endif /* _TEGRA_MMC_H_ */
index 643d5424b841d2a8839c607177e1d78e00124de7..919aec7f74c37f099bdf91ae32044720d4e53d68 100644 (file)
 #ifndef _SYS_PROTO_H_
 #define _SYS_PROTO_H_
 
-struct tegra20_sysinfo {
+struct tegra_sysinfo {
        char *board_string;
 };
 
 void invalidate_dcache(void);
 
-extern const struct tegra20_sysinfo sysinfo;
+extern const struct tegra_sysinfo sysinfo;
 
 #endif
index b2fb50e33e79b7aab2fa4f4b32d74a0810d48c23..c9485a1c8443ebb03ee926bbea1682295e8263bb 100644 (file)
 #define NV_PA_GPIO_BASE                0x6000D000
 #define NV_PA_EVP_BASE         0x6000F000
 #define NV_PA_APB_MISC_BASE    0x70000000
-#define TEGRA20_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800)
+#define NV_PA_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800)
 #define NV_PA_APB_UARTA_BASE   (NV_PA_APB_MISC_BASE + 0x6000)
 #define NV_PA_APB_UARTB_BASE   (NV_PA_APB_MISC_BASE + 0x6040)
 #define NV_PA_APB_UARTC_BASE   (NV_PA_APB_MISC_BASE + 0x6200)
 #define NV_PA_APB_UARTD_BASE   (NV_PA_APB_MISC_BASE + 0x6300)
 #define NV_PA_APB_UARTE_BASE   (NV_PA_APB_MISC_BASE + 0x6400)
-#define TEGRA20_NAND_BASE      (NV_PA_APB_MISC_BASE + 0x8000)
-#define TEGRA20_SPI_BASE       (NV_PA_APB_MISC_BASE + 0xC380)
-#define TEGRA20_PMC_BASE       (NV_PA_APB_MISC_BASE + 0xE400)
-#define TEGRA20_FUSE_BASE      (NV_PA_APB_MISC_BASE + 0xF800)
+#define NV_PA_NAND_BASE                (NV_PA_APB_MISC_BASE + 0x8000)
+#define NV_PA_SPI_BASE         (NV_PA_APB_MISC_BASE + 0xC380)
+#define NV_PA_PMC_BASE         (NV_PA_APB_MISC_BASE + 0xE400)
+#define NV_PA_FUSE_BASE                (NV_PA_APB_MISC_BASE + 0xF800)
 #define NV_PA_CSITE_BASE       0x70040000
 #define TEGRA_USB1_BASE                0xC5000000
 #define TEGRA_USB3_BASE                0xC5008000
 #define TEGRA_USB_ADDR_MASK    0xFFFFC000
 
-#define TEGRA20_SDRC_CS0       NV_PA_SDRAM_BASE
+#define NV_PA_SDRC_CS0         NV_PA_SDRAM_BASE
 #define LOW_LEVEL_SRAM_STACK   0x4000FFFC
 #define EARLY_AVP_STACK                (NV_PA_SDRAM_BASE + 0x20000)
 #define EARLY_CPU_STACK                (EARLY_AVP_STACK - 4096)
@@ -86,7 +86,7 @@ enum {
 };
 
 #else  /* __ASSEMBLY__ */
-#define PRM_RSTCTRL            TEGRA20_PMC_BASE
+#define PRM_RSTCTRL            NV_PA_PMC_BASE
 #endif
 
 #endif /* TEGRA20_H */
diff --git a/arch/arm/include/asm/arch-tegra20/tegra_mmc.h b/arch/arm/include/asm/arch-tegra20/tegra_mmc.h
new file mode 100644 (file)
index 0000000..dd746ca
--- /dev/null
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2009 SAMSUNG Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Portions Copyright (C) 2011-2012 NVIDIA Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __TEGRA_MMC_H_
+#define __TEGRA_MMC_H_
+
+#define TEGRA_SDMMC1_BASE      0xC8000000
+#define TEGRA_SDMMC2_BASE      0xC8000200
+#define TEGRA_SDMMC3_BASE      0xC8000400
+#define TEGRA_SDMMC4_BASE      0xC8000600
+
+#ifndef __ASSEMBLY__
+struct tegra_mmc {
+       unsigned int    sysad;          /* _SYSTEM_ADDRESS_0 */
+       unsigned short  blksize;        /* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */
+       unsigned short  blkcnt;         /* _BLOCK_SIZE_BLOCK_COUNT_0 31:16 */
+       unsigned int    argument;       /* _ARGUMENT_0 */
+       unsigned short  trnmod;         /* _CMD_XFER_MODE_0 15:00 xfer mode */
+       unsigned short  cmdreg;         /* _CMD_XFER_MODE_0 31:16 cmd reg */
+       unsigned int    rspreg0;        /* _RESPONSE_R0_R1_0 CMD RESP 31:00 */
+       unsigned int    rspreg1;        /* _RESPONSE_R2_R3_0 CMD RESP 63:32 */
+       unsigned int    rspreg2;        /* _RESPONSE_R4_R5_0 CMD RESP 95:64 */
+       unsigned int    rspreg3;        /* _RESPONSE_R6_R7_0 CMD RESP 127:96 */
+       unsigned int    bdata;          /* _BUFFER_DATA_PORT_0 */
+       unsigned int    prnsts;         /* _PRESENT_STATE_0 */
+       unsigned char   hostctl;        /* _POWER_CONTROL_HOST_0 7:00 */
+       unsigned char   pwrcon;         /* _POWER_CONTROL_HOST_0 15:8 */
+       unsigned char   blkgap;         /* _POWER_CONTROL_HOST_9 23:16 */
+       unsigned char   wakcon;         /* _POWER_CONTROL_HOST_0 31:24 */
+       unsigned short  clkcon;         /* _CLOCK_CONTROL_0 15:00 */
+       unsigned char   timeoutcon;     /* _TIMEOUT_CTRL 23:16 */
+       unsigned char   swrst;          /* _SW_RESET_ 31:24 */
+       unsigned int    norintsts;      /* _INTERRUPT_STATUS_0 */
+       unsigned int    norintstsen;    /* _INTERRUPT_STATUS_ENABLE_0 */
+       unsigned int    norintsigen;    /* _INTERRUPT_SIGNAL_ENABLE_0 */
+       unsigned short  acmd12errsts;   /* _AUTO_CMD12_ERR_STATUS_0 15:00 */
+       unsigned char   res1[2];        /* _RESERVED 31:16 */
+       unsigned int    capareg;        /* _CAPABILITIES_0 */
+       unsigned char   res2[4];        /* RESERVED, offset 44h-47h */
+       unsigned int    maxcurr;        /* _MAXIMUM_CURRENT_0 */
+       unsigned char   res3[4];        /* RESERVED, offset 4Ch-4Fh */
+       unsigned short  setacmd12err;   /* offset 50h */
+       unsigned short  setinterr;      /* offset 52h */
+       unsigned char   admaerr;        /* offset 54h */
+       unsigned char   res4[3];        /* RESERVED, offset 55h-57h */
+       unsigned long   admaaddr;       /* offset 58h-5Fh */
+       unsigned char   res5[0x9c];     /* RESERVED, offset 60h-FBh */
+       unsigned short  slotintstatus;  /* offset FCh */
+       unsigned short  hcver;          /* HOST Version */
+       unsigned char   res6[0x100];    /* RESERVED, offset 100h-1FFh */
+};
+
+#define TEGRA_MMC_HOSTCTL_DMASEL_MASK                          (3 << 3)
+#define TEGRA_MMC_HOSTCTL_DMASEL_SDMA                          (0 << 3)
+#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT                   (2 << 3)
+#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_64BIT                   (3 << 3)
+
+#define TEGRA_MMC_TRNMOD_DMA_ENABLE                            (1 << 0)
+#define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE                    (1 << 1)
+#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_WRITE               (0 << 4)
+#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ                        (1 << 4)
+#define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT                    (1 << 5)
+
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_MASK                 (3 << 0)
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE          (0 << 0)
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136           (1 << 0)
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48            (2 << 0)
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY       (3 << 0)
+
+#define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK                         (1 << 3)
+#define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK                       (1 << 4)
+#define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER     (1 << 5)
+
+#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD                       (1 << 0)
+#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT                       (1 << 1)
+
+#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE                 (1 << 0)
+#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE                 (1 << 1)
+#define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE                       (1 << 2)
+
+#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT                  8
+#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK                   (0xff << 8)
+
+#define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL                       (1 << 0)
+#define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE                  (1 << 1)
+#define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE                  (1 << 2)
+
+#define TEGRA_MMC_NORINTSTS_CMD_COMPLETE                       (1 << 0)
+#define TEGRA_MMC_NORINTSTS_XFER_COMPLETE                      (1 << 1)
+#define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT                      (1 << 3)
+#define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT                      (1 << 15)
+#define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT                                (1 << 16)
+
+#define TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE                     (1 << 0)
+#define TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE                    (1 << 1)
+#define TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT                    (1 << 3)
+#define TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY               (1 << 4)
+#define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY                        (1 << 5)
+
+#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE                    (1 << 1)
+
+struct mmc_host {
+       struct tegra_mmc *reg;
+       unsigned int version;   /* SDHCI spec. version */
+       unsigned int clock;     /* Current clock (MHz) */
+       unsigned int base;      /* Base address, SDMMC1/2/3/4 */
+       enum periph_id mmc_id;  /* Peripheral ID: PERIPH_ID_... */
+       int pwr_gpio;           /* Power GPIO */
+       int cd_gpio;            /* Change Detect GPIO */
+};
+
+#endif /* __ASSEMBLY__ */
+#endif /* __TEGRA_MMC_H_ */
index 8978beacc5d6e757183c220508d0a2018853c038..d53a93ff53ab653df5a4782fd786c119533ca4ca 100644 (file)
@@ -70,6 +70,6 @@ struct spi_tegra {
 #define SPI_STAT_CUR_BLKCNT            (1 << 15)
 
 #define SPI_TIMEOUT            1000
-#define TEGRA20_SPI_MAX_FREQ   52000000
+#define TEGRA_SPI_MAX_FREQ     52000000
 
 #endif /* _TEGRA_SPI_H_ */
index 43f7ab4efa6b1eb031390a6aacb29a9facab7dea..fdb99a73eeb82991cff4f1169a4f74a39df21e7e 100644 (file)
@@ -21,8 +21,8 @@
 
 /* Tegra20 timer functions */
 
-#ifndef _TEGRA20_TIMER_H
-#define _TEGRA20_TIMER_H
+#ifndef _TEGRA_TIMER_H
+#define _TEGRA_TIMER_H
 
 /* returns the current monotonic timer value in microseconds */
 unsigned long timer_get_us(void);
index a0a4d1d07ddc549c9e319bfb81a2d79751a456a3..93f12ea4f1914aade854f2dfbc3699925dcba0c9 100644 (file)
@@ -78,7 +78,7 @@ int board_mmc_init(bd_t *bd)
        pin_mux_mmc();
 
        /* init dev 0, SD slot, with 4-bit bus */
-       tegra20_mmc_init(0, 4, GPIO_PI6, GPIO_PH2);
+       tegra_mmc_init(0, 4, GPIO_PI6, GPIO_PH2);
 
        return 0;
 }
index cd684f29263439f52158928c52e02752aa3fa3d0..0f8f167017267218d35ba52092123046d3b59d08 100644 (file)
@@ -70,11 +70,11 @@ int board_mmc_init(bd_t *bd)
        debug("board_mmc_init: init eMMC\n");
        /* init dev 0, eMMC chip, with 4-bit bus */
        /* The board has an 8-bit bus, but 8-bit doesn't work yet */
-       tegra20_mmc_init(0, 4, -1, -1);
+       tegra_mmc_init(0, 4, -1, -1);
 
        debug("board_mmc_init: init SD slot\n");
        /* init dev 3, SD slot, with 4-bit bus */
-       tegra20_mmc_init(3, 4, GPIO_PV1, GPIO_PV5);
+       tegra_mmc_init(3, 4, GPIO_PV1, GPIO_PV5);
 
        return 0;
 }
index 5dae15b962f53eb626797c98b2a50055c0994e54..893cca8c19b202647ccbcf41db36af250af7e77c 100644 (file)
@@ -69,10 +69,10 @@ int board_mmc_init(bd_t *bd)
        pin_mux_mmc();
 
        /* init dev 0 (SDMMC4), (micro-SD slot) with 4-bit bus */
-       tegra20_mmc_init(0, 4, -1, GPIO_PP1);
+       tegra_mmc_init(0, 4, -1, GPIO_PP1);
 
        /* init dev 3 (SDMMC1), (SD slot) with 4-bit bus */
-       tegra20_mmc_init(3, 4, -1, -1);
+       tegra_mmc_init(3, 4, -1, -1);
 
        return 0;
 }
index 7ab20408e862ffc87e732f5944e1e5b02be4adf4..afe832a5295198258ff208e4576f591737129e15 100644 (file)
@@ -45,8 +45,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-const struct tegra20_sysinfo sysinfo = {
-       CONFIG_TEGRA20_BOARD_STRING
+const struct tegra_sysinfo sysinfo = {
+       CONFIG_TEGRA_BOARD_STRING
 };
 
 #ifndef CONFIG_SPL_BUILD
@@ -79,7 +79,7 @@ void pin_mux_spi(void) __attribute__((weak, alias("__pin_mux_spi")));
 static void power_det_init(void)
 {
 #if defined(CONFIG_TEGRA20)
-       struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+       struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
 
        /* turn off power detects */
        writel(0, &pmc->pmc_pwr_det_latch);
@@ -132,7 +132,7 @@ int board_init(void)
        board_usb_init(gd->fdt_blob);
 #endif
 
-#ifdef CONFIG_TEGRA20_LP0
+#ifdef CONFIG_TEGRA_LP0
        /* save Sdram params to PMC 2, 4, and 24 for WB0 */
        warmboot_save_sdram_params();
 
index 44977c78d1d301f63a5020c8eaff50bb592c0f4d..b4a811dc5f9b985ba24c046794433d259859e831 100644 (file)
@@ -73,11 +73,11 @@ int board_mmc_init(bd_t *bd)
        debug("board_mmc_init: init SD slot J26\n");
        /* init dev 0, SD slot J26, with 4-bit bus */
        /* The board has an 8-bit bus, but 8-bit doesn't work yet */
-       tegra20_mmc_init(0, 4, GPIO_PI6, GPIO_PH2);
+       tegra_mmc_init(0, 4, GPIO_PI6, GPIO_PH2);
 
        debug("board_mmc_init: init SD slot J5\n");
        /* init dev 2, SD slot J5, with 4-bit bus */
-       tegra20_mmc_init(2, 4, GPIO_PT3, GPIO_PI5);
+       tegra_mmc_init(2, 4, GPIO_PT3, GPIO_PI5);
 
        return 0;
 }
index 3298a6b3a8860a7847ced4a08979bd4b5659043e..667f60a9bb940fe27422dc1f27dd24b83fe464d7 100644 (file)
@@ -81,11 +81,11 @@ int board_mmc_init(bd_t *bd)
        debug("board_mmc_init: init eMMC\n");
        /* init dev 0, eMMC chip, with 4-bit bus */
        /* The board has an 8-bit bus, but 8-bit doesn't work yet */
-       tegra20_mmc_init(0, 4, -1, -1);
+       tegra_mmc_init(0, 4, -1, -1);
 
        debug("board_mmc_init: init SD slot\n");
        /* init dev 1, SD slot, with 4-bit bus */
-       tegra20_mmc_init(1, 4, GPIO_PI6, GPIO_PI5);
+       tegra_mmc_init(1, 4, GPIO_PI6, GPIO_PI5);
 
        return 0;
 }
index c0a114d6677e629431d166ee0763deaf32124dc0..598b2e5ce2518e646236b840629cb2d847df8720 100644 (file)
@@ -81,10 +81,10 @@ int board_mmc_init(bd_t *bd)
        pin_mux_mmc();
 
        /* init dev 0 (SDMMC4), (J29 "HSMMC") with 8-bit bus */
-       tegra20_mmc_init(0, 8, -1, -1);
+       tegra_mmc_init(0, 8, -1, -1);
 
        /* init dev 1 (SDMMC3), (J40 "SDIO3") with 8-bit bus */
-       tegra20_mmc_init(1, 8, -1, -1);
+       tegra_mmc_init(1, 8, -1, -1);
 
        return 0;
 }
index 8cfcf8283b3d03772dc5ce8298e4112bcf589310..747f4cf921213ffbdbbfe913de960b7f9d5319f2 100644 (file)
 #include <asm/gpio.h>
 
 enum {
-       TEGRA20_CMD_INFO,
-       TEGRA20_CMD_PORT,
-       TEGRA20_CMD_OUTPUT,
-       TEGRA20_CMD_INPUT,
+       TEGRA_CMD_INFO,
+       TEGRA_CMD_PORT,
+       TEGRA_CMD_OUTPUT,
+       TEGRA_CMD_INPUT,
 };
 
 static struct gpio_names {
index b4eb49127eb1374b905f4011ffa87826b184a188..e3be14e3cf3156a349bbf6abd03c520cd9b1d3aa 100644 (file)
@@ -262,7 +262,7 @@ exit:
        return error;
 }
 
-static int tegra20_i2c_write_data(u32 addr, u8 *data, u32 len)
+static int tegra_i2c_write_data(u32 addr, u8 *data, u32 len)
 {
        int error;
        struct i2c_trans_info trans_info;
@@ -275,12 +275,12 @@ static int tegra20_i2c_write_data(u32 addr, u8 *data, u32 len)
 
        error = send_recv_packets(&i2c_controllers[i2c_bus_num], &trans_info);
        if (error)
-               debug("tegra20_i2c_write_data: Error (%d) !!!\n", error);
+               debug("tegra_i2c_write_data: Error (%d) !!!\n", error);
 
        return error;
 }
 
-static int tegra20_i2c_read_data(u32 addr, u8 *data, u32 len)
+static int tegra_i2c_read_data(u32 addr, u8 *data, u32 len)
 {
        int error;
        struct i2c_trans_info trans_info;
@@ -293,7 +293,7 @@ static int tegra20_i2c_read_data(u32 addr, u8 *data, u32 len)
 
        error = send_recv_packets(&i2c_controllers[i2c_bus_num], &trans_info);
        if (error)
-               debug("tegra20_i2c_read_data: Error (%d) !!!\n", error);
+               debug("tegra_i2c_read_data: Error (%d) !!!\n", error);
 
        return error;
 }
@@ -438,7 +438,7 @@ int i2c_write_data(uchar chip, uchar *buffer, int len)
        debug("\n");
 
        /* Shift 7-bit address over for lower-level i2c functions */
-       rc = tegra20_i2c_write_data(chip << 1, buffer, len);
+       rc = tegra_i2c_write_data(chip << 1, buffer, len);
        if (rc)
                debug("i2c_write_data(): rc=%d\n", rc);
 
@@ -452,7 +452,7 @@ int i2c_read_data(uchar chip, uchar *buffer, int len)
 
        debug("inside i2c_read_data():\n");
        /* Shift 7-bit address over for lower-level i2c functions */
-       rc = tegra20_i2c_read_data(chip << 1, buffer, len);
+       rc = tegra_i2c_read_data(chip << 1, buffer, len);
        if (rc) {
                debug("i2c_read_data(): rc=%d\n", rc);
                return rc;
index 68c6a16bcc2a099485d7e83fcf0d21788c79a00d..0805e8667877853add06bfc628673826c1dbf146 100644 (file)
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB    := $(obj)libinput.o
 
 COBJS-$(CONFIG_I8042_KBD) += i8042.o
-COBJS-$(CONFIG_TEGRA20_KEYBOARD) += tegra-kbc.o
+COBJS-$(CONFIG_TEGRA_KEYBOARD) += tegra-kbc.o
 ifdef CONFIG_PS2KBD
 COBJS-y += keyboard.o pc_keyb.o
 COBJS-$(CONFIG_PS2MULT) += ps2mult.o ps2ser.o
index ddfa7279c2235ada4ceb1b8404dcaed5181fb1e8..ca8fad86572d9eaf3077912bbceae6d82a334907 100644 (file)
@@ -25,7 +25,7 @@
 #include <asm/io.h>
 #include <asm/arch/clk_rst.h>
 #include <asm/arch/clock.h>
-#include "tegra_mmc.h"
+#include <asm/arch/tegra_mmc.h>
 
 /* support 4 mmc hosts */
 struct mmc mmc_dev[4];
@@ -39,31 +39,31 @@ struct mmc_host mmc_host[4];
  * @param host         Structure to fill in (base, reg, mmc_id)
  * @param dev_index    Device index (0-3)
  */
-static void tegra20_get_setup(struct mmc_host *host, int dev_index)
+static void tegra_get_setup(struct mmc_host *host, int dev_index)
 {
-       debug("tegra20_get_base_mmc: dev_index = %d\n", dev_index);
+       debug("tegra_get_setup: dev_index = %d\n", dev_index);
 
        switch (dev_index) {
        case 1:
-               host->base = TEGRA20_SDMMC3_BASE;
+               host->base = TEGRA_SDMMC3_BASE;
                host->mmc_id = PERIPH_ID_SDMMC3;
                break;
        case 2:
-               host->base = TEGRA20_SDMMC2_BASE;
+               host->base = TEGRA_SDMMC2_BASE;
                host->mmc_id = PERIPH_ID_SDMMC2;
                break;
        case 3:
-               host->base = TEGRA20_SDMMC1_BASE;
+               host->base = TEGRA_SDMMC1_BASE;
                host->mmc_id = PERIPH_ID_SDMMC1;
                break;
        case 0:
        default:
-               host->base = TEGRA20_SDMMC4_BASE;
+               host->base = TEGRA_SDMMC4_BASE;
                host->mmc_id = PERIPH_ID_SDMMC4;
                break;
        }
 
-       host->reg = (struct tegra20_mmc *)host->base;
+       host->reg = (struct tegra_mmc *)host->base;
 }
 
 static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data)
@@ -345,7 +345,7 @@ static void mmc_change_clock(struct mmc_host *host, uint clock)
        debug(" mmc_change_clock called\n");
 
        /*
-        * Change Tegra20 SDMMCx clock divisor here. Source is 216MHz,
+        * Change Tegra SDMMCx clock divisor here. Source is 216MHz,
         * PLLP_OUT0
         */
        if (clock == 0)
@@ -494,11 +494,11 @@ static int mmc_core_init(struct mmc *mmc)
        return 0;
 }
 
-int tegra20_mmc_getcd(struct mmc *mmc)
+int tegra_mmc_getcd(struct mmc *mmc)
 {
        struct mmc_host *host = (struct mmc_host *)mmc->priv;
 
-       debug("tegra20_mmc_getcd called\n");
+       debug("tegra_mmc_getcd called\n");
 
        if (host->cd_gpio >= 0)
                return !gpio_get_value(host->cd_gpio);
@@ -506,13 +506,13 @@ int tegra20_mmc_getcd(struct mmc *mmc)
        return 1;
 }
 
-int tegra20_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
+int tegra_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
 {
        struct mmc_host *host;
        char gpusage[12]; /* "SD/MMCn PWR" or "SD/MMCn CD" */
        struct mmc *mmc;
 
-       debug(" tegra20_mmc_init: index %d, bus width %d "
+       debug(" tegra_mmc_init: index %d, bus width %d "
                "pwr_gpio %d cd_gpio %d\n",
                dev_index, bus_width, pwr_gpio, cd_gpio);
 
@@ -521,7 +521,7 @@ int tegra20_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
        host->clock = 0;
        host->pwr_gpio = pwr_gpio;
        host->cd_gpio = cd_gpio;
-       tegra20_get_setup(host, dev_index);
+       tegra_get_setup(host, dev_index);
 
        clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000);
 
@@ -539,12 +539,12 @@ int tegra20_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
 
        mmc = &mmc_dev[dev_index];
 
-       sprintf(mmc->name, "Tegra20 SD/MMC");
+       sprintf(mmc->name, "Tegra SD/MMC");
        mmc->priv = host;
        mmc->send_cmd = mmc_send_cmd;
        mmc->set_ios = mmc_set_ios;
        mmc->init = mmc_core_init;
-       mmc->getcd = tegra20_mmc_getcd;
+       mmc->getcd = tegra_mmc_getcd;
 
        mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
        if (bus_width == 8)
@@ -559,7 +559,7 @@ int tegra20_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
         * max freq is highest HS eMMC clock as per the SD/MMC spec
         *  (actually 52MHz)
         * Both of these are the closest equivalents w/216MHz source
-        *  clock and Tegra20 SDMMC divisors.
+        *  clock and Tegra SDMMC divisors.
         */
        mmc->f_min = 375000;
        mmc->f_max = 48000000;
diff --git a/drivers/mmc/tegra_mmc.h b/drivers/mmc/tegra_mmc.h
deleted file mode 100644 (file)
index b1f2564..0000000
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * (C) Copyright 2009 SAMSUNG Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- * Portions Copyright (C) 2011-2012 NVIDIA Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-
-#ifndef __TEGRA_MMC_H_
-#define __TEGRA_MMC_H_
-
-#define TEGRA20_SDMMC1_BASE    0xC8000000
-#define TEGRA20_SDMMC2_BASE    0xC8000200
-#define TEGRA20_SDMMC3_BASE    0xC8000400
-#define TEGRA20_SDMMC4_BASE    0xC8000600
-
-#ifndef __ASSEMBLY__
-struct tegra20_mmc {
-       unsigned int    sysad;          /* _SYSTEM_ADDRESS_0 */
-       unsigned short  blksize;        /* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */
-       unsigned short  blkcnt;         /* _BLOCK_SIZE_BLOCK_COUNT_0 31:16 */
-       unsigned int    argument;       /* _ARGUMENT_0 */
-       unsigned short  trnmod;         /* _CMD_XFER_MODE_0 15:00 xfer mode */
-       unsigned short  cmdreg;         /* _CMD_XFER_MODE_0 31:16 cmd reg */
-       unsigned int    rspreg0;        /* _RESPONSE_R0_R1_0 CMD RESP 31:00 */
-       unsigned int    rspreg1;        /* _RESPONSE_R2_R3_0 CMD RESP 63:32 */
-       unsigned int    rspreg2;        /* _RESPONSE_R4_R5_0 CMD RESP 95:64 */
-       unsigned int    rspreg3;        /* _RESPONSE_R6_R7_0 CMD RESP 127:96 */
-       unsigned int    bdata;          /* _BUFFER_DATA_PORT_0 */
-       unsigned int    prnsts;         /* _PRESENT_STATE_0 */
-       unsigned char   hostctl;        /* _POWER_CONTROL_HOST_0 7:00 */
-       unsigned char   pwrcon;         /* _POWER_CONTROL_HOST_0 15:8 */
-       unsigned char   blkgap;         /* _POWER_CONTROL_HOST_9 23:16 */
-       unsigned char   wakcon;         /* _POWER_CONTROL_HOST_0 31:24 */
-       unsigned short  clkcon;         /* _CLOCK_CONTROL_0 15:00 */
-       unsigned char   timeoutcon;     /* _TIMEOUT_CTRL 23:16 */
-       unsigned char   swrst;          /* _SW_RESET_ 31:24 */
-       unsigned int    norintsts;      /* _INTERRUPT_STATUS_0 */
-       unsigned int    norintstsen;    /* _INTERRUPT_STATUS_ENABLE_0 */
-       unsigned int    norintsigen;    /* _INTERRUPT_SIGNAL_ENABLE_0 */
-       unsigned short  acmd12errsts;   /* _AUTO_CMD12_ERR_STATUS_0 15:00 */
-       unsigned char   res1[2];        /* _RESERVED 31:16 */
-       unsigned int    capareg;        /* _CAPABILITIES_0 */
-       unsigned char   res2[4];        /* RESERVED, offset 44h-47h */
-       unsigned int    maxcurr;        /* _MAXIMUM_CURRENT_0 */
-       unsigned char   res3[4];        /* RESERVED, offset 4Ch-4Fh */
-       unsigned short  setacmd12err;   /* offset 50h */
-       unsigned short  setinterr;      /* offset 52h */
-       unsigned char   admaerr;        /* offset 54h */
-       unsigned char   res4[3];        /* RESERVED, offset 55h-57h */
-       unsigned long   admaaddr;       /* offset 58h-5Fh */
-       unsigned char   res5[0x9c];     /* RESERVED, offset 60h-FBh */
-       unsigned short  slotintstatus;  /* offset FCh */
-       unsigned short  hcver;          /* HOST Version */
-       unsigned char   res6[0x100];    /* RESERVED, offset 100h-1FFh */
-};
-
-#define TEGRA_MMC_HOSTCTL_DMASEL_MASK                          (3 << 3)
-#define TEGRA_MMC_HOSTCTL_DMASEL_SDMA                          (0 << 3)
-#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT                   (2 << 3)
-#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_64BIT                   (3 << 3)
-
-#define TEGRA_MMC_TRNMOD_DMA_ENABLE                            (1 << 0)
-#define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE                    (1 << 1)
-#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_WRITE               (0 << 4)
-#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ                        (1 << 4)
-#define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT                    (1 << 5)
-
-#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_MASK                 (3 << 0)
-#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE          (0 << 0)
-#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136           (1 << 0)
-#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48            (2 << 0)
-#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY       (3 << 0)
-
-#define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK                         (1 << 3)
-#define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK                       (1 << 4)
-#define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER     (1 << 5)
-
-#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD                       (1 << 0)
-#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT                       (1 << 1)
-
-#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE                 (1 << 0)
-#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE                 (1 << 1)
-#define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE                       (1 << 2)
-
-#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT                  8
-#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK                   (0xff << 8)
-
-#define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL                       (1 << 0)
-#define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE                  (1 << 1)
-#define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE                  (1 << 2)
-
-#define TEGRA_MMC_NORINTSTS_CMD_COMPLETE                       (1 << 0)
-#define TEGRA_MMC_NORINTSTS_XFER_COMPLETE                      (1 << 1)
-#define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT                      (1 << 3)
-#define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT                      (1 << 15)
-#define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT                                (1 << 16)
-
-#define TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE                     (1 << 0)
-#define TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE                    (1 << 1)
-#define TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT                    (1 << 3)
-#define TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY               (1 << 4)
-#define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY                        (1 << 5)
-
-#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE                    (1 << 1)
-
-struct mmc_host {
-       struct tegra20_mmc *reg;
-       unsigned int version;   /* SDHCI spec. version */
-       unsigned int clock;     /* Current clock (MHz) */
-       unsigned int base;      /* Base address, SDMMC1/2/3/4 */
-       enum periph_id mmc_id;  /* Peripheral ID: PERIPH_ID_... */
-       int pwr_gpio;           /* Power GPIO */
-       int cd_gpio;            /* Change Detect GPIO */
-};
-
-#endif /* __ASSEMBLY__ */
-#endif /* __TEGRA_MMC_H_ */
index 2355e022b0245f9d5959edb0a597bb7ae7181daf..18b00b2cae973d8160af54517c5806bedf378135 100644 (file)
@@ -72,9 +72,9 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
                return NULL;
        }
 
-       if (max_hz > TEGRA20_SPI_MAX_FREQ) {
+       if (max_hz > TEGRA_SPI_MAX_FREQ) {
                printf("SPI error: unsupported frequency %d Hz. Max frequency"
-                       " is %d Hz\n", max_hz, TEGRA20_SPI_MAX_FREQ);
+                       " is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ);
                return NULL;
        }
 
@@ -86,7 +86,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
        spi->slave.bus = bus;
        spi->slave.cs = cs;
        spi->freq = max_hz;
-       spi->regs = (struct spi_tegra *)TEGRA20_SPI_BASE;
+       spi->regs = (struct spi_tegra *)NV_PA_SPI_BASE;
        spi->mode = mode;
 
        return &spi->slave;
index 69857dd5810e1ffc5799baf6739df9e28385baac..e407ff4ca5384b149036641bf8f8bbfdd2bf4a76 100644 (file)
 
 /* High-level configuration options */
 #define V_PROMPT               "Tegra20 (Harmony) # "
-#define CONFIG_TEGRA20_BOARD_STRING    "NVIDIA Harmony"
+#define CONFIG_TEGRA_BOARD_STRING      "NVIDIA Harmony"
 
 /* Board-specific serial config */
 #define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA20_ENABLE_UARTD
+#define CONFIG_TEGRA_ENABLE_UARTD
 
 /* UARTD: keyboard satellite board UART, default */
 #define CONFIG_SYS_NS16550_COM1                NV_PA_APB_UARTD_BASE
-#ifdef CONFIG_TEGRA20_ENABLE_UARTA
+#ifdef CONFIG_TEGRA_ENABLE_UARTA
 /* UARTA: debug board UART */
 #define CONFIG_SYS_NS16550_COM2                NV_PA_APB_UARTA_BASE
 #endif
@@ -66,7 +66,7 @@
 #define CONFIG_CMD_NAND
 #define CONFIG_TEGRA_NAND
 #define CONFIG_SYS_MAX_NAND_DEVICE     1
-#define CONFIG_SYS_NAND_BASE   TEGRA20_NAND_BASE
+#define CONFIG_SYS_NAND_BASE   NV_PA_NAND_BASE
 
 /* Environment in NAND (which is 512M), aligned to start of last sector */
 #define CONFIG_ENV_IS_IN_NAND
@@ -87,6 +87,6 @@
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_DHCP
 
-#include "tegra20-common-post.h"
+#include "tegra-common-post.h"
 
 #endif /* __CONFIG_H */
index bce03a49fab52072a15f745cd4f3d03ac6ecbdd7..678b36b6cffc2844681dd09db7d2ded48e7ded84 100644 (file)
 
 /* High-level configuration options */
 #define V_PROMPT                       "Tegra20 (Medcom) # "
-#define CONFIG_TEGRA20_BOARD_STRING    "Avionic Design Medcom"
+#define CONFIG_TEGRA_BOARD_STRING      "Avionic Design Medcom"
 
 /* Board-specific serial config */
 #define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA20_ENABLE_UARTD    /* UARTD: debug UART */
+#define CONFIG_TEGRA_ENABLE_UARTD      /* UARTD: debug UART */
 #define CONFIG_SYS_NS16550_COM1                NV_PA_APB_UARTD_BASE
 
 #define CONFIG_BOARD_EARLY_INIT_F
@@ -78,6 +78,6 @@
        "ext2load mmc 0 0x17000000 /boot/uImage;"       \
        "bootm"
 
-#include "tegra20-common-post.h"
+#include "tegra-common-post.h"
 
 #endif /* __CONFIG_H */
index 99b8753c586a9f65a76a297880d9e1836becf326..24cda4839ee6ed99e74c3c5a6835e769bdee974d 100644 (file)
 
 /* High-level configuration options */
 #define V_PROMPT               "Tegra20 (Paz00) MOD # "
-#define CONFIG_TEGRA20_BOARD_STRING    "Compal Paz00"
+#define CONFIG_TEGRA_BOARD_STRING      "Compal Paz00"
 
 /* Board-specific serial config */
 #define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA20_ENABLE_UARTA
+#define CONFIG_TEGRA_ENABLE_UARTA
 #define CONFIG_SYS_NS16550_COM1                NV_PA_APB_UARTA_BASE
 
 #define CONFIG_MACH_TYPE               MACH_TYPE_PAZ00
@@ -69,6 +69,6 @@
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_DHCP
 
-#include "tegra20-common-post.h"
+#include "tegra-common-post.h"
 
 #endif /* __CONFIG_H */
index 42291d4e28be513b35d0f62afaa35753d0a6760a..65b42edc270b934b207b6764dbd741675b6508a3 100644 (file)
 
 /* High-level configuration options */
 #define V_PROMPT                       "Tegra20 (Plutux) # "
-#define CONFIG_TEGRA20_BOARD_STRING    "Avionic Design Plutux"
+#define CONFIG_TEGRA_BOARD_STRING      "Avionic Design Plutux"
 
 /* Board-specific serial config */
 #define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA20_ENABLE_UARTD    /* UARTD: debug UART */
+#define CONFIG_TEGRA_ENABLE_UARTD      /* UARTD: debug UART */
 #define CONFIG_SYS_NS16550_COM1                NV_PA_APB_UARTD_BASE
 
 #define CONFIG_BOARD_EARLY_INIT_F
@@ -78,6 +78,6 @@
        "ext2load mmc 0 0x17000000 /boot/uImage;"       \
        "bootm"
 
-#include "tegra20-common-post.h"
+#include "tegra-common-post.h"
 
 #endif /* __CONFIG_H */
index 69965021edf1f97aa0c75c522d396c360974f8b6..de19e38deb4ae7ad800c2007cc8d73f140dfa28e 100644 (file)
@@ -27,7 +27,7 @@
 #include <asm/sizes.h>
 
 /* LP0 suspend / resume */
-#define CONFIG_TEGRA20_LP0
+#define CONFIG_TEGRA_LP0
 #define CONFIG_AES
 #define CONFIG_TEGRA_PMU
 #define CONFIG_TPS6586X_POWER
 
 /* High-level configuration options */
 #define V_PROMPT               "Tegra20 (SeaBoard) # "
-#define CONFIG_TEGRA20_BOARD_STRING    "NVIDIA Seaboard"
+#define CONFIG_TEGRA_BOARD_STRING      "NVIDIA Seaboard"
 
 /* Board-specific serial config */
 #define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA20_ENABLE_UARTD
+#define CONFIG_TEGRA_ENABLE_UARTD
 #define CONFIG_SYS_NS16550_COM1                NV_PA_APB_UARTD_BASE
 
 /* On Seaboard: GPIO_PI3 = Port I = 8, bit = 3 */
 #define CONFIG_CMD_DHCP
 
 /* Enable keyboard */
-#define CONFIG_TEGRA20_KEYBOARD
+#define CONFIG_TEGRA_KEYBOARD
 #define CONFIG_KEYBOARD
 
-#undef TEGRA20_DEVICE_SETTINGS
-#define TEGRA20_DEVICE_SETTINGS        "stdin=serial,tegra-kbc\0" \
-                                       "stdout=serial\0" \
-                                       "stderr=serial\0"
+#undef TEGRA_DEVICE_SETTINGS
+#define TEGRA_DEVICE_SETTINGS  "stdin=serial,tegra-kbc\0" \
+                               "stdout=serial\0" \
+                               "stderr=serial\0"
 
-#include "tegra20-common-post.h"
+#include "tegra-common-post.h"
 
 /* NAND support */
 #define CONFIG_CMD_NAND
 #define CONFIG_SYS_MAX_NAND_DEVICE     1
 
 /* Somewhat oddly, the NAND base address must be a config option */
-#define CONFIG_SYS_NAND_BASE   TEGRA20_NAND_BASE
+#define CONFIG_SYS_NAND_BASE   NV_PA_NAND_BASE
 #endif /* __CONFIG_H */
index 9d14d15f69328443e1fde22db7a9b596f5e8ee37..d5da3c7a88c532cf5b40e983f41b1c1f1eb22977 100644 (file)
 
 /* High-level configuration options */
 #define V_PROMPT                       "Tegra20 (TEC) # "
-#define CONFIG_TEGRA20_BOARD_STRING    "Avionic Design Tamonten Evaluation Carrier"
+#define CONFIG_TEGRA_BOARD_STRING      "Avionic Design Tamonten Evaluation Carrier"
 #define CONFIG_SYS_BOARD_ODMDATA       0x2b0d8011
 
 /* Board-specific serial config */
 #define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA20_ENABLE_UARTD    /* UARTD: debug UART */
+#define CONFIG_TEGRA_ENABLE_UARTD      /* UARTD: debug UART */
 #define CONFIG_SYS_NS16550_COM1                NV_PA_APB_UARTD_BASE
 
 #define CONFIG_BOARD_EARLY_INIT_F
@@ -55,7 +55,7 @@
 #define CONFIG_CMD_NAND
 #define CONFIG_TEGRA_NAND
 #define CONFIG_SYS_MAX_NAND_DEVICE     1
-#define CONFIG_SYS_NAND_BASE           TEGRA20_NAND_BASE
+#define CONFIG_SYS_NAND_BASE           NV_PA_NAND_BASE
 
 /* Environment in NAND, aligned to start of last sector */
 #define CONFIG_ENV_IS_IN_NAND
@@ -87,6 +87,6 @@
        "ext2load mmc 0 0x17000000 /boot/uImage;"       \
        "bootm"
 
-#include "tegra20-common-post.h"
+#include "tegra-common-post.h"
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h
new file mode 100644 (file)
index 0000000..168b64b
--- /dev/null
@@ -0,0 +1,214 @@
+/*
+ * (C) Copyright 2010-2012
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __TEGRA_COMMON_POST_H
+#define __TEGRA_COMMON_POST_H
+
+#ifdef CONFIG_BOOTCOMMAND
+
+#define BOOTCMDS_COMMON ""
+
+#else
+
+#ifdef CONFIG_CMD_EXT2
+#define BOOT_FSTYPE_EXT2 "ext2 "
+#else
+#define BOOT_FSTYPE_EXT2 ""
+#endif
+
+#ifdef CONFIG_CMD_FAT
+#define BOOT_FSTYPE_FAT "fat"
+#else
+#define BOOT_FSTYPE_FAT ""
+#endif
+
+#ifdef CONFIG_CMD_MMC
+#define BOOTCMDS_MMC \
+       "mmc_boot=" \
+               "setenv devtype mmc; " \
+               "if mmc dev ${devnum}; then " \
+                       "run scan_boot; " \
+               "fi\0" \
+       "bootcmd_mmc0=setenv devnum 0; run mmc_boot;\0" \
+       "bootcmd_mmc1=setenv devnum 1; run mmc_boot;\0"
+#define BOOT_TARGETS_MMC "mmc1 mmc0"
+#else
+#define BOOTCMDS_MMC ""
+#define BOOT_TARGETS_MMC ""
+#endif
+
+#ifdef CONFIG_CMD_USB
+#define BOOTCMD_INIT_USB "run usb_init; "
+#define BOOTCMDS_USB \
+       "usb_init=" \
+               "if ${usb_need_init}; then " \
+                       "set usb_need_init false; " \
+                       "usb start 0; " \
+               "fi\0" \
+       \
+       "usb_boot=" \
+               "setenv devtype usb; " \
+               BOOTCMD_INIT_USB \
+               "if usb dev ${devnum}; then " \
+                       "run scan_boot; " \
+               "fi\0" \
+       \
+       "bootcmd_usb0=setenv devnum 0; run usb_boot;\0"
+#define BOOT_TARGETS_USB "usb0"
+#else
+#define BOOTCMD_INIT_USB ""
+#define BOOTCMDS_USB ""
+#define BOOT_TARGETS_USB ""
+#endif
+
+#ifdef CONFIG_CMD_DHCP
+#define BOOTCMDS_DHCP \
+       "bootcmd_dhcp=" \
+               BOOTCMD_INIT_USB \
+               "if dhcp ${scriptaddr} boot.scr.uimg; then "\
+                       "source ${scriptaddr}; " \
+               "fi\0"
+#define BOOT_TARGETS_DHCP "dhcp"
+#else
+#define BOOTCMDS_DHCP ""
+#define BOOT_TARGETS_DHCP ""
+#endif
+
+#define BOOTCMDS_COMMON \
+       "scriptaddr=0x400000\0" \
+       \
+       "rootpart=1\0" \
+       \
+       "script_boot="                                                    \
+               "if ${fs}load ${devtype} ${devnum}:${rootpart} "          \
+                               "${scriptaddr} ${prefix}${script}; then " \
+                       "echo ${script} found! Executing ...;"            \
+                       "source ${scriptaddr};"                           \
+               "fi;\0"                                                   \
+       \
+       "scan_boot="                                                      \
+               "echo Scanning ${devtype} ${devnum}...; "                 \
+               "for fs in ${boot_fstypes}; do "                          \
+                       "for prefix in ${boot_prefixes}; do "             \
+                               "for script in ${boot_scripts}; do "      \
+                                       "run script_boot; "               \
+                               "done; "                                  \
+                       "done; "                                          \
+               "done;\0"                                                 \
+       \
+       "boot_targets=" \
+               BOOT_TARGETS_MMC " " \
+               BOOT_TARGETS_USB " " \
+               BOOT_TARGETS_DHCP " " \
+               "\0" \
+       \
+       "boot_fstypes=" \
+               BOOT_FSTYPE_EXT2 " " \
+               BOOT_FSTYPE_FAT " " \
+               "\0" \
+       \
+       "boot_prefixes=/ /boot/\0" \
+       \
+       "boot_scripts=boot.scr.uimg boot.scr\0" \
+       \
+       BOOTCMDS_MMC \
+       BOOTCMDS_USB \
+       BOOTCMDS_DHCP
+
+#define CONFIG_BOOTCOMMAND \
+       "for target in ${boot_targets}; do run bootcmd_${target}; done"
+
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+       TEGRA_DEVICE_SETTINGS \
+       "fdt_load=0x01000000\0" \
+       "fdt_high=01100000\0" \
+       BOOTCMDS_COMMON
+
+/* overrides for SPL build here */
+#ifdef CONFIG_SPL_BUILD
+
+/* remove devicetree support */
+#ifdef CONFIG_OF_CONTROL
+#undef CONFIG_OF_CONTROL
+#endif
+
+/* remove SERIAL_MULTI */
+#ifdef CONFIG_SERIAL_MULTI
+#undef CONFIG_SERIAL_MULTI
+#endif
+
+/* remove I2C support */
+#ifdef CONFIG_TEGRA_I2C
+#undef CONFIG_TEGRA_I2C
+#endif
+#ifdef CONFIG_CMD_I2C
+#undef CONFIG_CMD_I2C
+#endif
+
+/* remove MMC support */
+#ifdef CONFIG_MMC
+#undef CONFIG_MMC
+#endif
+#ifdef CONFIG_GENERIC_MMC
+#undef CONFIG_GENERIC_MMC
+#endif
+#ifdef CONFIG_TEGRA_MMC
+#undef CONFIG_TEGRA_MMC
+#endif
+#ifdef CONFIG_CMD_MMC
+#undef CONFIG_CMD_MMC
+#endif
+
+/* remove partitions/filesystems */
+#ifdef CONFIG_DOS_PARTITION
+#undef CONFIG_DOS_PARTITION
+#endif
+#ifdef CONFIG_EFI_PARTITION
+#undef CONFIG_EFI_PARTITION
+#endif
+#ifdef CONFIG_CMD_EXT2
+#undef CONFIG_CMD_EXT2
+#endif
+#ifdef CONFIG_CMD_FAT
+#undef CONFIG_CMD_FAT
+#endif
+
+/* remove USB */
+#ifdef CONFIG_USB_EHCI
+#undef CONFIG_USB_EHCI
+#endif
+#ifdef CONFIG_USB_EHCI_TEGRA
+#undef CONFIG_USB_EHCI_TEGRA
+#endif
+#ifdef CONFIG_USB_STORAGE
+#undef CONFIG_USB_STORAGE
+#endif
+#ifdef CONFIG_CMD_USB
+#undef CONFIG_CMD_USB
+#endif
+
+#endif /* CONFIG_SPL_BUILD */
+
+#endif /* __TEGRA_COMMON_POST_H */
diff --git a/include/configs/tegra20-common-post.h b/include/configs/tegra20-common-post.h
deleted file mode 100644 (file)
index 42f270f..0000000
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * (C) Copyright 2010-2012
- * NVIDIA Corporation <www.nvidia.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __TEGRA20_COMMON_POST_H
-#define __TEGRA20_COMMON_POST_H
-
-#ifdef CONFIG_BOOTCOMMAND
-
-#define BOOTCMDS_COMMON ""
-
-#else
-
-#ifdef CONFIG_CMD_EXT2
-#define BOOT_FSTYPE_EXT2 "ext2 "
-#else
-#define BOOT_FSTYPE_EXT2 ""
-#endif
-
-#ifdef CONFIG_CMD_FAT
-#define BOOT_FSTYPE_FAT "fat"
-#else
-#define BOOT_FSTYPE_FAT ""
-#endif
-
-#ifdef CONFIG_CMD_MMC
-#define BOOTCMDS_MMC \
-       "mmc_boot=" \
-               "setenv devtype mmc; " \
-               "if mmc dev ${devnum}; then " \
-                       "run scan_boot; " \
-               "fi\0" \
-       "bootcmd_mmc0=setenv devnum 0; run mmc_boot;\0" \
-       "bootcmd_mmc1=setenv devnum 1; run mmc_boot;\0"
-#define BOOT_TARGETS_MMC "mmc1 mmc0"
-#else
-#define BOOTCMDS_MMC ""
-#define BOOT_TARGETS_MMC ""
-#endif
-
-#ifdef CONFIG_CMD_USB
-#define BOOTCMD_INIT_USB "run usb_init; "
-#define BOOTCMDS_USB \
-       "usb_init=" \
-               "if ${usb_need_init}; then " \
-                       "set usb_need_init false; " \
-                       "usb start 0; " \
-               "fi\0" \
-       \
-       "usb_boot=" \
-               "setenv devtype usb; " \
-               BOOTCMD_INIT_USB \
-               "if usb dev ${devnum}; then " \
-                       "run scan_boot; " \
-               "fi\0" \
-       \
-       "bootcmd_usb0=setenv devnum 0; run usb_boot;\0"
-#define BOOT_TARGETS_USB "usb0"
-#else
-#define BOOTCMD_INIT_USB ""
-#define BOOTCMDS_USB ""
-#define BOOT_TARGETS_USB ""
-#endif
-
-#ifdef CONFIG_CMD_DHCP
-#define BOOTCMDS_DHCP \
-       "bootcmd_dhcp=" \
-               BOOTCMD_INIT_USB \
-               "if dhcp ${scriptaddr} boot.scr.uimg; then "\
-                       "source ${scriptaddr}; " \
-               "fi\0"
-#define BOOT_TARGETS_DHCP "dhcp"
-#else
-#define BOOTCMDS_DHCP ""
-#define BOOT_TARGETS_DHCP ""
-#endif
-
-#define BOOTCMDS_COMMON \
-       "scriptaddr=0x400000\0" \
-       \
-       "rootpart=1\0" \
-       \
-       "script_boot="                                                    \
-               "if ${fs}load ${devtype} ${devnum}:${rootpart} "          \
-                               "${scriptaddr} ${prefix}${script}; then " \
-                       "echo ${script} found! Executing ...;"            \
-                       "source ${scriptaddr};"                           \
-               "fi;\0"                                                   \
-       \
-       "scan_boot="                                                      \
-               "echo Scanning ${devtype} ${devnum}...; "                 \
-               "for fs in ${boot_fstypes}; do "                          \
-                       "for prefix in ${boot_prefixes}; do "             \
-                               "for script in ${boot_scripts}; do "      \
-                                       "run script_boot; "               \
-                               "done; "                                  \
-                       "done; "                                          \
-               "done;\0"                                                 \
-       \
-       "boot_targets=" \
-               BOOT_TARGETS_MMC " " \
-               BOOT_TARGETS_USB " " \
-               BOOT_TARGETS_DHCP " " \
-               "\0" \
-       \
-       "boot_fstypes=" \
-               BOOT_FSTYPE_EXT2 " " \
-               BOOT_FSTYPE_FAT " " \
-               "\0" \
-       \
-       "boot_prefixes=/ /boot/\0" \
-       \
-       "boot_scripts=boot.scr.uimg boot.scr\0" \
-       \
-       BOOTCMDS_MMC \
-       BOOTCMDS_USB \
-       BOOTCMDS_DHCP
-
-#define CONFIG_BOOTCOMMAND \
-       "for target in ${boot_targets}; do run bootcmd_${target}; done"
-
-#endif
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-       TEGRA20_DEVICE_SETTINGS \
-       "fdt_load=0x01000000\0" \
-       "fdt_high=01100000\0" \
-       BOOTCMDS_COMMON
-
-/* overrides for SPL build here */
-#ifdef CONFIG_SPL_BUILD
-
-/* remove devicetree support */
-#ifdef CONFIG_OF_CONTROL
-#undef CONFIG_OF_CONTROL
-#endif
-
-/* remove SERIAL_MULTI */
-#ifdef CONFIG_SERIAL_MULTI
-#undef CONFIG_SERIAL_MULTI
-#endif
-
-/* remove I2C support */
-#ifdef CONFIG_TEGRA_I2C
-#undef CONFIG_TEGRA_I2C
-#endif
-#ifdef CONFIG_CMD_I2C
-#undef CONFIG_CMD_I2C
-#endif
-
-/* remove MMC support */
-#ifdef CONFIG_MMC
-#undef CONFIG_MMC
-#endif
-#ifdef CONFIG_GENERIC_MMC
-#undef CONFIG_GENERIC_MMC
-#endif
-#ifdef CONFIG_TEGRA20_MMC
-#undef CONFIG_TEGRA20_MMC
-#endif
-#ifdef CONFIG_CMD_MMC
-#undef CONFIG_CMD_MMC
-#endif
-
-/* remove partitions/filesystems */
-#ifdef CONFIG_DOS_PARTITION
-#undef CONFIG_DOS_PARTITION
-#endif
-#ifdef CONFIG_EFI_PARTITION
-#undef CONFIG_EFI_PARTITION
-#endif
-#ifdef CONFIG_CMD_EXT2
-#undef CONFIG_CMD_EXT2
-#endif
-#ifdef CONFIG_CMD_FAT
-#undef CONFIG_CMD_FAT
-#endif
-
-/* remove USB */
-#ifdef CONFIG_USB_EHCI
-#undef CONFIG_USB_EHCI
-#endif
-#ifdef CONFIG_USB_EHCI_TEGRA
-#undef CONFIG_USB_EHCI_TEGRA
-#endif
-#ifdef CONFIG_USB_STORAGE
-#undef CONFIG_USB_STORAGE
-#endif
-#ifdef CONFIG_CMD_USB
-#undef CONFIG_CMD_USB
-#endif
-
-#endif /* CONFIG_SPL_BUILD */
-
-#endif /* __TEGRA20_COMMON_POST_H */
index 02cf0cdc14c929156f6adc52d13cd9a5a697218b..098cdb4460d76e8a04ad0af478d0705b4be1c170 100644 (file)
@@ -54,7 +54,7 @@
 #define CONFIG_CMDLINE_TAG             /* enable passing of ATAGs */
 #define CONFIG_OF_LIBFDT               /* enable passing of devicetree */
 
-#ifdef CONFIG_TEGRA20_LP0
+#ifdef CONFIG_TEGRA_LP0
 #define TEGRA_LP0_ADDR                 0x1C406000
 #define TEGRA_LP0_SIZE                 0x2000
 #define TEGRA_LP0_VEC \
 /* Environment information, boards can override if required */
 #define CONFIG_CONSOLE_MUX
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define TEGRA20_DEVICE_SETTINGS        "stdin=serial\0" \
-                                       "stdout=serial\0" \
-                                       "stderr=serial\0"
+#define TEGRA_DEVICE_SETTINGS  "stdin=serial\0" \
+                               "stdout=serial\0" \
+                               "stderr=serial\0"
 
 #define CONFIG_LOADADDR                0x408000        /* def. location for kernel */
 #define CONFIG_BOOTDELAY       2               /* -1 to disable auto boot */
 /* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE            (CONFIG_SYS_CBSIZE)
 
-#define CONFIG_SYS_MEMTEST_START       (TEGRA20_SDRC_CS0 + 0x600000)
+#define CONFIG_SYS_MEMTEST_START       (NV_PA_SDRC_CS0 + 0x600000)
 #define CONFIG_SYS_MEMTEST_END         (CONFIG_SYS_MEMTEST_START + 0x100000)
 
 #define CONFIG_SYS_LOAD_ADDR           (0xA00800)      /* default */
  * Physical Memory Map
  */
 #define CONFIG_NR_DRAM_BANKS   1
-#define PHYS_SDRAM_1           TEGRA20_SDRC_CS0
+#define PHYS_SDRAM_1           NV_PA_SDRC_CS0
 #define PHYS_SDRAM_1_SIZE      0x20000000      /* 512M */
 
 #define CONFIG_SYS_TEXT_BASE   0x0010c000
index b3c524981f512d45e2d8e6492180309a54a5a60b..a46890c0947fbe94f099acad8d96a2d229f51309 100644 (file)
 
 /* High-level configuration options */
 #define V_PROMPT               "Tegra20 (TrimSlice) # "
-#define CONFIG_TEGRA20_BOARD_STRING    "Compulab Trimslice"
+#define CONFIG_TEGRA_BOARD_STRING      "Compulab Trimslice"
 
 /* Board-specific serial config */
 #define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA20_ENABLE_UARTA
-#define CONFIG_TEGRA20_UARTA_GPU
+#define CONFIG_TEGRA_ENABLE_UARTA
+#define CONFIG_TEGRA_UARTA_GPU
 #define CONFIG_SYS_NS16550_COM1                NV_PA_APB_UARTA_BASE
 
 #define CONFIG_MACH_TYPE               MACH_TYPE_TRIMSLICE
@@ -94,6 +94,6 @@
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_DHCP
 
-#include "tegra20-common-post.h"
+#include "tegra-common-post.h"
 
 #endif /* __CONFIG_H */
index f5e1bf81ff18a8cd2ecca606a3a8be8b336753c1..7d3a54f74322ab2052d0cf0180ed27294e6026dd 100644 (file)
 
 /* High-level configuration options */
 #define V_PROMPT               "Tegra20 (Ventana) # "
-#define CONFIG_TEGRA20_BOARD_STRING    "NVIDIA Ventana"
+#define CONFIG_TEGRA_BOARD_STRING      "NVIDIA Ventana"
 
 /* Board-specific serial config */
 #define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA20_ENABLE_UARTD
+#define CONFIG_TEGRA_ENABLE_UARTD
 #define CONFIG_SYS_NS16550_COM1                NV_PA_APB_UARTD_BASE
 
 #define CONFIG_MACH_TYPE               MACH_TYPE_VENTANA
@@ -76,6 +76,6 @@
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_DHCP
 
-#include "tegra20-common-post.h"
+#include "tegra-common-post.h"
 
 #endif /* __CONFIG_H */
index 32357181556a1603fbd3dce3aad2860158cb510a..6c565bae14d8596430808bce638c654d215de1e4 100644 (file)
 
 /* High-level configuration options */
 #define V_PROMPT               "Tegra20 (Whistler) # "
-#define CONFIG_TEGRA20_BOARD_STRING    "NVIDIA Whistler"
+#define CONFIG_TEGRA_BOARD_STRING      "NVIDIA Whistler"
 
 /* Board-specific serial config */
 #define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA20_ENABLE_UARTA
-#define CONFIG_TEGRA20_UARTA_UAA_UAB
+#define CONFIG_TEGRA_ENABLE_UARTA
+#define CONFIG_TEGRA_UARTA_UAA_UAB
 #define CONFIG_SYS_NS16550_COM1                NV_PA_APB_UARTA_BASE
 
 #define CONFIG_MACH_TYPE               MACH_TYPE_WHISTLER
@@ -90,6 +90,6 @@
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_DHCP
 
-#include "tegra20-common-post.h"
+#include "tegra-common-post.h"
 
 #endif /* __CONFIG_H */