powerpc/mpc85xx: Temporary fix for spin table backward compatibility

Once u-boot sets the spin table to cache-enabled memory, old kernel which
uses cache-inhibit mapping without coherence will not work properly. We
use this temporary fix until kernel has updated its spin table code.
For now this fix is activated by default. To disable this fix for new
kernel, set environmental variable "spin_table_compat=no". After kernel
has updated spin table code, this default shall be changed.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 705c16c5583d768e0094c8652e2a39d7ad8b2c7b..9c1887f5927c86581d86c010cfc0caa6abebb4e5 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -350,6 +350,10 @@ int cpu_init_r(void)
 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
        struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
 #endif
+#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
+       extern int spin_table_compat;
+       const char *spin;
+#endif
 
 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
        defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
@@ -395,6 +399,14 @@ int cpu_init_r(void)
        }
 #endif
 
+#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
+       spin = getenv("spin_table_compat");
+       if (spin && (*spin == 'n'))
+               spin_table_compat = 0;
+       else
+               spin_table_compat = 1;
+#endif
+
        puts ("L2:    ");
 
 #if defined(CONFIG_L2_CACHE)

diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S
index 4ba44a9028b0e98e912a1a6a7e039329dc5c8489..1f76925dc185dd65b4c6c909338f7d4979fdd00b 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -351,6 +351,13 @@ __secondary_reset_vector:
        .align L1_CACHE_SHIFT
        .global __second_half_boot_page
 __second_half_boot_page:
+#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
+       lis     r3,(spin_table_compat - __second_half_boot_page)@h
+       ori     r3,r3,(spin_table_compat - __second_half_boot_page)@l
+       add     r3,r3,r11 /* r11 has the address of __second_half_boot_page */
+       lwz     r14,0(r3)
+#endif
+
 #define EPAPR_MAGIC            0x45504150
 #define ENTRY_ADDR_UPPER       0
 #define ENTRY_ADDR_LOWER       4
@@ -383,7 +390,24 @@ __second_half_boot_page:
        stw     r8,ENTRY_ADDR_LOWER(r10)
 
        /* spin waiting for addr */
-3:     lwz     r4,ENTRY_ADDR_LOWER(r10)
+3:
+/*
+ * To comply with ePAPR 1.1, the spin table has been moved to cache-enabled
+ * memory. Old OS may not work with this change. A patch is waiting to be
+ * accepted for Linux kernel. Other OS needs similar fix to spin table.
+ * For OSes with old spin table code, we can enable this temporary fix by
+ * setting environmental variable "spin_table_compat". For new OSes, set
+ * "spin_table_compat=no". After Linux is fixed, we can remove this macro
+ * and related code. For now, it is enabled by default.
+ */
+#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
+       cmpwi   r14,0
+       beq     4f
+       dcbf    0, r10
+       sync
+4:
+#endif
+       lwz     r4,ENTRY_ADDR_LOWER(r10)
        andi.   r11,r4,1
        bne     3b
        isync
@@ -460,5 +484,14 @@ __second_half_boot_page:
        .globl __spin_table
 __spin_table:
        .space CONFIG_MAX_CPUS*ENTRY_SIZE
+
+#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
+       .align L1_CACHE_SHIFT
+       .global spin_table_compat
+spin_table_compat:
+       .long   1
+
+#endif
+
 __spin_table_end:
        .space 4096 - (__spin_table_end - __spin_table)

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 61dd06142755aca06b7151eebaf46ecb6221bc17..d1c1e0681acab512c332c450e5184c55bc71d126 100644 (file)
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -27,6 +27,12 @@
 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
 #endif
 
+/*
+ * This macro should be removed when we no longer care about backwards
+ * compatibility with older operating systems.
+ */
+#define CONFIG_PPC_SPINTABLE_COMPATIBLE
+
 #define FSL_DDR_VER_4_7        47
 
 /* Number of TLB CAM entries we have on FSL Book-E chips */