]> git.sur5r.net Git - u-boot/commitdiff
x86: qemu: Add ATA/SATA support
authorBin Meng <bmeng.cn@gmail.com>
Sat, 16 May 2015 01:33:19 +0000 (09:33 +0800)
committerSimon Glass <sjg@chromium.org>
Thu, 4 Jun 2015 08:39:39 +0000 (02:39 -0600)
Enable legacy IDE support on the pc target and AHCI support on the
q35 target. Default configuration is to support the pc target.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
include/configs/qemu-x86.h
include/pci_ids.h

index e2a223fdd6e3b3319b9a775ae072164f7919b7ed..77f88d2422a3900b461a42735872c21e584ce474 100644 (file)
                                        "stdout=serial,vga\0" \
                                        "stderr=serial,vga\0"
 
+/*
+ * ATA/SATA support for QEMU x86 targets
+ *   - Only legacy IDE controller is supported for QEMU '-M pc' target
+ *   - AHCI controller is supported for QEMU '-M q35' target
+ *
+ * Default configuraion is to support the QEMU default x86 target
+ * Undefine CONFIG_CMD_IDE to support q35 target
+ */
+#define CONFIG_CMD_IDE
+#ifdef CONFIG_CMD_IDE
+#define CONFIG_SYS_IDE_MAXBUS          2
+#define CONFIG_SYS_IDE_MAXDEVICE       4
+#define CONFIG_SYS_ATA_BASE_ADDR       0
+#define CONFIG_SYS_ATA_DATA_OFFSET     0
+#define CONFIG_SYS_ATA_REG_OFFSET      0
+#define CONFIG_SYS_ATA_ALT_OFFSET      0
+#define CONFIG_SYS_ATA_IDE0_OFFSET     0x1f0
+#define CONFIG_SYS_ATA_IDE1_OFFSET     0x170
+#define CONFIG_ATAPI
+
+#undef CONFIG_SCSI_AHCI
+#undef CONFIG_CMD_SCSI
+#else
 #define CONFIG_SCSI_DEV_LIST           \
-       {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1}
+       {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_AHCI}
+#endif
 
 /* GPIO is not supported */
 #undef CONFIG_INTEL_ICH6_GPIO
index 2e6685112b6067596b70edf7e3567b8e881eb552..5771e12e7290b76e66dfb21b473e90e8737ee554 100644 (file)
 #define PCI_DEVICE_ID_INTEL_ICH9_6     0x2930
 #define PCI_DEVICE_ID_INTEL_ICH9_7     0x2916
 #define PCI_DEVICE_ID_INTEL_ICH9_8     0x2918
+#define PCI_DEVICE_ID_INTEL_ICH9_AHCI  0x2922
 #define PCI_DEVICE_ID_INTEL_I7_MCR     0x2c18
 #define PCI_DEVICE_ID_INTEL_I7_MC_TAD  0x2c19
 #define PCI_DEVICE_ID_INTEL_I7_MC_RAS  0x2c1a