mov r1, #CS4_BASE
ldrh r1, [r1, #0x2]
/* Is 27MHz switch set? */
- ands r1, r1, #0x16
+ ands r1, r1, #0x10
/* 532-133-66.5 */
ldr r0, =CCM_BASE
(mfd * pd)) << 10;
}
-u32 mx31_get_mpl_dpdgck_clk(void)
+static u32 mx31_get_mpl_dpdgck_clk(void)
{
u32 infreq;
return mx31_decode_pll(__REG(CCM_MPCTL), infreq);
}
-u32 mx31_get_mcu_main_clk(void)
+static u32 mx31_get_mcu_main_clk(void)
{
/* For now we assume mpl_dpdgck_clk == mcu_main_clk
* which should be correct for most boards
#ifndef __ASM_ARCH_MX31_H
#define __ASM_ARCH_MX31_H
-u32 mx31_get_mpl_dpdgck_clk(void);
-u32 mx31_get_mcu_main_clk(void);
-u32 mx31_get_ipg_clk(void);
-void mx31_gpio_mux(unsigned long mode);
+extern u32 mx31_get_ipg_clk(void);
+extern void mx31_gpio_mux(unsigned long mode);
#endif /* __ASM_ARCH_MX31_H */
#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
#define CONFIG_MX31 1 /* in a mx31 */
#define CONFIG_MX31_HCLK_FREQ 26000000 /* RedBoot says 26MHz */
-#define CONFIG_MX31_CLK32 32000
+#define CONFIG_MX31_CLK32 32768
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CFG_LOAD_ADDR CONFIG_LOADADDR
-#define CFG_HZ 32000
+#define CFG_HZ CONFIG_MX31_CLK32 /* use 32kHz clock as source */
#define CONFIG_CMDLINE_EDITING 1