]> git.sur5r.net Git - u-boot/commitdiff
85xx: Don't icbi when unlocking the cache
authorKumar Gala <galak@kernel.crashing.org>
Wed, 27 Feb 2008 22:30:47 +0000 (16:30 -0600)
committerAndrew Fleming-AFLEMING <afleming@freescale.com>
Wed, 27 Feb 2008 22:30:47 +0000 (16:30 -0600)
There is no reason to icbi when invalidating the temporary stack in
the d-cache.  Its impossible on e500 to have the i-cache contain
any addresses in the temp stack and it can be problematic in generating
transactions on the bus to non-valid addresses.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
cpu/mpc85xx/start.S

index 636ef5da63f296046e9c2eeb67a342f1d69f79f5..15b804d9fcbfe024139d4b9b2a97d23e7cf821b0 100644 (file)
@@ -992,7 +992,6 @@ trap_reloc:
 
        blr
 
-#ifdef CFG_INIT_RAM_LOCK
 .globl unlock_ram_in_cache
 unlock_ram_in_cache:
        /* invalidate the INIT_RAM section */
@@ -1002,11 +1001,10 @@ unlock_ram_in_cache:
        andi.   r4,r4,0x1ff
        slwi    r4,r4,(10 - 1 - L1_CACHE_SHIFT)
        mtctr   r4
-1:     icbi    r0,r3
-       dcbi    r0,r3
+1:     dcbi    r0,r3
        addi    r3,r3,CFG_CACHELINE_SIZE
        bdnz    1b
-       sync                    /* Wait for all icbi to complete on bus */
+       sync
 
        /* Invalidate the TLB entries for the cache */
        lis     r3,CFG_INIT_RAM_ADDR@h
@@ -1020,4 +1018,3 @@ unlock_ram_in_cache:
        tlbivax 0,r3
        isync
        blr
-#endif