powerpc/mpc8548: Add workaround for erratum NMG_LBC103

The erratum NMG_LBC103 is LBIU3 in MPC8548 errata document.
Any local bus transaction may fail during LBIU resynchronization
process when the clock divider [CLKDIV] is changing. Ensure there
is no transaction on the local bus for at least 100 microseconds
after changing clock divider LCRR[CLKDIV].

Refer to the erratum LBIU3 of mpc8548.

Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index f0fa0f565eb9a9803b100fe86f5182986118cdf9..a09eb914068de94081a3f06eca5b96767deba552 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -99,6 +99,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
        if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
                puts("Work-around for Erratum NMG DDR120 enabled\n");
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
+       puts("Work-around for Erratum NMG_LBC103 enabled\n");
 #endif
        return 0;
 }

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index e2c5b6fc3e242bb14e66b8ec5a2badaaaa70c9ed..0a4ce538f3b3494bd262af16234d30fec21ca0f3 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -463,6 +463,9 @@ skip_l2:
        clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
        __raw_readl(&lbc->lcrr);
        isync();
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
+       udelay(100);
+#endif
 #endif
 
 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index a0a12b23e77d195a9162fe58e7fadb96df4700f1..fc78c58d036445289d44ab47459994946716d683 100644 (file)
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -63,6 +63,7 @@
 #define CONFIG_SYS_FSL_SEC_COMPAT      2
 #define CONFIG_SYS_CCSRBAR_DEFAULT     0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
+#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
 
 #elif defined(CONFIG_MPC8555)
 #define CONFIG_MAX_CPUS                        1