+commit 467bcee11fe26ad422f2de971aa70866079870f2
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Fri Dec 14 15:36:18 2007 +0100
+
+ cfi_flash: Add manufacturer-specific fixups
+
+ Run fixups based on the JEDEC manufacturer ID independent of the
+ command set ID.
+
+ This changes current behaviour: Previously, geometry reversal for AMD
+ chips were done based on the command set ID, while they are now done
+ based on the JEDEC manufacturer and device ID.
+
+ Also add fixup for top-boot Atmel chips. A fixup is needed for
+ AT49BV6416(T) too, but since u-boot currently only reads the low byte
+ of the device ID, there's no way to tell it apart from AT49BV642D,
+ which should not have this fixup. Since AT49BV642D support is
+ necessary to get ATNGW100 board support into mainline, I've commented
+ out the fixup for now.
+
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 0ddf06ddf6b4bd057ad4c5f0dffea7870ba06a2a
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Fri Dec 14 15:36:17 2007 +0100
+
+ cfi_flash: Add cmdset-specific init functions
+
+ Move things like reading JEDEC IDs and fixing up geometry reversal
+ into separate functions. The geometry reversal fixup is now performed
+ by altering the qry structure directly, which makes the sector init
+ code slightly cleaner.
+
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit e23741f4a6d8047520ef0d4971762749b3587d32
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Fri Dec 14 15:36:16 2007 +0100
+
+ cfi_flash: Read whole QRY structure in one go
+
+ Read out the whole CFI Standard Query structure after successful cfi
+ identification. This allows subsequent code to access this information
+ directly without having to go through flash_read_uchar() and friends.
+
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit df9c25ea04b38a0e05d4f8c73c5cc144cdafa7db
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Mon Dec 17 11:02:44 2007 +0100
+
+ AVR32: Fix logic inversion in disable_interrupts()
+
+ disable_interrupts() should return nonzero if interrupts were
+ _enabled_ before, not disabled.
+
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit acac475212cbedb17b321a363a1c878e2b47b37f
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Fri Dec 14 16:51:22 2007 +0100
+
+ AVR32: Enable interrupts at bootup
+
+ The timer code depends on the timer interrupt to keep track of the
+ upper 32 bits of the cycle counter. This obviously doesn't work when
+ interrupts are disabled the whole time.
+
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 9570bcd87f4db255514f43b6701746c412f8fef0
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Thu Nov 15 10:03:45 2007 +0100
+
+ AVR32: Fix wrong pin setup for USART3
+
+ As reported by Gerhard Berghofer:
+
+ in "gpio_enable_usart3" the correct pins for USART 3 are PB17 and PB18
+ instead of PB18 and PB19.
+
+ which is obviously correct. There's currently no code that uses
+ USART3, but custom boards may run into problems.
+
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 09ea0de03dcc3ee7af045b0b572227bda2c1c918
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Thu Nov 1 12:44:20 2007 +0100
+
+ README: Remove ATSTK1000 daughterboard list
+
+ As noted by Kim Phillips, these lists tend to become out of date.
+
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit c81cbbad21cb0ae983e2e796211202234cdc8be2
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Tue Oct 30 14:56:36 2007 +0100
+
+ Add ATSTK100[234] to MAINTAINERS
+
+ Add all the ATSTK1000 daughterboards to MAINTAINERS along with their
+ "mother". Also update the entry for ATSTK1000 to be not only about the
+ AP7000 CPU; it's intended to handle all CPUs in the AT32AP family.
+
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 64ff2357b1727213803591813dbc779c924bf772
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Mon Oct 29 13:02:54 2007 +0100
+
+ AVR32: Add support for the ATSTK1004 board
+
+ ATSTK1004 is a daughterboard for ATSTK1000 with the AT32AP7002 CPU,
+ which is a derivative of AT32AP7000.
+
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 667568db157f374b85abd7e03596ddd1f0b25681
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Mon Oct 29 13:02:54 2007 +0100
+
+ AVR32: Add support for the ATSTK1003 board
+
+ ATSTK1003 is a daughterboard for ATSTK1000 with the AT32AP7001 CPU,
+ which is a derivative of AT32AP7000.
+
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 5fee84a794a51ec830548cda485a770efb018b92
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Mon Oct 29 13:23:33 2007 +0100
+
+ AVR32: Make some AT32AP700x peripherals optional
+
+ Add a chip-features file providing definitions of the form
+
+ AT32AP700x_CHIP_HAS_<peripheral>
+
+ to indicate the availability of the given peripheral on the currently
+ selected chip.
+
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 36f28f8a9605ee5dcfa330482cfc62171261af97
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Mon Oct 29 13:09:56 2007 +0100
+
+ AVR32: Rename at32ap7000 -> at32ap700x
+
+ The SoC-specific code for all the AT32AP700x CPUs is practically
+ identical; the only difference is that some chips have less features
+ than others. By doing this rename, we can add support for the AP7000
+ derivatives simply by making some features conditional.
+
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 4d5fa99c73f354e7cf985efcf417ea55ca2f6a5e
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Fri Jun 29 18:22:34 2007 +0200
+
+ atmel_mci: Show SR when block read fails
+
+ Show controller status as well as card status when an error occurs
+ during block read.
+
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 12d30aa79779c2aa7a998bbae4c075f822a53004
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Thu Dec 13 12:56:34 2007 +0100
+
+ cfi_flash: Use map_physmem() and unmap_physmem()
+
+ Use map_physmem() and unmap_physmem() to convert from physical to
+ virtual addresses. This gives the arch a chance to provide an uncached
+ mapping for flash accesses.
+
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 4d7d6936eb29af7cca330937808312aa5f61454d
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Thu Dec 13 12:56:33 2007 +0100
+
+ Introduce map_physmem() and unmap_physmem()
+
+ map_physmem() returns a virtual address which can be used to access a
+ given physical address without involving the cache. unmap_physmem()
+ should be called when the virtual address returned by map_physmem() is
+ no longer needed.
+
+ This patch adds a stub implementation which simply returns the
+ physical address cast to a uchar * for all architectures except AVR32,
+ which converts the physical address to an uncached virtual mapping.
+ unmap_physmem() is a no-op on all architectures, but if any
+ architecture needs to do such mappings through the TLB, this is the
+ hook where those TLB entries can be invalidated.
+
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit cdbaefb5f5f03e54455d0439dcf6dbd97ead1f9d
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Thu Dec 13 12:56:32 2007 +0100
+
+ cfi_flash: Introduce read and write accessors
+
+ Introduce flash_read{8,16,32,64) and flash_write{8,16,32,64} and use
+ them to access the flash memory. This makes it clearer when the flash
+ is actually being accessed; merely dereferencing a volatile pointer
+ looks just like any other kind of access.
+
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 812711ce6b3a386125dcf0d6a59588e461abbb87
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Thu Dec 13 12:56:31 2007 +0100
+
+ Implement __raw_{read,write}[bwl] on all architectures
+
+ This adds implementations of __raw_read[bwl] and __raw_write[bwl] to
+ m68k, ppc, nios and nios2. The m68k and ppc implementations were taken
+ from Linux.
+
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit be60a9021c82fc5aecd5b2b1fc96f70a9c81bbcd
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Sat Oct 6 18:55:36 2007 +0200
+
+ cfi_flash: Reorder functions and eliminate extra prototypes
+
+ Reorder the functions in cfi_flash.c so that each function only uses
+ functions that have been defined before it. This allows the static
+ prototype declarations near the top to be eliminated and might allow
+ gcc to do a better job inlining functions.
+
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 3055793bcbdf24b1f8117f606ffb766d32eb766f
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Thu Dec 13 12:56:29 2007 +0100
+
+ cfi_flash: Make some needlessly global functions static
+
+ Make functions not declared in any header file static.
+
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 7e5b9b471518c5652febc68ba62b432193d6abf4
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Thu Dec 13 12:56:28 2007 +0100
+
+ cfi_flash: Break long lines
+
+ This patch tries to keep all lines in the cfi_flash driver below 80
+ columns. There are a few lines left which don't fit this requirement
+ because I couldn't find any trivial way to break them (i.e. it would
+ take some restructuring, which I intend to do in a later patch.)
+
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+commit 42026c9cb3a76849b41e6e24abfb7b56807a5c1a
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date: Tue Dec 11 13:59:57 2007 +0100
+
+ CFI: synchronize command offsets with Linux CFI driver
+
+ Fixes non-working CFI Flash on the Inka4x0 board.
+
+ Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
+
+commit 8ff3de61fc5f9b3b21647bce081a3b7f710f0d4d
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Fri Dec 7 12:17:34 2007 -0600
+
+ Handle MPC85xx PCIe reset errata (PCI-Ex 38)
+
+ On the MPC85xx boards that have PCIe enable the PCIe errata fix.
+ (MPC8544DS, MPC8548CDS, MPC8568MDS).
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 82ac8c97145a4c3bf8b3dbfad00fa96e920f9b9c
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Fri Dec 7 12:04:30 2007 -0600
+
+ Update Freescale MPC85xx ADS/CDS/MDS board config
+
+ * Enabled CONFIG_CMD_ELF
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit d435793229ce29a42797c1edc39f5b34f987f91a
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Fri Dec 7 04:59:26 2007 -0600
+
+ Handle Asynchronous DDR clock on 85xx
+
+ The MPC8572 introduces the concept of an asynchronous DDR clock with
+ regards to the platform clock.
+
+ Introduce get_ddr_freq() to report the DDR freq regardless of sync/async
+ mode.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 22abb2d2eaf7b795a6923c6273ec9cb53fda9a10
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Thu Nov 29 10:34:28 2007 -0600
+
+ Update Freescale MPC85xx ADS/CDS/MDS board config
+
+ * Removed some misc environment setup
+ * Enabled CONFIG_CMDLINE_EDITING
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 415a613babb84d5e5d5b42e8e553868c71fc3a64
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Thu Nov 29 10:47:44 2007 -0600
+
+ Move the MPC8541/MPC8555/MPC8548 CDS board under board/freescale.
+
+ Minor path corrections needed to ensure buildability.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit c2d943ffbfd3359b3b45d177b437379d2cb86fbf
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Thu Nov 29 10:16:18 2007 -0600
+
+ Move the MPC8540 ADS board under board/freescale.
+
+ Minor path corrections needed to ensure buildability.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 870ceac5b3a3486c109396e005af81ae762b5710
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Thu Nov 29 10:14:50 2007 -0600
+
+ Move the MPC8560 ADS board under board/freescale.
+
+ Minor path corrections needed to ensure buildability.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit acbca876fb3fec25cd9c55b0efc81ff618ff5262
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Thu Nov 29 10:13:47 2007 -0600
+
+ Move the MPC8568 MDS board under board/freescale.
+
+ Minor path corrections needed to ensure buildability.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit a853d56c59b33415304531443633808736acfc6e
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Thu Nov 29 02:18:59 2007 -0600
+
+ Use standard LAWAR_TRGT_IF_* defines for LAW setup on 85xx
+
+ We already had defines for LAWAR_TRGT_IF_* that we should use
+ rather than creating new ones. Also, added some missing defines for
+ PCIE targets.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 04db400892da37b76a585e332a0c137954ad2015
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Thu Nov 29 02:10:09 2007 -0600
+
+ Stop using immap_t on 85xx
+
+ In the future the offsets to various blocks may not be in same location.
+ Move to using CFG_MPC85xx_*_ADDR as the base of the registers
+ instead of getting it via &immap.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 2714223f8e04ab3e4133ff65872eef366d90bfea
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Thu Nov 29 01:23:09 2007 -0600
+
+ Remove CONFIG_OF_FLAT_TREE related code from mpc85xx since we now use libfdt
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit c480861bf000156e6a3e932c258db59ff2212dd3
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Thu Nov 29 01:06:19 2007 -0600
+
+ Update MPC8568 MDS to use libfdt
+
+ Updated the MPC8568 MDS config to use libfdt and assume use of aliases for
+ ethernet, pci, and serial for the various fixups that are done.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 1563f56e0c68f6920f956382d6d13bee3f01c0f7
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date: Wed Nov 14 15:52:06 2007 -0500
+
+ Add PCI Express support on MPC8568MDS
+
+ Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit b90d25497625b90ffa3f2911a0895ca237556ff5
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Thu Nov 29 00:11:44 2007 -0600
+
+ Update MPC85xx CDS to use libfdt
+
+ Updated the MPC85xx CDS config to use libfdt and assume use of aliases for
+ ethernet, pci, and serial for the various fixups that are done.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 0fd5ec66b10521a057ad73e69ab5f0f9eafba255
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Wed Nov 28 22:54:27 2007 -0600
+
+ Update MPC8540 ADS to use libfdt
+
+ Updated the MPC8540 ADS config to use libfdt and assume use of aliases for
+ ethernet, pci, and serial for the various fixups that are done.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 5ce715802f6c50dc78b3405b92f184b1e3710519
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Wed Nov 28 22:40:31 2007 -0600
+
+ Update MPC8560 ADS to use libfdt
+
+ Updated the MPC8560 ADS config to use libfdt and assume use of aliases for
+ ethernet, pci, and serial for the various fixups that are done.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit aafeefbdb8b029f5ca2a195598d0a501a606eea9
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Wed Nov 28 00:36:33 2007 -0600
+
+ Stop using immap_t for cpm offset on 85xx
+
+ In the future the offsets to various blocks may not be in same location.
+ Move to using CFG_MPC85xx_CPM_ADDR as the base of the CPM registers
+ instead of getting it via &immap->im_cpm.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit f59b55a5b8fcadaa99781ba48e7a38e956afa527
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Tue Nov 27 23:25:02 2007 -0600
+
+ Stop using immap_t for guts offset on 85xx
+
+ In the future the offsets to various blocks may not be in same location.
+ Move to using CFG_MPC85xx_GUTS_ADDR as the base of the guts registers
+ instead of getting it via &immap->im_gur.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 50c03c8cf494d91cdec39670d95337c743e16ec9
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Tue Nov 27 22:42:34 2007 -0600
+
+ Update MPC8544 DS config
+
+ * Removed HAS_ETH2/HAS_ETH3 - MPC8544 only has TSEC1/2
+ * Removed some misc environment setup
+ * Moved to using fdtfile & fdtaddr as fdt env var names
+ * Enabled CONFIG_CMDLINE_EDITING
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit addce57e2e4c49e77ffb2020a84690713bb18b47
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Mon Nov 26 17:12:24 2007 -0600
+
+ Update MPC8544DS to use libfdt
+
+ Updated the MPC8544DS config to use libfdt and assume use of aliases for
+ ethernet, pci, and serial for the various fixups that are done.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit f852ce72f100cabd1f11c21c085a0ad8eca9fb65
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Thu Nov 29 00:15:30 2007 -0600
+
+ Add libfdt based ft_cpu_setup for mpc85xx
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 9692c2734a47f23b44a0f68042a3e2ca8d1bfb39
+Author: Stefan Roese <sr@denx.de>
+Date: Sat Dec 8 08:25:09 2007 +0100
+
+ CFI: Coding style cleanup
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 81b20ccc2d795ae9a1199db5a50ad9c28d1e4d22
+Author: Michael Schwingen <michael@schwingen.org>
+Date: Fri Dec 7 23:35:02 2007 +0100
+
+ CFI: support JEDEC flash roms in CFI-flash framework
+
+ The following patch adds support for non-CFI flash ROMS, by hooking into the
+ CFI flash code and using most of its code, as recently discussed here in the
+ thread "Mixing CFI and non-CFI flashs".
+
+ Signed-off-by: Michael Schwingen <michael@schwingen.org>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit c01b17dd856fa120b2970f50d9598546a4927ec3
+Author: Gerald Van Baren <vanbaren@cideas.com>
+Date: Wed Nov 28 21:24:50 2007 -0500
+
+ Conditionally compile fdt_fixup_ethernet()
+
+ Fix compiler warnings: On boards that don't have ethernets defined,
+ don't compile fdt_fixup_ethernet().
+
+commit 246d4ae6bc282bc1841224e1c5fc49dc925e0bf7
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Tue Nov 27 21:59:46 2007 -0600
+
+ Convert boards that set memory node to use fdt_fixup_memory()
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 151c8b09b35eebe8fd9139cb6c1d91c27b22f058
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Mon Nov 26 17:06:15 2007 -0600
+
+ Added fdt_fixup_stdout that uses aliases to set linux,stdout-path
+
+ We use a combination of the serialN alias and CONFIG_CONS_INDEX to
+ determine which serial alias we should set linux,stdout-path to.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 3c9272813fad84c691d0e4989bb18a3ffebdebfc
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Mon Nov 26 14:57:45 2007 -0600
+
+ Add common memory fixup function
+
+ Add the function fdt_fixup_memory() to fixup the /memory node of the fdt
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 9c9109e7fcf7ac2ca19c95b8ac54b8d1c773b157
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Mon Nov 26 11:19:12 2007 -0600
+
+ Conditionally compile fdt_support.c
+
+ Modify common/Makefile to conditionally compile fdt_support.c based
+ on CONFIG_OF_LIBFDT.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit d88e7ba0980773479e1a64badb293116071b7ef0
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Mon Nov 26 10:41:40 2007 -0600
+
+ Fix build breakage due to libfdt import
+
+ The IDS8247 got lost in the update and need an API update
+ do to rename of functions in libfdt.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 28f384b171bbf1fb2dafb1046e6d259a6b2f8714
+Author: Gerald Van Baren <vanbaren@cideas.com>
+Date: Fri Nov 23 19:43:20 2007 -0500
+
+ Add spaces around the = in the fdt print format.
+
+ Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
+
+commit 29592ecba3b932b9b152bcec6c0c0806412db4a3
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date: Fri Dec 7 01:25:38 2007 +0900
+
+ sh: Moved driver of the SuperH dependence
+
+ The composition of the directory in the drivers/ changed.
+ I moved SuperH serial driver and marubun PCMCIA driver.
+
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 41be969f4957115ed7b1fe8b890bfaee99d7a7a2
+Author: Wolfgang Denk <wd@denx.de>
+Date: Thu Dec 6 10:21:19 2007 +0100
+
+ Release v1.3.1
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit cf5933ba1e97a1cd8f5f24070e820f21d976eaeb
+Author: Wolfgang Denk <wd@denx.de>
+Date: Thu Dec 6 10:21:03 2007 +0100
+
+ ADS5121 Board: fix compile problem.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 8d4f040a3c15036a6ea25a9c39e7d89fefa8440d
+Author: Wolfgang Denk <wd@denx.de>
+Date: Mon Dec 3 00:15:28 2007 +0100
+
+ Prepare for 1.3.1-rc1
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 260eea5676ca46903a335686cc020b29c4ca46fe
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date: Thu Nov 29 01:21:54 2007 +0900
+
+ sh: Add SuperH boards maintainer to MAINTAINERS file
+
+ Add MS7750SE and MS7722SE's board maintainer to MAINTAINERS file.
+
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit aa9c4f1d22701a92347c1c81f34d12c8ad3a3747
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date: Thu Nov 29 00:13:04 2007 +0900
+
+ sh: Add ms7750se support in MAKEALL
+
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit c7144373427a178332bf9754131c8c34c52c200a
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Tue Nov 27 09:44:53 2007 +0100
+
+ sh: Add sh3 and sh4 support in MAKEALL
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 130080874a3d28450098481a262c5f7c855e908d
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date: Sun Nov 25 02:51:17 2007 +0900
+
+ sh: Add document for SuperH.
+
+ This document is a summary of information concerning SuperH of U-Boot.
+
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 33ecdc2f9d64926e1a6067b28f3a0aefc3b6d23d
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date: Sun Nov 25 02:39:31 2007 +0900
+
+ sh: Add marubun's pcmcia driver
+
+ Marubun pcmcia is a chip for PCMCIA used with SuperH.
+ Of course, this can be used even by other architectures.
+ When use this driver, came to be able to use CompactFlash
+ and Ethernet.
+
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit febd86b969b975289ed948f1ac0eb9722da41ced
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date: Sun Nov 25 02:32:13 2007 +0900
+
+ sh: Update SuperH SCIF driver
+
+ - Changed volatile unsigned to vu_.
+ - Changed Makefile for kconfig.
+
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
commit a5f601fd1b1278deae5aa9fc27a232b0d1c1c788
Author: Wolfgang Denk <wd@denx.de>
Date: Mon Nov 26 19:18:21 2007 +0100
synchronizition with mainline
+commit eda3e1e6619ad0bee94ae4b16c99d88e77e2af13
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date: Sun Sep 23 02:42:38 2007 +0900
+
+ sh: Add support command of ide with sh
+
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit d91ea45d15cf8e0987456bd211ffbb650824b6f1
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date: Sun Sep 23 02:38:42 2007 +0900
+
+ sh: Update Makefile
+
+ Add support MS7722SE01 to Makefile.
+
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 6c0bbdccd379f5c8702af9e0765294c2fb7472a6
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date: Sun Sep 23 02:31:13 2007 +0900
+
+ sh: Add support Renesas sh7722 processor and Hitachi MS7722SE01 board
+
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 047375bfa4c3052fa50a748da7ff89e9dad3b364
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date: Sun Sep 23 02:19:24 2007 +0900
+
+ sh: Update MS7750SE01 platform
+
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 516ad760db3553766267ada01b7d5d727faa4bbd
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date: Sun Sep 23 02:17:08 2007 +0900
+
+ sh: Remove comment out code from include/asm-sh/cpu_sh4.h
+
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit b02bad128669e567fce87d8df823b06a0144b8db
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date: Sun Sep 23 02:12:30 2007 +0900
+
+ sh: Update core code of SuperH.
+
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
commit 66dcad3a9a53e0766d90e0084123bd8529522fb0
Author: Wolfgang Denk <wd@denx.de>
Date: Thu Sep 20 00:04:14 2007 +0200
Fix to compile JSE against 20070514 git of u-boot
+commit 69df3c4da0c93017cceb25a366e794570bd0ed98
+Author: Nobuhiro Iwamatsu <iwamatsu@rahute.(none)>
+Date: Sun May 13 21:01:03 2007 +0900
+
+ sh: MS7750SE support.
+
+ This adds support for the Hitachi MS7750SE.
+
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 0b135cfc2e524dc249b75057b55dd4cc09842e27
+Author: Nobuhiro Iwamatsu <iwamatsu@rahute.(none)>
+Date: Sun May 13 20:58:00 2007 +0900
+
+ sh: First support code of SuperH.
+
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
commit 61936667e86a250ae12fd2dc189d3588f0a59e0b
Author: Stefan Roese <sr@denx.de>
Date: Fri May 11 12:01:49 2007 +0200
E: ADharankar@ATTBI.Com
D: threads / scheduler example code
-N: Kári DavÃðsson
+N: K?ri Dav??sson
E: kd@flaga.is
D: FLAGA DM Support
D: Port for the ModNET50 Board, NET+50 CPU Port
W: http://www.imms.de
-N: Daniel Engström
+N: Daniel Engstr?m
E: daniel@omicron.se
D: x86 port, Support for sc520_cdp board
E: frank.morauf@salzbrenner.com
D: Support for Embedded Planet RPX Super Board
-N: David Müller
+N: David M?ller
E: d.mueller@elsoft.ch
D: Support for Samsung ARM920T SMDK2410 eval board
E: azu@sysgo.de
D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM
W: www.elinos.com
+
+N: Nobuhiro Iwamatsu
+E: iwamatsu@nigauri.org
+D: Support for SuperH, MS7750SE01 and MS7722SE01 boards.
+W: http://www.nigauri.org/~iwamatsu/
CPCI4052 PPC405GP
CPCI405AB PPC405GP
CPCI405DT PPC405GP
- CPCI440 PPC440GP
CPCIISER4 PPC405GP
DASA_SIM IOP480 (PPC401)
DP405 PPC405EP
PCI405 PPC405GP
PLU405 PPC405EP
PMC405 PPC405GP
+ PMC440 PPC440EPx
VOH405 PPC405EP
VOM405 PPC405EP
WUH405 PPC405EP
cogent_mpc8260 MPC8260
hymod MPC8260
+Larry Johnson <lrj@acm.org>
+
+ korat PPC440EPx
+
Brad Kemp <Brad.Kemp@seranoa.com>
ppmc8260 MPC8260
bamboo PPC440EP
bunbinga PPC405EP
ebony PPC440GP
+ haleakala PPC405EXr
katmai PPC440SPe
+ kilauea PPC405EX
lwmon5 PPC440EPx
+ makalu PPC405EX
ocotea PPC440GX
p3p440 PPC440GP
pcs440ep PPC440EP
Haavard Skinnemoen <hskinnemoen@atmel.com>
- ATSTK1000 AT32AP7000
+ ATSTK1000 AT32AP7xxx
+ ATSTK1002 AT32AP7000
+ ATSTK1003 AT32AP7001
+ ATSTK1004 AT32AP7002
+
+#########################################################################
+# SuperH Systems: #
+# #
+# Maintainer Name, Email Address #
+# Board CPU #
+#########################################################################
+
+Nobuhiro Iwmaatsu <iwamatsu@nigauri.org>
+
+ MS7750SE SH7750
+ MS7722SE SH7722
#########################################################################
# End of MAINTAINERS list #
CPCI4052 \
CPCI405AB \
CPCI405DT \
- CPCI440 \
CPCIISER4 \
CRAYL1 \
csb272 \
ERIC \
EXBITGEN \
G2000 \
+ haleakala \
+ haleakala_nand \
hcu4 \
hcu5 \
HH405 \
JSE \
KAREF \
katmai \
+ kilauea \
+ kilauea_nand \
+ korat \
luan \
lwmon5 \
+ makalu \
METROBOX \
MIP405 \
MIP405T \
PIP405 \
PLU405 \
PMC405 \
+ PMC440 \
PPChameleonEVB \
rainier \
sbc405 \
LIST_avr32=" \
atstk1002 \
+ atstk1003 \
+ atstk1004 \
"
#########################################################################
bf561-ezkit \
"
+#########################################################################
+## SH Systems
+#########################################################################
+
+LIST_sh4=" \
+ ms7750se \
+ ms7722se \
+"
+
+LIST_sh3=""
+
+
+LIST_sh=" \
+ ${LIST_sh3} \
+ ${LIST_sh4} \
+"
+
#-----------------------------------------------------------------------
#----- for now, just run PPC by default -----
mips|mips_el| \
nios|nios2| \
ppc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx| \
- x86|I486|TSEC)
+ x86|I486|TSEC| \
+ sh|sh4|sh3 \
+ )
for target in `eval echo '$LIST_'${arg}`
do
build_target ${target}
ifeq ($(ARCH),avr32)
CROSS_COMPILE = avr32-linux-
endif
+ifeq ($(ARCH),sh)
+CROSS_COMPILE = sh4-linux-
+endif
endif
endif
@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci405 esd
@echo "BOARD_REVISION = $(@:_config=)" >> $(obj)include/config.mk
-CPCI440_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci440 esd
-
CPCIISER4_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpciiser4 esd
katmai_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx katmai amcc
+# Kilauea & Haleakala images are identical (recognized via PVR)
+kilauea_config \
+haleakala_config: unconfig
+ @$(MKCONFIG) -n $@ -a kilauea ppc ppc4xx kilauea amcc
+
+kilauea_nand_config \
+haleakala_nand_config: unconfig
+ @mkdir -p $(obj)include $(obj)board/amcc/kilauea
+ @mkdir -p $(obj)nand_spl/board/amcc/kilauea
+ @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
+ @$(MKCONFIG) -n $@ -a kilauea ppc ppc4xx kilauea amcc
+ @echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/kilauea/config.tmp
+ @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
+
+korat_config: unconfig
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx korat
+
luan_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx luan amcc
lwmon5_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx lwmon5
+makalu_config: unconfig
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx makalu amcc
+
METROBOX_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx metrobox sandburst
PMC405_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx pmc405 esd
+PMC440_config: unconfig
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx pmc440 esd
+
PPChameleonEVB_config \
PPChameleonEVB_BA_25_config \
PPChameleonEVB_ME_25_config \
fi; \
echo "#define CONFIG_$${CFREQ}MHz" >>$(obj)include/config.h ; \
echo "... with $${CFREQ}MHz system clock" ; \
- if [ "$${CACHE}" == "yes" ] ; then \
+ if [ "$${CACHE}" = "yes" ] ; then \
echo "#define CONFIG_L2_CACHE" >>$(obj)include/config.h ; \
echo "... with L2 Cache support" ; \
else \
echo "#undef CONFIG_L2_CACHE" >>$(obj)include/config.h ; \
echo "... without L2 Cache support" ; \
fi; \
- if [ "$${BMODE}" == "60x" ] ; then \
+ if [ "$${BMODE}" = "60x" ] ; then \
echo "#define CONFIG_BUSMODE_60x" >>$(obj)include/config.h ; \
echo "... with 60x Bus Mode" ; \
else \
M54455EVB_i66_config) FLASH=INTEL; FREQ=66666666;; \
esac; \
>include/config.h ; \
- if [ "$${FLASH}" == "INTEL" ] ; then \
+ if [ "$${FLASH}" = "INTEL" ] ; then \
echo "#undef CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \
echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54455evb/config.tmp ; \
cp $(obj)board/freescale/m54455evb/u-boot.int $(obj)board/freescale/m54455evb/u-boot.lds ; \
#########################################################################
MPC8540ADS_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8540ads
+ @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8540ads freescale
MPC8540EVAL_config \
MPC8540EVAL_33_config \
@$(MKCONFIG) -a MPC8540EVAL ppc mpc85xx mpc8540eval
MPC8560ADS_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8560ads
+ @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8560ads freescale
MPC8541CDS_legacy_config \
MPC8541CDS_config: unconfig
echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
echo "... legacy" ; \
fi
- @$(MKCONFIG) -a MPC8541CDS ppc mpc85xx mpc8541cds cds
+ @$(MKCONFIG) -a MPC8541CDS ppc mpc85xx mpc8541cds freescale
MPC8544DS_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8544ds freescale
echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
echo "... legacy" ; \
fi
- @$(MKCONFIG) -a MPC8548CDS ppc mpc85xx mpc8548cds cds
+ @$(MKCONFIG) -a MPC8548CDS ppc mpc85xx mpc8548cds freescale
MPC8555CDS_legacy_config \
MPC8555CDS_config: unconfig
echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
echo "... legacy" ; \
fi
- @$(MKCONFIG) -a MPC8555CDS ppc mpc85xx mpc8555cds cds
+ @$(MKCONFIG) -a MPC8555CDS ppc mpc85xx mpc8555cds freescale
MPC8568MDS_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds
+ @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds freescale
PM854_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx pm854
#########################################################################
atstk1002_config : unconfig
- @$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap7000
+ @$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x
+
+atstk1003_config : unconfig
+ @$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x
+
+atstk1004_config : unconfig
+ @$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x
+
+#########################################################################
+#########################################################################
+#########################################################################
+
+#########################################################################
+## sh4 (Renesas SuperH)
+#########################################################################
+ms7750se_config: unconfig
+ @ >include/config.h
+ @echo "#define CONFIG_MS7750SE 1" >> include/config.h
+ @./mkconfig -a $(@:_config=) sh sh4 ms7750se
+
+ms7722se_config : unconfig
+ @ >include/config.h
+ @echo "#define CONFIG_MS7722SE 1" >> include/config.h
+ @./mkconfig -a $(@:_config=) sh sh4 ms7722se
#########################################################################
#########################################################################
- Board Type: Define exactly one, e.g. CONFIG_MPC8540ADS.
- CPU Daughterboard Type: (if CONFIG_ATSTK1000 is defined)
- Define exactly one of
- CONFIG_ATSTK1002
-
+ Define exactly one, e.g. CONFIG_ATSTK1002
- CPU Module Type: (if CONFIG_COGENT is defined)
Define exactly one of
0x00, /* Module data width continued: +0 */
0x04, /* 2.5 Volt */
0x75, /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */
+ 0x00, /* SDRAM Access from clock */
#ifdef CONFIG_DDR_ECC
0x02, /* ECC ON : 02 OFF : 00 */
#else
0x00, /* ECC ON : 02 OFF : 00 */
#endif
- 0x82, /* refresh Rate Type: Normal (15.625us) + Self refresh */
- 0,
+ 0x82, /* refresh Rate Type: Normal (7.8us) + Self refresh */
0,
0,
0x01, /* wcsbc = 1 */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
-/* . = env_offset;*/
-/* common/environment.o(.text)*/
*(.text)
*(.fixup)
cpu/ppc4xx/start.o (.text)
board/amcc/ebony/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
-/* . = env_offset;*/
-/* common/environment.o(.text)*/
*(.text)
*(.fixup)
#include <common.h>
#include <ppc4xx.h>
-#include <asm/processor.h>
#include <i2c.h>
-#include <asm-ppc/io.h>
-#include <asm-ppc/gpio.h>
-
-#include "../cpu/ppc4xx/440spe_pcie.h"
-
-#undef PCIE_ENDPOINT
-/* #define PCIE_ENDPOINT 1 */
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/4xx_pcie.h>
DECLARE_GLOBAL_DATA_PTR;
-int ppc440spe_init_pcie_rootport(int port);
-void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
-
int board_early_init_f (void)
{
unsigned long mfr;
mtdcr (uic0sr, 0x00000000); /* clear all interrupts*/
mtdcr (uic0sr, 0xffffffff); /* clear all interrupts*/
-/* SDR0_MFR should be part of Ethernet init */
- mfsdr (sdr_mfr, mfr);
- mfr &= ~SDR0_MFR_ECS_MASK;
-/* mtsdr(sdr_mfr, mfr); */
+ mfsdr(sdr_mfr, mfr);
+ mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
+ mtsdr(sdr_mfr, mfr);
mtsdr(SDR0_PFC0, CFG_PFC0);
{
struct pci_controller *hose;
int i, bus;
+ int ret = 0;
char *env;
unsigned int delay;
if (!katmai_pcie_card_present(i))
continue;
-#ifdef PCIE_ENDPOINT
- if (ppc440spe_init_pcie_endport(i)) {
-#else
- if (ppc440spe_init_pcie_rootport(i)) {
-#endif
- printf("PCIE%d: initialization failed\n", i);
+ if (is_end_point(i))
+ ret = ppc4xx_init_pcie_endport(i);
+ else
+ ret = ppc4xx_init_pcie_rootport(i);
+ if (ret) {
+ printf("PCIE%d: initialization as %s failed\n", i,
+ is_end_point(i) ? "endpoint" : "root-complex");
continue;
}
CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
CFG_PCIE_MEMSIZE,
- PCI_REGION_MEM
- );
+ PCI_REGION_MEM);
hose->region_count = 1;
pci_register_hose(hose);
-#ifdef PCIE_ENDPOINT
- ppc440spe_setup_pcie_endpoint(hose, i);
- /*
- * Reson for no scanning is endpoint can not generate
- * upstream configuration accesses.
- */
-#else
- ppc440spe_setup_pcie_rootpoint(hose, i);
-
- env = getenv ("pciscandelay");
- if (env != NULL) {
- delay = simple_strtoul (env, NULL, 10);
- if (delay > 5)
- printf ("Warning, expect noticable delay before PCIe"
- "scan due to 'pciscandelay' value!\n");
- mdelay (delay * 1000);
+ if (is_end_point(i)) {
+ ppc4xx_setup_pcie_endpoint(hose, i);
+ /*
+ * Reson for no scanning is endpoint can not generate
+ * upstream configuration accesses.
+ */
+ } else {
+ ppc4xx_setup_pcie_rootpoint(hose, i);
+ env = getenv ("pciscandelay");
+ if (env != NULL) {
+ delay = simple_strtoul(env, NULL, 10);
+ if (delay > 5)
+ printf("Warning, expect noticable delay before "
+ "PCIe scan due to 'pciscandelay' value!\n");
+ mdelay(delay * 1000);
+ }
+
+ /*
+ * Config access can only go down stream
+ */
+ hose->last_busno = pci_hose_scan(hose);
+ bus = hose->last_busno + 1;
}
-
- /*
- * Config access can only go down stream
- */
- hose->last_busno = pci_hose_scan(hose);
- bus = hose->last_busno + 1;
-#endif
}
}
#endif /* defined(CONFIG_PCI) */
return (ctrlc());
}
#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ u32 val[4];
+ int rc;
+
+ ft_cpu_setup(blob, bd);
+
+ /* Fixup NOR mapping */
+ val[0] = 0; /* chip select number */
+ val[1] = 0; /* always 0 */
+ val[2] = gd->bd->bi_flashstart;
+ val[3] = gd->bd->bi_flashsize;
+ rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
+ val, sizeof(val), 1);
+ if (rc)
+ printf("Unable to update property NOR mapping, err=%s\n",
+ fdt_strerror(rc));
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
--- /dev/null
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS = $(BOARD).o cmd_pll.o memory.o
+SOBJS = init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend *~
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/*
+ * ehnus: change pll frequency.
+ * Wed Sep 5 11:45:17 CST 2007
+ * hsun@udtech.com.cn
+ */
+
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <i2c.h>
+
+#ifdef CONFIG_CMD_EEPROM
+
+#define EEPROM_CONF_OFFSET 0
+#define EEPROM_TEST_OFFSET 16
+#define EEPROM_SDSTP_PARAM 16
+
+#define PLL_NAME_MAX 12
+#define BUF_STEP 8
+
+/* eeprom_wirtes 8Byte per op. */
+#define EEPROM_ALTER_FREQ(freq) \
+ do { \
+ int __i; \
+ for (__i = 0; __i < 2; __i++) \
+ eeprom_write (CFG_I2C_EEPROM_ADDR, \
+ EEPROM_CONF_OFFSET + __i*BUF_STEP, \
+ pll_select[freq], \
+ BUF_STEP + __i*BUF_STEP); \
+ } while (0)
+
+#define PDEBUG
+#ifdef PDEBUG
+#define PLL_DEBUG pll_debug(EEPROM_CONF_OFFSET)
+#else
+#define PLL_DEBUG
+#endif
+
+typedef enum {
+ PLL_ebc20,
+ PLL_333,
+ PLL_4001,
+ PLL_4002,
+ PLL_533,
+ PLL_600,
+ PLL_666, /* For now, kilauea can't support */
+ RCONF,
+ WTEST,
+ PLL_TOTAL
+} pll_freq_t;
+
+static const char
+pll_name[][PLL_NAME_MAX] = {
+ "PLL_ebc20",
+ "PLL_333",
+ "PLL_400@1",
+ "PLL_400@2",
+ "PLL_533",
+ "PLL_600",
+ "PLL_666",
+ "RCONF",
+ "WTEST",
+ ""
+};
+
+/*
+ * ehnus:
+ */
+static uchar
+pll_select[][EEPROM_SDSTP_PARAM] = {
+ /* 0: CPU 333MHz EBC 20MHz, for test only */
+ {
+ 0x8c, 0x12, 0xec, 0x12, 0x88, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ },
+
+ /* 0: 333 */
+ {
+ 0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ },
+
+ /* 1: 400_266 */
+ {
+ 0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ },
+
+ /* 2: 400 */
+ {
+ 0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ },
+
+ /* 3: 533 */
+ {
+ 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ },
+
+ /* 4: 600 */
+ {
+ 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ },
+
+ /* 5: 666 */
+ {
+ 0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ },
+
+ {}
+};
+
+static uchar
+testbuf[EEPROM_SDSTP_PARAM] = {
+ 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
+ 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff
+};
+
+static void
+pll_debug(int off)
+{
+ int i;
+ uchar buffer[EEPROM_SDSTP_PARAM];
+
+ memset(buffer, 0, sizeof(buffer));
+ eeprom_read(CFG_I2C_EEPROM_ADDR, off,
+ buffer, EEPROM_SDSTP_PARAM);
+
+ printf("Debug: SDSTP[0-3] at offset \"0x%02x\" lists as follows: \n", off);
+ for (i = 0; i < EEPROM_SDSTP_PARAM; i++)
+ printf("%02x ", buffer[i]);
+ printf("\n");
+}
+
+static void
+test_write(void)
+{
+ printf("Debug: test eeprom_write ... ");
+
+ /*
+ * Write twice, 8 bytes per write
+ */
+ eeprom_write (CFG_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET,
+ testbuf, 8);
+ eeprom_write (CFG_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET+8,
+ testbuf, 16);
+ printf("done\n");
+
+ pll_debug(EEPROM_TEST_OFFSET);
+}
+
+int
+do_pll_alter (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ char c = '\0';
+ pll_freq_t pll_freq;
+ if (argc < 2) {
+ printf("Usage: \n%s\n", cmdtp->usage);
+ goto ret;
+ }
+
+ for (pll_freq = PLL_ebc20; pll_freq < PLL_TOTAL; pll_freq++)
+ if (!strcmp(pll_name[pll_freq], argv[1]))
+ break;
+
+ switch (pll_freq) {
+ case PLL_ebc20:
+ case PLL_333:
+ case PLL_4001:
+ case PLL_4002:
+ case PLL_533:
+ case PLL_600:
+ EEPROM_ALTER_FREQ(pll_freq);
+ break;
+
+ case PLL_666: /* not support */
+ printf("Choose this option will result in a boot failure."
+ "\nContinue? (Y/N): ");
+
+ c = getc(); putc('\n');
+
+ if ((c == 'y') || (c == 'Y')) {
+ EEPROM_ALTER_FREQ(pll_freq);
+ break;
+ }
+ goto ret;
+
+ case RCONF:
+ pll_debug(EEPROM_CONF_OFFSET);
+ goto ret;
+ case WTEST:
+ printf("DEBUG: write test\n");
+ test_write();
+ goto ret;
+
+ default:
+ printf("Invalid options"
+ "\n\nUsage: \n%s\n", cmdtp->usage);
+ goto ret;
+ }
+
+ printf("PLL set to %s, "
+ "reset the board to take effect\n", pll_name[pll_freq]);
+
+ PLL_DEBUG;
+ret:
+ return 0;
+}
+
+U_BOOT_CMD(
+ pllalter, CFG_MAXARGS, 1, do_pll_alter,
+ "pllalter- change pll frequence \n",
+ "pllalter <selection> - change pll frequence \n\n\
+ ** New freq take effect after reset. ** \n\
+ ----------------------------------------------\n\
+ PLL_ebc20: Board: AMCC 405EX(r) Evaluation Board\n\
+ \t Same as PLL_333 \n\
+ \t except \n\
+ \t EBC: 20 MHz \n\
+ ----------------------------------------------\n\
+ PLL_333: Board: AMCC 405EX(r) Evaluation Board\n\
+ \t VCO: 666 MHz \n\
+ \t CPU: 333 MHz \n\
+ \t PLB: 166 MHz \n\
+ \t OPB: 83 MHz \n\
+ \t DDR: 83 MHz \n\
+ ------------------------------------------------\n\
+ PLL_400@1: Board: AMCC 405EX(r) Evaluation Board\n\
+ \t VCO: 800 MHz \n\
+ \t CPU: 400 MHz \n\
+ \t PLB: 133 MHz \n\
+ \t OPB: 66 MHz \n\
+ \t DDR: 133 MHz \n\
+ ------------------------------------------------\n\
+ PLL_400@2: Board: AMCC 405EX(r) Evaluation Board\n\
+ \t VCO: 800 MHz \n\
+ \t CPU: 400 MHz \n\
+ \t PLB: 200 MHz \n\
+ \t OPB: 100 MHz \n\
+ \t DDR: 200 MHz \n\
+ ----------------------------------------------\n\
+ PLL_533: Board: AMCC 405EX(r) Evaluation Board\n\
+ \t VCO: 1066 MHz \n\
+ \t CPU: 533 MHz \n\
+ \t PLB: 177 MHz \n\
+ \t OPB: 88 MHz \n\
+ \t DDR: 177 MHz \n\
+ ----------------------------------------------\n\
+ PLL_600: Board: AMCC 405EX(r) Evaluation Board\n\
+ \t VCO: 1200 MHz \n\
+ \t CPU: 600 MHz \n\
+ \t PLB: 200 MHz \n\
+ \t OPB: 100 MHz \n\
+ \t DDR: 200 MHz \n\
+ ----------------------------------------------\n\
+ PLL_666: Board: AMCC 405EX(r) Evaluation Board\n\
+ \t VCO: 1333 MHz \n\
+ \t CPU: 666 MHz \n\
+ \t PLB: 166 MHz \n\
+ \t OPB: 83 MHz \n\
+ \t DDR: 166 MHz \n\
+ -----------------------------------------------\n\
+ RCONF: Read current eeprom configuration. \n\
+ -----------------------------------------------\n\
+ WTEST: Test EEPROM write with predefined values\n\
+ -----------------------------------------------\n"
+ );
+
+#endif /* (CONFIG_COMMANDS & CFG_CMD_EEPROM) */
--- /dev/null
+#
+# (C) Copyright 2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+TEXT_BASE = 0xFFFA0000
+endif
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Based on code provided from UDTech and AMCC
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <ppc4xx.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#define mtsdram_as(reg, value) \
+ addi r4,0,reg ; \
+ mtdcr memcfga,r4 ; \
+ addis r4,0,value@h ; \
+ ori r4,r4,value@l ; \
+ mtdcr memcfgd,r4 ;
+
+ .globl ext_bus_cntlr_init
+ext_bus_cntlr_init:
+#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+
+ /*
+ * DDR2 setup
+ */
+
+ /* Following the DDR Core Manual, here is the initialization */
+
+ /* Step 1 */
+
+ /* Step 2 */
+
+ /* Step 3 */
+
+ /* base=00000000, size=256MByte (6), mode=7 (n*10*8) */
+ mtsdram_as(SDRAM_MB0CF, 0x00006701);
+
+ /* SET SDRAM_MB1CF - Not enabled */
+ mtsdram_as(SDRAM_MB1CF, 0x00000000);
+
+ /* SET SDRAM_MB2CF - Not enabled */
+ mtsdram_as(SDRAM_MB2CF, 0x00000000);
+
+ /* SET SDRAM_MB3CF - Not enabled */
+ mtsdram_as(SDRAM_MB3CF, 0x00000000);
+
+ /* SDRAM_CLKTR: Adv Addr clock by 90 deg */
+ mtsdram_as(SDRAM_CLKTR, 0x80000000);
+
+ /* Refresh Time register (0x30) Refresh every 7.8125uS */
+ mtsdram_as(SDRAM_RTR, 0x06180000);
+
+ /* SDRAM_SDTR1 */
+ mtsdram_as(SDRAM_SDTR1, 0x80201000);
+
+ /* SDRAM_SDTR2 */
+ mtsdram_as(SDRAM_SDTR2, 0x32204232);
+
+ /* SDRAM_SDTR3 */
+ mtsdram_as(SDRAM_SDTR3, 0x080b0d1a);
+
+ mtsdram_as(SDRAM_MMODE, 0x00000442);
+ mtsdram_as(SDRAM_MEMODE, 0x00000404);
+
+ /* SDRAM0_MCOPT1 (0X20) No ECC Gen */
+ mtsdram_as(SDRAM_MCOPT1, 0x04322000);
+
+ /* NOP */
+ mtsdram_as(SDRAM_INITPLR0, 0xa8380000);
+ /* precharge 3 DDR clock cycle */
+ mtsdram_as(SDRAM_INITPLR1, 0x81900400);
+ /* EMR2 twr = 2tck */
+ mtsdram_as(SDRAM_INITPLR2, 0x81020000);
+ /* EMR3 twr = 2tck */
+ mtsdram_as(SDRAM_INITPLR3, 0x81030000);
+ /* EMR DLL ENABLE twr = 2tck */
+ mtsdram_as(SDRAM_INITPLR4, 0x81010404);
+ /* MR w/ DLL reset
+ * Note: 5 is CL. May need to be changed
+ */
+ mtsdram_as(SDRAM_INITPLR5, 0x81000542);
+ /* precharge 3 DDR clock cycle */
+ mtsdram_as(SDRAM_INITPLR6, 0x81900400);
+ /* Auto-refresh trfc = 26tck */
+ mtsdram_as(SDRAM_INITPLR7, 0x8D080000);
+ /* Auto-refresh trfc = 26tck */
+ mtsdram_as(SDRAM_INITPLR8, 0x8D080000);
+ /* Auto-refresh */
+ mtsdram_as(SDRAM_INITPLR9, 0x8D080000);
+ /* Auto-refresh */
+ mtsdram_as(SDRAM_INITPLR10, 0x8D080000);
+ /* MRS - normal operation; wait 2 cycle (set wait to tMRD) */
+ mtsdram_as(SDRAM_INITPLR11, 0x81000442);
+ mtsdram_as(SDRAM_INITPLR12, 0x81010780);
+ mtsdram_as(SDRAM_INITPLR13, 0x81010400);
+ mtsdram_as(SDRAM_INITPLR14, 0x00000000);
+ mtsdram_as(SDRAM_INITPLR15, 0x00000000);
+
+ /* SET MCIF0_CODT Die Termination On */
+ mtsdram_as(SDRAM_CODT, 0x0080f837);
+ mtsdram_as(SDRAM_MODT0, 0x01800000);
+ mtsdram_as(SDRAM_MODT1, 0x00000000);
+
+ mtsdram_as(SDRAM_WRDTR, 0x00000000);
+
+ /* SDRAM0_MCOPT2 (0X21) Start initialization */
+ mtsdram_as(SDRAM_MCOPT2, 0x20000000);
+
+ /* Step 5 */
+ lis r3,0x1 /* 400000 = wait 100ms */
+ mtctr r3
+
+pll_wait:
+ bdnz pll_wait
+
+ /* Step 6 */
+
+ /* SDRAM_DLCR */
+ mtsdram_as(SDRAM_DLCR, 0x030000a5);
+
+ /* SDRAM_RDCC */
+ mtsdram_as(SDRAM_RDCC, 0x40000000);
+
+ /* SDRAM_RQDC */
+ mtsdram_as(SDRAM_RQDC, 0x80000038);
+
+ /* SDRAM_RFDC */
+ mtsdram_as(SDRAM_RFDC, 0x00000209);
+
+ /* Enable memory controller */
+ mtsdram_as(SDRAM_MCOPT2, 0x28000000);
+#endif /* #ifndef CONFIG_NAND_U_BOOT */
+
+ blr
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <ppc405.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_PCI)
+#include <pci.h>
+#include <asm/4xx_pcie.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*
+ * Board early initialization function
+ */
+int board_early_init_f (void)
+{
+ u32 val;
+
+ /*--------------------------------------------------------------------+
+ | Interrupt controller setup for the AMCC 405EX(r) PINE evaluation board.
+ +--------------------------------------------------------------------+
+ +---------------------------------------------------------------------+
+ |Interrupt| Source | Pol. | Sensi.| Crit. |
+ +---------+-----------------------------------+-------+-------+-------+
+ | IRQ 00 | UART0 | High | Level | Non |
+ | IRQ 01 | UART1 | High | Level | Non |
+ | IRQ 02 | IIC0 | High | Level | Non |
+ | IRQ 03 | TBD | High | Level | Non |
+ | IRQ 04 | TBD | High | Level | Non |
+ | IRQ 05 | EBM | High | Level | Non |
+ | IRQ 06 | BGI | High | Level | Non |
+ | IRQ 07 | IIC1 | Rising| Edge | Non |
+ | IRQ 08 | SPI | High | Lvl/ed| Non |
+ | IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non |
+ | IRQ 10 | MAL TX EOB | High | Level | Non |
+ | IRQ 11 | MAL RX EOB | High | Level | Non |
+ | IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non |
+ | IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non |
+ | IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non |
+ | IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non |
+ | IRQ 16 | PCIE0 AL | high | Level | Non |
+ | IRQ 17 | PCIE0 VPD access | rising| Edge | Non |
+ | IRQ 18 | PCIE0 hot reset request | rising| Edge | Non |
+ | IRQ 19 | PCIE0 hot reset request | faling| Edge | Non |
+ | IRQ 20 | PCIE0 TCR | High | Level | Non |
+ | IRQ 21 | PCIE0 MSI level0 | High | Level | Non |
+ | IRQ 22 | PCIE0 MSI level1 | High | Level | Non |
+ | IRQ 23 | Security EIP-94 | High | Level | Non |
+ | IRQ 24 | EMAC0 interrupt | High | Level | Non |
+ | IRQ 25 | EMAC1 interrupt | High | Level | Non |
+ | IRQ 26 | PCIE0 MSI level2 | High | Level | Non |
+ | IRQ 27 | External IRQ 4 | pgm H | Pgm | Non |
+ | IRQ 28 | UIC2 Non-critical Int. | High | Level | Non |
+ | IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. |
+ | IRQ 30 | UIC1 Non-critical Int. | High | Level | Non |
+ | IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. |
+ |----------------------------------------------------------------------
+ | IRQ 32 | MAL Serr | High | Level | Non |
+ | IRQ 33 | MAL Txde | High | Level | Non |
+ | IRQ 34 | MAL Rxde | High | Level | Non |
+ | IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non |
+ | IRQ 36 | PCIE0 DCR Error | High | Level | Non |
+ | IRQ 37 | EBC | High |Lvl Edg| Non |
+ | IRQ 38 | NDFC | High | Level | Non |
+ | IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non |
+ | IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non |
+ | IRQ 41 | PCIE1 AL | high | Level | Non |
+ | IRQ 42 | PCIE1 VPD access | rising| edge | Non |
+ | IRQ 43 | PCIE1 hot reset request | rising| Edge | Non |
+ | IRQ 44 | PCIE1 hot reset request | faling| Edge | Non |
+ | IRQ 45 | PCIE1 TCR | High | Level | Non |
+ | IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non |
+ | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
+ | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
+ | IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non |
+ | IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non |
+ | IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
+ | IRQ 52 | GPT Compare Timer 5 | high | Edge | Non |
+ | IRQ 53 | GPT Compare Timer 6 | high | Edge | Non |
+ | IRQ 54 | GPT Compare Timer 7 | high | Edge | Non |
+ | IRQ 55 | Serial ROM | High | Level | Non |
+ | IRQ 56 | GPT Decrement Pulse | High | Level | Non |
+ | IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non |
+ | IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non |
+ | IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non |
+ | IRQ 60 | EMAC0 Wake-up | High | Level | Non |
+ | IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non |
+ | IRQ 62 | EMAC1 Wake-up | High | Level | Non |
+ |----------------------------------------------------------------------
+ | IRQ 64 | PE0 AL | High | Level | Non |
+ | IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
+ | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
+ | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
+ | IRQ 68 | PE0 TCR | High | Level | Non |
+ | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
+ | IRQ 70 | PE0 DCR Error | High | Level | Non |
+ | IRQ 71 | Reserved | N/A | N/A | Non |
+ | IRQ 72 | PE1 AL | High | Level | Non |
+ | IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
+ | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
+ | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
+ | IRQ 76 | PE1 TCR | High | Level | Non |
+ | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
+ | IRQ 78 | PE1 DCR Error | High | Level | Non |
+ | IRQ 79 | Reserved | N/A | N/A | Non |
+ | IRQ 80 | PE2 AL | High | Level | Non |
+ | IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
+ | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
+ | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
+ | IRQ 84 | PE2 TCR | High | Level | Non |
+ | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
+ | IRQ 86 | PE2 DCR Error | High | Level | Non |
+ | IRQ 87 | Reserved | N/A | N/A | Non |
+ | IRQ 88 | External IRQ(5) | Progr | Progr | Non |
+ | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
+ | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
+ | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
+ | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
+ | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
+ | IRQ 94 | Reserved | N/A | N/A | Non |
+ | IRQ 95 | Reserved | N/A | N/A | Non |
+ |---------------------------------------------------------------------
+ +---------+-----------------------------------+-------+-------+------*/
+ /*--------------------------------------------------------------------+
+ | Initialise UIC registers. Clear all interrupts. Disable all
+ | interrupts.
+ | Set critical interrupt values. Set interrupt polarities. Set
+ | interrupt trigger levels. Make bit 0 High priority. Clear all
+ | interrupts again.
+ +-------------------------------------------------------------------*/
+
+ mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
+ mtdcr (uic2er, 0x00000000); /* disable all interrupts */
+ mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts */
+ mtdcr (uic2pr, 0xf7ffffff); /* Set Interrupt Polarities */
+ mtdcr (uic2tr, 0x01e1fff8); /* Set Interrupt Trigger Levels */
+ mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
+ mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
+
+ mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */
+ mtdcr (uic1er, 0x00000000); /* disable all interrupts */
+ mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts */
+ mtdcr (uic1pr, 0xfffac785); /* Set Interrupt Polarities */
+ mtdcr (uic1tr, 0x001d0040); /* Set Interrupt Trigger Levels */
+ mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr (uic1sr, 0x00000000); /* clear all interrupts */
+ mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */
+
+ mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
+ mtdcr (uic0er, 0x0000000a); /* Disable all interrupts */
+ /* Except cascade UIC0 and UIC1 */
+ mtdcr (uic0cr, 0x00000000); /* Set Critical / Non Critical interrupts */
+ mtdcr (uic0pr, 0xffbfefef); /* Set Interrupt Polarities */
+ mtdcr (uic0tr, 0x00007000); /* Set Interrupt Trigger Levels */
+ mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr (uic0sr, 0x00000000); /* clear all interrupts */
+ mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */
+
+ /*
+ * Note: Some cores are still in reset when the chip starts, so
+ * take them out of reset
+ */
+ mtsdr(SDR0_SRST, 0);
+
+ /*
+ * Configure FPGA register with PCIe reset
+ */
+ out_be32((void *)CFG_FPGA_BASE, 0xff570cc0); /* assert PCIe reset */
+ mdelay(50);
+ out_be32((void *)CFG_FPGA_BASE, 0xff570cc3); /* deassert PCIe reset */
+
+ /* Configure 405EX for NAND usage */
+ val = SDR0_CUST0_MUX_NDFC_SEL |
+ SDR0_CUST0_NDFC_ENABLE |
+ SDR0_CUST0_NDFC_BW_8_BIT |
+ SDR0_CUST0_NRB_BUSY |
+ (0x80000000 >> (28 + CFG_NAND_CS));
+ mtsdr(SDR0_CUST0, val);
+
+ /*
+ * Configure PFC (Pin Function Control) registers
+ * -> Enable USB
+ */
+ val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ;
+ mtsdr(SDR0_PFC1, val);
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+#ifdef CFG_ENV_IS_IN_FLASH
+ /* Monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ -CFG_MONITOR_LEN,
+ 0xffffffff,
+ &flash_info[0]);
+#endif
+
+ return 0;
+}
+
+int board_emac_count(void)
+{
+ u32 pvr = get_pvr();
+
+ /*
+ * 405EXr only has one EMAC interface, 405EX has two
+ */
+ if ((pvr == PVR_405EXR1_RA) || (pvr == PVR_405EXR2_RA))
+ return 1;
+ else
+ return 2;
+}
+
+static int board_pcie_count(void)
+{
+ u32 pvr = get_pvr();
+
+ /*
+ * 405EXr only has one EMAC interface, 405EX has two
+ */
+ if ((pvr == PVR_405EXR1_RA) || (pvr == PVR_405EXR2_RA))
+ return 1;
+ else
+ return 2;
+}
+
+int checkboard (void)
+{
+ char *s = getenv("serial#");
+ u32 pvr = get_pvr();
+
+ if ((pvr == PVR_405EXR1_RA) || (pvr == PVR_405EXR2_RA))
+ printf("Board: Haleakala - AMCC PPC405EXr Evaluation Board");
+ else
+ printf("Board: Kilauea - AMCC PPC405EX Evaluation Board");
+
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+ putc('\n');
+
+ return (0);
+}
+
+/*************************************************************************
+ * pci_pre_init
+ *
+ * This routine is called just prior to registering the hose and gives
+ * the board the opportunity to check things. Returning a value of zero
+ * indicates that things are bad & PCI initialization should be aborted.
+ *
+ * Different boards may wish to customize the pci controller structure
+ * (add regions, override default access routines, etc) or perform
+ * certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int pci_pre_init(struct pci_controller * hose )
+{
+ return 0;
+}
+#endif /* defined(CONFIG_PCI) */
+
+#ifdef CONFIG_PCI
+static struct pci_controller pcie_hose[2] = {{0},{0}};
+
+void pcie_setup_hoses(int busno)
+{
+ struct pci_controller *hose;
+ int i, bus;
+ int ret = 0;
+ bus = busno;
+ char *env;
+ unsigned int delay;
+
+ for (i = 0; i < board_pcie_count(); i++) {
+
+ if (is_end_point(i))
+ ret = ppc4xx_init_pcie_endport(i);
+ else
+ ret = ppc4xx_init_pcie_rootport(i);
+ if (ret) {
+ printf("PCIE%d: initialization as %s failed\n", i,
+ is_end_point(i) ? "endpoint" : "root-complex");
+ continue;
+ }
+
+ hose = &pcie_hose[i];
+ hose->first_busno = bus;
+ hose->last_busno = bus;
+ hose->current_busno = bus;
+
+ /* setup mem resource */
+ pci_set_region(hose->regions + 0,
+ CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
+ CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
+ CFG_PCIE_MEMSIZE,
+ PCI_REGION_MEM);
+ hose->region_count = 1;
+ pci_register_hose(hose);
+
+ if (is_end_point(i)) {
+ ppc4xx_setup_pcie_endpoint(hose, i);
+ /*
+ * Reson for no scanning is endpoint can not generate
+ * upstream configuration accesses.
+ */
+ } else {
+ ppc4xx_setup_pcie_rootpoint(hose, i);
+ env = getenv ("pciscandelay");
+ if (env != NULL) {
+ delay = simple_strtoul(env, NULL, 10);
+ if (delay > 5)
+ printf("Warning, expect noticable delay before "
+ "PCIe scan due to 'pciscandelay' value!\n");
+ mdelay(delay * 1000);
+ }
+
+ /*
+ * Config access can only go down stream
+ */
+ hose->last_busno = pci_hose_scan(hose);
+ bus = hose->last_busno + 1;
+ }
+ }
+}
+#endif
+
+#if defined(CONFIG_POST)
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+ return 0; /* No hotkeys supported */
+}
+#endif /* CONFIG_POST */
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ u32 val[4];
+ int rc;
+
+ ft_cpu_setup(blob, bd);
+
+ /* Fixup NOR mapping */
+ val[0] = 0; /* chip select number */
+ val[1] = 0; /* always 0 */
+ val[2] = gd->bd->bi_flashstart;
+ val[3] = gd->bd->bi_flashsize;
+ rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
+ val, sizeof(val), 1);
+ if (rc)
+ printf("Unable to update property NOR mapping, err=%s\n",
+ fdt_strerror(rc));
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <i2c.h>
+
+void sdram_init(void)
+{
+ return;
+}
+
+long int initdram(int board_type)
+{
+ return (CFG_MBYTES_SDRAM << 20);
+}
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+ printf ("testdram\n");
+#if defined (CONFIG_NAND_U_BOOT)
+ return 0;
+#endif
+ uint *pstart = (uint *) 0x00000000;
+ uint *pend = (uint *) 0x00001000;
+ uint *p;
+
+ for (p = pstart; p < pend; p++) {
+ *p = 0xaaaaaaaa;
+ }
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+#if !defined (CONFIG_NAND_SPL)
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+#endif
+ return 1;
+ }
+ }
+
+ for (p = pstart; p < pend; p++) {
+ *p = 0x55555555;
+ }
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+#if !defined (CONFIG_NAND_SPL)
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+#endif
+ return 1;
+ }
+ }
+#if !defined (CONFIG_NAND_SPL)
+ printf ("SDRAM test passed!!!\n");
+#endif
+ return 0;
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+
+ /* Align to next NAND block */
+ . = ALIGN(0x4000);
+ common/environment.o (.ppcenv)
+ /* Keep some space here for redundant env and potential bad env blocks */
+ . = ALIGN(0x10000);
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+/* To compile successfully, uncomment the following section.
+ * To go in ram, remove the section.
+ * Added by SunHe.
+ */
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/ppc4xx/start.o (.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
************************************************************************/
int board_early_init_f(void)
{
+ u32 mfr;
+
mtebc( pb0ap, 0x03800000 ); /* set chip selects */
mtebc( pb0cr, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
mtebc( pb1ap, 0x03800000 );
mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */
mtdcr( uic0sr, 0xffffffff );
+ mfsdr(sdr_mfr, mfr);
+ mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
+ mtsdr(sdr_mfr, mfr);
+
return 0;
}
--- /dev/null
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS = $(BOARD).o cmd_pll.o memory.o
+SOBJS = init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend *~
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/*
+ * ehnus: change pll frequency.
+ * Wed Sep 5 11:45:17 CST 2007
+ * hsun@udtech.com.cn
+ */
+
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <i2c.h>
+
+#ifdef CONFIG_CMD_EEPROM
+
+#define EEPROM_CONF_OFFSET 0
+#define EEPROM_TEST_OFFSET 16
+#define EEPROM_SDSTP_PARAM 16
+
+#define PLL_NAME_MAX 12
+#define BUF_STEP 8
+
+/* eeprom_wirtes 8Byte per op. */
+#define EEPROM_ALTER_FREQ(freq) \
+ do { \
+ int __i; \
+ for (__i = 0; __i < 2; __i++) \
+ eeprom_write (CFG_I2C_EEPROM_ADDR, \
+ EEPROM_CONF_OFFSET + __i*BUF_STEP, \
+ pll_select[freq], \
+ BUF_STEP + __i*BUF_STEP); \
+ } while (0)
+
+#define PDEBUG
+#ifdef PDEBUG
+#define PLL_DEBUG pll_debug(EEPROM_CONF_OFFSET)
+#else
+#define PLL_DEBUG
+#endif
+
+typedef enum {
+ PLL_ebc20,
+ PLL_333,
+ PLL_4001,
+ PLL_4002,
+ PLL_533,
+ PLL_600,
+ PLL_666, /* For now, kilauea can't support */
+ RCONF,
+ WTEST,
+ PLL_TOTAL
+} pll_freq_t;
+
+static const char
+pll_name[][PLL_NAME_MAX] = {
+ "PLL_ebc20",
+ "PLL_333",
+ "PLL_400@1",
+ "PLL_400@2",
+ "PLL_533",
+ "PLL_600",
+ "PLL_666",
+ "RCONF",
+ "WTEST",
+ ""
+};
+
+/*
+ * ehnus:
+ */
+static uchar
+pll_select[][EEPROM_SDSTP_PARAM] = {
+ /* 0: CPU 333MHz EBC 20MHz, for test only */
+ {
+ 0x8c, 0x12, 0xec, 0x12, 0x88, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ },
+
+ /* 0: 333 */
+ {
+ 0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ },
+
+ /* 1: 400_266 */
+ {
+ 0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ },
+
+ /* 2: 400 */
+ {
+ 0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ },
+
+ /* 3: 533 */
+ {
+ 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ },
+
+ /* 4: 600 */
+ {
+ 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ },
+
+ /* 5: 666 */
+ {
+ 0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ },
+
+ {}
+};
+
+static uchar
+testbuf[EEPROM_SDSTP_PARAM] = {
+ 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
+ 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff
+};
+
+static void
+pll_debug(int off)
+{
+ int i;
+ uchar buffer[EEPROM_SDSTP_PARAM];
+
+ memset(buffer, 0, sizeof(buffer));
+ eeprom_read(CFG_I2C_EEPROM_ADDR, off,
+ buffer, EEPROM_SDSTP_PARAM);
+
+ printf("Debug: SDSTP[0-3] at offset \"0x%02x\" lists as follows: \n", off);
+ for (i = 0; i < EEPROM_SDSTP_PARAM; i++)
+ printf("%02x ", buffer[i]);
+ printf("\n");
+}
+
+static void
+test_write(void)
+{
+ printf("Debug: test eeprom_write ... ");
+
+ /*
+ * Write twice, 8 bytes per write
+ */
+ eeprom_write (CFG_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET,
+ testbuf, 8);
+ eeprom_write (CFG_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET+8,
+ testbuf, 16);
+ printf("done\n");
+
+ pll_debug(EEPROM_TEST_OFFSET);
+}
+
+int
+do_pll_alter (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ char c = '\0';
+ pll_freq_t pll_freq;
+ if (argc < 2) {
+ printf("Usage: \n%s\n", cmdtp->usage);
+ goto ret;
+ }
+
+ for (pll_freq = PLL_ebc20; pll_freq < PLL_TOTAL; pll_freq++)
+ if (!strcmp(pll_name[pll_freq], argv[1]))
+ break;
+
+ switch (pll_freq) {
+ case PLL_ebc20:
+ case PLL_333:
+ case PLL_4001:
+ case PLL_4002:
+ case PLL_533:
+ case PLL_600:
+ EEPROM_ALTER_FREQ(pll_freq);
+ break;
+
+ case PLL_666: /* not support */
+ printf("Choose this option will result in a boot failure."
+ "\nContinue? (Y/N): ");
+
+ c = getc(); putc('\n');
+
+ if ((c == 'y') || (c == 'Y')) {
+ EEPROM_ALTER_FREQ(pll_freq);
+ break;
+ }
+ goto ret;
+
+ case RCONF:
+ pll_debug(EEPROM_CONF_OFFSET);
+ goto ret;
+ case WTEST:
+ printf("DEBUG: write test\n");
+ test_write();
+ goto ret;
+
+ default:
+ printf("Invalid options"
+ "\n\nUsage: \n%s\n", cmdtp->usage);
+ goto ret;
+ }
+
+ printf("PLL set to %s, "
+ "reset the board to take effect\n", pll_name[pll_freq]);
+
+ PLL_DEBUG;
+ret:
+ return 0;
+}
+
+U_BOOT_CMD(
+ pllalter, CFG_MAXARGS, 1, do_pll_alter,
+ "pllalter- change pll frequence \n",
+ "pllalter <selection> - change pll frequence \n\n\
+ ** New freq take effect after reset. ** \n\
+ ----------------------------------------------\n\
+ PLL_ebc20: Board: AMCC 405EX(r) Evaluation Board\n\
+ \t Same as PLL_333 \n\
+ \t except \n\
+ \t EBC: 20 MHz \n\
+ ----------------------------------------------\n\
+ PLL_333: Board: AMCC 405EX(r) Evaluation Board\n\
+ \t VCO: 666 MHz \n\
+ \t CPU: 333 MHz \n\
+ \t PLB: 166 MHz \n\
+ \t OPB: 83 MHz \n\
+ \t DDR: 83 MHz \n\
+ ------------------------------------------------\n\
+ PLL_400@1: Board: AMCC 405EX(r) Evaluation Board\n\
+ \t VCO: 800 MHz \n\
+ \t CPU: 400 MHz \n\
+ \t PLB: 133 MHz \n\
+ \t OPB: 66 MHz \n\
+ \t DDR: 133 MHz \n\
+ ------------------------------------------------\n\
+ PLL_400@2: Board: AMCC 405EX(r) Evaluation Board\n\
+ \t VCO: 800 MHz \n\
+ \t CPU: 400 MHz \n\
+ \t PLB: 200 MHz \n\
+ \t OPB: 100 MHz \n\
+ \t DDR: 200 MHz \n\
+ ----------------------------------------------\n\
+ PLL_533: Board: AMCC 405EX(r) Evaluation Board\n\
+ \t VCO: 1066 MHz \n\
+ \t CPU: 533 MHz \n\
+ \t PLB: 177 MHz \n\
+ \t OPB: 88 MHz \n\
+ \t DDR: 177 MHz \n\
+ ----------------------------------------------\n\
+ PLL_600: Board: AMCC 405EX(r) Evaluation Board\n\
+ \t VCO: 1200 MHz \n\
+ \t CPU: 600 MHz \n\
+ \t PLB: 200 MHz \n\
+ \t OPB: 100 MHz \n\
+ \t DDR: 200 MHz \n\
+ ----------------------------------------------\n\
+ PLL_666: Board: AMCC 405EX(r) Evaluation Board\n\
+ \t VCO: 1333 MHz \n\
+ \t CPU: 666 MHz \n\
+ \t PLB: 166 MHz \n\
+ \t OPB: 83 MHz \n\
+ \t DDR: 166 MHz \n\
+ -----------------------------------------------\n\
+ RCONF: Read current eeprom configuration. \n\
+ -----------------------------------------------\n\
+ WTEST: Test EEPROM write with predefined values\n\
+ -----------------------------------------------\n"
+ );
+
+#endif /* (CONFIG_COMMANDS & CFG_CMD_EEPROM) */
--- /dev/null
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xFFFA0000
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Based on code provided from Senao and AMCC
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <ppc4xx.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#define mtsdram_as(reg, value) \
+ addi r4,0,reg ; \
+ mtdcr memcfga,r4 ; \
+ addis r4,0,value@h ; \
+ ori r4,r4,value@l ; \
+ mtdcr memcfgd,r4 ;
+
+ .globl ext_bus_cntlr_init
+ext_bus_cntlr_init:
+
+ /*
+ * DDR2 setup
+ */
+
+ /* Following the DDR Core Manual, here is the initialization */
+
+ /* Step 1 */
+
+ /* Step 2 */
+
+ /* Step 3 */
+
+ /* base=00000000, size=128MByte (5), mode=2 (n*10*4) */
+ mtsdram_as(SDRAM_MB0CF, 0x00005201);
+
+ /* base=08000000, size=128MByte (5), mode=2 (n*10*4) */
+ mtsdram_as(SDRAM_MB1CF, (0x08000000 >> 3) | 0x5201);
+
+ /* SDRAM_CLKTR: Adv Addr clock by 90 deg */
+ mtsdram_as(SDRAM_CLKTR,0x80000000);
+
+ /* Refresh Time register (0x30) Refresh every 7.8125uS */
+ mtsdram_as(SDRAM_RTR, 0x06180000);
+
+ /* SDRAM_SDTR1 */
+ mtsdram_as(SDRAM_SDTR1, 0x80201000);
+
+ /* SDRAM_SDTR2 */
+ mtsdram_as(SDRAM_SDTR2, 0x32204232);
+
+ /* SDRAM_SDTR3 */
+ mtsdram_as(SDRAM_SDTR3, 0x080b0d1a);
+
+ mtsdram_as(SDRAM_MMODE, 0x00000442);
+ mtsdram_as(SDRAM_MEMODE, 0x00000404);
+
+ /* SDRAM0_MCOPT1 (0X20) No ECC Gen */
+ mtsdram_as(SDRAM_MCOPT1, 0x04322000);
+
+ /* NOP */
+ mtsdram_as(SDRAM_INITPLR0, 0xa8380000);
+ /* precharge 3 DDR clock cycle */
+ mtsdram_as(SDRAM_INITPLR1, 0x81900400);
+ /* EMR2 twr = 2tck */
+ mtsdram_as(SDRAM_INITPLR2, 0x81020000);
+ /* EMR3 twr = 2tck */
+ mtsdram_as(SDRAM_INITPLR3, 0x81030000);
+ /* EMR DLL ENABLE twr = 2tck */
+ mtsdram_as(SDRAM_INITPLR4, 0x81010404);
+ /* MR w/ DLL reset
+ * Note: 5 is CL. May need to be changed
+ */
+ mtsdram_as(SDRAM_INITPLR5, 0x81000542);
+ /* precharge 3 DDR clock cycle */
+ mtsdram_as(SDRAM_INITPLR6, 0x81900400);
+ /* Auto-refresh trfc = 26tck */
+ mtsdram_as(SDRAM_INITPLR7, 0x8D080000);
+ /* Auto-refresh trfc = 26tck */
+ mtsdram_as(SDRAM_INITPLR8, 0x8D080000);
+ /* Auto-refresh */
+ mtsdram_as(SDRAM_INITPLR9, 0x8D080000);
+ /* Auto-refresh */
+ mtsdram_as(SDRAM_INITPLR10, 0x8D080000);
+ /* MRS - normal operation; wait 2 cycle (set wait to tMRD) */
+ mtsdram_as(SDRAM_INITPLR11, 0x81000442);
+ mtsdram_as(SDRAM_INITPLR12, 0x81010780);
+ mtsdram_as(SDRAM_INITPLR13, 0x81010400);
+ mtsdram_as(SDRAM_INITPLR14, 0x00000000);
+ mtsdram_as(SDRAM_INITPLR15, 0x00000000);
+
+ /* SET MCIF0_CODT Die Termination On */
+ mtsdram_as(SDRAM_CODT, 0x0080f837);
+ mtsdram_as(SDRAM_MODT0, 0x01800000);
+#if 0 /* test-only: not sure if 0 is ok when 2nd bank is used */
+ mtsdram_as(SDRAM_MODT1, 0x00000000);
+#endif
+
+ mtsdram_as(SDRAM_WRDTR, 0x00000000);
+
+ /* SDRAM0_MCOPT2 (0X21) Start initialization */
+ mtsdram_as(SDRAM_MCOPT2, 0x20000000);
+
+ /* Step 5 */
+ lis r3,0x1 /* 400000 = wait 100ms */
+ mtctr r3
+
+pll_wait:
+ bdnz pll_wait
+
+ /* Step 6 */
+
+ /* SDRAM_DLCR */
+ mtsdram_as(SDRAM_DLCR, 0x030000a5);
+
+ /* SDRAM_RDCC */
+ mtsdram_as(SDRAM_RDCC, 0x40000000);
+
+ /* SDRAM_RQDC */
+ mtsdram_as(SDRAM_RQDC, 0x80000038);
+
+ /* SDRAM_RFDC */
+ mtsdram_as(SDRAM_RFDC, 0x00000209);
+
+ /* Enable memory controller */
+ mtsdram_as(SDRAM_MCOPT2, 0x28000000);
+
+ blr
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <ppc405.h>
+#include <libfdt.h>
+#include <asm/processor.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_PCI)
+#include <pci.h>
+#include <asm/4xx_pcie.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*
+ * Board early initialization function
+ */
+int board_early_init_f (void)
+{
+ u32 val;
+
+ /*--------------------------------------------------------------------+
+ | Interrupt controller setup for the AMCC 405EX(r) PINE evaluation board.
+ +--------------------------------------------------------------------+
+ +---------------------------------------------------------------------+
+ |Interrupt| Source | Pol. | Sensi.| Crit. |
+ +---------+-----------------------------------+-------+-------+-------+
+ | IRQ 00 | UART0 | High | Level | Non |
+ | IRQ 01 | UART1 | High | Level | Non |
+ | IRQ 02 | IIC0 | High | Level | Non |
+ | IRQ 03 | TBD | High | Level | Non |
+ | IRQ 04 | TBD | High | Level | Non |
+ | IRQ 05 | EBM | High | Level | Non |
+ | IRQ 06 | BGI | High | Level | Non |
+ | IRQ 07 | IIC1 | Rising| Edge | Non |
+ | IRQ 08 | SPI | High | Lvl/ed| Non |
+ | IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non |
+ | IRQ 10 | MAL TX EOB | High | Level | Non |
+ | IRQ 11 | MAL RX EOB | High | Level | Non |
+ | IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non |
+ | IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non |
+ | IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non |
+ | IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non |
+ | IRQ 16 | PCIE0 AL | high | Level | Non |
+ | IRQ 17 | PCIE0 VPD access | rising| Edge | Non |
+ | IRQ 18 | PCIE0 hot reset request | rising| Edge | Non |
+ | IRQ 19 | PCIE0 hot reset request | faling| Edge | Non |
+ | IRQ 20 | PCIE0 TCR | High | Level | Non |
+ | IRQ 21 | PCIE0 MSI level0 | High | Level | Non |
+ | IRQ 22 | PCIE0 MSI level1 | High | Level | Non |
+ | IRQ 23 | Security EIP-94 | High | Level | Non |
+ | IRQ 24 | EMAC0 interrupt | High | Level | Non |
+ | IRQ 25 | EMAC1 interrupt | High | Level | Non |
+ | IRQ 26 | PCIE0 MSI level2 | High | Level | Non |
+ | IRQ 27 | External IRQ 4 | pgm H | Pgm | Non |
+ | IRQ 28 | UIC2 Non-critical Int. | High | Level | Non |
+ | IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. |
+ | IRQ 30 | UIC1 Non-critical Int. | High | Level | Non |
+ | IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. |
+ |----------------------------------------------------------------------
+ | IRQ 32 | MAL Serr | High | Level | Non |
+ | IRQ 33 | MAL Txde | High | Level | Non |
+ | IRQ 34 | MAL Rxde | High | Level | Non |
+ | IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non |
+ | IRQ 36 | PCIE0 DCR Error | High | Level | Non |
+ | IRQ 37 | EBC | High |Lvl Edg| Non |
+ | IRQ 38 | NDFC | High | Level | Non |
+ | IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non |
+ | IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non |
+ | IRQ 41 | PCIE1 AL | high | Level | Non |
+ | IRQ 42 | PCIE1 VPD access | rising| edge | Non |
+ | IRQ 43 | PCIE1 hot reset request | rising| Edge | Non |
+ | IRQ 44 | PCIE1 hot reset request | faling| Edge | Non |
+ | IRQ 45 | PCIE1 TCR | High | Level | Non |
+ | IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non |
+ | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
+ | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
+ | IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non |
+ | IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non |
+ | IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
+ | IRQ 52 | GPT Compare Timer 5 | high | Edge | Non |
+ | IRQ 53 | GPT Compare Timer 6 | high | Edge | Non |
+ | IRQ 54 | GPT Compare Timer 7 | high | Edge | Non |
+ | IRQ 55 | Serial ROM | High | Level | Non |
+ | IRQ 56 | GPT Decrement Pulse | High | Level | Non |
+ | IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non |
+ | IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non |
+ | IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non |
+ | IRQ 60 | EMAC0 Wake-up | High | Level | Non |
+ | IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non |
+ | IRQ 62 | EMAC1 Wake-up | High | Level | Non |
+ |----------------------------------------------------------------------
+ | IRQ 64 | PE0 AL | High | Level | Non |
+ | IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
+ | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
+ | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
+ | IRQ 68 | PE0 TCR | High | Level | Non |
+ | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
+ | IRQ 70 | PE0 DCR Error | High | Level | Non |
+ | IRQ 71 | Reserved | N/A | N/A | Non |
+ | IRQ 72 | PE1 AL | High | Level | Non |
+ | IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
+ | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
+ | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
+ | IRQ 76 | PE1 TCR | High | Level | Non |
+ | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
+ | IRQ 78 | PE1 DCR Error | High | Level | Non |
+ | IRQ 79 | Reserved | N/A | N/A | Non |
+ | IRQ 80 | PE2 AL | High | Level | Non |
+ | IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
+ | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
+ | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
+ | IRQ 84 | PE2 TCR | High | Level | Non |
+ | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
+ | IRQ 86 | PE2 DCR Error | High | Level | Non |
+ | IRQ 87 | Reserved | N/A | N/A | Non |
+ | IRQ 88 | External IRQ(5) | Progr | Progr | Non |
+ | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
+ | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
+ | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
+ | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
+ | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
+ | IRQ 94 | Reserved | N/A | N/A | Non |
+ | IRQ 95 | Reserved | N/A | N/A | Non |
+ |---------------------------------------------------------------------
+ +---------+-----------------------------------+-------+-------+------*/
+ /*--------------------------------------------------------------------+
+ | Initialise UIC registers. Clear all interrupts. Disable all
+ | interrupts.
+ | Set critical interrupt values. Set interrupt polarities. Set
+ | interrupt trigger levels. Make bit 0 High priority. Clear all
+ | interrupts again.
+ +-------------------------------------------------------------------*/
+
+ mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
+ mtdcr (uic2er, 0x00000000); /* disable all interrupts */
+ mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts */
+ mtdcr (uic2pr, 0xf7ffffff); /* Set Interrupt Polarities */
+ mtdcr (uic2tr, 0x01e1fff8); /* Set Interrupt Trigger Levels */
+ mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
+ mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
+
+ mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */
+ mtdcr (uic1er, 0x00000000); /* disable all interrupts */
+ mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts */
+ mtdcr (uic1pr, 0xfffac785); /* Set Interrupt Polarities */
+ mtdcr (uic1tr, 0x001d0040); /* Set Interrupt Trigger Levels */
+ mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr (uic1sr, 0x00000000); /* clear all interrupts */
+ mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */
+
+ mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
+ mtdcr (uic0er, 0x0000000a); /* Disable all interrupts */
+ /* Except cascade UIC0 and UIC1 */
+ mtdcr (uic0cr, 0x00000000); /* Set Critical / Non Critical interrupts */
+ mtdcr (uic0pr, 0xffbfefef); /* Set Interrupt Polarities */
+ mtdcr (uic0tr, 0x00007000); /* Set Interrupt Trigger Levels */
+ mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr (uic0sr, 0x00000000); /* clear all interrupts */
+ mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */
+
+ /*
+ * Note: Some cores are still in reset when the chip starts, so
+ * take them out of reset
+ */
+ mtsdr(SDR0_SRST, 0);
+
+ /* Reset PCIe slots */
+ gpio_write_bit(CFG_GPIO_PCIE_RST, 0);
+ udelay(100);
+ gpio_write_bit(CFG_GPIO_PCIE_RST, 1);
+
+ /*
+ * Configure PFC (Pin Function Control) registers
+ * -> Enable USB
+ */
+ val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ;
+ mtsdr(SDR0_PFC1, val);
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+#ifdef CFG_ENV_IS_IN_FLASH
+ /* Monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ -CFG_MONITOR_LEN,
+ 0xffffffff,
+ &flash_info[0]);
+#endif
+
+ return 0;
+}
+
+int checkboard (void)
+{
+ char *s = getenv("serial#");
+
+ printf("Board: Makalu - AMCC PPC405EX Evaluation Board");
+
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+ putc('\n');
+
+ return (0);
+}
+
+/*************************************************************************
+ * pci_pre_init
+ *
+ * This routine is called just prior to registering the hose and gives
+ * the board the opportunity to check things. Returning a value of zero
+ * indicates that things are bad & PCI initialization should be aborted.
+ *
+ * Different boards may wish to customize the pci controller structure
+ * (add regions, override default access routines, etc) or perform
+ * certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int pci_pre_init(struct pci_controller * hose )
+{
+ return 0;
+}
+#endif /* defined(CONFIG_PCI) */
+
+#ifdef CONFIG_PCI
+static struct pci_controller pcie_hose[2] = {{0},{0}};
+
+void pcie_setup_hoses(int busno)
+{
+ struct pci_controller *hose;
+ int i, bus;
+ int ret = 0;
+ bus = busno;
+ char *env;
+ unsigned int delay;
+
+ for (i = 0; i < 2; i++) {
+
+ if (is_end_point(i))
+ ret = ppc4xx_init_pcie_endport(i);
+ else
+ ret = ppc4xx_init_pcie_rootport(i);
+ if (ret) {
+ printf("PCIE%d: initialization as %s failed\n", i,
+ is_end_point(i) ? "endpoint" : "root-complex");
+ continue;
+ }
+
+ hose = &pcie_hose[i];
+ hose->first_busno = bus;
+ hose->last_busno = bus;
+ hose->current_busno = bus;
+
+ /* setup mem resource */
+ pci_set_region(hose->regions + 0,
+ CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
+ CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
+ CFG_PCIE_MEMSIZE,
+ PCI_REGION_MEM);
+ hose->region_count = 1;
+ pci_register_hose(hose);
+
+ if (is_end_point(i)) {
+ ppc4xx_setup_pcie_endpoint(hose, i);
+ /*
+ * Reson for no scanning is endpoint can not generate
+ * upstream configuration accesses.
+ */
+ } else {
+ ppc4xx_setup_pcie_rootpoint(hose, i);
+ env = getenv ("pciscandelay");
+ if (env != NULL) {
+ delay = simple_strtoul(env, NULL, 10);
+ if (delay > 5)
+ printf("Warning, expect noticable delay before "
+ "PCIe scan due to 'pciscandelay' value!\n");
+ mdelay(delay * 1000);
+ }
+
+ /*
+ * Config access can only go down stream
+ */
+ hose->last_busno = pci_hose_scan(hose);
+ bus = hose->last_busno + 1;
+ }
+ }
+}
+#endif
+
+#if defined(CONFIG_POST)
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+ return 0; /* No hotkeys supported */
+}
+#endif /* CONFIG_POST */
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ u32 val[4];
+ int rc;
+
+ ft_cpu_setup(blob, bd);
+
+ /* Fixup NOR mapping */
+ val[0] = 0; /* chip select number */
+ val[1] = 0; /* always 0 */
+ val[2] = gd->bd->bi_flashstart;
+ val[3] = gd->bd->bi_flashsize;
+ rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
+ val, sizeof(val), 1);
+ if (rc)
+ printf("Unable to update property NOR mapping, err=%s\n",
+ fdt_strerror(rc));
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+void sdram_init(void)
+{
+ return;
+}
+
+long int initdram(int board_type)
+{
+ /*
+ * Same as on Kilauea, Makalu generates exception 0x200
+ * (machine check) after trap_init() in board_init_f,
+ * when SDRAM is initialized here (late) and d-cache is
+ * used earlier as INIT_RAM.
+ * So for now, initialize DDR2 in init.S very early and
+ * also use it for INIT_RAM. Then this exception doesn't
+ * occur.
+ */
+#if 0
+ u32 val;
+
+ /* base=00000000, size=128MByte (5), mode=2 (n*10*4) */
+ mtsdram(SDRAM_MB0CF, 0x00005201);
+
+ /* SET SDRAM_MB1CF - Not enabled */
+ mtsdram(SDRAM_MB1CF, 0x00000000);
+
+ /* SET SDRAM_MB2CF - Not enabled */
+ mtsdram(SDRAM_MB2CF, 0x00000000);
+
+ /* SET SDRAM_MB3CF - Not enabled */
+ mtsdram(SDRAM_MB3CF, 0x00000000);
+
+ /* SDRAM_CLKTR: Adv Addr clock by 90 deg */
+ mtsdram(SDRAM_CLKTR, 0x80000000);
+
+ /* Refresh Time register (0x30) Refresh every 7.8125uS */
+ mtsdram(SDRAM_RTR, 0x06180000);
+
+ /* SDRAM_SDTR1 */
+ mtsdram(SDRAM_SDTR1, 0x80201000);
+
+ /* SDRAM_SDTR2 */
+ mtsdram(SDRAM_SDTR2, 0x32204232);
+
+ /* SDRAM_SDTR3 */
+ mtsdram(SDRAM_SDTR3, 0x080b0d1a);
+
+ mtsdram(SDRAM_MMODE, 0x00000442);
+ mtsdram(SDRAM_MEMODE, 0x00000404);
+
+ /* SDRAM0_MCOPT1 (0X20) No ECC Gen */
+ mtsdram(SDRAM_MCOPT1, 0x04322000);
+
+ /* NOP */
+ mtsdram(SDRAM_INITPLR0, 0xa8380000);
+ /* precharge 3 DDR clock cycle */
+ mtsdram(SDRAM_INITPLR1, 0x81900400);
+ /* EMR2 twr = 2tck */
+ mtsdram(SDRAM_INITPLR2, 0x81020000);
+ /* EMR3 twr = 2tck */
+ mtsdram(SDRAM_INITPLR3, 0x81030000);
+ /* EMR DLL ENABLE twr = 2tck */
+ mtsdram(SDRAM_INITPLR4, 0x81010404);
+ /* MR w/ DLL reset
+ * Note: 5 is CL. May need to be changed
+ */
+ mtsdram(SDRAM_INITPLR5, 0x81000542);
+ /* precharge 3 DDR clock cycle */
+ mtsdram(SDRAM_INITPLR6, 0x81900400);
+ /* Auto-refresh trfc = 26tck */
+ mtsdram(SDRAM_INITPLR7, 0x8D080000);
+ /* Auto-refresh trfc = 26tck */
+ mtsdram(SDRAM_INITPLR8, 0x8D080000);
+ /* Auto-refresh */
+ mtsdram(SDRAM_INITPLR9, 0x8D080000);
+ /* Auto-refresh */
+ mtsdram(SDRAM_INITPLR10, 0x8D080000);
+ /* MRS - normal operation; wait 2 cycle (set wait to tMRD) */
+ mtsdram(SDRAM_INITPLR11, 0x81000442);
+ mtsdram(SDRAM_INITPLR12, 0x81010780);
+ mtsdram(SDRAM_INITPLR13, 0x81010400);
+ mtsdram(SDRAM_INITPLR14, 0x00000000);
+ mtsdram(SDRAM_INITPLR15, 0x00000000);
+
+ /* SET MCIF0_CODT Die Termination On */
+ mtsdram(SDRAM_CODT, 0x0080f837);
+ mtsdram(SDRAM_MODT0, 0x01800000);
+ mtsdram(SDRAM_MODT1, 0x00000000);
+
+ mtsdram(SDRAM_WRDTR, 0x00000000);
+
+ /* SDRAM0_MCOPT2 (0X21) Start initialization */
+ mtsdram(SDRAM_MCOPT2, 0x20000000);
+
+ /* Step 5 */
+ do {
+ mfsdram(SDRAM_MCSTAT, val);
+ } while ((val & SDRAM_MCSTAT_MIC_COMP) != SDRAM_MCSTAT_MIC_COMP);
+
+ /* Step 6 */
+
+ /* SDRAM_DLCR */
+ mtsdram(SDRAM_DLCR, 0x030000a5);
+
+ /* SDRAM_RDCC */
+ mtsdram(SDRAM_RDCC, 0x40000000);
+
+ /* SDRAM_RQDC */
+ mtsdram(SDRAM_RQDC, 0x80000038);
+
+ /* SDRAM_RFDC */
+ mtsdram(SDRAM_RFDC, 0x00000209);
+
+ /* Enable memory controller */
+ mfsdram(SDRAM_MCOPT2, val);
+ val |= SDRAM_MCOPT2_DCEN_ENABLE;
+ mtsdram(SDRAM_MCOPT2, val);
+#endif
+ return (CFG_MBYTES_SDRAM << 20);
+}
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+ printf ("testdram\n");
+#if defined (CONFIG_NAND_U_BOOT)
+ return 0;
+#endif
+ uint *pstart = (uint *) 0x00000000;
+ uint *pend = (uint *) 0x00001000;
+ uint *p;
+
+ for (p = pstart; p < pend; p++) {
+ *p = 0xaaaaaaaa;
+ }
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+#if !defined (CONFIG_NAND_SPL)
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+#endif
+ return 1;
+ }
+ }
+
+ for (p = pstart; p < pend; p++) {
+ *p = 0x55555555;
+ }
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+#if !defined (CONFIG_NAND_SPL)
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+#endif
+ return 1;
+ }
+ }
+#if !defined (CONFIG_NAND_SPL)
+ printf ("SDRAM test passed!!!\n");
+#endif
+ return 0;
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+/* To compile successfully, uncomment the following section.
+ * To go in ram, remove the section.
+ * Added by SunHe.
+ */
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/ppc4xx/start.o (.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
cpu/ppc4xx/start.o (.text)
board/amcc/ocotea/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
-/* . = env_offset;*/
-/* common/environment.o(.text)*/
*(.text)
*(.fixup)
*/
#include <ppc_asm.tmpl>
+#include <asm-ppc/mmu.h>
#include <config.h>
-/* General */
-#define TLB_VALID 0x00000200
-#define _256M 0x10000000
-
-/* Supported page sizes */
-
-#define SZ_1K 0x00000000
-#define SZ_4K 0x00000010
-#define SZ_16K 0x00000020
-#define SZ_64K 0x00000030
-#define SZ_256K 0x00000040
-#define SZ_1M 0x00000050
-#define SZ_8M 0x00000060
-#define SZ_16M 0x00000070
-#define SZ_256M 0x00000090
-
-/* Storage attributes */
-#define SA_W 0x00000800 /* Write-through */
-#define SA_I 0x00000400 /* Caching inhibited */
-#define SA_M 0x00000200 /* Memory coherence */
-#define SA_G 0x00000100 /* Guarded */
-#define SA_E 0x00000080 /* Endian */
-
-/* Access control */
-#define AC_X 0x00000024 /* Execute */
-#define AC_W 0x00000012 /* Write */
-#define AC_R 0x00000009 /* Read */
-
-/* Some handy macros */
-
-#define EPN(e) ((e) & 0xfffffc00)
-#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
-#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
-#define TLB2(a) ( (a)&0x00000fbf )
-
-#define tlbtab_start\
- mflr r1 ;\
- bl 0f ;
-
-#define tlbtab_end\
- .long 0, 0, 0 ; \
-0: mflr r0 ; \
- mtlr r1 ; \
- blr ;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
- .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-
-
/**************************************************************************
* TLB TABLE
*
#endif
/* TLB-entry for DDR SDRAM (Up to 2GB) */
+#ifdef CONFIG_4xx_DCACHE
+ tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G)
+#else
tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+#endif
#ifdef CFG_INIT_RAM_DCACHE
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
#define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
#define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
#define DDR0_26_TREF_MASK 0x00003FFF
-#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
-#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
+#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0)
+#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF)
#define DDR0_27 0x1B
#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000
*/
#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <ppc440.h>
#include <asm/processor.h>
#include <asm/io.h>
-#include <ppc440.h>
DECLARE_GLOBAL_DATA_PTR;
* Setup the GPIO pins
*-------------------------------------------------------------------*/
/* test-only: take GPIO init from pcs440ep ???? in config file */
- out32(GPIO0_OR, 0x00000000);
- out32(GPIO0_TCR, 0x0000000f);
- out32(GPIO0_OSRL, 0x50015400);
- out32(GPIO0_OSRH, 0x550050aa);
- out32(GPIO0_TSRL, 0x50015400);
- out32(GPIO0_TSRH, 0x55005000);
- out32(GPIO0_ISR1L, 0x50000000);
- out32(GPIO0_ISR1H, 0x00000000);
- out32(GPIO0_ISR2L, 0x00000000);
- out32(GPIO0_ISR2H, 0x00000100);
- out32(GPIO0_ISR3L, 0x00000000);
- out32(GPIO0_ISR3H, 0x00000000);
-
- out32(GPIO1_OR, 0x00000000);
- out32(GPIO1_TCR, 0xc2000000);
- out32(GPIO1_OSRL, 0x5c280000);
- out32(GPIO1_OSRH, 0x00000000);
- out32(GPIO1_TSRL, 0x0c000000);
- out32(GPIO1_TSRH, 0x00000000);
- out32(GPIO1_ISR1L, 0x00005550);
- out32(GPIO1_ISR1H, 0x00000000);
- out32(GPIO1_ISR2L, 0x00050000);
- out32(GPIO1_ISR2H, 0x00000000);
- out32(GPIO1_ISR3L, 0x01400000);
- out32(GPIO1_ISR3H, 0x00000000);
+ out_be32((u32 *) GPIO0_OR, 0x00000000);
+ out_be32((u32 *) GPIO0_TCR, 0x0000000f);
+ out_be32((u32 *) GPIO0_OSRL, 0x50015400);
+ out_be32((u32 *) GPIO0_OSRH, 0x550050aa);
+ out_be32((u32 *) GPIO0_TSRL, 0x50015400);
+ out_be32((u32 *) GPIO0_TSRH, 0x55005000);
+ out_be32((u32 *) GPIO0_ISR1L, 0x50000000);
+ out_be32((u32 *) GPIO0_ISR1H, 0x00000000);
+ out_be32((u32 *) GPIO0_ISR2L, 0x00000000);
+ out_be32((u32 *) GPIO0_ISR2H, 0x00000100);
+ out_be32((u32 *) GPIO0_ISR3L, 0x00000000);
+ out_be32((u32 *) GPIO0_ISR3H, 0x00000000);
+
+ out_be32((u32 *) GPIO1_OR, 0x00000000);
+ out_be32((u32 *) GPIO1_TCR, 0xc2000000);
+ out_be32((u32 *) GPIO1_OSRL, 0x5c280000);
+ out_be32((u32 *) GPIO1_OSRH, 0x00000000);
+ out_be32((u32 *) GPIO1_TSRL, 0x0c000000);
+ out_be32((u32 *) GPIO1_TSRH, 0x00000000);
+ out_be32((u32 *) GPIO1_ISR1L, 0x00005550);
+ out_be32((u32 *) GPIO1_ISR1H, 0x00000000);
+ out_be32((u32 *) GPIO1_ISR2L, 0x00050000);
+ out_be32((u32 *) GPIO1_ISR2H, 0x00000000);
+ out_be32((u32 *) GPIO1_ISR3L, 0x01400000);
+ out_be32((u32 *) GPIO1_ISR3H, 0x00000000);
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
mtdcr(uic2sr, 0xffffffff); /* clear all */
/* 50MHz tmrclk */
- *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
+ out_8((u8 *) CFG_BCSR_BASE + 0x04, 0x00);
/* clear write protects */
- *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00;
+ out_8((u8 *) CFG_BCSR_BASE + 0x07, 0x00);
/* enable Ethernet */
- *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0x00;
+ out_8((u8 *) CFG_BCSR_BASE + 0x08, 0x00);
/* enable USB device */
- *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x20;
+ out_8((u8 *) CFG_BCSR_BASE + 0x09, 0x20);
/* select Ethernet pins */
mfsdr(SDR0_PFC1, sdr0_pfc1);
return 0; /* No hotkeys supported */
}
#endif /* CONFIG_POST */
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ u32 val[4];
+ int rc;
+
+ ft_cpu_setup(blob, bd);
+
+ /* Fixup NOR mapping */
+ val[0] = 0; /* chip select number */
+ val[1] = 0; /* always 0 */
+ val[2] = gd->bd->bi_flashstart;
+ val[3] = gd->bd->bi_flashsize;
+ rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
+ val, sizeof(val), 1);
+ if (rc)
+ printf("Unable to update property NOR mapping, err=%s\n",
+ fdt_strerror(rc));
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
-/* . = env_offset;*/
-/* common/environment.o(.text)*/
*(.text)
*(.fixup)
/* read clock regsiter */
printf("===== Display reset and initialize register Start =========\n");
- mfclk(clk_pllc,reg);
+ mfcpr(clk_pllc,reg);
printf("cpr_pllc = %#010x\n",reg);
- mfclk(clk_plld,reg);
+ mfcpr(clk_plld,reg);
printf("cpr_plld = %#010x\n",reg);
- mfclk(clk_primad,reg);
+ mfcpr(clk_primad,reg);
printf("cpr_primad = %#010x\n",reg);
- mfclk(clk_primbd,reg);
+ mfcpr(clk_primbd,reg);
printf("cpr_primbd = %#010x\n",reg);
- mfclk(clk_opbd,reg);
+ mfcpr(clk_opbd,reg);
printf("cpr_opbd = %#010x\n",reg);
- mfclk(clk_perd,reg);
+ mfcpr(clk_perd,reg);
printf("cpr_perd = %#010x\n",reg);
- mfclk(clk_mald,reg);
+ mfcpr(clk_mald,reg);
printf("cpr_mald = %#010x\n",reg);
/* read sdr register */
cpu/ppc4xx/start.o (.text)
board/amcc/taishan/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
-/* . = env_offset;*/
-/* common/environment.o(.text)*/
*(.text)
*(.fixup)
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
-/* . = env_offset;*/
-/* common/environment.o(.text)*/
*(.text)
*(.fixup)
cpu/ppc4xx/start.o (.text)
board/amcc/yosemite/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
-/* . = env_offset;*/
-/* common/environment.o(.text)*/
*(.text)
*(.fixup)
cpu/ppc4xx/start.o (.text)
board/amcc/yucca/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
-/* . = env_offset;*/
-/* common/environment.o(.text)*/
*(.text)
*(.fixup)
+++ /dev/null
-/*
- * (C) Copyright 2002-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
- board/amcc/yucca/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
-/* common/environment.o(.text) */
-
- *(.text)
- *(.fixup)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- _end = . ;
- PROVIDE (end = .);
-}
#include <common.h>
#include <ppc4xx.h>
-#include <asm/processor.h>
#include <i2c.h>
-#include <asm-ppc/io.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/4xx_pcie.h>
#include "yucca.h"
-#include "../cpu/ppc4xx/440spe_pcie.h"
DECLARE_GLOBAL_DATA_PTR;
-#undef PCIE_ENDPOINT
-/* #define PCIE_ENDPOINT 1 */
-
void fpga_init (void);
-void get_sys_info(PPC440_SYS_INFO *board_cfg );
-int compare_to_true(char *str );
-char *remove_l_w_space(char *in_str );
-char *remove_t_w_space(char *in_str );
-int get_console_port(void);
-
-int ppc440spe_init_pcie_rootport(int port);
-void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
-
#define DEBUG_ENV
#ifdef DEBUG_ENV
#define DEBUGF(fmt,args...) printf(fmt ,##args)
mtdcr (uic0sr, 0x00000000); /* clear all interrupts */
mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */
- /* SDR0_MFR should be part of Ethernet init */
- mfsdr (sdr_mfr, mfr);
- mfr &= ~SDR0_MFR_ECS_MASK;
- /*mtsdr(sdr_mfr, mfr);*/
+ mfsdr(sdr_mfr, mfr);
+ mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
+ mtsdr(sdr_mfr, mfr);
+
fpga_init();
return 0;
{
struct pci_controller *hose;
int i, bus;
+ int ret = 0;
char *env;
unsigned int delay;
if (!yucca_pcie_card_present(i))
continue;
-#ifdef PCIE_ENDPOINT
- yucca_setup_pcie_fpga_endpoint(i);
- if (ppc440spe_init_pcie_endport(i)) {
-#else
- yucca_setup_pcie_fpga_rootpoint(i);
- if (ppc440spe_init_pcie_rootport(i)) {
-#endif
- printf("PCIE%d: initialization failed\n", i);
+ if (is_end_point(i)) {
+ yucca_setup_pcie_fpga_endpoint(i);
+ ret = ppc4xx_init_pcie_endport(i);
+ } else {
+ yucca_setup_pcie_fpga_rootpoint(i);
+ ret = ppc4xx_init_pcie_rootport(i);
+ }
+ if (ret) {
+ printf("PCIE%d: initialization as %s failed\n", i,
+ is_end_point(i) ? "endpoint" : "root-complex");
continue;
}
CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
CFG_PCIE_MEMSIZE,
- PCI_REGION_MEM
- );
+ PCI_REGION_MEM);
hose->region_count = 1;
pci_register_hose(hose);
-#ifdef PCIE_ENDPOINT
- ppc440spe_setup_pcie_endpoint(hose, i);
- /*
- * Reson for no scanning is endpoint can not generate
- * upstream configuration accesses.
- */
-#else
- ppc440spe_setup_pcie_rootpoint(hose, i);
-
- env = getenv ("pciscandelay");
- if (env != NULL) {
- delay = simple_strtoul (env, NULL, 10);
- if (delay > 5)
- printf ("Warning, expect noticable delay before PCIe"
- "scan due to 'pciscandelay' value!\n");
- mdelay (delay * 1000);
- }
+ if (is_end_point(i)) {
+ ppc4xx_setup_pcie_endpoint(hose, i);
+ /*
+ * Reson for no scanning is endpoint can not generate
+ * upstream configuration accesses.
+ */
+ } else {
+ ppc4xx_setup_pcie_rootpoint(hose, i);
+ env = getenv("pciscandelay");
+ if (env != NULL) {
+ delay = simple_strtoul(env, NULL, 10);
+ if (delay > 5)
+ printf("Warning, expect noticable delay before "
+ "PCIe scan due to 'pciscandelay' value!\n");
+ mdelay(delay * 1000);
+ }
- /*
- * Config access can only go down stream
- */
- hose->last_busno = pci_hose_scan(hose);
- bus = hose->last_busno + 1;
-#endif
+ /*
+ * Config access can only go down stream
+ */
+ hose->last_busno = pci_hose_scan(hose);
+ bus = hose->last_busno + 1;
+ }
}
}
#endif /* defined(CONFIG_PCI) */
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
+++ /dev/null
-/*
- * Copyright 2004 Freescale Semiconductor.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <common.h>
-
-
-/*
- * CADMUS Board System Registers
- */
-#ifndef CFG_CADMUS_BASE_REG
-#define CFG_CADMUS_BASE_REG (CADMUS_BASE_ADDR + 0x4000)
-#endif
-
-typedef struct cadmus_reg {
- u_char cm_ver; /* Board version */
- u_char cm_csr; /* General control/status */
- u_char cm_rst; /* Reset control */
- u_char cm_hsclk; /* High speed clock */
- u_char cm_hsxclk; /* High speed clock extended */
- u_char cm_led; /* LED data */
- u_char cm_pci; /* PCI control/status */
- u_char cm_dma; /* DMA control */
- u_char cm_reserved[248]; /* Total 256 bytes */
-} cadmus_reg_t;
-
-
-unsigned int
-get_board_version(void)
-{
- volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG;
-
- return cadmus->cm_ver;
-}
-
-
-unsigned long
-get_clock_freq(void)
-{
- volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG;
-
- uint pci1_speed = (cadmus->cm_pci >> 2) & 0x3; /* PSPEED in [4:5] */
-
- if (pci1_speed == 0) {
- return 33000000;
- } else if (pci1_speed == 1) {
- return 66000000;
- } else {
- /* Really, unknown. Be safe? */
- return 33000000;
- }
-}
-
-
-unsigned int
-get_pci_slot(void)
-{
- volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG;
-
- /*
- * PCI slot in USER bits CSR[6:7] by convention.
- */
- return ((cadmus->cm_csr >> 6) & 0x3) + 1;
-}
-
-
-unsigned int
-get_pci_dual(void)
-{
- volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG;
-
- /*
- * PCI DUAL in CM_PCI[3]
- */
- return cadmus->cm_pci & 0x10;
-}
+++ /dev/null
-/*
- * Copyright 2004 Freescale Semiconductor.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CADMUS_H_
-#define __CADMUS_H_
-
-
-/*
- * CADMUS Board System Register interface.
- */
-
-/*
- * Returns board version register.
- */
-extern unsigned int get_board_version(void);
-
-/*
- * Returns either 33000000 or 66000000 as the SYS_CLK_FREQ.
- */
-extern unsigned long get_clock_freq(void);
-
-
-/*
- * Returns 1 - 4, as found in the USER CSR[6:7] bits.
- */
-extern unsigned int get_pci_slot(void);
-
-
-/*
- * Returns PCI DUAL as found in CM_PCI[3].
- */
-extern unsigned int get_pci_dual(void);
-
-
-#endif /* __CADMUS_H_ */
+++ /dev/null
-/*
- * Copyright 2004 Freescale Semiconductor.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <common.h>
-#include <i2c.h>
-
-#include "eeprom.h"
-
-
-typedef struct {
- char idee_pcbid[4]; /* "CCID" for CDC v1.X */
- u8 idee_major;
- u8 idee_minor;
- char idee_serial[10];
- char idee_errata[2];
- char idee_date[8]; /* yyyymmdd */
- /* The rest of the EEPROM space is reserved */
-} id_eeprom_t;
-
-
-unsigned int
-get_cpu_board_revision(void)
-{
- uint major = 0;
- uint minor = 0;
-
- id_eeprom_t id_eeprom;
-
- i2c_read(CFG_I2C_EEPROM_ADDR, 0, 2,
- (uchar *) &id_eeprom, sizeof(id_eeprom));
-
- major = id_eeprom.idee_major;
- minor = id_eeprom.idee_minor;
-
- if (major == 0xff && minor == 0xff) {
- major = minor = 0;
- }
-
- return MPC85XX_CPU_BOARD_REV(major,minor);
-}
+++ /dev/null
-/*
- * Copyright 2004 Freescale Semiconductor.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __EEPROM_H_
-#define __EEPROM_H_
-
-
-/*
- * EEPROM Board System Register interface.
- */
-
-
-/*
- * CPU Board Revision
- */
-#define MPC85XX_CPU_BOARD_REV(maj, min) ((((maj)&0xff) << 8) | ((min) & 0xff))
-#define MPC85XX_CPU_BOARD_MAJOR(rev) (((rev) >> 8) & 0xff)
-#define MPC85XX_CPU_BOARD_MINOR(rev) ((rev) & 0xff)
-
-#define MPC85XX_CPU_BOARD_REV_UNKNOWN MPC85XX_CPU_BOARD_REV(0,0)
-#define MPC85XX_CPU_BOARD_REV_1_0 MPC85XX_CPU_BOARD_REV(1,0)
-#define MPC85XX_CPU_BOARD_REV_1_1 MPC85XX_CPU_BOARD_REV(1,1)
-
-/*
- * Returns CPU board revision register as a 16-bit value with
- * the Major in the high byte, and Minor in the low byte.
- */
-extern unsigned int get_cpu_board_revision(void);
-
-
-#endif /* __CADMUS_H_ */
+++ /dev/null
-/*
- * Copyright 2004 Freescale Semiconductor.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#include "cadmus.h"
-
-extern void ft_cpu_setup(void *blob, bd_t *bd);
-
-static void cds_pci_fixup(void *blob)
-{
- int len;
- u32 *map;
- int slot;
- int i;
-
- map = ft_get_prop(blob, "/" OF_SOC "/pci@8000/interrupt-map", &len);
-
- if (!map)
- map = ft_get_prop(blob, "/" OF_PCI "/interrupt-map", &len);
-
- if (map) {
- len /= sizeof(u32);
-
- slot = get_pci_slot();
-
- for (i=0;i<len;i+=7) {
- /* We rotate the interrupt pins so that the mapping
- * changes depending on the slot the carrier card is in.
- */
- map[3] = ((map[3] + slot - 2) % 4) + 1;
-
- map+=7;
- }
- } else {
- printf("*** Warning - No PCI node found\n");
- }
-}
-#endif
-
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
-{
- u32 *p;
- int len;
-
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
-#endif
- ft_cpu_setup(blob, bd);
-
- p = ft_get_prop(blob, "/memory/reg", &len);
- if (p != NULL) {
- *p++ = cpu_to_be32(bd->bi_memstart);
- *p = cpu_to_be32(bd->bi_memsize);
- }
-
- cds_pci_fixup(blob);
-}
-#endif
+++ /dev/null
-/*
- * Copyright 2006 Freescale Semiconductor.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <pci.h>
-
-/* Config the VIA chip */
-void mpc85xx_config_via(struct pci_controller *hose,
- pci_dev_t dev, struct pci_config_table *tab)
-{
- pci_dev_t bridge;
- unsigned int cmdstat;
-
- /* Enable USB and IDE functions */
- pci_hose_write_config_byte(hose, dev, 0x48, 0x08);
-
- pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
- cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY| PCI_COMMAND_MASTER;
- pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
- pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
- pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
-
- /*
- * Force the backplane P2P bridge to have a window
- * open from 0x00000000-0x00001fff in PCI I/O space.
- * This allows legacy I/O (i8259, etc) on the VIA
- * southbridge to be accessed.
- */
- bridge = PCI_BDF(0,BRIDGE_ID,0);
- pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0);
- pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0);
- pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10);
- pci_hose_write_config_word(hose, bridge, PCI_IO_LIMIT_UPPER16, 0);
-}
-
-/* Function 1, IDE */
-void mpc85xx_config_via_usbide(struct pci_controller *hose,
- pci_dev_t dev, struct pci_config_table *tab)
-{
- pciauto_config_device(hose, dev);
- /*
- * Since the P2P window was forced to cover the fixed
- * legacy I/O addresses, it is necessary to manually
- * place the base addresses for the IDE and USB functions
- * within this window.
- */
- pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1ff8);
- pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1ff4);
- pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1fe8);
- pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_3, 0x1fe4);
- pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fd0);
-}
-
-/* Function 2, USB ports 0-1 */
-void mpc85xx_config_via_usb(struct pci_controller *hose,
- pci_dev_t dev, struct pci_config_table *tab)
-{
- pciauto_config_device(hose, dev);
-
- pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fa0);
-}
-
-/* Function 3, USB ports 2-3 */
-void mpc85xx_config_via_usb2(struct pci_controller *hose,
- pci_dev_t dev, struct pci_config_table *tab)
-{
- pciauto_config_device(hose, dev);
-
- pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1f80);
-}
-
-/* Function 5, Power Management */
-void mpc85xx_config_via_power(struct pci_controller *hose,
- pci_dev_t dev, struct pci_config_table *tab)
-{
- pciauto_config_device(hose, dev);
-
- pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1e00);
- pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1dfc);
- pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1df8);
-}
-
-/* Function 6, AC97 Interface */
-void mpc85xx_config_via_ac97(struct pci_controller *hose,
- pci_dev_t dev, struct pci_config_table *tab)
-{
- pciauto_config_device(hose, dev);
-
- pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1c00);
-}
+++ /dev/null
-#ifndef _MPC85xx_VIA_H
-void mpc85xx_config_via(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
-
-/* Function 1, IDE */
-void mpc85xx_config_via_usbide(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
-
-/* Function 2, USB ports 0-1 */
-void mpc85xx_config_via_usb(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
-
-/* Function 3, USB ports 2-3 */
-void mpc85xx_config_via_usb2(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
-
-/* Function 5, Power Management */
-void mpc85xx_config_via_power(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
-
-/* Function 6, AC97 Interface */
-void mpc85xx_config_via_ac97(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
-#endif /* _MPC85xx_VIA_H */
+++ /dev/null
-#
-# Copyright 2004 Freescale Semiconductor.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB = $(obj)lib$(BOARD).a
-
-COBJS := $(BOARD).o \
- ../common/cadmus.o \
- ../common/eeprom.o \
- ../common/ft_board.o \
- ../common/via.o
-
-SOBJS := init.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
-
-clean:
- rm -f $(OBJS) $(SOBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-#
-# Copyright 2004 Freescale Semiconductor.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# mpc8541cds board
-#
-TEXT_BASE = 0xfff80000
-
-PLATFORM_CPPFLAGS += -DCONFIG_E500=1
-PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
-PLATFORM_CPPFLAGS += -DCONFIG_MPC8541=1
+++ /dev/null
-/*
- * Copyright 2004 Freescale Semiconductor.
- * Copyright 2002,2003, Motorola Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-#include <asm/cache.h>
-#include <asm/mmu.h>
-#include <config.h>
-#include <mpc85xx.h>
-
-
-/*
- * TLB0 and TLB1 Entries
- *
- * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
- * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
- * these TLB entries are established.
- *
- * The TLB entries for DDR are dynamically setup in spd_sdram()
- * and use TLB1 Entries 8 through 15 as needed according to the
- * size of DDR memory.
- *
- * MAS0: tlbsel, esel, nv
- * MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, sharen, x0, x1, w, i, m, g, e
- * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
- */
-
-#define entry_start \
- mflr r1 ; \
- bl 0f ;
-
-#define entry_end \
-0: mflr r0 ; \
- mtlr r1 ; \
- blr ;
-
-
- .section .bootpg, "ax"
- .globl tlb1_entry
-tlb1_entry:
- entry_start
-
- /*
- * Number of TLB0 and TLB1 entries in the following table
- */
- .long 13
-
-#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
- /*
- * TLB0 4K Non-cacheable, guarded
- * 0xff700000 4K Initial CCSRBAR mapping
- *
- * This ends up at a TLB0 Index==0 entry, and must not collide
- * with other TLB0 Entries.
- */
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
-#else
-#error("Update the number of table entries in tlb1_entry")
-#endif
-
- /*
- * TLB0 16K Cacheable, non-guarded
- * 0xd001_0000 16K Temporary Global data for initialization
- *
- * Use four 4K TLB0 entries. These entries must be cacheable
- * as they provide the bootstrap memory before the memory
- * controler and real memory have been configured.
- *
- * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
- * and must not collide with other TLB0 entries.
- */
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
-
- /*
- * TLB 0: 16M Non-cacheable, guarded
- * 0xff000000 16M FLASH
- * Out of reset this entry is only 4K.
- */
- .long TLB1_MAS0(1, 0, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 1: 256M Non-cacheable, guarded
- * 0x80000000 256M PCI1 MEM First half
- */
- .long TLB1_MAS0(1, 1, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 2: 256M Non-cacheable, guarded
- * 0x90000000 256M PCI1 MEM Second half
- */
- .long TLB1_MAS0(1, 2, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
- 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
- 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 3: 256M Non-cacheable, guarded
- * 0xa0000000 256M PCI2 MEM First half
- */
- .long TLB1_MAS0(1, 3, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 4: 256M Non-cacheable, guarded
- * 0xb0000000 256M PCI2 MEM Second half
- */
- .long TLB1_MAS0(1, 4, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000),
- 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000),
- 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 5: 64M Non-cacheable, guarded
- * 0xe000_0000 1M CCSRBAR
- * 0xe200_0000 16M PCI1 IO
- * 0xe300_0000 16M PCI2 IO
- */
- .long TLB1_MAS0(1, 5, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 6: 64M Cacheable, non-guarded
- * 0xf000_0000 64M LBC SDRAM
- */
- .long TLB1_MAS0(1, 6, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 7: 1M Non-cacheable, guarded
- * 0xf8000000 1M CADMUS registers
- */
- .long TLB1_MAS0(1, 7, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
- .long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1)
-
- entry_end
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000 0x7fff_ffff DDR 2G
- * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
- * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
- * 0xe000_0000 0xe000_ffff CCSR 1M
- * 0xe200_0000 0xe20f_ffff PCI1 IO 1M
- * 0xe210_0000 0xe21f_ffff PCI2 IO 1M
- * 0xf000_0000 0xf7ff_ffff SDRAM 128M
- * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
- * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
- * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
- *
- * Notes:
- * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- * If flash is 8M at default position (last 8M), no LAW needed.
- *
- * The defines below are 1-off of the actual LAWAR0 usage.
- * So LAWAR3 define uses the LAWAR4 register in the ECM.
- */
-
-#define LAWBAR0 0
-#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
-
-#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
-#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
-#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
-#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
-
-#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff)
-#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
-
-/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
-#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
-#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
-
- .section .bootpg, "ax"
- .globl law_entry
-
-law_entry:
- entry_start
- .long 6
- .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
- .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5
- entry_end
+++ /dev/null
-/*
- * Copyright 2004 Freescale Semiconductor.
- *
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/immap_85xx.h>
-#include <ioports.h>
-#include <spd.h>
-
-#include "../common/cadmus.h"
-#include "../common/eeprom.h"
-#include "../common/via.h"
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
-extern long int spd_sdram(void);
-
-void local_bus_init(void);
-void sdram_init(void);
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
- /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
- /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
- /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
- /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
- /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
- /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
- /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
- /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
- /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
- /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
- /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
- /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
- /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
- /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
- /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
- /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
- /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
- /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
- /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
- /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
- /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
- /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
- /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
- /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
- /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
- /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
- /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
- /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
- /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
- /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
- /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
- },
-
- /* Port B configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
- /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
- /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
- /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
- /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
- /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
- /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
- /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
- /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
- /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
- /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
- /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
- /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
- /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
- /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
- /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
- /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
- /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
- /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
- /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
- /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
- /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
- /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
- /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
- /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
- /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
- /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
- /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
- /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
- /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
- /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
- /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
- /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
- /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
- /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
- /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
- /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
- /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
- /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
- /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
- /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
- /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
- /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
- /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
- /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
- /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
- /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
- /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
- /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
- /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
- /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
- /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
- /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
- /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
- /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
- /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
- /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- }
-};
-
-int board_early_init_f (void)
-{
- return 0;
-}
-
-int checkboard (void)
-{
- volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
-
- /* PCI slot in USER bits CSR[6:7] by convention. */
- uint pci_slot = get_pci_slot ();
-
- uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
- uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
- uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
- uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
-
- uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
-
- uint cpu_board_rev = get_cpu_board_revision ();
-
- printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
- get_board_version (), pci_slot);
-
- printf ("CPU Board Revision %d.%d (0x%04x)\n",
- MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
- MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
-
- printf (" PCI1: %d bit, %s MHz, %s\n",
- (pci1_32) ? 32 : 64,
- (pci1_speed == 33000000) ? "33" :
- (pci1_speed == 66000000) ? "66" : "unknown",
- pci1_clk_sel ? "sync" : "async");
-
- if (pci_dual) {
- printf (" PCI2: 32 bit, 66 MHz, %s\n",
- pci2_clk_sel ? "sync" : "async");
- } else {
- printf (" PCI2: disabled\n");
- }
-
- /*
- * Initialize local bus.
- */
- local_bus_init ();
-
- return 0;
-}
-
-long int
-initdram(int board_type)
-{
- long dram_size = 0;
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
-
- puts("Initializing\n");
-
-#if defined(CONFIG_DDR_DLL)
- {
- /*
- * Work around to stabilize DDR DLL MSYNC_IN.
- * Errata DDR9 seems to have been fixed.
- * This is now the workaround for Errata DDR11:
- * Override DLL = 1, Course Adj = 1, Tap Select = 0
- */
-
- volatile ccsr_gur_t *gur= &immap->im_gur;
-
- gur->ddrdllcr = 0x81000000;
- asm("sync;isync;msync");
- udelay(200);
- }
-#endif
- dram_size = spd_sdram();
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(dram_size);
-#endif
- /*
- * SDRAM Initialization
- */
- sdram_init();
-
- puts(" DDR: ");
- return dram_size;
-}
-
-/*
- * Initialize Local Bus
- */
-void
-local_bus_init(void)
-{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
- volatile ccsr_lbc_t *lbc = &immap->im_lbc;
-
- uint clkdiv;
- uint lbc_hz;
- sys_info_t sysinfo;
- uint temp_lbcdll;
-
- /*
- * Errata LBC11.
- * Fix Local Bus clock glitch when DLL is enabled.
- *
- * If localbus freq is < 66Mhz, DLL bypass mode must be used.
- * If localbus freq is > 133Mhz, DLL can be safely enabled.
- * Between 66 and 133, the DLL is enabled with an override workaround.
- */
-
- get_sys_info(&sysinfo);
- clkdiv = lbc->lcrr & 0x0f;
- lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
-
- if (lbc_hz < 66) {
- lbc->lcrr |= 0x80000000; /* DLL Bypass */
-
- } else if (lbc_hz >= 133) {
- lbc->lcrr &= (~0x80000000); /* DLL Enabled */
-
- } else {
- lbc->lcrr &= (~0x8000000); /* DLL Enabled */
- udelay(200);
-
- /*
- * Sample LBC DLL ctrl reg, upshift it to set the
- * override bits.
- */
- temp_lbcdll = gur->lbcdllcr;
- gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
- asm("sync;isync;msync");
- }
-}
-
-/*
- * Initialize SDRAM memory on the Local Bus.
- */
-void
-sdram_init(void)
-{
-#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
-
- uint idx;
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_lbc_t *lbc = &immap->im_lbc;
- uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
- uint cpu_board_rev;
- uint lsdmr_common;
-
- puts(" SDRAM: ");
-
- print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
-
- /*
- * Setup SDRAM Base and Option Registers
- */
- lbc->or2 = CFG_OR2_PRELIM;
- asm("msync");
-
- lbc->br2 = CFG_BR2_PRELIM;
- asm("msync");
-
- lbc->lbcr = CFG_LBC_LBCR;
- asm("msync");
-
-
- lbc->lsrt = CFG_LBC_LSRT;
- lbc->mrtpr = CFG_LBC_MRTPR;
- asm("msync");
-
- /*
- * Determine which address lines to use baed on CPU board rev.
- */
- cpu_board_rev = get_cpu_board_revision();
- lsdmr_common = CFG_LBC_LSDMR_COMMON;
- if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
- lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
- } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
- lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
- } else {
- /*
- * Assume something unable to identify itself is
- * really old, and likely has lines 16/17 mapped.
- */
- lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
- }
-
- /*
- * Issue PRECHARGE ALL command.
- */
- lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(100);
-
- /*
- * Issue 8 AUTO REFRESH commands.
- */
- for (idx = 0; idx < 8; idx++) {
- lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(100);
- }
-
- /*
- * Issue 8 MODE-set command.
- */
- lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(100);
-
- /*
- * Issue NORMAL OP command.
- */
- lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(200); /* Overkill. Must wait > 200 bus cycles */
-
-#endif /* enable SDRAM init */
-}
-
-#if defined(CFG_DRAM_TEST)
-int
-testdram(void)
-{
- uint *pstart = (uint *) CFG_MEMTEST_START;
- uint *pend = (uint *) CFG_MEMTEST_END;
- uint *p;
-
- printf("Testing DRAM from 0x%08x to 0x%08x\n",
- CFG_MEMTEST_START,
- CFG_MEMTEST_END);
-
- printf("DRAM test phase 1:\n");
- for (p = pstart; p < pend; p++)
- *p = 0xaaaaaaaa;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0xaaaaaaaa) {
- printf ("DRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf("DRAM test phase 2:\n");
- for (p = pstart; p < pend; p++)
- *p = 0x55555555;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0x55555555) {
- printf ("DRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf("DRAM test passed.\n");
- return 0;
-}
-#endif
-
-#if defined(CONFIG_PCI)
-/* For some reason the Tundra PCI bridge shows up on itself as a
- * different device. Work around that by refusing to configure it.
- */
-void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
-
-static struct pci_config_table pci_mpc85xxcds_config_table[] = {
- {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
- {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
- {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
- mpc85xx_config_via_usbide, {0,0,0}},
- {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
- mpc85xx_config_via_usb, {0,0,0}},
- {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
- mpc85xx_config_via_usb2, {0,0,0}},
- {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
- mpc85xx_config_via_power, {0,0,0}},
- {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
- mpc85xx_config_via_ac97, {0,0,0}},
- {},
-};
-
-static struct pci_controller hose[] = {
- { config_table: pci_mpc85xxcds_config_table,},
-#ifdef CONFIG_MPC85XX_PCI2
- {},
-#endif
-};
-
-#endif /* CONFIG_PCI */
-
-void
-pci_init_board(void)
-{
-#ifdef CONFIG_PCI
- pci_mpc85xx_init(hose);
-#endif
-}
+++ /dev/null
-/*
- * Copyright 2004 Freescale Semiconductor.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xFFFFF000 :
- {
- cpu/mpc85xx/start.o (.bootpg)
- board/cds/mpc8541cds/init.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- cpu/mpc85xx/start.o (.text)
- board/cds/mpc8541cds/init.o (.text)
- cpu/mpc85xx/traps.o (.text)
- cpu/mpc85xx/interrupts.o (.text)
- cpu/mpc85xx/cpu_init.o (.text)
- cpu/mpc85xx/cpu.o (.text)
- drivers/net/tsec.o (.text)
- cpu/mpc85xx/speed.o (.text)
- cpu/mpc85xx/pci.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
- *(.text)
- *(.fixup)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
- __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- _end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-#
-# Copyright 2004 Freescale Semiconductor.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB = $(obj)lib$(BOARD).a
-
-COBJS := $(BOARD).o \
- ../common/cadmus.o \
- ../common/eeprom.o \
- ../common/ft_board.o \
- ../common/via.o
-
-SOBJS := init.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
-
-clean:
- rm -f $(OBJS) $(SOBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-#
-# Copyright 2004, 2007 Freescale Semiconductor.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# mpc8548cds board
-#
-ifndef TEXT_BASE
-TEXT_BASE = 0xfff80000
-endif
-
-PLATFORM_CPPFLAGS += -DCONFIG_E500=1
-PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
-PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1
+++ /dev/null
-/*
- * Copyright 2004, 2007 Freescale Semiconductor.
- * Copyright 2002,2003, Motorola Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-#include <asm/cache.h>
-#include <asm/mmu.h>
-#include <config.h>
-#include <mpc85xx.h>
-
-#define LAWAR_TRGT_PCI1 0x00000000
-#define LAWAR_TRGT_PCI2 0x00100000
-#define LAWAR_TRGT_PCIE 0x00200000
-#define LAWAR_TRGT_RIO 0x00c00000
-#define LAWAR_TRGT_LBC 0x00400000
-#define LAWAR_TRGT_DDR 0x00f00000
-
-/*
- * TLB0 and TLB1 Entries
- *
- * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
- * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
- * these TLB entries are established.
- *
- * The TLB entries for DDR are dynamically setup in spd_sdram()
- * and use TLB1 Entries 8 through 15 as needed according to the
- * size of DDR memory.
- *
- * MAS0: tlbsel, esel, nv
- * MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, sharen, x0, x1, w, i, m, g, e
- * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
- */
-
-#define entry_start \
- mflr r1 ; \
- bl 0f ;
-
-#define entry_end \
-0: mflr r0 ; \
- mtlr r1 ; \
- blr ;
-
-
- .section .bootpg, "ax"
- .globl tlb1_entry
-tlb1_entry:
- entry_start
-
- /*
- * Number of TLB0 and TLB1 entries in the following table
- */
- .long (2f-1f)/16
-
-1:
-#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
- /*
- * TLB0 4K Non-cacheable, guarded
- * 0xff700000 4K Initial CCSRBAR mapping
- *
- * This ends up at a TLB0 Index==0 entry, and must not collide
- * with other TLB0 Entries.
- */
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
-#else
-#error("Update the number of table entries in tlb1_entry")
-#endif
-
- /*
- * TLB0 16K Cacheable, guarded
- * Temporary Global data for initialization
- *
- * Use four 4K TLB0 entries. These entries must be cacheable
- * as they provide the bootstrap memory before the memory
- * controler and real memory have been configured.
- *
- * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
- * and must not collide with other TLB0 entries.
- */
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
- 0,0,0,0,0,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
- 0,0,0,0,0,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
- 0,0,0,0,0,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
- 0,0,0,0,0,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
-
- /*
- * TLB 0: 16M Non-cacheable, guarded
- * 0xff000000 16M FLASH
- * Out of reset this entry is only 4K.
- */
- .long TLB1_MAS0(1, 0, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_BOOT_BLOCK), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_BOOT_BLOCK), 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 1: 1G Non-cacheable, guarded
- * 0x80000000 1G PCI1/PCIE 8,9,a,b
- */
- .long TLB1_MAS0(1, 1, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI_PHYS), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI_PHYS), 0,0,0,0,0,1,0,1,0,1)
-
-#ifdef CFG_RIO_MEM_PHYS
- /*
- * TLB 2: 256M Non-cacheable, guarded
- */
- .long TLB1_MAS0(1, 2, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_PHYS),
- 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_PHYS), 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 3: 256M Non-cacheable, guarded
- */
- .long TLB1_MAS0(1, 3, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_PHYS + 0x10000000),
- 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_PHYS + 0x10000000),
- 0,0,0,0,0,1,0,1,0,1)
-#endif
- /*
- * TLB 5: 64M Non-cacheable, guarded
- * 0xe000_0000 1M CCSRBAR
- * 0xe200_0000 1M PCI1 IO
- * 0xe210_0000 1M PCI2 IO
- * 0xe300_0000 1M PCIe IO
- */
- .long TLB1_MAS0(1, 5, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 6: 64M Cacheable, non-guarded
- * 0xf000_0000 64M LBC SDRAM
- */
- .long TLB1_MAS0(1, 6, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 7: 64M Non-cacheable, guarded
- * 0xf8000000 64M CADMUS registers, relocated L2SRAM
- */
- .long TLB1_MAS0(1, 7, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
-
-2:
- entry_end
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000 0x7fff_ffff DDR 2G
- * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
- * 0xa000_0000 0xbfff_ffff PCIe MEM 512M
- * 0xc000_0000 0xdfff_ffff RapidIO 512M
- * 0xe000_0000 0xe000_ffff CCSR 1M
- * 0xe200_0000 0xe10f_ffff PCI1 IO 1M
- * 0xe280_0000 0xe20f_ffff PCI2 IO 1M
- * 0xe300_0000 0xe30f_ffff PCIe IO 1M
- * 0xf000_0000 0xf3ff_ffff SDRAM 64M
- * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
- * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
- * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
- *
- * Notes:
- * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- * If flash is 8M at default position (last 8M), no LAW needed.
- *
- * LAW 0 is reserved for boot mapping
- */
-
- .section .bootpg, "ax"
- .globl law_entry
-law_entry:
- entry_start
-
- .long (4f-3f)/8
-3:
- .long 0
- .long (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
-
-#ifdef CFG_PCI1_MEM_PHYS
- .long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
-
- .long (CFG_PCI1_IO_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
-#endif
-
-#ifdef CFG_PCI2_MEM_PHYS
- .long (CFG_PCI2_MEM_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
-
- .long (CFG_PCI2_IO_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)
-#endif
-
-#ifdef CFG_PCIE1_MEM_PHYS
- .long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_512M)
-
- .long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_1M)
-#endif
-
- /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
- .long (CFG_LBC_CACHE_BASE>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
-
-#ifdef CFG_RIO_MEM_PHYS
- .long (CFG_RIO_MEM_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)
-#endif
-4:
- entry_end
+++ /dev/null
-/*
- * Copyright 2004, 2007 Freescale Semiconductor.
- *
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/immap_85xx.h>
-#include <asm/immap_fsl_pci.h>
-#include <spd.h>
-#include <miiphy.h>
-
-#include "../common/cadmus.h"
-#include "../common/eeprom.h"
-#include "../common/via.h"
-
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#endif
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern long int spd_sdram(void);
-
-void local_bus_init(void);
-void sdram_init(void);
-
-int board_early_init_f (void)
-{
- return 0;
-}
-
-int checkboard (void)
-{
- volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
- volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
-
- /* PCI slot in USER bits CSR[6:7] by convention. */
- uint pci_slot = get_pci_slot ();
-
- uint cpu_board_rev = get_cpu_board_revision ();
-
- printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
- get_board_version (), pci_slot);
-
- printf ("CPU Board Revision %d.%d (0x%04x)\n",
- MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
- MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
- /*
- * Initialize local bus.
- */
- local_bus_init ();
-
- /*
- * Fix CPU2 errata: A core hang possible while executing a
- * msync instruction and a snoopable transaction from an I/O
- * master tagged to make quick forward progress is present.
- */
- ecm->eebpcr |= (1 << 16);
-
- /*
- * Hack TSEC 3 and 4 IO voltages.
- */
- gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
-
- ecm->eedr = 0xffffffff; /* clear ecm errors */
- ecm->eeer = 0xffffffff; /* enable ecm errors */
- return 0;
-}
-
-long int
-initdram(int board_type)
-{
- long dram_size = 0;
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
-
- puts("Initializing\n");
-
-#if defined(CONFIG_DDR_DLL)
- {
- /*
- * Work around to stabilize DDR DLL MSYNC_IN.
- * Errata DDR9 seems to have been fixed.
- * This is now the workaround for Errata DDR11:
- * Override DLL = 1, Course Adj = 1, Tap Select = 0
- */
-
- volatile ccsr_gur_t *gur= &immap->im_gur;
-
- gur->ddrdllcr = 0x81000000;
- asm("sync;isync;msync");
- udelay(200);
- }
-#endif
- dram_size = spd_sdram();
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(dram_size);
-#endif
- /*
- * SDRAM Initialization
- */
- sdram_init();
-
- puts(" DDR: ");
- return dram_size;
-}
-
-/*
- * Initialize Local Bus
- */
-void
-local_bus_init(void)
-{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
- volatile ccsr_lbc_t *lbc = &immap->im_lbc;
-
- uint clkdiv;
- uint lbc_hz;
- sys_info_t sysinfo;
-
- get_sys_info(&sysinfo);
- clkdiv = (lbc->lcrr & 0x0f) * 2;
- lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
-
- gur->lbiuiplldcr1 = 0x00078080;
- if (clkdiv == 16) {
- gur->lbiuiplldcr0 = 0x7c0f1bf0;
- } else if (clkdiv == 8) {
- gur->lbiuiplldcr0 = 0x6c0f1bf0;
- } else if (clkdiv == 4) {
- gur->lbiuiplldcr0 = 0x5c0f1bf0;
- }
-
- lbc->lcrr |= 0x00030000;
-
- asm("sync;isync;msync");
-
- lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
- lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
-}
-
-/*
- * Initialize SDRAM memory on the Local Bus.
- */
-void
-sdram_init(void)
-{
-#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
-
- uint idx;
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_lbc_t *lbc = &immap->im_lbc;
- uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
- uint cpu_board_rev;
- uint lsdmr_common;
-
- puts(" SDRAM: ");
-
- print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
-
- /*
- * Setup SDRAM Base and Option Registers
- */
- lbc->or2 = CFG_OR2_PRELIM;
- asm("msync");
-
- lbc->br2 = CFG_BR2_PRELIM;
- asm("msync");
-
- lbc->lbcr = CFG_LBC_LBCR;
- asm("msync");
-
-
- lbc->lsrt = CFG_LBC_LSRT;
- lbc->mrtpr = CFG_LBC_MRTPR;
- asm("msync");
-
- /*
- * MPC8548 uses "new" 15-16 style addressing.
- */
- cpu_board_rev = get_cpu_board_revision();
- lsdmr_common = CFG_LBC_LSDMR_COMMON;
- lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
-
- /*
- * Issue PRECHARGE ALL command.
- */
- lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(100);
-
- /*
- * Issue 8 AUTO REFRESH commands.
- */
- for (idx = 0; idx < 8; idx++) {
- lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(100);
- }
-
- /*
- * Issue 8 MODE-set command.
- */
- lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(100);
-
- /*
- * Issue NORMAL OP command.
- */
- lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(200); /* Overkill. Must wait > 200 bus cycles */
-
-#endif /* enable SDRAM init */
-}
-
-#if defined(CFG_DRAM_TEST)
-int
-testdram(void)
-{
- uint *pstart = (uint *) CFG_MEMTEST_START;
- uint *pend = (uint *) CFG_MEMTEST_END;
- uint *p;
-
- printf("Testing DRAM from 0x%08x to 0x%08x\n",
- CFG_MEMTEST_START,
- CFG_MEMTEST_END);
-
- printf("DRAM test phase 1:\n");
- for (p = pstart; p < pend; p++)
- *p = 0xaaaaaaaa;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0xaaaaaaaa) {
- printf ("DRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf("DRAM test phase 2:\n");
- for (p = pstart; p < pend; p++)
- *p = 0x55555555;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0x55555555) {
- printf ("DRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf("DRAM test passed.\n");
- return 0;
-}
-#endif
-
-#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
-/* For some reason the Tundra PCI bridge shows up on itself as a
- * different device. Work around that by refusing to configure it.
- */
-void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
-
-static struct pci_config_table pci_mpc85xxcds_config_table[] = {
- {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
- {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
- {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
- mpc85xx_config_via_usbide, {0,0,0}},
- {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
- mpc85xx_config_via_usb, {0,0,0}},
- {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
- mpc85xx_config_via_usb2, {0,0,0}},
- {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
- mpc85xx_config_via_power, {0,0,0}},
- {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
- mpc85xx_config_via_ac97, {0,0,0}},
- {},
-};
-
-static struct pci_controller pci1_hose = {
- config_table: pci_mpc85xxcds_config_table};
-#endif /* CONFIG_PCI */
-
-#ifdef CONFIG_PCI2
-static struct pci_controller pci2_hose;
-#endif /* CONFIG_PCI2 */
-
-#ifdef CONFIG_PCIE1
-static struct pci_controller pcie1_hose;
-#endif /* CONFIG_PCIE1 */
-
-int first_free_busno=0;
-
-void
-pci_init_board(void)
-{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
- uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
- uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
-
-
-#ifdef CONFIG_PCI1
-{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
- struct pci_controller *hose = &pci1_hose;
- struct pci_config_table *table;
-
- uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
- uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
- uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
-
- uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);
-
- uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
-
- if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
- printf (" PCI: %d bit, %s MHz, %s, %s, %s\n",
- (pci_32) ? 32 : 64,
- (pci_speed == 33333000) ? "33" :
- (pci_speed == 66666000) ? "66" : "unknown",
- pci_clk_sel ? "sync" : "async",
- pci_agent ? "agent" : "host",
- pci_arb ? "arbiter" : "external-arbiter"
- );
-
-
- /* inbound */
- pci_set_region(hose->regions + 0,
- CFG_PCI_MEMORY_BUS,
- CFG_PCI_MEMORY_PHYS,
- CFG_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
-
-
- /* outbound memory */
- pci_set_region(hose->regions + 1,
- CFG_PCI1_MEM_BASE,
- CFG_PCI1_MEM_PHYS,
- CFG_PCI1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(hose->regions + 2,
- CFG_PCI1_IO_BASE,
- CFG_PCI1_IO_PHYS,
- CFG_PCI1_IO_SIZE,
- PCI_REGION_IO);
- hose->region_count = 3;
-
- /* relocate config table pointers */
- hose->config_table = \
- (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off);
- for (table = hose->config_table; table && table->vendor; table++)
- table->config_device += gd->reloc_off;
-
- hose->first_busno=first_free_busno;
- pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
-
- fsl_pci_init(hose);
- first_free_busno=hose->last_busno+1;
- printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
-#ifdef CONFIG_PCIX_CHECK
- if (!(gur->pordevsr & PORDEVSR_PCI)) {
- /* PCI-X init */
- if (CONFIG_SYS_CLK_FREQ < 66000000)
- printf("PCI-X will only work at 66 MHz\n");
-
- reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
- | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
- pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
- }
-#endif
- } else {
- printf (" PCI: disabled\n");
- }
-}
-#else
- gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
-#endif
-
-#ifdef CONFIG_PCI2
-{
- uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
- uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
- if (pci_dual) {
- printf (" PCI2: 32 bit, 66 MHz, %s\n",
- pci2_clk_sel ? "sync" : "async");
- } else {
- printf (" PCI2: disabled\n");
- }
-}
-#else
- gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */
-#endif /* CONFIG_PCI2 */
-
-#ifdef CONFIG_PCIE1
-{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
- struct pci_controller *hose = &pcie1_hose;
- int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
-
- int pcie_configured = io_sel >= 1;
-
- if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
- printf ("\n PCIE connected to slot as %s (base address %x)",
- pcie_ep ? "End Point" : "Root Complex",
- (uint)pci);
-
- if (pci->pme_msg_det) {
- pci->pme_msg_det = 0xffffffff;
- debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
- }
- printf ("\n");
-
- /* inbound */
- pci_set_region(hose->regions + 0,
- CFG_PCI_MEMORY_BUS,
- CFG_PCI_MEMORY_PHYS,
- CFG_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
-
- /* outbound memory */
- pci_set_region(hose->regions + 1,
- CFG_PCIE1_MEM_BASE,
- CFG_PCIE1_MEM_PHYS,
- CFG_PCIE1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(hose->regions + 2,
- CFG_PCIE1_IO_BASE,
- CFG_PCIE1_IO_PHYS,
- CFG_PCIE1_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = 3;
-
- hose->first_busno=first_free_busno;
- pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
-
- fsl_pci_init(hose);
- printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno);
-
- first_free_busno=hose->last_busno+1;
-
- } else {
- printf (" PCIE: disabled\n");
- }
- }
-#else
- gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
-#endif
-
-}
-
-int last_stage_init(void)
-{
- unsigned short temp;
-
- /* Change the resistors for the PHY */
- /* This is needed to get the RGMII working for the 1.3+
- * CDS cards */
- if (get_board_version() == 0x13) {
- miiphy_write(CONFIG_TSEC1_NAME,
- TSEC1_PHY_ADDR, 29, 18);
-
- miiphy_read(CONFIG_TSEC1_NAME,
- TSEC1_PHY_ADDR, 30, &temp);
-
- temp = (temp & 0xf03f);
- temp |= 2 << 9; /* 36 ohm */
- temp |= 2 << 6; /* 39 ohm */
-
- miiphy_write(CONFIG_TSEC1_NAME,
- TSEC1_PHY_ADDR, 30, temp);
-
- miiphy_write(CONFIG_TSEC1_NAME,
- TSEC1_PHY_ADDR, 29, 3);
-
- miiphy_write(CONFIG_TSEC1_NAME,
- TSEC1_PHY_ADDR, 30, 0x8000);
- }
-
- return 0;
-}
-
-
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_pci_setup(void *blob, bd_t *bd)
-{
- u32 *p;
- int len;
-
-
-#ifdef CONFIG_PCI1
- p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
- if (p != NULL) {
- p[0] = 0;
- p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
- debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
- }
-#endif
-
-#ifdef CONFIG_PCIE1
- p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len);
- if (p != NULL) {
- p[0] = 0;
- p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
- debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]);
- }
-#endif
-}
-#endif
+++ /dev/null
-/*
- * Copyright 2004, 2007 Freescale Semiconductor.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xFFFFF000 :
- {
- cpu/mpc85xx/start.o (.bootpg)
- board/cds/mpc8548cds/init.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- cpu/mpc85xx/start.o (.text)
- board/cds/mpc8548cds/init.o (.text)
- cpu/mpc85xx/traps.o (.text)
- cpu/mpc85xx/interrupts.o (.text)
- cpu/mpc85xx/cpu_init.o (.text)
- cpu/mpc85xx/cpu.o (.text)
- drivers/net/tsec.o (.text)
- cpu/mpc85xx/speed.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
- *(.text)
- *(.fixup)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
- __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- _end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-#
-# Copyright 2004 Freescale Semiconductor.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB = $(obj)lib$(BOARD).a
-
-COBJS := $(BOARD).o \
- ../common/cadmus.o \
- ../common/eeprom.o \
- ../common/ft_board.o \
- ../common/via.o
-
-SOBJS := init.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
-
-clean:
- rm -f $(OBJS) $(SOBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-#
-# Copyright 2004 Freescale Semiconductor.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# mpc8555cds board
-#
-TEXT_BASE = 0xfff80000
-
-PLATFORM_CPPFLAGS += -DCONFIG_E500=1
-PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
-PLATFORM_CPPFLAGS += -DCONFIG_MPC8555=1
+++ /dev/null
-/*
- * Copyright 2004 Freescale Semiconductor.
- * Copyright 2002,2003, Motorola Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-#include <asm/cache.h>
-#include <asm/mmu.h>
-#include <config.h>
-#include <mpc85xx.h>
-
-
-/*
- * TLB0 and TLB1 Entries
- *
- * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
- * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
- * these TLB entries are established.
- *
- * The TLB entries for DDR are dynamically setup in spd_sdram()
- * and use TLB1 Entries 8 through 15 as needed according to the
- * size of DDR memory.
- *
- * MAS0: tlbsel, esel, nv
- * MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, sharen, x0, x1, w, i, m, g, e
- * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
- */
-
-#define entry_start \
- mflr r1 ; \
- bl 0f ;
-
-#define entry_end \
-0: mflr r0 ; \
- mtlr r1 ; \
- blr ;
-
-
- .section .bootpg, "ax"
- .globl tlb1_entry
-tlb1_entry:
- entry_start
-
- /*
- * Number of TLB0 and TLB1 entries in the following table
- */
- .long 13
-
-#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
- /*
- * TLB0 4K Non-cacheable, guarded
- * 0xff700000 4K Initial CCSRBAR mapping
- *
- * This ends up at a TLB0 Index==0 entry, and must not collide
- * with other TLB0 Entries.
- */
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
-#else
-#error("Update the number of table entries in tlb1_entry")
-#endif
-
- /*
- * TLB0 16K Cacheable, non-guarded
- * 0xd001_0000 16K Temporary Global data for initialization
- *
- * Use four 4K TLB0 entries. These entries must be cacheable
- * as they provide the bootstrap memory before the memory
- * controler and real memory have been configured.
- *
- * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
- * and must not collide with other TLB0 entries.
- */
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
-
- /*
- * TLB 0: 16M Non-cacheable, guarded
- * 0xff000000 16M FLASH
- * Out of reset this entry is only 4K.
- */
- .long TLB1_MAS0(1, 0, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 1: 256M Non-cacheable, guarded
- * 0x80000000 256M PCI1 MEM First half
- */
- .long TLB1_MAS0(1, 1, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 2: 256M Non-cacheable, guarded
- * 0x90000000 256M PCI1 MEM Second half
- */
- .long TLB1_MAS0(1, 2, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
- 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
- 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 3: 256M Non-cacheable, guarded
- * 0xa0000000 256M PCI2 MEM First half
- */
- .long TLB1_MAS0(1, 3, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 4: 256M Non-cacheable, guarded
- * 0xb0000000 256M PCI2 MEM Second half
- */
- .long TLB1_MAS0(1, 4, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000),
- 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000),
- 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 5: 64M Non-cacheable, guarded
- * 0xe000_0000 1M CCSRBAR
- * 0xe200_0000 16M PCI1 IO
- * 0xe300_0000 16M PCI2 IO
- */
- .long TLB1_MAS0(1, 5, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 6: 64M Cacheable, non-guarded
- * 0xf000_0000 64M LBC SDRAM
- */
- .long TLB1_MAS0(1, 6, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 7: 1M Non-cacheable, guarded
- * 0xf8000000 1M CADMUS registers
- */
- .long TLB1_MAS0(1, 7, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
- .long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1)
-
- entry_end
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000 0x7fff_ffff DDR 2G
- * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
- * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
- * 0xe000_0000 0xe000_ffff CCSR 1M
- * 0xe200_0000 0xe20f_ffff PCI1 IO 1M
- * 0xe210_0000 0xe21f_ffff PCI2 IO 1M
- * 0xf000_0000 0xf7ff_ffff SDRAM 128M
- * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
- * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
- * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
- *
- * Notes:
- * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- * If flash is 8M at default position (last 8M), no LAW needed.
- *
- * The defines below are 1-off of the actual LAWAR0 usage.
- * So LAWAR3 define uses the LAWAR4 register in the ECM.
- */
-
-#define LAWBAR0 0
-#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
-
-#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
-#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
-#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
-#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
-
-#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff)
-#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
-
-/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
-#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
-#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
-
- .section .bootpg, "ax"
- .globl law_entry
-
-law_entry:
- entry_start
- .long 6
- .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
- .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5
- entry_end
+++ /dev/null
-/*
- * Copyright 2004 Freescale Semiconductor.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/immap_85xx.h>
-#include <ioports.h>
-#include <spd.h>
-
-#include "../common/cadmus.h"
-#include "../common/eeprom.h"
-#include "../common/via.h"
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
-extern long int spd_sdram(void);
-
-void local_bus_init(void);
-void sdram_init(void);
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
- /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
- /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
- /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
- /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
- /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
- /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
- /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
- /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
- /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
- /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
- /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
- /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
- /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
- /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
- /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
- /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
- /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
- /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
- /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
- /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
- /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
- /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
- /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
- /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
- /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
- /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
- /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
- /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
- /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
- /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
- /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
- },
-
- /* Port B configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
- /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
- /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
- /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
- /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
- /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
- /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
- /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
- /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
- /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
- /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
- /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
- /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
- /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
- /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
- /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
- /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
- /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
- /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
- /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
- /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
- /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
- /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
- /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
- /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
- /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
- /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
- /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
- /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
- /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
- /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
- /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
- /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
- /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
- /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
- /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
- /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
- /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
- /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
- /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
- /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
- /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
- /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
- /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
- /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
- /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
- /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
- /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
- /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
- /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
- /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
- /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
- /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
- /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
- /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
- /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
- /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- }
-};
-
-int board_early_init_f (void)
-{
- return 0;
-}
-
-int checkboard (void)
-{
- volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
-
- /* PCI slot in USER bits CSR[6:7] by convention. */
- uint pci_slot = get_pci_slot ();
-
- uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
- uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
- uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
- uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
-
- uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
-
- uint cpu_board_rev = get_cpu_board_revision ();
-
- printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
- get_board_version (), pci_slot);
-
- printf ("CPU Board Revision %d.%d (0x%04x)\n",
- MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
- MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
-
- printf (" PCI1: %d bit, %s MHz, %s\n",
- (pci1_32) ? 32 : 64,
- (pci1_speed == 33000000) ? "33" :
- (pci1_speed == 66000000) ? "66" : "unknown",
- pci1_clk_sel ? "sync" : "async");
-
- if (pci_dual) {
- printf (" PCI2: 32 bit, 66 MHz, %s\n",
- pci2_clk_sel ? "sync" : "async");
- } else {
- printf (" PCI2: disabled\n");
- }
-
- /*
- * Initialize local bus.
- */
- local_bus_init ();
-
- return 0;
-}
-
-long int
-initdram(int board_type)
-{
- long dram_size = 0;
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
-
- puts("Initializing\n");
-
-#if defined(CONFIG_DDR_DLL)
- {
- /*
- * Work around to stabilize DDR DLL MSYNC_IN.
- * Errata DDR9 seems to have been fixed.
- * This is now the workaround for Errata DDR11:
- * Override DLL = 1, Course Adj = 1, Tap Select = 0
- */
-
- volatile ccsr_gur_t *gur= &immap->im_gur;
-
- gur->ddrdllcr = 0x81000000;
- asm("sync;isync;msync");
- udelay(200);
- }
-#endif
- dram_size = spd_sdram();
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(dram_size);
-#endif
- /*
- * SDRAM Initialization
- */
- sdram_init();
-
- puts(" DDR: ");
- return dram_size;
-}
-
-/*
- * Initialize Local Bus
- */
-void
-local_bus_init(void)
-{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
- volatile ccsr_lbc_t *lbc = &immap->im_lbc;
-
- uint clkdiv;
- uint lbc_hz;
- sys_info_t sysinfo;
- uint temp_lbcdll;
-
- /*
- * Errata LBC11.
- * Fix Local Bus clock glitch when DLL is enabled.
- *
- * If localbus freq is < 66Mhz, DLL bypass mode must be used.
- * If localbus freq is > 133Mhz, DLL can be safely enabled.
- * Between 66 and 133, the DLL is enabled with an override workaround.
- */
-
- get_sys_info(&sysinfo);
- clkdiv = lbc->lcrr & 0x0f;
- lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
-
- if (lbc_hz < 66) {
- lbc->lcrr |= 0x80000000; /* DLL Bypass */
-
- } else if (lbc_hz >= 133) {
- lbc->lcrr &= (~0x80000000); /* DLL Enabled */
-
- } else {
- lbc->lcrr &= (~0x8000000); /* DLL Enabled */
- udelay(200);
-
- /*
- * Sample LBC DLL ctrl reg, upshift it to set the
- * override bits.
- */
- temp_lbcdll = gur->lbcdllcr;
- gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
- asm("sync;isync;msync");
- }
-}
-
-/*
- * Initialize SDRAM memory on the Local Bus.
- */
-void
-sdram_init(void)
-{
-#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
-
- uint idx;
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_lbc_t *lbc = &immap->im_lbc;
- uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
- uint cpu_board_rev;
- uint lsdmr_common;
-
- puts(" SDRAM: ");
-
- print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
-
- /*
- * Setup SDRAM Base and Option Registers
- */
- lbc->or2 = CFG_OR2_PRELIM;
- asm("msync");
-
- lbc->br2 = CFG_BR2_PRELIM;
- asm("msync");
-
- lbc->lbcr = CFG_LBC_LBCR;
- asm("msync");
-
- lbc->lsrt = CFG_LBC_LSRT;
- lbc->mrtpr = CFG_LBC_MRTPR;
- asm("msync");
-
- /*
- * Determine which address lines to use baed on CPU board rev.
- */
- cpu_board_rev = get_cpu_board_revision();
- lsdmr_common = CFG_LBC_LSDMR_COMMON;
- if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
- lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
- } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
- lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
- } else {
- /*
- * Assume something unable to identify itself is
- * really old, and likely has lines 16/17 mapped.
- */
- lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
- }
-
- /*
- * Issue PRECHARGE ALL command.
- */
- lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(100);
-
- /*
- * Issue 8 AUTO REFRESH commands.
- */
- for (idx = 0; idx < 8; idx++) {
- lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(100);
- }
-
- /*
- * Issue 8 MODE-set command.
- */
- lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(100);
-
- /*
- * Issue NORMAL OP command.
- */
- lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(200); /* Overkill. Must wait > 200 bus cycles */
-
-#endif /* enable SDRAM init */
-}
-
-#if defined(CFG_DRAM_TEST)
-int
-testdram(void)
-{
- uint *pstart = (uint *) CFG_MEMTEST_START;
- uint *pend = (uint *) CFG_MEMTEST_END;
- uint *p;
-
- printf("Testing DRAM from 0x%08x to 0x%08x\n",
- CFG_MEMTEST_START,
- CFG_MEMTEST_END);
-
- printf("DRAM test phase 1:\n");
- for (p = pstart; p < pend; p++)
- *p = 0xaaaaaaaa;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0xaaaaaaaa) {
- printf ("DRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf("DRAM test phase 2:\n");
- for (p = pstart; p < pend; p++)
- *p = 0x55555555;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0x55555555) {
- printf ("DRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf("DRAM test passed.\n");
- return 0;
-}
-#endif
-
-#ifdef CONFIG_PCI
-/* For some reason the Tundra PCI bridge shows up on itself as a
- * different device. Work around that by refusing to configure it
- */
-void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
-
-static struct pci_config_table pci_mpc85xxcds_config_table[] = {
- {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
- {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
- {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
- mpc85xx_config_via_usbide, {0,0,0}},
- {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
- mpc85xx_config_via_usb, {0,0,0}},
- {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
- mpc85xx_config_via_usb2, {0,0,0}},
- {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
- mpc85xx_config_via_power, {0,0,0}},
- {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
- mpc85xx_config_via_ac97, {0,0,0}},
- {},
-};
-
-
-static struct pci_controller hose[] = {
- {
- config_table: pci_mpc85xxcds_config_table,
- },
-#ifdef CONFIG_MPC85XX_PCI2
- {},
-#endif
-};
-
-#endif
-
-void
-pci_init_board(void)
-{
-#ifdef CONFIG_PCI
- pci_mpc85xx_init(hose);
-#endif
-}
+++ /dev/null
-/*
- * Copyright 2004 Freescale Semiconductor.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xFFFFF000 :
- {
- cpu/mpc85xx/start.o (.bootpg)
- board/cds/mpc8555cds/init.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- cpu/mpc85xx/start.o (.text)
- board/cds/mpc8555cds/init.o (.text)
- cpu/mpc85xx/traps.o (.text)
- cpu/mpc85xx/interrupts.o (.text)
- cpu/mpc85xx/cpu_init.o (.text)
- cpu/mpc85xx/cpu.o (.text)
- drivers/net/tsec.o (.text)
- cpu/mpc85xx/speed.o (.text)
- cpu/mpc85xx/pci.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
- *(.text)
- *(.fixup)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
- __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- _end = . ;
- PROVIDE (end = .);
-}
{
int len, ret, nodeoffset = 0;
char module_name[MODULE_NAME_MAXLEN] = {0};
- ulong memory_data[2] = {0};
compose_module_name(hw_id, module_name);
len = strlen(module_name) + 1;
printf("ft_blob_update(): cannot set /model property err:%s\n",
fdt_strerror(ret));
- memory_data[0] = cpu_to_be32(bd->bi_memstart);
- memory_data[1] = cpu_to_be32(bd->bi_memsize);
+ ret = fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
- nodeoffset = fdt_path_offset (blob, "/memory");
- if (nodeoffset >= 0) {
- ret = fdt_setprop(blob, nodeoffset, "reg", memory_data,
- sizeof(memory_data));
- if (ret < 0)
+ if (ret < 0) {
printf("ft_blob_update): cannot set /memory/reg "
"property err:%s\n", fdt_strerror(ret));
}
- else {
- /* memory node is required in dts */
- printf("ft_blob_update(): cannot find /memory node "
- "err:%s\n", fdt_strerror(nodeoffset));
- }
}
#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
board/cray/L1/init.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
cpu/ppc4xx/4xx_enet.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
cpu/ppc4xx/4xx_enet.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
cpu/ppc4xx/4xx_enet.o (.text)
cpu/ppc4xx/start.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
cpu/ppc4xx/4xx_enet.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
cpu/ppc4xx/4xx_enet.o (.text)
cpu/ppc4xx/start.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
cpu/ppc4xx/start.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
cpu/ppc4xx/4xx_enet.o (.text)
cpu/ppc4xx/start.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
cpu/ppc4xx/start.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
cpu/ppc4xx/start.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
* MA 02111-1307 USA
*/
+#include "asm/io.h"
#include "lcd.h"
*/
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD0_RST); /* set reset to low */
udelay(10); /* wait 10us */
- if (config == 1) {
+ if (config == 1)
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */
- } else {
+ else
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */
- }
udelay(10); /* wait 10us */
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD0_RST); /* set reset to high */
} else {
*/
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD1_RST); /* set reset to low */
udelay(10); /* wait 10us */
- if (config == 1) {
+ if (config == 1)
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */
- } else {
+ else
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */
- }
udelay(10); /* wait 10us */
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD1_RST); /* set reset to high */
}
printf("Error: malloc in gunzip failed!\n");
return;
}
- if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE, (uchar *)logo_bmp, &len) != 0) {
+ if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE, (uchar *)logo_bmp, &len) != 0)
return;
- }
- if (len == CFG_VIDEO_LOGO_MAX_SIZE) {
+ if (len == CFG_VIDEO_LOGO_MAX_SIZE)
printf("Image could be truncated (increase CFG_VIDEO_LOGO_MAX_SIZE)!\n");
- }
/*
* Check for bmp mark 'BM'
break;
default:
printf("LCD: Unknown bpp (%d) im image!\n", bpp);
- if ((dst != NULL) && (dst != (uchar *)logo_bmp)) {
+ if ((dst != NULL) && (dst != (uchar *)logo_bmp))
free(dst);
- }
return;
}
printf(" (%d*%d, %dbpp)\n", width, height, bpp);
}
}
- if ((dst != NULL) && (dst != (uchar *)logo_bmp)) {
+ if ((dst != NULL) && (dst != (uchar *)logo_bmp))
free(dst);
- }
}
/*
* Detect epson
*/
- lcd_reg[0] = 0x00;
- lcd_reg[1] = 0x00;
+ out_8(&lcd_reg[0], 0x00);
+ out_8(&lcd_reg[1], 0x00);
- if (lcd_reg[0] == 0x1c) {
+ if (in_8(&lcd_reg[0]) == 0x1c) {
/*
* Big epson detected
*/
palette_value = 0x1e4;
lcd_depth = 16;
puts("LCD: S1D13806");
- } else if (lcd_reg[1] == 0x1c) {
+ } else if (in_8(&lcd_reg[1]) == 0x1c) {
/*
* Big epson detected (with register swap bug)
*/
palette_value = 0x1e5;
lcd_depth = 16;
puts("LCD: S1D13806S");
- } else if (lcd_reg[0] == 0x18) {
+ } else if (in_8(&lcd_reg[0]) == 0x18) {
/*
* Small epson detected (704)
*/
palette_value = 0x17;
lcd_depth = 8;
puts("LCD: S1D13704");
- } else if (lcd_reg[0x10000] == 0x24) {
+ } else if (in_8(&lcd_reg[0x10000]) == 0x24) {
/*
* Small epson detected (705)
*/
/*
* Setup lcd controller regs
*/
- for (i = 0; i<reg_count; i++) {
+ for (i = 0; i < reg_count; i++) {
s1dReg = regs[i].Index;
if (reg_byte_swap) {
if ((s1dReg & 0x0001) == 0)
cpu/ppc4xx/start.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
cpu/ppc4xx/start.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
+++ /dev/null
-#
-# (C) Copyright 2002-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB = $(obj)lib$(BOARD).a
-
-COBJS = $(BOARD).o strataflash.o ../common/misc.o
-SOBJS = init.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
-
-clean:
- rm -f $(SOBJS) $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# esd ADCIOP boards
-#
-
-#TEXT_BASE = 0xFFFE0000
-
-ifeq ($(ramsym),1)
-TEXT_BASE = 0x07FD0000
-else
-TEXT_BASE = 0xFFFC0000
-#TEXT_BASE = 0x01fc0000
-endif
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
-endif
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <common.h>
-#include <asm/processor.h>
-
-
-extern void lxt971_no_sleep(void);
-
-
-long int fixed_sdram( void );
-
-int board_early_init_f (void)
-{
- uint reg;
-
- /*--------------------------------------------------------------------
- * Setup the external bus controller/chip selects
- *-------------------------------------------------------------------*/
- mtdcr( ebccfga, xbcfg );
- reg = mfdcr( ebccfgd );
- mtdcr( ebccfgd, reg | 0x04000000 ); /* Set ATC */
-
- mtebc( pb0ap, 0x92015480 ); /* FLASH/SRAM */
- mtebc( pb0cr, 0xFF87A000 ); /* BAS=0xff8 8MB R/W 16-bit */
- /* test-only: other regs still missing... */
-
- /*--------------------------------------------------------------------
- * Setup the interrupt controller polarities, triggers, etc.
- *-------------------------------------------------------------------*/
- mtdcr( uic0sr, 0xffffffff ); /* clear all */
- mtdcr( uic0er, 0x00000000 ); /* disable all */
- mtdcr( uic0cr, 0x00000009 ); /* SMI & UIC1 crit are critical */
- mtdcr( uic0pr, 0xfffffe13 ); /* per ref-board manual */
- mtdcr( uic0tr, 0x01c00008 ); /* per ref-board manual */
- mtdcr( uic0vr, 0x00000001 ); /* int31 highest, base=0x000 */
- mtdcr( uic0sr, 0xffffffff ); /* clear all */
-
- mtdcr( uic1sr, 0xffffffff ); /* clear all */
- mtdcr( uic1er, 0x00000000 ); /* disable all */
- mtdcr( uic1cr, 0x00000000 ); /* all non-critical */
- mtdcr( uic1pr, 0xffffe0ff ); /* per ref-board manual */
- mtdcr( uic1tr, 0x00ffc000 ); /* per ref-board manual */
- mtdcr( uic1vr, 0x00000001 ); /* int31 highest, base=0x000 */
- mtdcr( uic1sr, 0xffffffff ); /* clear all */
-
- return 0;
-}
-
-
-int checkboard (void)
-{
- sys_info_t sysinfo;
- get_sys_info(&sysinfo);
-
- printf("Board: esd CPCI-440\n");
- printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz/1000000);
- printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor/1000000);
- printf("\tPLB: %lu MHz\n", sysinfo.freqPLB/1000000);
- printf("\tOPB: %lu MHz\n", sysinfo.freqOPB/1000000);
- printf("\tEPB: %lu MHz\n", sysinfo.freqEPB/1000000);
-
- /*
- * Disable sleep mode in LXT971
- */
- lxt971_no_sleep();
-
- return (0);
-}
-
-
-long int initdram (int board_type)
-{
- long dram_size = 0;
-
- dram_size = fixed_sdram();
- return dram_size;
-}
-
-
-/*************************************************************************
- * fixed sdram init -- doesn't use serial presence detect.
- *
- * Assumes: 64 MB, non-ECC, non-registered
- * PLB @ 133 MHz
- *
- ************************************************************************/
-long int fixed_sdram( void )
-{
- uint reg;
-
-#if 1 /* test-only */
- /*--------------------------------------------------------------------
- * Setup some default
- *------------------------------------------------------------------*/
- mtsdram( mem_uabba, 0x00000000 ); /* ubba=0 (default) */
- mtsdram( mem_slio, 0x00000000 ); /* rdre=0 wrre=0 rarw=0 */
- mtsdram( mem_devopt,0x00000000 ); /* dll=0 ds=0 (normal) */
- mtsdram( mem_wddctr,0x40000000 ); /* wrcp=0 dcd=0 */
- mtsdram( mem_clktr, 0x40000000 ); /* clkp=1 (90 deg wr) dcdt=0 */
-
- /*--------------------------------------------------------------------
- * Setup for board-specific specific mem
- *------------------------------------------------------------------*/
- /*
- * Following for CAS Latency = 2.5 @ 133 MHz PLB
- */
- mtsdram( mem_b0cr, 0x00082001 );/* SDBA=0x000, 64MB, Mode 2, enabled*/
- mtsdram( mem_tr0, 0x410a4012 );/* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
- /* RA=10 RD=3 */
- mtsdram( mem_tr1, 0x8080082f );/* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
- mtsdram( mem_rtr, 0x08200000 );/* Rate 15.625 ns @ 133 MHz PLB */
- mtsdram( mem_cfg1, 0x00000000 );/* Self-refresh exit, disable PM */
- udelay( 400 ); /* Delay 200 usecs (min) */
-
- /*--------------------------------------------------------------------
- * Enable the controller, then wait for DCEN to complete
- *------------------------------------------------------------------*/
- mtsdram( mem_cfg0, 0x86000000 );/* DCEN=1, PMUD=1, 64-bit */
- for(;;)
- {
- mfsdram( mem_mcsts, reg );
- if( reg & 0x80000000 )
- break;
- }
-
- return( 64 * 1024 * 1024 ); /* 64 MB */
-#else
- return( 32 * 1024 * 1024 ); /* 64 MB */
-#endif
-}
+++ /dev/null
-/*
-* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
-*
-* See file CREDITS for list of people who contributed to this
-* project.
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation; either version 2 of
-* the License, or (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program; if not, write to the Free Software
-* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-* MA 02111-1307 USA
-*/
-
-#include <ppc_asm.tmpl>
-#include <config.h>
-
-/* General */
-#define TLB_VALID 0x00000200
-
-/* Supported page sizes */
-
-#define SZ_1K 0x00000000
-#define SZ_4K 0x00000010
-#define SZ_16K 0x00000020
-#define SZ_64K 0x00000030
-#define SZ_256K 0x00000040
-#define SZ_1M 0x00000050
-#define SZ_16M 0x00000070
-#define SZ_256M 0x00000090
-
-/* Storage attributes */
-#define SA_W 0x00000800 /* Write-through */
-#define SA_I 0x00000400 /* Caching inhibited */
-#define SA_M 0x00000200 /* Memory coherence */
-#define SA_G 0x00000100 /* Guarded */
-#define SA_E 0x00000080 /* Endian */
-
-/* Access control */
-#define AC_X 0x00000024 /* Execute */
-#define AC_W 0x00000012 /* Write */
-#define AC_R 0x00000009 /* Read */
-
-/* Some handy macros */
-
-#define EPN(e) ((e) & 0xfffffc00)
-#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
-#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
-#define TLB2(a) ( (a)&0x00000fbf )
-
-#define tlbtab_start\
- mflr r1 ;\
- bl 0f ;
-
-#define tlbtab_end\
- .long 0, 0, 0 ; \
-0: mflr r0 ; \
- mtlr r1 ; \
- blr ;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
- .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- * Pointer to the table is returned in r1
- *
- *************************************************************************/
-
- .section .bootpg,"ax"
- .globl tlbtab
-
-tlbtab:
- tlbtab_start
- tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
- tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
- tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
- tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
- tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X )
- tlbtab_end
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/processor.h>
-
-#undef DEBUG_FLASH
-/*
- * This file implements a Common Flash Interface (CFI) driver for U-Boot.
- * The width of the port and the width of the chips are determined at initialization.
- * These widths are used to calculate the address for access CFI data structures.
- * It has been tested on an Intel Strataflash implementation.
- *
- * References
- * JEDEC Standard JESD68 - Common Flash Interface (CFI)
- * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
- * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
- * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
- *
- * TODO
- * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
- * Add support for other command sets Use the PRI and ALT to determine command set
- * Verify erase and program timeouts.
- */
-
-#define FLASH_CMD_CFI 0x98
-#define FLASH_CMD_READ_ID 0x90
-#define FLASH_CMD_RESET 0xff
-#define FLASH_CMD_BLOCK_ERASE 0x20
-#define FLASH_CMD_ERASE_CONFIRM 0xD0
-#define FLASH_CMD_WRITE 0x40
-#define FLASH_CMD_PROTECT 0x60
-#define FLASH_CMD_PROTECT_SET 0x01
-#define FLASH_CMD_PROTECT_CLEAR 0xD0
-#define FLASH_CMD_CLEAR_STATUS 0x50
-#define FLASH_CMD_WRITE_TO_BUFFER 0xE8
-#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
-
-#define FLASH_STATUS_DONE 0x80
-#define FLASH_STATUS_ESS 0x40
-#define FLASH_STATUS_ECLBS 0x20
-#define FLASH_STATUS_PSLBS 0x10
-#define FLASH_STATUS_VPENS 0x08
-#define FLASH_STATUS_PSS 0x04
-#define FLASH_STATUS_DPS 0x02
-#define FLASH_STATUS_R 0x01
-#define FLASH_STATUS_PROTECT 0x01
-
-#define FLASH_OFFSET_CFI 0x55
-#define FLASH_OFFSET_CFI_RESP 0x10
-#define FLASH_OFFSET_WTOUT 0x1F
-#define FLASH_OFFSET_WBTOUT 0x20
-#define FLASH_OFFSET_ETOUT 0x21
-#define FLASH_OFFSET_CETOUT 0x22
-#define FLASH_OFFSET_WMAX_TOUT 0x23
-#define FLASH_OFFSET_WBMAX_TOUT 0x24
-#define FLASH_OFFSET_EMAX_TOUT 0x25
-#define FLASH_OFFSET_CEMAX_TOUT 0x26
-#define FLASH_OFFSET_SIZE 0x27
-#define FLASH_OFFSET_INTERFACE 0x28
-#define FLASH_OFFSET_BUFFER_SIZE 0x2A
-#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C
-#define FLASH_OFFSET_ERASE_REGIONS 0x2D
-#define FLASH_OFFSET_PROTECT 0x02
-#define FLASH_OFFSET_USER_PROTECTION 0x85
-#define FLASH_OFFSET_INTEL_PROTECTION 0x81
-
-
-#define FLASH_MAN_CFI 0x01000000
-
-
-typedef union {
- unsigned char c;
- unsigned short w;
- unsigned long l;
-} cfiword_t;
-
-typedef union {
- unsigned char * cp;
- unsigned short *wp;
- unsigned long *lp;
-} cfiptr_t;
-
-#define NUM_ERASE_REGIONS 4
-
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-
-
-static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c);
-static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf);
-static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd);
-static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd);
-static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd);
-static int flash_detect_cfi(flash_info_t * info);
-static ulong flash_get_size (ulong base, int banknum);
-static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword);
-static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt);
-#ifdef CFG_FLASH_USE_BUFFER_WRITE
-static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len);
-#endif
-/*-----------------------------------------------------------------------
- * create an address based on the offset and the port width
- */
-inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset)
-{
- return ((uchar *)(info->start[sect] + (offset * info->portwidth)));
-}
-/*-----------------------------------------------------------------------
- * read a character at a port width address
- */
-inline uchar flash_read_uchar(flash_info_t * info, uchar offset)
-{
- uchar *cp;
- cp = flash_make_addr(info, 0, offset);
- return (cp[info->portwidth - 1]);
-}
-
-/*-----------------------------------------------------------------------
- * read a short word by swapping for ppc format.
- */
-ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset)
-{
- uchar * addr;
-
- addr = flash_make_addr(info, sect, offset);
- return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]);
-
-}
-
-/*-----------------------------------------------------------------------
- * read a long word by picking the least significant byte of each maiximum
- * port size word. Swap for ppc format.
- */
-ulong flash_read_long(flash_info_t * info, int sect, uchar offset)
-{
- uchar * addr;
-
- addr = flash_make_addr(info, sect, offset);
- return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) |
- (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]);
-
-}
-
-/*-----------------------------------------------------------------------
- */
-unsigned long flash_init (void)
-{
- unsigned long size;
- int i;
- unsigned long address;
-
-
- /* The flash is positioned back to back, with the demultiplexing of the chip
- * based on the A24 address line.
- *
- */
-
- address = CFG_FLASH_BASE;
- size = 0;
-
- /* Init: no FLASHes known */
- for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- size += flash_info[i].size = flash_get_size(address, i);
- address += CFG_FLASH_INCREMENT;
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i,
- flash_info[0].size, flash_info[i].size<<20);
- }
- }
-
-#if 0 /* test-only */
- /* Monitor protection ON by default */
-#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
- for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+monitor_flash_len-1; i++)
- (void)flash_real_protect(&flash_info[0], i, 1);
-#endif
-#endif
-
- return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- int rcode = 0;
- int prot;
- int sect;
-
- if( info->flash_id != FLASH_MAN_CFI) {
- printf ("Can't erase unknown flash type - aborted\n");
- return 1;
- }
- if ((s_first < 0) || (s_first > s_last)) {
- printf ("- no sectors to erase\n");
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
-
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
- flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
-
- if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) {
- rcode = 1;
- } else
- printf(".");
- }
- }
- printf (" done\n");
- return rcode;
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id != FLASH_MAN_CFI) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- printf("CFI conformant FLASH (%d x %d)",
- (info->portwidth << 3 ), (info->chipwidth << 3 ));
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
- printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
- info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n");
- printf (" %08lX%5s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong wp;
- ulong cp;
- int aln;
- cfiword_t cword;
- int i, rc;
-
- /* get lower aligned address */
- wp = (addr & ~(info->portwidth - 1));
-
- /* handle unaligned start */
- if((aln = addr - wp) != 0) {
- cword.l = 0;
- cp = wp;
- for(i=0;i<aln; ++i, ++cp)
- flash_add_byte(info, &cword, (*(uchar *)cp));
-
- for(; (i< info->portwidth) && (cnt > 0) ; i++) {
- flash_add_byte(info, &cword, *src++);
- cnt--;
- cp++;
- }
- for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
- flash_add_byte(info, &cword, (*(uchar *)cp));
- if((rc = flash_write_cfiword(info, wp, cword)) != 0)
- return rc;
- wp = cp;
- }
-
-#ifdef CFG_FLASH_USE_BUFFER_WRITE
- while(cnt >= info->portwidth) {
- i = info->buffer_size > cnt? cnt: info->buffer_size;
- if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK)
- return rc;
- wp += i;
- src += i;
- cnt -=i;
- }
-#else
- /* handle the aligned part */
- while(cnt >= info->portwidth) {
- cword.l = 0;
- for(i = 0; i < info->portwidth; i++) {
- flash_add_byte(info, &cword, *src++);
- }
- if((rc = flash_write_cfiword(info, wp, cword)) != 0)
- return rc;
- wp += info->portwidth;
- cnt -= info->portwidth;
- }
-#endif /* CFG_FLASH_USE_BUFFER_WRITE */
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- cword.l = 0;
- for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) {
- flash_add_byte(info, &cword, *src++);
- --cnt;
- }
- for (; i<info->portwidth; ++i, ++cp) {
- flash_add_byte(info, & cword, (*(uchar *)cp));
- }
-
- return flash_write_cfiword(info, wp, cword);
-}
-
-/*-----------------------------------------------------------------------
- */
-int flash_real_protect(flash_info_t *info, long sector, int prot)
-{
- int retcode = 0;
-
- flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
- if(prot)
- flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
- else
- flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
-
- if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout,
- prot?"protect":"unprotect")) == 0) {
-
- info->protect[sector] = prot;
- /* Intel's unprotect unprotects all locking */
- if(prot == 0) {
- int i;
- for(i = 0 ; i<info->sector_count; i++) {
- if(info->protect[i])
- flash_real_protect(info, i, 1);
- }
- }
- }
-
- return retcode;
-}
-/*-----------------------------------------------------------------------
- * wait for XSR.7 to be set. Time out with an error if it does not.
- * This routine does not set the flash to read-array mode.
- */
-static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
-{
- ulong start;
-
- /* Wait for command completion */
- start = get_timer (0);
- while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
- if (get_timer(start) > info->erase_blk_tout) {
- printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]);
- flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
- return ERR_TIMOUT;
- }
- }
- return ERR_OK;
-}
-/*-----------------------------------------------------------------------
- * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
- * This routine sets the flash to read-array mode.
- */
-static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
-{
- int retcode;
- retcode = flash_status_check(info, sector, tout, prompt);
- if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) {
- retcode = ERR_INVAL;
- printf("Flash %s error at address %lx\n", prompt,info->start[sector]);
- if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){
- printf("Command Sequence Error.\n");
- } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){
- printf("Block Erase Error.\n");
- retcode = ERR_NOT_ERASED;
- } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
- printf("Locking Error\n");
- }
- if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){
- printf("Block locked.\n");
- retcode = ERR_PROTECTED;
- }
- if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
- printf("Vpp Low Error.\n");
- }
- flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
- return retcode;
-}
-/*-----------------------------------------------------------------------
- */
-static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c)
-{
- switch(info->portwidth) {
- case FLASH_CFI_8BIT:
- cword->c = c;
- break;
- case FLASH_CFI_16BIT:
- cword->w = (cword->w << 8) | c;
- break;
- case FLASH_CFI_32BIT:
- cword->l = (cword->l << 8) | c;
- }
-}
-
-
-/*-----------------------------------------------------------------------
- * make a proper sized command based on the port and chip widths
- */
-static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf)
-{
- int i;
- uchar *cp = (uchar *)cmdbuf;
- for(i=0; i< info->portwidth; i++)
- *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd;
-}
-
-/*
- * Write a proper sized command to the correct address
- */
-static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd)
-{
-
- volatile cfiptr_t addr;
- cfiword_t cword;
- addr.cp = flash_make_addr(info, sect, offset);
- flash_make_cmd(info, cmd, &cword);
- switch(info->portwidth) {
- case FLASH_CFI_8BIT:
- *addr.cp = cword.c;
- break;
- case FLASH_CFI_16BIT:
- *addr.wp = cword.w;
- break;
- case FLASH_CFI_32BIT:
- *addr.lp = cword.l;
- break;
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd)
-{
- cfiptr_t cptr;
- cfiword_t cword;
- int retval;
- cptr.cp = flash_make_addr(info, sect, offset);
- flash_make_cmd(info, cmd, &cword);
- switch(info->portwidth) {
- case FLASH_CFI_8BIT:
- retval = (cptr.cp[0] == cword.c);
- break;
- case FLASH_CFI_16BIT:
- retval = (cptr.wp[0] == cword.w);
- break;
- case FLASH_CFI_32BIT:
- retval = (cptr.lp[0] == cword.l);
- break;
- default:
- retval = 0;
- break;
- }
- return retval;
-}
-/*-----------------------------------------------------------------------
- */
-static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd)
-{
- cfiptr_t cptr;
- cfiword_t cword;
- int retval;
- cptr.cp = flash_make_addr(info, sect, offset);
- flash_make_cmd(info, cmd, &cword);
- switch(info->portwidth) {
- case FLASH_CFI_8BIT:
- retval = ((cptr.cp[0] & cword.c) == cword.c);
- break;
- case FLASH_CFI_16BIT:
- retval = ((cptr.wp[0] & cword.w) == cword.w);
- break;
- case FLASH_CFI_32BIT:
- retval = ((cptr.lp[0] & cword.l) == cword.l);
- break;
- default:
- retval = 0;
- break;
- }
- return retval;
-}
-
-/*-----------------------------------------------------------------------
- * detect if flash is compatible with the Common Flash Interface (CFI)
- * http://www.jedec.org/download/search/jesd68.pdf
- *
- */
-static int flash_detect_cfi(flash_info_t * info)
-{
-
- for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT;
- info->portwidth <<= 1) {
- for(info->chipwidth =FLASH_CFI_BY8;
- info->chipwidth <= info->portwidth;
- info->chipwidth <<= 1) {
- flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
- flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
- if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') &&
- flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
- flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y'))
- return 1;
- }
- }
- return 0;
-}
-/*
- * The following code cannot be run from FLASH!
- *
- */
-static ulong flash_get_size (ulong base, int banknum)
-{
- flash_info_t * info = &flash_info[banknum];
- int i, j;
- int sect_cnt;
- unsigned long sector;
- unsigned long tmp;
- int size_ratio;
- uchar num_erase_regions;
- int erase_region_size;
- int erase_region_count;
-
- info->start[0] = base;
-
- if(flash_detect_cfi(info)){
-#ifdef DEBUG_FLASH
- printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */
-#endif
- size_ratio = info->portwidth / info->chipwidth;
- num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
-#ifdef DEBUG_FLASH
- printf("found %d erase regions\n", num_erase_regions);
-#endif
- sect_cnt = 0;
- sector = base;
- for(i = 0 ; i < num_erase_regions; i++) {
- if(i > NUM_ERASE_REGIONS) {
- printf("%d erase regions found, only %d used\n",
- num_erase_regions, NUM_ERASE_REGIONS);
- break;
- }
- tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS);
- erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128;
- tmp >>= 16;
- erase_region_count = (tmp & 0xffff) +1;
- for(j = 0; j< erase_region_count; j++) {
- info->start[sect_cnt] = sector;
- sector += (erase_region_size * size_ratio);
- info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT);
- sect_cnt++;
- }
- }
-
- info->sector_count = sect_cnt;
- /* multiply the size by the number of chips */
- info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio;
- info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
- tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
- info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
- tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
- info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
- tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
- info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000;
- info->flash_id = FLASH_MAN_CFI;
- }
-
- flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
- return(info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword)
-{
-
- cfiptr_t ctladdr;
- cfiptr_t cptr;
- int flag;
-
- ctladdr.cp = flash_make_addr(info, 0, 0);
- cptr.cp = (uchar *)dest;
-
-
- /* Check if Flash is (sufficiently) erased */
- switch(info->portwidth) {
- case FLASH_CFI_8BIT:
- flag = ((cptr.cp[0] & cword.c) == cword.c);
- break;
- case FLASH_CFI_16BIT:
- flag = ((cptr.wp[0] & cword.w) == cword.w);
- break;
- case FLASH_CFI_32BIT:
- flag = ((cptr.lp[0] & cword.l) == cword.l);
- break;
- default:
- return 2;
- }
- if(!flag)
- return 2;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
-
- switch(info->portwidth) {
- case FLASH_CFI_8BIT:
- cptr.cp[0] = cword.c;
- break;
- case FLASH_CFI_16BIT:
- cptr.wp[0] = cword.w;
- break;
- case FLASH_CFI_32BIT:
- cptr.lp[0] = cword.l;
- break;
- }
-
- /* re-enable interrupts if necessary */
- if(flag)
- enable_interrupts();
-
- return flash_full_status_check(info, 0, info->write_tout, "write");
-}
-
-#ifdef CFG_FLASH_USE_BUFFER_WRITE
-
-/* loop through the sectors from the highest address
- * when the passed address is greater or equal to the sector address
- * we have a match
- */
-static int find_sector(flash_info_t *info, ulong addr)
-{
- int sector;
- for(sector = info->sector_count - 1; sector >= 0; sector--) {
- if(addr >= info->start[sector])
- break;
- }
- return sector;
-}
-
-static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len)
-{
-
- int sector;
- int cnt;
- int retcode;
- volatile cfiptr_t src;
- volatile cfiptr_t dst;
-
- src.cp = cp;
- dst.cp = (uchar *)dest;
- sector = find_sector(info, dest);
- flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
- if((retcode = flash_status_check(info, sector, info->buffer_write_tout,
- "write to buffer")) == ERR_OK) {
- switch(info->portwidth) {
- case FLASH_CFI_8BIT:
- cnt = len;
- break;
- case FLASH_CFI_16BIT:
- cnt = len >> 1;
- break;
- case FLASH_CFI_32BIT:
- cnt = len >> 2;
- break;
- default:
- return ERR_INVAL;
- break;
- }
- flash_write_cmd(info, sector, 0, (uchar)cnt-1);
- while(cnt-- > 0) {
- switch(info->portwidth) {
- case FLASH_CFI_8BIT:
- *dst.cp++ = *src.cp++;
- break;
- case FLASH_CFI_16BIT:
- *dst.wp++ = *src.wp++;
- break;
- case FLASH_CFI_32BIT:
- *dst.lp++ = *src.lp++;
- break;
- default:
- return ERR_INVAL;
- break;
- }
- }
- flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM);
- retcode = flash_full_status_check(info, sector, info->buffer_write_tout,
- "buffer write");
- }
- flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
- return retcode;
-}
-#endif /* CFG_USE_FLASH_BUFFER_WRITE */
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
-/* .resetvec 0x01FFFFFC :*/
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xFFFFF000 :
-/* .bootpg 0x01FFF000 :*/
- {
- cpu/ppc4xx/start.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
- board/esd/cpci440/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
-/* . = env_offset;*/
-/* common/environment.o(.text)*/
-
- *(.text)
- *(.fixup)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- _end = . ;
- PROVIDE (end = .);
-}
cpu/ppc4xx/start.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
cpu/ppc4xx/start.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/iop480_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
cpu/ppc4xx/start.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
cpu/ppc4xx/4xx_enet.o (.text)
cpu/ppc4xx/start.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
cpu/ppc4xx/start.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
cpu/ppc4xx/start.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
cpu/ppc4xx/4xx_enet.o (.text)
#include <command.h>
#include <pci.h>
#include <pci_ids.h>
-#include <405gp_pci.h>
+#include <asm/4xx_pci.h>
#if defined(CONFIG_CMD_BSP)
cpu/ppc4xx/start.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
#include <net.h>
#include <asm/io.h>
#include <pci.h>
-#include <405gp_pci.h>
+#include <asm/4xx_pci.h>
#include <asm/processor.h>
#include "pci405.h"
#include <command.h>
#include <malloc.h>
#include <pci.h>
-#include <405gp_pci.h>
+#include <asm/4xx_pci.h>
#include "pci405.h"
cpu/ppc4xx/start.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
int misc_init_r (void)
{
- volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
- volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
+ unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
+ unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
unsigned char *dst;
ulong len = sizeof(fpgadata);
int status;
/*
* Reset external DUARTs
*/
- out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_DUART_RST);
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
udelay(10); /* wait 10us */
- out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_DUART_RST);
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
udelay(1000); /* wait 1ms */
+ /*
+ * Set NAND-FLASH GPIO signals to default
+ */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_NAND_CE);
+
+ /*
+ * Setup EEPROM write protection
+ */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
+ out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_EEPROM_WP);
+
/*
* Enable interrupts in exar duart mcr[3]
*/
- *duart0_mcr = 0x08;
- *duart1_mcr = 0x08;
+ out_8(duart0_mcr, 0x08);
+ out_8(duart1_mcr, 0x08);
return (0);
}
lxt971_no_sleep();
#endif
}
+
+
+#if defined(CFG_EEPROM_WREN)
+/* Input: <dev_addr> I2C address of EEPROM device to enable.
+ * <state> -1: deliver current state
+ * 0: disable write
+ * 1: enable write
+ * Returns: -1: wrong device address
+ * 0: dis-/en- able done
+ * 0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable (unsigned dev_addr, int state)
+{
+ if (CFG_I2C_EEPROM_ADDR != dev_addr) {
+ return -1;
+ } else {
+ switch (state) {
+ case 1:
+ /* Enable write access, clear bit GPIO0. */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_EEPROM_WP);
+ state = 0;
+ break;
+ case 0:
+ /* Disable write access, set bit GPIO0. */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
+ state = 0;
+ break;
+ default:
+ /* Read current status back. */
+ state = (0 == (in_be32((void*)GPIO0_OR) & CFG_EEPROM_WP));
+ break;
+ }
+ }
+ return state;
+}
+
+int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ int query = argc == 1;
+ int state = 0;
+
+ if (query) {
+ /* Query write access state. */
+ state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
+ if (state < 0) {
+ puts ("Query of write access state failed.\n");
+ } else {
+ printf ("Write access for device 0x%0x is %sabled.\n",
+ CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
+ state = 0;
+ }
+ } else {
+ if ('0' == argv[1][0]) {
+ /* Disable write access. */
+ state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
+ } else {
+ /* Enable write access. */
+ state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
+ }
+ if (state < 0) {
+ puts ("Setup of write access state failed.\n");
+ }
+ }
+
+ return state;
+}
+
+U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
+ "eepwren - Enable / disable / query EEPROM write access\n",
+ NULL);
+#endif /* #if defined(CFG_EEPROM_WREN) */
cpu/ppc4xx/start.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
cpu/ppc4xx/4xx_enet.o (.text)
cpu/ppc4xx/start.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
--- /dev/null
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS = $(BOARD).o cmd_pmc440.o sdram.o fpga.o \
+ ../common/cmd_loadpci.o
+
+SOBJS = init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Matthias Fuchs, esd Gmbh, matthias.fuchs@esd-electronics.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <asm/processor.h>
+
+#include "pmc440.h"
+
+int is_monarch(void);
+int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt);
+int eeprom_write_enable(unsigned dev_addr, int state);
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_BSP)
+
+static int got_fifoirq;
+static int got_hcirq;
+
+int fpga_interrupt(u32 arg)
+{
+ pmc440_fpga_t *fpga = (pmc440_fpga_t *)arg;
+ int rc = -1; /* not for us */
+ u32 status = FPGA_IN32(&fpga->status);
+
+ /* check for interrupt from fifo module */
+ if (status & STATUS_FIFO_ISF) {
+ /* disable this int source */
+ FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
+ rc = 0;
+ got_fifoirq = 1; /* trigger backend */
+ }
+
+ if (status & STATUS_HOST_ISF) {
+ FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);
+ rc = 0;
+ got_hcirq = 1;
+ }
+
+ return rc;
+}
+
+
+int do_waithci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+
+ got_hcirq = 0;
+
+ FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
+ FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);
+
+ irq_install_handler(IRQ0_FPGA,
+ (interrupt_handler_t *)fpga_interrupt,
+ fpga);
+
+ FPGA_SETBITS(&fpga->ctrla, CTRL_HOST_IE);
+
+ while (!got_hcirq) {
+ /* Abort if ctrl-c was pressed */
+ if (ctrlc()) {
+ puts("\nAbort\n");
+ break;
+ }
+ }
+ if (got_hcirq)
+ printf("Got interrupt!\n");
+
+ FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
+ irq_free_handler(IRQ0_FPGA);
+ return 0;
+}
+U_BOOT_CMD(
+ waithci, 1, 1, do_waithci,
+ "waithci - Wait for host control interrupt\n",
+ NULL
+ );
+
+
+void dump_fifo(pmc440_fpga_t *fpga, int f, int *n)
+{
+ u32 ctrl;
+
+ while (!((ctrl = FPGA_IN32(&fpga->fifo[f].ctrl)) & FIFO_EMPTY)) {
+ printf("%5d %d %3d %08x",
+ (*n)++, f, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL),
+ FPGA_IN32(&fpga->fifo[f].data));
+ if (ctrl & FIFO_OVERFLOW) {
+ printf(" OVERFLOW\n");
+ FPGA_CLRBITS(&fpga->fifo[f].ctrl, FIFO_OVERFLOW);
+ } else
+ printf("\n");
+ }
+}
+
+
+int do_fifo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+ int i;
+ int n = 0;
+ u32 ctrl, data, f;
+ char str[] = "\\|/-";
+ int abort = 0;
+ int count = 0;
+ int count2 = 0;
+
+ switch (argc) {
+ case 1:
+ /* print all fifos status information */
+ printf("fifo level status\n");
+ printf("______________________________\n");
+ for (i=0; i<FIFO_COUNT; i++) {
+ ctrl = FPGA_IN32(&fpga->fifo[i].ctrl);
+ printf(" %d %3d %s%s%s %s\n",
+ i, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL),
+ ctrl & FIFO_FULL ? "FULL " : "",
+ ctrl & FIFO_EMPTY ? "EMPTY " : "",
+ ctrl & (FIFO_FULL|FIFO_EMPTY) ? "" : "NOT EMPTY",
+ ctrl & FIFO_OVERFLOW ? "OVERFLOW" : "");
+ }
+ break;
+
+ case 2:
+ /* completely read out fifo 'n' */
+ if (!strcmp(argv[1],"read")) {
+ printf(" # fifo level data\n");
+ printf("______________________________\n");
+
+ for (i=0; i<FIFO_COUNT; i++)
+ dump_fifo(fpga, i, &n);
+
+ } else if (!strcmp(argv[1],"wait")) {
+ got_fifoirq = 0;
+
+ irq_install_handler(IRQ0_FPGA,
+ (interrupt_handler_t *)fpga_interrupt,
+ fpga);
+
+ printf(" # fifo level data\n");
+ printf("______________________________\n");
+
+ /* enable all fifo interrupts */
+ FPGA_OUT32(&fpga->hostctrl,
+ HOSTCTRL_FIFOIE_GATE | HOSTCTRL_FIFOIE_FLAG);
+ for (i=0; i<FIFO_COUNT; i++) {
+ /* enable interrupts from all fifos */
+ FPGA_SETBITS(&fpga->fifo[i].ctrl, FIFO_IE);
+ }
+
+ while (1) {
+ /* wait loop */
+ while (!got_fifoirq) {
+ count++;
+ if (!(count % 100)) {
+ count2++;
+ putc(0x08); /* backspace */
+ putc(str[count2 % 4]);
+ }
+
+ /* Abort if ctrl-c was pressed */
+ if ((abort = ctrlc())) {
+ puts("\nAbort\n");
+ break;
+ }
+ udelay(1000);
+ }
+ if (abort)
+ break;
+
+ /* simple fifo backend */
+ if (got_fifoirq) {
+ for (i=0; i<FIFO_COUNT; i++)
+ dump_fifo(fpga, i, &n);
+
+ got_fifoirq = 0;
+ /* unmask global fifo irq */
+ FPGA_OUT32(&fpga->hostctrl,
+ HOSTCTRL_FIFOIE_GATE | HOSTCTRL_FIFOIE_FLAG);
+ }
+ }
+
+ /* disable all fifo interrupts */
+ FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
+ for (i=0; i<FIFO_COUNT; i++)
+ FPGA_CLRBITS(&fpga->fifo[i].ctrl, FIFO_IE);
+
+ irq_free_handler(IRQ0_FPGA);
+
+ } else {
+ printf("Usage:\nfifo %s\n", cmdtp->help);
+ return 1;
+ }
+ break;
+
+ case 4:
+ case 5:
+ if (!strcmp(argv[1],"write")) {
+ /* get fifo number or fifo address */
+ f = simple_strtoul(argv[2], NULL, 16);
+
+ /* data paramter */
+ data = simple_strtoul(argv[3], NULL, 16);
+
+ /* get optional count parameter */
+ n = 1;
+ if (argc >= 5)
+ n = (int)simple_strtoul(argv[4], NULL, 10);
+
+ if (f < FIFO_COUNT) {
+ printf("writing %d x %08x to fifo %d\n",
+ n, data, f);
+ for (i=0; i<n; i++)
+ FPGA_OUT32(&fpga->fifo[f].data, data);
+ } else {
+ printf("writing %d x %08x to fifo port at address %08x\n",
+ n, data, f);
+ for (i=0; i<n; i++)
+ out32(f, data);
+ }
+ } else {
+ printf("Usage:\nfifo %s\n", cmdtp->help);
+ return 1;
+ }
+ break;
+
+ default:
+ printf("Usage:\nfifo %s\n", cmdtp->help);
+ return 1;
+ }
+ return 0;
+}
+U_BOOT_CMD(
+ fifo, 5, 1, do_fifo,
+ "fifo - Fifo module operations\n",
+ "wait\nfifo read\n"
+ "fifo write fifo(0..3) data [cnt=1]\n"
+ "fifo write address(>=4) data [cnt=1]\n"
+ " - without arguments: print all fifo's status\n"
+ " - with 'wait' argument: interrupt driven read from all fifos\n"
+ " - with 'read' argument: read current contents from all fifos\n"
+ " - with 'write' argument: write 'data' 'cnt' times to 'fifo' or 'address'\n"
+ );
+
+
+int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ ulong sdsdp[5];
+ ulong delay;
+ int count=16;
+
+ if (argc < 2) {
+ printf("Usage:\nsbe %s\n", cmdtp->help);
+ return -1;
+ }
+
+ if (argc > 1) {
+ if (!strcmp(argv[1], "400")) {
+ /* PLB=133MHz, PLB/PCI=4 */
+ printf("Bootstrapping for 400MHz\n");
+ sdsdp[0]=0x8678624e;
+ sdsdp[1]=0x0947a030;
+ sdsdp[2]=0x40082350;
+ sdsdp[3]=0x0d050000;
+ } else if (!strcmp(argv[1], "533")) {
+ /* PLB=133MHz, PLB/PCI=3 */
+ printf("Bootstrapping for 533MHz\n");
+ sdsdp[0]=0x87788252;
+ sdsdp[1]=0x095fa030;
+ sdsdp[2]=0x40082350;
+ sdsdp[3]=0x0d050000;
+ } else if (!strcmp(argv[1], "667")) {
+ /* PLB=133MHz, PLB/PCI=4 */
+ printf("Bootstrapping for 667MHz\n");
+ sdsdp[0]=0x8778a256;
+ sdsdp[1]=0x0947a030;
+ sdsdp[2]=0x40082350;
+ sdsdp[3]=0x0d050000;
+ } else if (!strcmp(argv[1], "test")) {
+ /* TODO: this will replace the 667 MHz config above.
+ * But it needs some more testing on a real 667 MHz CPU.
+ */
+ printf("Bootstrapping for test (667MHz PLB=133PLB PLB/PCI=3)\n");
+ sdsdp[0]=0x8778a256;
+ sdsdp[1]=0x095fa030;
+ sdsdp[2]=0x40082350;
+ sdsdp[3]=0x0d050000;
+ } else {
+ printf("Usage:\nsbe %s\n", cmdtp->help);
+ return -1;
+ }
+ }
+
+ if (argc > 2) {
+ sdsdp[4] = 0;
+ if (argv[2][0]=='1')
+ sdsdp[4]=0x19750100;
+ else if (argv[2][0]=='0')
+ sdsdp[4]=0x19750000;
+ if (sdsdp[4])
+ count += 4;
+ }
+
+ if (argc > 3) {
+ delay = simple_strtoul(argv[3], NULL, 10);
+ if (delay > 20)
+ delay = 20;
+ sdsdp[4] |= delay;
+ }
+
+ printf("Writing boot EEPROM ...\n");
+ if (bootstrap_eeprom_write(CFG_I2C_BOOT_EEPROM_ADDR,
+ 0, (uchar*)sdsdp, count) != 0)
+ printf("bootstrap_eeprom_write failed\n");
+ else
+ printf("done (dump via 'i2c md 52 0.1 14')\n");
+
+ return 0;
+}
+U_BOOT_CMD(
+ sbe, 4, 0, do_setup_bootstrap_eeprom,
+ "sbe - setup bootstrap eeprom\n",
+ "<cpufreq:400|533|667> [<console-uart:0|1> [<bringup delay (0..20s)>]]"
+ );
+
+
+#if defined(CONFIG_PRAM)
+#include <environment.h>
+extern env_t *env_ptr;
+
+int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ u32 memsize;
+ u32 pram, env_base;
+ char *v;
+ u32 param;
+ ulong *lptr;
+
+ memsize = gd->bd->bi_memsize;
+
+ v = getenv("pram");
+ if (v)
+ pram = simple_strtoul(v, NULL, 10);
+ else {
+ printf("Error: pram undefined. Please define pram in KiB\n");
+ return 1;
+ }
+
+ param = memsize - (pram << 10);
+ printf("PARAM: @%08x\n", param);
+
+ memset((void*)param, 0, (pram << 10));
+ env_base = memsize - 4096 - ((CFG_ENV_SIZE + 4096) & ~(4096-1));
+ memcpy((void*)env_base, env_ptr, CFG_ENV_SIZE);
+
+ lptr = (ulong*)memsize;
+ *(--lptr) = CFG_ENV_SIZE;
+ *(--lptr) = memsize - env_base;
+ *(--lptr) = crc32(0, (void*)(memsize - 0x08), 0x08);
+ *(--lptr) = 0;
+
+ /* make sure data can be accessed through PCI */
+ flush_dcache_range(param, param + (pram << 10) - 1);
+ return 0;
+}
+U_BOOT_CMD(
+ painit, 1, 1, do_painit,
+ "painit - prepare PciAccess system\n",
+ NULL
+ );
+#endif /* CONFIG_PRAM */
+
+
+int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ if (argc > 1) {
+ if (argv[1][0] == '0') {
+ /* assert */
+ printf("self-reset# asserted\n");
+ out_be32((void*)GPIO0_TCR,
+ in_be32((void*)GPIO0_TCR) | GPIO0_SELF_RST);
+ } else {
+ /* deassert */
+ printf("self-reset# deasserted\n");
+ out_be32((void*)GPIO0_TCR,
+ in_be32((void*)GPIO0_TCR) & ~GPIO0_SELF_RST);
+ }
+ } else {
+ printf("self-reset# is %s\n",
+ in_be32((void*)GPIO0_TCR) & GPIO0_SELF_RST ?
+ "active" : "inactive");
+ }
+
+ return 0;
+}
+U_BOOT_CMD(
+ selfreset, 2, 1, do_selfreset,
+ "selfreset- assert self-reset# signal\n",
+ NULL
+ );
+
+
+int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+
+ /* requiers bootet FPGA and PLD_IOEN_N active */
+ if (in_be32((void*)GPIO1_OR) & GPIO1_IOEN_N) {
+ printf("Error: resetout requires a bootet FPGA\n");
+ return -1;
+ }
+
+ if (argc > 1) {
+ if (argv[1][0] == '0') {
+ /* assert */
+ printf("PMC-RESETOUT# asserted\n");
+ FPGA_OUT32(&fpga->hostctrl,
+ HOSTCTRL_PMCRSTOUT_GATE);
+ } else {
+ /* deassert */
+ printf("PMC-RESETOUT# deasserted\n");
+ FPGA_OUT32(&fpga->hostctrl,
+ HOSTCTRL_PMCRSTOUT_GATE | HOSTCTRL_PMCRSTOUT_FLAG);
+ }
+ } else {
+ printf("PMC-RESETOUT# is %s\n",
+ FPGA_IN32(&fpga->hostctrl) & HOSTCTRL_PMCRSTOUT_FLAG ?
+ "inactive" : "active");
+ }
+
+ return 0;
+}
+U_BOOT_CMD(
+ resetout, 2, 1, do_resetout,
+ "resetout - assert PMC-RESETOUT# signal\n",
+ NULL
+ );
+
+
+int do_inta(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ if (is_monarch()) {
+ printf("This command is only supported in non-monarch mode\n");
+ return -1;
+ }
+
+ if (argc > 1) {
+ if (argv[1][0] == '0') {
+ /* assert */
+ printf("inta# asserted\n");
+ out_be32((void*)GPIO1_TCR,
+ in_be32((void*)GPIO1_TCR) | GPIO1_INTA_FAKE);
+ } else {
+ /* deassert */
+ printf("inta# deasserted\n");
+ out_be32((void*)GPIO1_TCR,
+ in_be32((void*)GPIO1_TCR) & ~GPIO1_INTA_FAKE);
+ }
+ } else {
+ printf("inta# is %s\n", in_be32((void*)GPIO1_TCR) & GPIO1_INTA_FAKE ? "active" : "inactive");
+ }
+ return 0;
+}
+U_BOOT_CMD(
+ inta, 2, 1, do_inta,
+ "inta - Assert/Deassert or query INTA# state in non-monarch mode\n",
+ NULL
+ );
+
+
+/* test-only */
+int do_pmm(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ ulong pciaddr;
+
+ if (argc > 1) {
+ pciaddr = simple_strtoul(argv[1], NULL, 16);
+
+ pciaddr &= 0xf0000000;
+
+ /* map PCI address at 0xc0000000 in PLB space */
+ out32r(PCIX0_PMM1MA, 0x00000000); /* PMM1 Mask/Attribute - disabled b4 setting */
+ out32r(PCIX0_PMM1LA, 0xc0000000); /* PMM1 Local Address */
+ out32r(PCIX0_PMM1PCILA, pciaddr); /* PMM1 PCI Low Address */
+ out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM1 PCI High Address */
+ out32r(PCIX0_PMM1MA, 0xf0000001); /* 256MB + No prefetching, and enable region */
+ } else {
+ printf("Usage:\npmm %s\n", cmdtp->help);
+ }
+ return 0;
+}
+U_BOOT_CMD(
+ pmm, 2, 1, do_pmm,
+ "pmm - Setup pmm[1] registers\n",
+ "<pciaddr> (pciaddr will be aligned to 256MB)\n"
+ );
+
+#if defined(CFG_EEPROM_WREN)
+int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ int query = argc == 1;
+ int state = 0;
+
+ if (query) {
+ /* Query write access state. */
+ state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, -1);
+ if (state < 0) {
+ puts("Query of write access state failed.\n");
+ } else {
+ printf("Write access for device 0x%0x is %sabled.\n",
+ CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
+ state = 0;
+ }
+ } else {
+ if ('0' == argv[1][0]) {
+ /* Disable write access. */
+ state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 0);
+ } else {
+ /* Enable write access. */
+ state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 1);
+ }
+ if (state < 0) {
+ puts("Setup of write access state failed.\n");
+ }
+ }
+
+ return state;
+}
+U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
+ "eepwren - Enable / disable / query EEPROM write access\n",
+ NULL);
+#endif /* #if defined(CFG_EEPROM_WREN) */
+
+#endif /* CONFIG_CMD_BSP */
--- /dev/null
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+# AMCC 440EPx Reference Platform (Sequoia) board
+#
+
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+TEXT_BASE = 0xFFFA0000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <spartan2.h>
+#include <spartan3.h>
+#include <command.h>
+#include "fpga.h"
+#include "pmc440.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_FPGA)
+
+#define USE_SP_CODE
+
+#ifdef USE_SP_CODE
+Xilinx_Spartan3_Slave_Parallel_fns pmc440_fpga_fns = {
+ fpga_pre_config_fn,
+ fpga_pgm_fn,
+ fpga_init_fn,
+ NULL, /* err */
+ fpga_done_fn,
+ fpga_clk_fn,
+ fpga_cs_fn,
+ fpga_wr_fn,
+ NULL, /* rdata */
+ fpga_wdata_fn,
+ fpga_busy_fn,
+ fpga_abort_fn,
+ fpga_post_config_fn,
+};
+#else
+Xilinx_Spartan3_Slave_Serial_fns pmc440_fpga_fns = {
+ fpga_pre_config_fn,
+ fpga_pgm_fn,
+ fpga_clk_fn,
+ fpga_init_fn,
+ fpga_done_fn,
+ fpga_wr_fn,
+ fpga_post_config_fn,
+};
+#endif
+
+Xilinx_Spartan2_Slave_Serial_fns ngcc_fpga_fns = {
+ ngcc_fpga_pre_config_fn,
+ ngcc_fpga_pgm_fn,
+ ngcc_fpga_clk_fn,
+ ngcc_fpga_init_fn,
+ ngcc_fpga_done_fn,
+ ngcc_fpga_wr_fn,
+ ngcc_fpga_post_config_fn
+};
+
+Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
+ XILINX_XC3S1200E_DESC(
+#ifdef USE_SP_CODE
+ slave_parallel,
+#else
+ slave_serial,
+#endif
+ (void *)&pmc440_fpga_fns,
+ 0),
+ XILINX_XC2S200_DESC(
+ slave_serial,
+ (void *)&ngcc_fpga_fns,
+ 0)
+};
+
+
+/*
+ * Set the active-low FPGA reset signal.
+ */
+void fpga_reset(int assert)
+{
+ debug("%s:%d: RESET ", __FUNCTION__, __LINE__);
+ if (assert) {
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_DATA);
+ debug("asserted\n");
+ } else {
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_DATA);
+ debug("deasserted\n");
+ }
+}
+
+
+/*
+ * Initialize the SelectMap interface. We assume that the mode and the
+ * initial state of all of the port pins have already been set!
+ */
+void fpga_serialslave_init(void)
+{
+ debug("%s:%d: Initialize serial slave interface\n", __FUNCTION__,
+ __LINE__);
+ fpga_pgm_fn(FALSE, FALSE, 0); /* make sure program pin is inactive */
+}
+
+
+/*
+ * Set the FPGA's active-low SelectMap program line to the specified level
+ */
+int fpga_pgm_fn(int assert, int flush, int cookie)
+{
+ debug("%s:%d: FPGA PROGRAM ",
+ __FUNCTION__, __LINE__);
+
+ if (assert) {
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_PRG);
+ debug("asserted\n");
+ } else {
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_PRG);
+ debug("deasserted\n");
+ }
+ return assert;
+}
+
+
+/*
+ * Test the state of the active-low FPGA INIT line. Return 1 on INIT
+ * asserted (low).
+ */
+int fpga_init_fn(int cookie)
+{
+ if (in_be32((void*)GPIO1_IR) & GPIO1_FPGA_INIT)
+ return 0;
+ else
+ return 1;
+}
+
+#ifdef USE_SP_CODE
+int fpga_abort_fn(int cookie)
+{
+ return 0;
+}
+
+
+int fpga_cs_fn(int assert_cs, int flush, int cookie)
+{
+ return assert_cs;
+}
+
+
+int fpga_busy_fn(int cookie)
+{
+ return 1;
+}
+#endif
+
+
+/*
+ * Test the state of the active-high FPGA DONE pin
+ */
+int fpga_done_fn(int cookie)
+{
+ if (in_be32((void*)GPIO1_IR) & GPIO1_FPGA_DONE)
+ return 1;
+ else
+ return 0;
+}
+
+
+/*
+ * FPGA pre-configuration function. Just make sure that
+ * FPGA reset is asserted to keep the FPGA from starting up after
+ * configuration.
+ */
+int fpga_pre_config_fn(int cookie)
+{
+ debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
+ fpga_reset(TRUE);
+
+ /* release init# */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | GPIO0_FPGA_FORCEINIT);
+ /* disable PLD IOs */
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_IOEN_N);
+ return 0;
+}
+
+
+/*
+ * FPGA post configuration function. Blip the FPGA reset line and then see if
+ * the FPGA appears to be running.
+ */
+int fpga_post_config_fn(int cookie)
+{
+ pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+ int rc=0;
+ char *s;
+
+ debug("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__);
+
+ /* enable PLD0..7 pins */
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_IOEN_N);
+
+ fpga_reset(TRUE);
+ udelay (100);
+ fpga_reset(FALSE);
+ udelay (100);
+
+ FPGA_OUT32(&fpga->status, (gd->board_type << STATUS_HWREV_SHIFT) & STATUS_HWREV_MASK);
+
+ /* NGCC only: enable ledlink */
+ if ((s = getenv("bd_type")) && !strcmp(s, "ngcc"))
+ FPGA_SETBITS(&fpga->ctrla, 0x29f8c000);
+
+ return rc;
+}
+
+
+int fpga_clk_fn(int assert_clk, int flush, int cookie)
+{
+ if (assert_clk)
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_CLK);
+ else
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_CLK);
+
+ return assert_clk;
+}
+
+
+int fpga_wr_fn(int assert_write, int flush, int cookie)
+{
+ if (assert_write)
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_DATA);
+ else
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_DATA);
+
+ return assert_write;
+}
+
+#ifdef USE_SP_CODE
+int fpga_wdata_fn(uchar data, int flush, int cookie)
+{
+ uchar val = data;
+ ulong or = in_be32((void*)GPIO1_OR);
+ int i = 7;
+ do {
+ /* Write data */
+ if (val & 0x80)
+ or = (or & ~GPIO1_FPGA_CLK) | GPIO1_FPGA_DATA;
+ else
+ or = or & ~(GPIO1_FPGA_CLK | GPIO1_FPGA_DATA);
+
+ out_be32((void*)GPIO1_OR, or);
+
+ /* Assert the clock */
+ or |= GPIO1_FPGA_CLK;
+ out_be32((void*)GPIO1_OR, or);
+ val <<= 1;
+ i --;
+ } while (i > 0);
+
+ /* Write last data bit (the 8th clock comes from the sp_load() code */
+ if (val & 0x80)
+ or = (or & ~GPIO1_FPGA_CLK) | GPIO1_FPGA_DATA;
+ else
+ or = or & ~(GPIO1_FPGA_CLK | GPIO1_FPGA_DATA);
+
+ out_be32((void*)GPIO1_OR, or);
+
+ return 0;
+}
+#endif
+
+#define NGCC_FPGA_PRG CLOCK_EN
+#define NGCC_FPGA_DATA RESET_OUT
+#define NGCC_FPGA_DONE CLOCK_IN
+#define NGCC_FPGA_INIT IRIGB_R_IN
+#define NGCC_FPGA_CLK CLOCK_OUT
+
+void ngcc_fpga_serialslave_init(void)
+{
+ debug("%s:%d: Initialize serial slave interface\n",
+ __FUNCTION__, __LINE__);
+
+ /* make sure program pin is inactive */
+ ngcc_fpga_pgm_fn (FALSE, FALSE, 0);
+}
+
+/*
+ * Set the active-low FPGA reset signal.
+ */
+void ngcc_fpga_reset(int assert)
+{
+ debug("%s:%d: RESET ", __FUNCTION__, __LINE__);
+
+ if (assert) {
+ FPGA_CLRBITS(NGCC_CTRL_BASE, NGCC_CTRL_FPGARST_N);
+ debug("asserted\n");
+ } else {
+ FPGA_SETBITS(NGCC_CTRL_BASE, NGCC_CTRL_FPGARST_N);
+ debug("deasserted\n");
+ }
+}
+
+
+/*
+ * Set the FPGA's active-low SelectMap program line to the specified level
+ */
+int ngcc_fpga_pgm_fn(int assert, int flush, int cookie)
+{
+ pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+
+ debug("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__);
+
+ if (assert) {
+ FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_PRG);
+ debug("asserted\n");
+ } else {
+ FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_PRG);
+ debug("deasserted\n");
+ }
+
+ return assert;
+}
+
+
+/*
+ * Test the state of the active-low FPGA INIT line. Return 1 on INIT
+ * asserted (low).
+ */
+int ngcc_fpga_init_fn(int cookie)
+{
+ pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+
+ debug("%s:%d: INIT check... ", __FUNCTION__, __LINE__);
+ if (FPGA_IN32(&fpga->status) & NGCC_FPGA_INIT) {
+ debug("high\n");
+ return 0;
+ } else {
+ debug("low\n");
+ return 1;
+ }
+}
+
+
+/*
+ * Test the state of the active-high FPGA DONE pin
+ */
+int ngcc_fpga_done_fn(int cookie)
+{
+ pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+
+ debug("%s:%d: DONE check... ", __FUNCTION__, __LINE__);
+ if (FPGA_IN32(&fpga->status) & NGCC_FPGA_DONE) {
+ debug("DONE high\n");
+ return 1;
+ } else {
+ debug("low\n");
+ return 0;
+ }
+}
+
+
+/*
+ * FPGA pre-configuration function.
+ */
+int ngcc_fpga_pre_config_fn(int cookie)
+{
+ pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+ debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
+
+ ngcc_fpga_reset(TRUE);
+ FPGA_CLRBITS(&fpga->ctrla, 0xfffffe00);
+
+ ngcc_fpga_reset(TRUE);
+ return 0;
+}
+
+
+/*
+ * FPGA post configuration function. Blip the FPGA reset line and then see if
+ * the FPGA appears to be running.
+ */
+int ngcc_fpga_post_config_fn(int cookie)
+{
+ pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+
+ debug("%s:%d: NGCC FPGA post configuration\n", __FUNCTION__, __LINE__);
+
+ udelay (100);
+ ngcc_fpga_reset(FALSE);
+
+ FPGA_SETBITS(&fpga->ctrla, 0x29f8c000);
+
+ return 0;
+}
+
+
+int ngcc_fpga_clk_fn(int assert_clk, int flush, int cookie)
+{
+ pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+
+ if (assert_clk)
+ FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_CLK);
+ else
+ FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_CLK);
+
+ return assert_clk;
+}
+
+
+int ngcc_fpga_wr_fn(int assert_write, int flush, int cookie)
+{
+ pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+
+ if (assert_write)
+ FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_DATA);
+ else
+ FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_DATA);
+
+ return assert_write;
+}
+
+
+/*
+ * Initialize the fpga. Return 1 on success, 0 on failure.
+ */
+int pmc440_init_fpga(void)
+{
+ char *s;
+
+ debug("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n",
+ __FUNCTION__, __LINE__, gd->reloc_off);
+ fpga_init(gd->reloc_off);
+
+ fpga_serialslave_init ();
+ debug("%s:%d: Adding fpga 0\n", __FUNCTION__, __LINE__);
+ fpga_add (fpga_xilinx, &fpga[0]);
+
+ /* NGCC only */
+ if ((s = getenv("bd_type")) && !strcmp(s, "ngcc")) {
+ ngcc_fpga_serialslave_init ();
+ debug("%s:%d: Adding fpga 1\n", __FUNCTION__, __LINE__);
+ fpga_add (fpga_xilinx, &fpga[1]);
+ }
+
+ return 0;
+}
+#endif /* CONFIG_FPGA */
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+extern int pmc440_init_fpga(void);
+
+extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
+extern int fpga_init_fn(int cookie);
+extern int fpga_err_fn(int cookie);
+extern int fpga_done_fn(int cookie);
+extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
+extern int fpga_cs_fn(int assert_cs, int flush, int cookie);
+extern int fpga_wr_fn(int assert_write, int flush, int cookie);
+extern int fpga_wdata_fn (uchar data, int flush, int cookie);
+extern int fpga_read_data_fn(unsigned char *data, int cookie);
+extern int fpga_write_data_fn(unsigned char data, int flush, int cookie);
+extern int fpga_busy_fn(int cookie);
+extern int fpga_abort_fn(int cookie );
+extern int fpga_pre_config_fn(int cookie );
+extern int fpga_post_config_fn(int cookie );
+
+extern int ngcc_fpga_pgm_fn(int assert_pgm, int flush, int cookie);
+extern int ngcc_fpga_init_fn(int cookie);
+extern int ngcc_fpga_done_fn(int cookie);
+extern int ngcc_fpga_clk_fn(int assert_clk, int flush, int cookie);
+extern int ngcc_fpga_wr_fn(int assert_write, int flush, int cookie);
+extern int ngcc_fpga_pre_config_fn(int cookie );
+extern int ngcc_fpga_post_config_fn(int cookie );
--- /dev/null
+/*
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <asm-ppc/mmu.h>
+#include <config.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
+#ifndef CONFIG_NAND_SPL
+ tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
+#else
+ tlbentry( CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G )
+#endif
+
+ /* TLB-entry for DDR SDRAM (Up to 2GB) */
+#ifdef CONFIG_4xx_DCACHE
+ tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G)
+#else
+ tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+#endif
+
+#ifdef CFG_INIT_RAM_DCACHE
+ /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+ tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+#endif
+
+ /* TLB-entry for PCI Memory */
+ tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
+
+ /* TLB-entries for EBC */
+ /* PMC440 maps EBC to 0xef000000 which is handled by the peripheral
+ * tlb entry.
+ * This dummy entry is only for convinience in order not to modify the
+ * amount of entries. Currently OS/9 relies on this :-)
+ */
+ tlbentry( 0xc0000000, SZ_256M, 0xc0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+
+ /* TLB-entry for NAND */
+ tlbentry( CFG_NAND_ADDR, SZ_1K, CFG_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+
+ /* TLB-entry for Internal Registers & OCM */
+ tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I )
+
+ /*TLB-entry PCI registers*/
+ tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+
+ /* TLB-entry for peripherals */
+ tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+
+ /* TLB-entry PCI IO space */
+ tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+
+ /* TODO: what about high IO space */
+ tlbtab_end
+
+#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+ /*
+ * For NAND booting the first TLB has to be reconfigured to full size
+ * and with caching disabled after running from RAM!
+ */
+#define TLB00 TLB0(CFG_BOOT_BASE_ADDR, SZ_256M)
+#define TLB01 TLB1(CFG_BOOT_BASE_ADDR, 1)
+#define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
+
+ .globl reconfig_tlb0
+reconfig_tlb0:
+ sync
+ isync
+ addi r4,r0,0x0000 /* TLB entry #0 */
+ lis r5,TLB00@h
+ ori r5,r5,TLB00@l
+ tlbwe r5,r4,0x0000 /* Save it out */
+ lis r5,TLB01@h
+ ori r5,r5,TLB01@l
+ tlbwe r5,r4,0x0001 /* Save it out */
+ lis r5,TLB02@h
+ ori r5,r5,TLB02@l
+ tlbwe r5,r4,0x0002 /* Save it out */
+ sync
+ isync
+ blr
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
+ * Based on board/amcc/sequoia/sequoia.c
+ *
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2006
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <ppc440.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+#include <i2c.h>
+#ifdef CONFIG_RESET_PHY_R
+#include <miiphy.h>
+#endif
+#include <serial.h>
+#include "fpga.h"
+#include "pmc440.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+ulong flash_get_size(ulong base, int banknum);
+int pci_is_66mhz(void);
+int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt);
+
+
+struct serial_device *default_serial_console(void)
+{
+ uchar buf[4];
+ ulong delay;
+ int i;
+ ulong val;
+
+ /*
+ * Use default console on P4 when strapping jumper
+ * is installed (bootstrap option != 'H').
+ */
+ mfsdr(SDR_PINSTP, val);
+ if (((val & 0xf0000000) >> 29) != 7)
+ return &serial1_device;
+
+ ulong scratchreg = in_be32((void*)GPIO0_ISR3L);
+ if (!(scratchreg & 0x80)) {
+ /* mark scratchreg valid */
+ scratchreg = (scratchreg & 0xffffff00) | 0x80;
+
+ i = bootstrap_eeprom_read(CFG_I2C_BOOT_EEPROM_ADDR, 0x10, buf, 4);
+ if ((i != -1) && (buf[0] == 0x19) && (buf[1] == 0x75)) {
+ scratchreg |= buf[2];
+
+ /* bringup delay for console */
+ for (delay=0; delay<(1000 * (ulong)buf[3]); delay++) {
+ udelay(1000);
+ }
+ } else
+ scratchreg |= 0x01;
+ out_be32((void*)GPIO0_ISR3L, scratchreg);
+ }
+
+ if (scratchreg & 0x01)
+ return &serial1_device;
+ else
+ return &serial0_device;
+}
+
+int board_early_init_f(void)
+{
+ u32 sdr0_cust0;
+ u32 sdr0_pfc1, sdr0_pfc2;
+ u32 reg;
+
+ /* general EBC configuration (disable EBC timeouts) */
+ mtdcr(ebccfga, xbcfg);
+ mtdcr(ebccfgd, 0xf8400000);
+
+ /*--------------------------------------------------------------------
+ * Setup the GPIO pins
+ * TODO: setup GPIOs via CFG_4xx_GPIO_TABLE in board's config file
+ *-------------------------------------------------------------------*/
+ out32(GPIO0_OR, 0x40000002);
+ out32(GPIO0_TCR, 0x4c90011f);
+ out32(GPIO0_OSRL, 0x28011400);
+ out32(GPIO0_OSRH, 0x55005000);
+ out32(GPIO0_TSRL, 0x08011400);
+ out32(GPIO0_TSRH, 0x55005000);
+ out32(GPIO0_ISR1L, 0x54000000);
+ out32(GPIO0_ISR1H, 0x00000000);
+ out32(GPIO0_ISR2L, 0x44000000);
+ out32(GPIO0_ISR2H, 0x00000100);
+ out32(GPIO0_ISR3L, 0x00000000);
+ out32(GPIO0_ISR3H, 0x00000000);
+
+ out32(GPIO1_OR, 0x80002408);
+ out32(GPIO1_TCR, 0xd6003c08);
+ out32(GPIO1_OSRL, 0x0a5a0000);
+ out32(GPIO1_OSRH, 0x00000000);
+ out32(GPIO1_TSRL, 0x00000000);
+ out32(GPIO1_TSRH, 0x00000000);
+ out32(GPIO1_ISR1L, 0x00005555);
+ out32(GPIO1_ISR1H, 0x40000000);
+ out32(GPIO1_ISR2L, 0x04010000);
+ out32(GPIO1_ISR2H, 0x00000000);
+ out32(GPIO1_ISR3L, 0x01400000);
+ out32(GPIO1_ISR3H, 0x00000000);
+
+ /* patch PLB:PCI divider for 66MHz PCI */
+ mfcpr(clk_spcid, reg);
+ if (pci_is_66mhz() && (reg != 0x02000000)) {
+ mtcpr(clk_spcid, 0x02000000); /* 133MHZ : 2 for 66MHz PCI */
+
+ mfcpr(clk_icfg, reg);
+ reg |= CPR0_ICFG_RLI_MASK;
+ mtcpr(clk_icfg, reg);
+
+ mtspr(dbcr0, 0x20000000); /* do chip reset */
+ }
+
+ /*--------------------------------------------------------------------
+ * Setup the interrupt controller polarities, triggers, etc.
+ *-------------------------------------------------------------------*/
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+ mtdcr(uic0er, 0x00000000); /* disable all */
+ mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
+ mtdcr(uic0pr, 0xfffff7ef);
+ mtdcr(uic0tr, 0x00000000);
+ mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+ mtdcr(uic1er, 0x00000000); /* disable all */
+ mtdcr(uic1cr, 0x00000000); /* all non-critical */
+ mtdcr(uic1pr, 0xffffc7f5);
+ mtdcr(uic1tr, 0x00000000);
+ mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+
+ mtdcr(uic2sr, 0xffffffff); /* clear all */
+ mtdcr(uic2er, 0x00000000); /* disable all */
+ mtdcr(uic2cr, 0x00000000); /* all non-critical */
+ mtdcr(uic2pr, 0x27ffffff);
+ mtdcr(uic2tr, 0x00000000);
+ mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(uic2sr, 0xffffffff); /* clear all */
+
+ /* select Ethernet pins */
+ mfsdr(SDR0_PFC1, sdr0_pfc1);
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | SDR0_PFC1_SELECT_CONFIG_4;
+ mfsdr(SDR0_PFC2, sdr0_pfc2);
+ sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | SDR0_PFC2_SELECT_CONFIG_4;
+
+ /* enable 2nd IIC */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
+
+ mtsdr(SDR0_PFC2, sdr0_pfc2);
+ mtsdr(SDR0_PFC1, sdr0_pfc1);
+
+ /* setup NAND FLASH */
+ mfsdr(SDR0_CUST0, sdr0_cust0);
+ sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
+ SDR0_CUST0_NDFC_ENABLE |
+ SDR0_CUST0_NDFC_BW_8_BIT |
+ SDR0_CUST0_NDFC_ARE_MASK |
+ (0x80000000 >> (28 + CFG_NAND_CS));
+ mtsdr(SDR0_CUST0, sdr0_cust0);
+
+ return 0;
+}
+
+/*---------------------------------------------------------------------------+
+ | misc_init_r.
+ +---------------------------------------------------------------------------*/
+int misc_init_r(void)
+{
+ uint pbcr;
+ int size_val = 0;
+ u32 reg;
+ unsigned long usb2d0cr = 0;
+ unsigned long usb2phy0cr, usb2h0cr = 0;
+ unsigned long sdr0_pfc1;
+ char *act = getenv("usbact");
+
+ /*
+ * FLASH stuff...
+ */
+
+ /* Re-do sizing to get full correct info */
+
+ /* adjust flash start and offset */
+ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+ gd->bd->bi_flashoffset = 0;
+
+#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+ mtdcr(ebccfga, pb2cr);
+#else
+ mtdcr(ebccfga, pb0cr);
+#endif
+ pbcr = mfdcr(ebccfgd);
+ switch (gd->bd->bi_flashsize) {
+ case 1 << 20:
+ size_val = 0;
+ break;
+ case 2 << 20:
+ size_val = 1;
+ break;
+ case 4 << 20:
+ size_val = 2;
+ break;
+ case 8 << 20:
+ size_val = 3;
+ break;
+ case 16 << 20:
+ size_val = 4;
+ break;
+ case 32 << 20:
+ size_val = 5;
+ break;
+ case 64 << 20:
+ size_val = 6;
+ break;
+ case 128 << 20:
+ size_val = 7;
+ break;
+ }
+ pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+ mtdcr(ebccfga, pb2cr);
+#else
+ mtdcr(ebccfga, pb0cr);
+#endif
+ mtdcr(ebccfgd, pbcr);
+
+ /*
+ * Re-check to get correct base address
+ */
+ flash_get_size(gd->bd->bi_flashstart, 0);
+
+#ifdef CFG_ENV_IS_IN_FLASH
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ -CFG_MONITOR_LEN,
+ 0xffffffff,
+ &flash_info[0]);
+
+ /* Env protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR_REDUND,
+ CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
+ &flash_info[0]);
+#endif
+
+ /*
+ * USB suff...
+ */
+ if ((act == NULL || strcmp(act, "hostdev") == 0) &&
+ !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)){
+ /* SDR Setting */
+ mfsdr(SDR0_PFC1, sdr0_pfc1);
+ mfsdr(SDR0_USB2D0CR, usb2d0cr);
+ mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mfsdr(SDR0_USB2H0CR, usb2h0cr);
+
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
+
+ /* An 8-bit/60MHz interface is the only possible alternative
+ when connecting the Device to the PHY */
+ usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
+ usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
+
+ usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
+ sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
+
+ mtsdr(SDR0_PFC1, sdr0_pfc1);
+ mtsdr(SDR0_USB2D0CR, usb2d0cr);
+ mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mtsdr(SDR0_USB2H0CR, usb2h0cr);
+
+ /*clear resets*/
+ udelay(1000);
+ mtsdr(SDR0_SRST1, 0x00000000);
+ udelay(1000);
+ mtsdr(SDR0_SRST0, 0x00000000);
+
+ printf("USB: Host\n");
+
+ } else if ((strcmp(act, "dev") == 0) || (in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) {
+ /*-------------------PATCH-------------------------------*/
+ mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
+ mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+
+ udelay (1000);
+ mtsdr(SDR0_SRST1, 0x672c6000);
+
+ udelay (1000);
+ mtsdr(SDR0_SRST0, 0x00000080);
+
+ udelay (1000);
+ mtsdr(SDR0_SRST1, 0x60206000);
+
+ *(unsigned int *)(0xe0000350) = 0x00000001;
+
+ udelay (1000);
+ mtsdr(SDR0_SRST1, 0x60306000);
+ /*-------------------PATCH-------------------------------*/
+
+ /* SDR Setting */
+ mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mfsdr(SDR0_USB2H0CR, usb2h0cr);
+ mfsdr(SDR0_USB2D0CR, usb2d0cr);
+ mfsdr(SDR0_PFC1, sdr0_pfc1);
+
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; /*0*/
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; /*0*/
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; /*0*/
+
+ usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
+ usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; /*0*/
+
+ usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
+
+ sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
+ sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; /*1*/
+
+ mtsdr(SDR0_USB2H0CR, usb2h0cr);
+ mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mtsdr(SDR0_USB2D0CR, usb2d0cr);
+ mtsdr(SDR0_PFC1, sdr0_pfc1);
+
+ /*clear resets*/
+ udelay(1000);
+ mtsdr(SDR0_SRST1, 0x00000000);
+ udelay(1000);
+ mtsdr(SDR0_SRST0, 0x00000000);
+
+ printf("USB: Device\n");
+ }
+
+ /*
+ * Clear PLB4A0_ACR[WRP]
+ * This fix will make the MAL burst disabling patch for the Linux
+ * EMAC driver obsolete.
+ */
+ reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
+ mtdcr(plb4_acr, reg);
+
+#ifdef CONFIG_FPGA
+ pmc440_init_fpga();
+#endif
+
+ /* turn off POST LED */
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_POST_N);
+ /* turn on RUN LED */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~GPIO0_LED_RUN_N);
+ return 0;
+}
+
+int is_monarch(void)
+{
+ if (in_be32((void*)GPIO1_IR) & GPIO1_NONMONARCH)
+ return 0;
+
+ return 1;
+}
+
+int pci_is_66mhz(void)
+{
+ if (in_be32((void*)GPIO1_IR) & GPIO1_M66EN)
+ return 1;
+ return 0;
+}
+
+int board_revision(void)
+{
+ return (int)((in_be32((void*)GPIO1_IR) & GPIO1_HWID_MASK) >> 4);
+}
+
+int checkboard(void)
+{
+ puts("Board: esd GmbH - PMC440");
+
+ gd->board_type = board_revision();
+ printf(", Rev 1.%ld, ", gd->board_type);
+
+ if (!is_monarch()) {
+ puts("non-");
+ }
+
+ printf("monarch, PCI=%s MHz\n", pci_is_66mhz() ? "66" : "33");
+ return (0);
+}
+
+
+#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
+/*
+ * Assign interrupts to PCI devices. Some OSs rely on this.
+ */
+void pmc440_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+ unsigned char int_line[] = {IRQ_PCIC, IRQ_PCID, IRQ_PCIA, IRQ_PCIB};
+
+ pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
+ int_line[PCI_DEV(dev) & 0x03]);
+}
+#endif
+
+/*************************************************************************
+ * pci_pre_init
+ *
+ * This routine is called just prior to registering the hose and gives
+ * the board the opportunity to check things. Returning a value of zero
+ * indicates that things are bad & PCI initialization should be aborted.
+ *
+ * Different boards may wish to customize the pci controller structure
+ * (add regions, override default access routines, etc) or perform
+ * certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int pci_pre_init(struct pci_controller *hose)
+{
+ unsigned long addr;
+
+ /*-------------------------------------------------------------------------+
+ | Set priority for all PLB3 devices to 0.
+ | Set PLB3 arbiter to fair mode.
+ +-------------------------------------------------------------------------*/
+ mfsdr(sdr_amp1, addr);
+ mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
+ addr = mfdcr(plb3_acr);
+ mtdcr(plb3_acr, addr | 0x80000000);
+
+ /*-------------------------------------------------------------------------+
+ | Set priority for all PLB4 devices to 0.
+ +-------------------------------------------------------------------------*/
+ mfsdr(sdr_amp0, addr);
+ mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
+ addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
+ mtdcr(plb4_acr, addr);
+
+ /*-------------------------------------------------------------------------+
+ | Set Nebula PLB4 arbiter to fair mode.
+ +-------------------------------------------------------------------------*/
+ /* Segment0 */
+ addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
+ addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
+ addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
+ addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
+ mtdcr(plb0_acr, addr);
+
+ /* Segment1 */
+ addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
+ addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
+ addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
+ addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
+ mtdcr(plb1_acr, addr);
+
+#ifdef CONFIG_PCI_PNP
+ hose->fixup_irq = pmc440_pci_fixup_irq;
+#endif
+
+ return 1;
+}
+#endif /* defined(CONFIG_PCI) */
+
+/*************************************************************************
+ * pci_target_init
+ *
+ * The bootstrap configuration provides default settings for the pci
+ * inbound map (PIM). But the bootstrap config choices are limited and
+ * may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller *hose)
+{
+ /*--------------------------------------------------------------------------+
+ * Set up Direct MMIO registers
+ *--------------------------------------------------------------------------*/
+ /*--------------------------------------------------------------------------+
+ | PowerPC440EPX PCI Master configuration.
+ | Map one 1Gig range of PLB/processor addresses to PCI memory space.
+ | PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF
+ | Use byte reversed out routines to handle endianess.
+ | Make this region non-prefetchable.
+ +--------------------------------------------------------------------------*/
+ out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
+ out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
+ out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
+ out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIX0_PMM0MA, 0xc0000001); /* 1G + No prefetching, and enable region */
+
+ if (!is_monarch()) {
+ /* BAR1: top 64MB of RAM */
+ out32r(PCIX0_PTM1MS, 0xfc000001); /* Memory Size/Attribute */
+ out32r(PCIX0_PTM1LA, 0x0c000000); /* Local Addr. Reg */
+ } else {
+ /* BAR1: complete 256MB RAM (TODO: make dynamic) */
+ out32r(PCIX0_PTM1MS, 0xf0000001); /* Memory Size/Attribute */
+ out32r(PCIX0_PTM1LA, 0x00000000); /* Local Addr. Reg */
+ }
+
+ /* BAR2: 16 MB FPGA registers */
+ out32r(PCIX0_PTM2MS, 0xff000001); /* Memory Size/Attribute */
+ out32r(PCIX0_PTM2LA, 0xef000000); /* Local Addr. Reg */
+
+ if (is_monarch()) {
+ /* BAR2: map FPGA registers behind system memory at 1GB */
+ pci_write_config_dword(0, PCI_BASE_ADDRESS_2, 0x40000008);
+ }
+
+ /*--------------------------------------------------------------------------+
+ * Set up Configuration registers
+ *--------------------------------------------------------------------------*/
+
+ /* Program the board's vendor id */
+ pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
+ CFG_PCI_SUBSYS_VENDORID);
+
+#if 0 /* disabled for PMC405 backward compatibility */
+ /* Configure command register as bus master */
+ pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
+#endif
+
+ /* 240nS PCI clock */
+ pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
+
+ /* No error reporting */
+ pci_write_config_word(0, PCI_ERREN, 0);
+
+ pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
+
+ if (!is_monarch()) {
+ /* Program the board's subsystem id/classcode */
+ pci_write_config_word(0, PCI_SUBSYSTEM_ID,
+ CFG_PCI_SUBSYS_ID_NONMONARCH);
+ pci_write_config_word(0, PCI_CLASS_SUB_CODE,
+ CFG_PCI_CLASSCODE_NONMONARCH);
+
+ /* PCI configuration done: release ERREADY */
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_PPC_EREADY);
+ out_be32((void*)GPIO1_TCR, in_be32((void*)GPIO1_TCR) | GPIO1_PPC_EREADY);
+ } else {
+ /* Program the board's subsystem id/classcode */
+ pci_write_config_word(0, PCI_SUBSYSTEM_ID,
+ CFG_PCI_SUBSYS_ID_MONARCH);
+ pci_write_config_word(0, PCI_CLASS_SUB_CODE,
+ CFG_PCI_CLASSCODE_MONARCH);
+ }
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+/*************************************************************************
+ * pci_master_init
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
+void pci_master_init(struct pci_controller *hose)
+{
+ unsigned short temp_short;
+
+ /*--------------------------------------------------------------------------+
+ | Write the PowerPC440 EP PCI Configuration regs.
+ | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
+ | Enable PowerPC440 EP to act as a PCI memory target (PTM).
+ +--------------------------------------------------------------------------*/
+ if (is_monarch()) {
+ pci_read_config_word(0, PCI_COMMAND, &temp_short);
+ pci_write_config_word(0, PCI_COMMAND,
+ temp_short | PCI_COMMAND_MASTER |
+ PCI_COMMAND_MEMORY);
+ }
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
+
+
+static void wait_for_pci_ready(void)
+{
+ int i;
+ char *s = getenv("pcidelay");
+ if (s) {
+ int ms = simple_strtoul(s, NULL, 10);
+ printf("PCI: Waiting for %d ms\n", ms);
+ for (i=0; i<ms; i++)
+ udelay(1000);
+ }
+
+ if (!(in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY)) {
+ printf("PCI: Waiting for EREADY (CTRL-C to skip) ... ");
+ while (1) {
+ if (ctrlc()) {
+ puts("abort\n");
+ break;
+ }
+ if (in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY) {
+ printf("done\n");
+ break;
+ }
+ }
+ }
+}
+
+
+/*************************************************************************
+ * is_pci_host
+ *
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
+ *
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
+ *
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+ char *s = getenv("pciscan");
+ if (s == NULL)
+ if (is_monarch()) {
+ wait_for_pci_ready();
+ return 1;
+ } else
+ return 0;
+ else if (!strcmp(s, "yes"))
+ return 1;
+
+ return 0;
+}
+#endif /* defined(CONFIG_PCI) */
+#if defined(CONFIG_POST)
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+ return 0; /* No hotkeys supported */
+}
+#endif /* CONFIG_POST */
+
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+ if (miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0001) == 0) {
+ miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0010);
+ miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0df0);
+ miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, 0x0e10);
+ miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0000);
+ }
+
+ if (miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0001) == 0) {
+ miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0010);
+ miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0df0);
+ miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x10, 0x0e10);
+ miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0000);
+ }
+}
+#endif
+
+#if defined(CFG_EEPROM_WREN)
+/* Input: <dev_addr> I2C address of EEPROM device to enable.
+ * <state> -1: deliver current state
+ * 0: disable write
+ * 1: enable write
+ * Returns: -1: wrong device address
+ * 0: dis-/en- able done
+ * 0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable(unsigned dev_addr, int state)
+{
+ if ((CFG_I2C_EEPROM_ADDR != dev_addr) && (CFG_I2C_BOOT_EEPROM_ADDR != dev_addr)) {
+ return -1;
+ } else {
+ switch (state) {
+ case 1:
+ /* Enable write access, clear bit GPIO_SINT2. */
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~GPIO0_EP_EEP);
+ state = 0;
+ break;
+ case 0:
+ /* Disable write access, set bit GPIO_SINT2. */
+ out32(GPIO0_OR, in32(GPIO0_OR) | GPIO0_EP_EEP);
+ state = 0;
+ break;
+ default:
+ /* Read current status back. */
+ state = (0 == (in32(GPIO0_OR) & GPIO0_EP_EEP));
+ break;
+ }
+ }
+ return state;
+}
+#endif /* #if defined(CFG_EEPROM_WREN) */
+
+
+#define CFG_BOOT_EEPROM_PAGE_WRITE_BITS 3
+int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
+{
+ unsigned end = offset + cnt;
+ unsigned blk_off;
+ int rcode = 0;
+
+#if defined(CFG_EEPROM_WREN)
+ eeprom_write_enable(dev_addr, 1);
+#endif
+ /* Write data until done or would cross a write page boundary.
+ * We must write the address again when changing pages
+ * because the address counter only increments within a page.
+ */
+
+ while (offset < end) {
+ unsigned alen, len;
+ unsigned maxlen;
+ uchar addr[2];
+
+ blk_off = offset & 0xFF; /* block offset */
+
+ addr[0] = offset >> 8; /* block number */
+ addr[1] = blk_off; /* block offset */
+ alen = 2;
+ addr[0] |= dev_addr; /* insert device address */
+
+ len = end - offset;
+
+#define BOOT_EEPROM_PAGE_SIZE (1 << CFG_BOOT_EEPROM_PAGE_WRITE_BITS)
+#define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
+
+ maxlen = BOOT_EEPROM_PAGE_SIZE - BOOT_EEPROM_PAGE_OFFSET(blk_off);
+ if (maxlen > I2C_RXTX_LEN)
+ maxlen = I2C_RXTX_LEN;
+
+ if (len > maxlen)
+ len = maxlen;
+
+ if (i2c_write (addr[0], offset, alen-1, buffer, len) != 0)
+ rcode = 1;
+
+ buffer += len;
+ offset += len;
+
+#if defined(CFG_EEPROM_PAGE_WRITE_DELAY_MS)
+ udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+#endif
+ }
+#if defined(CFG_EEPROM_WREN)
+ eeprom_write_enable(dev_addr, 0);
+#endif
+ return rcode;
+}
+
+
+int bootstrap_eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
+{
+ unsigned end = offset + cnt;
+ unsigned blk_off;
+ int rcode = 0;
+
+ /* Read data until done or would cross a page boundary.
+ * We must write the address again when changing pages
+ * because the next page may be in a different device.
+ */
+ while (offset < end) {
+ unsigned alen, len;
+ unsigned maxlen;
+ uchar addr[2];
+
+ blk_off = offset & 0xFF; /* block offset */
+
+ addr[0] = offset >> 8; /* block number */
+ addr[1] = blk_off; /* block offset */
+ alen = 2;
+
+ addr[0] |= dev_addr; /* insert device address */
+
+ len = end - offset;
+
+ maxlen = 0x100 - blk_off;
+ if (maxlen > I2C_RXTX_LEN)
+ maxlen = I2C_RXTX_LEN;
+ if (len > maxlen)
+ len = maxlen;
+
+ if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0)
+ rcode = 1;
+ buffer += len;
+ offset += len;
+ }
+
+ return rcode;
+}
+
+
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_BOARD_INIT)
+int usb_board_init(void)
+{
+ char *act = getenv("usbact");
+ int i;
+
+ if ((act == NULL || strcmp(act, "hostdev") == 0) &&
+ !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT))
+ /* enable power on USB socket */
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N);
+
+ for (i=0; i<1000; i++)
+ udelay(1000);
+
+ return 0;
+}
+
+int usb_board_stop(void)
+{
+ /* disable power on USB socket */
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_USB_PWR_N);
+ return 0;
+}
+
+int usb_board_init_fail(void)
+{
+ usb_board_stop();
+ return 0;
+}
+#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_BOARD_INIT) */
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ u32 val[4];
+ int rc;
+
+ ft_cpu_setup(blob, bd);
+
+ /* Fixup NOR mapping */
+ val[0] = 0; /* chip select number */
+ val[1] = 0; /* always 0 */
+ val[2] = gd->bd->bi_flashstart;
+ val[3] = gd->bd->bi_flashsize;
+ rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
+ val, sizeof(val), 1);
+ if (rc)
+ printf("Unable to update property NOR mapping, err=%s\n",
+ fdt_strerror(rc));
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __PMC440_H__
+#define __PMC440_H__
+
+
+/*-----------------------------------------------------------------------
+ * GPIOs
+ */
+#define GPIO1_INTA_FAKE (0x80000000 >> (45-32)) /* GPIO45 OD */
+#define GPIO1_NONMONARCH (0x80000000 >> (63-32)) /* GPIO63 I */
+#define GPIO1_PPC_EREADY (0x80000000 >> (62-32)) /* GPIO62 I/O */
+#define GPIO1_M66EN (0x80000000 >> (61-32)) /* GPIO61 I */
+#define GPIO1_POST_N (0x80000000 >> (60-32)) /* GPIO60 O */
+#define GPIO1_IOEN_N (0x80000000 >> (50-32)) /* GPIO50 O */
+#define GPIO1_HWID_MASK (0xf0000000 >> (56-32)) /* GPIO56..59 I */
+
+#define GPIO1_USB_PWR_N (0x80000000 >> (32-32)) /* GPIO32 I */
+#define GPIO0_LED_RUN_N (0x80000000 >> 30) /* GPIO30 O */
+#define GPIO0_EP_EEP (0x80000000 >> 23) /* GPIO23 O */
+#define GPIO0_USB_ID (0x80000000 >> 21) /* GPIO21 I */
+#define GPIO0_USB_PRSNT (0x80000000 >> 20) /* GPIO20 I */
+#define GPIO0_SELF_RST (0x80000000 >> 6) /* GPIO6 OD */
+
+/* FPGA programming pin configuration */
+#define GPIO1_FPGA_PRG (0x80000000 >> (53-32)) /* FPGA program pin (ppc output) */
+#define GPIO1_FPGA_CLK (0x80000000 >> (51-32)) /* FPGA clk pin (ppc output) */
+#define GPIO1_FPGA_DATA (0x80000000 >> (52-32)) /* FPGA data pin (ppc output) */
+#define GPIO1_FPGA_DONE (0x80000000 >> (55-32)) /* FPGA done pin (ppc input) */
+#define GPIO1_FPGA_INIT (0x80000000 >> (54-32)) /* FPGA init pin (ppc input) */
+#define GPIO0_FPGA_FORCEINIT (0x80000000 >> 27) /* low: force INIT# low */
+
+/*-----------------------------------------------------------------------
+ * FPGA interface
+ */
+#define FPGA_BA CFG_FPGA_BASE0
+#define FPGA_OUT32(p,v) out_be32(((void*)(p)), (v))
+#define FPGA_IN32(p) in_be32((void*)(p))
+#define FPGA_SETBITS(p,v) out_be32(((void*)(p)), in_be32((void*)(p)) | (v))
+#define FPGA_CLRBITS(p,v) out_be32(((void*)(p)), in_be32((void*)(p)) & ~(v))
+
+struct pmc440_fifo_s {
+ u32 data;
+ u32 ctrl;
+};
+
+/* fifo ctrl register */
+#define FIFO_IE (1 << 15)
+#define FIFO_OVERFLOW (1 << 10)
+#define FIFO_EMPTY (1 << 9)
+#define FIFO_FULL (1 << 8)
+#define FIFO_LEVEL_MASK 0x000000ff
+
+#define FIFO_COUNT 4
+
+struct pmc440_fpga_s {
+ u32 ctrla;
+ u32 status;
+ u32 ctrlb;
+ u32 pad1[0x40 / sizeof(u32) - 3];
+ u32 irig_time; /* offset: 0x0040 */
+ u32 irig_tod;
+ u32 irig_cf;
+ u32 pad2;
+ u32 irig_rx_time; /* offset: 0x0050 */
+ u32 pad3[3];
+ u32 hostctrl; /* offset: 0x0060 */
+ u32 pad4[0x20 / sizeof(u32) - 1];
+ struct pmc440_fifo_s fifo[FIFO_COUNT]; /* 0x0080..0x009f */
+};
+
+typedef struct pmc440_fpga_s pmc440_fpga_t;
+
+/* ctrl register */
+#define CTRL_HOST_IE (1 << 8)
+
+/* outputs */
+#define RESET_EN (1 << 31)
+#define CLOCK_EN (1 << 30)
+#define RESET_OUT (1 << 19)
+#define CLOCK_OUT (1 << 22)
+#define RESET_OUT (1 << 19)
+#define IRIGB_R_OUT (1 << 14)
+
+
+/* status register */
+#define STATUS_VERSION_SHIFT 24
+#define STATUS_VERSION_MASK 0xff000000
+#define STATUS_HWREV_SHIFT 20
+#define STATUS_HWREV_MASK 0x00f00000
+
+#define STATUS_CAN_ISF (1 << 11)
+#define STATUS_CSTM_ISF (1 << 10)
+#define STATUS_FIFO_ISF (1 << 9)
+#define STATUS_HOST_ISF (1 << 8)
+
+
+/* inputs */
+#define RESET_IN (1 << 0)
+#define CLOCK_IN (1 << 1)
+#define IRIGB_R_IN (1 << 5)
+
+
+/* hostctrl register */
+#define HOSTCTRL_PMCRSTOUT_GATE (1 << 17)
+#define HOSTCTRL_PMCRSTOUT_FLAG (1 << 16)
+#define HOSTCTRL_CSTM1IE_GATE (1 << 7)
+#define HOSTCTRL_CSTM1IW_FLAG (1 << 6)
+#define HOSTCTRL_CSTM0IE_GATE (1 << 5)
+#define HOSTCTRL_CSTM0IW_FLAG (1 << 4)
+#define HOSTCTRL_FIFOIE_GATE (1 << 3)
+#define HOSTCTRL_FIFOIE_FLAG (1 << 2)
+#define HOSTCTRL_HCINT_GATE (1 << 1)
+#define HOSTCTRL_HCINT_FLAG (1 << 0)
+
+#define NGCC_CTRL_BASE (CFG_FPGA_BASE0 + 0x80000)
+#define NGCC_CTRL_FPGARST_N (1 << 2)
+
+/*-----------------------------------------------------------------------
+ * FPGA to PPC interrupt
+ */
+#define IRQ0_FPGA (32+28) /* UIC1 - FPGA internal */
+#define IRQ1_FPGA (32+30) /* UIC1 - custom module */
+#define IRQ2_FPGA (64+ 3) /* UIC2 - custom module / CAN */
+#define IRQ_ETH0 (64+ 4) /* UIC2 */
+#define IRQ_ETH1 ( 27) /* UIC0 */
+#define IRQ_RTC (64+ 0) /* UIC2 */
+#define IRQ_PCIA (64+ 1) /* UIC2 */
+#define IRQ_PCIB (32+18) /* UIC1 */
+#define IRQ_PCIC (32+19) /* UIC1 */
+#define IRQ_PCID (32+20) /* UIC1 */
+
+#endif /* __PMC440_H__ */
--- /dev/null
+/*
+ * (C) Copyright 2006
+ * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
+ * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
+ * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
+ *
+ * (C) Copyright 2006-2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* define DEBUG for debug output */
+#undef DEBUG
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <ppc440.h>
+
+#include "sdram.h"
+
+#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
+ defined(CONFIG_DDR_DATA_EYE)
+/*-----------------------------------------------------------------------------+
+ * wait_for_dlllock.
+ +----------------------------------------------------------------------------*/
+static int wait_for_dlllock(void)
+{
+ unsigned long val;
+ int wait = 0;
+
+ /* -----------------------------------------------------------+
+ * Wait for the DCC master delay line to finish calibration
+ * ----------------------------------------------------------*/
+ mtdcr(ddrcfga, DDR0_17);
+ val = DDR0_17_DLLLOCKREG_UNLOCKED;
+
+ while (wait != 0xffff) {
+ val = mfdcr(ddrcfgd);
+ if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED)
+ /* dlllockreg bit on */
+ return 0;
+ else
+ wait++;
+ }
+ debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
+ debug("Waiting for dlllockreg bit to raise\n");
+
+ return -1;
+}
+#endif
+
+#if defined(CONFIG_DDR_DATA_EYE)
+/*-----------------------------------------------------------------------------+
+ * wait_for_dram_init_complete.
+ +----------------------------------------------------------------------------*/
+int wait_for_dram_init_complete(void)
+{
+ unsigned long val;
+ int wait = 0;
+
+ /* --------------------------------------------------------------+
+ * Wait for 'DRAM initialization complete' bit in status register
+ * -------------------------------------------------------------*/
+ mtdcr(ddrcfga, DDR0_00);
+
+ while (wait != 0xffff) {
+ val = mfdcr(ddrcfgd);
+ if ((val & DDR0_00_INT_STATUS_BIT6) == DDR0_00_INT_STATUS_BIT6)
+ /* 'DRAM initialization complete' bit */
+ return 0;
+ else
+ wait++;
+ }
+
+ debug("DRAM initialization complete bit in status register did not rise\n");
+
+ return -1;
+}
+
+#define NUM_TRIES 64
+#define NUM_READS 10
+
+/*-----------------------------------------------------------------------------+
+ * denali_core_search_data_eye.
+ +----------------------------------------------------------------------------*/
+void denali_core_search_data_eye(unsigned long memory_size)
+{
+ int k, j;
+ u32 val;
+ u32 wr_dqs_shift, dqs_out_shift, dll_dqs_delay_X;
+ u32 max_passing_cases = 0, wr_dqs_shift_with_max_passing_cases = 0;
+ u32 passing_cases = 0, dll_dqs_delay_X_sw_val = 0;
+ u32 dll_dqs_delay_X_start_window = 0, dll_dqs_delay_X_end_window = 0;
+ volatile u32 *ram_pointer;
+ u32 test[NUM_TRIES] = {
+ 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
+ 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
+ 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
+ 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
+ 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
+ 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
+ 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
+ 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
+ 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
+ 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
+ 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
+ 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
+ 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
+
+ ram_pointer = (volatile u32 *)(CFG_SDRAM_BASE);
+
+ for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) {
+ /*for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) {*/
+
+ /* -----------------------------------------------------------+
+ * De-assert 'start' parameter.
+ * ----------------------------------------------------------*/
+ mtdcr(ddrcfga, DDR0_02);
+ val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
+ mtdcr(ddrcfgd, val);
+
+ /* -----------------------------------------------------------+
+ * Set 'wr_dqs_shift'
+ * ----------------------------------------------------------*/
+ mtdcr(ddrcfga, DDR0_09);
+ val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
+ | DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
+ mtdcr(ddrcfgd, val);
+
+ /* -----------------------------------------------------------+
+ * Set 'dqs_out_shift' = wr_dqs_shift + 32
+ * ----------------------------------------------------------*/
+ dqs_out_shift = wr_dqs_shift + 32;
+ mtdcr(ddrcfga, DDR0_22);
+ val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
+ | DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
+ mtdcr(ddrcfgd, val);
+
+ passing_cases = 0;
+
+ for (dll_dqs_delay_X = 1; dll_dqs_delay_X < 64; dll_dqs_delay_X++) {
+ /*for (dll_dqs_delay_X=1; dll_dqs_delay_X<128; dll_dqs_delay_X++) {*/
+ /* -----------------------------------------------------------+
+ * Set 'dll_dqs_delay_X'.
+ * ----------------------------------------------------------*/
+ /* dll_dqs_delay_0 */
+ mtdcr(ddrcfga, DDR0_17);
+ val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
+ | DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
+ mtdcr(ddrcfgd, val);
+ /* dll_dqs_delay_1 to dll_dqs_delay_4 */
+ mtdcr(ddrcfga, DDR0_18);
+ val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
+ | DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
+ | DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
+ | DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
+ | DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
+ mtdcr(ddrcfgd, val);
+ /* dll_dqs_delay_5 to dll_dqs_delay_8 */
+ mtdcr(ddrcfga, DDR0_19);
+ val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
+ | DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
+ | DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
+ | DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
+ | DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
+ mtdcr(ddrcfgd, val);
+
+ ppcMsync();
+ ppcMbar();
+
+ /* -----------------------------------------------------------+
+ * Assert 'start' parameter.
+ * ----------------------------------------------------------*/
+ mtdcr(ddrcfga, DDR0_02);
+ val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
+ mtdcr(ddrcfgd, val);
+
+ ppcMsync();
+ ppcMbar();
+
+ /* -----------------------------------------------------------+
+ * Wait for the DCC master delay line to finish calibration
+ * ----------------------------------------------------------*/
+ if (wait_for_dlllock() != 0) {
+ printf("dlllock did not occur !!!\n");
+ printf("denali_core_search_data_eye!!!\n");
+ printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
+ wr_dqs_shift, dll_dqs_delay_X);
+ hang();
+ }
+ ppcMsync();
+ ppcMbar();
+
+ if (wait_for_dram_init_complete() != 0) {
+ printf("dram init complete did not occur !!!\n");
+ printf("denali_core_search_data_eye!!!\n");
+ printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
+ wr_dqs_shift, dll_dqs_delay_X);
+ hang();
+ }
+ udelay(100); /* wait 100us to ensure init is really completed !!! */
+
+ /* write values */
+ for (j=0; j<NUM_TRIES; j++) {
+ ram_pointer[j] = test[j];
+
+ /* clear any cache at ram location */
+ __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
+ }
+
+ /* read values back */
+ for (j=0; j<NUM_TRIES; j++) {
+ for (k=0; k<NUM_READS; k++) {
+ /* clear any cache at ram location */
+ __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
+
+ if (ram_pointer[j] != test[j])
+ break;
+ }
+
+ /* read error */
+ if (k != NUM_READS)
+ break;
+ }
+
+ /* See if the dll_dqs_delay_X value passed.*/
+ if (j < NUM_TRIES) {
+ /* Failed */
+ passing_cases = 0;
+ /* break; */
+ } else {
+ /* Passed */
+ if (passing_cases == 0)
+ dll_dqs_delay_X_sw_val = dll_dqs_delay_X;
+ passing_cases++;
+ if (passing_cases >= max_passing_cases) {
+ max_passing_cases = passing_cases;
+ wr_dqs_shift_with_max_passing_cases = wr_dqs_shift;
+ dll_dqs_delay_X_start_window = dll_dqs_delay_X_sw_val;
+ dll_dqs_delay_X_end_window = dll_dqs_delay_X;
+ }
+ }
+
+ /* -----------------------------------------------------------+
+ * De-assert 'start' parameter.
+ * ----------------------------------------------------------*/
+ mtdcr(ddrcfga, DDR0_02);
+ val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
+ mtdcr(ddrcfgd, val);
+
+ } /* for (dll_dqs_delay_X=0; dll_dqs_delay_X<128; dll_dqs_delay_X++) */
+
+ } /* for (wr_dqs_shift=0; wr_dqs_shift<96; wr_dqs_shift++) */
+
+ /* -----------------------------------------------------------+
+ * Largest passing window is now detected.
+ * ----------------------------------------------------------*/
+
+ /* Compute dll_dqs_delay_X value */
+ dll_dqs_delay_X = (dll_dqs_delay_X_end_window + dll_dqs_delay_X_start_window) / 2;
+ wr_dqs_shift = wr_dqs_shift_with_max_passing_cases;
+
+ debug("DQS calibration - Window detected:\n");
+ debug("max_passing_cases = %d\n", max_passing_cases);
+ debug("wr_dqs_shift = %d\n", wr_dqs_shift);
+ debug("dll_dqs_delay_X = %d\n", dll_dqs_delay_X);
+ debug("dll_dqs_delay_X window = %d - %d\n",
+ dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window);
+
+ /* -----------------------------------------------------------+
+ * De-assert 'start' parameter.
+ * ----------------------------------------------------------*/
+ mtdcr(ddrcfga, DDR0_02);
+ val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
+ mtdcr(ddrcfgd, val);
+
+ /* -----------------------------------------------------------+
+ * Set 'wr_dqs_shift'
+ * ----------------------------------------------------------*/
+ mtdcr(ddrcfga, DDR0_09);
+ val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
+ | DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
+ mtdcr(ddrcfgd, val);
+ debug("DDR0_09=0x%08lx\n", val);
+
+ /* -----------------------------------------------------------+
+ * Set 'dqs_out_shift' = wr_dqs_shift + 32
+ * ----------------------------------------------------------*/
+ dqs_out_shift = wr_dqs_shift + 32;
+ mtdcr(ddrcfga, DDR0_22);
+ val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
+ | DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
+ mtdcr(ddrcfgd, val);
+ debug("DDR0_22=0x%08lx\n", val);
+
+ /* -----------------------------------------------------------+
+ * Set 'dll_dqs_delay_X'.
+ * ----------------------------------------------------------*/
+ /* dll_dqs_delay_0 */
+ mtdcr(ddrcfga, DDR0_17);
+ val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
+ | DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
+ mtdcr(ddrcfgd, val);
+ debug("DDR0_17=0x%08lx\n", val);
+
+ /* dll_dqs_delay_1 to dll_dqs_delay_4 */
+ mtdcr(ddrcfga, DDR0_18);
+ val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
+ | DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
+ | DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
+ | DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
+ | DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
+ mtdcr(ddrcfgd, val);
+ debug("DDR0_18=0x%08lx\n", val);
+
+ /* dll_dqs_delay_5 to dll_dqs_delay_8 */
+ mtdcr(ddrcfga, DDR0_19);
+ val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
+ | DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
+ | DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
+ | DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
+ | DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
+ mtdcr(ddrcfgd, val);
+ debug("DDR0_19=0x%08lx\n", val);
+
+ /* -----------------------------------------------------------+
+ * Assert 'start' parameter.
+ * ----------------------------------------------------------*/
+ mtdcr(ddrcfga, DDR0_02);
+ val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
+ mtdcr(ddrcfgd, val);
+
+ ppcMsync();
+ ppcMbar();
+
+ /* -----------------------------------------------------------+
+ * Wait for the DCC master delay line to finish calibration
+ * ----------------------------------------------------------*/
+ if (wait_for_dlllock() != 0) {
+ printf("dlllock did not occur !!!\n");
+ hang();
+ }
+ ppcMsync();
+ ppcMbar();
+
+ if (wait_for_dram_init_complete() != 0) {
+ printf("dram init complete did not occur !!!\n");
+ hang();
+ }
+ udelay(100); /* wait 100us to ensure init is really completed !!! */
+}
+#endif /* CONFIG_DDR_DATA_EYE */
+
+#if defined(CONFIG_NAND_SPL)
+/* Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big
+ * for the 4k NAND boot image so define bus_frequency to 133MHz here
+ * which is save for the refresh counter setup.
+ */
+#define get_bus_freq(val) 133000000
+#endif
+
+/*************************************************************************
+ *
+ * initdram -- 440EPx's DDR controller is a DENALI Core
+ *
+ ************************************************************************/
+long int initdram (int board_type)
+{
+#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+#if !defined(CONFIG_NAND_SPL)
+ ulong speed = get_bus_freq(0);
+#else
+ ulong speed = 133333333; /* 133MHz is on the safe side */
+#endif
+
+ mtsdram(DDR0_02, 0x00000000);
+
+ mtsdram(DDR0_00, 0x0000190A);
+ mtsdram(DDR0_01, 0x01000000);
+ mtsdram(DDR0_03, 0x02030602);
+ mtsdram(DDR0_04, 0x0A020200);
+ mtsdram(DDR0_05, 0x02020308);
+ mtsdram(DDR0_06, 0x0102C812);
+ mtsdram(DDR0_07, 0x000D0100);
+ mtsdram(DDR0_08, 0x02430001);
+ mtsdram(DDR0_09, 0x00011D5F);
+ mtsdram(DDR0_10, 0x00000300);
+ mtsdram(DDR0_11, 0x0027C800);
+ mtsdram(DDR0_12, 0x00000003);
+ mtsdram(DDR0_14, 0x00000000);
+ mtsdram(DDR0_17, 0x19000000);
+ mtsdram(DDR0_18, 0x19191919);
+ mtsdram(DDR0_19, 0x19191919);
+ mtsdram(DDR0_20, 0x0B0B0B0B);
+ mtsdram(DDR0_21, 0x0B0B0B0B);
+ mtsdram(DDR0_22, 0x00267F0B);
+ mtsdram(DDR0_23, 0x00000000);
+ mtsdram(DDR0_24, 0x01010002);
+ if (speed > 133333334)
+ mtsdram(DDR0_26, 0x5B26050C);
+ else
+ mtsdram(DDR0_26, 0x5B260408);
+ mtsdram(DDR0_27, 0x0000682B);
+ mtsdram(DDR0_28, 0x00000000);
+ mtsdram(DDR0_31, 0x00000000);
+ mtsdram(DDR0_42, 0x01000006);
+ mtsdram(DDR0_43, 0x030A0200);
+ mtsdram(DDR0_44, 0x00000003);
+ mtsdram(DDR0_02, 0x00000001);
+
+ wait_for_dlllock();
+#endif /* #ifndef CONFIG_NAND_U_BOOT */
+
+#ifdef CONFIG_DDR_DATA_EYE
+ /* -----------------------------------------------------------+
+ * Perform data eye search if requested.
+ * ----------------------------------------------------------*/
+ denali_core_search_data_eye(CFG_MBYTES_SDRAM << 20);
+#endif
+
+ return (CFG_MBYTES_SDRAM << 20);
+}
--- /dev/null
+/*
+ * (C) Copyright 2006
+ * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
+ * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
+ * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SPD_SDRAM_DENALI_H_
+#define _SPD_SDRAM_DENALI_H_
+
+#define ppcMsync sync
+#define ppcMbar eieio
+
+/* General definitions */
+#define MAX_SPD_BYTE 128 /* highest SPD byte # to read */
+#define DENALI_REG_NUMBER 45 /* 45 Regs in PPC440EPx Denali Core */
+#define SUPPORTED_DIMMS_NB 7 /* Number of supported DIMM modules types */
+#define SDRAM_NONE 0 /* No DIMM detected in Slot */
+#define MAXRANKS 2 /* 2 ranks maximum */
+
+/* Supported PLB Frequencies */
+#define PLB_FREQ_133MHZ 133333333
+#define PLB_FREQ_152MHZ 152000000
+#define PLB_FREQ_160MHZ 160000000
+#define PLB_FREQ_166MHZ 166666666
+
+/* Denali Core Registers */
+#define SDRAM_DCR_BASE 0x10
+
+#define DDR_DCR_BASE 0x10
+#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */
+#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */
+
+/*-----------------------------------------------------------------------------+
+ | Values for ddrcfga register - indirect addressing of these regs
+ +-----------------------------------------------------------------------------*/
+
+#define DDR0_00 0x00
+#define DDR0_00_INT_ACK_MASK 0x7F000000 /* Write only */
+#define DDR0_00_INT_ACK_ALL 0x7F000000
+#define DDR0_00_INT_ACK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
+#define DDR0_00_INT_ACK_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
+/* Status */
+#define DDR0_00_INT_STATUS_MASK 0x00FF0000 /* Read only */
+/* Bit0. A single access outside the defined PHYSICAL memory space detected. */
+#define DDR0_00_INT_STATUS_BIT0 0x00010000
+/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */
+#define DDR0_00_INT_STATUS_BIT1 0x00020000
+/* Bit2. Single correctable ECC event detected */
+#define DDR0_00_INT_STATUS_BIT2 0x00040000
+/* Bit3. Multiple correctable ECC events detected. */
+#define DDR0_00_INT_STATUS_BIT3 0x00080000
+/* Bit4. Single uncorrectable ECC event detected. */
+#define DDR0_00_INT_STATUS_BIT4 0x00100000
+/* Bit5. Multiple uncorrectable ECC events detected. */
+#define DDR0_00_INT_STATUS_BIT5 0x00200000
+/* Bit6. DRAM initialization complete. */
+#define DDR0_00_INT_STATUS_BIT6 0x00400000
+/* Bit7. Logical OR of all lower bits. */
+#define DDR0_00_INT_STATUS_BIT7 0x00800000
+
+#define DDR0_00_INT_STATUS_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
+#define DDR0_00_INT_STATUS_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
+#define DDR0_00_DLL_INCREMENT_MASK 0x00007F00
+#define DDR0_00_DLL_INCREMENT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
+#define DDR0_00_DLL_INCREMENT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
+#define DDR0_00_DLL_START_POINT_MASK 0x0000007F
+#define DDR0_00_DLL_START_POINT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
+#define DDR0_00_DLL_START_POINT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
+
+
+#define DDR0_01 0x01
+#define DDR0_01_PLB0_DB_CS_LOWER_MASK 0x1F000000
+#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
+#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
+#define DDR0_01_PLB0_DB_CS_UPPER_MASK 0x001F0000
+#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
+#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n) ((((unsigned long)(n))>>16)&0x1F)
+#define DDR0_01_OUT_OF_RANGE_TYPE_MASK 0x00000700 /* Read only */
+#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
+#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
+#define DDR0_01_INT_MASK_MASK 0x000000FF
+#define DDR0_01_INT_MASK_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
+#define DDR0_01_INT_MASK_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
+#define DDR0_01_INT_MASK_ALL_ON 0x000000FF
+#define DDR0_01_INT_MASK_ALL_OFF 0x00000000
+
+#define DDR0_02 0x02
+#define DDR0_02_MAX_CS_REG_MASK 0x02000000 /* Read only */
+#define DDR0_02_MAX_CS_REG_ENCODE(n) ((((unsigned long)(n))&0x2)<<24)
+#define DDR0_02_MAX_CS_REG_DECODE(n) ((((unsigned long)(n))>>24)&0x2)
+#define DDR0_02_MAX_COL_REG_MASK 0x000F0000 /* Read only */
+#define DDR0_02_MAX_COL_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<16)
+#define DDR0_02_MAX_COL_REG_DECODE(n) ((((unsigned long)(n))>>16)&0xF)
+#define DDR0_02_MAX_ROW_REG_MASK 0x00000F00 /* Read only */
+#define DDR0_02_MAX_ROW_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
+#define DDR0_02_MAX_ROW_REG_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
+#define DDR0_02_START_MASK 0x00000001
+#define DDR0_02_START_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
+#define DDR0_02_START_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
+#define DDR0_02_START_OFF 0x00000000
+#define DDR0_02_START_ON 0x00000001
+
+#define DDR0_03 0x03
+#define DDR0_03_BSTLEN_MASK 0x07000000
+#define DDR0_03_BSTLEN_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
+#define DDR0_03_BSTLEN_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
+#define DDR0_03_CASLAT_MASK 0x00070000
+#define DDR0_03_CASLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
+#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
+#define DDR0_03_CASLAT_LIN_MASK 0x00000F00
+#define DDR0_03_CASLAT_LIN_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
+#define DDR0_03_CASLAT_LIN_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
+#define DDR0_03_INITAREF_MASK 0x0000000F
+#define DDR0_03_INITAREF_ENCODE(n) ((((unsigned long)(n))&0xF)<<0)
+#define DDR0_03_INITAREF_DECODE(n) ((((unsigned long)(n))>>0)&0xF)
+
+#define DDR0_04 0x04
+#define DDR0_04_TRC_MASK 0x1F000000
+#define DDR0_04_TRC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
+#define DDR0_04_TRC_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
+#define DDR0_04_TRRD_MASK 0x00070000
+#define DDR0_04_TRRD_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
+#define DDR0_04_TRRD_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
+#define DDR0_04_TRTP_MASK 0x00000700
+#define DDR0_04_TRTP_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
+#define DDR0_04_TRTP_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
+
+#define DDR0_05 0x05
+#define DDR0_05_TMRD_MASK 0x1F000000
+#define DDR0_05_TMRD_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
+#define DDR0_05_TMRD_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
+#define DDR0_05_TEMRS_MASK 0x00070000
+#define DDR0_05_TEMRS_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
+#define DDR0_05_TEMRS_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
+#define DDR0_05_TRP_MASK 0x00000F00
+#define DDR0_05_TRP_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
+#define DDR0_05_TRP_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
+#define DDR0_05_TRAS_MIN_MASK 0x000000FF
+#define DDR0_05_TRAS_MIN_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
+#define DDR0_05_TRAS_MIN_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
+
+#define DDR0_06 0x06
+#define DDR0_06_WRITEINTERP_MASK 0x01000000
+#define DDR0_06_WRITEINTERP_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
+#define DDR0_06_WRITEINTERP_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
+#define DDR0_06_TWTR_MASK 0x00070000
+#define DDR0_06_TWTR_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
+#define DDR0_06_TWTR_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
+#define DDR0_06_TDLL_MASK 0x0000FF00
+#define DDR0_06_TDLL_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
+#define DDR0_06_TDLL_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
+#define DDR0_06_TRFC_MASK 0x0000007F
+#define DDR0_06_TRFC_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
+#define DDR0_06_TRFC_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
+
+#define DDR0_07 0x07
+#define DDR0_07_NO_CMD_INIT_MASK 0x01000000
+#define DDR0_07_NO_CMD_INIT_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
+#define DDR0_07_NO_CMD_INIT_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
+#define DDR0_07_TFAW_MASK 0x001F0000
+#define DDR0_07_TFAW_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
+#define DDR0_07_TFAW_DECODE(n) ((((unsigned long)(n))>>16)&0x1F)
+#define DDR0_07_AUTO_REFRESH_MODE_MASK 0x00000100
+#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
+#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
+#define DDR0_07_AREFRESH_MASK 0x00000001
+#define DDR0_07_AREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
+#define DDR0_07_AREFRESH_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
+
+#define DDR0_08 0x08
+#define DDR0_08_WRLAT_MASK 0x07000000
+#define DDR0_08_WRLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
+#define DDR0_08_WRLAT_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
+#define DDR0_08_TCPD_MASK 0x00FF0000
+#define DDR0_08_TCPD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
+#define DDR0_08_TCPD_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
+#define DDR0_08_DQS_N_EN_MASK 0x00000100
+#define DDR0_08_DQS_N_EN_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
+#define DDR0_08_DQS_N_EN_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
+#define DDR0_08_DDRII_SDRAM_MODE_MASK 0x00000001
+#define DDR0_08_DDRII_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
+#define DDR0_08_DDRII_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
+
+#define DDR0_09 0x09
+#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK 0x1F000000
+#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
+#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
+#define DDR0_09_RTT_0_MASK 0x00030000
+#define DDR0_09_RTT_0_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
+#define DDR0_09_RTT_0_DECODE(n) ((((unsigned long)(n))>>16)&0x3)
+#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK 0x00007F00
+#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
+#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
+#define DDR0_09_WR_DQS_SHIFT_MASK 0x0000007F
+#define DDR0_09_WR_DQS_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
+#define DDR0_09_WR_DQS_SHIFT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
+
+#define DDR0_10 0x0A
+#define DDR0_10_WRITE_MODEREG_MASK 0x00010000 /* Write only */
+#define DDR0_10_WRITE_MODEREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
+#define DDR0_10_WRITE_MODEREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
+#define DDR0_10_CS_MAP_MASK 0x00000300
+#define DDR0_10_CS_MAP_NO_MEM 0x00000000
+#define DDR0_10_CS_MAP_RANK0_INSTALLED 0x00000100
+#define DDR0_10_CS_MAP_RANK1_INSTALLED 0x00000200
+#define DDR0_10_CS_MAP_ENCODE(n) ((((unsigned long)(n))&0x3)<<8)
+#define DDR0_10_CS_MAP_DECODE(n) ((((unsigned long)(n))>>8)&0x3)
+#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK 0x0000001F
+#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<0)
+#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x1F)
+
+#define DDR0_11 0x0B
+#define DDR0_11_SREFRESH_MASK 0x01000000
+#define DDR0_11_SREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
+#define DDR0_11_SREFRESH_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
+#define DDR0_11_TXSNR_MASK 0x00FF0000
+#define DDR0_11_TXSNR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
+#define DDR0_11_TXSNR_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
+#define DDR0_11_TXSR_MASK 0x0000FF00
+#define DDR0_11_TXSR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
+#define DDR0_11_TXSR_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
+
+#define DDR0_12 0x0C
+#define DDR0_12_TCKE_MASK 0x0000007
+#define DDR0_12_TCKE_ENCODE(n) ((((unsigned long)(n))&0x7)<<0)
+#define DDR0_12_TCKE_DECODE(n) ((((unsigned long)(n))>>0)&0x7)
+
+#define DDR0_13 0x0D
+
+#define DDR0_14 0x0E
+#define DDR0_14_DLL_BYPASS_MODE_MASK 0x01000000
+#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
+#define DDR0_14_DLL_BYPASS_MODE_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
+#define DDR0_14_REDUC_MASK 0x00010000
+#define DDR0_14_REDUC_64BITS 0x00000000
+#define DDR0_14_REDUC_32BITS 0x00010000
+#define DDR0_14_REDUC_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
+#define DDR0_14_REDUC_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
+#define DDR0_14_REG_DIMM_ENABLE_MASK 0x00000100
+#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
+#define DDR0_14_REG_DIMM_ENABLE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
+
+#define DDR0_15 0x0F
+
+#define DDR0_16 0x10
+
+#define DDR0_17 0x11
+#define DDR0_17_DLL_DQS_DELAY_0_MASK 0x7F000000
+#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
+#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
+#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */
+#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000
+#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000
+#define DDR0_17_DLLLOCKREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
+#define DDR0_17_DLLLOCKREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
+#define DDR0_17_DLL_LOCK_MASK 0x00007F00 /* Read only */
+#define DDR0_17_DLL_LOCK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
+#define DDR0_17_DLL_LOCK_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
+
+#define DDR0_18 0x12
+#define DDR0_18_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
+#define DDR0_18_DLL_DQS_DELAY_4_MASK 0x7F000000
+#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
+#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
+#define DDR0_18_DLL_DQS_DELAY_3_MASK 0x007F0000
+#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
+#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
+#define DDR0_18_DLL_DQS_DELAY_2_MASK 0x00007F00
+#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
+#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
+#define DDR0_18_DLL_DQS_DELAY_1_MASK 0x0000007F
+#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
+#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
+
+#define DDR0_19 0x13
+#define DDR0_19_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
+#define DDR0_19_DLL_DQS_DELAY_8_MASK 0x7F000000
+#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
+#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
+#define DDR0_19_DLL_DQS_DELAY_7_MASK 0x007F0000
+#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
+#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
+#define DDR0_19_DLL_DQS_DELAY_6_MASK 0x00007F00
+#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
+#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
+#define DDR0_19_DLL_DQS_DELAY_5_MASK 0x0000007F
+#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
+#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
+
+#define DDR0_20 0x14
+#define DDR0_20_DLL_DQS_BYPASS_3_MASK 0x7F000000
+#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
+#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
+#define DDR0_20_DLL_DQS_BYPASS_2_MASK 0x007F0000
+#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
+#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
+#define DDR0_20_DLL_DQS_BYPASS_1_MASK 0x00007F00
+#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
+#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
+#define DDR0_20_DLL_DQS_BYPASS_0_MASK 0x0000007F
+#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
+#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
+
+#define DDR0_21 0x15
+#define DDR0_21_DLL_DQS_BYPASS_7_MASK 0x7F000000
+#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
+#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
+#define DDR0_21_DLL_DQS_BYPASS_6_MASK 0x007F0000
+#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
+#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
+#define DDR0_21_DLL_DQS_BYPASS_5_MASK 0x00007F00
+#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
+#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
+#define DDR0_21_DLL_DQS_BYPASS_4_MASK 0x0000007F
+#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
+#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
+
+#define DDR0_22 0x16
+/* ECC */
+#define DDR0_22_CTRL_RAW_MASK 0x03000000
+#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not being used */
+#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC checking is on, but no attempts to correct*/
+#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* No ECC RAM storage available */
+#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC checking and correcting on */
+#define DDR0_22_CTRL_RAW_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
+#define DDR0_22_CTRL_RAW_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
+
+#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000
+#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
+#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
+#define DDR0_22_DQS_OUT_SHIFT_MASK 0x00007F00
+#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
+#define DDR0_22_DQS_OUT_SHIFT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
+#define DDR0_22_DLL_DQS_BYPASS_8_MASK 0x0000007F
+#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
+#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
+
+
+#define DDR0_23 0x17
+#define DDR0_23_ODT_RD_MAP_CS0_MASK 0x03000000
+#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
+#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
+#define DDR0_23_ECC_C_SYND_MASK 0x00FF0000 /* Read only */
+#define DDR0_23_ECC_C_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
+#define DDR0_23_ECC_C_SYND_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
+#define DDR0_23_ECC_U_SYND_MASK 0x0000FF00 /* Read only */
+#define DDR0_23_ECC_U_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
+#define DDR0_23_ECC_U_SYND_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
+#define DDR0_23_FWC_MASK 0x00000001 /* Write only */
+#define DDR0_23_FWC_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
+#define DDR0_23_FWC_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
+
+#define DDR0_24 0x18
+#define DDR0_24_RTT_PAD_TERMINATION_MASK 0x03000000
+#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
+#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
+#define DDR0_24_ODT_WR_MAP_CS1_MASK 0x00030000
+#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
+#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>16)&0x3)
+#define DDR0_24_ODT_RD_MAP_CS1_MASK 0x00000300
+#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<8)
+#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>8)&0x3)
+#define DDR0_24_ODT_WR_MAP_CS0_MASK 0x00000003
+#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<0)
+#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>0)&0x3)
+
+#define DDR0_25 0x19
+#define DDR0_25_VERSION_MASK 0xFFFF0000 /* Read only */
+#define DDR0_25_VERSION_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
+#define DDR0_25_VERSION_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
+#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK 0x000003FF /* Read only */
+#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
+#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
+
+#define DDR0_26 0x1A
+#define DDR0_26_TRAS_MAX_MASK 0xFFFF0000
+#define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
+#define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
+#define DDR0_26_TREF_MASK 0x00003FFF
+#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
+#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
+
+#define DDR0_27 0x1B
+#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000
+#define DDR0_27_EMRS_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16)
+#define DDR0_27_EMRS_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF)
+#define DDR0_27_TINIT_MASK 0x0000FFFF
+#define DDR0_27_TINIT_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0)
+#define DDR0_27_TINIT_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF)
+
+#define DDR0_28 0x1C
+#define DDR0_28_EMRS3_DATA_MASK 0x3FFF0000
+#define DDR0_28_EMRS3_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16)
+#define DDR0_28_EMRS3_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF)
+#define DDR0_28_EMRS2_DATA_MASK 0x00003FFF
+#define DDR0_28_EMRS2_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0)
+#define DDR0_28_EMRS2_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF)
+
+#define DDR0_29 0x1D
+
+#define DDR0_30 0x1E
+
+#define DDR0_31 0x1F
+#define DDR0_31_XOR_CHECK_BITS_MASK 0x0000FFFF
+#define DDR0_31_XOR_CHECK_BITS_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0)
+#define DDR0_31_XOR_CHECK_BITS_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF)
+
+#define DDR0_32 0x20
+#define DDR0_32_OUT_OF_RANGE_ADDR_MASK 0xFFFFFFFF /* Read only */
+#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
+#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_33 0x21
+#define DDR0_33_OUT_OF_RANGE_ADDR_MASK 0x00000001 /* Read only */
+#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
+#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
+
+#define DDR0_34 0x22
+#define DDR0_34_ECC_U_ADDR_MASK 0xFFFFFFFF /* Read only */
+#define DDR0_34_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
+#define DDR0_34_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_35 0x23
+#define DDR0_35_ECC_U_ADDR_MASK 0x00000001 /* Read only */
+#define DDR0_35_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
+#define DDR0_35_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
+
+#define DDR0_36 0x24
+#define DDR0_36_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
+#define DDR0_36_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
+#define DDR0_36_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_37 0x25
+#define DDR0_37_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
+#define DDR0_37_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
+#define DDR0_37_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_38 0x26
+#define DDR0_38_ECC_C_ADDR_MASK 0xFFFFFFFF /* Read only */
+#define DDR0_38_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
+#define DDR0_38_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_39 0x27
+#define DDR0_39_ECC_C_ADDR_MASK 0x00000001 /* Read only */
+#define DDR0_39_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
+#define DDR0_39_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
+
+#define DDR0_40 0x28
+#define DDR0_40_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
+#define DDR0_40_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
+#define DDR0_40_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_41 0x29
+#define DDR0_41_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
+#define DDR0_41_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
+#define DDR0_41_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_42 0x2A
+#define DDR0_42_ADDR_PINS_MASK 0x07000000
+#define DDR0_42_ADDR_PINS_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
+#define DDR0_42_ADDR_PINS_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
+#define DDR0_42_CASLAT_LIN_GATE_MASK 0x0000000F
+#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n) ((((unsigned long)(n))&0xF)<<0)
+#define DDR0_42_CASLAT_LIN_GATE_DECODE(n) ((((unsigned long)(n))>>0)&0xF)
+
+#define DDR0_43 0x2B
+#define DDR0_43_TWR_MASK 0x07000000
+#define DDR0_43_TWR_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
+#define DDR0_43_TWR_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
+#define DDR0_43_APREBIT_MASK 0x000F0000
+#define DDR0_43_APREBIT_ENCODE(n) ((((unsigned long)(n))&0xF)<<16)
+#define DDR0_43_APREBIT_DECODE(n) ((((unsigned long)(n))>>16)&0xF)
+#define DDR0_43_COLUMN_SIZE_MASK 0x00000700
+#define DDR0_43_COLUMN_SIZE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
+#define DDR0_43_COLUMN_SIZE_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
+#define DDR0_43_EIGHT_BANK_MODE_MASK 0x00000001
+#define DDR0_43_EIGHT_BANK_MODE_8_BANKS 0x00000001
+#define DDR0_43_EIGHT_BANK_MODE_4_BANKS 0x00000000
+#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
+#define DDR0_43_EIGHT_BANK_MODE_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
+
+#define DDR0_44 0x2C
+#define DDR0_44_TRCD_MASK 0x000000FF
+#define DDR0_44_TRCD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
+#define DDR0_44_TRCD_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
+
+#endif /* _SPD_SDRAM_DENALI_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+
+ /* Align to next NAND block */
+ . = ALIGN(0x4000);
+ common/environment.o (.ppcenv)
+ /* Keep some space here for redundant env and potential bad env blocks */
+ . = ALIGN(0x10000);
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/ppc4xx/start.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+
+ ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
+
+ _end = . ;
+ PROVIDE (end = .);
+}
cpu/ppc4xx/start.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
cpu/ppc4xx/4xx_enet.o (.text)
*/
#include <common.h>
+#include <asm/io.h>
#include <asm/processor.h>
#include <command.h>
#include <malloc.h>
int misc_init_r (void)
{
- volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
- volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
- volatile unsigned short *lcd_contrast =
+ unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
+ unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
+ unsigned short *lcd_contrast =
(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 4);
- volatile unsigned short *lcd_backlight =
+ unsigned short *lcd_backlight =
(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 6);
unsigned char *dst;
ulong len = sizeof(fpgadata);
/*
* Reset FPGA via FPGA_INIT pin
*/
- out32(GPIO0_TCR, in32(GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~FPGA_INIT); /* reset low */
+ out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~FPGA_INIT); /* reset low */
udelay(1000); /* wait 1ms */
- out32(GPIO0_OR, in32(GPIO0_OR) | FPGA_INIT); /* reset high */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | FPGA_INIT); /* reset high */
udelay(1000); /* wait 1ms */
/*
* Reset external DUARTs
*/
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
udelay(10); /* wait 10us */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
udelay(1000); /* wait 1ms */
+ /*
+ * Set NAND-FLASH GPIO signals to default
+ */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_NAND_CE);
+
+ /*
+ * Setup EEPROM write protection
+ */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
+ out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_EEPROM_WP);
+
/*
* Enable interrupts in exar duart mcr[3]
*/
- *duart0_mcr = 0x08;
- *duart1_mcr = 0x08;
+ out_8(duart0_mcr, 0x08);
+ out_8(duart1_mcr, 0x08);
/*
* Init lcd interface and display logo
/*
* Set invert bit in small lcd controller
*/
- *(unsigned char *)(CFG_LCD_SMALL_REG + 2) |= 0x01;
+ out_8((unsigned char *)(CFG_LCD_SMALL_REG + 2),
+ in_8((unsigned char *)(CFG_LCD_SMALL_REG + 2)) | 0x01);
/*
* Set default contrast voltage on epson vga controller
*/
- *lcd_contrast = 0x4646;
+ out_be16(lcd_contrast, 0x4646);
/*
* Enable backlight
*/
- *lcd_backlight = 0xffff;
+ out_be16(lcd_backlight, 0xffff);
+
+ /*
+ * Enable external I2C bus
+ */
+ out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_IIC_ON);
return (0);
}
putc ('\n');
- /*
- * Disable sleep mode in LXT971
- */
- lxt971_no_sleep();
-
return 0;
}
}
}
#endif /* CONFIG_IDE_RESET */
+
+#if defined(CONFIG_RESET_PHY_R)
+void reset_phy(void)
+{
+#ifdef CONFIG_LXT971_NO_SLEEP
+
+ /*
+ * Disable sleep mode in LXT971
+ */
+ lxt971_no_sleep();
+#endif
+}
+#endif
+
+#if defined(CFG_EEPROM_WREN)
+/* Input: <dev_addr> I2C address of EEPROM device to enable.
+ * <state> -1: deliver current state
+ * 0: disable write
+ * 1: enable write
+ * Returns: -1: wrong device address
+ * 0: dis-/en- able done
+ * 0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable (unsigned dev_addr, int state)
+{
+ if (CFG_I2C_EEPROM_ADDR != dev_addr) {
+ return -1;
+ } else {
+ switch (state) {
+ case 1:
+ /* Enable write access, clear bit GPIO0. */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_EEPROM_WP);
+ state = 0;
+ break;
+ case 0:
+ /* Disable write access, set bit GPIO0. */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
+ state = 0;
+ break;
+ default:
+ /* Read current status back. */
+ state = (0 == (in_be32((void*)GPIO0_OR) & CFG_EEPROM_WP));
+ break;
+ }
+ }
+ return state;
+}
+
+int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ int query = argc == 1;
+ int state = 0;
+
+ if (query) {
+ /* Query write access state. */
+ state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
+ if (state < 0) {
+ puts ("Query of write access state failed.\n");
+ } else {
+ printf ("Write access for device 0x%0x is %sabled.\n",
+ CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
+ state = 0;
+ }
+ } else {
+ if ('0' == argv[1][0]) {
+ /* Disable write access. */
+ state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
+ } else {
+ /* Enable write access. */
+ state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
+ }
+ if (state < 0) {
+ puts ("Setup of write access state failed.\n");
+ }
+ }
+
+ return state;
+}
+
+U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
+ "eepwren - Enable / disable / query EEPROM write access\n",
+ NULL);
+#endif /* #if defined(CFG_EEPROM_WREN) */
cpu/ppc4xx/start.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
cpu/ppc4xx/start.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+
+
+/*
+ * CADMUS Board System Registers
+ */
+#ifndef CFG_CADMUS_BASE_REG
+#define CFG_CADMUS_BASE_REG (CADMUS_BASE_ADDR + 0x4000)
+#endif
+
+typedef struct cadmus_reg {
+ u_char cm_ver; /* Board version */
+ u_char cm_csr; /* General control/status */
+ u_char cm_rst; /* Reset control */
+ u_char cm_hsclk; /* High speed clock */
+ u_char cm_hsxclk; /* High speed clock extended */
+ u_char cm_led; /* LED data */
+ u_char cm_pci; /* PCI control/status */
+ u_char cm_dma; /* DMA control */
+ u_char cm_reserved[248]; /* Total 256 bytes */
+} cadmus_reg_t;
+
+
+unsigned int
+get_board_version(void)
+{
+ volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG;
+
+ return cadmus->cm_ver;
+}
+
+
+unsigned long
+get_clock_freq(void)
+{
+ volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG;
+
+ uint pci1_speed = (cadmus->cm_pci >> 2) & 0x3; /* PSPEED in [4:5] */
+
+ if (pci1_speed == 0) {
+ return 33000000;
+ } else if (pci1_speed == 1) {
+ return 66000000;
+ } else {
+ /* Really, unknown. Be safe? */
+ return 33000000;
+ }
+}
+
+
+unsigned int
+get_pci_slot(void)
+{
+ volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG;
+
+ /*
+ * PCI slot in USER bits CSR[6:7] by convention.
+ */
+ return ((cadmus->cm_csr >> 6) & 0x3) + 1;
+}
+
+
+unsigned int
+get_pci_dual(void)
+{
+ volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG;
+
+ /*
+ * PCI DUAL in CM_PCI[3]
+ */
+ return cadmus->cm_pci & 0x10;
+}
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CADMUS_H_
+#define __CADMUS_H_
+
+
+/*
+ * CADMUS Board System Register interface.
+ */
+
+/*
+ * Returns board version register.
+ */
+extern unsigned int get_board_version(void);
+
+/*
+ * Returns either 33000000 or 66000000 as the SYS_CLK_FREQ.
+ */
+extern unsigned long get_clock_freq(void);
+
+
+/*
+ * Returns 1 - 4, as found in the USER CSR[6:7] bits.
+ */
+extern unsigned int get_pci_slot(void);
+
+
+/*
+ * Returns PCI DUAL as found in CM_PCI[3].
+ */
+extern unsigned int get_pci_dual(void);
+
+
+#endif /* __CADMUS_H_ */
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <i2c.h>
+
+#include "eeprom.h"
+
+
+typedef struct {
+ char idee_pcbid[4]; /* "CCID" for CDC v1.X */
+ u8 idee_major;
+ u8 idee_minor;
+ char idee_serial[10];
+ char idee_errata[2];
+ char idee_date[8]; /* yyyymmdd */
+ /* The rest of the EEPROM space is reserved */
+} id_eeprom_t;
+
+
+unsigned int
+get_cpu_board_revision(void)
+{
+ uint major = 0;
+ uint minor = 0;
+
+ id_eeprom_t id_eeprom;
+
+ i2c_read(CFG_I2C_EEPROM_ADDR, 0, 2,
+ (uchar *) &id_eeprom, sizeof(id_eeprom));
+
+ major = id_eeprom.idee_major;
+ minor = id_eeprom.idee_minor;
+
+ if (major == 0xff && minor == 0xff) {
+ major = minor = 0;
+ }
+
+ return MPC85XX_CPU_BOARD_REV(major,minor);
+}
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __EEPROM_H_
+#define __EEPROM_H_
+
+
+/*
+ * EEPROM Board System Register interface.
+ */
+
+
+/*
+ * CPU Board Revision
+ */
+#define MPC85XX_CPU_BOARD_REV(maj, min) ((((maj)&0xff) << 8) | ((min) & 0xff))
+#define MPC85XX_CPU_BOARD_MAJOR(rev) (((rev) >> 8) & 0xff)
+#define MPC85XX_CPU_BOARD_MINOR(rev) ((rev) & 0xff)
+
+#define MPC85XX_CPU_BOARD_REV_UNKNOWN MPC85XX_CPU_BOARD_REV(0,0)
+#define MPC85XX_CPU_BOARD_REV_1_0 MPC85XX_CPU_BOARD_REV(1,0)
+#define MPC85XX_CPU_BOARD_REV_1_1 MPC85XX_CPU_BOARD_REV(1,1)
+
+/*
+ * Returns CPU board revision register as a 16-bit value with
+ * the Major in the high byte, and Minor in the low byte.
+ */
+extern unsigned int get_cpu_board_revision(void);
+
+
+#endif /* __CADMUS_H_ */
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include "cadmus.h"
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+static void cds_pci_fixup(void *blob)
+{
+ int node, tmp[2];
+ const char *path;
+ int len, slot, i;
+ u32 *map = NULL;
+
+ node = fdt_path_offset(blob, "/aliases");
+ tmp[0] = 0;
+ if (node >= 0) {
+ path = fdt_getprop(blob, node, "pci0", NULL);
+ if (path) {
+ node = fdt_path_offset(blob, path);
+ if (node >= 0) {
+ map = fdt_getprop_w(blob, node, "interrupt-map", &len);
+ }
+ }
+ }
+
+ if (map) {
+ len /= sizeof(u32);
+
+ slot = get_pci_slot();
+
+ for (i=0;i<len;i+=7) {
+ /* We rotate the interrupt pins so that the mapping
+ * changes depending on the slot the carrier card is in.
+ */
+ map[3] = ((map[3] + slot - 2) % 4) + 1;
+ map+=7;
+ }
+ }
+}
+
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
+ cds_pci_fixup(blob);
+#endif
+}
+#endif
--- /dev/null
+/*
+ * Copyright 2006 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+
+/* Config the VIA chip */
+void mpc85xx_config_via(struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *tab)
+{
+ pci_dev_t bridge;
+ unsigned int cmdstat;
+
+ /* Enable USB and IDE functions */
+ pci_hose_write_config_byte(hose, dev, 0x48, 0x08);
+
+ pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
+ cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY| PCI_COMMAND_MASTER;
+ pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
+ pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+ pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
+
+ /*
+ * Force the backplane P2P bridge to have a window
+ * open from 0x00000000-0x00001fff in PCI I/O space.
+ * This allows legacy I/O (i8259, etc) on the VIA
+ * southbridge to be accessed.
+ */
+ bridge = PCI_BDF(0,BRIDGE_ID,0);
+ pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0);
+ pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0);
+ pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10);
+ pci_hose_write_config_word(hose, bridge, PCI_IO_LIMIT_UPPER16, 0);
+}
+
+/* Function 1, IDE */
+void mpc85xx_config_via_usbide(struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *tab)
+{
+ pciauto_config_device(hose, dev);
+ /*
+ * Since the P2P window was forced to cover the fixed
+ * legacy I/O addresses, it is necessary to manually
+ * place the base addresses for the IDE and USB functions
+ * within this window.
+ */
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1ff8);
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1ff4);
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1fe8);
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_3, 0x1fe4);
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fd0);
+}
+
+/* Function 2, USB ports 0-1 */
+void mpc85xx_config_via_usb(struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *tab)
+{
+ pciauto_config_device(hose, dev);
+
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fa0);
+}
+
+/* Function 3, USB ports 2-3 */
+void mpc85xx_config_via_usb2(struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *tab)
+{
+ pciauto_config_device(hose, dev);
+
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1f80);
+}
+
+/* Function 5, Power Management */
+void mpc85xx_config_via_power(struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *tab)
+{
+ pciauto_config_device(hose, dev);
+
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1e00);
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1dfc);
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1df8);
+}
+
+/* Function 6, AC97 Interface */
+void mpc85xx_config_via_ac97(struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *tab)
+{
+ pciauto_config_device(hose, dev);
+
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1c00);
+}
--- /dev/null
+#ifndef _MPC85xx_VIA_H
+void mpc85xx_config_via(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+
+/* Function 1, IDE */
+void mpc85xx_config_via_usbide(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+
+/* Function 2, USB ports 0-1 */
+void mpc85xx_config_via_usb(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+
+/* Function 3, USB ports 2-3 */
+void mpc85xx_config_via_usb2(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+
+/* Function 5, Power Management */
+void mpc85xx_config_via_power(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+
+/* Function 6, AC97 Interface */
+void mpc85xx_config_via_ac97(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+#endif /* _MPC85xx_VIA_H */
--- /dev/null
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o
+SOBJS := init.o
+#SOBJS :=
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+# Copyright 2004 Freescale Semiconductor.
+# Modified by Xianghua Xiao, X.Xiao@motorola.com
+# (C) Copyright 2002,Motorola Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8540ads board
+# default CCARBAR is at 0xff700000
+# assume U-Boot is less than 0.5MB
+#
+TEXT_BASE = 0xfff80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8540=1
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Copyright (C) 2002,2003, Motorola Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+
+/*
+ * TLB0 and TLB1 Entries
+ *
+ * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
+ * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
+ * these TLB entries are established.
+ *
+ * The TLB entries for DDR are dynamically setup in spd_sdram()
+ * and use TLB1 Entries 8 through 15 as needed according to the
+ * size of DDR memory.
+ *
+ * MAS0: tlbsel, esel, nv
+ * MAS1: valid, iprot, tid, ts, tsize
+ * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
+ */
+
+#define entry_start \
+ mflr r1 ; \
+ bl 0f ;
+
+#define entry_end \
+0: mflr r0 ; \
+ mtlr r1 ; \
+ blr ;
+
+
+ .section .bootpg, "ax"
+ .globl tlb1_entry
+tlb1_entry:
+ entry_start
+
+ /*
+ * Number of TLB0 and TLB1 entries in the following table
+ */
+ .long 13
+
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+ /*
+ * TLB0 4K Non-cacheable, guarded
+ * 0xff700000 4K Initial CCSRBAR mapping
+ *
+ * This ends up at a TLB0 Index==0 entry, and must not collide
+ * with other TLB0 Entries.
+ */
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+#else
+#error("Update the number of table entries in tlb1_entry")
+#endif
+
+ /*
+ * TLB0 16K Cacheable, non-guarded
+ * 0xd001_0000 16K Temporary Global data for initialization
+ *
+ * Use four 4K TLB0 entries. These entries must be cacheable
+ * as they provide the bootstrap memory before the memory
+ * controler and real memory have been configured.
+ *
+ * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+ * and must not collide with other TLB0 entries.
+ */
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+
+ /*
+ * TLB 0: 16M Non-cacheable, guarded
+ * 0xff000000 16M FLASH
+ * Out of reset this entry is only 4K.
+ */
+ .long TLB1_MAS0(1, 0, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 1: 256M Non-cacheable, guarded
+ * 0x80000000 256M PCI1 MEM First half
+ */
+ .long TLB1_MAS0(1, 1, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 2: 256M Non-cacheable, guarded
+ * 0x90000000 256M PCI1 MEM Second half
+ */
+ .long TLB1_MAS0(1, 2, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
+ 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 3: 256M Non-cacheable, guarded
+ * 0xc0000000 256M Rapid IO MEM First half
+ */
+ .long TLB1_MAS0(1, 3, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 4: 256M Non-cacheable, guarded
+ * 0xd0000000 256M Rapid IO MEM Second half
+ */
+ .long TLB1_MAS0(1, 4, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),
+ 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 5: 64M Non-cacheable, guarded
+ * 0xe000_0000 1M CCSRBAR
+ * 0xe200_0000 16M PCI1 IO
+ */
+ .long TLB1_MAS0(1, 5, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 6: 64M Cacheable, non-guarded
+ * 0xf000_0000 64M LBC SDRAM
+ */
+ .long TLB1_MAS0(1, 6, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 7: 16K Non-cacheable, guarded
+ * 0xf8000000 16K BCSR registers
+ */
+ .long TLB1_MAS0(1, 7, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR), 0,0,0,0,0,1,0,1,0,1)
+
+#if !defined(CONFIG_SPD_EEPROM)
+ /*
+ * TLB 8, 9: 128M DDR
+ * 0x00000000 64M DDR System memory
+ * 0x04000000 64M DDR System memory
+ * Without SPD EEPROM configured DDR, this must be setup manually.
+ * Make sure the TLB count at the top of this table is correct.
+ * Likely it needs to be increased by two for these entries.
+ */
+#error("Update the number of table entries in tlb1_entry")
+ .long TLB1_MAS0(1, 8, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(1, 9, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x4000000),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x4000000),
+ 0,0,0,0,0,1,0,1,0,1)
+#endif
+
+ entry_end
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000 0x7fff_ffff DDR 2G
+ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
+ * 0xc000_0000 0xdfff_ffff RapidIO 512M
+ * 0xe000_0000 0xe000_ffff CCSR 1M
+ * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
+ * 0xf000_0000 0xf7ff_ffff SDRAM 128M
+ * 0xf800_0000 0xf80f_ffff BCSR 1M
+ * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M
+ *
+ * Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+#if !defined(CONFIG_SPD_EEPROM)
+#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
+#else
+#define LAWBAR0 0
+#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+#endif
+
+#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+/*
+ * This is not so much the SDRAM map as it is the whole localbus map.
+ */
+#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
+#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_1M))
+
+/*
+ * Rapid IO at 0xc000_0000 for 512 M
+ */
+#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
+#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+
+ .section .bootpg, "ax"
+ .globl law_entry
+law_entry:
+ entry_start
+ .long 0x05
+ .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
+ .long LAWBAR4,LAWAR4
+ entry_end
--- /dev/null
+ /*
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2002,2003, Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <spd.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+extern long int spd_sdram(void);
+
+void local_bus_init(void);
+void sdram_init(void);
+long int fixed_sdram(void);
+
+
+int board_early_init_f (void)
+{
+ return 0;
+}
+
+int checkboard (void)
+{
+ puts("Board: ADS\n");
+
+#ifdef CONFIG_PCI
+ printf(" PCI1: 32 bit, %d MHz (compiled)\n",
+ CONFIG_SYS_CLK_FREQ / 1000000);
+#else
+ printf(" PCI1: disabled\n");
+#endif
+
+ /*
+ * Initialize local bus.
+ */
+ local_bus_init();
+
+ return 0;
+}
+
+
+long int
+initdram(int board_type)
+{
+ long dram_size = 0;
+ extern long spd_sdram (void);
+
+ puts("Initializing\n");
+
+#if defined(CONFIG_DDR_DLL)
+ {
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ uint temp_ddrdll = 0;
+
+ /*
+ * Work around to stabilize DDR DLL
+ */
+ temp_ddrdll = gur->ddrdllcr;
+ gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
+ asm("sync;isync;msync");
+ }
+#endif
+
+#if defined(CONFIG_SPD_EEPROM)
+ dram_size = spd_sdram ();
+#else
+ dram_size = fixed_sdram ();
+#endif
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /*
+ * Initialize and enable DDR ECC.
+ */
+ ddr_enable_ecc(dram_size);
+#endif
+
+ /*
+ * Initialize SDRAM.
+ */
+ sdram_init();
+
+ puts(" DDR: ");
+ return dram_size;
+}
+
+
+/*
+ * Initialize Local Bus
+ */
+
+void
+local_bus_init(void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+
+ uint clkdiv;
+ uint lbc_hz;
+ sys_info_t sysinfo;
+
+ /*
+ * Errata LBC11.
+ * Fix Local Bus clock glitch when DLL is enabled.
+ *
+ * If localbus freq is < 66Mhz, DLL bypass mode must be used.
+ * If localbus freq is > 133Mhz, DLL can be safely enabled.
+ * Between 66 and 133, the DLL is enabled with an override workaround.
+ */
+
+ get_sys_info(&sysinfo);
+ clkdiv = lbc->lcrr & 0x0f;
+ lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+ if (lbc_hz < 66) {
+ lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
+
+ } else if (lbc_hz >= 133) {
+ lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+
+ } else {
+ /*
+ * On REV1 boards, need to change CLKDIV before enable DLL.
+ * Default CLKDIV is 8, change it to 4 temporarily.
+ */
+ uint pvr = get_pvr();
+ uint temp_lbcdll = 0;
+
+ if (pvr == PVR_85xx_REV1) {
+ /* FIXME: Justify the high bit here. */
+ lbc->lcrr = 0x10000004;
+ }
+
+ lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+ udelay(200);
+
+ /*
+ * Sample LBC DLL ctrl reg, upshift it to set the
+ * override bits.
+ */
+ temp_lbcdll = gur->lbcdllcr;
+ gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
+ asm("sync;isync;msync");
+ }
+}
+
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+
+void
+sdram_init(void)
+{
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+ uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+
+ puts(" SDRAM: ");
+ print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+
+ /*
+ * Setup SDRAM Base and Option Registers
+ */
+ lbc->or2 = CFG_OR2_PRELIM;
+ lbc->br2 = CFG_BR2_PRELIM;
+ lbc->lbcr = CFG_LBC_LBCR;
+ asm("msync");
+
+ lbc->lsrt = CFG_LBC_LSRT;
+ lbc->mrtpr = CFG_LBC_MRTPR;
+ asm("sync");
+
+ /*
+ * Configure the SDRAM controller.
+ */
+ lbc->lsdmr = CFG_LBC_LSDMR_1;
+ asm("sync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ lbc->lsdmr = CFG_LBC_LSDMR_2;
+ asm("sync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ lbc->lsdmr = CFG_LBC_LSDMR_3;
+ asm("sync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ lbc->lsdmr = CFG_LBC_LSDMR_4;
+ asm("sync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ lbc->lsdmr = CFG_LBC_LSDMR_5;
+ asm("sync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+}
+
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+ uint *pstart = (uint *) CFG_MEMTEST_START;
+ uint *pend = (uint *) CFG_MEMTEST_END;
+ uint *p;
+
+ printf("SDRAM test phase 1:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("SDRAM test phase 2:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("SDRAM test passed.\n");
+ return 0;
+}
+#endif
+
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ * fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+long int fixed_sdram (void)
+{
+ #ifndef CFG_RAMBOOT
+ volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
+
+ ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
+ ddr->cs0_config = CFG_DDR_CS0_CONFIG;
+ ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
+ ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
+ ddr->sdram_mode = CFG_DDR_MODE;
+ ddr->sdram_interval = CFG_DDR_INTERVAL;
+ #if defined (CONFIG_DDR_ECC)
+ ddr->err_disable = 0x0000000D;
+ ddr->err_sbe = 0x00ff0000;
+ #endif
+ asm("sync;isync;msync");
+ udelay(500);
+ #if defined (CONFIG_DDR_ECC)
+ /* Enable ECC checking */
+ ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
+ #else
+ ddr->sdram_cfg = CFG_DDR_CONTROL;
+ #endif
+ asm("sync; isync; msync");
+ udelay(500);
+ #endif
+ return CFG_SDRAM_SIZE * 1024 * 1024;
+}
+#endif /* !defined(CONFIG_SPD_EEPROM) */
+
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+
+static struct pci_controller hose;
+
+#endif /* CONFIG_PCI */
+
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+ pci_mpc85xx_init(&hose);
+#endif /* CONFIG_PCI */
+}
+
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+ int node, tmp[2];
+ const char *path;
+
+ ft_cpu_setup(blob, bd);
+
+ node = fdt_path_offset(blob, "/aliases");
+ tmp[0] = 0;
+ if (node >= 0) {
+#ifdef CONFIG_PCI
+ path = fdt_getprop(blob, node, "pci0", NULL);
+ if (path) {
+ tmp[1] = hose.last_busno - hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+ }
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2002,2003, Motorola,Inc.
+ * Xianghua Xiao, X.Xiao@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/mpc85xx/start.o (.bootpg)
+ board/freescale/mpc8540ads/init.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc85xx/start.o (.text)
+ board/freescale/mpc8540ads/init.o (.text)
+ cpu/mpc85xx/traps.o (.text)
+ cpu/mpc85xx/interrupts.o (.text)
+ cpu/mpc85xx/cpu_init.o (.text)
+ cpu/mpc85xx/cpu.o (.text)
+ cpu/mpc85xx/speed.o (.text)
+ cpu/mpc85xx/pci.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+#
+# Copyright 2004 Freescale Semiconductor.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o \
+ ../common/cadmus.o \
+ ../common/eeprom.o \
+ ../common/ft_board.o \
+ ../common/via.o
+
+SOBJS := init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# Copyright 2004 Freescale Semiconductor.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8541cds board
+#
+TEXT_BASE = 0xfff80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8541=1
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2002,2003, Motorola Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+
+/*
+ * TLB0 and TLB1 Entries
+ *
+ * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
+ * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
+ * these TLB entries are established.
+ *
+ * The TLB entries for DDR are dynamically setup in spd_sdram()
+ * and use TLB1 Entries 8 through 15 as needed according to the
+ * size of DDR memory.
+ *
+ * MAS0: tlbsel, esel, nv
+ * MAS1: valid, iprot, tid, ts, tsize
+ * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
+ */
+
+#define entry_start \
+ mflr r1 ; \
+ bl 0f ;
+
+#define entry_end \
+0: mflr r0 ; \
+ mtlr r1 ; \
+ blr ;
+
+
+ .section .bootpg, "ax"
+ .globl tlb1_entry
+tlb1_entry:
+ entry_start
+
+ /*
+ * Number of TLB0 and TLB1 entries in the following table
+ */
+ .long 13
+
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+ /*
+ * TLB0 4K Non-cacheable, guarded
+ * 0xff700000 4K Initial CCSRBAR mapping
+ *
+ * This ends up at a TLB0 Index==0 entry, and must not collide
+ * with other TLB0 Entries.
+ */
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+#else
+#error("Update the number of table entries in tlb1_entry")
+#endif
+
+ /*
+ * TLB0 16K Cacheable, non-guarded
+ * 0xd001_0000 16K Temporary Global data for initialization
+ *
+ * Use four 4K TLB0 entries. These entries must be cacheable
+ * as they provide the bootstrap memory before the memory
+ * controler and real memory have been configured.
+ *
+ * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+ * and must not collide with other TLB0 entries.
+ */
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+
+ /*
+ * TLB 0: 16M Non-cacheable, guarded
+ * 0xff000000 16M FLASH
+ * Out of reset this entry is only 4K.
+ */
+ .long TLB1_MAS0(1, 0, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 1: 256M Non-cacheable, guarded
+ * 0x80000000 256M PCI1 MEM First half
+ */
+ .long TLB1_MAS0(1, 1, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 2: 256M Non-cacheable, guarded
+ * 0x90000000 256M PCI1 MEM Second half
+ */
+ .long TLB1_MAS0(1, 2, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
+ 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 3: 256M Non-cacheable, guarded
+ * 0xa0000000 256M PCI2 MEM First half
+ */
+ .long TLB1_MAS0(1, 3, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 4: 256M Non-cacheable, guarded
+ * 0xb0000000 256M PCI2 MEM Second half
+ */
+ .long TLB1_MAS0(1, 4, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000),
+ 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 5: 64M Non-cacheable, guarded
+ * 0xe000_0000 1M CCSRBAR
+ * 0xe200_0000 16M PCI1 IO
+ * 0xe300_0000 16M PCI2 IO
+ */
+ .long TLB1_MAS0(1, 5, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 6: 64M Cacheable, non-guarded
+ * 0xf000_0000 64M LBC SDRAM
+ */
+ .long TLB1_MAS0(1, 6, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 7: 1M Non-cacheable, guarded
+ * 0xf8000000 1M CADMUS registers
+ */
+ .long TLB1_MAS0(1, 7, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
+ .long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1)
+
+ entry_end
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000 0x7fff_ffff DDR 2G
+ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
+ * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
+ * 0xe000_0000 0xe000_ffff CCSR 1M
+ * 0xe200_0000 0xe20f_ffff PCI1 IO 1M
+ * 0xe210_0000 0xe21f_ffff PCI2 IO 1M
+ * 0xf000_0000 0xf7ff_ffff SDRAM 128M
+ * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
+ * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
+ * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
+ *
+ * Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ * The defines below are 1-off of the actual LAWAR0 usage.
+ * So LAWAR3 define uses the LAWAR4 register in the ECM.
+ */
+
+#define LAWBAR0 0
+#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+
+#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
+#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
+#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
+
+#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff)
+#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
+
+/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+ .section .bootpg, "ax"
+ .globl law_entry
+
+law_entry:
+ entry_start
+ .long 6
+ .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
+ .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5
+ entry_end
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <ioports.h>
+#include <spd.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+#include "../common/cadmus.h"
+#include "../common/eeprom.h"
+#include "../common/via.h"
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+extern long int spd_sdram(void);
+
+void local_bus_init(void);
+void sdram_init(void);
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+ /* Port A configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
+ /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
+ /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
+ /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
+ /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
+ /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
+ /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
+ /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
+ /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
+ /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
+ /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
+ /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
+ /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
+ /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
+ /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
+ /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
+ /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
+ /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
+ /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
+ /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
+ /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
+ /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
+ /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
+ /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
+ /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
+ /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
+ /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
+ /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
+ /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
+ /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
+ /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
+ /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
+ },
+
+ /* Port B configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
+ /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
+ /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
+ /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
+ /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
+ /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
+ /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
+ /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
+ /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
+ /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
+ /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
+ /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
+ /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
+ /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
+ /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
+ /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
+ /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
+ /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
+ /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
+ /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
+ /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ },
+
+ /* Port C */
+ { /* conf ppar psor pdir podr pdat */
+ /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
+ /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
+ /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
+ /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
+ /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
+ /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
+ /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
+ /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
+ /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
+ /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
+ /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
+ /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
+ /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
+ /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
+ /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
+ /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
+ /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
+ /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
+ /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
+ /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
+ /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
+ /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
+ /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
+ /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
+ /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
+ /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
+ /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
+ /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
+ /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
+ /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
+ /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
+ /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
+ },
+
+ /* Port D */
+ { /* conf ppar psor pdir podr pdat */
+ /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
+ /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
+ /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
+ /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
+ /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
+ /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
+ /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
+ /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
+ /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
+ /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
+ /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
+ /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
+ /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
+ /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
+ /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
+ /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
+ /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
+ /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
+ /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
+ /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
+ /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
+ /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
+ /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
+ /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
+ /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
+ /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
+ /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
+ /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
+ /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ }
+};
+
+int board_early_init_f (void)
+{
+ return 0;
+}
+
+int checkboard (void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+
+ /* PCI slot in USER bits CSR[6:7] by convention. */
+ uint pci_slot = get_pci_slot ();
+
+ uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
+ uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
+ uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
+ uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
+
+ uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
+
+ uint cpu_board_rev = get_cpu_board_revision ();
+
+ printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
+ get_board_version (), pci_slot);
+
+ printf ("CPU Board Revision %d.%d (0x%04x)\n",
+ MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
+ MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
+
+ printf (" PCI1: %d bit, %s MHz, %s\n",
+ (pci1_32) ? 32 : 64,
+ (pci1_speed == 33000000) ? "33" :
+ (pci1_speed == 66000000) ? "66" : "unknown",
+ pci1_clk_sel ? "sync" : "async");
+
+ if (pci_dual) {
+ printf (" PCI2: 32 bit, 66 MHz, %s\n",
+ pci2_clk_sel ? "sync" : "async");
+ } else {
+ printf (" PCI2: disabled\n");
+ }
+
+ /*
+ * Initialize local bus.
+ */
+ local_bus_init ();
+
+ return 0;
+}
+
+long int
+initdram(int board_type)
+{
+ long dram_size = 0;
+
+ puts("Initializing\n");
+
+#if defined(CONFIG_DDR_DLL)
+ {
+ /*
+ * Work around to stabilize DDR DLL MSYNC_IN.
+ * Errata DDR9 seems to have been fixed.
+ * This is now the workaround for Errata DDR11:
+ * Override DLL = 1, Course Adj = 1, Tap Select = 0
+ */
+
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+
+ gur->ddrdllcr = 0x81000000;
+ asm("sync;isync;msync");
+ udelay(200);
+ }
+#endif
+ dram_size = spd_sdram();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /*
+ * Initialize and enable DDR ECC.
+ */
+ ddr_enable_ecc(dram_size);
+#endif
+ /*
+ * SDRAM Initialization
+ */
+ sdram_init();
+
+ puts(" DDR: ");
+ return dram_size;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+
+ uint clkdiv;
+ uint lbc_hz;
+ sys_info_t sysinfo;
+ uint temp_lbcdll;
+
+ /*
+ * Errata LBC11.
+ * Fix Local Bus clock glitch when DLL is enabled.
+ *
+ * If localbus freq is < 66Mhz, DLL bypass mode must be used.
+ * If localbus freq is > 133Mhz, DLL can be safely enabled.
+ * Between 66 and 133, the DLL is enabled with an override workaround.
+ */
+
+ get_sys_info(&sysinfo);
+ clkdiv = lbc->lcrr & 0x0f;
+ lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+ if (lbc_hz < 66) {
+ lbc->lcrr |= 0x80000000; /* DLL Bypass */
+
+ } else if (lbc_hz >= 133) {
+ lbc->lcrr &= (~0x80000000); /* DLL Enabled */
+
+ } else {
+ lbc->lcrr &= (~0x8000000); /* DLL Enabled */
+ udelay(200);
+
+ /*
+ * Sample LBC DLL ctrl reg, upshift it to set the
+ * override bits.
+ */
+ temp_lbcdll = gur->lbcdllcr;
+ gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
+ asm("sync;isync;msync");
+ }
+}
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+void
+sdram_init(void)
+{
+#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
+
+ uint idx;
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+ uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+ uint cpu_board_rev;
+ uint lsdmr_common;
+
+ puts(" SDRAM: ");
+
+ print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+
+ /*
+ * Setup SDRAM Base and Option Registers
+ */
+ lbc->or2 = CFG_OR2_PRELIM;
+ asm("msync");
+
+ lbc->br2 = CFG_BR2_PRELIM;
+ asm("msync");
+
+ lbc->lbcr = CFG_LBC_LBCR;
+ asm("msync");
+
+
+ lbc->lsrt = CFG_LBC_LSRT;
+ lbc->mrtpr = CFG_LBC_MRTPR;
+ asm("msync");
+
+ /*
+ * Determine which address lines to use baed on CPU board rev.
+ */
+ cpu_board_rev = get_cpu_board_revision();
+ lsdmr_common = CFG_LBC_LSDMR_COMMON;
+ if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
+ lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
+ } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
+ lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
+ } else {
+ /*
+ * Assume something unable to identify itself is
+ * really old, and likely has lines 16/17 mapped.
+ */
+ lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
+ }
+
+ /*
+ * Issue PRECHARGE ALL command.
+ */
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ /*
+ * Issue 8 AUTO REFRESH commands.
+ */
+ for (idx = 0; idx < 8; idx++) {
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+ }
+
+ /*
+ * Issue 8 MODE-set command.
+ */
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ /*
+ * Issue NORMAL OP command.
+ */
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(200); /* Overkill. Must wait > 200 bus cycles */
+
+#endif /* enable SDRAM init */
+}
+
+#if defined(CFG_DRAM_TEST)
+int
+testdram(void)
+{
+ uint *pstart = (uint *) CFG_MEMTEST_START;
+ uint *pend = (uint *) CFG_MEMTEST_END;
+ uint *p;
+
+ printf("Testing DRAM from 0x%08x to 0x%08x\n",
+ CFG_MEMTEST_START,
+ CFG_MEMTEST_END);
+
+ printf("DRAM test phase 1:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf ("DRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("DRAM test phase 2:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf ("DRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("DRAM test passed.\n");
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_PCI)
+/* For some reason the Tundra PCI bridge shows up on itself as a
+ * different device. Work around that by refusing to configure it.
+ */
+void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
+
+static struct pci_config_table pci_mpc85xxcds_config_table[] = {
+ {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
+ {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
+ {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
+ mpc85xx_config_via_usbide, {0,0,0}},
+ {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
+ mpc85xx_config_via_usb, {0,0,0}},
+ {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
+ mpc85xx_config_via_usb2, {0,0,0}},
+ {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
+ mpc85xx_config_via_power, {0,0,0}},
+ {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
+ mpc85xx_config_via_ac97, {0,0,0}},
+ {},
+};
+
+static struct pci_controller hose[] = {
+ { config_table: pci_mpc85xxcds_config_table,},
+#ifdef CONFIG_MPC85XX_PCI2
+ {},
+#endif
+};
+
+#endif /* CONFIG_PCI */
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+ pci_mpc85xx_init(hose);
+#endif
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_pci_setup(void *blob, bd_t *bd)
+{
+ int node, tmp[2];
+ const char *path;
+
+ node = fdt_path_offset(blob, "/aliases");
+ tmp[0] = 0;
+ if (node >= 0) {
+#ifdef CONFIG_PCI1
+ path = fdt_getprop(blob, node, "pci0", NULL);
+ if (path) {
+ tmp[1] = hose[0].last_busno - hose[0].first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+#ifdef CONFIG_MPC85XX_PCI2
+ path = fdt_getprop(blob, node, "pci1", NULL);
+ if (path) {
+ tmp[1] = hose[1].last_busno - hose[1].first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+ }
+}
+#endif
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/mpc85xx/start.o (.bootpg)
+ board/freescale/mpc8541cds/init.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc85xx/start.o (.text)
+ board/freescale/mpc8541cds/init.o (.text)
+ cpu/mpc85xx/traps.o (.text)
+ cpu/mpc85xx/interrupts.o (.text)
+ cpu/mpc85xx/cpu_init.o (.text)
+ cpu/mpc85xx/cpu.o (.text)
+ drivers/net/tsec.o (.text)
+ cpu/mpc85xx/speed.o (.text)
+ cpu/mpc85xx/pci.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
#include <config.h>
#include <mpc85xx.h>
-#define LAWAR_TRGT_PCI1 0x00000000
-#define LAWAR_TRGT_PCIE1 0x00200000
-#define LAWAR_TRGT_PCIE2 0x00100000
-#define LAWAR_TRGT_PCIE3 0x00300000
-#define LAWAR_TRGT_LBC 0x00400000
-#define LAWAR_TRGT_DDR 0x00f00000
-
/*
* TLB0 and TLB1 Entries
*
.long (4f-3f)/8
3:
.long 0
- .long (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
+ .long (LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
.long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
+ .long LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
.long (CFG_PCI1_IO_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
+ .long LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
.long (CFG_LBC_CACHE_BASE>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
+ .long LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
.long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M)
+ .long LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M)
.long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
+ .long LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
.long (CFG_PCIE2_MEM_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
+ .long LAWAR_EN | LAWAR_TRGT_IF_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
.long (CFG_PCIE2_IO_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_64K)
+ .long LAWAR_EN | LAWAR_TRGT_IF_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_64K)
/* contains both PCIE3 MEM & IO space */
.long (CFG_PCIE3_MEM_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_4M)
+ .long LAWAR_EN | LAWAR_TRGT_IF_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_4M)
4:
entry_end
#include <asm/io.h>
#include <spd.h>
#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
#include "../common/pixis.h"
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-extern void ft_cpu_setup(void *blob, bd_t *bd);
-#endif
-
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
int checkboard (void)
{
- volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
- volatile ccsr_lbc_t *lbc = &immap->im_lbc;
- volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+ volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
if ((uint)&gur->porpllsr != 0xe00e0000) {
printf("immap size error %x\n",&gur->porpllsr);
void
pci_init_board(void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
uint devdisr = gur->devdisr;
uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
return val;
}
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+#if defined(CONFIG_OF_BOARD_SETUP)
+
void
ft_board_setup(void *blob, bd_t *bd)
{
- u32 *p;
- int len;
+ int node, tmp[2];
+ const char *path;
ft_cpu_setup(blob, bd);
- p = ft_get_prop(blob, "/memory/reg", &len);
- if (p != NULL) {
- *p++ = cpu_to_be32(bd->bi_memstart);
- *p = cpu_to_be32(bd->bi_memsize);
- }
+ node = fdt_path_offset(blob, "/aliases");
+ tmp[0] = 0;
+ if (node >= 0) {
#ifdef CONFIG_PCI1
- p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
- if (p != NULL) {
- p[0] = 0;
- p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
- debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
- }
-#endif
-#ifdef CONFIG_PCIE1
- p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len);
- if (p != NULL) {
- p[0] = 0;
- p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
- debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]);
- }
+ path = fdt_getprop(blob, node, "pci0", NULL);
+ if (path) {
+ tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
#endif
#ifdef CONFIG_PCIE2
- p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len);
- if (p != NULL) {
- p[0] = 0;
- p[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
- debug("PCI@9000 first_busno=%d last_busno=%d\n",p[0],p[1]);
- }
+ path = fdt_getprop(blob, node, "pci1", NULL);
+ if (path) {
+ tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+#ifdef CONFIG_PCIE1
+ path = fdt_getprop(blob, node, "pci2", NULL);
+ if (path) {
+ tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
#endif
#ifdef CONFIG_PCIE3
- p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@b000/bus-range", &len);
- if (p != NULL) {
- p[0] = 0;
- p[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;;
- debug("PCI@b000 first_busno=%d last_busno=%d\n",p[0],p[1]);
- }
+ path = fdt_getprop(blob, node, "pci3", NULL);
+ if (path) {
+ tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
#endif
+ }
}
#endif
--- /dev/null
+#
+# Copyright 2004 Freescale Semiconductor.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o \
+ ../common/cadmus.o \
+ ../common/eeprom.o \
+ ../common/ft_board.o \
+ ../common/via.o
+
+SOBJS := init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# Copyright 2004, 2007 Freescale Semiconductor.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8548cds board
+#
+ifndef TEXT_BASE
+TEXT_BASE = 0xfff80000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1
--- /dev/null
+/*
+ * Copyright 2004, 2007 Freescale Semiconductor.
+ * Copyright 2002,2003, Motorola Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+/*
+ * TLB0 and TLB1 Entries
+ *
+ * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
+ * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
+ * these TLB entries are established.
+ *
+ * The TLB entries for DDR are dynamically setup in spd_sdram()
+ * and use TLB1 Entries 8 through 15 as needed according to the
+ * size of DDR memory.
+ *
+ * MAS0: tlbsel, esel, nv
+ * MAS1: valid, iprot, tid, ts, tsize
+ * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
+ */
+
+#define entry_start \
+ mflr r1 ; \
+ bl 0f ;
+
+#define entry_end \
+0: mflr r0 ; \
+ mtlr r1 ; \
+ blr ;
+
+
+ .section .bootpg, "ax"
+ .globl tlb1_entry
+tlb1_entry:
+ entry_start
+
+ /*
+ * Number of TLB0 and TLB1 entries in the following table
+ */
+ .long (2f-1f)/16
+
+1:
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+ /*
+ * TLB0 4K Non-cacheable, guarded
+ * 0xff700000 4K Initial CCSRBAR mapping
+ *
+ * This ends up at a TLB0 Index==0 entry, and must not collide
+ * with other TLB0 Entries.
+ */
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+#else
+#error("Update the number of table entries in tlb1_entry")
+#endif
+
+ /*
+ * TLB0 16K Cacheable, guarded
+ * Temporary Global data for initialization
+ *
+ * Use four 4K TLB0 entries. These entries must be cacheable
+ * as they provide the bootstrap memory before the memory
+ * controler and real memory have been configured.
+ *
+ * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+ * and must not collide with other TLB0 entries.
+ */
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
+ 0,0,0,0,0,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+ 0,0,0,0,0,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+ 0,0,0,0,0,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+ 0,0,0,0,0,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+
+ /*
+ * TLB 0: 16M Non-cacheable, guarded
+ * 0xff000000 16M FLASH
+ * Out of reset this entry is only 4K.
+ */
+ .long TLB1_MAS0(1, 0, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_BOOT_BLOCK), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_BOOT_BLOCK), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 1: 1G Non-cacheable, guarded
+ * 0x80000000 1G PCI1/PCIE 8,9,a,b
+ */
+ .long TLB1_MAS0(1, 1, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI_PHYS), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI_PHYS), 0,0,0,0,0,1,0,1,0,1)
+
+#ifdef CFG_RIO_MEM_PHYS
+ /*
+ * TLB 2: 256M Non-cacheable, guarded
+ */
+ .long TLB1_MAS0(1, 2, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_PHYS),
+ 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_PHYS), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 3: 256M Non-cacheable, guarded
+ */
+ .long TLB1_MAS0(1, 3, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_PHYS + 0x10000000),
+ 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_PHYS + 0x10000000),
+ 0,0,0,0,0,1,0,1,0,1)
+#endif
+ /*
+ * TLB 5: 64M Non-cacheable, guarded
+ * 0xe000_0000 1M CCSRBAR
+ * 0xe200_0000 1M PCI1 IO
+ * 0xe210_0000 1M PCI2 IO
+ * 0xe300_0000 1M PCIe IO
+ */
+ .long TLB1_MAS0(1, 5, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 6: 64M Cacheable, non-guarded
+ * 0xf000_0000 64M LBC SDRAM
+ */
+ .long TLB1_MAS0(1, 6, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 7: 64M Non-cacheable, guarded
+ * 0xf8000000 64M CADMUS registers, relocated L2SRAM
+ */
+ .long TLB1_MAS0(1, 7, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+2:
+ entry_end
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000 0x7fff_ffff DDR 2G
+ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
+ * 0xa000_0000 0xbfff_ffff PCIe MEM 512M
+ * 0xc000_0000 0xdfff_ffff RapidIO 512M
+ * 0xe000_0000 0xe000_ffff CCSR 1M
+ * 0xe200_0000 0xe10f_ffff PCI1 IO 1M
+ * 0xe280_0000 0xe20f_ffff PCI2 IO 1M
+ * 0xe300_0000 0xe30f_ffff PCIe IO 1M
+ * 0xf000_0000 0xf3ff_ffff SDRAM 64M
+ * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
+ * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
+ * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
+ *
+ * Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ * LAW 0 is reserved for boot mapping
+ */
+
+ .section .bootpg, "ax"
+ .globl law_entry
+law_entry:
+ entry_start
+
+ .long (4f-3f)/8
+3:
+ .long 0
+ .long (LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
+
+#ifdef CFG_PCI1_MEM_PHYS
+ .long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
+
+ .long (CFG_PCI1_IO_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
+#endif
+
+#ifdef CFG_PCI2_MEM_PHYS
+ .long (CFG_PCI2_MEM_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
+
+ .long (CFG_PCI2_IO_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)
+#endif
+
+#ifdef CFG_PCIE1_MEM_PHYS
+ .long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
+
+ .long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
+#endif
+
+ /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+ .long (CFG_LBC_CACHE_BASE>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
+
+#ifdef CFG_RIO_MEM_PHYS
+ .long (CFG_RIO_MEM_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)
+#endif
+4:
+ entry_end
--- /dev/null
+/*
+ * Copyright 2004, 2007 Freescale Semiconductor.
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/immap_fsl_pci.h>
+#include <spd.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+#include "../common/cadmus.h"
+#include "../common/eeprom.h"
+#include "../common/via.h"
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern long int spd_sdram(void);
+
+void local_bus_init(void);
+void sdram_init(void);
+
+int board_early_init_f (void)
+{
+ return 0;
+}
+
+int checkboard (void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
+
+ /* PCI slot in USER bits CSR[6:7] by convention. */
+ uint pci_slot = get_pci_slot ();
+
+ uint cpu_board_rev = get_cpu_board_revision ();
+
+ printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
+ get_board_version (), pci_slot);
+
+ printf ("CPU Board Revision %d.%d (0x%04x)\n",
+ MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
+ MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
+ /*
+ * Initialize local bus.
+ */
+ local_bus_init ();
+
+ /*
+ * Fix CPU2 errata: A core hang possible while executing a
+ * msync instruction and a snoopable transaction from an I/O
+ * master tagged to make quick forward progress is present.
+ */
+ ecm->eebpcr |= (1 << 16);
+
+ /*
+ * Hack TSEC 3 and 4 IO voltages.
+ */
+ gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
+
+ ecm->eedr = 0xffffffff; /* clear ecm errors */
+ ecm->eeer = 0xffffffff; /* enable ecm errors */
+ return 0;
+}
+
+long int
+initdram(int board_type)
+{
+ long dram_size = 0;
+
+ puts("Initializing\n");
+
+#if defined(CONFIG_DDR_DLL)
+ {
+ /*
+ * Work around to stabilize DDR DLL MSYNC_IN.
+ * Errata DDR9 seems to have been fixed.
+ * This is now the workaround for Errata DDR11:
+ * Override DLL = 1, Course Adj = 1, Tap Select = 0
+ */
+
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+
+ gur->ddrdllcr = 0x81000000;
+ asm("sync;isync;msync");
+ udelay(200);
+ }
+#endif
+ dram_size = spd_sdram();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /*
+ * Initialize and enable DDR ECC.
+ */
+ ddr_enable_ecc(dram_size);
+#endif
+ /*
+ * SDRAM Initialization
+ */
+ sdram_init();
+
+ puts(" DDR: ");
+ return dram_size;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+
+ uint clkdiv;
+ uint lbc_hz;
+ sys_info_t sysinfo;
+
+ get_sys_info(&sysinfo);
+ clkdiv = (lbc->lcrr & 0x0f) * 2;
+ lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+ gur->lbiuiplldcr1 = 0x00078080;
+ if (clkdiv == 16) {
+ gur->lbiuiplldcr0 = 0x7c0f1bf0;
+ } else if (clkdiv == 8) {
+ gur->lbiuiplldcr0 = 0x6c0f1bf0;
+ } else if (clkdiv == 4) {
+ gur->lbiuiplldcr0 = 0x5c0f1bf0;
+ }
+
+ lbc->lcrr |= 0x00030000;
+
+ asm("sync;isync;msync");
+
+ lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
+ lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
+}
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+void
+sdram_init(void)
+{
+#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
+
+ uint idx;
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+ uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+ uint cpu_board_rev;
+ uint lsdmr_common;
+
+ puts(" SDRAM: ");
+
+ print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+
+ /*
+ * Setup SDRAM Base and Option Registers
+ */
+ lbc->or2 = CFG_OR2_PRELIM;
+ asm("msync");
+
+ lbc->br2 = CFG_BR2_PRELIM;
+ asm("msync");
+
+ lbc->lbcr = CFG_LBC_LBCR;
+ asm("msync");
+
+
+ lbc->lsrt = CFG_LBC_LSRT;
+ lbc->mrtpr = CFG_LBC_MRTPR;
+ asm("msync");
+
+ /*
+ * MPC8548 uses "new" 15-16 style addressing.
+ */
+ cpu_board_rev = get_cpu_board_revision();
+ lsdmr_common = CFG_LBC_LSDMR_COMMON;
+ lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
+
+ /*
+ * Issue PRECHARGE ALL command.
+ */
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ /*
+ * Issue 8 AUTO REFRESH commands.
+ */
+ for (idx = 0; idx < 8; idx++) {
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+ }
+
+ /*
+ * Issue 8 MODE-set command.
+ */
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ /*
+ * Issue NORMAL OP command.
+ */
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(200); /* Overkill. Must wait > 200 bus cycles */
+
+#endif /* enable SDRAM init */
+}
+
+#if defined(CFG_DRAM_TEST)
+int
+testdram(void)
+{
+ uint *pstart = (uint *) CFG_MEMTEST_START;
+ uint *pend = (uint *) CFG_MEMTEST_END;
+ uint *p;
+
+ printf("Testing DRAM from 0x%08x to 0x%08x\n",
+ CFG_MEMTEST_START,
+ CFG_MEMTEST_END);
+
+ printf("DRAM test phase 1:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf ("DRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("DRAM test phase 2:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf ("DRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("DRAM test passed.\n");
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
+/* For some reason the Tundra PCI bridge shows up on itself as a
+ * different device. Work around that by refusing to configure it.
+ */
+void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
+
+static struct pci_config_table pci_mpc85xxcds_config_table[] = {
+ {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
+ {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
+ {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
+ mpc85xx_config_via_usbide, {0,0,0}},
+ {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
+ mpc85xx_config_via_usb, {0,0,0}},
+ {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
+ mpc85xx_config_via_usb2, {0,0,0}},
+ {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
+ mpc85xx_config_via_power, {0,0,0}},
+ {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
+ mpc85xx_config_via_ac97, {0,0,0}},
+ {},
+};
+
+static struct pci_controller pci1_hose = {
+ config_table: pci_mpc85xxcds_config_table};
+#endif /* CONFIG_PCI */
+
+#ifdef CONFIG_PCI2
+static struct pci_controller pci2_hose;
+#endif /* CONFIG_PCI2 */
+
+#ifdef CONFIG_PCIE1
+static struct pci_controller pcie1_hose;
+#endif /* CONFIG_PCIE1 */
+
+int first_free_busno=0;
+
+void
+pci_init_board(void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+ uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
+
+
+#ifdef CONFIG_PCI1
+{
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
+ extern void fsl_pci_init(struct pci_controller *hose);
+ struct pci_controller *hose = &pci1_hose;
+ struct pci_config_table *table;
+
+ uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
+ uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
+ uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
+
+ uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);
+
+ uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
+
+ if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
+ printf (" PCI: %d bit, %s MHz, %s, %s, %s\n",
+ (pci_32) ? 32 : 64,
+ (pci_speed == 33333000) ? "33" :
+ (pci_speed == 66666000) ? "66" : "unknown",
+ pci_clk_sel ? "sync" : "async",
+ pci_agent ? "agent" : "host",
+ pci_arb ? "arbiter" : "external-arbiter"
+ );
+
+
+ /* inbound */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI_MEMORY_BUS,
+ CFG_PCI_MEMORY_PHYS,
+ CFG_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+
+ /* outbound memory */
+ pci_set_region(hose->regions + 1,
+ CFG_PCI1_MEM_BASE,
+ CFG_PCI1_MEM_PHYS,
+ CFG_PCI1_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(hose->regions + 2,
+ CFG_PCI1_IO_BASE,
+ CFG_PCI1_IO_PHYS,
+ CFG_PCI1_IO_SIZE,
+ PCI_REGION_IO);
+ hose->region_count = 3;
+
+ /* relocate config table pointers */
+ hose->config_table = \
+ (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off);
+ for (table = hose->config_table; table && table->vendor; table++)
+ table->config_device += gd->reloc_off;
+
+ hose->first_busno=first_free_busno;
+ pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+ fsl_pci_init(hose);
+ first_free_busno=hose->last_busno+1;
+ printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
+#ifdef CONFIG_PCIX_CHECK
+ if (!(gur->pordevsr & PORDEVSR_PCI)) {
+ /* PCI-X init */
+ if (CONFIG_SYS_CLK_FREQ < 66000000)
+ printf("PCI-X will only work at 66 MHz\n");
+
+ reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
+ | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
+ pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
+ }
+#endif
+ } else {
+ printf (" PCI: disabled\n");
+ }
+}
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
+#endif
+
+#ifdef CONFIG_PCI2
+{
+ uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
+ uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
+ if (pci_dual) {
+ printf (" PCI2: 32 bit, 66 MHz, %s\n",
+ pci2_clk_sel ? "sync" : "async");
+ } else {
+ printf (" PCI2: disabled\n");
+ }
+}
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */
+#endif /* CONFIG_PCI2 */
+
+#ifdef CONFIG_PCIE1
+{
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
+ extern void fsl_pci_init(struct pci_controller *hose);
+ struct pci_controller *hose = &pcie1_hose;
+ int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
+
+ int pcie_configured = io_sel >= 1;
+
+ if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
+ printf ("\n PCIE connected to slot as %s (base address %x)",
+ pcie_ep ? "End Point" : "Root Complex",
+ (uint)pci);
+
+ if (pci->pme_msg_det) {
+ pci->pme_msg_det = 0xffffffff;
+ debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
+ }
+ printf ("\n");
+
+ /* inbound */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI_MEMORY_BUS,
+ CFG_PCI_MEMORY_PHYS,
+ CFG_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ /* outbound memory */
+ pci_set_region(hose->regions + 1,
+ CFG_PCIE1_MEM_BASE,
+ CFG_PCIE1_MEM_PHYS,
+ CFG_PCIE1_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(hose->regions + 2,
+ CFG_PCIE1_IO_BASE,
+ CFG_PCIE1_IO_PHYS,
+ CFG_PCIE1_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 3;
+
+ hose->first_busno=first_free_busno;
+ pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+ fsl_pci_init(hose);
+ printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno);
+
+ first_free_busno=hose->last_busno+1;
+
+ } else {
+ printf (" PCIE: disabled\n");
+ }
+ }
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+#endif
+
+}
+
+int last_stage_init(void)
+{
+ unsigned short temp;
+
+ /* Change the resistors for the PHY */
+ /* This is needed to get the RGMII working for the 1.3+
+ * CDS cards */
+ if (get_board_version() == 0x13) {
+ miiphy_write(CONFIG_TSEC1_NAME,
+ TSEC1_PHY_ADDR, 29, 18);
+
+ miiphy_read(CONFIG_TSEC1_NAME,
+ TSEC1_PHY_ADDR, 30, &temp);
+
+ temp = (temp & 0xf03f);
+ temp |= 2 << 9; /* 36 ohm */
+ temp |= 2 << 6; /* 39 ohm */
+
+ miiphy_write(CONFIG_TSEC1_NAME,
+ TSEC1_PHY_ADDR, 30, temp);
+
+ miiphy_write(CONFIG_TSEC1_NAME,
+ TSEC1_PHY_ADDR, 29, 3);
+
+ miiphy_write(CONFIG_TSEC1_NAME,
+ TSEC1_PHY_ADDR, 30, 0x8000);
+ }
+
+ return 0;
+}
+
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_pci_setup(void *blob, bd_t *bd)
+{
+ int node, tmp[2];
+ const char *path;
+
+ node = fdt_path_offset(blob, "/aliases");
+ tmp[0] = 0;
+ if (node >= 0) {
+#ifdef CONFIG_PCI1
+ path = fdt_getprop(blob, node, "pci0", NULL);
+ if (path) {
+ tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+#ifdef CONFIG_PCIE1
+ path = fdt_getprop(blob, node, "pci1", NULL);
+ if (path) {
+ tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+ }
+}
+#endif
--- /dev/null
+/*
+ * Copyright 2004, 2007 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/mpc85xx/start.o (.bootpg)
+ board/freescale/mpc8548cds/init.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc85xx/start.o (.text)
+ board/freescale/mpc8548cds/init.o (.text)
+ cpu/mpc85xx/traps.o (.text)
+ cpu/mpc85xx/interrupts.o (.text)
+ cpu/mpc85xx/cpu_init.o (.text)
+ cpu/mpc85xx/cpu.o (.text)
+ drivers/net/tsec.o (.text)
+ cpu/mpc85xx/speed.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+#
+# Copyright 2004 Freescale Semiconductor.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o \
+ ../common/cadmus.o \
+ ../common/eeprom.o \
+ ../common/ft_board.o \
+ ../common/via.o
+
+SOBJS := init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# Copyright 2004 Freescale Semiconductor.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8555cds board
+#
+TEXT_BASE = 0xfff80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8555=1
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2002,2003, Motorola Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+
+/*
+ * TLB0 and TLB1 Entries
+ *
+ * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
+ * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
+ * these TLB entries are established.
+ *
+ * The TLB entries for DDR are dynamically setup in spd_sdram()
+ * and use TLB1 Entries 8 through 15 as needed according to the
+ * size of DDR memory.
+ *
+ * MAS0: tlbsel, esel, nv
+ * MAS1: valid, iprot, tid, ts, tsize
+ * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
+ */
+
+#define entry_start \
+ mflr r1 ; \
+ bl 0f ;
+
+#define entry_end \
+0: mflr r0 ; \
+ mtlr r1 ; \
+ blr ;
+
+
+ .section .bootpg, "ax"
+ .globl tlb1_entry
+tlb1_entry:
+ entry_start
+
+ /*
+ * Number of TLB0 and TLB1 entries in the following table
+ */
+ .long 13
+
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+ /*
+ * TLB0 4K Non-cacheable, guarded
+ * 0xff700000 4K Initial CCSRBAR mapping
+ *
+ * This ends up at a TLB0 Index==0 entry, and must not collide
+ * with other TLB0 Entries.
+ */
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+#else
+#error("Update the number of table entries in tlb1_entry")
+#endif
+
+ /*
+ * TLB0 16K Cacheable, non-guarded
+ * 0xd001_0000 16K Temporary Global data for initialization
+ *
+ * Use four 4K TLB0 entries. These entries must be cacheable
+ * as they provide the bootstrap memory before the memory
+ * controler and real memory have been configured.
+ *
+ * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+ * and must not collide with other TLB0 entries.
+ */
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+
+ /*
+ * TLB 0: 16M Non-cacheable, guarded
+ * 0xff000000 16M FLASH
+ * Out of reset this entry is only 4K.
+ */
+ .long TLB1_MAS0(1, 0, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 1: 256M Non-cacheable, guarded
+ * 0x80000000 256M PCI1 MEM First half
+ */
+ .long TLB1_MAS0(1, 1, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 2: 256M Non-cacheable, guarded
+ * 0x90000000 256M PCI1 MEM Second half
+ */
+ .long TLB1_MAS0(1, 2, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
+ 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 3: 256M Non-cacheable, guarded
+ * 0xa0000000 256M PCI2 MEM First half
+ */
+ .long TLB1_MAS0(1, 3, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 4: 256M Non-cacheable, guarded
+ * 0xb0000000 256M PCI2 MEM Second half
+ */
+ .long TLB1_MAS0(1, 4, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000),
+ 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 5: 64M Non-cacheable, guarded
+ * 0xe000_0000 1M CCSRBAR
+ * 0xe200_0000 16M PCI1 IO
+ * 0xe300_0000 16M PCI2 IO
+ */
+ .long TLB1_MAS0(1, 5, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 6: 64M Cacheable, non-guarded
+ * 0xf000_0000 64M LBC SDRAM
+ */
+ .long TLB1_MAS0(1, 6, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 7: 1M Non-cacheable, guarded
+ * 0xf8000000 1M CADMUS registers
+ */
+ .long TLB1_MAS0(1, 7, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
+ .long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1)
+
+ entry_end
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000 0x7fff_ffff DDR 2G
+ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
+ * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
+ * 0xe000_0000 0xe000_ffff CCSR 1M
+ * 0xe200_0000 0xe20f_ffff PCI1 IO 1M
+ * 0xe210_0000 0xe21f_ffff PCI2 IO 1M
+ * 0xf000_0000 0xf7ff_ffff SDRAM 128M
+ * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
+ * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
+ * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
+ *
+ * Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ * The defines below are 1-off of the actual LAWAR0 usage.
+ * So LAWAR3 define uses the LAWAR4 register in the ECM.
+ */
+
+#define LAWBAR0 0
+#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+
+#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
+#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
+#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
+
+#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff)
+#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
+
+/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+ .section .bootpg, "ax"
+ .globl law_entry
+
+law_entry:
+ entry_start
+ .long 6
+ .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
+ .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5
+ entry_end
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <ioports.h>
+#include <spd.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+#include "../common/cadmus.h"
+#include "../common/eeprom.h"
+#include "../common/via.h"
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+extern long int spd_sdram(void);
+
+void local_bus_init(void);
+void sdram_init(void);
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+ /* Port A configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
+ /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
+ /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
+ /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
+ /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
+ /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
+ /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
+ /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
+ /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
+ /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
+ /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
+ /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
+ /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
+ /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
+ /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
+ /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
+ /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
+ /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
+ /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
+ /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
+ /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
+ /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
+ /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
+ /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
+ /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
+ /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
+ /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
+ /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
+ /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
+ /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
+ /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
+ /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
+ },
+
+ /* Port B configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
+ /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
+ /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
+ /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
+ /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
+ /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
+ /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
+ /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
+ /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
+ /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
+ /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
+ /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
+ /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
+ /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
+ /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
+ /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
+ /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
+ /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
+ /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
+ /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
+ /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ },
+
+ /* Port C */
+ { /* conf ppar psor pdir podr pdat */
+ /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
+ /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
+ /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
+ /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
+ /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
+ /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
+ /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
+ /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
+ /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
+ /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
+ /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
+ /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
+ /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
+ /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
+ /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
+ /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
+ /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
+ /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
+ /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
+ /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
+ /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
+ /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
+ /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
+ /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
+ /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
+ /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
+ /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
+ /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
+ /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
+ /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
+ /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
+ /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
+ },
+
+ /* Port D */
+ { /* conf ppar psor pdir podr pdat */
+ /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
+ /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
+ /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
+ /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
+ /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
+ /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
+ /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
+ /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
+ /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
+ /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
+ /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
+ /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
+ /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
+ /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
+ /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
+ /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
+ /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
+ /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
+ /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
+ /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
+ /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
+ /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
+ /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
+ /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
+ /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
+ /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
+ /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
+ /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
+ /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ }
+};
+
+int board_early_init_f (void)
+{
+ return 0;
+}
+
+int checkboard (void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+
+ /* PCI slot in USER bits CSR[6:7] by convention. */
+ uint pci_slot = get_pci_slot ();
+
+ uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
+ uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
+ uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
+ uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
+
+ uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
+
+ uint cpu_board_rev = get_cpu_board_revision ();
+
+ printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
+ get_board_version (), pci_slot);
+
+ printf ("CPU Board Revision %d.%d (0x%04x)\n",
+ MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
+ MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
+
+ printf (" PCI1: %d bit, %s MHz, %s\n",
+ (pci1_32) ? 32 : 64,
+ (pci1_speed == 33000000) ? "33" :
+ (pci1_speed == 66000000) ? "66" : "unknown",
+ pci1_clk_sel ? "sync" : "async");
+
+ if (pci_dual) {
+ printf (" PCI2: 32 bit, 66 MHz, %s\n",
+ pci2_clk_sel ? "sync" : "async");
+ } else {
+ printf (" PCI2: disabled\n");
+ }
+
+ /*
+ * Initialize local bus.
+ */
+ local_bus_init ();
+
+ return 0;
+}
+
+long int
+initdram(int board_type)
+{
+ long dram_size = 0;
+
+ puts("Initializing\n");
+
+#if defined(CONFIG_DDR_DLL)
+ {
+ /*
+ * Work around to stabilize DDR DLL MSYNC_IN.
+ * Errata DDR9 seems to have been fixed.
+ * This is now the workaround for Errata DDR11:
+ * Override DLL = 1, Course Adj = 1, Tap Select = 0
+ */
+
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+
+ gur->ddrdllcr = 0x81000000;
+ asm("sync;isync;msync");
+ udelay(200);
+ }
+#endif
+ dram_size = spd_sdram();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /*
+ * Initialize and enable DDR ECC.
+ */
+ ddr_enable_ecc(dram_size);
+#endif
+ /*
+ * SDRAM Initialization
+ */
+ sdram_init();
+
+ puts(" DDR: ");
+ return dram_size;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+
+ uint clkdiv;
+ uint lbc_hz;
+ sys_info_t sysinfo;
+ uint temp_lbcdll;
+
+ /*
+ * Errata LBC11.
+ * Fix Local Bus clock glitch when DLL is enabled.
+ *
+ * If localbus freq is < 66Mhz, DLL bypass mode must be used.
+ * If localbus freq is > 133Mhz, DLL can be safely enabled.
+ * Between 66 and 133, the DLL is enabled with an override workaround.
+ */
+
+ get_sys_info(&sysinfo);
+ clkdiv = lbc->lcrr & 0x0f;
+ lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+ if (lbc_hz < 66) {
+ lbc->lcrr |= 0x80000000; /* DLL Bypass */
+
+ } else if (lbc_hz >= 133) {
+ lbc->lcrr &= (~0x80000000); /* DLL Enabled */
+
+ } else {
+ lbc->lcrr &= (~0x8000000); /* DLL Enabled */
+ udelay(200);
+
+ /*
+ * Sample LBC DLL ctrl reg, upshift it to set the
+ * override bits.
+ */
+ temp_lbcdll = gur->lbcdllcr;
+ gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
+ asm("sync;isync;msync");
+ }
+}
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+void
+sdram_init(void)
+{
+#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
+
+ uint idx;
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+ uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+ uint cpu_board_rev;
+ uint lsdmr_common;
+
+ puts(" SDRAM: ");
+
+ print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+
+ /*
+ * Setup SDRAM Base and Option Registers
+ */
+ lbc->or2 = CFG_OR2_PRELIM;
+ asm("msync");
+
+ lbc->br2 = CFG_BR2_PRELIM;
+ asm("msync");
+
+ lbc->lbcr = CFG_LBC_LBCR;
+ asm("msync");
+
+ lbc->lsrt = CFG_LBC_LSRT;
+ lbc->mrtpr = CFG_LBC_MRTPR;
+ asm("msync");
+
+ /*
+ * Determine which address lines to use baed on CPU board rev.
+ */
+ cpu_board_rev = get_cpu_board_revision();
+ lsdmr_common = CFG_LBC_LSDMR_COMMON;
+ if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
+ lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
+ } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
+ lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
+ } else {
+ /*
+ * Assume something unable to identify itself is
+ * really old, and likely has lines 16/17 mapped.
+ */
+ lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
+ }
+
+ /*
+ * Issue PRECHARGE ALL command.
+ */
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ /*
+ * Issue 8 AUTO REFRESH commands.
+ */
+ for (idx = 0; idx < 8; idx++) {
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+ }
+
+ /*
+ * Issue 8 MODE-set command.
+ */
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ /*
+ * Issue NORMAL OP command.
+ */
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(200); /* Overkill. Must wait > 200 bus cycles */
+
+#endif /* enable SDRAM init */
+}
+
+#if defined(CFG_DRAM_TEST)
+int
+testdram(void)
+{
+ uint *pstart = (uint *) CFG_MEMTEST_START;
+ uint *pend = (uint *) CFG_MEMTEST_END;
+ uint *p;
+
+ printf("Testing DRAM from 0x%08x to 0x%08x\n",
+ CFG_MEMTEST_START,
+ CFG_MEMTEST_END);
+
+ printf("DRAM test phase 1:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf ("DRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("DRAM test phase 2:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf ("DRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("DRAM test passed.\n");
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_PCI
+/* For some reason the Tundra PCI bridge shows up on itself as a
+ * different device. Work around that by refusing to configure it
+ */
+void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
+
+static struct pci_config_table pci_mpc85xxcds_config_table[] = {
+ {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
+ {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
+ {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
+ mpc85xx_config_via_usbide, {0,0,0}},
+ {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
+ mpc85xx_config_via_usb, {0,0,0}},
+ {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
+ mpc85xx_config_via_usb2, {0,0,0}},
+ {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
+ mpc85xx_config_via_power, {0,0,0}},
+ {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
+ mpc85xx_config_via_ac97, {0,0,0}},
+ {},
+};
+
+
+static struct pci_controller hose[] = {
+ {
+ config_table: pci_mpc85xxcds_config_table,
+ },
+#ifdef CONFIG_MPC85XX_PCI2
+ {},
+#endif
+};
+
+#endif
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+ pci_mpc85xx_init(hose);
+#endif
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_pci_setup(void *blob, bd_t *bd)
+{
+ int node, tmp[2];
+ const char *path;
+
+ node = fdt_path_offset(blob, "/aliases");
+ tmp[0] = 0;
+ if (node >= 0) {
+#ifdef CONFIG_PCI1
+ path = fdt_getprop(blob, node, "pci0", NULL);
+ if (path) {
+ tmp[1] = hose[0].last_busno - hose[0].first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+#ifdef CONFIG_MPC85XX_PCI2
+ path = fdt_getprop(blob, node, "pci1", NULL);
+ if (path) {
+ tmp[1] = hose[1].last_busno - hose[1].first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+ }
+}
+#endif
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/mpc85xx/start.o (.bootpg)
+ board/freescale/mpc8555cds/init.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc85xx/start.o (.text)
+ board/freescale/mpc8555cds/init.o (.text)
+ cpu/mpc85xx/traps.o (.text)
+ cpu/mpc85xx/interrupts.o (.text)
+ cpu/mpc85xx/cpu_init.o (.text)
+ cpu/mpc85xx/cpu.o (.text)
+ drivers/net/tsec.o (.text)
+ cpu/mpc85xx/speed.o (.text)
+ cpu/mpc85xx/pci.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o
+SOBJS := init.o
+#SOBJS :=
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+# Copyright 2004 Freescale Semiconductor.
+# Modified by Xianghua Xiao, X.Xiao@motorola.com
+# (C) Copyright 2002,2003 Motorola Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8560ads board
+# default CCARBAR is at 0xff700000
+# assume U-Boot is less than 0.5MB
+#
+TEXT_BASE = 0xfff80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Copyright (C) 2002,2003, Motorola Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+
+/*
+ * TLB0 and TLB1 Entries
+ *
+ * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
+ * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
+ * these TLB entries are established.
+ *
+ * The TLB entries for DDR are dynamically setup in spd_sdram()
+ * and use TLB1 Entries 8 through 15 as needed according to the
+ * size of DDR memory.
+ *
+ * MAS0: tlbsel, esel, nv
+ * MAS1: valid, iprot, tid, ts, tsize
+ * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
+ */
+
+#define entry_start \
+ mflr r1 ; \
+ bl 0f ;
+
+#define entry_end \
+0: mflr r0 ; \
+ mtlr r1 ; \
+ blr ;
+
+
+ .section .bootpg, "ax"
+ .globl tlb1_entry
+tlb1_entry:
+ entry_start
+
+ /*
+ * Number of TLB0 and TLB1 entries in the following table
+ */
+ .long 13
+
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+ /*
+ * TLB0 4K Non-cacheable, guarded
+ * 0xff700000 4K Initial CCSRBAR mapping
+ *
+ * This ends up at a TLB0 Index==0 entry, and must not collide
+ * with other TLB0 Entries.
+ */
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+#else
+#error("Update the number of table entries in tlb1_entry")
+#endif
+
+ /*
+ * TLB0 16K Cacheable, non-guarded
+ * 0xd001_0000 16K Temporary Global data for initialization
+ *
+ * Use four 4K TLB0 entries. These entries must be cacheable
+ * as they provide the bootstrap memory before the memory
+ * controler and real memory have been configured.
+ *
+ * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+ * and must not collide with other TLB0 entries.
+ */
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+
+ /*
+ * TLB 0: 16M Non-cacheable, guarded
+ * 0xff000000 16M FLASH
+ * Out of reset this entry is only 4K.
+ */
+ .long TLB1_MAS0(1, 0, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 1: 256M Non-cacheable, guarded
+ * 0x80000000 256M PCI1 MEM First half
+ */
+ .long TLB1_MAS0(1, 1, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 2: 256M Non-cacheable, guarded
+ * 0x90000000 256M PCI1 MEM Second half
+ */
+ .long TLB1_MAS0(1, 2, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
+ 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 3: 256M Non-cacheable, guarded
+ * 0xc0000000 256M Rapid IO MEM First half
+ */
+ .long TLB1_MAS0(1, 3, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 4: 256M Non-cacheable, guarded
+ * 0xd0000000 256M Rapid IO MEM Second half
+ */
+ .long TLB1_MAS0(1, 4, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),
+ 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 5: 64M Non-cacheable, guarded
+ * 0xe000_0000 1M CCSRBAR
+ * 0xe200_0000 16M PCI1 IO
+ */
+ .long TLB1_MAS0(1, 5, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 6: 64M Cacheable, non-guarded
+ * 0xf000_0000 64M LBC SDRAM
+ */
+ .long TLB1_MAS0(1, 6, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 7: 16K Non-cacheable, guarded
+ * 0xf8000000 16K BCSR registers
+ */
+ .long TLB1_MAS0(1, 7, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR), 0,0,0,0,0,1,0,1,0,1)
+
+#if !defined(CONFIG_SPD_EEPROM)
+ /*
+ * TLB 8, 9: 128M DDR
+ * 0x00000000 64M DDR System memory
+ * 0x04000000 64M DDR System memory
+ * Without SPD EEPROM configured DDR, this must be setup manually.
+ * Make sure the TLB count at the top of this table is correct.
+ * Likely it needs to be increased by two for these entries.
+ */
+#error("Update the number of table entries in tlb1_entry")
+ .long TLB1_MAS0(1, 8, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(1, 9, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x4000000),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x4000000),
+ 0,0,0,0,0,1,0,1,0,1)
+#endif
+
+ entry_end
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000 0x7fff_ffff DDR 2G
+ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
+ * 0xc000_0000 0xdfff_ffff RapidIO 512M
+ * 0xe000_0000 0xe000_ffff CCSR 1M
+ * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
+ * 0xf000_0000 0xf7ff_ffff SDRAM 128M
+ * 0xf800_0000 0xf80f_ffff BCSR 1M
+ * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M
+ *
+ * Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+#if !defined(CONFIG_SPD_EEPROM)
+#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
+#else
+#define LAWBAR0 0
+#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+#endif
+
+#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+/*
+ * This is not so much the SDRAM map as it is the whole localbus map.
+ */
+#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
+#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_1M))
+
+/*
+ * Rapid IO at 0xc000_0000 for 512 M
+ */
+#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
+#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+
+ .section .bootpg, "ax"
+ .globl law_entry
+law_entry:
+ entry_start
+ .long 0x05
+ .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
+ .long LAWBAR4,LAWAR4
+ entry_end
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2003,Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <ioports.h>
+#include <spd.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+extern long int spd_sdram(void);
+
+void local_bus_init(void);
+void sdram_init(void);
+long int fixed_sdram(void);
+
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+ /* Port A configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
+ /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
+ /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
+ /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
+ /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
+ /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
+ /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
+ /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
+ /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
+ /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
+ /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
+ /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
+ /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
+ /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
+ /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
+ /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
+ /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
+ /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
+ /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
+ /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
+ /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
+ /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
+ /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
+ /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
+ /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
+ /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
+ /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
+ /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
+ /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
+ /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
+ /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
+ /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
+ },
+
+ /* Port B configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
+ /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
+ /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
+ /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
+ /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
+ /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
+ /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
+ /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
+ /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
+ /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
+ /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
+ /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
+ /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
+ /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
+ /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
+ /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
+ /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
+ /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
+ /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
+ /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
+ /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ },
+
+ /* Port C */
+ { /* conf ppar psor pdir podr pdat */
+ /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
+ /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
+ /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
+ /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
+ /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
+ /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
+ /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
+ /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
+ /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
+ /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
+ /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
+ /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
+ /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
+ /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
+ /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
+ /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
+ /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
+ /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
+ /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
+ /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
+ /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
+ /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
+ /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
+ /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
+ /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
+ /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
+ /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
+ /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
+ /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
+ /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
+ /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
+ /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
+ },
+
+ /* Port D */
+ { /* conf ppar psor pdir podr pdat */
+ /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
+ /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
+ /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
+ /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
+ /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
+ /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
+ /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
+ /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
+ /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
+ /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
+ /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
+ /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
+ /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
+ /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
+ /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
+ /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
+ /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
+ /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
+ /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
+ /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
+ /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
+ /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
+ /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
+ /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
+ /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
+ /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
+ /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
+ /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
+ /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ }
+};
+
+
+/*
+ * MPC8560ADS Board Status & Control Registers
+ */
+typedef struct bcsr_ {
+ volatile unsigned char bcsr0;
+ volatile unsigned char bcsr1;
+ volatile unsigned char bcsr2;
+ volatile unsigned char bcsr3;
+ volatile unsigned char bcsr4;
+ volatile unsigned char bcsr5;
+} bcsr_t;
+
+
+int board_early_init_f (void)
+{
+ return 0;
+}
+
+void reset_phy (void)
+{
+#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
+ volatile bcsr_t *bcsr = (bcsr_t *) CFG_BCSR;
+#endif
+ /* reset Giga bit Ethernet port if needed here */
+
+ /* reset the CPM FEC port */
+#if (CONFIG_ETHER_INDEX == 2)
+ bcsr->bcsr2 &= ~FETH2_RST;
+ udelay(2);
+ bcsr->bcsr2 |= FETH2_RST;
+ udelay(1000);
+#elif (CONFIG_ETHER_INDEX == 3)
+ bcsr->bcsr3 &= ~FETH3_RST;
+ udelay(2);
+ bcsr->bcsr3 |= FETH3_RST;
+ udelay(1000);
+#endif
+#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
+ /* reset PHY */
+ miiphy_reset("FCC1 ETHERNET", 0x0);
+
+ /* change PHY address to 0x02 */
+ bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);
+
+ bb_miiphy_write(NULL, 0x02, PHY_BMCR,
+ PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+#endif /* CONFIG_MII */
+}
+
+
+int checkboard (void)
+{
+ puts("Board: ADS\n");
+
+#ifdef CONFIG_PCI
+ printf(" PCI1: 32 bit, %d MHz (compiled)\n",
+ CONFIG_SYS_CLK_FREQ / 1000000);
+#else
+ printf(" PCI1: disabled\n");
+#endif
+
+ /*
+ * Initialize local bus.
+ */
+ local_bus_init();
+
+ return 0;
+}
+
+
+long int
+initdram(int board_type)
+{
+ long dram_size = 0;
+ extern long spd_sdram (void);
+
+ puts("Initializing\n");
+
+#if defined(CONFIG_DDR_DLL)
+ {
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ uint temp_ddrdll = 0;
+
+ /*
+ * Work around to stabilize DDR DLL
+ */
+ temp_ddrdll = gur->ddrdllcr;
+ gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
+ asm("sync;isync;msync");
+ }
+#endif
+
+#if defined(CONFIG_SPD_EEPROM)
+ dram_size = spd_sdram ();
+#else
+ dram_size = fixed_sdram ();
+#endif
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /*
+ * Initialize and enable DDR ECC.
+ */
+ ddr_enable_ecc(dram_size);
+#endif
+
+ /*
+ * Initialize SDRAM.
+ */
+ sdram_init();
+
+ puts(" DDR: ");
+ return dram_size;
+}
+
+
+/*
+ * Initialize Local Bus
+ */
+
+void
+local_bus_init(void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+
+ uint clkdiv;
+ uint lbc_hz;
+ sys_info_t sysinfo;
+
+ /*
+ * Errata LBC11.
+ * Fix Local Bus clock glitch when DLL is enabled.
+ *
+ * If localbus freq is < 66Mhz, DLL bypass mode must be used.
+ * If localbus freq is > 133Mhz, DLL can be safely enabled.
+ * Between 66 and 133, the DLL is enabled with an override workaround.
+ */
+
+ get_sys_info(&sysinfo);
+ clkdiv = lbc->lcrr & 0x0f;
+ lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+ if (lbc_hz < 66) {
+ lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
+
+ } else if (lbc_hz >= 133) {
+ lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+
+ } else {
+ /*
+ * On REV1 boards, need to change CLKDIV before enable DLL.
+ * Default CLKDIV is 8, change it to 4 temporarily.
+ */
+ uint pvr = get_pvr();
+ uint temp_lbcdll = 0;
+
+ if (pvr == PVR_85xx_REV1) {
+ /* FIXME: Justify the high bit here. */
+ lbc->lcrr = 0x10000004;
+ }
+
+ lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);/* DLL Enabled */
+ udelay(200);
+
+ /*
+ * Sample LBC DLL ctrl reg, upshift it to set the
+ * override bits.
+ */
+ temp_lbcdll = gur->lbcdllcr;
+ gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
+ asm("sync;isync;msync");
+ }
+}
+
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+
+void
+sdram_init(void)
+{
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+ uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+
+ puts(" SDRAM: ");
+ print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+
+ /*
+ * Setup SDRAM Base and Option Registers
+ */
+ lbc->or2 = CFG_OR2_PRELIM;
+ lbc->br2 = CFG_BR2_PRELIM;
+ lbc->lbcr = CFG_LBC_LBCR;
+ asm("msync");
+
+ lbc->lsrt = CFG_LBC_LSRT;
+ lbc->mrtpr = CFG_LBC_MRTPR;
+ asm("sync");
+
+ /*
+ * Configure the SDRAM controller.
+ */
+ lbc->lsdmr = CFG_LBC_LSDMR_1;
+ asm("sync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ lbc->lsdmr = CFG_LBC_LSDMR_2;
+ asm("sync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ lbc->lsdmr = CFG_LBC_LSDMR_3;
+ asm("sync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ lbc->lsdmr = CFG_LBC_LSDMR_4;
+ asm("sync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ lbc->lsdmr = CFG_LBC_LSDMR_5;
+ asm("sync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+}
+
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+ uint *pstart = (uint *) CFG_MEMTEST_START;
+ uint *pend = (uint *) CFG_MEMTEST_END;
+ uint *p;
+
+ printf("SDRAM test phase 1:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("SDRAM test phase 2:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("SDRAM test passed.\n");
+ return 0;
+}
+#endif
+
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ * fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+long int fixed_sdram (void)
+{
+ #ifndef CFG_RAMBOOT
+ volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
+
+ ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
+ ddr->cs0_config = CFG_DDR_CS0_CONFIG;
+ ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
+ ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
+ ddr->sdram_mode = CFG_DDR_MODE;
+ ddr->sdram_interval = CFG_DDR_INTERVAL;
+ #if defined (CONFIG_DDR_ECC)
+ ddr->err_disable = 0x0000000D;
+ ddr->err_sbe = 0x00ff0000;
+ #endif
+ asm("sync;isync;msync");
+ udelay(500);
+ #if defined (CONFIG_DDR_ECC)
+ /* Enable ECC checking */
+ ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
+ #else
+ ddr->sdram_cfg = CFG_DDR_CONTROL;
+ #endif
+ asm("sync; isync; msync");
+ udelay(500);
+ #endif
+ return CFG_SDRAM_SIZE * 1024 * 1024;
+}
+#endif /* !defined(CONFIG_SPD_EEPROM) */
+
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc85xxads_config_table[] = {
+ { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+ PCI_IDSEL_NUMBER, PCI_ANY_ID,
+ pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+ PCI_ENET0_MEMADDR,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
+ } },
+ { }
+};
+#endif
+
+
+static struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+ config_table: pci_mpc85xxads_config_table,
+#endif
+};
+
+#endif /* CONFIG_PCI */
+
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+ pci_mpc85xx_init(&hose);
+#endif /* CONFIG_PCI */
+}
+
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+ int node, tmp[2];
+ const char *path;
+
+ ft_cpu_setup(blob, bd);
+
+ node = fdt_path_offset(blob, "/aliases");
+ tmp[0] = 0;
+ if (node >= 0) {
+#ifdef CONFIG_PCI
+ path = fdt_getprop(blob, node, "pci0", NULL);
+ if (path) {
+ tmp[1] = hose.last_busno - hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+ }
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2002,2003,Motorola,Inc.
+ * Xianghua Xiao, X.Xiao@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/mpc85xx/start.o (.bootpg)
+ board/freescale/mpc8560ads/init.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc85xx/start.o (.text)
+ board/freescale/mpc8560ads/init.o (.text)
+ cpu/mpc85xx/commproc.o (.text)
+ cpu/mpc85xx/traps.o (.text)
+ cpu/mpc85xx/interrupts.o (.text)
+ cpu/mpc85xx/serial_scc.o (.text)
+ cpu/mpc85xx/ether_fcc.o (.text)
+ cpu/mpc85xx/cpu_init.o (.text)
+ cpu/mpc85xx/cpu.o (.text)
+ cpu/mpc85xx/speed.o (.text)
+ cpu/mpc85xx/spd_sdram.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+#
+# Copyright 2004-2007 Freescale Semiconductor.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o bcsr.o
+
+SOBJS := init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright 2007 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include "bcsr.h"
+
+void enable_8568mds_duart()
+{
+ volatile uint* duart_mux = (uint *)(CFG_CCSRBAR + 0xe0060);
+ volatile uint* devices = (uint *)(CFG_CCSRBAR + 0xe0070);
+ volatile u8 *bcsr = (u8 *)(CFG_BCSR);
+
+ *duart_mux = 0x80000000; /* Set the mux to Duart on PMUXCR */
+ *devices = 0; /* Enable all peripheral devices */
+ bcsr[5] |= 0x01; /* Enable Duart in BCSR*/
+}
+
+void enable_8568mds_flash_write()
+{
+ volatile u8 *bcsr = (u8 *)(CFG_BCSR);
+
+ bcsr[9] |= 0x01;
+}
+
+void disable_8568mds_flash_write()
+{
+ volatile u8 *bcsr = (u8 *)(CFG_BCSR);
+
+ bcsr[9] &= ~(0x01);
+}
+
+void enable_8568mds_qe_mdio()
+{
+ u8 *bcsr = (u8 *)(CFG_BCSR);
+
+ bcsr[7] |= 0x01;
+}
--- /dev/null
+/*
+ * Copyright 2007 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __BCSR_H_
+#define __BCSR_H_
+
+#include <common.h>
+
+/* BCSR Bit definitions
+ * BCSR 0 *
+ 0:3 ccb sys pll
+ 4:6 cfg core pll
+ 7 cfg boot seq
+
+ * BCSR 1 *
+ 0:2 cfg rom lock
+ 3:5 cfg host agent
+ 6 PCI IO
+ 7 cfg RIO size
+
+ * BCSR 2 *
+ 0:4 QE PLL
+ 5 QE clock
+ 6 cfg PCI arbiter
+
+ * BCSR 3 *
+ 0 TSEC1 reduce
+ 1 TSEC2 reduce
+ 2:3 TSEC1 protocol
+ 4:5 TSEC2 protocol
+ 6 PHY1 slave
+ 7 PHY2 slave
+
+ * BCSR 4 *
+ 4 clock enable
+ 5 boot EPROM
+ 6 GETH transactive reset
+ 7 BRD write potect
+
+ * BCSR 5 *
+ 1:3 Leds 1-3
+ 4 UPC1 enable
+ 5 UPC2 enable
+ 6 UPC2 pos
+ 7 RS232 enable
+
+ * BCSR 6 *
+ 0 CFG ver 0
+ 1 CFG ver 1
+ 6 Register config led
+ 7 Power on reset
+
+ * BCSR 7 *
+ 2 board host mode indication
+ 5 enable TSEC1 PHY
+ 6 enable TSEC2 PHY
+
+ * BCSR 8 *
+ 0 UCC GETH1 enable
+ 1 UCC GMII enable
+ 3 UCC TBI enable
+ 5 UCC MII enable
+ 7 Real time clock reset
+
+ * BCSR 9 *
+ 0 UCC2 GETH enable
+ 1 UCC2 GMII enable
+ 3 UCC2 TBI enable
+ 5 UCC2 MII enable
+ 6 Ready only - indicate flash ready after burning
+ 7 Flash write protect
+*/
+
+/*BCSR Utils functions*/
+
+void enable_8568mds_duart(void);
+void enable_8568mds_flash_write(void);
+void disable_8568mds_flash_write(void);
+void enable_8568mds_qe_mdio(void);
+
+#endif /* __BCSR_H_ */
--- /dev/null
+#
+# Copyright 2007 Freescale Semiconductor.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8568mds board
+#
+TEXT_BASE = 0xfff80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8568=1
--- /dev/null
+/*
+ * Copyright 2004-2007 Freescale Semiconductor.
+ * Copyright 2002,2003, Motorola Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+/*
+ * TLB0 and TLB1 Entries
+ *
+ * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
+ * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
+ * these TLB entries are established.
+ *
+ * The TLB entries for DDR are dynamically setup in spd_sdram()
+ * and use TLB1 Entries 8 through 15 as needed according to the
+ * size of DDR memory.
+ *
+ * MAS0: tlbsel, esel, nv
+ * MAS1: valid, iprot, tid, ts, tsize
+ * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
+ */
+#define entry_start \
+ mflr r1 ; \
+ bl 0f ;
+
+#define entry_end \
+0: mflr r0 ; \
+ mtlr r1 ; \
+ blr ;
+
+
+ .section .bootpg, "ax"
+ .globl tlb1_entry
+tlb1_entry:
+ entry_start
+
+ /*
+ * Number of TLB0 and TLB1 entries in the following table
+ */
+ .long (2f-1f)/16
+
+1:
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+ /*
+ * TLB0 4K Non-cacheable, guarded
+ * 0xff700000 4K Initial CCSRBAR mapping
+ *
+ * This ends up at a TLB0 Index==0 entry, and must not collide
+ * with other TLB0 Entries.
+ */
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+#else
+#error("Update the number of table entries in tlb1_entry")
+#endif
+
+ /*
+ * TLB0 16K Cacheable, non-guarded
+ * 0xd001_0000 16K Temporary Global data for initialization
+ *
+ * Use four 4K TLB0 entries. These entries must be cacheable
+ * as they provide the bootstrap memory before the memory
+ * controler and real memory have been configured.
+ *
+ * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+ * and must not collide with other TLB0 entries.
+ */
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ /* TLB 1 Initializations */
+ /*
+ * TLBe 0: 16M Non-cacheable, guarded
+ * 0xff000000 16M FLASH (upper half)
+ * Out of reset this entry is only 4K.
+ */
+ .long TLB1_MAS0(1, 0, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE + 0x1000000),
+ 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE + 0x1000000),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLBe 1: 16M Non-cacheable, guarded
+ * 0xfe000000 16M FLASH (lower half)
+ */
+ .long TLB1_MAS0(1, 1, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLBe 2: 1G Non-cacheable, guarded
+ * 0x80000000 512M PCI1 MEM
+ * 0xa0000000 512M PCIe MEM
+ */
+ .long TLB1_MAS0(1, 2, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLBe 3: 64M Non-cacheable, guarded
+ * 0xe000_0000 1M CCSRBAR
+ * 0xe200_0000 8M PCI1 IO
+ * 0xe280_0000 8M PCIe IO
+ */
+ .long TLB1_MAS0(1, 3, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLBe 4: 64M Cacheable, non-guarded
+ * 0xf000_0000 64M LBC SDRAM
+ */
+ .long TLB1_MAS0(1, 4, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLBe 5: 256K Non-cacheable, guarded
+ * 0xf8000000 32K BCSR
+ * 0xf8008000 32K PIB (CS4)
+ * 0xf8010000 32K PIB (CS5)
+ */
+ .long TLB1_MAS0(1, 5, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+2:
+ entry_end
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ *0) 0x0000_0000 0x7fff_ffff DDR 2G
+ *1) 0x8000_0000 0x9fff_ffff PCI1 MEM 512MB
+ *2) 0xa000_0000 0xbfff_ffff PCIe MEM 512MB
+ *-) 0xe000_0000 0xe00f_ffff CCSR 1M
+ *3) 0xe200_0000 0xe27f_ffff PCI1 I/O 8M
+ *4) 0xe280_0000 0xe2ff_ffff PCIe I/O 8M
+ *5) 0xc000_0000 0xdfff_ffff SRIO 512MB
+ *6.a) 0xf000_0000 0xf3ff_ffff SDRAM 64MB
+ *6.b) 0xf800_0000 0xf800_7fff BCSR 32KB
+ *6.c) 0xf800_8000 0xf800_ffff PIB (CS4) 32KB
+ *6.d) 0xf801_0000 0xf801_7fff PIB (CS5) 32KB
+ *6.e) 0xfe00_0000 0xffff_ffff Flash 32MB
+ *
+ *Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ * The defines below are 1-off of the actual LAWAR0 usage.
+ * So LAWAR3 define uses the LAWAR4 register in the ECM.
+ */
+
+#define LAWBAR0 0
+#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+
+#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR2 ((CFG_PCIE1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
+#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
+
+#define LAWBAR4 ((CFG_PCIE1_IO_PHYS>>12) & 0xfffff)
+#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
+
+#define LAWBAR5 ((CFG_SRIO_MEM_BASE>>12) & 0xfffff)
+#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+/* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */
+#define LAWBAR6 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+ .section .bootpg, "ax"
+ .globl law_entry
+
+law_entry:
+ entry_start
+ .long (4f-3f)/8
+3:
+ .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
+ .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5,LAWBAR6,LAWAR6
+4:
+ entry_end
--- /dev/null
+/*
+ * Copyright 2007 Freescale Semiconductor.
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/immap_fsl_pci.h>
+#include <spd.h>
+#include <i2c.h>
+#include <ioports.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+#include "bcsr.h"
+
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+ /* GETH1 */
+ {4, 10, 1, 0, 2}, /* TxD0 */
+ {4, 9, 1, 0, 2}, /* TxD1 */
+ {4, 8, 1, 0, 2}, /* TxD2 */
+ {4, 7, 1, 0, 2}, /* TxD3 */
+ {4, 23, 1, 0, 2}, /* TxD4 */
+ {4, 22, 1, 0, 2}, /* TxD5 */
+ {4, 21, 1, 0, 2}, /* TxD6 */
+ {4, 20, 1, 0, 2}, /* TxD7 */
+ {4, 15, 2, 0, 2}, /* RxD0 */
+ {4, 14, 2, 0, 2}, /* RxD1 */
+ {4, 13, 2, 0, 2}, /* RxD2 */
+ {4, 12, 2, 0, 2}, /* RxD3 */
+ {4, 29, 2, 0, 2}, /* RxD4 */
+ {4, 28, 2, 0, 2}, /* RxD5 */
+ {4, 27, 2, 0, 2}, /* RxD6 */
+ {4, 26, 2, 0, 2}, /* RxD7 */
+ {4, 11, 1, 0, 2}, /* TX_EN */
+ {4, 24, 1, 0, 2}, /* TX_ER */
+ {4, 16, 2, 0, 2}, /* RX_DV */
+ {4, 30, 2, 0, 2}, /* RX_ER */
+ {4, 17, 2, 0, 2}, /* RX_CLK */
+ {4, 19, 1, 0, 2}, /* GTX_CLK */
+ {1, 31, 2, 0, 3}, /* GTX125 */
+
+ /* GETH2 */
+ {5, 10, 1, 0, 2}, /* TxD0 */
+ {5, 9, 1, 0, 2}, /* TxD1 */
+ {5, 8, 1, 0, 2}, /* TxD2 */
+ {5, 7, 1, 0, 2}, /* TxD3 */
+ {5, 23, 1, 0, 2}, /* TxD4 */
+ {5, 22, 1, 0, 2}, /* TxD5 */
+ {5, 21, 1, 0, 2}, /* TxD6 */
+ {5, 20, 1, 0, 2}, /* TxD7 */
+ {5, 15, 2, 0, 2}, /* RxD0 */
+ {5, 14, 2, 0, 2}, /* RxD1 */
+ {5, 13, 2, 0, 2}, /* RxD2 */
+ {5, 12, 2, 0, 2}, /* RxD3 */
+ {5, 29, 2, 0, 2}, /* RxD4 */
+ {5, 28, 2, 0, 2}, /* RxD5 */
+ {5, 27, 2, 0, 3}, /* RxD6 */
+ {5, 26, 2, 0, 2}, /* RxD7 */
+ {5, 11, 1, 0, 2}, /* TX_EN */
+ {5, 24, 1, 0, 2}, /* TX_ER */
+ {5, 16, 2, 0, 2}, /* RX_DV */
+ {5, 30, 2, 0, 2}, /* RX_ER */
+ {5, 17, 2, 0, 2}, /* RX_CLK */
+ {5, 19, 1, 0, 2}, /* GTX_CLK */
+ {1, 31, 2, 0, 3}, /* GTX125 */
+ {4, 6, 3, 0, 2}, /* MDIO */
+ {4, 5, 1, 0, 2}, /* MDC */
+ {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
+};
+
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+extern long int spd_sdram(void);
+
+void local_bus_init(void);
+void sdram_init(void);
+
+int board_early_init_f (void)
+{
+ /*
+ * Initialize local bus.
+ */
+ local_bus_init ();
+
+ enable_8568mds_duart();
+ enable_8568mds_flash_write();
+#if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS)
+ enable_8568mds_qe_mdio();
+#endif
+
+#ifdef CFG_I2C2_OFFSET
+ /* Enable I2C2_SCL and I2C2_SDA */
+ volatile struct par_io *port_c;
+ port_c = (struct par_io*)(CFG_IMMR + 0xe0140);
+ port_c->cpdir2 |= 0x0f000000;
+ port_c->cppar2 &= ~0x0f000000;
+ port_c->cppar2 |= 0x0a000000;
+#endif
+
+ return 0;
+}
+
+int checkboard (void)
+{
+ printf ("Board: 8568 MDS\n");
+
+ return 0;
+}
+
+long int
+initdram(int board_type)
+{
+ long dram_size = 0;
+
+ puts("Initializing\n");
+
+#if defined(CONFIG_DDR_DLL)
+ {
+ /*
+ * Work around to stabilize DDR DLL MSYNC_IN.
+ * Errata DDR9 seems to have been fixed.
+ * This is now the workaround for Errata DDR11:
+ * Override DLL = 1, Course Adj = 1, Tap Select = 0
+ */
+
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+
+ gur->ddrdllcr = 0x81000000;
+ asm("sync;isync;msync");
+ udelay(200);
+ }
+#endif
+ dram_size = spd_sdram();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /*
+ * Initialize and enable DDR ECC.
+ */
+ ddr_enable_ecc(dram_size);
+#endif
+ /*
+ * SDRAM Initialization
+ */
+ sdram_init();
+
+ puts(" DDR: ");
+ return dram_size;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+
+ uint clkdiv;
+ uint lbc_hz;
+ sys_info_t sysinfo;
+
+ get_sys_info(&sysinfo);
+ clkdiv = (lbc->lcrr & 0x0f) * 2;
+ lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+ gur->lbiuiplldcr1 = 0x00078080;
+ if (clkdiv == 16) {
+ gur->lbiuiplldcr0 = 0x7c0f1bf0;
+ } else if (clkdiv == 8) {
+ gur->lbiuiplldcr0 = 0x6c0f1bf0;
+ } else if (clkdiv == 4) {
+ gur->lbiuiplldcr0 = 0x5c0f1bf0;
+ }
+
+ lbc->lcrr |= 0x00030000;
+
+ asm("sync;isync;msync");
+}
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+void
+sdram_init(void)
+{
+#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
+
+ uint idx;
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+ uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+ uint lsdmr_common;
+
+ puts(" SDRAM: ");
+
+ print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+
+ /*
+ * Setup SDRAM Base and Option Registers
+ */
+ lbc->or2 = CFG_OR2_PRELIM;
+ asm("msync");
+
+ lbc->br2 = CFG_BR2_PRELIM;
+ asm("msync");
+
+ lbc->lbcr = CFG_LBC_LBCR;
+ asm("msync");
+
+
+ lbc->lsrt = CFG_LBC_LSRT;
+ lbc->mrtpr = CFG_LBC_MRTPR;
+ asm("msync");
+
+ /*
+ * MPC8568 uses "new" 15-16 style addressing.
+ */
+ lsdmr_common = CFG_LBC_LSDMR_COMMON;
+ lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
+
+ /*
+ * Issue PRECHARGE ALL command.
+ */
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ /*
+ * Issue 8 AUTO REFRESH commands.
+ */
+ for (idx = 0; idx < 8; idx++) {
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+ }
+
+ /*
+ * Issue 8 MODE-set command.
+ */
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ /*
+ * Issue NORMAL OP command.
+ */
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(200); /* Overkill. Must wait > 200 bus cycles */
+
+#endif /* enable SDRAM init */
+}
+
+#if defined(CFG_DRAM_TEST)
+int
+testdram(void)
+{
+ uint *pstart = (uint *) CFG_MEMTEST_START;
+ uint *pend = (uint *) CFG_MEMTEST_END;
+ uint *p;
+
+ printf("Testing DRAM from 0x%08x to 0x%08x\n",
+ CFG_MEMTEST_START,
+ CFG_MEMTEST_END);
+
+ printf("DRAM test phase 1:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf ("DRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("DRAM test phase 2:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf ("DRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("DRAM test passed.\n");
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_PCI)
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc8568mds_config_table[] = {
+ {
+ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+ pci_cfgfunc_config_device,
+ {PCI_ENET0_IOADDR,
+ PCI_ENET0_MEMADDR,
+ PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
+ },
+ {}
+};
+#endif
+
+static struct pci_controller pci1_hose = {
+#ifndef CONFIG_PCI_PNP
+ config_table: pci_mpc8568mds_config_table,
+#endif
+};
+#endif /* CONFIG_PCI */
+
+#ifdef CONFIG_PCIE1
+static struct pci_controller pcie1_hose;
+#endif /* CONFIG_PCIE1 */
+
+int first_free_busno = 0;
+
+/*
+ * pib_init() -- Initialize the PCA9555 IO expander on the PIB board
+ */
+void
+pib_init(void)
+{
+ u8 val8, orig_i2c_bus;
+ /*
+ * Assign PIB PMC2/3 to PCI bus
+ */
+
+ /*switch temporarily to I2C bus #2 */
+ orig_i2c_bus = i2c_get_bus_num();
+ i2c_set_bus_num(1);
+
+ val8 = 0x00;
+ i2c_write(0x23, 0x6, 1, &val8, 1);
+ i2c_write(0x23, 0x7, 1, &val8, 1);
+ val8 = 0xff;
+ i2c_write(0x23, 0x2, 1, &val8, 1);
+ i2c_write(0x23, 0x3, 1, &val8, 1);
+
+ val8 = 0x00;
+ i2c_write(0x26, 0x6, 1, &val8, 1);
+ val8 = 0x34;
+ i2c_write(0x26, 0x7, 1, &val8, 1);
+ val8 = 0xf9;
+ i2c_write(0x26, 0x2, 1, &val8, 1);
+ val8 = 0xff;
+ i2c_write(0x26, 0x3, 1, &val8, 1);
+
+ val8 = 0x00;
+ i2c_write(0x27, 0x6, 1, &val8, 1);
+ i2c_write(0x27, 0x7, 1, &val8, 1);
+ val8 = 0xff;
+ i2c_write(0x27, 0x2, 1, &val8, 1);
+ val8 = 0xef;
+ i2c_write(0x27, 0x3, 1, &val8, 1);
+
+ asm("eieio");
+}
+
+#ifdef CONFIG_PCI
+void
+pci_init_board(void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+ uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
+
+#ifdef CONFIG_PCI1
+{
+ pib_init();
+
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
+ extern void fsl_pci_init(struct pci_controller *hose);
+ struct pci_controller *hose = &pci1_hose;
+
+ uint pci_32 = 1; /* PORDEVSR[15] */
+ uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
+ uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
+
+ uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);
+
+ uint pci_speed = 66666000;
+
+ if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
+ printf (" PCI: %d bit, %s MHz, %s, %s, %s\n",
+ (pci_32) ? 32 : 64,
+ (pci_speed == 33333000) ? "33" :
+ (pci_speed == 66666000) ? "66" : "unknown",
+ pci_clk_sel ? "sync" : "async",
+ pci_agent ? "agent" : "host",
+ pci_arb ? "arbiter" : "external-arbiter"
+ );
+
+ /* inbound */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI_MEMORY_BUS,
+ CFG_PCI_MEMORY_PHYS,
+ CFG_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ /* outbound memory */
+ pci_set_region(hose->regions + 1,
+ CFG_PCI1_MEM_BASE,
+ CFG_PCI1_MEM_PHYS,
+ CFG_PCI1_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(hose->regions + 2,
+ CFG_PCI1_IO_BASE,
+ CFG_PCI1_IO_PHYS,
+ CFG_PCI1_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 3;
+
+ hose->first_busno = first_free_busno;
+ pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+ fsl_pci_init(hose);
+ first_free_busno = hose->last_busno+1;
+ printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
+ } else {
+ printf (" PCI: disabled\n");
+ }
+}
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
+#endif
+
+#ifdef CONFIG_PCIE1
+{
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
+ extern void fsl_pci_init(struct pci_controller *hose);
+ struct pci_controller *hose = &pcie1_hose;
+ int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
+
+ int pcie_configured = io_sel >= 1;
+
+ if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
+ printf ("\n PCIE connected to slot as %s (base address %x)",
+ pcie_ep ? "End Point" : "Root Complex",
+ (uint)pci);
+
+ if (pci->pme_msg_det) {
+ pci->pme_msg_det = 0xffffffff;
+ debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
+ }
+ printf ("\n");
+
+ /* inbound */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI_MEMORY_BUS,
+ CFG_PCI_MEMORY_PHYS,
+ CFG_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ /* outbound memory */
+ pci_set_region(hose->regions + 1,
+ CFG_PCIE1_MEM_BASE,
+ CFG_PCIE1_MEM_PHYS,
+ CFG_PCIE1_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(hose->regions + 2,
+ CFG_PCIE1_IO_BASE,
+ CFG_PCIE1_IO_PHYS,
+ CFG_PCIE1_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 3;
+
+ hose->first_busno=first_free_busno;
+ pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+ fsl_pci_init(hose);
+ printf ("PCIE on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
+
+ first_free_busno=hose->last_busno+1;
+
+ } else {
+ printf (" PCIE: disabled\n");
+ }
+}
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+#endif
+}
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+ int node, tmp[2];
+ const char *path;
+
+ ft_cpu_setup(blob, bd);
+
+ node = fdt_path_offset(blob, "/aliases");
+ tmp[0] = 0;
+ if (node >= 0) {
+#ifdef CONFIG_PCI1
+ path = fdt_getprop(blob, node, "pci0", NULL);
+ if (path) {
+ tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+#ifdef CONFIG_PCIE1
+ path = fdt_getprop(blob, node, "pci1", NULL);
+ if (path) {
+ tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+ }
+}
+#endif
--- /dev/null
+/*
+ * Copyright 2004-2007 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+
+SECTIONS
+{
+ /* ELIOR - From RAM: From FLASH: 0xFFFFFFFC*/
+ .resetvec 0xFFFFFFFC:
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ /*(ELIOR - From RAM: From FLASH: 0xFFFFF000*/
+ .bootpg 0xFFFFF000:
+ {
+ cpu/mpc85xx/start.o (.bootpg)
+ board/freescale/mpc8568mds/init.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc85xx/start.o (.text)
+ board/freescale/mpc8568mds/init.o (.text)
+ cpu/mpc85xx/traps.o (.text)
+ cpu/mpc85xx/interrupts.o (.text)
+ cpu/mpc85xx/cpu_init.o (.text)
+ cpu/mpc85xx/cpu.o (.text)
+ cpu/mpc85xx/speed.o (.text)
+ cpu/mpc85xx/pci.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
cpu/ppc4xx/start.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
cpu/ppc4xx/4xx_enet.o (.text)
*/
void ft_blob_update(void *blob, bd_t *bd)
{
- int ret, nodeoffset = 0;
- ulong memory_data[2] = {0};
+ int ret;
- memory_data[0] = cpu_to_be32(bd->bi_memstart);
- memory_data[1] = cpu_to_be32(bd->bi_memsize);
+ ret = fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
- nodeoffset = fdt_find_node_by_path (blob, "/memory");
- if (nodeoffset >= 0) {
- ret = fdt_setprop(blob, nodeoffset, "reg", memory_data,
- sizeof(memory_data));
- if (ret < 0)
+ if (ret < 0) {
printf("ft_blob_update): cannot set /memory/reg "
"property err:%s\n", fdt_strerror(ret));
}
- else {
- /* memory node is required in dts */
- printf("ft_blob_update(): cannot find /memory node "
- "err:%s\n", fdt_strerror(nodeoffset));
- }
}
void ft_board_setup(void *blob, bd_t *bd)
cpu="arm_intcm"
variant="unknown core module"
-if [ "$1" == "" ]
+if [ "$1" = "" ]
then
echo "$0:: No parameters - using arm_intcm"
else
esac
fi
-if [ "$cpu" == "arm_intcm" ]
+if [ "$cpu" = "arm_intcm" ]
then
echo "/* Core module undefined/not ported */" >> tmp.fil
echo "#define CONFIG_ARM_INTCM 1" >> tmp.fil
cpu="arm_intcm"
variant="unknown core module"
-if [ "$1" == "" ]
+if [ "$1" = "" ]
then
echo "$0:: No parameters - using arm_intcm"
else
fi
-if [ "$cpu" == "arm_intcm" ]
+if [ "$cpu" = "arm_intcm" ]
then
echo "/* Core module undefined/not ported */" >> tmp.fil
echo "#define CONFIG_ARM_INTCM 1" >> tmp.fil
--- /dev/null
+#
+# (C) Copyright 2002-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS = $(BOARD).o
+SOBJS = init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+# Korat (PPC440EPx) board
+#
+
+TEXT_BASE = 0xFFFA0000
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
--- /dev/null
+/*
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <asm-ppc/mmu.h>
+#include <config.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
+ tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
+
+ /*
+ * TLB entries for SDRAM are not needed on this platform. They are
+ * generated dynamically in the SPD DDR2 detection routine.
+ */
+
+#ifdef CFG_INIT_RAM_DCACHE
+ /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+ tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+#endif
+
+ /* TLB-entry for PCI Memory */
+ tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
+
+ /* TLB-entry for EBC */
+ tlbentry( CFG_CPLD_BASE, SZ_1K, CFG_CPLD_BASE, 1, AC_R|AC_W|SA_G|SA_I )
+
+ /* TLB-entry for Internal Registers & OCM */
+ /* I wonder why this must be executable -- lrj@acm.org 2007-10-08 */
+ tlbentry( 0xE0000000, SZ_16M, 0xE0000000, 0, AC_R|AC_W|AC_X|SA_I )
+
+ /*TLB-entry PCI registers*/
+ tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|SA_G|SA_I )
+
+ /* TLB-entry for peripherals */
+ tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|SA_G|SA_I)
+
+ /* TLB-entry PCI IO Space - from sr@denx.de */
+ tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|SA_G|SA_I)
+
+ tlbtab_end
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Larry Johnson, lrj@acm.org
+ *
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2006
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm-ppc/io.h>
+#include <i2c.h>
+#include <ppc440.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+ulong flash_get_size(ulong base, int banknum);
+
+int board_early_init_f(void)
+{
+ u32 sdr0_pfc1, sdr0_pfc2;
+ u32 gpio0_ir;
+ u32 reg;
+ int eth;
+
+ mtdcr(ebccfga, xbcfg);
+ mtdcr(ebccfgd, 0xb8400000);
+
+ /*--------------------------------------------------------------------
+ * Setup the GPIO pins
+ *
+ * Korat GPIO usage:
+ *
+ * Init.
+ * Pin Source I/O value Function
+ * ------ ------ --- ----- ---------------------------------
+ * GPIO00 Alt1 I/O x PerAddr07
+ * GPIO01 Alt1 I/O x PerAddr06
+ * GPIO02 Alt1 I/O x PerAddr05
+ * GPIO03 GPIO x x GPIO03 to expansion bus connector
+ * GPIO04 GPIO x x GPIO04 to expansion bus connector
+ * GPIO05 GPIO x x GPIO05 to expansion bus connector
+ * GPIO06 Alt1 O x PerCS1 (2nd NOR flash)
+ * GPIO07 Alt1 O x PerCS2 (CPLD)
+ * GPIO08 Alt1 O x PerCS3 to expansion bus connector
+ * GPIO09 Alt1 O x PerCS4 to expansion bus connector
+ * GPIO10 Alt1 O x PerCS5 to expansion bus connector
+ * GPIO11 Alt1 I x PerErr
+ * GPIO12 GPIO O 0 ATMega !Reset
+ * GPIO13 GPIO O 1 SPI Atmega !SS
+ * GPIO14 GPIO O 1 Write protect EEPROM #1 (0xA8)
+ * GPIO15 GPIO O 0 CPU Run LED !On
+ * GPIO16 Alt1 O x GMC1TxD0
+ * GPIO17 Alt1 O x GMC1TxD1
+ * GPIO18 Alt1 O x GMC1TxD2
+ * GPIO19 Alt1 O x GMC1TxD3
+ * GPIO20 Alt1 O x RejectPkt0
+ * GPIO21 Alt1 O x RejectPkt1
+ * GPIO22 GPIO I x PGOOD_DDR
+ * GPIO23 Alt1 O x SCPD0
+ * GPIO24 Alt1 O x GMC0TxD2
+ * GPIO25 Alt1 O x GMC0TxD3
+ * GPIO26 GPIO? I/O x IIC0SDA (selected in SDR0_PFC4)
+ * GPIO27 GPIO O 0 PHY #0 1000BASE-X
+ * GPIO28 GPIO O 0 PHY #1 1000BASE-X
+ * GPIO29 GPIO I x Test jumper !Present
+ * GPIO30 GPIO I x SFP module #0 !Present
+ * GPIO31 GPIO I x SFP module #1 !Present
+ *
+ * GPIO32 GPIO O 1 SFP module #0 Tx !Enable
+ * GPIO33 GPIO O 1 SFP module #1 Tx !Enable
+ * GPIO34 Alt2 I x !UART1_CTS
+ * GPIO35 Alt2 O x !UART1_RTS
+ * GPIO36 Alt1 I x !UART0_CTS
+ * GPIO37 Alt1 O x !UART0_RTS
+ * GPIO38 Alt2 O x UART1_Tx
+ * GPIO39 Alt2 I x UART1_Rx
+ * GPIO40 Alt1 I x IRQ0 (Ethernet 0)
+ * GPIO41 Alt1 I x IRQ1 (Ethernet 1)
+ * GPIO42 Alt1 I x IRQ2 (PCI interrupt)
+ * GPIO43 Alt1 I x IRQ3 (System Alert from CPLD)
+ * GPIO44 xxxx x x (grounded through pulldown)
+ * GPIO45 GPIO O 0 PHY #0 Enable
+ * GPIO46 GPIO O 0 PHY #1 Enable
+ * GPIO47 GPIO I x Reset switch !Pressed
+ * GPIO48 GPIO I x Shutdown switch !Pressed
+ * GPIO49 xxxx x x (reserved for trace port)
+ * . . . . .
+ * . . . . .
+ * . . . . .
+ * GPIO63 xxxx x x (reserved for trace port)
+ *-------------------------------------------------------------------*/
+
+ out_be32((u32 *) GPIO0_OR, 0x00060000);
+ out_be32((u32 *) GPIO1_OR, 0xC0000000);
+
+ out_be32((u32 *) GPIO0_OSRL, 0x54055400);
+ out_be32((u32 *) GPIO0_OSRH, 0x55015000);
+ out_be32((u32 *) GPIO1_OSRL, 0x02180000);
+ out_be32((u32 *) GPIO1_OSRH, 0x00000000);
+
+ out_be32((u32 *) GPIO0_TSRL, 0x54055500);
+ out_be32((u32 *) GPIO0_TSRH, 0x00015000);
+ out_be32((u32 *) GPIO1_TSRL, 0x00000000);
+ out_be32((u32 *) GPIO1_TSRH, 0x00000000);
+
+ out_be32((u32 *) GPIO0_TCR, 0x000FF0D8);
+ out_be32((u32 *) GPIO1_TCR, 0xD6060000);
+
+ out_be32((u32 *) GPIO0_ISR1L, 0x54000100);
+ out_be32((u32 *) GPIO0_ISR1H, 0x00500000);
+ out_be32((u32 *) GPIO1_ISR1L, 0x00405500);
+ out_be32((u32 *) GPIO1_ISR1H, 0x00000000);
+
+ out_be32((u32 *) GPIO0_ISR2L, 0x00000000);
+ out_be32((u32 *) GPIO0_ISR2H, 0x00000000);
+ out_be32((u32 *) GPIO1_ISR2L, 0x04010000);
+ out_be32((u32 *) GPIO1_ISR2H, 0x00000000);
+
+ out_be32((u32 *) GPIO0_ISR3L, 0x00000000);
+ out_be32((u32 *) GPIO0_ISR3H, 0x00000000);
+ out_be32((u32 *) GPIO1_ISR3L, 0x00000000);
+ out_be32((u32 *) GPIO1_ISR3H, 0x00000000);
+
+ /*--------------------------------------------------------------------
+ * Setup the interrupt controller polarities, triggers, etc.
+ *-------------------------------------------------------------------*/
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+ mtdcr(uic0er, 0x00000000); /* disable all */
+ mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
+ mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
+ mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
+ mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+ mtdcr(uic1er, 0x00000000); /* disable all */
+ mtdcr(uic1cr, 0x00000000); /* all non-critical */
+ mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
+ mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
+ mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+
+ mtdcr(uic2sr, 0xffffffff); /* clear all */
+ mtdcr(uic2er, 0x00000000); /* disable all */
+ mtdcr(uic2cr, 0x00000000); /* all non-critical */
+ mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
+ mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
+ mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(uic2sr, 0xffffffff); /* clear all */
+
+ /* take sim card reader and CF controller out of reset */
+ out_8((u8 *) CFG_CPLD_BASE + 0x04, 0x80);
+
+ /* Configure the two Ethernet PHYs. For each PHY, configure for fiber
+ * if the SFP module is present, and for copper if it is not present.
+ */
+ gpio0_ir = in_be32((u32 *) GPIO0_IR);
+ for (eth = 0; eth < 2; ++eth) {
+ if (gpio0_ir & (0x00000001 << (1 - eth))) {
+ /* SFP module not present: configure PHY for copper. */
+ /* Set PHY to autonegotate 10 MB, 100MB, or 1 GB */
+ out_8((u8 *) CFG_CPLD_BASE + 0x06,
+ in_8((u8 *) CFG_CPLD_BASE + 0x06) |
+ 0x06 << (4 * eth));
+ } else {
+ /* SFP module present: configure PHY for fiber and
+ enable output */
+ out_be32((u32 *) GPIO0_OR, in_be32((u32 *) GPIO0_OR) |
+ (0x00000001 << (4 - eth)));
+ out_be32((u32 *) GPIO1_OR, in_be32((u32 *) GPIO1_OR) &
+ ~(0x00000001 << (31 - eth)));
+ }
+ }
+ /* enable Ethernet: set GPIO45 and GPIO46 to 1 */
+ out_be32((u32 *) GPIO1_OR, in_be32((u32 *) GPIO1_OR) | 0x00060000);
+
+ /* select Ethernet pins */
+ mfsdr(SDR0_PFC1, sdr0_pfc1);
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
+ SDR0_PFC1_SELECT_CONFIG_4;
+ mfsdr(SDR0_PFC2, sdr0_pfc2);
+ sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
+ SDR0_PFC2_SELECT_CONFIG_4;
+ mtsdr(SDR0_PFC2, sdr0_pfc2);
+ mtsdr(SDR0_PFC1, sdr0_pfc1);
+
+ /* PCI arbiter enabled */
+ mfsdr(sdr_pci0, reg);
+ mtsdr(sdr_pci0, 0x80000000 | reg);
+
+ return 0;
+}
+
+static int man_data_read(unsigned int addr)
+{
+ /*
+ * Read an octet of data from address "addr" in the manufacturer's
+ * information serial EEPROM, or -1 on error.
+ */
+ u8 data[2];
+
+ if (0 != i2c_probe(MAN_DATA_EEPROM_ADDR) ||
+ 0 != i2c_read(MAN_DATA_EEPROM_ADDR, addr, 1, data, 1)) {
+ debug("man_data_read(0x%02X) failed\n", addr);
+ return -1;
+ }
+ debug("man_info_read(0x%02X) returned 0x%02X\n", addr, data[0]);
+ return data[0];
+}
+
+static unsigned int man_data_field_addr(unsigned int const field)
+{
+ /*
+ * The manufacturer's information serial EEPROM contains a sequence of
+ * zero-delimited fields. Return the starting address of field "field",
+ * or 0 on error.
+ */
+ unsigned addr, i;
+
+ if (0 == field || 'A' != man_data_read(0) || '\0' != man_data_read(1))
+ /* Only format "A" is currently supported */
+ return 0;
+
+ for (addr = 2, i = 1; i < field && addr < 256; ++addr) {
+ if ('\0' == man_data_read(addr))
+ ++i;
+ }
+ return (addr < 256) ? addr : 0;
+}
+
+static char *man_data_read_field(char s[], unsigned const field,
+ unsigned const length)
+{
+ /*
+ * Place the null-terminated contents of field "field" of length
+ * "length" from the manufacturer's information serial EEPROM into
+ * string "s[length + 1]" and return a pointer to s, or return 0 on
+ * error. In either case the original contents of s[] is not preserved.
+ */
+ unsigned addr, i;
+
+ addr = man_data_field_addr(field);
+ if (0 == addr || addr + length >= 255)
+ return 0;
+
+ for (i = 0; i < length; ++i) {
+ int const c = man_data_read(addr++);
+
+ if (c <= 0)
+ return 0;
+
+ s[i] = (char)c;
+ }
+ if (0 != man_data_read(addr))
+ return 0;
+
+ s[i] = '\0';
+ return s;
+}
+
+static void set_serial_number(void)
+{
+ /*
+ * If the environmental variable "serial#" is not set, try to set it
+ * from the manufacturer's information serial EEPROM.
+ */
+ char s[MAN_SERIAL_NO_LENGTH + 1];
+
+ if (0 == getenv("serial#") &&
+ 0 != man_data_read_field(s, MAN_SERIAL_NO_FIELD,
+ MAN_SERIAL_NO_LENGTH))
+ setenv("serial#", s);
+}
+
+static void set_mac_addresses(void)
+{
+ /*
+ * If the environmental variables "ethaddr" and/or "eth1addr" are not
+ * set, try to set them from the manufacturer's information serial
+ * EEPROM.
+ */
+ char s[MAN_MAC_ADDR_LENGTH + 1];
+
+ if (0 != getenv("ethaddr") && 0 != getenv("eth1addr"))
+ return;
+
+ if (0 == man_data_read_field(s, MAN_MAC_ADDR_FIELD,
+ MAN_MAC_ADDR_LENGTH))
+ return;
+
+ if (0 == getenv("ethaddr"))
+ setenv("ethaddr", s);
+
+ if (0 == getenv("eth1addr")) {
+ ++s[MAN_MAC_ADDR_LENGTH - 1];
+ setenv("eth1addr", s);
+ }
+}
+
+/*---------------------------------------------------------------------------+
+ | misc_init_r.
+ +---------------------------------------------------------------------------*/
+int misc_init_r(void)
+{
+ uint pbcr;
+ int size_val = 0;
+ u32 reg;
+ unsigned long usb2d0cr = 0;
+ unsigned long usb2phy0cr, usb2h0cr = 0;
+ unsigned long sdr0_pfc1;
+ char *act = getenv("usbact");
+
+ /*
+ * FLASH stuff...
+ */
+
+ /* Re-do sizing to get full correct info */
+
+ /* adjust flash start and offset */
+ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+ gd->bd->bi_flashoffset = 0;
+
+ mtdcr(ebccfga, pb0cr);
+ pbcr = mfdcr(ebccfgd);
+ switch (gd->bd->bi_flashsize) {
+ case 1 << 20:
+ size_val = 0;
+ break;
+ case 2 << 20:
+ size_val = 1;
+ break;
+ case 4 << 20:
+ size_val = 2;
+ break;
+ case 8 << 20:
+ size_val = 3;
+ break;
+ case 16 << 20:
+ size_val = 4;
+ break;
+ case 32 << 20:
+ size_val = 5;
+ break;
+ case 64 << 20:
+ size_val = 6;
+ break;
+ case 128 << 20:
+ size_val = 7;
+ break;
+ }
+ pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+ mtdcr(ebccfga, pb0cr);
+ mtdcr(ebccfgd, pbcr);
+
+ /*
+ * Re-check to get correct base address
+ */
+ flash_get_size(gd->bd->bi_flashstart, 0);
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET, -CFG_MONITOR_LEN, 0xffffffff,
+ &flash_info[0]);
+
+ /* Env protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR_REDUND,
+ CFG_ENV_ADDR_REDUND + 2 * CFG_ENV_SECT_SIZE - 1,
+ &flash_info[0]);
+
+ /*
+ * USB suff...
+ */
+ if (act == NULL || strcmp(act, "hostdev") == 0) {
+ /* SDR Setting */
+ mfsdr(SDR0_PFC1, sdr0_pfc1);
+ mfsdr(SDR0_USB2D0CR, usb2d0cr);
+ mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mfsdr(SDR0_USB2H0CR, usb2h0cr);
+
+ usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0 */
+ usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1 */
+ usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0 */
+ usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1 */
+ usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1 */
+
+ /* An 8-bit/60MHz interface is the only possible alternative
+ when connecting the Device to the PHY */
+ usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK;
+ usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1 */
+
+ /* To enable the USB 2.0 Device function through the UTMI interface */
+ usb2d0cr = usb2d0cr & ~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
+ usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1 */
+
+ sdr0_pfc1 = sdr0_pfc1 & ~SDR0_PFC1_UES_MASK;
+ sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0 */
+
+ mtsdr(SDR0_PFC1, sdr0_pfc1);
+ mtsdr(SDR0_USB2D0CR, usb2d0cr);
+ mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mtsdr(SDR0_USB2H0CR, usb2h0cr);
+
+ /*clear resets */
+ udelay(1000);
+ mtsdr(SDR0_SRST1, 0x00000000);
+ udelay(1000);
+ mtsdr(SDR0_SRST0, 0x00000000);
+
+ printf("USB: Host(int phy) Device(ext phy)\n");
+
+ } else if (strcmp(act, "dev") == 0) {
+ /*-------------------PATCH-------------------------------*/
+ mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+
+ usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0 */
+ usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0 */
+ usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1 */
+ usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1 */
+ mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+
+ udelay(1000);
+ mtsdr(SDR0_SRST1, 0x672c6000);
+
+ udelay(1000);
+ mtsdr(SDR0_SRST0, 0x00000080);
+
+ udelay(1000);
+ mtsdr(SDR0_SRST1, 0x60206000);
+
+ *(unsigned int *)(0xe0000350) = 0x00000001;
+
+ udelay(1000);
+ mtsdr(SDR0_SRST1, 0x60306000);
+ /*-------------------PATCH-------------------------------*/
+
+ /* SDR Setting */
+ mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mfsdr(SDR0_USB2H0CR, usb2h0cr);
+ mfsdr(SDR0_USB2D0CR, usb2d0cr);
+ mfsdr(SDR0_PFC1, sdr0_pfc1);
+
+ usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0 */
+ usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; /*0 */
+ usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1 */
+ usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; /*0 */
+ usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; /*0 */
+
+ usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK;
+ usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; /*0 */
+
+ usb2d0cr = usb2d0cr & ~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
+ usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION; /*0 */
+
+ sdr0_pfc1 = sdr0_pfc1 & ~SDR0_PFC1_UES_MASK;
+ sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; /*1 */
+
+ mtsdr(SDR0_USB2H0CR, usb2h0cr);
+ mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mtsdr(SDR0_USB2D0CR, usb2d0cr);
+ mtsdr(SDR0_PFC1, sdr0_pfc1);
+
+ /*clear resets */
+ udelay(1000);
+ mtsdr(SDR0_SRST1, 0x00000000);
+ udelay(1000);
+ mtsdr(SDR0_SRST0, 0x00000000);
+
+ printf("USB: Device(int phy)\n");
+ }
+
+ mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */
+ reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
+ mtsdr(SDR0_SRST1, reg);
+
+ /*
+ * Clear PLB4A0_ACR[WRP]
+ * This fix will make the MAL burst disabling patch for the Linux
+ * EMAC driver obsolete.
+ */
+ reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
+ mtdcr(plb4_acr, reg);
+
+ set_serial_number();
+ set_mac_addresses();
+ return 0;
+}
+
+int checkboard(void)
+{
+ char const *const s = getenv("serial#");
+ u8 const rev = in_8((u8 *) CFG_CPLD_BASE + 0);
+ u32 const gpio0_or = in_be32((u32 *) GPIO0_OR);
+
+ printf("Board: Korat, Rev. %X", rev);
+ if (s != NULL)
+ printf(", serial# %s", s);
+
+ printf(", Ethernet PHY 0: ");
+ if (gpio0_or & 0x00000010)
+ printf("fiber");
+ else
+ printf("copper");
+
+ printf(", PHY 1: ");
+ if (gpio0_or & 0x00000008)
+ printf("fiber");
+ else
+ printf("copper");
+
+ printf(".\n");
+ return (0);
+}
+
+#if defined(CFG_DRAM_TEST)
+int testdram(void)
+{
+ unsigned long *mem = (unsigned long *)0;
+ const unsigned long kend = (1024 / sizeof(unsigned long));
+ unsigned long k, n;
+
+ mtmsr(0);
+
+ /* TODO: find correct size of SDRAM */
+ for (k = 0; k < CFG_MBYTES_SDRAM;
+ ++k, mem += (1024 / sizeof(unsigned long))) {
+ if ((k & 1023) == 0)
+ printf("%3d MB\r", k / 1024);
+
+ memset(mem, 0xaaaaaaaa, 1024);
+ for (n = 0; n < kend; ++n) {
+ if (mem[n] != 0xaaaaaaaa) {
+ printf("SDRAM test fails at: %08x\n",
+ (uint) & mem[n]);
+ return 1;
+ }
+ }
+
+ memset(mem, 0x55555555, 1024);
+ for (n = 0; n < kend; ++n) {
+ if (mem[n] != 0x55555555) {
+ printf("SDRAM test fails at: %08x\n",
+ (uint) & mem[n]);
+ return 1;
+ }
+ }
+ }
+ printf("SDRAM test passes\n");
+ return 0;
+}
+#endif /* defined(CFG_DRAM_TEST) */
+
+/*************************************************************************
+ * pci_pre_init
+ *
+ * This routine is called just prior to registering the hose and gives
+ * the board the opportunity to check things. Returning a value of zero
+ * indicates that things are bad & PCI initialization should be aborted.
+ *
+ * Different boards may wish to customize the pci controller structure
+ * (add regions, override default access routines, etc) or perform
+ * certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int pci_pre_init(struct pci_controller *hose)
+{
+ unsigned long addr;
+
+ /*-------------------------------------------------------------------------+
+ | Set priority for all PLB3 devices to 0.
+ | Set PLB3 arbiter to fair mode.
+ +-------------------------------------------------------------------------*/
+ mfsdr(sdr_amp1, addr);
+ mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
+ addr = mfdcr(plb3_acr);
+ mtdcr(plb3_acr, addr | 0x80000000);
+
+ /*-------------------------------------------------------------------------+
+ | Set priority for all PLB4 devices to 0.
+ +-------------------------------------------------------------------------*/
+ mfsdr(sdr_amp0, addr);
+ mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
+ addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
+ mtdcr(plb4_acr, addr);
+
+ /*-------------------------------------------------------------------------+
+ | Set Nebula PLB4 arbiter to fair mode.
+ +-------------------------------------------------------------------------*/
+ /* Segment0 */
+ addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
+ addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
+ addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
+ addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
+ mtdcr(plb0_acr, addr);
+
+ /* Segment1 */
+ addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
+ addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
+ addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
+ addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
+ mtdcr(plb1_acr, addr);
+
+ return 1;
+}
+#endif /* defined(CONFIG_PCI) */
+
+/*************************************************************************
+ * pci_target_init
+ *
+ * The bootstrap configuration provides default settings for the pci
+ * inbound map (PIM). But the bootstrap config choices are limited and
+ * may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller *hose)
+{
+ /*--------------------------------------------------------------------------+
+ * Set up Direct MMIO registers
+ *--------------------------------------------------------------------------*/
+ /*--------------------------------------------------------------------------+
+ | PowerPC440EPX PCI Master configuration.
+ | Map one 1Gig range of PLB/processor addresses to PCI memory space.
+ | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
+ | Use byte reversed out routines to handle endianess.
+ | Make this region non-prefetchable.
+ +--------------------------------------------------------------------------*/
+ out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
+ out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
+ out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
+ out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
+
+ out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
+ out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
+ out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
+ out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
+
+ out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
+ out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
+ out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
+ out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
+
+ /*--------------------------------------------------------------------------+
+ * Set up Configuration registers
+ *--------------------------------------------------------------------------*/
+
+ /* Program the board's subsystem id/vendor id */
+ pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
+ CFG_PCI_SUBSYS_VENDORID);
+ pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
+
+ /* Configure command register as bus master */
+ pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
+
+ /* 240nS PCI clock */
+ pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
+
+ /* No error reporting */
+ pci_write_config_word(0, PCI_ERREN, 0);
+
+ pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
+
+ /*--------------------------------------------------------------------------+
+ * Set up Configuration registers for on-board NEC uPD720101 USB controller
+ *--------------------------------------------------------------------------*/
+ pci_write_config_dword(PCI_BDF(0x0, 0xC, 0x0), 0xE4, 0x00000020);
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+/*************************************************************************
+ * pci_master_init
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
+void pci_master_init(struct pci_controller *hose)
+{
+ unsigned short temp_short;
+
+ /*--------------------------------------------------------------------------+
+ | Write the PowerPC440 EP PCI Configuration regs.
+ | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
+ | Enable PowerPC440 EP to act as a PCI memory target (PTM).
+ +--------------------------------------------------------------------------*/
+ pci_read_config_word(0, PCI_COMMAND, &temp_short);
+ pci_write_config_word(0, PCI_COMMAND,
+ temp_short | PCI_COMMAND_MASTER |
+ PCI_COMMAND_MEMORY);
+}
+#endif
+
+/*************************************************************************
+ * is_pci_host
+ *
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
+ *
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
+ *
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+ /* Korat is always configured as host. */
+ return (1);
+}
+#endif
+
+#if defined(CONFIG_POST)
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+ return 0; /* No hotkeys supported */
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/ppc4xx/start.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+
+ ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
+
+ _end = . ;
+ PROVIDE (end = .);
+}
void board_add_ram_info(int use_default)
{
- PPC440_SYS_INFO board_cfg;
+ PPC4xx_SYS_INFO board_cfg;
u32 val;
if (is_ecc_enabled())
#define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
#define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
#define DDR0_26_TREF_MASK 0x00003FFF
-#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
-#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
+#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0)
+#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF)
#define DDR0_27 0x1B
#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
cpu/ppc4xx/4xx_enet.o (.text)
+++ /dev/null
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).a
-
-COBJS := $(BOARD).o
-SOBJS := init.o
-#SOBJS :=
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
-
-clean:
- rm -f $(OBJS) $(SOBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-# Copyright 2004 Freescale Semiconductor.
-# Modified by Xianghua Xiao, X.Xiao@motorola.com
-# (C) Copyright 2002,Motorola Inc.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# mpc8540ads board
-# default CCARBAR is at 0xff700000
-# assume U-Boot is less than 0.5MB
-#
-TEXT_BASE = 0xfff80000
-
-PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
-PLATFORM_CPPFLAGS += -DCONFIG_MPC8540=1
-PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+++ /dev/null
-/*
- * Copyright 2004 Freescale Semiconductor.
- * Copyright (C) 2002,2003, Motorola Inc.
- * Xianghua Xiao <X.Xiao@motorola.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-#include <asm/cache.h>
-#include <asm/mmu.h>
-#include <config.h>
-#include <mpc85xx.h>
-
-
-/*
- * TLB0 and TLB1 Entries
- *
- * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
- * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
- * these TLB entries are established.
- *
- * The TLB entries for DDR are dynamically setup in spd_sdram()
- * and use TLB1 Entries 8 through 15 as needed according to the
- * size of DDR memory.
- *
- * MAS0: tlbsel, esel, nv
- * MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, sharen, x0, x1, w, i, m, g, e
- * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
- */
-
-#define entry_start \
- mflr r1 ; \
- bl 0f ;
-
-#define entry_end \
-0: mflr r0 ; \
- mtlr r1 ; \
- blr ;
-
-
- .section .bootpg, "ax"
- .globl tlb1_entry
-tlb1_entry:
- entry_start
-
- /*
- * Number of TLB0 and TLB1 entries in the following table
- */
- .long 13
-
-#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
- /*
- * TLB0 4K Non-cacheable, guarded
- * 0xff700000 4K Initial CCSRBAR mapping
- *
- * This ends up at a TLB0 Index==0 entry, and must not collide
- * with other TLB0 Entries.
- */
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
-#else
-#error("Update the number of table entries in tlb1_entry")
-#endif
-
- /*
- * TLB0 16K Cacheable, non-guarded
- * 0xd001_0000 16K Temporary Global data for initialization
- *
- * Use four 4K TLB0 entries. These entries must be cacheable
- * as they provide the bootstrap memory before the memory
- * controler and real memory have been configured.
- *
- * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
- * and must not collide with other TLB0 entries.
- */
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
-
- /*
- * TLB 0: 16M Non-cacheable, guarded
- * 0xff000000 16M FLASH
- * Out of reset this entry is only 4K.
- */
- .long TLB1_MAS0(1, 0, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 1: 256M Non-cacheable, guarded
- * 0x80000000 256M PCI1 MEM First half
- */
- .long TLB1_MAS0(1, 1, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 2: 256M Non-cacheable, guarded
- * 0x90000000 256M PCI1 MEM Second half
- */
- .long TLB1_MAS0(1, 2, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
- 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
- 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 3: 256M Non-cacheable, guarded
- * 0xc0000000 256M Rapid IO MEM First half
- */
- .long TLB1_MAS0(1, 3, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 4: 256M Non-cacheable, guarded
- * 0xd0000000 256M Rapid IO MEM Second half
- */
- .long TLB1_MAS0(1, 4, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),
- 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),
- 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 5: 64M Non-cacheable, guarded
- * 0xe000_0000 1M CCSRBAR
- * 0xe200_0000 16M PCI1 IO
- */
- .long TLB1_MAS0(1, 5, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 6: 64M Cacheable, non-guarded
- * 0xf000_0000 64M LBC SDRAM
- */
- .long TLB1_MAS0(1, 6, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 7: 16K Non-cacheable, guarded
- * 0xf8000000 16K BCSR registers
- */
- .long TLB1_MAS0(1, 7, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR), 0,0,0,0,0,1,0,1,0,1)
-
-#if !defined(CONFIG_SPD_EEPROM)
- /*
- * TLB 8, 9: 128M DDR
- * 0x00000000 64M DDR System memory
- * 0x04000000 64M DDR System memory
- * Without SPD EEPROM configured DDR, this must be setup manually.
- * Make sure the TLB count at the top of this table is correct.
- * Likely it needs to be increased by two for these entries.
- */
-#error("Update the number of table entries in tlb1_entry")
- .long TLB1_MAS0(1, 8, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(1, 9, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x4000000),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x4000000),
- 0,0,0,0,0,1,0,1,0,1)
-#endif
-
- entry_end
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000 0x7fff_ffff DDR 2G
- * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
- * 0xc000_0000 0xdfff_ffff RapidIO 512M
- * 0xe000_0000 0xe000_ffff CCSR 1M
- * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
- * 0xf000_0000 0xf7ff_ffff SDRAM 128M
- * 0xf800_0000 0xf80f_ffff BCSR 1M
- * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M
- *
- * Notes:
- * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- * If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-#if !defined(CONFIG_SPD_EEPROM)
-#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
-#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
-#else
-#define LAWBAR0 0
-#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
-#endif
-
-#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
-#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-/*
- * This is not so much the SDRAM map as it is the whole localbus map.
- */
-#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
-#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
-
-#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
-#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_1M))
-
-/*
- * Rapid IO at 0xc000_0000 for 512 M
- */
-#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
-#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-
- .section .bootpg, "ax"
- .globl law_entry
-law_entry:
- entry_start
- .long 0x05
- .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
- .long LAWBAR4,LAWAR4
- entry_end
+++ /dev/null
- /*
- * Copyright 2004 Freescale Semiconductor.
- * (C) Copyright 2002,2003, Motorola Inc.
- * Xianghua Xiao, (X.Xiao@motorola.com)
- *
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <common.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/immap_85xx.h>
-#include <spd.h>
-
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#endif
-
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
-extern long int spd_sdram(void);
-
-void local_bus_init(void);
-void sdram_init(void);
-long int fixed_sdram(void);
-
-
-int board_early_init_f (void)
-{
- return 0;
-}
-
-int checkboard (void)
-{
- puts("Board: ADS\n");
-
-#ifdef CONFIG_PCI
- printf(" PCI1: 32 bit, %d MHz (compiled)\n",
- CONFIG_SYS_CLK_FREQ / 1000000);
-#else
- printf(" PCI1: disabled\n");
-#endif
-
- /*
- * Initialize local bus.
- */
- local_bus_init();
-
- return 0;
-}
-
-
-long int
-initdram(int board_type)
-{
- long dram_size = 0;
- extern long spd_sdram (void);
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
-
- puts("Initializing\n");
-
-#if defined(CONFIG_DDR_DLL)
- {
- volatile ccsr_gur_t *gur= &immap->im_gur;
- uint temp_ddrdll = 0;
-
- /*
- * Work around to stabilize DDR DLL
- */
- temp_ddrdll = gur->ddrdllcr;
- gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
- asm("sync;isync;msync");
- }
-#endif
-
-#if defined(CONFIG_SPD_EEPROM)
- dram_size = spd_sdram ();
-#else
- dram_size = fixed_sdram ();
-#endif
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(dram_size);
-#endif
-
- /*
- * Initialize SDRAM.
- */
- sdram_init();
-
- puts(" DDR: ");
- return dram_size;
-}
-
-
-/*
- * Initialize Local Bus
- */
-
-void
-local_bus_init(void)
-{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
- volatile ccsr_lbc_t *lbc = &immap->im_lbc;
-
- uint clkdiv;
- uint lbc_hz;
- sys_info_t sysinfo;
-
- /*
- * Errata LBC11.
- * Fix Local Bus clock glitch when DLL is enabled.
- *
- * If localbus freq is < 66Mhz, DLL bypass mode must be used.
- * If localbus freq is > 133Mhz, DLL can be safely enabled.
- * Between 66 and 133, the DLL is enabled with an override workaround.
- */
-
- get_sys_info(&sysinfo);
- clkdiv = lbc->lcrr & 0x0f;
- lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
-
- if (lbc_hz < 66) {
- lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
-
- } else if (lbc_hz >= 133) {
- lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
-
- } else {
- /*
- * On REV1 boards, need to change CLKDIV before enable DLL.
- * Default CLKDIV is 8, change it to 4 temporarily.
- */
- uint pvr = get_pvr();
- uint temp_lbcdll = 0;
-
- if (pvr == PVR_85xx_REV1) {
- /* FIXME: Justify the high bit here. */
- lbc->lcrr = 0x10000004;
- }
-
- lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
- udelay(200);
-
- /*
- * Sample LBC DLL ctrl reg, upshift it to set the
- * override bits.
- */
- temp_lbcdll = gur->lbcdllcr;
- gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
- asm("sync;isync;msync");
- }
-}
-
-
-/*
- * Initialize SDRAM memory on the Local Bus.
- */
-
-void
-sdram_init(void)
-{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_lbc_t *lbc= &immap->im_lbc;
- uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
-
- puts(" SDRAM: ");
- print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
-
- /*
- * Setup SDRAM Base and Option Registers
- */
- lbc->or2 = CFG_OR2_PRELIM;
- lbc->br2 = CFG_BR2_PRELIM;
- lbc->lbcr = CFG_LBC_LBCR;
- asm("msync");
-
- lbc->lsrt = CFG_LBC_LSRT;
- lbc->mrtpr = CFG_LBC_MRTPR;
- asm("sync");
-
- /*
- * Configure the SDRAM controller.
- */
- lbc->lsdmr = CFG_LBC_LSDMR_1;
- asm("sync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(100);
-
- lbc->lsdmr = CFG_LBC_LSDMR_2;
- asm("sync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(100);
-
- lbc->lsdmr = CFG_LBC_LSDMR_3;
- asm("sync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(100);
-
- lbc->lsdmr = CFG_LBC_LSDMR_4;
- asm("sync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(100);
-
- lbc->lsdmr = CFG_LBC_LSDMR_5;
- asm("sync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(100);
-}
-
-
-#if defined(CFG_DRAM_TEST)
-int testdram (void)
-{
- uint *pstart = (uint *) CFG_MEMTEST_START;
- uint *pend = (uint *) CFG_MEMTEST_END;
- uint *p;
-
- printf("SDRAM test phase 1:\n");
- for (p = pstart; p < pend; p++)
- *p = 0xaaaaaaaa;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0xaaaaaaaa) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf("SDRAM test phase 2:\n");
- for (p = pstart; p < pend; p++)
- *p = 0x55555555;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0x55555555) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf("SDRAM test passed.\n");
- return 0;
-}
-#endif
-
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*************************************************************************
- * fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-long int fixed_sdram (void)
-{
- #ifndef CFG_RAMBOOT
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_ddr_t *ddr= &immap->im_ddr;
-
- ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
- ddr->cs0_config = CFG_DDR_CS0_CONFIG;
- ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
- ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
- ddr->sdram_mode = CFG_DDR_MODE;
- ddr->sdram_interval = CFG_DDR_INTERVAL;
- #if defined (CONFIG_DDR_ECC)
- ddr->err_disable = 0x0000000D;
- ddr->err_sbe = 0x00ff0000;
- #endif
- asm("sync;isync;msync");
- udelay(500);
- #if defined (CONFIG_DDR_ECC)
- /* Enable ECC checking */
- ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
- #else
- ddr->sdram_cfg = CFG_DDR_CONTROL;
- #endif
- asm("sync; isync; msync");
- udelay(500);
- #endif
- return CFG_SDRAM_SIZE * 1024 * 1024;
-}
-#endif /* !defined(CONFIG_SPD_EEPROM) */
-
-
-#if defined(CONFIG_PCI)
-/*
- * Initialize PCI Devices, report devices found.
- */
-
-
-static struct pci_controller hose;
-
-#endif /* CONFIG_PCI */
-
-
-void
-pci_init_board(void)
-{
-#ifdef CONFIG_PCI
- pci_mpc85xx_init(&hose);
-#endif /* CONFIG_PCI */
-}
-
-
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
-{
- u32 *p;
- int len;
-
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
-#endif
- ft_cpu_setup(blob, bd);
-
- p = ft_get_prop(blob, "/memory/reg", &len);
- if (p != NULL) {
- *p++ = cpu_to_be32(bd->bi_memstart);
- *p = cpu_to_be32(bd->bi_memsize);
- }
-}
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2002,2003, Motorola,Inc.
- * Xianghua Xiao, X.Xiao@motorola.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xFFFFF000 :
- {
- cpu/mpc85xx/start.o (.bootpg)
- board/mpc8540ads/init.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- cpu/mpc85xx/start.o (.text)
- board/mpc8540ads/init.o (.text)
- cpu/mpc85xx/traps.o (.text)
- cpu/mpc85xx/interrupts.o (.text)
- cpu/mpc85xx/cpu_init.o (.text)
- cpu/mpc85xx/cpu.o (.text)
- cpu/mpc85xx/speed.o (.text)
- cpu/mpc85xx/pci.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
- *(.text)
- *(.fixup)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
- __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- _end = . ;
- PROVIDE (end = .);
-}
int board_pre_init (void)
{
#if defined(CONFIG_PCI)
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
- volatile ccsr_pcix_t *pci = &immr->im_pcix;
+ volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
pci->peer &= 0xffffffdf; /* disable master abort */
#endif
{
long dram_size = 0;
extern long spd_sdram (void);
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
#if !defined(CONFIG_RAM_AS_FLASH)
- volatile ccsr_lbc_t *lbc= &immap->im_lbc;
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
sys_info_t sysinfo;
uint temp_lbcdll = 0;
#endif
#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
- volatile ccsr_gur_t *gur= &immap->im_gur;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
#endif
#if defined(CONFIG_DDR_DLL)
* enable errors */
uint *p = 0;
uint i = 0;
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+ volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
dma_init();
for (*p = 0; p < (uint *)(8 * 1024); p++) {
if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
long int fixed_sdram (void)
{
#ifndef CFG_RAMBOOT
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+ volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
ddr->cs0_config = CFG_DDR_CS0_CONFIG;
+++ /dev/null
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).a
-
-COBJS := $(BOARD).o
-SOBJS := init.o
-#SOBJS :=
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
-
-clean:
- rm -f $(OBJS) $(SOBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-# Copyright 2004 Freescale Semiconductor.
-# Modified by Xianghua Xiao, X.Xiao@motorola.com
-# (C) Copyright 2002,2003 Motorola Inc.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# mpc8560ads board
-# default CCARBAR is at 0xff700000
-# assume U-Boot is less than 0.5MB
-#
-TEXT_BASE = 0xfff80000
-
-PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
-PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+++ /dev/null
-/*
- * Copyright 2004 Freescale Semiconductor.
- * Copyright (C) 2002,2003, Motorola Inc.
- * Xianghua Xiao <X.Xiao@motorola.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-#include <asm/cache.h>
-#include <asm/mmu.h>
-#include <config.h>
-#include <mpc85xx.h>
-
-
-/*
- * TLB0 and TLB1 Entries
- *
- * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
- * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
- * these TLB entries are established.
- *
- * The TLB entries for DDR are dynamically setup in spd_sdram()
- * and use TLB1 Entries 8 through 15 as needed according to the
- * size of DDR memory.
- *
- * MAS0: tlbsel, esel, nv
- * MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, sharen, x0, x1, w, i, m, g, e
- * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
- */
-
-#define entry_start \
- mflr r1 ; \
- bl 0f ;
-
-#define entry_end \
-0: mflr r0 ; \
- mtlr r1 ; \
- blr ;
-
-
- .section .bootpg, "ax"
- .globl tlb1_entry
-tlb1_entry:
- entry_start
-
- /*
- * Number of TLB0 and TLB1 entries in the following table
- */
- .long 13
-
-#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
- /*
- * TLB0 4K Non-cacheable, guarded
- * 0xff700000 4K Initial CCSRBAR mapping
- *
- * This ends up at a TLB0 Index==0 entry, and must not collide
- * with other TLB0 Entries.
- */
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
-#else
-#error("Update the number of table entries in tlb1_entry")
-#endif
-
- /*
- * TLB0 16K Cacheable, non-guarded
- * 0xd001_0000 16K Temporary Global data for initialization
- *
- * Use four 4K TLB0 entries. These entries must be cacheable
- * as they provide the bootstrap memory before the memory
- * controler and real memory have been configured.
- *
- * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
- * and must not collide with other TLB0 entries.
- */
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
-
- /*
- * TLB 0: 16M Non-cacheable, guarded
- * 0xff000000 16M FLASH
- * Out of reset this entry is only 4K.
- */
- .long TLB1_MAS0(1, 0, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 1: 256M Non-cacheable, guarded
- * 0x80000000 256M PCI1 MEM First half
- */
- .long TLB1_MAS0(1, 1, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 2: 256M Non-cacheable, guarded
- * 0x90000000 256M PCI1 MEM Second half
- */
- .long TLB1_MAS0(1, 2, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
- 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
- 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 3: 256M Non-cacheable, guarded
- * 0xc0000000 256M Rapid IO MEM First half
- */
- .long TLB1_MAS0(1, 3, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 4: 256M Non-cacheable, guarded
- * 0xd0000000 256M Rapid IO MEM Second half
- */
- .long TLB1_MAS0(1, 4, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),
- 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),
- 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 5: 64M Non-cacheable, guarded
- * 0xe000_0000 1M CCSRBAR
- * 0xe200_0000 16M PCI1 IO
- */
- .long TLB1_MAS0(1, 5, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 6: 64M Cacheable, non-guarded
- * 0xf000_0000 64M LBC SDRAM
- */
- .long TLB1_MAS0(1, 6, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 7: 16K Non-cacheable, guarded
- * 0xf8000000 16K BCSR registers
- */
- .long TLB1_MAS0(1, 7, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR), 0,0,0,0,0,1,0,1,0,1)
-
-#if !defined(CONFIG_SPD_EEPROM)
- /*
- * TLB 8, 9: 128M DDR
- * 0x00000000 64M DDR System memory
- * 0x04000000 64M DDR System memory
- * Without SPD EEPROM configured DDR, this must be setup manually.
- * Make sure the TLB count at the top of this table is correct.
- * Likely it needs to be increased by two for these entries.
- */
-#error("Update the number of table entries in tlb1_entry")
- .long TLB1_MAS0(1, 8, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(1, 9, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x4000000),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x4000000),
- 0,0,0,0,0,1,0,1,0,1)
-#endif
-
- entry_end
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000 0x7fff_ffff DDR 2G
- * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
- * 0xc000_0000 0xdfff_ffff RapidIO 512M
- * 0xe000_0000 0xe000_ffff CCSR 1M
- * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
- * 0xf000_0000 0xf7ff_ffff SDRAM 128M
- * 0xf800_0000 0xf80f_ffff BCSR 1M
- * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M
- *
- * Notes:
- * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- * If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-#if !defined(CONFIG_SPD_EEPROM)
-#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
-#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
-#else
-#define LAWBAR0 0
-#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
-#endif
-
-#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
-#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-/*
- * This is not so much the SDRAM map as it is the whole localbus map.
- */
-#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
-#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
-
-#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
-#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_1M))
-
-/*
- * Rapid IO at 0xc000_0000 for 512 M
- */
-#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
-#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-
- .section .bootpg, "ax"
- .globl law_entry
-law_entry:
- entry_start
- .long 0x05
- .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
- .long LAWBAR4,LAWAR4
- entry_end
+++ /dev/null
-/*
- * Copyright 2004 Freescale Semiconductor.
- * (C) Copyright 2003,Motorola Inc.
- * Xianghua Xiao, (X.Xiao@motorola.com)
- *
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <common.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/immap_85xx.h>
-#include <ioports.h>
-#include <spd.h>
-#include <miiphy.h>
-
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#endif
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
-extern long int spd_sdram(void);
-
-void local_bus_init(void);
-void sdram_init(void);
-long int fixed_sdram(void);
-
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
- /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
- /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
- /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
- /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
- /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
- /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
- /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
- /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
- /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
- /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
- /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
- /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
- /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
- /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
- /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
- /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
- /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
- /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
- /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
- /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
- /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
- /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
- /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
- /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
- /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
- /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
- /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
- /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
- /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
- /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
- /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
- },
-
- /* Port B configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
- /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
- /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
- /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
- /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
- /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
- /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
- /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
- /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
- /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
- /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
- /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
- /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
- /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
- /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
- /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
- /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
- /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
- /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
- /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
- /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
- /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
- /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
- /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
- /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
- /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
- /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
- /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
- /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
- /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
- /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
- /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
- /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
- /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
- /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
- /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
- /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
- /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
- /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
- /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
- /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
- /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
- /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
- /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
- /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
- /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
- /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
- /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
- /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
- /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
- /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
- /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
- /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
- /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
- /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
- /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
- /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- }
-};
-
-
-/*
- * MPC8560ADS Board Status & Control Registers
- */
-typedef struct bcsr_ {
- volatile unsigned char bcsr0;
- volatile unsigned char bcsr1;
- volatile unsigned char bcsr2;
- volatile unsigned char bcsr3;
- volatile unsigned char bcsr4;
- volatile unsigned char bcsr5;
-} bcsr_t;
-
-
-int board_early_init_f (void)
-{
- return 0;
-}
-
-void reset_phy (void)
-{
-#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
- volatile bcsr_t *bcsr = (bcsr_t *) CFG_BCSR;
-#endif
- /* reset Giga bit Ethernet port if needed here */
-
- /* reset the CPM FEC port */
-#if (CONFIG_ETHER_INDEX == 2)
- bcsr->bcsr2 &= ~FETH2_RST;
- udelay(2);
- bcsr->bcsr2 |= FETH2_RST;
- udelay(1000);
-#elif (CONFIG_ETHER_INDEX == 3)
- bcsr->bcsr3 &= ~FETH3_RST;
- udelay(2);
- bcsr->bcsr3 |= FETH3_RST;
- udelay(1000);
-#endif
-#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
- /* reset PHY */
- miiphy_reset("FCC1 ETHERNET", 0x0);
-
- /* change PHY address to 0x02 */
- bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);
-
- bb_miiphy_write(NULL, 0x02, PHY_BMCR,
- PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
-#endif /* CONFIG_MII */
-}
-
-
-int checkboard (void)
-{
- puts("Board: ADS\n");
-
-#ifdef CONFIG_PCI
- printf(" PCI1: 32 bit, %d MHz (compiled)\n",
- CONFIG_SYS_CLK_FREQ / 1000000);
-#else
- printf(" PCI1: disabled\n");
-#endif
-
- /*
- * Initialize local bus.
- */
- local_bus_init();
-
- return 0;
-}
-
-
-long int
-initdram(int board_type)
-{
- long dram_size = 0;
- extern long spd_sdram (void);
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
-
- puts("Initializing\n");
-
-#if defined(CONFIG_DDR_DLL)
- {
- volatile ccsr_gur_t *gur= &immap->im_gur;
- uint temp_ddrdll = 0;
-
- /*
- * Work around to stabilize DDR DLL
- */
- temp_ddrdll = gur->ddrdllcr;
- gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
- asm("sync;isync;msync");
- }
-#endif
-
-#if defined(CONFIG_SPD_EEPROM)
- dram_size = spd_sdram ();
-#else
- dram_size = fixed_sdram ();
-#endif
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(dram_size);
-#endif
-
- /*
- * Initialize SDRAM.
- */
- sdram_init();
-
- puts(" DDR: ");
- return dram_size;
-}
-
-
-/*
- * Initialize Local Bus
- */
-
-void
-local_bus_init(void)
-{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
- volatile ccsr_lbc_t *lbc = &immap->im_lbc;
-
- uint clkdiv;
- uint lbc_hz;
- sys_info_t sysinfo;
-
- /*
- * Errata LBC11.
- * Fix Local Bus clock glitch when DLL is enabled.
- *
- * If localbus freq is < 66Mhz, DLL bypass mode must be used.
- * If localbus freq is > 133Mhz, DLL can be safely enabled.
- * Between 66 and 133, the DLL is enabled with an override workaround.
- */
-
- get_sys_info(&sysinfo);
- clkdiv = lbc->lcrr & 0x0f;
- lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
-
- if (lbc_hz < 66) {
- lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
-
- } else if (lbc_hz >= 133) {
- lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
-
- } else {
- /*
- * On REV1 boards, need to change CLKDIV before enable DLL.
- * Default CLKDIV is 8, change it to 4 temporarily.
- */
- uint pvr = get_pvr();
- uint temp_lbcdll = 0;
-
- if (pvr == PVR_85xx_REV1) {
- /* FIXME: Justify the high bit here. */
- lbc->lcrr = 0x10000004;
- }
-
- lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);/* DLL Enabled */
- udelay(200);
-
- /*
- * Sample LBC DLL ctrl reg, upshift it to set the
- * override bits.
- */
- temp_lbcdll = gur->lbcdllcr;
- gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
- asm("sync;isync;msync");
- }
-}
-
-
-/*
- * Initialize SDRAM memory on the Local Bus.
- */
-
-void
-sdram_init(void)
-{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_lbc_t *lbc= &immap->im_lbc;
- uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
-
- puts(" SDRAM: ");
- print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
-
- /*
- * Setup SDRAM Base and Option Registers
- */
- lbc->or2 = CFG_OR2_PRELIM;
- lbc->br2 = CFG_BR2_PRELIM;
- lbc->lbcr = CFG_LBC_LBCR;
- asm("msync");
-
- lbc->lsrt = CFG_LBC_LSRT;
- lbc->mrtpr = CFG_LBC_MRTPR;
- asm("sync");
-
- /*
- * Configure the SDRAM controller.
- */
- lbc->lsdmr = CFG_LBC_LSDMR_1;
- asm("sync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(100);
-
- lbc->lsdmr = CFG_LBC_LSDMR_2;
- asm("sync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(100);
-
- lbc->lsdmr = CFG_LBC_LSDMR_3;
- asm("sync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(100);
-
- lbc->lsdmr = CFG_LBC_LSDMR_4;
- asm("sync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(100);
-
- lbc->lsdmr = CFG_LBC_LSDMR_5;
- asm("sync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(100);
-}
-
-
-#if defined(CFG_DRAM_TEST)
-int testdram (void)
-{
- uint *pstart = (uint *) CFG_MEMTEST_START;
- uint *pend = (uint *) CFG_MEMTEST_END;
- uint *p;
-
- printf("SDRAM test phase 1:\n");
- for (p = pstart; p < pend; p++)
- *p = 0xaaaaaaaa;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0xaaaaaaaa) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf("SDRAM test phase 2:\n");
- for (p = pstart; p < pend; p++)
- *p = 0x55555555;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0x55555555) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf("SDRAM test passed.\n");
- return 0;
-}
-#endif
-
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*************************************************************************
- * fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-long int fixed_sdram (void)
-{
- #ifndef CFG_RAMBOOT
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_ddr_t *ddr= &immap->im_ddr;
-
- ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
- ddr->cs0_config = CFG_DDR_CS0_CONFIG;
- ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
- ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
- ddr->sdram_mode = CFG_DDR_MODE;
- ddr->sdram_interval = CFG_DDR_INTERVAL;
- #if defined (CONFIG_DDR_ECC)
- ddr->err_disable = 0x0000000D;
- ddr->err_sbe = 0x00ff0000;
- #endif
- asm("sync;isync;msync");
- udelay(500);
- #if defined (CONFIG_DDR_ECC)
- /* Enable ECC checking */
- ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
- #else
- ddr->sdram_cfg = CFG_DDR_CONTROL;
- #endif
- asm("sync; isync; msync");
- udelay(500);
- #endif
- return CFG_SDRAM_SIZE * 1024 * 1024;
-}
-#endif /* !defined(CONFIG_SPD_EEPROM) */
-
-
-#if defined(CONFIG_PCI)
-/*
- * Initialize PCI Devices, report devices found.
- */
-
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_mpc85xxads_config_table[] = {
- { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- PCI_IDSEL_NUMBER, PCI_ANY_ID,
- pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
- } },
- { }
-};
-#endif
-
-
-static struct pci_controller hose = {
-#ifndef CONFIG_PCI_PNP
- config_table: pci_mpc85xxads_config_table,
-#endif
-};
-
-#endif /* CONFIG_PCI */
-
-
-void
-pci_init_board(void)
-{
-#ifdef CONFIG_PCI
- pci_mpc85xx_init(&hose);
-#endif /* CONFIG_PCI */
-}
-
-
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_soc_setup(void *blob, bd_t *bd)
-{
- u32 *p;
- int len;
-
- p = ft_get_prop(blob, "/" OF_SOC "/cpm@e0000000/brg-frequency", &len);
-
- if (p != NULL)
- *p = cpu_to_be32(bd->bi_brgfreq);
-
- p = ft_get_prop(blob,
- "/" OF_SOC "/cpm@e0000000/scc@91a00/current-speed",
- &len);
- if (p != NULL)
- *p = cpu_to_be32(bd->bi_baudrate);
-
- p = ft_get_prop(blob,
- "/" OF_SOC "/cpm@e0000000/scc@91a20/current-speed",
- &len);
- if (p != NULL)
- *p = cpu_to_be32(bd->bi_baudrate);
-}
-
-void
-ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
- ft_soc_setup(blob, bd);
-}
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2002,2003,Motorola,Inc.
- * Xianghua Xiao, X.Xiao@motorola.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xFFFFF000 :
- {
- cpu/mpc85xx/start.o (.bootpg)
- board/mpc8560ads/init.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- cpu/mpc85xx/start.o (.text)
- board/mpc8560ads/init.o (.text)
- cpu/mpc85xx/commproc.o (.text)
- cpu/mpc85xx/traps.o (.text)
- cpu/mpc85xx/interrupts.o (.text)
- cpu/mpc85xx/serial_scc.o (.text)
- cpu/mpc85xx/ether_fcc.o (.text)
- cpu/mpc85xx/cpu_init.o (.text)
- cpu/mpc85xx/cpu.o (.text)
- cpu/mpc85xx/speed.o (.text)
- cpu/mpc85xx/spd_sdram.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
- *(.text)
- *(.fixup)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
- __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- _end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-#
-# Copyright 2004-2007 Freescale Semiconductor.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB = $(obj)lib$(BOARD).a
-
-COBJS := $(BOARD).o \
- bcsr.o \
- ft_board.o
-
-SOBJS := init.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
-
-clean:
- rm -f $(OBJS) $(SOBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-/*
- * Copyright 2007 Freescale Semiconductor.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include "bcsr.h"
-
-void enable_8568mds_duart()
-{
- volatile uint* duart_mux = (uint *)(CFG_CCSRBAR + 0xe0060);
- volatile uint* devices = (uint *)(CFG_CCSRBAR + 0xe0070);
- volatile u8 *bcsr = (u8 *)(CFG_BCSR);
-
- *duart_mux = 0x80000000; /* Set the mux to Duart on PMUXCR */
- *devices = 0; /* Enable all peripheral devices */
- bcsr[5] |= 0x01; /* Enable Duart in BCSR*/
-}
-
-void enable_8568mds_flash_write()
-{
- volatile u8 *bcsr = (u8 *)(CFG_BCSR);
-
- bcsr[9] |= 0x01;
-}
-
-void disable_8568mds_flash_write()
-{
- volatile u8 *bcsr = (u8 *)(CFG_BCSR);
-
- bcsr[9] &= ~(0x01);
-}
-
-void enable_8568mds_qe_mdio()
-{
- u8 *bcsr = (u8 *)(CFG_BCSR);
-
- bcsr[7] |= 0x01;
-}
+++ /dev/null
-/*
- * Copyright 2007 Freescale Semiconductor.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __BCSR_H_
-#define __BCSR_H_
-
-#include <common.h>
-
-/* BCSR Bit definitions
- * BCSR 0 *
- 0:3 ccb sys pll
- 4:6 cfg core pll
- 7 cfg boot seq
-
- * BCSR 1 *
- 0:2 cfg rom lock
- 3:5 cfg host agent
- 6 PCI IO
- 7 cfg RIO size
-
- * BCSR 2 *
- 0:4 QE PLL
- 5 QE clock
- 6 cfg PCI arbiter
-
- * BCSR 3 *
- 0 TSEC1 reduce
- 1 TSEC2 reduce
- 2:3 TSEC1 protocol
- 4:5 TSEC2 protocol
- 6 PHY1 slave
- 7 PHY2 slave
-
- * BCSR 4 *
- 4 clock enable
- 5 boot EPROM
- 6 GETH transactive reset
- 7 BRD write potect
-
- * BCSR 5 *
- 1:3 Leds 1-3
- 4 UPC1 enable
- 5 UPC2 enable
- 6 UPC2 pos
- 7 RS232 enable
-
- * BCSR 6 *
- 0 CFG ver 0
- 1 CFG ver 1
- 6 Register config led
- 7 Power on reset
-
- * BCSR 7 *
- 2 board host mode indication
- 5 enable TSEC1 PHY
- 6 enable TSEC2 PHY
-
- * BCSR 8 *
- 0 UCC GETH1 enable
- 1 UCC GMII enable
- 3 UCC TBI enable
- 5 UCC MII enable
- 7 Real time clock reset
-
- * BCSR 9 *
- 0 UCC2 GETH enable
- 1 UCC2 GMII enable
- 3 UCC2 TBI enable
- 5 UCC2 MII enable
- 6 Ready only - indicate flash ready after burning
- 7 Flash write protect
-*/
-
-/*BCSR Utils functions*/
-
-void enable_8568mds_duart(void);
-void enable_8568mds_flash_write(void);
-void disable_8568mds_flash_write(void);
-void enable_8568mds_qe_mdio(void);
-
-#endif /* __BCSR_H_ */
+++ /dev/null
-#
-# Copyright 2007 Freescale Semiconductor.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# mpc8568mds board
-#
-TEXT_BASE = 0xfff80000
-
-PLATFORM_CPPFLAGS += -DCONFIG_E500=1
-PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
-PLATFORM_CPPFLAGS += -DCONFIG_MPC8568=1
+++ /dev/null
-/*
- * Copyright 2004-2007 Freescale Semiconductor.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#include <ft_build.h>
-
-extern void ft_cpu_setup(void *blob, bd_t *bd);
-
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
-{
- u32 *p;
- int len;
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
-#endif
- ft_cpu_setup(blob, bd);
- p = ft_get_prop(blob, "/memory/reg", &len);
- if (p != NULL) {
- *p++ = cpu_to_be32(bd->bi_memstart);
- *p = cpu_to_be32(bd->bi_memsize);
- }
-}
-#endif /* CONFIG_OF_FLAT_TREE && CONFIG_OF_BOARD_SETUP */
+++ /dev/null
-/*
- * Copyright 2004-2007 Freescale Semiconductor.
- * Copyright 2002,2003, Motorola Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-#include <asm/cache.h>
-#include <asm/mmu.h>
-#include <config.h>
-#include <mpc85xx.h>
-
-
-/*
- * TLB0 and TLB1 Entries
- *
- * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
- * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
- * these TLB entries are established.
- *
- * The TLB entries for DDR are dynamically setup in spd_sdram()
- * and use TLB1 Entries 8 through 15 as needed according to the
- * size of DDR memory.
- *
- * MAS0: tlbsel, esel, nv
- * MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, sharen, x0, x1, w, i, m, g, e
- * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
- */
-#define entry_start \
- mflr r1 ; \
- bl 0f ;
-
-#define entry_end \
-0: mflr r0 ; \
- mtlr r1 ; \
- blr ;
-
-
- .section .bootpg, "ax"
- .globl tlb1_entry
-tlb1_entry:
- entry_start
-
- /*
- * Number of TLB0 and TLB1 entries in the following table
- */
- .long (2f-1f)/16
-
-1:
-#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
- /*
- * TLB0 4K Non-cacheable, guarded
- * 0xff700000 4K Initial CCSRBAR mapping
- *
- * This ends up at a TLB0 Index==0 entry, and must not collide
- * with other TLB0 Entries.
- */
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
-#else
-#error("Update the number of table entries in tlb1_entry")
-#endif
-
- /*
- * TLB0 16K Cacheable, non-guarded
- * 0xd001_0000 16K Temporary Global data for initialization
- *
- * Use four 4K TLB0 entries. These entries must be cacheable
- * as they provide the bootstrap memory before the memory
- * controler and real memory have been configured.
- *
- * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
- * and must not collide with other TLB0 entries.
- */
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
- .long TLB1_MAS0(0, 0, 0)
- .long TLB1_MAS1(1, 0, 0, 0, 0)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
- 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
- 0,0,0,0,0,1,0,1,0,1)
-
- /* TLB 1 Initializations */
- /*
- * TLBe 0: 16M Non-cacheable, guarded
- * 0xff000000 16M FLASH (upper half)
- * Out of reset this entry is only 4K.
- */
- .long TLB1_MAS0(1, 0, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE + 0x1000000),
- 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE + 0x1000000),
- 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLBe 1: 16M Non-cacheable, guarded
- * 0xfe000000 16M FLASH (lower half)
- */
- .long TLB1_MAS0(1, 1, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLBe 2: 1G Non-cacheable, guarded
- * 0x80000000 512M PCI1 MEM
- * 0xa0000000 512M PCIe MEM
- */
- .long TLB1_MAS0(1, 2, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLBe 3: 64M Non-cacheable, guarded
- * 0xe000_0000 1M CCSRBAR
- * 0xe200_0000 8M PCI1 IO
- * 0xe280_0000 8M PCIe IO
- */
- .long TLB1_MAS0(1, 3, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLBe 4: 64M Cacheable, non-guarded
- * 0xf000_0000 64M LBC SDRAM
- */
- .long TLB1_MAS0(1, 4, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLBe 5: 256K Non-cacheable, guarded
- * 0xf8000000 32K BCSR
- * 0xf8008000 32K PIB (CS4)
- * 0xf8010000 32K PIB (CS5)
- */
- .long TLB1_MAS0(1, 5, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR_BASE), 0,0,0,0,0,1,0,1,0,1)
-
-2:
- entry_end
-
-/*
- * LAW(Local Access Window) configuration:
- *
- *0) 0x0000_0000 0x7fff_ffff DDR 2G
- *1) 0x8000_0000 0x9fff_ffff PCI1 MEM 512MB
- *2) 0xa000_0000 0xbfff_ffff PCIe MEM 512MB
- *-) 0xe000_0000 0xe00f_ffff CCSR 1M
- *3) 0xe200_0000 0xe27f_ffff PCI1 I/O 8M
- *4) 0xe280_0000 0xe2ff_ffff PCIe I/O 8M
- *5) 0xc000_0000 0xdfff_ffff SRIO 512MB
- *6.a) 0xf000_0000 0xf3ff_ffff SDRAM 64MB
- *6.b) 0xf800_0000 0xf800_7fff BCSR 32KB
- *6.c) 0xf800_8000 0xf800_ffff PIB (CS4) 32KB
- *6.d) 0xf801_0000 0xf801_7fff PIB (CS5) 32KB
- *6.e) 0xfe00_0000 0xffff_ffff Flash 32MB
- *
- *Notes:
- * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- * If flash is 8M at default position (last 8M), no LAW needed.
- *
- * The defines below are 1-off of the actual LAWAR0 usage.
- * So LAWAR3 define uses the LAWAR4 register in the ECM.
- */
-
-#define LAWBAR0 0
-#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
-
-#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
-#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-#define LAWBAR2 ((CFG_PEX_MEM_BASE>>12) & 0xfffff)
-#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
-#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
-
-#define LAWBAR4 ((CFG_PEX_IO_PHYS>>12) & 0xfffff)
-#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_8M))
-
-
-#define LAWBAR5 ((CFG_SRIO_MEM_BASE>>12) & 0xfffff)
-#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-/* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */
-#define LAWBAR6 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
-#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
-
- .section .bootpg, "ax"
- .globl law_entry
-
-law_entry:
- entry_start
- .long (4f-3f)/8
-3:
- .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
- .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5,LAWBAR6,LAWAR6
-4:
- entry_end
+++ /dev/null
-/*
- * Copyright 2007 Freescale Semiconductor.
- *
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/immap_85xx.h>
-#include <spd.h>
-#include <i2c.h>
-#include <ioports.h>
-
-#include "bcsr.h"
-
-const qe_iop_conf_t qe_iop_conf_tab[] = {
- /* GETH1 */
- {4, 10, 1, 0, 2}, /* TxD0 */
- {4, 9, 1, 0, 2}, /* TxD1 */
- {4, 8, 1, 0, 2}, /* TxD2 */
- {4, 7, 1, 0, 2}, /* TxD3 */
- {4, 23, 1, 0, 2}, /* TxD4 */
- {4, 22, 1, 0, 2}, /* TxD5 */
- {4, 21, 1, 0, 2}, /* TxD6 */
- {4, 20, 1, 0, 2}, /* TxD7 */
- {4, 15, 2, 0, 2}, /* RxD0 */
- {4, 14, 2, 0, 2}, /* RxD1 */
- {4, 13, 2, 0, 2}, /* RxD2 */
- {4, 12, 2, 0, 2}, /* RxD3 */
- {4, 29, 2, 0, 2}, /* RxD4 */
- {4, 28, 2, 0, 2}, /* RxD5 */
- {4, 27, 2, 0, 2}, /* RxD6 */
- {4, 26, 2, 0, 2}, /* RxD7 */
- {4, 11, 1, 0, 2}, /* TX_EN */
- {4, 24, 1, 0, 2}, /* TX_ER */
- {4, 16, 2, 0, 2}, /* RX_DV */
- {4, 30, 2, 0, 2}, /* RX_ER */
- {4, 17, 2, 0, 2}, /* RX_CLK */
- {4, 19, 1, 0, 2}, /* GTX_CLK */
- {1, 31, 2, 0, 3}, /* GTX125 */
-
- /* GETH2 */
- {5, 10, 1, 0, 2}, /* TxD0 */
- {5, 9, 1, 0, 2}, /* TxD1 */
- {5, 8, 1, 0, 2}, /* TxD2 */
- {5, 7, 1, 0, 2}, /* TxD3 */
- {5, 23, 1, 0, 2}, /* TxD4 */
- {5, 22, 1, 0, 2}, /* TxD5 */
- {5, 21, 1, 0, 2}, /* TxD6 */
- {5, 20, 1, 0, 2}, /* TxD7 */
- {5, 15, 2, 0, 2}, /* RxD0 */
- {5, 14, 2, 0, 2}, /* RxD1 */
- {5, 13, 2, 0, 2}, /* RxD2 */
- {5, 12, 2, 0, 2}, /* RxD3 */
- {5, 29, 2, 0, 2}, /* RxD4 */
- {5, 28, 2, 0, 2}, /* RxD5 */
- {5, 27, 2, 0, 3}, /* RxD6 */
- {5, 26, 2, 0, 2}, /* RxD7 */
- {5, 11, 1, 0, 2}, /* TX_EN */
- {5, 24, 1, 0, 2}, /* TX_ER */
- {5, 16, 2, 0, 2}, /* RX_DV */
- {5, 30, 2, 0, 2}, /* RX_ER */
- {5, 17, 2, 0, 2}, /* RX_CLK */
- {5, 19, 1, 0, 2}, /* GTX_CLK */
- {1, 31, 2, 0, 3}, /* GTX125 */
- {4, 6, 3, 0, 2}, /* MDIO */
- {4, 5, 1, 0, 2}, /* MDC */
- {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
-};
-
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
-extern long int spd_sdram(void);
-
-void local_bus_init(void);
-void sdram_init(void);
-
-int board_early_init_f (void)
-{
- /*
- * Initialize local bus.
- */
- local_bus_init ();
-
- enable_8568mds_duart();
- enable_8568mds_flash_write();
-#if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS)
- enable_8568mds_qe_mdio();
-#endif
-
-#ifdef CFG_I2C2_OFFSET
- /* Enable I2C2_SCL and I2C2_SDA */
- volatile struct par_io *port_c;
- port_c = (struct par_io*)(CFG_IMMR + 0xe0140);
- port_c->cpdir2 |= 0x0f000000;
- port_c->cppar2 &= ~0x0f000000;
- port_c->cppar2 |= 0x0a000000;
-#endif
-
- return 0;
-}
-
-int checkboard (void)
-{
- printf ("Board: 8568 MDS\n");
-
- return 0;
-}
-
-long int
-initdram(int board_type)
-{
- long dram_size = 0;
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
-
- puts("Initializing\n");
-
-#if defined(CONFIG_DDR_DLL)
- {
- /*
- * Work around to stabilize DDR DLL MSYNC_IN.
- * Errata DDR9 seems to have been fixed.
- * This is now the workaround for Errata DDR11:
- * Override DLL = 1, Course Adj = 1, Tap Select = 0
- */
-
- volatile ccsr_gur_t *gur= &immap->im_gur;
-
- gur->ddrdllcr = 0x81000000;
- asm("sync;isync;msync");
- udelay(200);
- }
-#endif
- dram_size = spd_sdram();
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(dram_size);
-#endif
- /*
- * SDRAM Initialization
- */
- sdram_init();
-
- puts(" DDR: ");
- return dram_size;
-}
-
-/*
- * Initialize Local Bus
- */
-void
-local_bus_init(void)
-{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
- volatile ccsr_lbc_t *lbc = &immap->im_lbc;
-
- uint clkdiv;
- uint lbc_hz;
- sys_info_t sysinfo;
-
- get_sys_info(&sysinfo);
- clkdiv = (lbc->lcrr & 0x0f) * 2;
- lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
-
- gur->lbiuiplldcr1 = 0x00078080;
- if (clkdiv == 16) {
- gur->lbiuiplldcr0 = 0x7c0f1bf0;
- } else if (clkdiv == 8) {
- gur->lbiuiplldcr0 = 0x6c0f1bf0;
- } else if (clkdiv == 4) {
- gur->lbiuiplldcr0 = 0x5c0f1bf0;
- }
-
- lbc->lcrr |= 0x00030000;
-
- asm("sync;isync;msync");
-}
-
-/*
- * Initialize SDRAM memory on the Local Bus.
- */
-void
-sdram_init(void)
-{
-#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
-
- uint idx;
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_lbc_t *lbc = &immap->im_lbc;
- uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
- uint lsdmr_common;
-
- puts(" SDRAM: ");
-
- print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
-
- /*
- * Setup SDRAM Base and Option Registers
- */
- lbc->or2 = CFG_OR2_PRELIM;
- asm("msync");
-
- lbc->br2 = CFG_BR2_PRELIM;
- asm("msync");
-
- lbc->lbcr = CFG_LBC_LBCR;
- asm("msync");
-
-
- lbc->lsrt = CFG_LBC_LSRT;
- lbc->mrtpr = CFG_LBC_MRTPR;
- asm("msync");
-
- /*
- * MPC8568 uses "new" 15-16 style addressing.
- */
- lsdmr_common = CFG_LBC_LSDMR_COMMON;
- lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
-
- /*
- * Issue PRECHARGE ALL command.
- */
- lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(100);
-
- /*
- * Issue 8 AUTO REFRESH commands.
- */
- for (idx = 0; idx < 8; idx++) {
- lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(100);
- }
-
- /*
- * Issue 8 MODE-set command.
- */
- lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(100);
-
- /*
- * Issue NORMAL OP command.
- */
- lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(200); /* Overkill. Must wait > 200 bus cycles */
-
-#endif /* enable SDRAM init */
-}
-
-#if defined(CFG_DRAM_TEST)
-int
-testdram(void)
-{
- uint *pstart = (uint *) CFG_MEMTEST_START;
- uint *pend = (uint *) CFG_MEMTEST_END;
- uint *p;
-
- printf("Testing DRAM from 0x%08x to 0x%08x\n",
- CFG_MEMTEST_START,
- CFG_MEMTEST_END);
-
- printf("DRAM test phase 1:\n");
- for (p = pstart; p < pend; p++)
- *p = 0xaaaaaaaa;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0xaaaaaaaa) {
- printf ("DRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf("DRAM test phase 2:\n");
- for (p = pstart; p < pend; p++)
- *p = 0x55555555;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0x55555555) {
- printf ("DRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf("DRAM test passed.\n");
- return 0;
-}
-#endif
-
-#if defined(CONFIG_PCI)
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_mpc8568mds_config_table[] = {
- {
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- pci_cfgfunc_config_device,
- {PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
- },
- {}
-};
-#endif
-
-static struct pci_controller hose[] = {
- {
-#ifndef CONFIG_PCI_PNP
- config_table: pci_mpc8568mds_config_table,
-#endif
- }
-};
-
-#endif /* CONFIG_PCI */
-
-/*
- * pib_init() -- Initialize the PCA9555 IO expander on the PIB board
- */
-void
-pib_init(void)
-{
- u8 val8, orig_i2c_bus;
- /*
- * Assign PIB PMC2/3 to PCI bus
- */
-
- /*switch temporarily to I2C bus #2 */
- orig_i2c_bus = i2c_get_bus_num();
- i2c_set_bus_num(1);
-
- val8 = 0x00;
- i2c_write(0x23, 0x6, 1, &val8, 1);
- i2c_write(0x23, 0x7, 1, &val8, 1);
- val8 = 0xff;
- i2c_write(0x23, 0x2, 1, &val8, 1);
- i2c_write(0x23, 0x3, 1, &val8, 1);
-
- val8 = 0x00;
- i2c_write(0x26, 0x6, 1, &val8, 1);
- val8 = 0x34;
- i2c_write(0x26, 0x7, 1, &val8, 1);
- val8 = 0xf9;
- i2c_write(0x26, 0x2, 1, &val8, 1);
- val8 = 0xff;
- i2c_write(0x26, 0x3, 1, &val8, 1);
-
- val8 = 0x00;
- i2c_write(0x27, 0x6, 1, &val8, 1);
- i2c_write(0x27, 0x7, 1, &val8, 1);
- val8 = 0xff;
- i2c_write(0x27, 0x2, 1, &val8, 1);
- val8 = 0xef;
- i2c_write(0x27, 0x3, 1, &val8, 1);
-
- asm("eieio");
-}
-
-void
-pci_init_board(void)
-{
-#ifdef CONFIG_PCI
- pib_init();
- pci_mpc85xx_init(hose);
-#endif
-}
+++ /dev/null
-/*
- * Copyright 2004-2007 Freescale Semiconductor.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-
-SECTIONS
-{
- /* ELIOR - From RAM: From FLASH: 0xFFFFFFFC*/
- .resetvec 0xFFFFFFFC:
- {
- *(.resetvec)
- } = 0xffff
-
- /*(ELIOR - From RAM: From FLASH: 0xFFFFF000*/
- .bootpg 0xFFFFF000:
- {
- cpu/mpc85xx/start.o (.bootpg)
- board/mpc8568mds/init.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- cpu/mpc85xx/start.o (.text)
- board/mpc8568mds/init.o (.text)
- cpu/mpc85xx/traps.o (.text)
- cpu/mpc85xx/interrupts.o (.text)
- cpu/mpc85xx/cpu_init.o (.text)
- cpu/mpc85xx/cpu.o (.text)
- cpu/mpc85xx/speed.o (.text)
- cpu/mpc85xx/pci.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
- *(.text)
- *(.fixup)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
- __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- _end = . ;
- PROVIDE (end = .);
-}
#ifdef CONFIG_PIP405
#include "../pip405/pip405.h"
-#include <405gp_pci.h>
+#include <asm/4xx_pci.h>
#endif
#ifdef CONFIG_MIP405
#include "../mip405/mip405.h"
-#include <405gp_pci.h>
+#include <asm/4xx_pci.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
void video_get_info_str (int line_number, char *info)
{
/* init video info strings for graphic console */
- PPC405_SYS_INFO sys_info;
+ PPC4xx_SYS_INFO sys_info;
char rev;
int i,boot;
unsigned long pvr;
#if defined(CONFIG_PIP405)
#include "../pip405/pip405.h"
#endif
-#include <405gp_pci.h>
+#include <asm/4xx_pci.h>
#else /* defined(CONFIG_PATI) */
#include <mpc5xx.h>
#endif
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
cpu/ppc4xx/4xx_enet.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
--- /dev/null
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# Copyright (C) 2007
+# Kenati Technologies, Inc.
+#
+# board/ms7722se/Makefile
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := ms7722se.o
+SOBJS := lowlevel_init.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- /dev/null
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# Copyright (C) 2007
+# Kenati Technologies, Inc.
+#
+# board/ms7722se/config.mk
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+#
+# TEXT_BASE refers to image _after_ relocation.
+#
+# NOTE: Must match value used in u-boot.lds (in this directory).
+#
+
+TEXT_BASE = 0x8FFC0000
--- /dev/null
+/*
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * Copyright (C) 2007
+ * Kenati Technologies, Inc.
+ *
+ * board/ms7722se/lowlevel_init.S
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#include <asm/processor.h>
+
+/*
+ * Board specific low level init code, called _very_ early in the
+ * startup sequence. Relocation to SDRAM has not happened yet, no
+ * stack is available, bss section has not been initialised, etc.
+ *
+ * (Note: As no stack is available, no subroutines can be called...).
+ */
+
+ .global lowlevel_init
+
+ .text
+ .align 2
+
+lowlevel_init:
+
+ mov.l CCR_A, r1 ! Address of Cache Control Register
+ mov.l CCR_D, r0 ! Instruction Cache Invalidate
+ mov.l r0, @r1
+
+ mov.l MMUCR_A, r1 ! Address of MMU Control Register
+ mov.l MMUCR_D, r0 ! TI == TLB Invalidate bit
+ mov.l r0, @r1
+
+ mov.l MSTPCR0_A, r1 ! Address of Power Control Register 0
+ mov.l MSTPCR0_D, r0 !
+ mov.l r0, @r1
+
+ mov.l MSTPCR2_A, r1 ! Address of Power Control Register 2
+ mov.l MSTPCR2_D, r0 !
+ mov.l r0, @r1
+
+ mov.l SBSCR_A, r1 !
+ mov.w SBSCR_D, r0 !
+ mov.w r0, @r1
+
+ mov.l PSCR_A, r1 !
+ mov.w PSCR_D, r0 !
+ mov.w r0, @r1
+
+! mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register)
+! mov.w RWTCSR_D_1, r0 ! 0xA507 -> timer_STOP/WDT_CLK=max
+! mov.w r0, @r1
+
+ mov.l RWTCNT_A, r1 ! 0xA4520000 (Watchdog Count Register)
+ mov.w RWTCNT_D, r0 ! 0x5A00 -> Clear
+ mov.w r0, @r1
+
+ mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register)
+ mov.w RWTCSR_D_2, r0 ! 0xA504 -> timer_STOP/CLK=500ms
+ mov.w r0, @r1
+
+ mov.l FRQCR_A, r1 ! 0xA4150000 Frequency control register
+ mov.l FRQCR_D, r0 !
+ mov.l r0, @r1
+
+ mov.l CCR_A, r1 ! Address of Cache Control Register
+ mov.l CCR_D_2, r0 ! ??
+ mov.l r0, @r1
+
+bsc_init:
+
+ mov.l PSELA_A, r1
+ mov.w PSELA_D, r0
+ mov.w r0, @r1
+
+ mov.l DRVCR_A, r1
+ mov.w DRVCR_D, r0
+ mov.w r0, @r1
+
+ mov.l PCCR_A, r1
+ mov.w PCCR_D, r0
+ mov.w r0, @r1
+
+ mov.l PECR_A, r1
+ mov.w PECR_D, r0
+ mov.w r0, @r1
+
+ mov.l PJCR_A, r1
+ mov.w PJCR_D, r0
+ mov.w r0, @r1
+
+ mov.l PXCR_A, r1
+ mov.w PXCR_D, r0
+ mov.w r0, @r1
+
+ mov.l CMNCR_A, r1 ! CMNCR address -> R1
+ mov.l CMNCR_D, r0 ! CMNCR data -> R0
+ mov.l r0, @r1 ! CMNCR set
+
+ mov.l CS0BCR_A, r1 ! CS0BCR address -> R1
+ mov.l CS0BCR_D, r0 ! CS0BCR data -> R0
+ mov.l r0, @r1 ! CS0BCR set
+
+ mov.l CS2BCR_A, r1 ! CS2BCR address -> R1
+ mov.l CS2BCR_D, r0 ! CS2BCR data -> R0
+ mov.l r0, @r1 ! CS2BCR set
+
+ mov.l CS4BCR_A, r1 ! CS4BCR address -> R1
+ mov.l CS4BCR_D, r0 ! CS4BCR data -> R0
+ mov.l r0, @r1 ! CS4BCR set
+
+ mov.l CS5ABCR_A, r1 ! CS5ABCR address -> R1
+ mov.l CS5ABCR_D, r0 ! CS5ABCR data -> R0
+ mov.l r0, @r1 ! CS5ABCR set
+
+ mov.l CS5BBCR_A, r1 ! CS5BBCR address -> R1
+ mov.l CS5BBCR_D, r0 ! CS5BBCR data -> R0
+ mov.l r0, @r1 ! CS5BBCR set
+
+ mov.l CS6ABCR_A, r1 ! CS6ABCR address -> R1
+ mov.l CS6ABCR_D, r0 ! CS6ABCR data -> R0
+ mov.l r0, @r1 ! CS6ABCR set
+
+ mov.l CS0WCR_A, r1 ! CS0WCR address -> R1
+ mov.l CS0WCR_D, r0 ! CS0WCR data -> R0
+ mov.l r0, @r1 ! CS0WCR set
+
+ mov.l CS2WCR_A, r1 ! CS2WCR address -> R1
+ mov.l CS2WCR_D, r0 ! CS2WCR data -> R0
+ mov.l r0, @r1 ! CS2WCR set
+
+ mov.l CS4WCR_A, r1 ! CS4WCR address -> R1
+ mov.l CS4WCR_D, r0 ! CS4WCR data -> R0
+ mov.l r0, @r1 ! CS4WCR set
+
+ mov.l CS5AWCR_A, r1 ! CS5AWCR address -> R1
+ mov.l CS5AWCR_D, r0 ! CS5AWCR data -> R0
+ mov.l r0, @r1 ! CS5AWCR set
+
+ mov.l CS5BWCR_A, r1 ! CS5BWCR address -> R1
+ mov.l CS5BWCR_D, r0 ! CS5BWCR data -> R0
+ mov.l r0, @r1 ! CS5BWCR set
+
+ mov.l CS6AWCR_A, r1 ! CS6AWCR address -> R1
+ mov.l CS6AWCR_D, r0 ! CS6AWCR data -> R0
+ mov.l r0, @r1 ! CS6AWCR set
+
+ ! SDRAM initialization
+ mov.l SDCR_A, r1 ! SB_SDCR address -> R1
+ mov.l SDCR_D, r0 ! SB_SDCR data -> R0
+ mov.l r0, @r1 ! SB_SDCR set
+
+ mov.l SDWCR_A, r1 ! SB_SDWCR address -> R1
+ mov.l SDWCR_D, r0 ! SB_SDWCR data -> R0
+ mov.l r0, @r1 ! SB_SDWCR set
+
+ mov.l SDPCR_A, r1 ! SB_SDPCR address -> R1
+ mov.l SDPCR_D, r0 ! SB_SDPCR data -> R0
+ mov.l r0, @r1 ! SB_SDPCR set
+
+ mov.l RTCOR_A, r1 ! SB_RTCOR address -> R1
+ mov.l RTCOR_D, r0 ! SB_RTCOR data -> R0
+ mov.l r0, @r1 ! SB_RTCOR set
+
+ mov.l RTCSR_A, r1 ! SB_RTCSR address -> R1
+ mov.l RTCSR_D, r0 ! SB_RTCSR data -> R0
+ mov.l r0, @r1 ! SB_RTCSR set
+
+ mov.l SDMR3_A, r1 ! SDMR3 address -> R1
+ mov #0x00, r0 ! SDMR3 data -> R0
+ mov.b r0, @r1 ! SDMR3 set
+
+ ! BL bit off (init = ON) (?!?)
+
+ stc sr, r0 ! BL bit off(init=ON)
+ mov.l SR_MASK_D, r1
+ and r1, r0
+ ldc r0, sr
+
+ rts
+ mov #0, r0
+
+ .align 2
+
+CCR_A: .long CCR
+MMUCR_A: .long MMUCR
+MSTPCR0_A: .long MSTPCR0
+MSTPCR2_A: .long MSTPCR2
+SBSCR_A: .long SBSCR
+PSCR_A: .long PSCR
+RWTCSR_A: .long RWTCSR
+RWTCNT_A: .long RWTCNT
+FRQCR_A: .long FRQCR
+
+CCR_D: .long 0x00000800
+CCR_D_2: .long 0x00000103
+MMUCR_D: .long 0x00000004
+MSTPCR0_D: .long 0x00001001
+MSTPCR2_D: .long 0xffffffff
+FRQCR_D: .long 0x07022538
+
+PSELA_A: .long 0xa405014E
+PSELA_D: .word 0x0A10
+ .align 2
+
+DRVCR_A: .long 0xa405018A
+DRVCR_D: .word 0x0554
+ .align 2
+
+PCCR_A: .long 0xa4050104
+PCCR_D: .word 0x8800
+ .align 2
+
+PECR_A: .long 0xa4050108
+PECR_D: .word 0x0000
+ .align 2
+
+PJCR_A: .long 0xa4050110
+PJCR_D: .word 0x1000
+ .align 2
+
+PXCR_A: .long 0xa4050148
+PXCR_D: .word 0x0AAA
+ .align 2
+
+CMNCR_A: .long CMNCR
+CMNCR_D: .long 0x00000013
+CS0BCR_A: .long CS0BCR ! Flash bank 1
+CS0BCR_D: .long 0x24920400
+CS2BCR_A: .long CS2BCR ! SRAM
+CS2BCR_D: .long 0x24920400
+CS4BCR_A: .long CS4BCR ! FPGA, PCMCIA, USB, ext slot
+CS4BCR_D: .long 0x24920400
+CS5ABCR_A: .long CS5ABCR ! Ext slot
+CS5ABCR_D: .long 0x24920400
+CS5BBCR_A: .long CS5BBCR ! USB controller
+CS5BBCR_D: .long 0x24920400
+CS6ABCR_A: .long CS6ABCR ! Ethernet
+CS6ABCR_D: .long 0x24920400
+
+CS0WCR_A: .long CS0WCR
+CS0WCR_D: .long 0x00000300
+CS2WCR_A: .long CS2WCR
+CS2WCR_D: .long 0x00000300
+CS4WCR_A: .long CS4WCR
+CS4WCR_D: .long 0x00000300
+CS5AWCR_A: .long CS5AWCR
+CS5AWCR_D: .long 0x00000300
+CS5BWCR_A: .long CS5BWCR
+CS5BWCR_D: .long 0x00000300
+CS6AWCR_A: .long CS6AWCR
+CS6AWCR_D: .long 0x00000300
+
+SDCR_A: .long SBSC_SDCR
+SDCR_D: .long 0x00020809
+SDWCR_A: .long SBSC_SDWCR
+SDWCR_D: .long 0x00164d0d
+SDPCR_A: .long SBSC_SDPCR
+SDPCR_D: .long 0x00000087
+RTCOR_A: .long SBSC_RTCOR
+RTCOR_D: .long 0xA55A0034
+RTCSR_A: .long SBSC_RTCSR
+RTCSR_D: .long 0xA55A0010
+SDMR3_A: .long 0xFE500180
+
+ .align 1
+
+SBSCR_D: .word 0x0040
+PSCR_D: .word 0x0000
+RWTCSR_D_1: .word 0xA507
+RWTCSR_D_2: .word 0xA507
+RWTCNT_D: .word 0x5A00
+
+SR_MASK_D: .long 0xEFFFFF0F
--- /dev/null
+/*
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * Copyright (C) 2007
+ * Kenati Technologies, Inc.
+ *
+ * board/ms7722se/ms7722se.c
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+#define LED_BASE 0xB0800000
+
+int checkboard(void)
+{
+ puts("BOARD: Hitachi UL MS7722SE\n");
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Setup PTXMD[1:0] for /CS6A */
+ outw(inw(PXCR) & ~0xf000, PXCR);
+
+ return 0;
+}
+
+int dram_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_memstart = CFG_SDRAM_BASE;
+ gd->bd->bi_memsize = CFG_SDRAM_SIZE;
+ printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
+ return 0;
+}
+
+void led_set_state (unsigned short value)
+{
+ *((volatile unsigned short *) LED_BASE) = (value & 0xFF);
+}
--- /dev/null
+/*
+ * Copyrigth (c) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+ /*
+ Base address of internal SDRAM is 0x0C000000.
+ Although size of SDRAM can be either 16 or 32 MBytes,
+ we assume 16 MBytes (ie ignore upper half if the full
+ 32 MBytes is present).
+
+ NOTE: This address must match with the definition of
+ TEXT_BASE in config.mk (in this directory).
+
+ */
+ . = 0x8C000000 + (64*1024*1024) - (256*1024);
+
+ PROVIDE (reloc_dst = .);
+
+ PROVIDE (_ftext = .);
+ PROVIDE (_fcode = .);
+ PROVIDE (_start = .);
+
+ .text :
+ {
+ cpu/sh4/start.o (.text)
+ . = ALIGN(8192);
+ common/environment.o (.ppcenv)
+ . = ALIGN(8192);
+ common/environment.o (.ppcenvr)
+ . = ALIGN(8192);
+ *(.text)
+ . = ALIGN(4);
+ } =0xFF
+ PROVIDE (_ecode = .);
+ .rodata :
+ {
+ *(.rodata)
+ . = ALIGN(4);
+ }
+ PROVIDE (_etext = .);
+
+
+ PROVIDE (_fdata = .);
+ .data :
+ {
+ *(.data)
+ . = ALIGN(4);
+ }
+ PROVIDE (_edata = .);
+
+ PROVIDE (_fgot = .);
+ .got :
+ {
+ *(.got)
+ . = ALIGN(4);
+ }
+ PROVIDE (_egot = .);
+
+ PROVIDE (__u_boot_cmd_start = .);
+ .u_boot_cmd :
+ {
+ *(.u_boot_cmd)
+ . = ALIGN(4);
+ }
+ PROVIDE (__u_boot_cmd_end = .);
+
+ PROVIDE (reloc_dst_end = .);
+ /* _reloc_dst_end = .; */
+
+ PROVIDE (bss_start = .);
+ PROVIDE (__bss_start = .);
+ .bss :
+ {
+ *(.bss)
+ . = ALIGN(4);
+ }
+ PROVIDE (bss_end = .);
+
+ PROVIDE (_end = .);
+}
--- /dev/null
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := ms7750se.o
+SOBJS := lowlevel_init.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#################################################################
--- /dev/null
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+# NOTE: Must match value used in u-boot.lds (in this directory).
+#
+TEXT_BASE = 0x8FFC0000
--- /dev/null
+/*
+ modified from SH-IPL+g
+ Renesaso SuperH / Solution Enginge MS775xSE01 BSC setting.
+
+ Support CPU : SH7750/SH7750S/SH7750R/SH7751/SH7751R
+
+ Coyright (c) 2007 Nobuhiro Iwamatsu <iwmatsu@nigauri.org>
+
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+*/
+
+#include <config.h>
+#include <version.h>
+
+#include <asm/processor.h>
+
+#ifdef CONFIG_CPU_SH7751
+#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */
+#define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */
+#ifdef CONFIG_MARUBUN_PCCARD
+#define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15
+ A3:2 A2:15 A1:15 A0:6 A0B:7 */
+#else /* CONFIG_MARUBUN_PCCARD */
+#define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15
+ A3:2 A2:15 A1:15 A0:6 A0B:7 */
+#endif /* CONFIG_MARUBUN_PCCARD */
+#define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
+ A2: 1-3 A1: 1-3 A0: 0-1 */
+#define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */
+#define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */
+#define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, ... */
+#define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */
+#else /* CONFIG_CPU_SH7751 */
+#define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */
+#define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */
+#define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15
+ A3:2 A2:15 A1:15 A0:15 A0B:7 */
+#define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
+ A2: 1-3 A1: 1-3 A0: 0-1 */
+#define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */
+#define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */
+#define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, ... */
+#define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */
+#endif /* CONFIG_CPU_SH7751 */
+
+ .global lowlevel_init
+ .text
+ .align 2
+
+lowlevel_init:
+
+ mov.l CCR_A, r1 ! CCR Address
+ mov.l CCR_D_DISABLE, r0 ! CCR Data
+ mov.l r0, @r1
+
+init_bsc:
+ mov.l FRQCR_A,r1 /* FRQCR Address */
+ mov.l FRQCR_D,r0 /* FRQCR Data */
+ mov.w r0,@r1
+
+ mov.l BCR1_A,r1 /* BCR1 Address */
+ mov.l BCR1_D,r0 /* BCR1 Data */
+ mov.l r0,@r1
+
+ mov.l BCR2_A,r1 /* BCR2 Address */
+ mov.l BCR2_D,r0 /* BCR2 Data */
+ mov.w r0,@r1
+
+ mov.l WCR1_A,r1 /* WCR1 Address */
+ mov.l WCR1_D,r0 /* WCR1 Data */
+ mov.l r0,@r1
+
+ mov.l WCR2_A,r1 /* WCR2 Address */
+ mov.l WCR2_D,r0 /* WCR2 Data */
+ mov.l r0,@r1
+
+ mov.l WCR3_A,r1 /* WCR3 Address */
+ mov.l WCR3_D,r0 /* WCR3 Data */
+ mov.l r0,@r1
+
+ mov.l MCR_A,r1 /* MCR Address */
+ mov.l MCR_D1,r0 /* MCR Data1 */
+ mov.l r0,@r1
+
+ mov.l SDMR3_A,r1 /* Set SDRAM mode */
+ mov #0,r0
+ mov.b r0,@r1
+
+ ! Do you need PCMCIA setting?
+ ! If so, please add the lines here...
+
+ mov.l RTCNT_A,r1 /* RTCNT Address */
+ mov.l RTCNT_D,r0 /* RTCNT Data */
+ mov.w r0,@r1
+
+ mov.l RTCOR_A,r1 /* RTCOR Address */
+ mov.l RTCOR_D,r0 /* RTCOR Data */
+ mov.w r0,@r1
+
+ mov.l RTCSR_A,r1 /* RTCSR Address */
+ mov.l RTCSR_D,r0 /* RTCSR Data */
+ mov.w r0,@r1
+
+ mov.l RFCR_A,r1 /* RFCR Address */
+ mov.l RFCR_D,r0 /* RFCR Data */
+ mov.w r0,@r1 /* Clear reflesh counter */
+ /* Wait DRAM refresh 30 times */
+ mov #30,r3
+1:
+ mov.w @r1,r0
+ extu.w r0,r2
+ cmp/hi r3,r2
+ bf 1b
+
+ mov.l MCR_A,r1 /* MCR Address */
+ mov.l MCR_D2,r0 /* MCR Data2 */
+ mov.l r0,@r1
+
+ mov.l SDMR3_A,r1 /* Set SDRAM mode */
+ mov #0,r0
+ mov.b r0,@r1
+
+ rts
+ nop
+
+ .align 2
+
+CCR_A: .long CCR
+CCR_D_DISABLE: .long 0x0808
+FRQCR_A: .long FRQCR
+FRQCR_D:
+#ifdef CONFIG_CPU_TYPE_R
+ .long 0x00000e1a /* 12:3:3 */
+#else /* CONFIG_CPU_TYPE_R */
+#ifdef CONFIG_GOOD_SESH4
+ .long 0x00000e13 /* 6:2:1 */
+#else
+ .long 0x00000e23 /* 6:1:1 */
+#endif
+#endif /* CONFIG_CPU_TYPE_R */
+
+BCR1_A: .long BCR1
+BCR1_D: .long 0x00000008 /* Area 3 SDRAM */
+BCR2_A: .long BCR2
+BCR2_D: .long BCR2_D_VALUE /* Bus width settings */
+WCR1_A: .long WCR1
+WCR1_D: .long WCR1_D_VALUE /* Inter-area or turnaround wait states */
+WCR2_A: .long WCR2
+WCR2_D: .long WCR2_D_VALUE /* Per-area access and burst wait states */
+WCR3_A: .long WCR3
+WCR3_D: .long WCR3_D_VALUE /* Address setup and data hold cycles */
+RTCSR_A: .long RTCSR
+RTCSR_D: .long 0xA518 /* RTCSR Write Code A5h Data 18h */
+RTCNT_A: .long RTCNT
+RTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */
+RTCOR_A: .long RTCOR
+RTCOR_D: .long RTCOR_D_VALUE /* Set refresh time (about 15us) */
+SDMR3_A: .long SDMR3_ADDRESS
+MCR_A: .long MCR
+MCR_D1: .long MCR_D1_VALUE
+MCR_D2: .long MCR_D2_VALUE
+RFCR_A: .long RFCR
+RFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */
--- /dev/null
+/*
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+int checkboard(void)
+{
+ puts("BOARD: SH7750/SH7750S/SH7750R Solution Engine\n");
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_memstart = CFG_SDRAM_BASE;
+ gd->bd->bi_memsize = CFG_SDRAM_SIZE;
+ printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
+ return 0;
+}
+
+int board_late_init(void)
+{
+ return 0;
+}
--- /dev/null
+/*
+ * Copyrigth (c) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+ /*
+ Base address of internal SDRAM is 0x0C000000.
+ Although size of SDRAM can be either 16 or 32 MBytes,
+ we assume 16 MBytes (ie ignore upper half if the full
+ 32 MBytes is present).
+
+ NOTE: This address must match with the definition of
+ TEXT_BASE in config.mk (in this directory).
+
+ */
+ . = 0x8C000000 + (64*1024*1024) - (256*1024);
+
+ PROVIDE (reloc_dst = .);
+
+ PROVIDE (_ftext = .);
+ PROVIDE (_fcode = .);
+ PROVIDE (_start = .);
+
+ .text :
+ {
+ cpu/sh4/start.o (.text)
+ . = ALIGN(8192);
+ common/environment.o (.ppcenv)
+ . = ALIGN(8192);
+ common/environment.o (.ppcenvr)
+ . = ALIGN(8192);
+ *(.text)
+ . = ALIGN(4);
+ } =0xFF
+ PROVIDE (_ecode = .);
+ .rodata :
+ {
+ *(.rodata)
+ . = ALIGN(4);
+ }
+ PROVIDE (_etext = .);
+
+
+ PROVIDE (_fdata = .);
+ .data :
+ {
+ *(.data)
+ . = ALIGN(4);
+ }
+ PROVIDE (_edata = .);
+
+ PROVIDE (_fgot = .);
+ .got :
+ {
+ *(.got)
+ . = ALIGN(4);
+ }
+ PROVIDE (_egot = .);
+
+ PROVIDE (__u_boot_cmd_start = .);
+ .u_boot_cmd :
+ {
+ *(.u_boot_cmd)
+ . = ALIGN(4);
+ }
+ PROVIDE (__u_boot_cmd_end = .);
+
+ PROVIDE (reloc_dst_end = .);
+ /* _reloc_dst_end = .; */
+
+ PROVIDE (bss_start = .);
+ PROVIDE (__bss_start = .);
+ .bss :
+ {
+ *(.bss)
+ . = ALIGN(4);
+ }
+ PROVIDE (bss_end = .);
+
+ PROVIDE (_end = .);
+}
void board_add_ram_info(int use_default)
{
- PPC440_SYS_INFO board_cfg;
+ PPC4xx_SYS_INFO board_cfg;
u32 val;
mfsdram(DDR0_22, val);
val &= DDR0_22_CTRL_RAW_MASK;
int board_early_init_f (void)
{
#if defined(CONFIG_PCI)
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
- volatile ccsr_pcix_t *pci = &immr->im_pcix;
+ volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
pci->peer &= 0xffffffdf; /* disable master abort */
#endif
{
long dram_size = 0;
extern long spd_sdram (void);
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
puts("Initializing\n");
#if defined(CONFIG_DDR_DLL)
{
- volatile ccsr_gur_t *gur= &immap->im_gur;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
int i,x;
x = 10;
void
local_bus_init(void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
- volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
uint clkdiv;
uint lbc_hz;
long int fixed_sdram (void)
{
#ifndef CFG_RAMBOOT
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+ volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
ddr->cs0_config = CFG_DDR_CS0_CONFIG;
{
long dram_size = 0;
extern long spd_sdram (void);
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
puts("Initializing\n");
#if defined(CONFIG_DDR_DLL)
{
- volatile ccsr_gur_t *gur= &immap->im_gur;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
int i,x;
x = 10;
void
local_bus_init(void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
- volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
uint clkdiv;
uint lbc_hz;
long int fixed_sdram (void)
{
#ifndef CFG_RAMBOOT
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+ volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
ddr->cs0_config = CFG_DDR_CS0_CONFIG;
cpu/ppc4xx/start.o (.text)
board/prodrive/alpr/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
-/* . = env_offset;*/
-/* common/environment.o(.text)*/
*(.text)
*(.fixup)
cpu/ppc4xx/start.o (.text)
board/prodrive/p3p440/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
-/* . = env_offset;*/
-/* common/environment.o(.text)*/
*(.text)
*(.fixup)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
cpu/ppc4xx/4xx_enet.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
cpu/ppc4xx/4xx_enet.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
cpu/ppc4xx/4xx_enet.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
cpu/ppc4xx/4xx_enet.o (.text)
cpu/ppc4xx/start.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
cpu/ppc4xx/4xx_enet.o (.text)
int board_early_init_f (void)
{
#if defined(CONFIG_PCI)
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
- volatile ccsr_pcix_t *pci = &immr->im_pcix;
+ volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
pci->peer &= 0xfffffffdf; /* disable master abort */
#endif
{
long dram_size = 0;
extern long spd_sdram (void);
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
#if 0
#if !defined(CONFIG_RAM_AS_FLASH)
- volatile ccsr_lbc_t *lbc= &immap->im_lbc;
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
sys_info_t sysinfo;
uint temp_lbcdll = 0;
#endif
#endif /* 0 */
#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
- volatile ccsr_gur_t *gur= &immap->im_gur;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
#endif
#if defined(CONFIG_DDR_DLL)
uint temp_ddrdll = 0;
* enable errors */
uint *p = 0;
uint i = 0;
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+ volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
dma_init();
for (*p = 0; p < (uint *)(8 * 1024); p++) {
if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
#define CFG_DDR_CONTROL 0xc2000000
#ifndef CFG_RAMBOOT
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+ volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
ddr->cs0_bnds = 0x00000007;
ddr->cs1_bnds = 0x0010001f;
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
board_early_init_f(void)
{
#if defined(CONFIG_PCI)
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
- volatile ccsr_pcix_t *pci = &immr->im_pcix;
+ volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
pci->peer &= 0xfffffffdf; /* disable master abort */
#endif
{
long dram_size = 0;
extern long spd_sdram (void);
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
#if defined(CONFIG_DDR_DLL)
{
- volatile ccsr_gur_t *gur= &immap->im_gur;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
uint temp_ddrdll = 0;
/* Work around to stabilize DDR DLL */
board_early_init_f(void)
{
#if defined(CONFIG_PCI)
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
- volatile ccsr_pcix_t *pci = &immr->im_pcix;
+ volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
pci->peer &= 0xffffffdf; /* disable master abort */
#endif
#if defined(CONFIG_DDR_DLL)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_gur_t *gur= &immap->im_gur;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
uint temp_ddrdll = 0;
/* Work around to stabilize DDR DLL */
long int sdram_setup(int casl)
{
int i;
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
- volatile ccsr_ddr_t *ddr = &immap->im_ddr;
+ volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR);
unsigned long cfg_ddr_timing1;
unsigned long cfg_ddr_mode;
* This DLL-Override only used on TQM8540 and TQM8560
*/
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
- volatile ccsr_gur_t *gur= &immap->im_gur;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
int i,x;
x = 10;
int misc_init_r (void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_lbc_t *memctl = &immap->im_lbc;
+ volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
/*
* Adjust flash start and offset to detected values
*/
void local_bus_init (void)
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
- volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
uint clkdiv;
uint lbc_hz;
DECLARE_GLOBAL_DATA_PTR;
+#if !defined(CFG_FLASH_CFI_DRIVER) /* do not use if CFI driver is configured */
+
#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
&& !defined(CONFIG_TQM885D)
# ifndef CFG_OR_TIMING_FLASH_AT_50MHZ
/*-----------------------------------------------------------------------
*/
+
+#endif /* !defined(CFG_FLASH_CFI_DRIVER) */
#define _NOT_USED_ 0xFFFFFFFF
+/* UPM initialization table for SDRAM: 40, 50, 66 MHz CLKOUT @ CAS latency 2, tWR=2 */
const uint sdram_table[] =
{
/*
/*
* Single Write. (Offset 18 in UPMA RAM)
*/
- 0x1F0DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ 0x1F0DFC04, 0xEEABBC00, 0x11B77C04, 0xEFFAFC44,
+ 0x1FF5FC47, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Write. (Offset 20 in UPMA RAM)
*/
0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
- 0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */
- _NOT_USED_,
+ 0xF0AFFC00, 0xF0AFFC04, 0xE1BAFC44, 0x1FF5FC47, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
/*
* Exception. (Offset 3c in UPMA RAM)
*/
- 0x7FFFFC07, /* last */
+ 0xFFFFFC07, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_,
};
#ifndef CONFIG_CAN_DRIVER
if ((board_type != 'L') &&
(board_type != 'M') &&
- (board_type != 'D') ) { /* "L" and "M" type boards have only one bank SDRAM */
+ (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */
memctl->memc_or3 = CFG_OR3_PRELIM;
memctl->memc_br3 = CFG_BR3_PRELIM;
}
#ifndef CONFIG_CAN_DRIVER
if ((board_type != 'L') &&
(board_type != 'M') &&
- (board_type != 'D') ) { /* "L" and "M" type boards have only one bank SDRAM */
+ (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */
/*
* Check Bank 1 Memory Size
* use current column settings
mkdir -p ${obj}include
variant=PB926EJ-S
-if [ "$1" == "" ]
+if [ "$1" = "" ]
then
echo "$0:: No parameters - using versatilepb_config"
echo "#define CONFIG_ARCH_VERSATILE_PB" > ${obj}include/config.h
get_PCI_freq(void)
{
ulong val;
- PPC405_SYS_INFO sys_info;
+ PPC4xx_SYS_INFO sys_info;
get_sys_info(&sys_info);
val = sys_info.freqPCI;
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
cpu/ppc4xx/4xx_enet.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
COBJS-$(CONFIG_CMD_EXT2) += cmd_ext2.o
COBJS-$(CONFIG_CMD_FAT) += cmd_fat.o
COBJS-y += cmd_fdc.o
-COBJS-$(CONFIG_OF_LIBFDT) += cmd_fdt.o
+COBJS-$(CONFIG_OF_LIBFDT) += cmd_fdt.o fdt_support.o
COBJS-$(CONFIG_CMD_FDOS) += cmd_fdos.o
COBJS-$(CONFIG_CMD_FLASH) += cmd_flash.o
ifdef CONFIG_FPGA
COBJS-y += env_nvram.o
COBJS-y += env_nowhere.o
COBJS-y += exports.o
-COBJS-y += fdt_support.o
COBJS-y += flash.o
COBJS-y += fpga.o
COBJS-y += ft_build.o
if (hdr->ih_arch != IH_CPU_NIOS2)
#elif defined(__PPC__)
if (hdr->ih_arch != IH_CPU_PPC)
+#elif defined(__sh__)
+ if (hdr->ih_arch != IH_CPU_SH)
#else
# error Unknown CPU type
#endif
printf("%s %s\n", pathp, prop);
return 0;
} else if (len > 0) {
- printf("%s=", prop);
+ printf("%s = ", prop);
print_data (nodep, len);
printf("\n");
return 0;
pathp);
} else {
if (level <= depth) {
- printf("%s%s=",
+ printf("%s%s = ",
&tabs[MAX_LEVEL - level],
pathp);
print_data (nodep, len);
#endif /* __LITTLE_ENDIAN || CONFIG_AU1X00 */
-#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA)
+#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA) || defined(CONFIG_SH)
static void
output_data(int dev, ulong *sect_buf, int words)
{
}
#endif /* __PPC__ */
-#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA)
+#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA) || defined(CONFIG_SH)
static void
input_data(int dev, ulong *sect_buf, int words)
{
#include <common.h>
#include <linux/ctype.h>
#include <linux/types.h>
-
-#ifdef CONFIG_OF_LIBFDT
-
#include <asm/global_data.h>
#include <fdt.h>
#include <libfdt.h>
#include <fdt_support.h>
+#include <exports.h>
/*
* Global data (for the gd->bd)
return fdt_setprop(fdt, nodeoff, prop, val, len);
}
+#ifdef CONFIG_OF_STDOUT_VIA_ALIAS
+static int fdt_fixup_stdout(void *fdt, int choosenoff)
+{
+ int err = 0;
+#ifdef CONFIG_CONS_INDEX
+ int node;
+ char sername[9] = { 0 };
+ const char *path;
+
+ sprintf(sername, "serial%d", CONFIG_CONS_INDEX - 1);
+
+ err = node = fdt_path_offset(fdt, "/aliases");
+ if (node >= 0) {
+ int len;
+ path = fdt_getprop(fdt, node, sername, &len);
+ if (path) {
+ char *p = malloc(len);
+ err = -FDT_ERR_NOSPACE;
+ if (p) {
+ memcpy(p, path, len);
+ err = fdt_setprop(fdt, choosenoff,
+ "linux,stdout-path", p, len);
+ free(p);
+ }
+ } else {
+ err = len;
+ }
+ }
+#endif
+ if (err < 0)
+ printf("WARNING: could not set linux,stdout-path %s.\n",
+ fdt_strerror(err));
+
+ return err;
+}
+#endif
+
int fdt_chosen(void *fdt, ulong initrd_start, ulong initrd_end, int force)
{
int nodeoffset;
printf("WARNING: could not set linux,initrd-end %s.\n",
fdt_strerror(err));
}
+
+#ifdef CONFIG_OF_STDOUT_VIA_ALIAS
+ err = fdt_fixup_stdout(fdt, nodeoffset);
+#endif
+
#ifdef OF_STDOUT_PATH
err = fdt_setprop(fdt, nodeoffset,
"linux,stdout-path", OF_STDOUT_PATH, strlen(OF_STDOUT_PATH)+1);
do_fixup_by_compat(fdt, compat, prop, &val, 4, create);
}
+int fdt_fixup_memory(void *blob, u64 start, u64 size)
+{
+ int err, nodeoffset, len = 0;
+ u8 tmp[16];
+ const u32 *addrcell, *sizecell;
+
+ err = fdt_check_header(blob);
+ if (err < 0) {
+ printf("%s: %s\n", __FUNCTION__, fdt_strerror(err));
+ return err;
+ }
+
+ /* update, or add and update /memory node */
+ nodeoffset = fdt_path_offset(blob, "/memory");
+ if (nodeoffset < 0) {
+ nodeoffset = fdt_add_subnode(blob, 0, "memory");
+ if (nodeoffset < 0)
+ printf("WARNING: could not create /memory: %s.\n",
+ fdt_strerror(nodeoffset));
+ return nodeoffset;
+ }
+ err = fdt_setprop(blob, nodeoffset, "device_type", "memory",
+ sizeof("memory"));
+ if (err < 0) {
+ printf("WARNING: could not set %s %s.\n", "device_type",
+ fdt_strerror(err));
+ return err;
+ }
+
+ addrcell = fdt_getprop(blob, 0, "#address-cells", NULL);
+ /* use shifts and mask to ensure endianness */
+ if ((addrcell) && (*addrcell == 2)) {
+ tmp[0] = (start >> 56) & 0xff;
+ tmp[1] = (start >> 48) & 0xff;
+ tmp[2] = (start >> 40) & 0xff;
+ tmp[3] = (start >> 32) & 0xff;
+ tmp[4] = (start >> 24) & 0xff;
+ tmp[5] = (start >> 16) & 0xff;
+ tmp[6] = (start >> 8) & 0xff;
+ tmp[7] = (start ) & 0xff;
+ len = 8;
+ } else {
+ tmp[0] = (start >> 24) & 0xff;
+ tmp[1] = (start >> 16) & 0xff;
+ tmp[2] = (start >> 8) & 0xff;
+ tmp[3] = (start ) & 0xff;
+ len = 4;
+ }
+
+ sizecell = fdt_getprop(blob, 0, "#size-cells", NULL);
+ /* use shifts and mask to ensure endianness */
+ if ((sizecell) && (*sizecell == 2)) {
+ tmp[0+len] = (size >> 56) & 0xff;
+ tmp[1+len] = (size >> 48) & 0xff;
+ tmp[2+len] = (size >> 40) & 0xff;
+ tmp[3+len] = (size >> 32) & 0xff;
+ tmp[4+len] = (size >> 24) & 0xff;
+ tmp[5+len] = (size >> 16) & 0xff;
+ tmp[6+len] = (size >> 8) & 0xff;
+ tmp[7+len] = (size ) & 0xff;
+ len += 8;
+ } else {
+ tmp[0+len] = (size >> 24) & 0xff;
+ tmp[1+len] = (size >> 16) & 0xff;
+ tmp[2+len] = (size >> 8) & 0xff;
+ tmp[3+len] = (size ) & 0xff;
+ len += 4;
+ }
+
+ err = fdt_setprop(blob, nodeoffset, "reg", tmp, len);
+ if (err < 0) {
+ printf("WARNING: could not set %s %s.\n",
+ "reg", fdt_strerror(err));
+ return err;
+ }
+ return 0;
+}
+
+#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
+ defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
+
void fdt_fixup_ethernet(void *fdt, bd_t *bd)
{
int node;
#endif
}
}
-
-#endif /* CONFIG_OF_LIBFDT */
+#endif
|| defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
return &serial_scc_device;
#elif defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
- || defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_MPC5xxx)
+ || defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) \
+ || defined(CONFIG_MPC5xxx)
#if defined(CONFIG_CONS_INDEX) && defined(CFG_NS16550_SERIAL)
#if (CONFIG_CONS_INDEX==1)
return &eserial1_device;
#endif
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
- || defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_MPC5xxx)
+ || defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) \
+ || defined(CONFIG_MPC5xxx)
serial_register(&serial0_device);
serial_register(&serial1_device);
#endif
#include <usb.h>
#ifdef CONFIG_4xx
-#include <405gp_pci.h>
+#include <asm/4xx_pci.h>
#endif
#undef USB_DEBUG
+++ /dev/null
-#
-# Copyright (C) 2005-2006 Atmel Corporation
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB := $(obj)lib$(SOC).a
-
-COBJS := gpio.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all: $(obj).depend $(LIB)
-
-$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $^
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-/*
- * Copyright (C) 2006 Atmel Corporation
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-
-#include <asm/arch/gpio.h>
-
-/*
- * Lots of small functions here. We depend on --gc-sections getting
- * rid of the ones we don't need.
- */
-void gpio_enable_ebi(void)
-{
-#ifdef CFG_HSDRAMC
-#ifndef CFG_SDRAM_16BIT
- gpio_select_periph_A(GPIO_PIN_PE0, 0);
- gpio_select_periph_A(GPIO_PIN_PE1, 0);
- gpio_select_periph_A(GPIO_PIN_PE2, 0);
- gpio_select_periph_A(GPIO_PIN_PE3, 0);
- gpio_select_periph_A(GPIO_PIN_PE4, 0);
- gpio_select_periph_A(GPIO_PIN_PE5, 0);
- gpio_select_periph_A(GPIO_PIN_PE6, 0);
- gpio_select_periph_A(GPIO_PIN_PE7, 0);
- gpio_select_periph_A(GPIO_PIN_PE8, 0);
- gpio_select_periph_A(GPIO_PIN_PE9, 0);
- gpio_select_periph_A(GPIO_PIN_PE10, 0);
- gpio_select_periph_A(GPIO_PIN_PE11, 0);
- gpio_select_periph_A(GPIO_PIN_PE12, 0);
- gpio_select_periph_A(GPIO_PIN_PE13, 0);
- gpio_select_periph_A(GPIO_PIN_PE14, 0);
- gpio_select_periph_A(GPIO_PIN_PE15, 0);
-#endif
- gpio_select_periph_A(GPIO_PIN_PE26, 0);
-#endif
-}
-
-void gpio_enable_usart0(void)
-{
- gpio_select_periph_B(GPIO_PIN_PA8, 0);
- gpio_select_periph_B(GPIO_PIN_PA9, 0);
-}
-
-void gpio_enable_usart1(void)
-{
- gpio_select_periph_A(GPIO_PIN_PA17, 0);
- gpio_select_periph_A(GPIO_PIN_PA18, 0);
-}
-
-void gpio_enable_usart2(void)
-{
- gpio_select_periph_B(GPIO_PIN_PB26, 0);
- gpio_select_periph_B(GPIO_PIN_PB27, 0);
-}
-
-void gpio_enable_usart3(void)
-{
- gpio_select_periph_B(GPIO_PIN_PB18, 0);
- gpio_select_periph_B(GPIO_PIN_PB19, 0);
-}
-
-void gpio_enable_macb0(void)
-{
- gpio_select_periph_A(GPIO_PIN_PC3, 0); /* TXD0 */
- gpio_select_periph_A(GPIO_PIN_PC4, 0); /* TXD1 */
- gpio_select_periph_A(GPIO_PIN_PC7, 0); /* TXEN */
- gpio_select_periph_A(GPIO_PIN_PC8, 0); /* TXCK */
- gpio_select_periph_A(GPIO_PIN_PC9, 0); /* RXD0 */
- gpio_select_periph_A(GPIO_PIN_PC10, 0); /* RXD1 */
- gpio_select_periph_A(GPIO_PIN_PC13, 0); /* RXER */
- gpio_select_periph_A(GPIO_PIN_PC15, 0); /* RXDV */
- gpio_select_periph_A(GPIO_PIN_PC16, 0); /* MDC */
- gpio_select_periph_A(GPIO_PIN_PC17, 0); /* MDIO */
-#if !defined(CONFIG_RMII)
- gpio_select_periph_A(GPIO_PIN_PC0, 0); /* COL */
- gpio_select_periph_A(GPIO_PIN_PC1, 0); /* CRS */
- gpio_select_periph_A(GPIO_PIN_PC2, 0); /* TXER */
- gpio_select_periph_A(GPIO_PIN_PC5, 0); /* TXD2 */
- gpio_select_periph_A(GPIO_PIN_PC6, 0); /* TXD3 */
- gpio_select_periph_A(GPIO_PIN_PC11, 0); /* RXD2 */
- gpio_select_periph_A(GPIO_PIN_PC12, 0); /* RXD3 */
- gpio_select_periph_A(GPIO_PIN_PC14, 0); /* RXCK */
- gpio_select_periph_A(GPIO_PIN_PC18, 0); /* SPD */
-#endif
-}
-
-void gpio_enable_macb1(void)
-{
- gpio_select_periph_B(GPIO_PIN_PD13, 0); /* TXD0 */
- gpio_select_periph_B(GPIO_PIN_PD14, 0); /* TXD1 */
- gpio_select_periph_B(GPIO_PIN_PD11, 0); /* TXEN */
- gpio_select_periph_B(GPIO_PIN_PD12, 0); /* TXCK */
- gpio_select_periph_B(GPIO_PIN_PD10, 0); /* RXD0 */
- gpio_select_periph_B(GPIO_PIN_PD6, 0); /* RXD1 */
- gpio_select_periph_B(GPIO_PIN_PD5, 0); /* RXER */
- gpio_select_periph_B(GPIO_PIN_PD4, 0); /* RXDV */
- gpio_select_periph_B(GPIO_PIN_PD3, 0); /* MDC */
- gpio_select_periph_B(GPIO_PIN_PD2, 0); /* MDIO */
-#if !defined(CONFIG_RMII)
- gpio_select_periph_B(GPIO_PIN_PC19, 0); /* COL */
- gpio_select_periph_B(GPIO_PIN_PC23, 0); /* CRS */
- gpio_select_periph_B(GPIO_PIN_PC26, 0); /* TXER */
- gpio_select_periph_B(GPIO_PIN_PC27, 0); /* TXD2 */
- gpio_select_periph_B(GPIO_PIN_PC28, 0); /* TXD3 */
- gpio_select_periph_B(GPIO_PIN_PC29, 0); /* RXD2 */
- gpio_select_periph_B(GPIO_PIN_PC30, 0); /* RXD3 */
- gpio_select_periph_B(GPIO_PIN_PC24, 0); /* RXCK */
- gpio_select_periph_B(GPIO_PIN_PD15, 0); /* SPD */
-#endif
-}
-
-void gpio_enable_mmci(void)
-{
- gpio_select_periph_A(GPIO_PIN_PA10, 0); /* CLK */
- gpio_select_periph_A(GPIO_PIN_PA11, 0); /* CMD */
- gpio_select_periph_A(GPIO_PIN_PA12, 0); /* DATA0 */
- gpio_select_periph_A(GPIO_PIN_PA13, 0); /* DATA1 */
- gpio_select_periph_A(GPIO_PIN_PA14, 0); /* DATA2 */
- gpio_select_periph_A(GPIO_PIN_PA15, 0); /* DATA3 */
-}
--- /dev/null
+#
+# Copyright (C) 2005-2006 Atmel Corporation
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB := $(obj)lib$(SOC).a
+
+COBJS := gpio.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $^
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/arch/chip-features.h>
+#include <asm/arch/gpio.h>
+
+/*
+ * Lots of small functions here. We depend on --gc-sections getting
+ * rid of the ones we don't need.
+ */
+void gpio_enable_ebi(void)
+{
+#ifdef CFG_HSDRAMC
+#ifndef CFG_SDRAM_16BIT
+ gpio_select_periph_A(GPIO_PIN_PE0, 0);
+ gpio_select_periph_A(GPIO_PIN_PE1, 0);
+ gpio_select_periph_A(GPIO_PIN_PE2, 0);
+ gpio_select_periph_A(GPIO_PIN_PE3, 0);
+ gpio_select_periph_A(GPIO_PIN_PE4, 0);
+ gpio_select_periph_A(GPIO_PIN_PE5, 0);
+ gpio_select_periph_A(GPIO_PIN_PE6, 0);
+ gpio_select_periph_A(GPIO_PIN_PE7, 0);
+ gpio_select_periph_A(GPIO_PIN_PE8, 0);
+ gpio_select_periph_A(GPIO_PIN_PE9, 0);
+ gpio_select_periph_A(GPIO_PIN_PE10, 0);
+ gpio_select_periph_A(GPIO_PIN_PE11, 0);
+ gpio_select_periph_A(GPIO_PIN_PE12, 0);
+ gpio_select_periph_A(GPIO_PIN_PE13, 0);
+ gpio_select_periph_A(GPIO_PIN_PE14, 0);
+ gpio_select_periph_A(GPIO_PIN_PE15, 0);
+#endif
+ gpio_select_periph_A(GPIO_PIN_PE26, 0);
+#endif
+}
+
+#ifdef AT32AP700x_CHIP_HAS_USART
+void gpio_enable_usart0(void)
+{
+ gpio_select_periph_B(GPIO_PIN_PA8, 0);
+ gpio_select_periph_B(GPIO_PIN_PA9, 0);
+}
+
+void gpio_enable_usart1(void)
+{
+ gpio_select_periph_A(GPIO_PIN_PA17, 0);
+ gpio_select_periph_A(GPIO_PIN_PA18, 0);
+}
+
+void gpio_enable_usart2(void)
+{
+ gpio_select_periph_B(GPIO_PIN_PB26, 0);
+ gpio_select_periph_B(GPIO_PIN_PB27, 0);
+}
+
+void gpio_enable_usart3(void)
+{
+ gpio_select_periph_B(GPIO_PIN_PB17, 0);
+ gpio_select_periph_B(GPIO_PIN_PB18, 0);
+}
+#endif
+
+#ifdef AT32AP700x_CHIP_HAS_MACB
+void gpio_enable_macb0(void)
+{
+ gpio_select_periph_A(GPIO_PIN_PC3, 0); /* TXD0 */
+ gpio_select_periph_A(GPIO_PIN_PC4, 0); /* TXD1 */
+ gpio_select_periph_A(GPIO_PIN_PC7, 0); /* TXEN */
+ gpio_select_periph_A(GPIO_PIN_PC8, 0); /* TXCK */
+ gpio_select_periph_A(GPIO_PIN_PC9, 0); /* RXD0 */
+ gpio_select_periph_A(GPIO_PIN_PC10, 0); /* RXD1 */
+ gpio_select_periph_A(GPIO_PIN_PC13, 0); /* RXER */
+ gpio_select_periph_A(GPIO_PIN_PC15, 0); /* RXDV */
+ gpio_select_periph_A(GPIO_PIN_PC16, 0); /* MDC */
+ gpio_select_periph_A(GPIO_PIN_PC17, 0); /* MDIO */
+#if !defined(CONFIG_RMII)
+ gpio_select_periph_A(GPIO_PIN_PC0, 0); /* COL */
+ gpio_select_periph_A(GPIO_PIN_PC1, 0); /* CRS */
+ gpio_select_periph_A(GPIO_PIN_PC2, 0); /* TXER */
+ gpio_select_periph_A(GPIO_PIN_PC5, 0); /* TXD2 */
+ gpio_select_periph_A(GPIO_PIN_PC6, 0); /* TXD3 */
+ gpio_select_periph_A(GPIO_PIN_PC11, 0); /* RXD2 */
+ gpio_select_periph_A(GPIO_PIN_PC12, 0); /* RXD3 */
+ gpio_select_periph_A(GPIO_PIN_PC14, 0); /* RXCK */
+ gpio_select_periph_A(GPIO_PIN_PC18, 0); /* SPD */
+#endif
+}
+
+void gpio_enable_macb1(void)
+{
+ gpio_select_periph_B(GPIO_PIN_PD13, 0); /* TXD0 */
+ gpio_select_periph_B(GPIO_PIN_PD14, 0); /* TXD1 */
+ gpio_select_periph_B(GPIO_PIN_PD11, 0); /* TXEN */
+ gpio_select_periph_B(GPIO_PIN_PD12, 0); /* TXCK */
+ gpio_select_periph_B(GPIO_PIN_PD10, 0); /* RXD0 */
+ gpio_select_periph_B(GPIO_PIN_PD6, 0); /* RXD1 */
+ gpio_select_periph_B(GPIO_PIN_PD5, 0); /* RXER */
+ gpio_select_periph_B(GPIO_PIN_PD4, 0); /* RXDV */
+ gpio_select_periph_B(GPIO_PIN_PD3, 0); /* MDC */
+ gpio_select_periph_B(GPIO_PIN_PD2, 0); /* MDIO */
+#if !defined(CONFIG_RMII)
+ gpio_select_periph_B(GPIO_PIN_PC19, 0); /* COL */
+ gpio_select_periph_B(GPIO_PIN_PC23, 0); /* CRS */
+ gpio_select_periph_B(GPIO_PIN_PC26, 0); /* TXER */
+ gpio_select_periph_B(GPIO_PIN_PC27, 0); /* TXD2 */
+ gpio_select_periph_B(GPIO_PIN_PC28, 0); /* TXD3 */
+ gpio_select_periph_B(GPIO_PIN_PC29, 0); /* RXD2 */
+ gpio_select_periph_B(GPIO_PIN_PC30, 0); /* RXD3 */
+ gpio_select_periph_B(GPIO_PIN_PC24, 0); /* RXCK */
+ gpio_select_periph_B(GPIO_PIN_PD15, 0); /* SPD */
+#endif
+}
+#endif
+
+#ifdef AT32AP700x_CHIP_HAS_MMCI
+void gpio_enable_mmci(void)
+{
+ gpio_select_periph_A(GPIO_PIN_PA10, 0); /* CLK */
+ gpio_select_periph_A(GPIO_PIN_PA11, 0); /* CMD */
+ gpio_select_periph_A(GPIO_PIN_PA12, 0); /* DATA0 */
+ gpio_select_periph_A(GPIO_PIN_PA13, 0); /* DATA1 */
+ gpio_select_periph_A(GPIO_PIN_PA14, 0); /* DATA2 */
+ gpio_select_periph_A(GPIO_PIN_PA15, 0); /* DATA3 */
+}
+#endif
/* Put the device into Transfer state */
ret = mmc_cmd(MMC_CMD_SELECT_CARD, mmc_rca << 16, resp, R1 | NCR);
- if (ret) goto fail;
+ if (ret) goto out;
/* Set block length */
ret = mmc_cmd(MMC_CMD_SET_BLOCKLEN, mmc_blkdev.blksz, resp, R1 | NCR);
- if (ret) goto fail;
+ if (ret) goto out;
pr_debug("MCI_DTOR = %08lx\n", mmci_readl(DTOR));
start * mmc_blkdev.blksz, resp,
(R1 | NCR | TRCMD_START | TRDIR_READ
| TRTYP_BLOCK));
- if (ret) goto fail;
+ if (ret) goto out;
ret = -EIO;
wordcount = 0;
do {
status = mmci_readl(SR);
if (status & (ERROR_FLAGS | MMCI_BIT(OVRE)))
- goto fail;
+ goto read_error;
} while (!(status & MMCI_BIT(RXRDY)));
if (status & MMCI_BIT(RXRDY)) {
mmc_cmd(MMC_CMD_SELECT_CARD, 0, resp, NCR);
return i;
-fail:
+read_error:
mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR);
- printf("mmc: bread failed, card status = %08x\n", card_status);
+ printf("mmc: bread failed, status = %08x, card status = %08x\n",
+ status, card_status);
goto out;
}
#include <ft_build.h>
#elif defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
+#include <fdt_support.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
int nodeoffset;
int err;
int j;
- int tmp[2];
for (j = 0; j < (sizeof(fixup_props) / sizeof(fixup_props[0])); j++) {
nodeoffset = fdt_path_offset(blob, fixup_props[j].node);
}
}
- /* update, or add and update /memory node */
- nodeoffset = fdt_path_offset(blob, "/memory");
- if (nodeoffset < 0) {
- nodeoffset = fdt_add_subnode(blob, 0, "memory");
- if (nodeoffset < 0)
- debug("failed to add /memory node: %s\n",
- fdt_strerror(nodeoffset));
- }
- if (nodeoffset >= 0) {
- fdt_setprop(blob, nodeoffset, "device_type",
- "memory", sizeof("memory"));
- tmp[0] = cpu_to_be32(bd->bi_memstart);
- tmp[1] = cpu_to_be32(bd->bi_memsize);
- fdt_setprop(blob, nodeoffset, "reg", tmp, sizeof(tmp));
- }
+ fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
}
#elif defined(CONFIG_OF_FLAT_TREE)
void
LIB = $(obj)lib$(CPU).a
START = start.o resetvec.o
+COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \
- pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o qe_io.o
+ pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o qe_io.o \
+ $(COBJS-y)
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
void
m8560_cpm_reset(void)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
volatile ulong count;
gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
/*
* Reset CPM
*/
- immr->im_cpm.im_cpm_cp.cpcr = CPM_CR_RST;
+ cpm->im_cpm_cp.cpcr = CPM_CR_RST;
count = 0;
do { /* Spin until command processed */
__asm__ __volatile__ ("eieio");
- } while ((immr->im_cpm.im_cpm_cp.cpcr & CPM_CR_FLG) && ++count < 1000000);
+ } while ((cpm->im_cpm_cp.cpcr & CPM_CR_FLG) && ++count < 1000000);
}
/* Allocate some memory from the dual ported ram.
uint
m8560_cpm_dpalloc(uint size, uint align)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
uint retloc;
uint align_mask, off;
uint savebase;
retloc = gd->dp_alloc_base;
gd->dp_alloc_base += size;
- memset((void *)&(immr->im_cpm.im_dprambase[retloc]), 0, size);
+ memset((void *)&(cpm->im_dprambase[retloc]), 0, size);
return(retloc);
}
void
m8560_cpm_setbrg(uint brg, uint rate)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
volatile uint *bp;
/* This is good enough to get SMCs running.....
*/
if (brg < 4) {
- bp = (uint *)&(immr->im_cpm.im_cpm_brg1.brgc1);
+ bp = (uint *)&(cpm->im_cpm_brg1.brgc1);
}
else {
- bp = (uint *)&(immr->im_cpm.im_cpm_brg2.brgc5);
+ bp = (uint *)&(cpm->im_cpm_brg2.brgc5);
brg -= 4;
}
bp += brg;
void
m8560_cpm_fastbrg(uint brg, uint rate, int div16)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
volatile uint *bp;
/* This is good enough to get SMCs running.....
*/
if (brg < 4) {
- bp = (uint *)&(immr->im_cpm.im_cpm_brg1.brgc1);
+ bp = (uint *)&(cpm->im_cpm_brg1.brgc1);
}
else {
- bp = (uint *)&(immr->im_cpm.im_cpm_brg2.brgc5);
+ bp = (uint *)&(cpm->im_cpm_brg2.brgc5);
brg -= 4;
}
bp += brg;
void
m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
volatile uint *bp;
if (brg < 4) {
- bp = (uint *)&(immr->im_cpm.im_cpm_brg1.brgc1);
+ bp = (uint *)&(cpm->im_cpm_brg1.brgc1);
}
else {
- bp = (uint *)&(immr->im_cpm.im_cpm_brg2.brgc5);
+ bp = (uint *)&(cpm->im_cpm_brg2.brgc5);
brg -= 4;
}
bp += brg;
#include <command.h>
#include <asm/cache.h>
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#endif
-
-
int checkcpu (void)
{
sys_info_t sysinfo;
uint fam;
uint ver;
uint major, minor;
+ u32 ddr_ratio;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
svr = get_svr();
ver = SVR_VER(svr);
puts("Clock Configuration:\n");
printf(" CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
printf("CCB:%4lu MHz,\n", sysinfo.freqSystemBus / 1000000);
- printf(" DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
+
+ ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
+ switch (ddr_ratio) {
+ case 0x0:
+ printf(" DDR:%4lu MHz, ", sysinfo.freqDDRBus / 2000000);
+ break;
+ case 0x7:
+ printf(" DDR:%4lu MHz (Synchronous), ", sysinfo.freqDDRBus / 2000000);
+ break;
+ default:
+ printf(" DDR:%4lu MHz (Asynchronous), ", sysinfo.freqDDRBus / 2000000);
+ break;
+ }
#if defined(CFG_LBC_LCRR)
lcrr = CFG_LBC_LCRR;
#else
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_lbc_t *lbc= &immap->im_lbc;
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
lcrr = lbc->lcrr;
}
#if defined(CONFIG_DDR_ECC)
void dma_init(void) {
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_dma_t *dma = &immap->im_dma;
+ volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
dma->satr0 = 0x02c40000;
dma->datr0 = 0x02c40000;
}
uint dma_check(void) {
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_dma_t *dma = &immap->im_dma;
+ volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
volatile uint status = dma->sr0;
/* While the channel is busy, spin */
}
int dma_xfer(void *dest, uint count, void *src) {
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_dma_t *dma = &immap->im_dma;
+ volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
dma->dar0 = (uint) dest;
dma->sar0 = (uint) src;
return dma_check();
}
#endif
-
-
-#ifdef CONFIG_OF_FLAT_TREE
-void
-ft_cpu_setup(void *blob, bd_t *bd)
-{
- u32 *p;
- ulong clock;
- int len;
-
- clock = bd->bi_busfreq;
- p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
- if (p != NULL)
- *p = cpu_to_be32(clock);
-
- p = ft_get_prop(blob, "/qe@e0080000/" OF_CPU "/bus-frequency", &len);
- if (p != NULL)
- *p = cpu_to_be32(clock);
-
- p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
- if (p != NULL)
- *p = cpu_to_be32(clock);
-
- p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
- if (p != NULL)
- *p = cpu_to_be32(clock);
-
-#if defined(CONFIG_HAS_ETH0)
- p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
- if (p)
- memcpy(p, bd->bi_enetaddr, 6);
-
- p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len);
- if (p)
- memcpy(p, bd->bi_enetaddr, 6);
-#endif
-
-#if defined(CONFIG_HAS_ETH1)
- p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
- if (p)
- memcpy(p, bd->bi_enet1addr, 6);
-
- p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len);
- if (p)
- memcpy(p, bd->bi_enet1addr, 6);
-#endif
-
-#if defined(CONFIG_HAS_ETH2)
- p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len);
- if (p)
- memcpy(p, bd->bi_enet2addr, 6);
-
- p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/local-mac-address", &len);
- if (p)
- memcpy(p, bd->bi_enet2addr, 6);
-
-#ifdef CONFIG_UEC_ETH
- p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/mac-address", &len);
- if (p)
- memcpy(p, bd->bi_enet2addr, 6);
-
- p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/local-mac-address", &len);
- if (p)
- memcpy(p, bd->bi_enet2addr, 6);
-
-#endif
-#endif
-
-#if defined(CONFIG_HAS_ETH3)
- p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len);
- if (p)
- memcpy(p, bd->bi_enet3addr, 6);
-
- p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/local-mac-address", &len);
- if (p)
- memcpy(p, bd->bi_enet3addr, 6);
-
-#ifdef CONFIG_UEC_ETH
- p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/mac-address", &len);
- if (p)
- memcpy(p, bd->bi_enet3addr, 6);
-
- p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/local-mac-address", &len);
- if (p)
- memcpy(p, bd->bi_enet3addr, 6);
-
-#endif
-#endif
-
-}
-#endif
#endif
#ifdef CONFIG_CPM2
-static void config_8560_ioports (volatile immap_t * immr)
+void config_8560_ioports (volatile ccsr_cpm_t * cpm)
{
int portnum;
}
if (pmsk != 0) {
- volatile ioport_t *iop = ioport_addr (immr, portnum);
+ volatile ioport_t *iop = ioport_addr (cpm, portnum);
uint tpmsk = ~pmsk;
/*
void cpu_init_f (void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_lbc_t *memctl = &immap->im_lbc;
+ volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
extern void m8560_cpm_reset (void);
/* Pointer is writable since we allocated a register for it */
#ifdef CONFIG_CPM2
- config_8560_ioports(immap);
+ config_8560_ioports((ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR);
#endif
/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
int cpu_init_r(void)
{
-#if defined(CONFIG_CLEAR_LAW0) || defined(CONFIG_L2_CACHE)
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
-#endif
#ifdef CONFIG_CLEAR_LAW0
- volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
+ volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
/* clear alternate boot location LAW (used for sdram, or ddr bank) */
ecm->lawar0 = 0;
#endif
#if defined(CONFIG_L2_CACHE)
- volatile ccsr_l2cache_t *l2cache = &immap->im_l2cache;
+ volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR;
volatile uint cache_ctl;
uint svr, ver;
uint l2srbar;
{
struct ether_fcc_info_s * info = dev->priv;
int i;
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
- volatile ccsr_cpm_cp_t *cp = &(immr->im_cpm.im_cpm_cp);
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
+ volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp);
fcc_enet_t *pram_ptr;
unsigned long mem_addr;
/* 28.9 - (1-2): ioports have been set up already */
/* 28.9 - (3): connect FCC's tx and rx clocks */
- immr->im_cpm.im_cpm_mux.cmxuar = 0; /* ATM */
- immr->im_cpm.im_cpm_mux.cmxfcr = (immr->im_cpm.im_cpm_mux.cmxfcr & ~info->cmxfcr_mask) |
+ cpm->im_cpm_mux.cmxuar = 0; /* ATM */
+ cpm->im_cpm_mux.cmxfcr = (cpm->im_cpm_mux.cmxfcr & ~info->cmxfcr_mask) |
info->cmxfcr_value;
/* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, set Mode Ethernet */
if(info->ether_index == 0) {
- immr->im_cpm.im_cpm_fcc1.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
+ cpm->im_cpm_fcc1.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
} else if (info->ether_index == 1) {
- immr->im_cpm.im_cpm_fcc2.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
+ cpm->im_cpm_fcc2.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
} else if (info->ether_index == 2) {
- immr->im_cpm.im_cpm_fcc3.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
+ cpm->im_cpm_fcc3.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
}
/* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet,MII */
if(info->ether_index == 0) {
- immr->im_cpm.im_cpm_fcc1.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
+ cpm->im_cpm_fcc1.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
} else if (info->ether_index == 1){
- immr->im_cpm.im_cpm_fcc2.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
+ cpm->im_cpm_fcc2.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
} else if (info->ether_index == 2){
- immr->im_cpm.im_cpm_fcc3.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
+ cpm->im_cpm_fcc3.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
}
/* 28.9 - (6): FDSR: Ethernet Syn */
if(info->ether_index == 0) {
- immr->im_cpm.im_cpm_fcc1.fdsr = 0xD555;
+ cpm->im_cpm_fcc1.fdsr = 0xD555;
} else if (info->ether_index == 1) {
- immr->im_cpm.im_cpm_fcc2.fdsr = 0xD555;
+ cpm->im_cpm_fcc2.fdsr = 0xD555;
} else if (info->ether_index == 2) {
- immr->im_cpm.im_cpm_fcc3.fdsr = 0xD555;
+ cpm->im_cpm_fcc3.fdsr = 0xD555;
}
/* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */
rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
/* 28.9 - (7): initialize parameter ram */
- pram_ptr = (fcc_enet_t *)&(immr->im_cpm.im_dprambase[info->proff_enet]);
+ pram_ptr = (fcc_enet_t *)&(cpm->im_dprambase[info->proff_enet]);
/* clear whole structure to make sure all reserved fields are zero */
memset((void*)pram_ptr, 0, sizeof(fcc_enet_t));
/* 28.9 - (8)(9): clear out events in FCCE */
/* 28.9 - (9): FCCM: mask all events */
if(info->ether_index == 0) {
- immr->im_cpm.im_cpm_fcc1.fcce = ~0x0;
- immr->im_cpm.im_cpm_fcc1.fccm = 0;
+ cpm->im_cpm_fcc1.fcce = ~0x0;
+ cpm->im_cpm_fcc1.fccm = 0;
} else if (info->ether_index == 1) {
- immr->im_cpm.im_cpm_fcc2.fcce = ~0x0;
- immr->im_cpm.im_cpm_fcc2.fccm = 0;
+ cpm->im_cpm_fcc2.fcce = ~0x0;
+ cpm->im_cpm_fcc2.fccm = 0;
} else if (info->ether_index == 2) {
- immr->im_cpm.im_cpm_fcc3.fcce = ~0x0;
- immr->im_cpm.im_cpm_fcc3.fccm = 0;
+ cpm->im_cpm_fcc3.fcce = ~0x0;
+ cpm->im_cpm_fcc3.fccm = 0;
}
/* 28.9 - (10-12): we don't use ethernet interrupts */
/* 28.9 - (14): enable tx/rx in gfmr */
if(info->ether_index == 0) {
- immr->im_cpm.im_cpm_fcc1.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
+ cpm->im_cpm_fcc1.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
} else if (info->ether_index == 1) {
- immr->im_cpm.im_cpm_fcc2.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
+ cpm->im_cpm_fcc2.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
} else if (info->ether_index == 2) {
- immr->im_cpm.im_cpm_fcc3.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
+ cpm->im_cpm_fcc3.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
}
return 1;
static void fec_halt(struct eth_device* dev)
{
struct ether_fcc_info_s * info = dev->priv;
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
/* write GFMR: disable tx/rx */
if(info->ether_index == 0) {
- immr->im_cpm.im_cpm_fcc1.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
+ cpm->im_cpm_fcc1.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
} else if(info->ether_index == 1) {
- immr->im_cpm.im_cpm_fcc2.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
+ cpm->im_cpm_fcc2.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
} else if(info->ether_index == 2) {
- immr->im_cpm.im_cpm_fcc3.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
+ cpm->im_cpm_fcc3.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
}
}
--- /dev/null
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+void ft_cpu_setup(void *blob, bd_t *bd)
+{
+#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
+ defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
+ fdt_fixup_ethernet(blob, bd);
+#endif
+
+ do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
+ "timebase-frequency", bd->bi_busfreq / 8, 1);
+ do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
+ "bus-frequency", bd->bi_busfreq, 1);
+ do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
+ "clock-frequency", bd->bi_intfreq, 1);
+ do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
+ "bus-frequency", bd->bi_busfreq, 1);
+#ifdef CONFIG_QE
+ do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
+ "bus-frequency", bd->bi_busfreq, 1);
+#endif
+
+#ifdef CFG_NS16550
+ do_fixup_by_compat_u32(blob, "ns16550",
+ "clock-frequency", bd->bi_busfreq, 1);
+#endif
+
+#ifdef CONFIG_CPM2
+ do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart",
+ "current-speed", bd->bi_baudrate, 1);
+
+ do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
+ "clock-frequency", bd->bi_brgfreq, 1);
+#endif
+
+ fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
+}
int interrupt_init (void)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR);
- immr->im_pic.gcr = MPC85xx_PICGCR_RST;
- while (immr->im_pic.gcr & MPC85xx_PICGCR_RST);
- immr->im_pic.gcr = MPC85xx_PICGCR_M;
+ pic->gcr = MPC85xx_PICGCR_RST;
+ while (pic->gcr & MPC85xx_PICGCR_RST);
+ pic->gcr = MPC85xx_PICGCR_M;
decrementer_count = get_tbclk() / CFG_HZ;
mtspr(SPRN_TCR, TCR_PIE);
set_dec (decrementer_count);
set_msr (get_msr () | MSR_EE);
#ifdef CONFIG_INTERRUPTS
- volatile ccsr_pic_t *pic = &immr->im_pic;
-
pic->iivpr1 = 0x810002; /* 50220 enable ecm interrupts */
debug("iivpr1@%x = %x\n",&pic->iivpr1, pic->iivpr1);
#include <asm/cpm_85xx.h>
#include <pci.h>
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#endif
-
#if defined(CONFIG_PCI)
static struct pci_controller *pci_hose;
u16 reg16;
u32 dev;
- volatile immap_t *immap = (immap_t *)CFG_CCSRBAR;
- volatile ccsr_pcix_t *pcix = &immap->im_pcix;
+ volatile ccsr_pcix_t *pcix = (void *)(CFG_MPC85xx_PCIX_ADDR);
#ifdef CONFIG_MPC85XX_PCI2
- volatile ccsr_pcix_t *pcix2 = &immap->im_pcix2;
+ volatile ccsr_pcix_t *pcix2 = (void *)(CFG_MPC85xx_PCIX2_ADDR);
#endif
- volatile ccsr_gur_t *gur = &immap->im_gur;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
struct pci_controller * hose;
pci_hose = board_hose;
hose->last_busno = pci_hose_scan(hose);
#endif
}
-
-#ifdef CONFIG_OF_FLAT_TREE
-void
-ft_pci_setup(void *blob, bd_t *bd)
-{
- u32 *p;
- int len;
-
- p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
- if (p != NULL) {
- p[0] = pci_hose[0].first_busno;
- p[1] = pci_hose[0].last_busno;
- }
-
-#ifdef CONFIG_MPC85XX_PCI2
- p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@9000/bus-range", &len);
- if (p != NULL) {
- p[0] = pci_hose[1].first_busno;
- p[1] = pci_hose[1].last_busno;
- }
-#endif
-}
-#endif /* CONFIG_OF_FLAT_TREE */
#endif /* CONFIG_PCI */
u32 pin_2bit_assign;
u32 pin_1bit_mask;
u32 tmp_val;
- volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
volatile par_io_t *par_io = (volatile par_io_t *)
- &(im->im_gur.qe_par_io);
+ &(gur->qe_par_io);
/* Caculate pin location and 2bit mask and dir */
pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
int serial_init (void)
{
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
volatile ccsr_cpm_scc_t *sp;
volatile scc_uart_t *up;
volatile cbd_t *tbdf, *rbdf;
- volatile ccsr_cpm_cp_t *cp = &(im->im_cpm.im_cpm_cp);
+ volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp);
uint dpaddr;
/* initialize pointers to SCC */
- sp = (ccsr_cpm_scc_t *) &(im->im_cpm.im_cpm_scc[SCC_INDEX]);
- up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]);
+ sp = (ccsr_cpm_scc_t *) &(cpm->im_cpm_scc[SCC_INDEX]);
+ up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
/* Disable transmitter/receiver.
*/
/* put the SCC channel into NMSI (non multiplexd serial interface)
* mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15).
*/
- im->im_cpm.im_cpm_mux.cmxscr = \
- (im->im_cpm.im_cpm_mux.cmxscr&~CMXSCR_MASK)|CMXSCR_VALUE;
+ cpm->im_cpm_mux.cmxscr = \
+ (cpm->im_cpm_mux.cmxscr&~CMXSCR_MASK)|CMXSCR_VALUE;
/* Set up the baud rate generator.
*/
/* Set the physical address of the host memory buffers in
* the buffer descriptors.
*/
- rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[dpaddr]);
+ rbdf = (cbd_t *)&(cpm->im_dprambase[dpaddr]);
rbdf->cbd_bufaddr = (uint) (rbdf+2);
rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP;
tbdf = rbdf + 1;
{
volatile scc_uart_t *up;
volatile cbd_t *tbdf;
- volatile immap_t *im;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
if (c == '\n')
serial_putc ('\r');
- im = (immap_t *)CFG_IMMR;
- up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]);
- tbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_tbase]);
+ up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
+ tbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_tbase]);
/* Wait for last character to go.
*/
{
volatile cbd_t *rbdf;
volatile scc_uart_t *up;
- volatile immap_t *im;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
unsigned char c;
- im = (immap_t *)CFG_IMMR;
- up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]);
- rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_rbase]);
+ up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
+ rbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_rbase]);
/* Wait for character to show up.
*/
{
volatile cbd_t *rbdf;
volatile scc_uart_t *up;
- volatile immap_t *im;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
- im = (immap_t *)CFG_IMMR;
- up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]);
- rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_rbase]);
+ up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
+ rbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_rbase]);
return ((rbdf->cbd_sc & BD_SC_EMPTY) == 0);
}
{
int clks;
- clks = picos / (2000000000 / (get_bus_freq(0) / 1000));
- if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) {
+ clks = picos / (2000000000 / (get_ddr_freq(0) / 1000));
+ if (picos % (2000000000 / (get_ddr_freq(0) / 1000)) != 0) {
clks++;
}
long int
spd_sdram(void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_ddr_t *ddr = &immap->im_ddr;
+ volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR);
spd_eeprom_t spd;
unsigned int n_ranks;
unsigned int rank_density;
if ((SVR_VER(get_svr()) == SVR_8548_E) &&
(SVR_MJREV(get_svr()) == 1) &&
(spd.mem_type == SPD_MEMTYPE_DDR2)) {
- volatile ccsr_gur_t *gur = &immap->im_gur;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
gur->ddrioovcr = (0x80000000 /* Enable */
| 0x10000000);/* VSEL to 1.8V */
}
* Adjust the CAS Latency to allow for bus speeds that
* are slower than the DDR module.
*/
- busfreq = get_bus_freq(0) / 1000000; /* MHz */
+ busfreq = get_ddr_freq(0) / 1000000; /* MHz */
effective_data_rate = max_data_rate;
if (busfreq < 90) {
static unsigned int
setup_laws_and_tlbs(unsigned int memsize)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
+ volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
unsigned int tlb_size;
unsigned int law_size;
unsigned int ram_tlb_index;
{
uint *p = 0;
uint i = 0;
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+ volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
dma_init();
void get_sys_info (sys_info_t * sysInfo)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
uint plat_ratio,e500_ratio,half_freqSystemBus;
plat_ratio = (gur->porpllsr) & 0x0000003e;
* overflow for processor speeds above 2GHz */
half_freqSystemBus = sysInfo->freqSystemBus/2;
sysInfo->freqProcessor = e500_ratio*half_freqSystemBus;
+ sysInfo->freqDDRBus = sysInfo->freqSystemBus;
+
+#ifdef CONFIG_DDR_CLK_FREQ
+ {
+ u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
+ if (ddr_ratio != 0x7)
+ sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
+ }
+#endif
}
{
sys_info_t sys_info;
#if defined(CONFIG_CPM2)
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
uint sccr, dfbrg;
/* set VCO = 4 * BRG */
- immap->im_cpm.im_cpm_intctl.sccr &= 0xfffffffc;
- sccr = immap->im_cpm.im_cpm_intctl.sccr;
+ cpm->im_cpm_intctl.sccr &= 0xfffffffc;
+ sccr = cpm->im_cpm_intctl.sccr;
dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
#endif
get_sys_info (&sys_info);
return val;
}
+
+/********************************************
+ * get_ddr_freq
+ * return ddr bus freq in Hz
+ *********************************************/
+ulong get_ddr_freq (ulong dummy)
+{
+ ulong val;
+
+ sys_info_t sys_info;
+
+ get_sys_info (&sys_info);
+ val = sys_info.freqDDRBus;
+
+ return val;
+}
void
ExtIntException(struct pt_regs *regs)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_pic_t *pic = &immap->im_pic;
+ volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR);
+
uint vect;
#if defined(CONFIG_CMD_KGDB)
*/
sccr_reg = immr->im_clkrst.car_sccr;
sccr_reg &= ~SCCR_EBDF11;
-#if defined(CONFIG_TQM885D)
- if (gd->cpu_clk <= 80000000) {
-#else
+
if (gd->cpu_clk <= 66000000) {
-#endif
sccr_reg |= SCCR_EBDF00; /* bus division factor = 1 */
gd->bus_clk = gd->cpu_clk;
} else {
+++ /dev/null
-/*-----------------------------------------------------------------------------+
- *
- * This source code has been made available to you by IBM on an AS-IS
- * basis. Anyone receiving this source is licensed under IBM
- * copyrights to use it in any way he or she deems fit, including
- * copying it, modifying it, compiling it, and redistributing it either
- * with or without modifications. No license under IBM patents or
- * patent applications is to be implied by the copyright license.
- *
- * Any user of this software should understand that IBM cannot provide
- * technical support for this software and will not be responsible for
- * any consequences resulting from the use of this software.
- *
- * Any person who transfers this source code or any derivative work
- * must include the IBM copyright notice, this paragraph, and the
- * preceding two paragraphs in the transferred software.
- *
- * COPYRIGHT I B M CORPORATION 1995
- * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
- *-----------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------+
- *
- * File Name: 405gp_pci.c
- *
- * Function: Initialization code for the 405GP PCI Configuration regs.
- *
- * Author: Mark Game
- *
- * Change Activity-
- *
- * Date Description of Change BY
- * --------- --------------------- ---
- * 09-Sep-98 Created MCG
- * 02-Nov-98 Removed External arbiter selected message JWB
- * 27-Nov-98 Zero out PTMBAR2 and disable in PTM2MS JWB
- * 04-Jan-99 Zero out other unused PMM and PTM regs. Change bus scan MCG
- * from (0 to n) to (1 to n).
- * 17-May-99 Port to Walnut JWB
- * 17-Jun-99 Updated for VGA support JWB
- * 21-Jun-99 Updated to allow SRAM region to be a target from PCI bus JWB
- * 19-Jul-99 Updated for 405GP pass 1 errata #26 (Low PCI subsequent MCG
- * target latency timer values are not supported).
- * Should be fixed in pass 2.
- * 09-Sep-99 Removed use of PTM2 since the SRAM region no longer needs JWB
- * to be a PCI target. Zero out PTMBAR2 and disable in PTM2MS.
- * 10-Dec-99 Updated PCI_Write_CFG_Reg for pass2 errata #6 JWB
- * 11-Jan-00 Ensure PMMxMAs disabled before setting PMMxLAs. This is not
- * really required after a reset since PMMxMAs are already
- * disabled but is a good practice nonetheless. JWB
- * 12-Jun-01 stefan.roese@esd-electronics.com
- * - PCI host/adapter handling reworked
- * 09-Jul-01 stefan.roese@esd-electronics.com
- * - PCI host now configures from device 0 (not 1) to max_dev,
- * (host configures itself)
- * - On CPCI-405 pci base address and size is generated from
- * SDRAM and FLASH size (CFG regs not used anymore)
- * - Some minor changes for CPCI-405-A (adapter version)
- * 14-Sep-01 stefan.roese@esd-electronics.com
- * - CONFIG_PCI_SCAN_SHOW added to print pci devices upon startup
- * 28-Sep-01 stefan.roese@esd-electronics.com
- * - Changed pci master configuration for linux compatibility
- * (no need for bios_fixup() anymore)
- * 26-Feb-02 stefan.roese@esd-electronics.com
- * - Bug fixed in pci configuration (Andrew May)
- * - Removed pci class code init for CPCI405 board
- * 15-May-02 stefan.roese@esd-electronics.com
- * - New vga device handling
- * 29-May-02 stefan.roese@esd-electronics.com
- * - PCI class code init added (if defined)
- *----------------------------------------------------------------------------*/
-
-#include <common.h>
-#include <command.h>
-#if !defined(CONFIG_440)
-#include <405gp_pci.h>
-#endif
-#include <asm/processor.h>
-#include <pci.h>
-
-#ifdef CONFIG_PCI
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Board-specific pci initialization
- * Platform code can reimplement pci_pre_init() if needed
- */
-int __pci_pre_init(struct pci_controller *hose)
-{
- return 1;
-}
-int pci_pre_init(struct pci_controller *hose) __attribute__((weak, alias("__pci_pre_init")));
-
-#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
-
-#if defined(CONFIG_PMC405)
-ushort pmc405_pci_subsys_deviceid(void);
-#endif
-
-/*#define DEBUG*/
-
-/*-----------------------------------------------------------------------------+
- * pci_init. Initializes the 405GP PCI Configuration regs.
- *-----------------------------------------------------------------------------*/
-void pci_405gp_init(struct pci_controller *hose)
-{
- int i, reg_num = 0;
- bd_t *bd = gd->bd;
-
- unsigned short temp_short;
- unsigned long ptmpcila[2] = {CFG_PCI_PTM1PCI, CFG_PCI_PTM2PCI};
-#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405)
- char *ptmla_str, *ptmms_str;
-#endif
- unsigned long ptmla[2] = {CFG_PCI_PTM1LA, CFG_PCI_PTM2LA};
- unsigned long ptmms[2] = {CFG_PCI_PTM1MS, CFG_PCI_PTM2MS};
-#if defined(CONFIG_PIP405) || defined (CONFIG_MIP405)
- unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0};
- unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0};
- unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0};
- unsigned long pmmpciha[3] = {0x00000000, 0x00000000, 0};
-#else
- unsigned long pmmla[3] = {0x80000000, 0,0};
- unsigned long pmmma[3] = {0xC0000001, 0,0};
- unsigned long pmmpcila[3] = {0x80000000, 0,0};
- unsigned long pmmpciha[3] = {0x00000000, 0,0};
-#endif
-#ifdef CONFIG_PCI_PNP
-#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
- char *s;
-#endif
-#endif
-
-#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405)
- ptmla_str = getenv("ptm1la");
- ptmms_str = getenv("ptm1ms");
- if(NULL != ptmla_str && NULL != ptmms_str ) {
- ptmla[0] = simple_strtoul (ptmla_str, NULL, 16);
- ptmms[0] = simple_strtoul (ptmms_str, NULL, 16);
- }
-
- ptmla_str = getenv("ptm2la");
- ptmms_str = getenv("ptm2ms");
- if(NULL != ptmla_str && NULL != ptmms_str ) {
- ptmla[1] = simple_strtoul (ptmla_str, NULL, 16);
- ptmms[1] = simple_strtoul (ptmms_str, NULL, 16);
- }
-#endif
-
- /*
- * Register the hose
- */
- hose->first_busno = 0;
- hose->last_busno = 0xff;
-
- /* ISA/PCI I/O space */
- pci_set_region(hose->regions + reg_num++,
- MIN_PCI_PCI_IOADDR,
- MIN_PLB_PCI_IOADDR,
- 0x10000,
- PCI_REGION_IO);
-
- /* PCI I/O space */
- pci_set_region(hose->regions + reg_num++,
- 0x00800000,
- 0xe8800000,
- 0x03800000,
- PCI_REGION_IO);
-
- reg_num = 2;
-
- /* Memory spaces */
- for (i=0; i<2; i++)
- if (ptmms[i] & 1)
- {
- if (!i) hose->pci_fb = hose->regions + reg_num;
-
- pci_set_region(hose->regions + reg_num++,
- ptmpcila[i], ptmla[i],
- ~(ptmms[i] & 0xfffff000) + 1,
- PCI_REGION_MEM |
- PCI_REGION_MEMORY);
- }
-
- /* PCI memory spaces */
- for (i=0; i<3; i++)
- if (pmmma[i] & 1)
- {
- pci_set_region(hose->regions + reg_num++,
- pmmpcila[i], pmmla[i],
- ~(pmmma[i] & 0xfffff000) + 1,
- PCI_REGION_MEM);
- }
-
- hose->region_count = reg_num;
-
- pci_setup_indirect(hose,
- PCICFGADR,
- PCICFGDATA);
-
- if (hose->pci_fb)
- pciauto_region_init(hose->pci_fb);
-
- /* Let board change/modify hose & do initial checks */
- if (pci_pre_init (hose) == 0) {
- printf("PCI: Board-specific initialization failed.\n");
- printf("PCI: Configuration aborted.\n");
- return;
- }
-
- pci_register_hose(hose);
-
- /*--------------------------------------------------------------------------+
- * 405GP PCI Master configuration.
- * Map one 512 MB range of PLB/processor addresses to PCI memory space.
- * PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF
- * Use byte reversed out routines to handle endianess.
- *--------------------------------------------------------------------------*/
- out32r(PMM0MA, (pmmma[0]&~0x1)); /* disable, configure PMMxLA, PMMxPCILA first */
- out32r(PMM0LA, pmmla[0]);
- out32r(PMM0PCILA, pmmpcila[0]);
- out32r(PMM0PCIHA, pmmpciha[0]);
- out32r(PMM0MA, pmmma[0]);
-
- /*--------------------------------------------------------------------------+
- * PMM1 is not used. Initialize them to zero.
- *--------------------------------------------------------------------------*/
- out32r(PMM1MA, (pmmma[1]&~0x1));
- out32r(PMM1LA, pmmla[1]);
- out32r(PMM1PCILA, pmmpcila[1]);
- out32r(PMM1PCIHA, pmmpciha[1]);
- out32r(PMM1MA, pmmma[1]);
-
- /*--------------------------------------------------------------------------+
- * PMM2 is not used. Initialize them to zero.
- *--------------------------------------------------------------------------*/
- out32r(PMM2MA, (pmmma[2]&~0x1));
- out32r(PMM2LA, pmmla[2]);
- out32r(PMM2PCILA, pmmpcila[2]);
- out32r(PMM2PCIHA, pmmpciha[2]);
- out32r(PMM2MA, pmmma[2]);
-
- /*--------------------------------------------------------------------------+
- * 405GP PCI Target configuration. (PTM1)
- * Note: PTM1MS is hardwire enabled but we set the enable bit anyway.
- *--------------------------------------------------------------------------*/
- out32r(PTM1LA, ptmla[0]); /* insert address */
- out32r(PTM1MS, ptmms[0]); /* insert size, enable bit is 1 */
- pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_1, ptmpcila[0]);
-
- /*--------------------------------------------------------------------------+
- * 405GP PCI Target configuration. (PTM2)
- *--------------------------------------------------------------------------*/
- out32r(PTM2LA, ptmla[1]); /* insert address */
- pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, ptmpcila[1]);
-
- if (ptmms[1] == 0)
- {
- out32r(PTM2MS, 0x00000001); /* set enable bit */
- pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, 0x00000000);
- out32r(PTM2MS, 0x00000000); /* disable */
- }
- else
- {
- out32r(PTM2MS, ptmms[1]); /* insert size, enable bit is 1 */
- }
-
- /*
- * Insert Subsystem Vendor and Device ID
- */
- pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CFG_PCI_SUBSYS_VENDORID);
-#ifdef CONFIG_CPCI405
- if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
- pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID);
- else
- pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID2);
-#else
- pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID);
-#endif
-
- /*
- * Insert Class-code
- */
-#ifdef CFG_PCI_CLASSCODE
- pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CFG_PCI_CLASSCODE);
-#endif /* CFG_PCI_CLASSCODE */
-
- /*--------------------------------------------------------------------------+
- * If PCI speed = 66Mhz, set 66Mhz capable bit.
- *--------------------------------------------------------------------------*/
- if (bd->bi_pci_busfreq >= 66000000) {
- pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short);
- pci_write_config_word(PCIDEVID_405GP,PCI_STATUS,(temp_short|PCI_STATUS_66MHZ));
- }
-
-#if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER)
-#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
- if ((mfdcr(strap) & PSR_PCI_ARBIT_EN) ||
- (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
-#endif
- {
- /*--------------------------------------------------------------------------+
- * Write the 405GP PCI Configuration regs.
- * Enable 405GP to be a master on the PCI bus (PMM).
- * Enable 405GP to act as a PCI memory target (PTM).
- *--------------------------------------------------------------------------*/
- pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &temp_short);
- pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND, temp_short |
- PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
- }
-#endif
-
-#if defined(CONFIG_405EP) /* on ppc405ep vendor id is not set */
- pci_write_config_word(PCIDEVID_405GP, PCI_VENDOR_ID, 0x1014); /* IBM */
-#endif
-
- /*
- * Set HCE bit (Host Configuration Enabled)
- */
- pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &temp_short);
- pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (temp_short | 0x0001));
-
-#ifdef CONFIG_PCI_PNP
- /*--------------------------------------------------------------------------+
- * Scan the PCI bus and configure devices found.
- *--------------------------------------------------------------------------*/
-#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
- if ((mfdcr(strap) & PSR_PCI_ARBIT_EN) ||
- (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
-#endif
- {
-#ifdef CONFIG_PCI_SCAN_SHOW
- printf("PCI: Bus Dev VenId DevId Class Int\n");
-#endif
- hose->last_busno = pci_hose_scan(hose);
- }
-#endif /* CONFIG_PCI_PNP */
-
-}
-
-/*
- * drivers/pci.c skips every host bridge but the 405GP since it could
- * be set as an Adapter.
- *
- * I (Andrew May) don't know what we should do here, but I don't want
- * the auto setup of a PCI device disabling what is done pci_405gp_init
- * as has happened before.
- */
-void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev,
- struct pci_config_table *entry)
-{
-#ifdef DEBUG
- printf("405gp_setup_bridge\n");
-#endif
-}
-
-/*
- *
- */
-
-void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
-{
- unsigned char int_line = 0xff;
-
- /*
- * Write pci interrupt line register (cpci405 specific)
- */
- switch (PCI_DEV(dev) & 0x03)
- {
- case 0:
- int_line = 27 + 2;
- break;
- case 1:
- int_line = 27 + 3;
- break;
- case 2:
- int_line = 27 + 0;
- break;
- case 3:
- int_line = 27 + 1;
- break;
- }
-
- pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
-}
-
-void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
- struct pci_config_table *entry)
-{
- unsigned int cmdstat = 0;
-
- pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
-
- /* always enable io space on vga boards */
- pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
- cmdstat |= PCI_COMMAND_IO;
- pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
-}
-
-#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) && !(defined (CONFIG_SC3))
-
-/*
- *As is these functs get called out of flash Not a horrible
- *thing, but something to keep in mind. (no statics?)
- */
-static struct pci_config_table pci_405gp_config_table[] = {
-/*if VendID is 0 it terminates the table search (ie Walnut)*/
-#ifdef CFG_PCI_SUBSYS_VENDORID
- {CFG_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST,
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge},
-#endif
- {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA,
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
-
- {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA,
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
-
- { }
-};
-
-static struct pci_controller hose = {
- fixup_irq: pci_405gp_fixup_irq,
- config_table: pci_405gp_config_table,
-};
-
-void pci_init_board(void)
-{
- /*we want the ptrs to RAM not flash (ie don't use init list)*/
- hose.fixup_irq = pci_405gp_fixup_irq;
- hose.config_table = pci_405gp_config_table;
- pci_405gp_init(&hose);
-}
-
-#endif
-
-#endif /* CONFIG_405GP */
-
-/*-----------------------------------------------------------------------------+
- * CONFIG_440
- *-----------------------------------------------------------------------------*/
-#if defined(CONFIG_440)
-
-static struct pci_controller ppc440_hose = {0};
-
-
-int pci_440_init (struct pci_controller *hose)
-{
- int reg_num = 0;
-
-#ifndef CONFIG_DISABLE_PISE_TEST
- /*--------------------------------------------------------------------------+
- * The PCI initialization sequence enable bit must be set ... if not abort
- * pci setup since updating the bit requires chip reset.
- *--------------------------------------------------------------------------*/
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
- unsigned long strap;
-
- mfsdr(sdr_sdstp1,strap);
- if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) {
- printf("PCI: SDR0_STRP1[PISE] not set.\n");
- printf("PCI: Configuration aborted.\n");
- return -1;
- }
-#elif defined(CONFIG_440GP)
- unsigned long strap;
-
- strap = mfdcr(cpc0_strp1);
- if ((strap & CPC0_STRP1_PISE_MASK) == 0) {
- printf("PCI: CPC0_STRP1[PISE] not set.\n");
- printf("PCI: Configuration aborted.\n");
- return -1;
- }
-#endif
-#endif /* CONFIG_DISABLE_PISE_TEST */
-
- /*--------------------------------------------------------------------------+
- * PCI controller init
- *--------------------------------------------------------------------------*/
- hose->first_busno = 0;
- hose->last_busno = 0;
-
- /* PCI I/O space */
- pci_set_region(hose->regions + reg_num++,
- 0x00000000,
- PCIX0_IOBASE,
- 0x10000,
- PCI_REGION_IO);
-
- /* PCI memory space */
- pci_set_region(hose->regions + reg_num++,
- CFG_PCI_TARGBASE,
- CFG_PCI_MEMBASE,
-#ifdef CFG_PCI_MEMSIZE
- CFG_PCI_MEMSIZE,
-#else
- 0x10000000,
-#endif
- PCI_REGION_MEM );
-
-#if defined(CONFIG_PCI_SYS_MEM_BUS) && defined(CONFIG_PCI_SYS_MEM_PHYS) && \
- defined(CONFIG_PCI_SYS_MEM_SIZE)
- /* System memory space */
- pci_set_region(hose->regions + reg_num++,
- CONFIG_PCI_SYS_MEM_BUS,
- CONFIG_PCI_SYS_MEM_PHYS,
- CONFIG_PCI_SYS_MEM_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY );
-#endif
-
- hose->region_count = reg_num;
-
- pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA);
-
- /* Let board change/modify hose & do initial checks */
- if (pci_pre_init (hose) == 0) {
- printf("PCI: Board-specific initialization failed.\n");
- printf("PCI: Configuration aborted.\n");
- return -1;
- }
-
- pci_register_hose( hose );
-
- /*--------------------------------------------------------------------------+
- * PCI target init
- *--------------------------------------------------------------------------*/
-#if defined(CFG_PCI_TARGET_INIT)
- pci_target_init(hose); /* Let board setup pci target */
-#else
- out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
- out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_ID );
- out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
-#endif
-
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
- out32r( PCIX0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */
- out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */
-#elif defined(PCIX0_BRDGOPT1)
- out32r( PCIX0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */
- out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config */
-#endif
-
- /*--------------------------------------------------------------------------+
- * PCI master init: default is one 256MB region for PCI memory:
- * 0x3_00000000 - 0x3_0FFFFFFF ==> CFG_PCI_MEMBASE
- *--------------------------------------------------------------------------*/
-#if defined(CFG_PCI_MASTER_INIT)
- pci_master_init(hose); /* Let board setup pci master */
-#else
- out32r( PCIX0_POM0SA, 0 ); /* disable */
- out32r( PCIX0_POM1SA, 0 ); /* disable */
- out32r( PCIX0_POM2SA, 0 ); /* disable */
-#if defined(CONFIG_440SPE)
- out32r( PCIX0_POM0LAL, 0x10000000 );
- out32r( PCIX0_POM0LAH, 0x0000000c );
-#else
- out32r( PCIX0_POM0LAL, 0x00000000 );
- out32r( PCIX0_POM0LAH, 0x00000003 );
-#endif
- out32r( PCIX0_POM0PCIAL, CFG_PCI_MEMBASE );
- out32r( PCIX0_POM0PCIAH, 0x00000000 );
- out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */
- out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 );
-#endif
-
- /*--------------------------------------------------------------------------+
- * PCI host configuration -- we don't make any assumptions here ... the
- * _board_must_indicate_ what to do -- there's just too many runtime
- * scenarios in environments like cPCI, PPMC, etc. to make a determination
- * based on hard-coded values or state of arbiter enable.
- *--------------------------------------------------------------------------*/
- if (is_pci_host(hose)) {
-#ifdef CONFIG_PCI_SCAN_SHOW
- printf("PCI: Bus Dev VenId DevId Class Int\n");
-#endif
-#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
- !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
- out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
-#endif
- hose->last_busno = pci_hose_scan(hose);
- }
- return hose->last_busno;
-}
-
-void pci_init_board(void)
-{
- int busno;
-
- busno = pci_440_init (&ppc440_hose);
-#if defined(CONFIG_440SPE)
- pcie_setup_hoses(busno + 1);
-#endif
-}
-
-#endif /* CONFIG_440 */
-#endif /* CONFIG_PCI */
int t_rc;
int min_cas;
- PPC405_SYS_INFO sys_info;
+ PPC4xx_SYS_INFO sys_info;
unsigned long bus_period_x_10;
/*
+++ /dev/null
-/*
- * (C) Copyright 2006 - 2007
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Copyright (c) 2005 Cisco Systems. All rights reserved.
- * Roland Dreier <rolandd@cisco.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <asm/processor.h>
-#include <asm-ppc/io.h>
-#include <ppc4xx.h>
-#include <common.h>
-#include <pci.h>
-
-#if defined(CONFIG_440SPE) && defined(CONFIG_PCI)
-
-#include "440spe_pcie.h"
-
-enum {
- PTYPE_ENDPOINT = 0x0,
- PTYPE_LEGACY_ENDPOINT = 0x1,
- PTYPE_ROOT_PORT = 0x4,
-
- LNKW_X1 = 0x1,
- LNKW_X4 = 0x4,
- LNKW_X8 = 0x8
-};
-
-static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn)
-{
- u8 *base = (u8*)hose->cfg_data;
-
- /* use local configuration space for the first bus */
- if (PCI_BUS(devfn) == 0) {
- if (hose->cfg_data == (u8*)CFG_PCIE0_CFGBASE)
- base = (u8*)CFG_PCIE0_XCFGBASE;
- if (hose->cfg_data == (u8*)CFG_PCIE1_CFGBASE)
- base = (u8*)CFG_PCIE1_XCFGBASE;
- if (hose->cfg_data == (u8*)CFG_PCIE2_CFGBASE)
- base = (u8*)CFG_PCIE2_XCFGBASE;
- }
-
- return base;
-}
-
-static void pcie_dmer_disable(void)
-{
- mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE),
- mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) | GPL_DMER_MASK_DISA);
- mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE),
- mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) | GPL_DMER_MASK_DISA);
- mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE),
- mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) | GPL_DMER_MASK_DISA);
-}
-
-static void pcie_dmer_enable(void)
-{
- mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE0_BASE),
- mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) & ~GPL_DMER_MASK_DISA);
- mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE1_BASE),
- mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) & ~GPL_DMER_MASK_DISA);
- mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE2_BASE),
- mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA);
-}
-
-static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
- int offset, int len, u32 *val) {
-
- u8 *address;
- *val = 0;
-
- /*
- * Bus numbers are relative to hose->first_busno
- */
- devfn -= PCI_BDF(hose->first_busno, 0, 0);
-
- /*
- * NOTICE: configuration space ranges are currenlty mapped only for
- * the first 16 buses, so such limit must be imposed. In case more
- * buses are required the TLB settings in board/amcc/<board>/init.S
- * need to be altered accordingly (one bus takes 1 MB of memory space).
- */
- if (PCI_BUS(devfn) >= 16)
- return 0;
-
- /*
- * Only single device/single function is supported for the primary and
- * secondary buses of the 440SPe host bridge.
- */
- if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
- ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
- return 0;
-
- address = pcie_get_base(hose, devfn);
- offset += devfn << 4;
-
- /*
- * Reading from configuration space of non-existing device can
- * generate transaction errors. For the read duration we suppress
- * assertion of machine check exceptions to avoid those.
- */
- pcie_dmer_disable ();
-
- switch (len) {
- case 1:
- *val = in_8(hose->cfg_data + offset);
- break;
- case 2:
- *val = in_le16((u16 *)(hose->cfg_data + offset));
- break;
- default:
- *val = in_le32((u32*)(hose->cfg_data + offset));
- break;
- }
-
- pcie_dmer_enable ();
-
- return 0;
-}
-
-static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
- int offset, int len, u32 val) {
-
- u8 *address;
-
- /*
- * Bus numbers are relative to hose->first_busno
- */
- devfn -= PCI_BDF(hose->first_busno, 0, 0);
-
- /*
- * Same constraints as in pcie_read_config().
- */
- if (PCI_BUS(devfn) >= 16)
- return 0;
-
- if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
- ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
- return 0;
-
- address = pcie_get_base(hose, devfn);
- offset += devfn << 4;
-
- /*
- * Suppress MCK exceptions, similar to pcie_read_config()
- */
- pcie_dmer_disable ();
-
- switch (len) {
- case 1:
- out_8(hose->cfg_data + offset, val);
- break;
- case 2:
- out_le16((u16 *)(hose->cfg_data + offset), val);
- break;
- default:
- out_le32((u32 *)(hose->cfg_data + offset), val);
- break;
- }
-
- pcie_dmer_enable ();
-
- return 0;
-}
-
-int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 *val)
-{
- u32 v;
- int rv;
-
- rv = pcie_read_config(hose, dev, offset, 1, &v);
- *val = (u8)v;
- return rv;
-}
-
-int pcie_read_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 *val)
-{
- u32 v;
- int rv;
-
- rv = pcie_read_config(hose, dev, offset, 2, &v);
- *val = (u16)v;
- return rv;
-}
-
-int pcie_read_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 *val)
-{
- u32 v;
- int rv;
-
- rv = pcie_read_config(hose, dev, offset, 3, &v);
- *val = (u32)v;
- return rv;
-}
-
-int pcie_write_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 val)
-{
- return pcie_write_config(hose,(u32)dev,offset,1,val);
-}
-
-int pcie_write_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 val)
-{
- return pcie_write_config(hose,(u32)dev,offset,2,(u32 )val);
-}
-
-int pcie_write_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 val)
-{
- return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val);
-}
-
-static void ppc440spe_setup_utl(u32 port) {
-
- volatile void *utl_base = NULL;
-
- /*
- * Map UTL registers
- */
- switch (port) {
- case 0:
- mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c);
- mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x20000000);
- mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001);
- mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800);
- break;
-
- case 1:
- mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c);
- mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x20001000);
- mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001);
- mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800);
- break;
-
- case 2:
- mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c);
- mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x20002000);
- mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001);
- mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800);
- break;
- }
- utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port);
-
- /*
- * Set buffer allocations and then assert VRB and TXE.
- */
- out_be32(utl_base + PEUTL_OUTTR, 0x08000000);
- out_be32(utl_base + PEUTL_INTR, 0x02000000);
- out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000);
- out_be32(utl_base + PEUTL_PBBSZ, 0x53000000);
- out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000);
- out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000);
- out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
- out_be32(utl_base + PEUTL_PCTL, 0x80800066);
-}
-
-static int check_error(void)
-{
- u32 valPE0, valPE1, valPE2;
- int err = 0;
-
- /* SDR0_PEGPLLLCT1 reset */
- if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000)) {
- printf("PCIE: SDR0_PEGPLLLCT1 reset error 0x%x\n", valPE0);
- }
-
- valPE0 = SDR_READ(PESDR0_RCSSET);
- valPE1 = SDR_READ(PESDR1_RCSSET);
- valPE2 = SDR_READ(PESDR2_RCSSET);
-
- /* SDR0_PExRCSSET rstgu */
- if (!(valPE0 & 0x01000000) ||
- !(valPE1 & 0x01000000) ||
- !(valPE2 & 0x01000000)) {
- printf("PCIE: SDR0_PExRCSSET rstgu error\n");
- err = -1;
- }
-
- /* SDR0_PExRCSSET rstdl */
- if (!(valPE0 & 0x00010000) ||
- !(valPE1 & 0x00010000) ||
- !(valPE2 & 0x00010000)) {
- printf("PCIE: SDR0_PExRCSSET rstdl error\n");
- err = -1;
- }
-
- /* SDR0_PExRCSSET rstpyn */
- if ((valPE0 & 0x00001000) ||
- (valPE1 & 0x00001000) ||
- (valPE2 & 0x00001000)) {
- printf("PCIE: SDR0_PExRCSSET rstpyn error\n");
- err = -1;
- }
-
- /* SDR0_PExRCSSET hldplb */
- if ((valPE0 & 0x10000000) ||
- (valPE1 & 0x10000000) ||
- (valPE2 & 0x10000000)) {
- printf("PCIE: SDR0_PExRCSSET hldplb error\n");
- err = -1;
- }
-
- /* SDR0_PExRCSSET rdy */
- if ((valPE0 & 0x00100000) ||
- (valPE1 & 0x00100000) ||
- (valPE2 & 0x00100000)) {
- printf("PCIE: SDR0_PExRCSSET rdy error\n");
- err = -1;
- }
-
- /* SDR0_PExRCSSET shutdown */
- if ((valPE0 & 0x00000100) ||
- (valPE1 & 0x00000100) ||
- (valPE2 & 0x00000100)) {
- printf("PCIE: SDR0_PExRCSSET shutdown error\n");
- err = -1;
- }
- return err;
-}
-
-/*
- * Initialize PCI Express core
- */
-int ppc440spe_init_pcie(void)
-{
- int time_out = 20;
-
- /* Set PLL clock receiver to LVPECL */
- SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28);
-
- if (check_error())
- return -1;
-
- if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000))
- {
- printf("PCIE: PESDR_PLLCT2 resistance calibration failed (0x%08x)\n",
- SDR_READ(PESDR0_PLLLCT2));
- return -1;
- }
- /* De-assert reset of PCIe PLL, wait for lock */
- SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24));
- udelay(3);
-
- while (time_out) {
- if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) {
- time_out--;
- udelay(1);
- } else
- break;
- }
- if (!time_out) {
- printf("PCIE: VCO output not locked\n");
- return -1;
- }
- return 0;
-}
-
-/*
- * Yucca board as End point and root point setup
- * and
- * testing inbound and out bound windows
- *
- * YUCCA board can be plugged into another yucca board or you can get PCI-E
- * cable which can be used to setup loop back from one port to another port.
- * Please rememeber that unless there is a endpoint plugged in to root port it
- * will not initialize. It is the same in case of endpoint , unless there is
- * root port attached it will not initialize.
- *
- * In this release of software all the PCI-E ports are configured as either
- * endpoint or rootpoint.In future we will have support for selective ports
- * setup as endpoint and root point in single board.
- *
- * Once your board came up as root point , you can verify by reading
- * /proc/bus/pci/devices. Where you can see the configuration registers
- * of end point device attached to the port.
- *
- * Enpoint cofiguration can be verified by connecting Yucca board to any
- * host or another yucca board. Then try to scan the device. In case of
- * linux use "lspci" or appripriate os command.
- *
- * How do I verify the inbound and out bound windows ?(yucca to yucca)
- * in this configuration inbound and outbound windows are setup to access
- * sram memroy area. SRAM is at 0x4 0000 0000 , on PLB bus. This address
- * is mapped at 0x90000000. From u-boot prompt write data 0xb000 0000,
- * This is waere your POM(PLB out bound memory window) mapped. then
- * read the data from other yucca board's u-boot prompt at address
- * 0x9000 0000(SRAM). Data should match.
- * In case of inbound , write data to u-boot command prompt at 0xb000 0000
- * which is mapped to 0x4 0000 0000. Now on rootpoint yucca u-boot prompt check
- * data at 0x9000 0000(SRAM).Data should match.
- */
-int ppc440spe_init_pcie_rootport(int port)
-{
- static int core_init;
- volatile u32 val = 0;
- int attempts;
-
- if (!core_init) {
- ++core_init;
- if (ppc440spe_init_pcie())
- return -1;
- }
-
- /*
- * Initialize various parts of the PCI Express core for our port:
- *
- * - Set as a root port and enable max width
- * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4).
- * - Set up UTL configuration.
- * - Increase SERDES drive strength to levels suggested by AMCC.
- * - De-assert RSTPYN, RSTDL and RSTGU.
- *
- * NOTICE for revB chip: PESDRn_UTLSET2 is not set - we leave it with
- * default setting 0x11310000. The register has new fields,
- * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core
- * hang.
- */
- switch (port) {
- case 0:
- SDR_WRITE(PESDR0_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X8 << 12);
-
- SDR_WRITE(PESDR0_UTLSET1, 0x21222222);
- if (!ppc440spe_revB())
- SDR_WRITE(PESDR0_UTLSET2, 0x11000000);
- SDR_WRITE(PESDR0_HSSL0SET1, 0x35000000);
- SDR_WRITE(PESDR0_HSSL1SET1, 0x35000000);
- SDR_WRITE(PESDR0_HSSL2SET1, 0x35000000);
- SDR_WRITE(PESDR0_HSSL3SET1, 0x35000000);
- SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000);
- SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000);
- SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000);
- SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000);
- SDR_WRITE(PESDR0_RCSSET,
- (SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
- break;
-
- case 1:
- SDR_WRITE(PESDR1_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12);
- SDR_WRITE(PESDR1_UTLSET1, 0x21222222);
- if (!ppc440spe_revB())
- SDR_WRITE(PESDR1_UTLSET2, 0x11000000);
- SDR_WRITE(PESDR1_HSSL0SET1, 0x35000000);
- SDR_WRITE(PESDR1_HSSL1SET1, 0x35000000);
- SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000);
- SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000);
- SDR_WRITE(PESDR1_RCSSET,
- (SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
- break;
-
- case 2:
- SDR_WRITE(PESDR2_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12);
- SDR_WRITE(PESDR2_UTLSET1, 0x21222222);
- if (!ppc440spe_revB())
- SDR_WRITE(PESDR2_UTLSET2, 0x11000000);
- SDR_WRITE(PESDR2_HSSL0SET1, 0x35000000);
- SDR_WRITE(PESDR2_HSSL1SET1, 0x35000000);
- SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000);
- SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000);
- SDR_WRITE(PESDR2_RCSSET,
- (SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
- break;
- }
- /*
- * Notice: the following delay has critical impact on device
- * initialization - if too short (<50ms) the link doesn't get up.
- */
- mdelay(100);
-
- switch (port) {
- case 0:
- val = SDR_READ(PESDR0_RCSSTS);
- break;
- case 1:
- val = SDR_READ(PESDR1_RCSSTS);
- break;
- case 2:
- val = SDR_READ(PESDR2_RCSSTS);
- break;
- }
-
- if (val & (1 << 20)) {
- printf("PCIE%d: PGRST failed %08x\n", port, val);
- return -1;
- }
-
- /*
- * Verify link is up
- */
- val = 0;
- switch (port) {
- case 0:
- val = SDR_READ(PESDR0_LOOP);
- break;
- case 1:
- val = SDR_READ(PESDR1_LOOP);
- break;
- case 2:
- val = SDR_READ(PESDR2_LOOP);
- break;
- }
- if (!(val & 0x00001000)) {
- printf("PCIE%d: link is not up.\n", port);
- return -1;
- }
-
- /*
- * Setup UTL registers - but only on revA!
- * We use default settings for revB chip.
- */
- if (!ppc440spe_revB())
- ppc440spe_setup_utl(port);
-
- /*
- * We map PCI Express configuration access into the 512MB regions
- *
- * NOTICE: revB is very strict about PLB real addressess and ranges to
- * be mapped for config space; it seems to only work with d_nnnn_nnnn
- * range (hangs the core upon config transaction attempts when set
- * otherwise) while revA uses c_nnnn_nnnn.
- *
- * For revA:
- * PCIE0: 0xc_4000_0000
- * PCIE1: 0xc_8000_0000
- * PCIE2: 0xc_c000_0000
- *
- * For revB:
- * PCIE0: 0xd_0000_0000
- * PCIE1: 0xd_2000_0000
- * PCIE2: 0xd_4000_0000
- */
-
- switch (port) {
- case 0:
- if (ppc440spe_revB()) {
- mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000d);
- mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x00000000);
- } else {
- /* revA */
- mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000c);
- mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x40000000);
- }
- mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */
- break;
-
- case 1:
- if (ppc440spe_revB()) {
- mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000d);
- mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x20000000);
- } else {
- mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000c);
- mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x80000000);
- }
- mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
- break;
-
- case 2:
- if (ppc440spe_revB()) {
- mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000d);
- mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0x40000000);
- } else {
- mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000c);
- mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0xc0000000);
- }
- mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */
- break;
- }
-
- /*
- * Check for VC0 active and assert RDY.
- */
- attempts = 10;
- switch (port) {
- case 0:
- while(!(SDR_READ(PESDR0_RCSSTS) & (1 << 16))) {
- if (!(attempts--)) {
- printf("PCIE0: VC0 not active\n");
- return -1;
- }
- mdelay(1000);
- }
- SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20);
- break;
- case 1:
- while(!(SDR_READ(PESDR1_RCSSTS) & (1 << 16))) {
- if (!(attempts--)) {
- printf("PCIE1: VC0 not active\n");
- return -1;
- }
- mdelay(1000);
- }
-
- SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20);
- break;
- case 2:
- while(!(SDR_READ(PESDR2_RCSSTS) & (1 << 16))) {
- if (!(attempts--)) {
- printf("PCIE2: VC0 not active\n");
- return -1;
- }
- mdelay(1000);
- }
-
- SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20);
- break;
- }
- mdelay(100);
-
- return 0;
-}
-
-int ppc440spe_init_pcie_endport(int port)
-{
- static int core_init;
- volatile u32 val = 0;
- int attempts;
-
- if (!core_init) {
- ++core_init;
- if (ppc440spe_init_pcie())
- return -1;
- }
-
- /*
- * Initialize various parts of the PCI Express core for our port:
- *
- * - Set as a end port and enable max width
- * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4).
- * - Set up UTL configuration.
- * - Increase SERDES drive strength to levels suggested by AMCC.
- * - De-assert RSTPYN, RSTDL and RSTGU.
- *
- * NOTICE for revB chip: PESDRn_UTLSET2 is not set - we leave it with
- * default setting 0x11310000. The register has new fields,
- * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core
- * hang.
- */
- switch (port) {
- case 0:
- SDR_WRITE(PESDR0_DLPSET, 1 << 24 | PTYPE_LEGACY_ENDPOINT << 20 | LNKW_X8 << 12);
-
- SDR_WRITE(PESDR0_UTLSET1, 0x20222222);
- if (!ppc440spe_revB())
- SDR_WRITE(PESDR0_UTLSET2, 0x11000000);
- SDR_WRITE(PESDR0_HSSL0SET1, 0x35000000);
- SDR_WRITE(PESDR0_HSSL1SET1, 0x35000000);
- SDR_WRITE(PESDR0_HSSL2SET1, 0x35000000);
- SDR_WRITE(PESDR0_HSSL3SET1, 0x35000000);
- SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000);
- SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000);
- SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000);
- SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000);
- SDR_WRITE(PESDR0_RCSSET,
- (SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
- break;
-
- case 1:
- SDR_WRITE(PESDR1_DLPSET, 1 << 24 | PTYPE_LEGACY_ENDPOINT << 20 | LNKW_X4 << 12);
- SDR_WRITE(PESDR1_UTLSET1, 0x20222222);
- if (!ppc440spe_revB())
- SDR_WRITE(PESDR1_UTLSET2, 0x11000000);
- SDR_WRITE(PESDR1_HSSL0SET1, 0x35000000);
- SDR_WRITE(PESDR1_HSSL1SET1, 0x35000000);
- SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000);
- SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000);
- SDR_WRITE(PESDR1_RCSSET,
- (SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
- break;
-
- case 2:
- SDR_WRITE(PESDR2_DLPSET, 1 << 24 | PTYPE_LEGACY_ENDPOINT << 20 | LNKW_X4 << 12);
- SDR_WRITE(PESDR2_UTLSET1, 0x20222222);
- if (!ppc440spe_revB())
- SDR_WRITE(PESDR2_UTLSET2, 0x11000000);
- SDR_WRITE(PESDR2_HSSL0SET1, 0x35000000);
- SDR_WRITE(PESDR2_HSSL1SET1, 0x35000000);
- SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000);
- SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000);
- SDR_WRITE(PESDR2_RCSSET,
- (SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
- break;
- }
- /*
- * Notice: the following delay has critical impact on device
- * initialization - if too short (<50ms) the link doesn't get up.
- */
- mdelay(100);
-
- switch (port) {
- case 0: val = SDR_READ(PESDR0_RCSSTS); break;
- case 1: val = SDR_READ(PESDR1_RCSSTS); break;
- case 2: val = SDR_READ(PESDR2_RCSSTS); break;
- }
-
- if (val & (1 << 20)) {
- printf("PCIE%d: PGRST failed %08x\n", port, val);
- return -1;
- }
-
- /*
- * Verify link is up
- */
- val = 0;
- switch (port)
- {
- case 0:
- val = SDR_READ(PESDR0_LOOP);
- break;
- case 1:
- val = SDR_READ(PESDR1_LOOP);
- break;
- case 2:
- val = SDR_READ(PESDR2_LOOP);
- break;
- }
- if (!(val & 0x00001000)) {
- printf("PCIE%d: link is not up.\n", port);
- return -1;
- }
-
- /*
- * Setup UTL registers - but only on revA!
- * We use default settings for revB chip.
- */
- if (!ppc440spe_revB())
- ppc440spe_setup_utl(port);
-
- /*
- * We map PCI Express configuration access into the 512MB regions
- *
- * NOTICE: revB is very strict about PLB real addressess and ranges to
- * be mapped for config space; it seems to only work with d_nnnn_nnnn
- * range (hangs the core upon config transaction attempts when set
- * otherwise) while revA uses c_nnnn_nnnn.
- *
- * For revA:
- * PCIE0: 0xc_4000_0000
- * PCIE1: 0xc_8000_0000
- * PCIE2: 0xc_c000_0000
- *
- * For revB:
- * PCIE0: 0xd_0000_0000
- * PCIE1: 0xd_2000_0000
- * PCIE2: 0xd_4000_0000
- */
- switch (port) {
- case 0:
- if (ppc440spe_revB()) {
- mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000d);
- mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x00000000);
- } else {
- /* revA */
- mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000c);
- mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x40000000);
- }
- mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */
- break;
-
- case 1:
- if (ppc440spe_revB()) {
- mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000d);
- mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x20000000);
- } else {
- mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000c);
- mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x80000000);
- }
- mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
- break;
-
- case 2:
- if (ppc440spe_revB()) {
- mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000d);
- mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0x40000000);
- } else {
- mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000c);
- mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0xc0000000);
- }
- mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */
- break;
- }
-
- /*
- * Check for VC0 active and assert RDY.
- */
- attempts = 10;
- switch (port) {
- case 0:
- while(!(SDR_READ(PESDR0_RCSSTS) & (1 << 16))) {
- if (!(attempts--)) {
- printf("PCIE0: VC0 not active\n");
- return -1;
- }
- mdelay(1000);
- }
- SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20);
- break;
- case 1:
- while(!(SDR_READ(PESDR1_RCSSTS) & (1 << 16))) {
- if (!(attempts--)) {
- printf("PCIE1: VC0 not active\n");
- return -1;
- }
- mdelay(1000);
- }
-
- SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20);
- break;
- case 2:
- while(!(SDR_READ(PESDR2_RCSSTS) & (1 << 16))) {
- if (!(attempts--)) {
- printf("PCIE2: VC0 not active\n");
- return -1;
- }
- mdelay(1000);
- }
-
- SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20);
- break;
- }
- mdelay(100);
-
- return 0;
-}
-
-void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port)
-{
- volatile void *mbase = NULL;
- volatile void *rmbase = NULL;
-
- pci_set_ops(hose,
- pcie_read_config_byte,
- pcie_read_config_word,
- pcie_read_config_dword,
- pcie_write_config_byte,
- pcie_write_config_word,
- pcie_write_config_dword);
-
- switch (port) {
- case 0:
- mbase = (u32 *)CFG_PCIE0_XCFGBASE;
- rmbase = (u32 *)CFG_PCIE0_CFGBASE;
- hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE;
- break;
- case 1:
- mbase = (u32 *)CFG_PCIE1_XCFGBASE;
- rmbase = (u32 *)CFG_PCIE1_CFGBASE;
- hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE;
- break;
- case 2:
- mbase = (u32 *)CFG_PCIE2_XCFGBASE;
- rmbase = (u32 *)CFG_PCIE2_CFGBASE;
- hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE;
- break;
- }
-
- /*
- * Set bus numbers on our root port
- */
- out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
- out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
- out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
-
- /*
- * Set up outbound translation to hose->mem_space from PLB
- * addresses at an offset of 0xd_0000_0000. We set the low
- * bits of the mask to 11 to turn off splitting into 8
- * subregions and to enable the outbound translation.
- */
- out_le32(mbase + PECFG_POM0LAH, 0x00000000);
- out_le32(mbase + PECFG_POM0LAL, 0x00000000);
-
- switch (port) {
- case 0:
- mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d);
- mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
- port * CFG_PCIE_MEMSIZE);
- mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
- mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
- ~(CFG_PCIE_MEMSIZE - 1) | 3);
- break;
- case 1:
- mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d);
- mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), (CFG_PCIE_MEMBASE +
- port * CFG_PCIE_MEMSIZE));
- mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
- mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
- ~(CFG_PCIE_MEMSIZE - 1) | 3);
- break;
- case 2:
- mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d);
- mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), (CFG_PCIE_MEMBASE +
- port * CFG_PCIE_MEMSIZE));
- mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
- mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
- ~(CFG_PCIE_MEMSIZE - 1) | 3);
- break;
- }
-
- /* Set up 16GB inbound memory window at 0 */
- out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
- out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
- out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc);
- out_le32(mbase + PECFG_BAR0LMPA, 0);
-
- out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
- out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
- out_le32(mbase + PECFG_PIM0LAL, 0);
- out_le32(mbase + PECFG_PIM0LAH, 0);
- out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
- out_le32(mbase + PECFG_PIM1LAH, 0x00000004);
- out_le32(mbase + PECFG_PIMEN, 0x1);
-
- /* Enable I/O, Mem, and Busmaster cycles */
- out_le16((u16 *)(mbase + PCI_COMMAND),
- in_le16((u16 *)(mbase + PCI_COMMAND)) |
- PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
- printf("PCIE:%d successfully set as rootpoint\n",port);
-
- /* Set Device and Vendor Id */
- switch (port) {
- case 0:
- out_le16(mbase + 0x200, 0xaaa0);
- out_le16(mbase + 0x202, 0xbed0);
- break;
- case 1:
- out_le16(mbase + 0x200, 0xaaa1);
- out_le16(mbase + 0x202, 0xbed1);
- break;
- case 2:
- out_le16(mbase + 0x200, 0xaaa2);
- out_le16(mbase + 0x202, 0xbed2);
- break;
- default:
- out_le16(mbase + 0x200, 0xaaa3);
- out_le16(mbase + 0x202, 0xbed3);
- }
-
- /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
- out_le32(mbase + 0x208, 0x06040001);
-
-}
-
-int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port)
-{
- volatile void *mbase = NULL;
- int attempts = 0;
-
- pci_set_ops(hose,
- pcie_read_config_byte,
- pcie_read_config_word,
- pcie_read_config_dword,
- pcie_write_config_byte,
- pcie_write_config_word,
- pcie_write_config_dword);
-
- switch (port) {
- case 0:
- mbase = (u32 *)CFG_PCIE0_XCFGBASE;
- hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE;
- break;
- case 1:
- mbase = (u32 *)CFG_PCIE1_XCFGBASE;
- hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE;
- break;
- case 2:
- mbase = (u32 *)CFG_PCIE2_XCFGBASE;
- hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE;
- break;
- }
-
- /*
- * Set up outbound translation to hose->mem_space from PLB
- * addresses at an offset of 0xd_0000_0000. We set the low
- * bits of the mask to 11 to turn off splitting into 8
- * subregions and to enable the outbound translation.
- */
- out_le32(mbase + PECFG_POM0LAH, 0x00001ff8);
- out_le32(mbase + PECFG_POM0LAL, 0x00001000);
-
- switch (port) {
- case 0:
- mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d);
- mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
- port * CFG_PCIE_MEMSIZE);
- mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
- mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
- ~(CFG_PCIE_MEMSIZE - 1) | 3);
- break;
- case 1:
- mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d);
- mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), (CFG_PCIE_MEMBASE +
- port * CFG_PCIE_MEMSIZE));
- mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
- mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
- ~(CFG_PCIE_MEMSIZE - 1) | 3);
- break;
- case 2:
- mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d);
- mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), (CFG_PCIE_MEMBASE +
- port * CFG_PCIE_MEMSIZE));
- mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
- mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
- ~(CFG_PCIE_MEMSIZE - 1) | 3);
- break;
- }
-
- /* Set up 16GB inbound memory window at 0 */
- out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
- out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
- out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc);
- out_le32(mbase + PECFG_BAR0LMPA, 0);
- out_le32(mbase + PECFG_PIM0LAL, 0x00000000);
- out_le32(mbase + PECFG_PIM0LAH, 0x00000004); /* pointing to SRAM */
- out_le32(mbase + PECFG_PIMEN, 0x1);
-
- /* Enable I/O, Mem, and Busmaster cycles */
- out_le16((u16 *)(mbase + PCI_COMMAND),
- in_le16((u16 *)(mbase + PCI_COMMAND)) |
- PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
- out_le16(mbase + 0x200,0xcaad); /* Setting vendor ID */
- out_le16(mbase + 0x202,0xfeed); /* Setting device ID */
- attempts = 10;
- switch (port) {
- case 0:
- while (!(SDR_READ(PESDR0_RCSSTS) & (1 << 8))) {
- if (!(attempts--)) {
- printf("PCIE0: BMEN is not active\n");
- return -1;
- }
- mdelay(1000);
- }
- break;
- case 1:
- while (!(SDR_READ(PESDR1_RCSSTS) & (1 << 8))) {
- if (!(attempts--)) {
- printf("PCIE1: BMEN is not active\n");
- return -1;
- }
- mdelay(1000);
- }
- break;
- case 2:
- while (!(SDR_READ(PESDR2_RCSSTS) & (1 << 8))) {
- if (!(attempts--)) {
- printf("PCIE2: BMEN is not active\n");
- return -1;
- }
- mdelay(1000);
- }
- break;
- }
- printf("PCIE:%d successfully set as endpoint\n",port);
-
- return 0;
-}
-#endif /* CONFIG_440SPE && CONFIG_PCI */
+++ /dev/null
-/*
- * Copyright (c) 2005 Cisco Systems. All rights reserved.
- * Roland Dreier <rolandd@cisco.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#include <ppc4xx.h>
-#ifndef __440SPE_PCIE_H
-#define __440SPE_PCIE_H
-
-#define mdelay(n) ({unsigned long __ms=(n); while (__ms--) udelay(1000);})
-
-#define DCRN_SDR0_CFGADDR 0x00e
-#define DCRN_SDR0_CFGDATA 0x00f
-
-#define DCRN_PCIE0_BASE 0x100
-#define DCRN_PCIE1_BASE 0x120
-#define DCRN_PCIE2_BASE 0x140
-#define PCIE0 DCRN_PCIE0_BASE
-#define PCIE1 DCRN_PCIE1_BASE
-#define PCIE2 DCRN_PCIE2_BASE
-
-#define DCRN_PEGPL_CFGBAH(base) (base + 0x00)
-#define DCRN_PEGPL_CFGBAL(base) (base + 0x01)
-#define DCRN_PEGPL_CFGMSK(base) (base + 0x02)
-#define DCRN_PEGPL_MSGBAH(base) (base + 0x03)
-#define DCRN_PEGPL_MSGBAL(base) (base + 0x04)
-#define DCRN_PEGPL_MSGMSK(base) (base + 0x05)
-#define DCRN_PEGPL_OMR1BAH(base) (base + 0x06)
-#define DCRN_PEGPL_OMR1BAL(base) (base + 0x07)
-#define DCRN_PEGPL_OMR1MSKH(base) (base + 0x08)
-#define DCRN_PEGPL_OMR1MSKL(base) (base + 0x09)
-#define DCRN_PEGPL_REGBAH(base) (base + 0x12)
-#define DCRN_PEGPL_REGBAL(base) (base + 0x13)
-#define DCRN_PEGPL_REGMSK(base) (base + 0x14)
-#define DCRN_PEGPL_SPECIAL(base) (base + 0x15)
-#define DCRN_PEGPL_CFG(base) (base + 0x16)
-
-/*
- * System DCRs (SDRs)
- */
-#define PESDR0_PLLLCT1 0x03a0
-#define PESDR0_PLLLCT2 0x03a1
-#define PESDR0_PLLLCT3 0x03a2
-
-#define PESDR0_UTLSET1 0x0300
-#define PESDR0_UTLSET2 0x0301
-#define PESDR0_DLPSET 0x0302
-#define PESDR0_LOOP 0x0303
-#define PESDR0_RCSSET 0x0304
-#define PESDR0_RCSSTS 0x0305
-#define PESDR0_HSSL0SET1 0x0306
-#define PESDR0_HSSL0SET2 0x0307
-#define PESDR0_HSSL0STS 0x0308
-#define PESDR0_HSSL1SET1 0x0309
-#define PESDR0_HSSL1SET2 0x030a
-#define PESDR0_HSSL1STS 0x030b
-#define PESDR0_HSSL2SET1 0x030c
-#define PESDR0_HSSL2SET2 0x030d
-#define PESDR0_HSSL2STS 0x030e
-#define PESDR0_HSSL3SET1 0x030f
-#define PESDR0_HSSL3SET2 0x0310
-#define PESDR0_HSSL3STS 0x0311
-#define PESDR0_HSSL4SET1 0x0312
-#define PESDR0_HSSL4SET2 0x0313
-#define PESDR0_HSSL4STS 0x0314
-#define PESDR0_HSSL5SET1 0x0315
-#define PESDR0_HSSL5SET2 0x0316
-#define PESDR0_HSSL5STS 0x0317
-#define PESDR0_HSSL6SET1 0x0318
-#define PESDR0_HSSL6SET2 0x0319
-#define PESDR0_HSSL6STS 0x031a
-#define PESDR0_HSSL7SET1 0x031b
-#define PESDR0_HSSL7SET2 0x031c
-#define PESDR0_HSSL7STS 0x031d
-#define PESDR0_HSSCTLSET 0x031e
-#define PESDR0_LANE_ABCD 0x031f
-#define PESDR0_LANE_EFGH 0x0320
-
-#define PESDR1_UTLSET1 0x0340
-#define PESDR1_UTLSET2 0x0341
-#define PESDR1_DLPSET 0x0342
-#define PESDR1_LOOP 0x0343
-#define PESDR1_RCSSET 0x0344
-#define PESDR1_RCSSTS 0x0345
-#define PESDR1_HSSL0SET1 0x0346
-#define PESDR1_HSSL0SET2 0x0347
-#define PESDR1_HSSL0STS 0x0348
-#define PESDR1_HSSL1SET1 0x0349
-#define PESDR1_HSSL1SET2 0x034a
-#define PESDR1_HSSL1STS 0x034b
-#define PESDR1_HSSL2SET1 0x034c
-#define PESDR1_HSSL2SET2 0x034d
-#define PESDR1_HSSL2STS 0x034e
-#define PESDR1_HSSL3SET1 0x034f
-#define PESDR1_HSSL3SET2 0x0350
-#define PESDR1_HSSL3STS 0x0351
-#define PESDR1_HSSCTLSET 0x0352
-#define PESDR1_LANE_ABCD 0x0353
-
-#define PESDR2_UTLSET1 0x0370
-#define PESDR2_UTLSET2 0x0371
-#define PESDR2_DLPSET 0x0372
-#define PESDR2_LOOP 0x0373
-#define PESDR2_RCSSET 0x0374
-#define PESDR2_RCSSTS 0x0375
-#define PESDR2_HSSL0SET1 0x0376
-#define PESDR2_HSSL0SET2 0x0377
-#define PESDR2_HSSL0STS 0x0378
-#define PESDR2_HSSL1SET1 0x0379
-#define PESDR2_HSSL1SET2 0x037a
-#define PESDR2_HSSL1STS 0x037b
-#define PESDR2_HSSL2SET1 0x037c
-#define PESDR2_HSSL2SET2 0x037d
-#define PESDR2_HSSL2STS 0x037e
-#define PESDR2_HSSL3SET1 0x037f
-#define PESDR2_HSSL3SET2 0x0380
-#define PESDR2_HSSL3STS 0x0381
-#define PESDR2_HSSCTLSET 0x0382
-#define PESDR2_LANE_ABCD 0x0383
-
-/*
- * UTL register offsets
- */
-#define PEUTL_PBBSZ 0x20
-#define PEUTL_OPDBSZ 0x68
-#define PEUTL_IPHBSZ 0x70
-#define PEUTL_IPDBSZ 0x78
-#define PEUTL_OUTTR 0x90
-#define PEUTL_INTR 0x98
-#define PEUTL_PCTL 0xa0
-#define PEUTL_RCIRQEN 0xb8
-
-/*
- * Config space register offsets
- */
-#define PECFG_BAR0LMPA 0x210
-#define PECFG_BAR0HMPA 0x214
-#define PECFG_BAR1MPA 0x218
-#define PECFG_BAR2MPA 0x220
-
-#define PECFG_PIMEN 0x33c
-#define PECFG_PIM0LAL 0x340
-#define PECFG_PIM0LAH 0x344
-#define PECFG_PIM1LAL 0x348
-#define PECFG_PIM1LAH 0x34c
-#define PECFG_PIM01SAL 0x350
-#define PECFG_PIM01SAH 0x354
-
-#define PECFG_POM0LAL 0x380
-#define PECFG_POM0LAH 0x384
-
-#define SDR_READ(offset) ({\
- mtdcr(DCRN_SDR0_CFGADDR, offset); \
- mfdcr(DCRN_SDR0_CFGDATA);})
-
-#define SDR_WRITE(offset, data) ({\
- mtdcr(DCRN_SDR0_CFGADDR, offset); \
- mtdcr(DCRN_SDR0_CFGDATA,data);})
-
-#define GPL_DMER_MASK_DISA 0x02000000
-
-int ppc440spe_init_pcie(void);
-int ppc440spe_init_pcie_rootport(int port);
-void yucca_setup_pcie_fpga_rootpoint(int port);
-void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port);
-int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port);
-int yucca_pcie_card_present(int port);
-int pcie_hose_scan(struct pci_controller *hose, int bus);
-#endif /* __440SPE_PCIE_H */
* memory.
*
* If at some time this restriction doesn't apply anymore, just define
- * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup
+ * CONFIG_4xx_DCACHE in the board config file and this code should setup
* everything correctly.
*/
-#ifdef CFG_ENABLE_SDRAM_CACHE
+#ifdef CONFIG_4xx_DCACHE
#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
#else
#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
*/
check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
/*
* Soft-reset SDRAM controller.
*/
unsigned char refresh_rate_type;
unsigned long refresh_interval;
unsigned long sdram_rtr;
- PPC440_SYS_INFO sys_info;
+ PPC4xx_SYS_INFO sys_info;
/*
* get the board info
unsigned long tcyc_2_0_ns_x_10;
unsigned long tcyc_reg;
unsigned long bus_period_x_10;
- PPC440_SYS_INFO sys_info;
+ PPC4xx_SYS_INFO sys_info;
unsigned long residue;
/*
unsigned char window_found;
unsigned char fail_found;
unsigned char pass_found;
- PPC440_SYS_INFO sys_info;
+ PPC4xx_SYS_INFO sys_info;
/*
* get the board info
}
rdclt_average = ((max_start + max_end) >> 1);
- if (rdclt_average >= 0x60)
- while (1)
- ;
if (rdclt_average < 0) {
rdclt_average = 0;
* memory.
*
* If at some time this restriction doesn't apply anymore, just define
- * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup
+ * CONFIG_4xx_DCACHE in the board config file and this code should setup
* everything correctly.
*/
-#ifdef CFG_ENABLE_SDRAM_CACHE
+#ifdef CONFIG_4xx_DCACHE
#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
#else
#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
void board_add_ram_info(int use_default)
{
- PPC440_SYS_INFO board_cfg;
+ PPC4xx_SYS_INFO board_cfg;
u32 val;
if (is_ecc_enabled())
unsigned long calc_cycle_time;
unsigned long sdram_freq;
unsigned long sdr_ddrpll;
- PPC440_SYS_INFO board_cfg;
+ PPC4xx_SYS_INFO board_cfg;
/*------------------------------------------------------------------
* Get the board configuration info.
unsigned long max_4_0_tcyc_ns_x_100;
unsigned long max_5_0_tcyc_ns_x_100;
unsigned long cycle_time_ns_x_100[3];
- PPC440_SYS_INFO board_cfg;
+ PPC4xx_SYS_INFO board_cfg;
unsigned char cas_2_0_available;
unsigned char cas_2_5_available;
unsigned char cas_3_0_available;
unsigned char *iic0_dimm_addr,
unsigned long num_dimm_banks)
{
- PPC440_SYS_INFO board_cfg;
+ PPC4xx_SYS_INFO board_cfg;
unsigned long max_refresh_rate;
unsigned long dimm_num;
unsigned long refresh_rate_type;
unsigned long sdram_freq;
unsigned long sdr_ddrpll;
- PPC440_SYS_INFO board_cfg;
+ PPC4xx_SYS_INFO board_cfg;
/*------------------------------------------------------------------
* Get the board configuration info.
/*------------------------------------------------------------------
* Set the BxCF regs. First, wipe out the bank config registers.
*-----------------------------------------------------------------*/
- mtdcr(SDRAMC_CFGADDR, SDRAM_MB0CF);
- mtdcr(SDRAMC_CFGDATA, 0x00000000);
- mtdcr(SDRAMC_CFGADDR, SDRAM_MB1CF);
- mtdcr(SDRAMC_CFGDATA, 0x00000000);
- mtdcr(SDRAMC_CFGADDR, SDRAM_MB2CF);
- mtdcr(SDRAMC_CFGDATA, 0x00000000);
- mtdcr(SDRAMC_CFGADDR, SDRAM_MB3CF);
- mtdcr(SDRAMC_CFGDATA, 0x00000000);
+ mtsdram(SDRAM_MB0CF, 0x00000000);
+ mtsdram(SDRAM_MB1CF, 0x00000000);
+ mtsdram(SDRAM_MB2CF, 0x00000000);
+ mtsdram(SDRAM_MB3CF, 0x00000000);
mode = SDRAM_BXCF_M_BE_ENABLE;
bank_0_populated = 1;
for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
- mtdcr(SDRAMC_CFGADDR, SDRAM_MB0CF + ((dimm_num + bank_0_populated + ind_rank) << 2));
- mtdcr(SDRAMC_CFGDATA, mode);
+ mtsdram(SDRAM_MB0CF +
+ ((dimm_num + bank_0_populated + ind_rank) << 2),
+ mode);
}
}
}
#include <common.h>
#include <net.h>
#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
#include <commproc.h>
#include <ppc4xx.h>
#include <ppc4xx_enet.h>
#endif
#define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
-#define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */
+#define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* 5000 ms autonegotiate timeout */
/* Ethernet Transmit and Receive Buffers */
/* AS.HARNOIS
#define BI_PHYMODE_GMII 3
#define BI_PHYMODE_RTBI 4
#define BI_PHYMODE_TBI 5
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_405EX)
#define BI_PHYMODE_SMII 6
#define BI_PHYMODE_MII 7
#endif
-#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || \
- defined(CONFIG_440GRX) || defined(CONFIG_440SP)
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_405EX)
#define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
#endif
/*
* Get count of EMAC devices (doesn't have to be the max. possible number
* supported by the cpu)
+ *
+ * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the
+ * EMAC count is possible. As it is needed for the Kilauea/Haleakala
+ * 405EX/405EXr eval board, using the same binary.
*/
+#if defined(CONFIG_BOARD_EMAC_COUNT)
+#define LAST_EMAC_NUM board_emac_count()
+#else /* CONFIG_BOARD_EMAC_COUNT */
#if defined(CONFIG_HAS_ETH3)
#define LAST_EMAC_NUM 4
#elif defined(CONFIG_HAS_ETH2)
#else
#define LAST_EMAC_NUM 1
#endif
+#endif /* CONFIG_BOARD_EMAC_COUNT */
/* normal boards start with EMAC0 */
#if !defined(CONFIG_EMAC_NR_START)
#define CONFIG_EMAC_NR_START 0
#endif
+#if defined(CONFIG_405EX) || defined(CONFIG_440EPX)
+#define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev)))
+#else
+#define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev) * 2))
+#endif
+
+#define MAL_RX_DESC_SIZE 2048
+#define MAL_TX_DESC_SIZE 2048
+#define MAL_ALLOC_SIZE (MAL_TX_DESC_SIZE + MAL_RX_DESC_SIZE)
+
/*-----------------------------------------------------------------------------+
* Prototypes and externals.
*-----------------------------------------------------------------------------*/
extern int emac4xx_miiphy_write (char *devname, unsigned char addr,
unsigned char reg, unsigned short value);
+int board_emac_count(void);
+
/*-----------------------------------------------------------------------------+
| ppc_4xx_eth_halt
| Disable MAL channel, and EMACn
{
EMAC_4XX_HW_PST hw_p = dev->priv;
uint32_t failsafe = 10000;
-#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#if defined(CONFIG_440SPE) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_405EX)
unsigned long mfr;
#endif
- out32 (EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
+ out_be32((void *)EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
/* 1st reset MAL channel */
/* Note: writing a 0 to a channel has no effect */
}
/* EMAC RESET */
-#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#if defined(CONFIG_440SPE) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_405EX)
/* provide clocks for EMAC internal loopback */
mfsdr (sdr_mfr, mfr);
mfr |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
mtsdr(sdr_mfr, mfr);
#endif
- out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
+ out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
-#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#if defined(CONFIG_440SPE) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_405EX)
/* remove clocks for EMAC internal loopback */
mfsdr (sdr_mfr, mfr);
mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
/* Ensure we setup mdio for this devnum and ONLY this devnum */
zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
- out32 (ZMII_FER, zmiifer);
- out32 (RGMII_FER, rmiifer);
+ out_be32((void *)ZMII_FER, zmiifer);
+ out_be32((void *)RGMII_FER, rmiifer);
return ((int)pfc1);
}
switch (pfc1) {
case SDR0_PFC1_SELECT_CONFIG_2:
/* 1 x GMII port */
- out32 (ZMII_FER, 0x00);
- out32 (RGMII_FER, 0x00000037);
+ out_be32((void *)ZMII_FER, 0x00);
+ out_be32((void *)RGMII_FER, 0x00000037);
bis->bi_phymode[0] = BI_PHYMODE_GMII;
bis->bi_phymode[1] = BI_PHYMODE_NONE;
break;
case SDR0_PFC1_SELECT_CONFIG_4:
/* 2 x RGMII ports */
- out32 (ZMII_FER, 0x00);
- out32 (RGMII_FER, 0x00000055);
+ out_be32((void *)ZMII_FER, 0x00);
+ out_be32((void *)RGMII_FER, 0x00000055);
bis->bi_phymode[0] = BI_PHYMODE_RGMII;
bis->bi_phymode[1] = BI_PHYMODE_RGMII;
break;
case SDR0_PFC1_SELECT_CONFIG_6:
/* 2 x SMII ports */
- out32 (ZMII_FER,
- ((ZMII_FER_SMII) << ZMII_FER_V(0)) |
- ((ZMII_FER_SMII) << ZMII_FER_V(1)));
- out32 (RGMII_FER, 0x00000000);
+ out_be32((void *)ZMII_FER,
+ ((ZMII_FER_SMII) << ZMII_FER_V(0)) |
+ ((ZMII_FER_SMII) << ZMII_FER_V(1)));
+ out_be32((void *)RGMII_FER, 0x00000000);
bis->bi_phymode[0] = BI_PHYMODE_SMII;
bis->bi_phymode[1] = BI_PHYMODE_SMII;
break;
case SDR0_PFC1_SELECT_CONFIG_1_2:
/* only 1 x MII supported */
- out32 (ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0));
- out32 (RGMII_FER, 0x00000000);
+ out_be32((void *)ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0));
+ out_be32((void *)RGMII_FER, 0x00000000);
bis->bi_phymode[0] = BI_PHYMODE_MII;
bis->bi_phymode[1] = BI_PHYMODE_NONE;
break;
}
/* Ensure we setup mdio for this devnum and ONLY this devnum */
- zmiifer = in32 (ZMII_FER);
+ zmiifer = in_be32((void *)ZMII_FER);
zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
- out32 (ZMII_FER, zmiifer);
+ out_be32((void *)ZMII_FER, zmiifer);
return ((int)0x0);
}
#endif /* CONFIG_440EPX */
+#if defined(CONFIG_405EX)
+int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
+{
+ u32 gmiifer = 0;
+
+ /*
+ * Right now only 2*RGMII is supported. Please extend when needed.
+ * sr - 2007-09-19
+ */
+ switch (1) {
+ case 1:
+ /* 2 x RGMII ports */
+ out_be32((void *)RGMII_FER, 0x00000055);
+ bis->bi_phymode[0] = BI_PHYMODE_RGMII;
+ bis->bi_phymode[1] = BI_PHYMODE_RGMII;
+ break;
+ case 2:
+ /* 2 x SMII ports */
+ break;
+ default:
+ break;
+ }
+
+ /* Ensure we setup mdio for this devnum and ONLY this devnum */
+ gmiifer = in_be32((void *)RGMII_FER);
+ gmiifer |= (1 << (19-devnum));
+ out_be32((void *)RGMII_FER, gmiifer);
+
+ return ((int)0x0);
+}
+#endif /* CONFIG_405EX */
+
+static inline void *malloc_aligned(u32 size, u32 align)
+{
+ return (void *)(((u32)malloc(size + align) + align - 1) &
+ ~(align - 1));
+}
+
static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
{
- int i, j;
+ int i;
unsigned long reg = 0;
unsigned long msr;
unsigned long speed;
unsigned short reg_short;
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_405EX)
sys_info_t sysinfo;
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_405EX)
int ethgroup = -1;
#endif
#endif
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_405EX)
unsigned long mfr;
#endif
-
+ u32 bd_cached;
+ u32 bd_uncached = 0;
EMAC_4XX_HW_PST hw_p = dev->priv;
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_405EX)
/* Need to get the OPB frequency so we can access the PHY */
get_sys_info (&sysinfo);
#endif
/* NOTE: Therefore, disable all other EMACS, since we handle */
/* NOTE: only one emac at a time */
reg = 0;
- out32 (ZMII_FER, 0);
+ out_be32((void *)ZMII_FER, 0);
udelay (100);
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
- out32 (ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
+ out_be32((void *)ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
#elif defined(CONFIG_440GX) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
#elif defined(CONFIG_440GP)
/* set RMII mode */
- out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
+ out_be32((void *)ZMII_FER, ZMII_RMII | ZMII_MDI0);
#else
if ((devnum == 0) || (devnum == 1)) {
- out32 (ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
+ out_be32((void *)ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
} else { /* ((devnum == 2) || (devnum == 3)) */
- out32 (ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum));
- out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) |
- (RGMII_FER_RGMII << RGMII_FER_V (3))));
+ out_be32((void *)ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum));
+ out_be32((void *)RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) |
+ (RGMII_FER_RGMII << RGMII_FER_V (3))));
}
#endif
- out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
+ out_be32((void *)ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
+#if defined(CONFIG_405EX)
+ ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
+#endif
__asm__ volatile ("eieio");
/* reset emac so we have access to the phy */
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_405EX)
/* provide clocks for EMAC internal loopback */
mfsdr (sdr_mfr, mfr);
mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum);
mtsdr(sdr_mfr, mfr);
#endif
- out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
- __asm__ volatile ("eieio");
+ out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
failsafe = 1000;
- while ((in32 (EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
+ while ((in_be32((void *)EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
udelay (1000);
failsafe--;
}
if (failsafe <= 0)
printf("\nProblem resetting EMAC!\n");
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_405EX)
/* remove clocks for EMAC internal loopback */
mfsdr (sdr_mfr, mfr);
mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum);
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_405EX)
/* Whack the M1 register */
mode_reg = 0x0;
mode_reg &= ~0x00000038;
else
mode_reg |= EMAC_M1_OBCI_GT100;
- out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
+ out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg);
#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
/* wait for PHY to complete auto negotiation */
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_405EX)
#if defined(CONFIG_CIS8201_PHY)
/*
#endif
/* Set ZMII/RGMII speed according to the phy link speed */
- reg = in32 (ZMII_SSR);
+ reg = in_be32((void *)ZMII_SSR);
if ( (speed == 100) || (speed == 1000) )
- out32 (ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum)));
+ out_be32((void *)ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum)));
else
- out32 (ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
+ out_be32((void *)ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
if ((devnum == 2) || (devnum == 3)) {
if (speed == 1000)
printf("Error in RGMII Speed\n");
return -1;
}
- out32 (RGMII_SSR, reg);
+ out_be32((void *)RGMII_SSR, reg);
}
#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_405EX)
if (speed == 1000)
reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
else if (speed == 100)
printf("Error in RGMII Speed\n");
return -1;
}
- out32 (RGMII_SSR, reg);
+ out_be32((void *)RGMII_SSR, reg);
#endif
/* set the Mal configuration reg */
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_405EX)
mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
#else
}
#endif
- /* Free "old" buffers */
- if (hw_p->alloc_tx_buf)
- free (hw_p->alloc_tx_buf);
- if (hw_p->alloc_rx_buf)
- free (hw_p->alloc_rx_buf);
-
/*
* Malloc MAL buffer desciptors, make sure they are
* aligned on cache line boundary size
* (401/403/IOP480 = 16, 405 = 32)
* and doesn't cross cache block boundaries.
*/
- hw_p->alloc_tx_buf =
- (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_TX_BUFF) +
- ((2 * CFG_CACHELINE_SIZE) - 2));
- if (NULL == hw_p->alloc_tx_buf)
- return -1;
- if (((int) hw_p->alloc_tx_buf & CACHELINE_MASK) != 0) {
- hw_p->tx =
- (mal_desc_t *) ((int) hw_p->alloc_tx_buf +
- CFG_CACHELINE_SIZE -
- ((int) hw_p->
- alloc_tx_buf & CACHELINE_MASK));
- } else {
- hw_p->tx = hw_p->alloc_tx_buf;
- }
+ if (hw_p->first_init == 0) {
+ debug("*** Allocating descriptor memory ***\n");
- hw_p->alloc_rx_buf =
- (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_RX_BUFF) +
- ((2 * CFG_CACHELINE_SIZE) - 2));
- if (NULL == hw_p->alloc_rx_buf) {
- free(hw_p->alloc_tx_buf);
- hw_p->alloc_tx_buf = NULL;
- return -1;
- }
+ bd_cached = (u32)malloc_aligned(MAL_ALLOC_SIZE, 4096);
+ if (!bd_cached) {
+ printf("%s: Error allocating MAL descriptor buffers!\n");
+ return -1;
+ }
- if (((int) hw_p->alloc_rx_buf & CACHELINE_MASK) != 0) {
- hw_p->rx =
- (mal_desc_t *) ((int) hw_p->alloc_rx_buf +
- CFG_CACHELINE_SIZE -
- ((int) hw_p->
- alloc_rx_buf & CACHELINE_MASK));
- } else {
- hw_p->rx = hw_p->alloc_rx_buf;
+#ifdef CONFIG_4xx_DCACHE
+ flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE);
+ bd_uncached = bis->bi_memsize;
+ program_tlb(bd_cached, bd_uncached, MAL_ALLOC_SIZE,
+ TLB_WORD2_I_ENABLE);
+#else
+ bd_uncached = bd_cached;
+#endif
+ hw_p->tx_phys = bd_cached;
+ hw_p->rx_phys = bd_cached + MAL_TX_DESC_SIZE;
+ hw_p->tx = (mal_desc_t *)(bd_uncached);
+ hw_p->rx = (mal_desc_t *)(bd_uncached + MAL_TX_DESC_SIZE);
+ debug("hw_p->tx=%08x, hw_p->rx=%08x\n", hw_p->tx, hw_p->rx);
}
for (i = 0; i < NUM_TX_BUFF; i++) {
hw_p->tx[i].ctrl = 0;
hw_p->tx[i].data_len = 0;
- if (hw_p->first_init == 0) {
- hw_p->txbuf_ptr =
- (char *) malloc (ENET_MAX_MTU_ALIGNED);
- if (NULL == hw_p->txbuf_ptr) {
- free(hw_p->alloc_rx_buf);
- free(hw_p->alloc_tx_buf);
- hw_p->alloc_rx_buf = NULL;
- hw_p->alloc_tx_buf = NULL;
- for(j = 0; j < i; j++) {
- free(hw_p->tx[i].data_ptr);
- hw_p->tx[i].data_ptr = NULL;
- }
- }
- }
+ if (hw_p->first_init == 0)
+ hw_p->txbuf_ptr = malloc_aligned(MAL_ALLOC_SIZE,
+ L1_CACHE_BYTES);
hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
if ((NUM_TX_BUFF - 1) == i)
hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
hw_p->tx_run[i] = -1;
-#if 0
- printf ("TX_BUFF %d @ 0x%08lx\n", i,
- (ulong) hw_p->tx[i].data_ptr);
-#endif
+ debug("TX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->tx[i].data_ptr);
}
for (i = 0; i < NUM_RX_BUFF; i++) {
hw_p->rx[i].ctrl = 0;
hw_p->rx[i].data_len = 0;
- /* rx[i].data_ptr = (char *) &rx_buff[i]; */
- hw_p->rx[i].data_ptr = (char *) NetRxPackets[i];
+ hw_p->rx[i].data_ptr = (char *)NetRxPackets[i];
if ((NUM_RX_BUFF - 1) == i)
hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
hw_p->rx_ready[i] = -1;
-#if 0
- printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) hw_p->rx[i].data_ptr);
-#endif
+ debug("RX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->rx[i].data_ptr);
}
reg = 0x00000000;
reg = reg << 8;
reg |= dev->enetaddr[1];
- out32 (EMAC_IAH + hw_p->hw_addr, reg);
+ out_be32((void *)EMAC_IAH + hw_p->hw_addr, reg);
reg = 0x00000000;
reg |= dev->enetaddr[2]; /* set low address */
reg = reg << 8;
reg |= dev->enetaddr[5];
- out32 (EMAC_IAL + hw_p->hw_addr, reg);
+ out_be32((void *)EMAC_IAL + hw_p->hw_addr, reg);
switch (devnum) {
case 1:
/* setup MAL tx & rx channel pointers */
#if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
- mtdcr (maltxctp2r, hw_p->tx);
+ mtdcr (maltxctp2r, hw_p->tx_phys);
#else
- mtdcr (maltxctp1r, hw_p->tx);
+ mtdcr (maltxctp1r, hw_p->tx_phys);
#endif
#if defined(CONFIG_440)
mtdcr (maltxbattr, 0x0);
mtdcr (malrxbattr, 0x0);
#endif
- mtdcr (malrxctp1r, hw_p->rx);
+ mtdcr (malrxctp1r, hw_p->rx_phys);
/* set RX buffer size */
mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
break;
/* setup MAL tx & rx channel pointers */
mtdcr (maltxbattr, 0x0);
mtdcr (malrxbattr, 0x0);
- mtdcr (maltxctp2r, hw_p->tx);
- mtdcr (malrxctp2r, hw_p->rx);
+ mtdcr (maltxctp2r, hw_p->tx_phys);
+ mtdcr (malrxctp2r, hw_p->rx_phys);
/* set RX buffer size */
mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16);
break;
case 3:
/* setup MAL tx & rx channel pointers */
mtdcr (maltxbattr, 0x0);
- mtdcr (maltxctp3r, hw_p->tx);
+ mtdcr (maltxctp3r, hw_p->tx_phys);
mtdcr (malrxbattr, 0x0);
- mtdcr (malrxctp3r, hw_p->rx);
+ mtdcr (malrxctp3r, hw_p->rx_phys);
/* set RX buffer size */
mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
break;
mtdcr (maltxbattr, 0x0);
mtdcr (malrxbattr, 0x0);
#endif
- mtdcr (maltxctp0r, hw_p->tx);
- mtdcr (malrxctp0r, hw_p->rx);
+ mtdcr (maltxctp0r, hw_p->tx_phys);
+ mtdcr (malrxctp0r, hw_p->rx_phys);
/* set RX buffer size */
mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
break;
mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
/* set transmit enable & receive enable */
- out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
+ out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
/* set receive fifo to 4k and tx fifo to 2k */
- mode_reg = in32 (EMAC_M1 + hw_p->hw_addr);
+ mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr);
mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
/* set speed */
if (duplex == FULL)
mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
- out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
+ out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg);
/* Enable broadcast and indvidual address */
/* TBS: enabling runts as some misbehaved nics will send runts */
- out32 (EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
+ out_be32((void *)EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
/* we probably need to set the tx mode1 reg? maybe at tx time */
/* set transmit request threshold register */
- out32 (EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
+ out_be32((void *)EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
/* set receive low/high water mark register */
#if defined(CONFIG_440)
/* 440s has a 64 byte burst length */
- out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
+ out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
#else
/* 405s have a 16 byte burst length */
- out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
+ out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
#endif /* defined(CONFIG_440) */
- out32 (EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
+ out_be32((void *)EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
/* Set fifo limit entry in tx mode 0 */
- out32 (EMAC_TXM0 + hw_p->hw_addr, 0x00000003);
+ out_be32((void *)EMAC_TXM0 + hw_p->hw_addr, 0x00000003);
/* Frame gap set */
- out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
+ out_be32((void *)EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
/* Set EMAC IER */
hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE;
if (speed == _100BASET)
hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
- out32 (EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
- out32 (EMAC_IER + hw_p->hw_addr, hw_p->emac_ier);
+ out_be32((void *)EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
+ out_be32((void *)EMAC_IER + hw_p->hw_addr, hw_p->emac_ier);
if (hw_p->first_init == 0) {
/*
* Connect interrupt service routines
*/
- irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2),
- (interrupt_handler_t *) enetInt, dev);
+ irq_install_handler(ETH_IRQ_NUM(hw_p->devnum),
+ (interrupt_handler_t *) enetInt, dev);
}
mtmsr (msr); /* enable interrupts again */
/* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
+ flush_dcache_range((u32)hw_p->txbuf_ptr, (u32)hw_p->txbuf_ptr + len);
/*-----------------------------------------------------------------------+
* set TX Buffer busy, and send it
__asm__ volatile ("eieio");
- out32 (EMAC_TXM0 + hw_p->hw_addr,
- in32 (EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
+ out_be32((void *)EMAC_TXM0 + hw_p->hw_addr,
+ in_be32((void *)EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
#ifdef INFO_4XX_ENET
hw_p->stats.pkts_tx++;
#endif
*-----------------------------------------------------------------------*/
time_start = get_timer (0);
while (1) {
- temp_txm0 = in32 (EMAC_TXM0 + hw_p->hw_addr);
+ temp_txm0 = in_be32((void *)EMAC_TXM0 + hw_p->hw_addr);
/* loop until either TINT turns on or 3 seconds elapse */
if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
/* transmit is done, so now check for errors
}
-#if defined (CONFIG_440)
+#if defined (CONFIG_440) || defined(CONFIG_405EX)
#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
/*
#define UIC0SR uic0sr
#endif
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_405EX)
#define UICMSR_ETHX uic0msr
#define UICSR_ETHX uic0sr
#else
/* port by port dispatch of emac interrupts */
if (hw_p->devnum == 0) {
if (UIC_ETH0 & my_uicmsr_ethx) { /* look for EMAC errors */
- emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
+ emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
if ((hw_p->emac_ier & emac_isr) != 0) {
emac_err (dev, emac_isr);
serviced = 1;
#if !defined(CONFIG_440SP)
if (hw_p->devnum == 1) {
if (UIC_ETH1 & my_uicmsr_ethx) { /* look for EMAC errors */
- emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
+ emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
if ((hw_p->emac_ier & emac_isr) != 0) {
emac_err (dev, emac_isr);
serviced = 1;
#if defined (CONFIG_440GX)
if (hw_p->devnum == 2) {
if (UIC_ETH2 & my_uic2msr) { /* look for EMAC errors */
- emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
+ emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
if ((hw_p->emac_ier & emac_isr) != 0) {
emac_err (dev, emac_isr);
serviced = 1;
if (hw_p->devnum == 3) {
if (UIC_ETH3 & my_uic2msr) { /* look for EMAC errors */
- emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
+ emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
if ((hw_p->emac_ier & emac_isr) != 0) {
emac_err (dev, emac_isr);
serviced = 1;
/* port by port dispatch of emac interrupts */
if ((SEL_UIC_DEF(hw_p->devnum) & my_uicmsr) != 0) { /* look for EMAC errors */
- emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
+ emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
if ((hw_p->emac_ier & emac_isr) != 0) {
emac_err (dev, emac_isr);
serviced = 1;
EMAC_4XX_HW_PST hw_p = dev->priv;
printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
- out32 (EMAC_ISR + hw_p->hw_addr, isr);
+ out_be32((void *)EMAC_ISR + hw_p->hw_addr, isr);
}
/*-----------------------------------------------------------------------------+
/* Pass the packet up to the protocol layers. */
/* NetReceive(NetRxPackets[rxIdx], length - 4); */
/* NetReceive(NetRxPackets[i], length); */
+ invalidate_dcache_range((u32)hw_p->rx[user_index].data_ptr,
+ (u32)hw_p->rx[user_index].data_ptr +
+ length - 4);
NetReceive (NetRxPackets[user_index], length - 4);
/* Free Recv Buffer */
hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
bis->bi_phymode[2] = 2;
bis->bi_phymode[3] = 2;
+#endif
+#if defined(CONFIG_440GX) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_405EX)
ppc_4xx_eth_setup_bridge(0, bis);
#endif
if (0 == virgin) {
/* set the MAL IER ??? names may change with new spec ??? */
-#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#if defined(CONFIG_440SPE) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_405EX)
mal_ier =
MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE |
MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ;
--- /dev/null
+/*-----------------------------------------------------------------------------+
+ *
+ * This source code has been made available to you by IBM on an AS-IS
+ * basis. Anyone receiving this source is licensed under IBM
+ * copyrights to use it in any way he or she deems fit, including
+ * copying it, modifying it, compiling it, and redistributing it either
+ * with or without modifications. No license under IBM patents or
+ * patent applications is to be implied by the copyright license.
+ *
+ * Any user of this software should understand that IBM cannot provide
+ * technical support for this software and will not be responsible for
+ * any consequences resulting from the use of this software.
+ *
+ * Any person who transfers this source code or any derivative work
+ * must include the IBM copyright notice, this paragraph, and the
+ * preceding two paragraphs in the transferred software.
+ *
+ * COPYRIGHT I B M CORPORATION 1995
+ * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
+ *-----------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------+
+ *
+ * File Name: 405gp_pci.c
+ *
+ * Function: Initialization code for the 405GP PCI Configuration regs.
+ *
+ * Author: Mark Game
+ *
+ * Change Activity-
+ *
+ * Date Description of Change BY
+ * --------- --------------------- ---
+ * 09-Sep-98 Created MCG
+ * 02-Nov-98 Removed External arbiter selected message JWB
+ * 27-Nov-98 Zero out PTMBAR2 and disable in PTM2MS JWB
+ * 04-Jan-99 Zero out other unused PMM and PTM regs. Change bus scan MCG
+ * from (0 to n) to (1 to n).
+ * 17-May-99 Port to Walnut JWB
+ * 17-Jun-99 Updated for VGA support JWB
+ * 21-Jun-99 Updated to allow SRAM region to be a target from PCI bus JWB
+ * 19-Jul-99 Updated for 405GP pass 1 errata #26 (Low PCI subsequent MCG
+ * target latency timer values are not supported).
+ * Should be fixed in pass 2.
+ * 09-Sep-99 Removed use of PTM2 since the SRAM region no longer needs JWB
+ * to be a PCI target. Zero out PTMBAR2 and disable in PTM2MS.
+ * 10-Dec-99 Updated PCI_Write_CFG_Reg for pass2 errata #6 JWB
+ * 11-Jan-00 Ensure PMMxMAs disabled before setting PMMxLAs. This is not
+ * really required after a reset since PMMxMAs are already
+ * disabled but is a good practice nonetheless. JWB
+ * 12-Jun-01 stefan.roese@esd-electronics.com
+ * - PCI host/adapter handling reworked
+ * 09-Jul-01 stefan.roese@esd-electronics.com
+ * - PCI host now configures from device 0 (not 1) to max_dev,
+ * (host configures itself)
+ * - On CPCI-405 pci base address and size is generated from
+ * SDRAM and FLASH size (CFG regs not used anymore)
+ * - Some minor changes for CPCI-405-A (adapter version)
+ * 14-Sep-01 stefan.roese@esd-electronics.com
+ * - CONFIG_PCI_SCAN_SHOW added to print pci devices upon startup
+ * 28-Sep-01 stefan.roese@esd-electronics.com
+ * - Changed pci master configuration for linux compatibility
+ * (no need for bios_fixup() anymore)
+ * 26-Feb-02 stefan.roese@esd-electronics.com
+ * - Bug fixed in pci configuration (Andrew May)
+ * - Removed pci class code init for CPCI405 board
+ * 15-May-02 stefan.roese@esd-electronics.com
+ * - New vga device handling
+ * 29-May-02 stefan.roese@esd-electronics.com
+ * - PCI class code init added (if defined)
+ *----------------------------------------------------------------------------*/
+
+#include <common.h>
+#include <command.h>
+#if !defined(CONFIG_440)
+#include <asm/4xx_pci.h>
+#endif
+#include <asm/processor.h>
+#include <pci.h>
+
+#ifdef CONFIG_PCI
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Board-specific pci initialization
+ * Platform code can reimplement pci_pre_init() if needed
+ */
+int __pci_pre_init(struct pci_controller *hose)
+{
+ return 1;
+}
+int pci_pre_init(struct pci_controller *hose) __attribute__((weak, alias("__pci_pre_init")));
+
+#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
+
+#if defined(CONFIG_PMC405)
+ushort pmc405_pci_subsys_deviceid(void);
+#endif
+
+/*#define DEBUG*/
+
+/*-----------------------------------------------------------------------------+
+ * pci_init. Initializes the 405GP PCI Configuration regs.
+ *-----------------------------------------------------------------------------*/
+void pci_405gp_init(struct pci_controller *hose)
+{
+ int i, reg_num = 0;
+ bd_t *bd = gd->bd;
+
+ unsigned short temp_short;
+ unsigned long ptmpcila[2] = {CFG_PCI_PTM1PCI, CFG_PCI_PTM2PCI};
+#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405)
+ char *ptmla_str, *ptmms_str;
+#endif
+ unsigned long ptmla[2] = {CFG_PCI_PTM1LA, CFG_PCI_PTM2LA};
+ unsigned long ptmms[2] = {CFG_PCI_PTM1MS, CFG_PCI_PTM2MS};
+#if defined(CONFIG_PIP405) || defined (CONFIG_MIP405)
+ unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0};
+ unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0};
+ unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0};
+ unsigned long pmmpciha[3] = {0x00000000, 0x00000000, 0};
+#else
+ unsigned long pmmla[3] = {0x80000000, 0,0};
+ unsigned long pmmma[3] = {0xC0000001, 0,0};
+ unsigned long pmmpcila[3] = {0x80000000, 0,0};
+ unsigned long pmmpciha[3] = {0x00000000, 0,0};
+#endif
+#ifdef CONFIG_PCI_PNP
+#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
+ char *s;
+#endif
+#endif
+
+#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405)
+ ptmla_str = getenv("ptm1la");
+ ptmms_str = getenv("ptm1ms");
+ if(NULL != ptmla_str && NULL != ptmms_str ) {
+ ptmla[0] = simple_strtoul (ptmla_str, NULL, 16);
+ ptmms[0] = simple_strtoul (ptmms_str, NULL, 16);
+ }
+
+ ptmla_str = getenv("ptm2la");
+ ptmms_str = getenv("ptm2ms");
+ if(NULL != ptmla_str && NULL != ptmms_str ) {
+ ptmla[1] = simple_strtoul (ptmla_str, NULL, 16);
+ ptmms[1] = simple_strtoul (ptmms_str, NULL, 16);
+ }
+#endif
+
+ /*
+ * Register the hose
+ */
+ hose->first_busno = 0;
+ hose->last_busno = 0xff;
+
+ /* ISA/PCI I/O space */
+ pci_set_region(hose->regions + reg_num++,
+ MIN_PCI_PCI_IOADDR,
+ MIN_PLB_PCI_IOADDR,
+ 0x10000,
+ PCI_REGION_IO);
+
+ /* PCI I/O space */
+ pci_set_region(hose->regions + reg_num++,
+ 0x00800000,
+ 0xe8800000,
+ 0x03800000,
+ PCI_REGION_IO);
+
+ reg_num = 2;
+
+ /* Memory spaces */
+ for (i=0; i<2; i++)
+ if (ptmms[i] & 1)
+ {
+ if (!i) hose->pci_fb = hose->regions + reg_num;
+
+ pci_set_region(hose->regions + reg_num++,
+ ptmpcila[i], ptmla[i],
+ ~(ptmms[i] & 0xfffff000) + 1,
+ PCI_REGION_MEM |
+ PCI_REGION_MEMORY);
+ }
+
+ /* PCI memory spaces */
+ for (i=0; i<3; i++)
+ if (pmmma[i] & 1)
+ {
+ pci_set_region(hose->regions + reg_num++,
+ pmmpcila[i], pmmla[i],
+ ~(pmmma[i] & 0xfffff000) + 1,
+ PCI_REGION_MEM);
+ }
+
+ hose->region_count = reg_num;
+
+ pci_setup_indirect(hose,
+ PCICFGADR,
+ PCICFGDATA);
+
+ if (hose->pci_fb)
+ pciauto_region_init(hose->pci_fb);
+
+ /* Let board change/modify hose & do initial checks */
+ if (pci_pre_init (hose) == 0) {
+ printf("PCI: Board-specific initialization failed.\n");
+ printf("PCI: Configuration aborted.\n");
+ return;
+ }
+
+ pci_register_hose(hose);
+
+ /*--------------------------------------------------------------------------+
+ * 405GP PCI Master configuration.
+ * Map one 512 MB range of PLB/processor addresses to PCI memory space.
+ * PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF
+ * Use byte reversed out routines to handle endianess.
+ *--------------------------------------------------------------------------*/
+ out32r(PMM0MA, (pmmma[0]&~0x1)); /* disable, configure PMMxLA, PMMxPCILA first */
+ out32r(PMM0LA, pmmla[0]);
+ out32r(PMM0PCILA, pmmpcila[0]);
+ out32r(PMM0PCIHA, pmmpciha[0]);
+ out32r(PMM0MA, pmmma[0]);
+
+ /*--------------------------------------------------------------------------+
+ * PMM1 is not used. Initialize them to zero.
+ *--------------------------------------------------------------------------*/
+ out32r(PMM1MA, (pmmma[1]&~0x1));
+ out32r(PMM1LA, pmmla[1]);
+ out32r(PMM1PCILA, pmmpcila[1]);
+ out32r(PMM1PCIHA, pmmpciha[1]);
+ out32r(PMM1MA, pmmma[1]);
+
+ /*--------------------------------------------------------------------------+
+ * PMM2 is not used. Initialize them to zero.
+ *--------------------------------------------------------------------------*/
+ out32r(PMM2MA, (pmmma[2]&~0x1));
+ out32r(PMM2LA, pmmla[2]);
+ out32r(PMM2PCILA, pmmpcila[2]);
+ out32r(PMM2PCIHA, pmmpciha[2]);
+ out32r(PMM2MA, pmmma[2]);
+
+ /*--------------------------------------------------------------------------+
+ * 405GP PCI Target configuration. (PTM1)
+ * Note: PTM1MS is hardwire enabled but we set the enable bit anyway.
+ *--------------------------------------------------------------------------*/
+ out32r(PTM1LA, ptmla[0]); /* insert address */
+ out32r(PTM1MS, ptmms[0]); /* insert size, enable bit is 1 */
+ pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_1, ptmpcila[0]);
+
+ /*--------------------------------------------------------------------------+
+ * 405GP PCI Target configuration. (PTM2)
+ *--------------------------------------------------------------------------*/
+ out32r(PTM2LA, ptmla[1]); /* insert address */
+ pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, ptmpcila[1]);
+
+ if (ptmms[1] == 0)
+ {
+ out32r(PTM2MS, 0x00000001); /* set enable bit */
+ pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, 0x00000000);
+ out32r(PTM2MS, 0x00000000); /* disable */
+ }
+ else
+ {
+ out32r(PTM2MS, ptmms[1]); /* insert size, enable bit is 1 */
+ }
+
+ /*
+ * Insert Subsystem Vendor and Device ID
+ */
+ pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CFG_PCI_SUBSYS_VENDORID);
+#ifdef CONFIG_CPCI405
+ if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
+ pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID);
+ else
+ pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID2);
+#else
+ pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID);
+#endif
+
+ /*
+ * Insert Class-code
+ */
+#ifdef CFG_PCI_CLASSCODE
+ pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CFG_PCI_CLASSCODE);
+#endif /* CFG_PCI_CLASSCODE */
+
+ /*--------------------------------------------------------------------------+
+ * If PCI speed = 66Mhz, set 66Mhz capable bit.
+ *--------------------------------------------------------------------------*/
+ if (bd->bi_pci_busfreq >= 66000000) {
+ pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short);
+ pci_write_config_word(PCIDEVID_405GP,PCI_STATUS,(temp_short|PCI_STATUS_66MHZ));
+ }
+
+#if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER)
+#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
+ if ((mfdcr(strap) & PSR_PCI_ARBIT_EN) ||
+ (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
+#endif
+ {
+ /*--------------------------------------------------------------------------+
+ * Write the 405GP PCI Configuration regs.
+ * Enable 405GP to be a master on the PCI bus (PMM).
+ * Enable 405GP to act as a PCI memory target (PTM).
+ *--------------------------------------------------------------------------*/
+ pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &temp_short);
+ pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND, temp_short |
+ PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+ }
+#endif
+
+#if defined(CONFIG_405EP) /* on ppc405ep vendor id is not set */
+ pci_write_config_word(PCIDEVID_405GP, PCI_VENDOR_ID, 0x1014); /* IBM */
+#endif
+
+ /*
+ * Set HCE bit (Host Configuration Enabled)
+ */
+ pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &temp_short);
+ pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (temp_short | 0x0001));
+
+#ifdef CONFIG_PCI_PNP
+ /*--------------------------------------------------------------------------+
+ * Scan the PCI bus and configure devices found.
+ *--------------------------------------------------------------------------*/
+#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
+ if ((mfdcr(strap) & PSR_PCI_ARBIT_EN) ||
+ (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
+#endif
+ {
+#ifdef CONFIG_PCI_SCAN_SHOW
+ printf("PCI: Bus Dev VenId DevId Class Int\n");
+#endif
+ hose->last_busno = pci_hose_scan(hose);
+ }
+#endif /* CONFIG_PCI_PNP */
+
+}
+
+/*
+ * drivers/pci.c skips every host bridge but the 405GP since it could
+ * be set as an Adapter.
+ *
+ * I (Andrew May) don't know what we should do here, but I don't want
+ * the auto setup of a PCI device disabling what is done pci_405gp_init
+ * as has happened before.
+ */
+void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev,
+ struct pci_config_table *entry)
+{
+#ifdef DEBUG
+ printf("405gp_setup_bridge\n");
+#endif
+}
+
+/*
+ *
+ */
+
+void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+ unsigned char int_line = 0xff;
+
+ /*
+ * Write pci interrupt line register (cpci405 specific)
+ */
+ switch (PCI_DEV(dev) & 0x03)
+ {
+ case 0:
+ int_line = 27 + 2;
+ break;
+ case 1:
+ int_line = 27 + 3;
+ break;
+ case 2:
+ int_line = 27 + 0;
+ break;
+ case 3:
+ int_line = 27 + 1;
+ break;
+ }
+
+ pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
+}
+
+void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
+ struct pci_config_table *entry)
+{
+ unsigned int cmdstat = 0;
+
+ pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
+
+ /* always enable io space on vga boards */
+ pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
+ cmdstat |= PCI_COMMAND_IO;
+ pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
+}
+
+#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) && !(defined (CONFIG_SC3))
+
+/*
+ *As is these functs get called out of flash Not a horrible
+ *thing, but something to keep in mind. (no statics?)
+ */
+static struct pci_config_table pci_405gp_config_table[] = {
+/*if VendID is 0 it terminates the table search (ie Walnut)*/
+#ifdef CFG_PCI_SUBSYS_VENDORID
+ {CFG_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST,
+ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge},
+#endif
+ {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA,
+ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
+
+ {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA,
+ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
+
+ { }
+};
+
+static struct pci_controller hose = {
+ fixup_irq: pci_405gp_fixup_irq,
+ config_table: pci_405gp_config_table,
+};
+
+void pci_init_board(void)
+{
+ /*we want the ptrs to RAM not flash (ie don't use init list)*/
+ hose.fixup_irq = pci_405gp_fixup_irq;
+ hose.config_table = pci_405gp_config_table;
+ pci_405gp_init(&hose);
+}
+
+#endif
+
+#endif /* CONFIG_405GP */
+
+/*-----------------------------------------------------------------------------+
+ * CONFIG_440
+ *-----------------------------------------------------------------------------*/
+#if defined(CONFIG_440)
+
+static struct pci_controller ppc440_hose = {0};
+
+
+int pci_440_init (struct pci_controller *hose)
+{
+ int reg_num = 0;
+
+#ifndef CONFIG_DISABLE_PISE_TEST
+ /*--------------------------------------------------------------------------+
+ * The PCI initialization sequence enable bit must be set ... if not abort
+ * pci setup since updating the bit requires chip reset.
+ *--------------------------------------------------------------------------*/
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+ unsigned long strap;
+
+ mfsdr(sdr_sdstp1,strap);
+ if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) {
+ printf("PCI: SDR0_STRP1[PISE] not set.\n");
+ printf("PCI: Configuration aborted.\n");
+ return -1;
+ }
+#elif defined(CONFIG_440GP)
+ unsigned long strap;
+
+ strap = mfdcr(cpc0_strp1);
+ if ((strap & CPC0_STRP1_PISE_MASK) == 0) {
+ printf("PCI: CPC0_STRP1[PISE] not set.\n");
+ printf("PCI: Configuration aborted.\n");
+ return -1;
+ }
+#endif
+#endif /* CONFIG_DISABLE_PISE_TEST */
+
+ /*--------------------------------------------------------------------------+
+ * PCI controller init
+ *--------------------------------------------------------------------------*/
+ hose->first_busno = 0;
+ hose->last_busno = 0;
+
+ /* PCI I/O space */
+ pci_set_region(hose->regions + reg_num++,
+ 0x00000000,
+ PCIX0_IOBASE,
+ 0x10000,
+ PCI_REGION_IO);
+
+ /* PCI memory space */
+ pci_set_region(hose->regions + reg_num++,
+ CFG_PCI_TARGBASE,
+ CFG_PCI_MEMBASE,
+#ifdef CFG_PCI_MEMSIZE
+ CFG_PCI_MEMSIZE,
+#else
+ 0x10000000,
+#endif
+ PCI_REGION_MEM );
+
+#if defined(CONFIG_PCI_SYS_MEM_BUS) && defined(CONFIG_PCI_SYS_MEM_PHYS) && \
+ defined(CONFIG_PCI_SYS_MEM_SIZE)
+ /* System memory space */
+ pci_set_region(hose->regions + reg_num++,
+ CONFIG_PCI_SYS_MEM_BUS,
+ CONFIG_PCI_SYS_MEM_PHYS,
+ CONFIG_PCI_SYS_MEM_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY );
+#endif
+
+ hose->region_count = reg_num;
+
+ pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA);
+
+ /* Let board change/modify hose & do initial checks */
+ if (pci_pre_init (hose) == 0) {
+ printf("PCI: Board-specific initialization failed.\n");
+ printf("PCI: Configuration aborted.\n");
+ return -1;
+ }
+
+ pci_register_hose( hose );
+
+ /*--------------------------------------------------------------------------+
+ * PCI target init
+ *--------------------------------------------------------------------------*/
+#if defined(CFG_PCI_TARGET_INIT)
+ pci_target_init(hose); /* Let board setup pci target */
+#else
+ out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
+ out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_ID );
+ out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
+#endif
+
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+ out32r( PCIX0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */
+ out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */
+#elif defined(PCIX0_BRDGOPT1)
+ out32r( PCIX0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */
+ out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config */
+#endif
+
+ /*--------------------------------------------------------------------------+
+ * PCI master init: default is one 256MB region for PCI memory:
+ * 0x3_00000000 - 0x3_0FFFFFFF ==> CFG_PCI_MEMBASE
+ *--------------------------------------------------------------------------*/
+#if defined(CFG_PCI_MASTER_INIT)
+ pci_master_init(hose); /* Let board setup pci master */
+#else
+ out32r( PCIX0_POM0SA, 0 ); /* disable */
+ out32r( PCIX0_POM1SA, 0 ); /* disable */
+ out32r( PCIX0_POM2SA, 0 ); /* disable */
+#if defined(CONFIG_440SPE)
+ out32r( PCIX0_POM0LAL, 0x10000000 );
+ out32r( PCIX0_POM0LAH, 0x0000000c );
+#else
+ out32r( PCIX0_POM0LAL, 0x00000000 );
+ out32r( PCIX0_POM0LAH, 0x00000003 );
+#endif
+ out32r( PCIX0_POM0PCIAL, CFG_PCI_MEMBASE );
+ out32r( PCIX0_POM0PCIAH, 0x00000000 );
+ out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */
+ out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 );
+#endif
+
+ /*--------------------------------------------------------------------------+
+ * PCI host configuration -- we don't make any assumptions here ... the
+ * _board_must_indicate_ what to do -- there's just too many runtime
+ * scenarios in environments like cPCI, PPMC, etc. to make a determination
+ * based on hard-coded values or state of arbiter enable.
+ *--------------------------------------------------------------------------*/
+ if (is_pci_host(hose)) {
+#ifdef CONFIG_PCI_SCAN_SHOW
+ printf("PCI: Bus Dev VenId DevId Class Int\n");
+#endif
+#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
+ !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
+ out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
+#endif
+ hose->last_busno = pci_hose_scan(hose);
+ }
+ return hose->last_busno;
+}
+
+void pci_init_board(void)
+{
+ int busno;
+
+ busno = pci_440_init (&ppc440_hose);
+#if defined(CONFIG_440SPE)
+ pcie_setup_hoses(busno + 1);
+#endif
+}
+
+#endif /* CONFIG_440 */
+
+#if defined(CONFIG_405EX)
+void pci_init_board(void)
+{
+#ifdef CONFIG_PCI_SCAN_SHOW
+ printf("PCI: Bus Dev VenId DevId Class Int\n");
+#endif
+ pcie_setup_hoses(0);
+}
+#endif /* CONFIG_405EX */
+
+#endif /* CONFIG_PCI */
--- /dev/null
+/*
+ * (C) Copyright 2006 - 2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (c) 2005 Cisco Systems. All rights reserved.
+ * Roland Dreier <rolandd@cisco.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+/* define DEBUG for debugging output (obviously ;-)) */
+#if 0
+#define DEBUG
+#endif
+
+#include <asm/processor.h>
+#include <asm-ppc/io.h>
+#include <ppc4xx.h>
+#include <common.h>
+#include <pci.h>
+
+#if (defined(CONFIG_440SPE) || defined(CONFIG_405EX)) && \
+ defined(CONFIG_PCI)
+
+#include <asm/4xx_pcie.h>
+
+enum {
+ PTYPE_ENDPOINT = 0x0,
+ PTYPE_LEGACY_ENDPOINT = 0x1,
+ PTYPE_ROOT_PORT = 0x4,
+
+ LNKW_X1 = 0x1,
+ LNKW_X4 = 0x4,
+ LNKW_X8 = 0x8
+};
+
+static int validate_endpoint(struct pci_controller *hose)
+{
+ if (hose->cfg_data == (u8 *)CFG_PCIE0_CFGBASE)
+ return (is_end_point(0));
+ else if (hose->cfg_data == (u8 *)CFG_PCIE1_CFGBASE)
+ return (is_end_point(1));
+#if CFG_PCIE_NR_PORTS > 2
+ else if (hose->cfg_data == (u8 *)CFG_PCIE2_CFGBASE)
+ return (is_end_point(2));
+#endif
+
+ return 0;
+}
+
+static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn)
+{
+ u8 *base = (u8*)hose->cfg_data;
+
+ /* use local configuration space for the first bus */
+ if (PCI_BUS(devfn) == 0) {
+ if (hose->cfg_data == (u8*)CFG_PCIE0_CFGBASE)
+ base = (u8*)CFG_PCIE0_XCFGBASE;
+ if (hose->cfg_data == (u8*)CFG_PCIE1_CFGBASE)
+ base = (u8*)CFG_PCIE1_XCFGBASE;
+#if CFG_PCIE_NR_PORTS > 2
+ if (hose->cfg_data == (u8*)CFG_PCIE2_CFGBASE)
+ base = (u8*)CFG_PCIE2_XCFGBASE;
+#endif
+ }
+
+ return base;
+}
+
+static void pcie_dmer_disable(void)
+{
+ mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE),
+ mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) | GPL_DMER_MASK_DISA);
+ mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE),
+ mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) | GPL_DMER_MASK_DISA);
+#if CFG_PCIE_NR_PORTS > 2
+ mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE),
+ mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) | GPL_DMER_MASK_DISA);
+#endif
+}
+
+static void pcie_dmer_enable(void)
+{
+ mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE0_BASE),
+ mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) & ~GPL_DMER_MASK_DISA);
+ mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE1_BASE),
+ mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) & ~GPL_DMER_MASK_DISA);
+#if CFG_PCIE_NR_PORTS > 2
+ mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE2_BASE),
+ mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA);
+#endif
+}
+
+static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
+ int offset, int len, u32 *val) {
+
+ u8 *address;
+ *val = 0;
+
+ if (validate_endpoint(hose))
+ return 0; /* No upstream config access */
+
+ /*
+ * Bus numbers are relative to hose->first_busno
+ */
+ devfn -= PCI_BDF(hose->first_busno, 0, 0);
+
+ /*
+ * NOTICE: configuration space ranges are currenlty mapped only for
+ * the first 16 buses, so such limit must be imposed. In case more
+ * buses are required the TLB settings in board/amcc/<board>/init.S
+ * need to be altered accordingly (one bus takes 1 MB of memory space).
+ */
+ if (PCI_BUS(devfn) >= 16)
+ return 0;
+
+ /*
+ * Only single device/single function is supported for the primary and
+ * secondary buses of the 440SPe host bridge.
+ */
+ if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
+ ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
+ return 0;
+
+ address = pcie_get_base(hose, devfn);
+ offset += devfn << 4;
+
+ /*
+ * Reading from configuration space of non-existing device can
+ * generate transaction errors. For the read duration we suppress
+ * assertion of machine check exceptions to avoid those.
+ */
+ pcie_dmer_disable ();
+
+ debug("%s: cfg_data=%08x offset=%08x\n", __func__, hose->cfg_data, offset);
+ switch (len) {
+ case 1:
+ *val = in_8(hose->cfg_data + offset);
+ break;
+ case 2:
+ *val = in_le16((u16 *)(hose->cfg_data + offset));
+ break;
+ default:
+ *val = in_le32((u32*)(hose->cfg_data + offset));
+ break;
+ }
+
+ pcie_dmer_enable ();
+
+ return 0;
+}
+
+static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
+ int offset, int len, u32 val) {
+
+ u8 *address;
+
+ if (validate_endpoint(hose))
+ return 0; /* No upstream config access */
+
+ /*
+ * Bus numbers are relative to hose->first_busno
+ */
+ devfn -= PCI_BDF(hose->first_busno, 0, 0);
+
+ /*
+ * Same constraints as in pcie_read_config().
+ */
+ if (PCI_BUS(devfn) >= 16)
+ return 0;
+
+ if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
+ ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
+ return 0;
+
+ address = pcie_get_base(hose, devfn);
+ offset += devfn << 4;
+
+ /*
+ * Suppress MCK exceptions, similar to pcie_read_config()
+ */
+ pcie_dmer_disable ();
+
+ switch (len) {
+ case 1:
+ out_8(hose->cfg_data + offset, val);
+ break;
+ case 2:
+ out_le16((u16 *)(hose->cfg_data + offset), val);
+ break;
+ default:
+ out_le32((u32 *)(hose->cfg_data + offset), val);
+ break;
+ }
+
+ pcie_dmer_enable ();
+
+ return 0;
+}
+
+int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 *val)
+{
+ u32 v;
+ int rv;
+
+ rv = pcie_read_config(hose, dev, offset, 1, &v);
+ *val = (u8)v;
+ return rv;
+}
+
+int pcie_read_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 *val)
+{
+ u32 v;
+ int rv;
+
+ rv = pcie_read_config(hose, dev, offset, 2, &v);
+ *val = (u16)v;
+ return rv;
+}
+
+int pcie_read_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 *val)
+{
+ u32 v;
+ int rv;
+
+ rv = pcie_read_config(hose, dev, offset, 3, &v);
+ *val = (u32)v;
+ return rv;
+}
+
+int pcie_write_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 val)
+{
+ return pcie_write_config(hose,(u32)dev,offset,1,val);
+}
+
+int pcie_write_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 val)
+{
+ return pcie_write_config(hose,(u32)dev,offset,2,(u32 )val);
+}
+
+int pcie_write_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 val)
+{
+ return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val);
+}
+
+#if defined(CONFIG_440SPE)
+static void ppc4xx_setup_utl(u32 port) {
+
+ volatile void *utl_base = NULL;
+
+ /*
+ * Map UTL registers
+ */
+ switch (port) {
+ case 0:
+ mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c);
+ mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x20000000);
+ mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001);
+ mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800);
+ break;
+
+ case 1:
+ mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c);
+ mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x20001000);
+ mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001);
+ mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800);
+ break;
+
+ case 2:
+ mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c);
+ mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x20002000);
+ mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001);
+ mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800);
+ break;
+ }
+ utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port);
+
+ /*
+ * Set buffer allocations and then assert VRB and TXE.
+ */
+ out_be32(utl_base + PEUTL_OUTTR, 0x08000000);
+ out_be32(utl_base + PEUTL_INTR, 0x02000000);
+ out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000);
+ out_be32(utl_base + PEUTL_PBBSZ, 0x53000000);
+ out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000);
+ out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000);
+ out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
+ out_be32(utl_base + PEUTL_PCTL, 0x80800066);
+}
+
+static int check_error(void)
+{
+ u32 valPE0, valPE1, valPE2;
+ int err = 0;
+
+ /* SDR0_PEGPLLLCT1 reset */
+ if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000)) {
+ printf("PCIE: SDR0_PEGPLLLCT1 reset error 0x%x\n", valPE0);
+ }
+
+ valPE0 = SDR_READ(PESDR0_RCSSET);
+ valPE1 = SDR_READ(PESDR1_RCSSET);
+ valPE2 = SDR_READ(PESDR2_RCSSET);
+
+ /* SDR0_PExRCSSET rstgu */
+ if (!(valPE0 & 0x01000000) ||
+ !(valPE1 & 0x01000000) ||
+ !(valPE2 & 0x01000000)) {
+ printf("PCIE: SDR0_PExRCSSET rstgu error\n");
+ err = -1;
+ }
+
+ /* SDR0_PExRCSSET rstdl */
+ if (!(valPE0 & 0x00010000) ||
+ !(valPE1 & 0x00010000) ||
+ !(valPE2 & 0x00010000)) {
+ printf("PCIE: SDR0_PExRCSSET rstdl error\n");
+ err = -1;
+ }
+
+ /* SDR0_PExRCSSET rstpyn */
+ if ((valPE0 & 0x00001000) ||
+ (valPE1 & 0x00001000) ||
+ (valPE2 & 0x00001000)) {
+ printf("PCIE: SDR0_PExRCSSET rstpyn error\n");
+ err = -1;
+ }
+
+ /* SDR0_PExRCSSET hldplb */
+ if ((valPE0 & 0x10000000) ||
+ (valPE1 & 0x10000000) ||
+ (valPE2 & 0x10000000)) {
+ printf("PCIE: SDR0_PExRCSSET hldplb error\n");
+ err = -1;
+ }
+
+ /* SDR0_PExRCSSET rdy */
+ if ((valPE0 & 0x00100000) ||
+ (valPE1 & 0x00100000) ||
+ (valPE2 & 0x00100000)) {
+ printf("PCIE: SDR0_PExRCSSET rdy error\n");
+ err = -1;
+ }
+
+ /* SDR0_PExRCSSET shutdown */
+ if ((valPE0 & 0x00000100) ||
+ (valPE1 & 0x00000100) ||
+ (valPE2 & 0x00000100)) {
+ printf("PCIE: SDR0_PExRCSSET shutdown error\n");
+ err = -1;
+ }
+ return err;
+}
+
+/*
+ * Initialize PCI Express core
+ */
+int ppc4xx_init_pcie(void)
+{
+ int time_out = 20;
+
+ /* Set PLL clock receiver to LVPECL */
+ SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28);
+
+ if (check_error())
+ return -1;
+
+ if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000))
+ {
+ printf("PCIE: PESDR_PLLCT2 resistance calibration failed (0x%08x)\n",
+ SDR_READ(PESDR0_PLLLCT2));
+ return -1;
+ }
+ /* De-assert reset of PCIe PLL, wait for lock */
+ SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24));
+ udelay(3);
+
+ while (time_out) {
+ if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) {
+ time_out--;
+ udelay(1);
+ } else
+ break;
+ }
+ if (!time_out) {
+ printf("PCIE: VCO output not locked\n");
+ return -1;
+ }
+ return 0;
+}
+#else
+static void ppc4xx_setup_utl(u32 port)
+{
+ u32 utl_base;
+
+ /*
+ * Map UTL registers at 0xef4f_n000 (4K 0xfff mask) PEGPLn_REGMSK
+ */
+ switch (port) {
+ case 0:
+ mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x00000000);
+ mtdcr(DCRN_PEGPL_REGBAL(PCIE0), CFG_PCIE0_UTLBASE);
+ mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* 4k region, valid */
+ mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0);
+ break;
+
+ case 1:
+ mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x00000000);
+ mtdcr(DCRN_PEGPL_REGBAL(PCIE1), CFG_PCIE1_UTLBASE);
+ mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* 4k region, valid */
+ mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0);
+
+ break;
+ }
+ utl_base = (port==0) ? CFG_PCIE0_UTLBASE : CFG_PCIE1_UTLBASE;
+
+ /*
+ * Set buffer allocations and then assert VRB and TXE.
+ */
+ out_be32((u32 *)(utl_base + PEUTL_OUTTR), 0x02000000);
+ out_be32((u32 *)(utl_base + PEUTL_INTR), 0x02000000);
+ out_be32((u32 *)(utl_base + PEUTL_OPDBSZ), 0x04000000);
+ out_be32((u32 *)(utl_base + PEUTL_PBBSZ), 0x21000000);
+ out_be32((u32 *)(utl_base + PEUTL_IPHBSZ), 0x02000000);
+ out_be32((u32 *)(utl_base + PEUTL_IPDBSZ), 0x04000000);
+ out_be32((u32 *)(utl_base + PEUTL_RCIRQEN), 0x00f00000);
+ out_be32((u32 *)(utl_base + PEUTL_PCTL), 0x80800066);
+
+ out_be32((u32 *)(utl_base + PEUTL_PBCTL), 0x0800000c);
+ out_be32((u32 *)(utl_base + PEUTL_RCSTA),
+ in_be32((u32 *)(utl_base + PEUTL_RCSTA)) | 0x000040000);
+}
+
+int ppc4xx_init_pcie(void)
+{
+ /*
+ * Nothing to do on 405EX
+ */
+ return 0;
+}
+#endif
+
+/*
+ * Board-specific pcie initialization
+ * Platform code can reimplement ppc4xx_init_pcie_port_hw() if needed
+ */
+
+/*
+ * Initialize various parts of the PCI Express core for our port:
+ *
+ * - Set as a root port and enable max width
+ * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4).
+ * - Set up UTL configuration.
+ * - Increase SERDES drive strength to levels suggested by AMCC.
+ * - De-assert RSTPYN, RSTDL and RSTGU.
+ *
+ * NOTICE for 440SPE revB chip: PESDRn_UTLSET2 is not set - we leave it
+ * with default setting 0x11310000. The register has new fields,
+ * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core
+ * hang.
+ */
+#if defined(CONFIG_440SPE)
+int __ppc4xx_init_pcie_port_hw(int port, int rootport)
+{
+ u32 val = 1 << 24;
+ u32 utlset1;
+
+ if (rootport) {
+ val = PTYPE_ROOT_PORT << 20;
+ utlset1 = 0x21222222;
+ } else {
+ val = PTYPE_LEGACY_ENDPOINT << 20;
+ utlset1 = 0x20222222;
+ }
+
+ if (port == 0)
+ val |= LNKW_X8 << 12;
+ else
+ val |= LNKW_X4 << 12;
+
+ SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
+ SDR_WRITE(SDRN_PESDR_UTLSET1(port), utlset1);
+ if (!ppc440spe_revB())
+ SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x11000000);
+ SDR_WRITE(SDRN_PESDR_HSSL0SET1(port), 0x35000000);
+ SDR_WRITE(SDRN_PESDR_HSSL1SET1(port), 0x35000000);
+ SDR_WRITE(SDRN_PESDR_HSSL2SET1(port), 0x35000000);
+ SDR_WRITE(SDRN_PESDR_HSSL3SET1(port), 0x35000000);
+ if (port == 0) {
+ SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000);
+ SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000);
+ SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000);
+ SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000);
+ }
+ SDR_WRITE(SDRN_PESDR_RCSSET(port), (SDR_READ(SDRN_PESDR_RCSSET(port)) &
+ ~(1 << 24 | 1 << 16)) | 1 << 12);
+
+ return 0;
+}
+#endif /* CONFIG_440SPE */
+
+#if defined(CONFIG_405EX)
+int __ppc4xx_init_pcie_port_hw(int port, int rootport)
+{
+ u32 val;
+
+ if (rootport)
+ val = 0x00401000;
+ else
+ val = 0x00101000;
+
+ SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
+ SDR_WRITE(SDRN_PESDR_UTLSET1(port), 0x00000000);
+ SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01010000);
+ SDR_WRITE(SDRN_PESDR_PHYSET1(port), 0x720F0000);
+ SDR_WRITE(SDRN_PESDR_PHYSET2(port), 0x70600003);
+
+ /* Assert the PE0_PHY reset */
+ SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01010000);
+ udelay(1000);
+
+ /* deassert the PE0_hotreset */
+ if (is_end_point(port))
+ SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01111000);
+ else
+ SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01101000);
+
+ /* poll for phy !reset */
+ while (!(SDR_READ(SDRN_PESDR_PHYSTA(port)) & 0x00001000))
+ ;
+
+ /* deassert the PE0_gpl_utl_reset */
+ SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x00101000);
+
+ if (port == 0)
+ mtdcr(DCRN_PEGPL_CFG(PCIE0), 0x10000000); /* guarded on */
+ else
+ mtdcr(DCRN_PEGPL_CFG(PCIE1), 0x10000000); /* guarded on */
+
+ return 0;
+}
+#endif /* CONFIG_405EX */
+
+int ppc4xx_init_pcie_port_hw(int port, int rootport)
+__attribute__((weak, alias("__ppc4xx_init_pcie_port_hw")));
+
+/*
+ * We map PCI Express configuration access into the 512MB regions
+ *
+ * NOTICE: revB is very strict about PLB real addressess and ranges to
+ * be mapped for config space; it seems to only work with d_nnnn_nnnn
+ * range (hangs the core upon config transaction attempts when set
+ * otherwise) while revA uses c_nnnn_nnnn.
+ *
+ * For revA:
+ * PCIE0: 0xc_4000_0000
+ * PCIE1: 0xc_8000_0000
+ * PCIE2: 0xc_c000_0000
+ *
+ * For revB:
+ * PCIE0: 0xd_0000_0000
+ * PCIE1: 0xd_2000_0000
+ * PCIE2: 0xd_4000_0000
+ *
+ * For 405EX:
+ * PCIE0: 0xa000_0000
+ * PCIE1: 0xc000_0000
+ */
+static inline u64 ppc4xx_get_cfgaddr(int port)
+{
+#if defined(CONFIG_405EX)
+ if (port == 0)
+ return (u64)CFG_PCIE0_CFGBASE;
+ else
+ return (u64)CFG_PCIE1_CFGBASE;
+#endif
+#if defined(CONFIG_440SPE)
+ if (ppc440spe_revB()) {
+ switch (port) {
+ default: /* to satisfy compiler */
+ case 0:
+ return 0x0000000d00000000ULL;
+ case 1:
+ return 0x0000000d20000000ULL;
+ case 2:
+ return 0x0000000d40000000ULL;
+ }
+ } else {
+ switch (port) {
+ default: /* to satisfy compiler */
+ case 0:
+ return 0x0000000c40000000ULL;
+ case 1:
+ return 0x0000000c80000000ULL;
+ case 2:
+ return 0x0000000cc0000000ULL;
+ }
+ }
+#endif
+}
+
+/*
+ * 4xx boards as end point and root point setup
+ * and
+ * testing inbound and out bound windows
+ *
+ * 4xx boards can be plugged into another 4xx boards or you can get PCI-E
+ * cable which can be used to setup loop back from one port to another port.
+ * Please rememeber that unless there is a endpoint plugged in to root port it
+ * will not initialize. It is the same in case of endpoint , unless there is
+ * root port attached it will not initialize.
+ *
+ * In this release of software all the PCI-E ports are configured as either
+ * endpoint or rootpoint.In future we will have support for selective ports
+ * setup as endpoint and root point in single board.
+ *
+ * Once your board came up as root point , you can verify by reading
+ * /proc/bus/pci/devices. Where you can see the configuration registers
+ * of end point device attached to the port.
+ *
+ * Enpoint cofiguration can be verified by connecting 4xx board to any
+ * host or another 4xx board. Then try to scan the device. In case of
+ * linux use "lspci" or appripriate os command.
+ *
+ * How do I verify the inbound and out bound windows ? (4xx to 4xx)
+ * in this configuration inbound and outbound windows are setup to access
+ * sram memroy area. SRAM is at 0x4 0000 0000 , on PLB bus. This address
+ * is mapped at 0x90000000. From u-boot prompt write data 0xb000 0000,
+ * This is waere your POM(PLB out bound memory window) mapped. then
+ * read the data from other 4xx board's u-boot prompt at address
+ * 0x9000 0000(SRAM). Data should match.
+ * In case of inbound , write data to u-boot command prompt at 0xb000 0000
+ * which is mapped to 0x4 0000 0000. Now on rootpoint yucca u-boot prompt check
+ * data at 0x9000 0000(SRAM).Data should match.
+ */
+int ppc4xx_init_pcie_port(int port, int rootport)
+{
+ static int core_init;
+ volatile u32 val = 0;
+ int attempts;
+ u64 addr;
+ u32 low, high;
+
+ if (!core_init) {
+ if (ppc4xx_init_pcie())
+ return -1;
+ ++core_init;
+ }
+
+ /*
+ * Initialize various parts of the PCI Express core for our port
+ */
+ ppc4xx_init_pcie_port_hw(port, rootport);
+
+ /*
+ * Notice: the following delay has critical impact on device
+ * initialization - if too short (<50ms) the link doesn't get up.
+ */
+ mdelay(100);
+
+ val = SDR_READ(SDRN_PESDR_RCSSTS(port));
+ if (val & (1 << 20)) {
+ printf("PCIE%d: PGRST failed %08x\n", port, val);
+ return -1;
+ }
+
+ /*
+ * Verify link is up
+ */
+ val = SDR_READ(SDRN_PESDR_LOOP(port));
+ if (!(val & 0x00001000)) {
+ printf("PCIE%d: link is not up.\n", port);
+ return -1;
+ }
+
+ /*
+ * Setup UTL registers - but only on revA!
+ * We use default settings for revB chip.
+ */
+ if (!ppc440spe_revB())
+ ppc4xx_setup_utl(port);
+
+ /*
+ * We map PCI Express configuration access into the 512MB regions
+ */
+ addr = ppc4xx_get_cfgaddr(port);
+ low = U64_TO_U32_LOW(addr);
+ high = U64_TO_U32_HIGH(addr);
+
+ switch (port) {
+ case 0:
+ mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), high);
+ mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), low);
+ mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */
+ break;
+ case 1:
+ mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), high);
+ mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), low);
+ mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
+ break;
+#if CFG_PCIE_NR_PORTS > 2
+ case 2:
+ mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), high);
+ mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), low);
+ mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */
+ break;
+#endif
+ }
+
+ /*
+ * Check for VC0 active and assert RDY.
+ */
+ attempts = 10;
+ while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 16))) {
+ if (!(attempts--)) {
+ printf("PCIE%d: VC0 not active\n", port);
+ return -1;
+ }
+ mdelay(1000);
+ }
+ SDR_WRITE(SDRN_PESDR_RCSSET(port),
+ SDR_READ(SDRN_PESDR_RCSSET(port)) | 1 << 20);
+ mdelay(100);
+
+ return 0;
+}
+
+int ppc4xx_init_pcie_rootport(int port)
+{
+ return ppc4xx_init_pcie_port(port, 1);
+}
+
+int ppc4xx_init_pcie_endport(int port)
+{
+ return ppc4xx_init_pcie_port(port, 0);
+}
+
+void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
+{
+ volatile void *mbase = NULL;
+ volatile void *rmbase = NULL;
+
+ pci_set_ops(hose,
+ pcie_read_config_byte,
+ pcie_read_config_word,
+ pcie_read_config_dword,
+ pcie_write_config_byte,
+ pcie_write_config_word,
+ pcie_write_config_dword);
+
+ switch (port) {
+ case 0:
+ mbase = (u32 *)CFG_PCIE0_XCFGBASE;
+ rmbase = (u32 *)CFG_PCIE0_CFGBASE;
+ hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE;
+ break;
+ case 1:
+ mbase = (u32 *)CFG_PCIE1_XCFGBASE;
+ rmbase = (u32 *)CFG_PCIE1_CFGBASE;
+ hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE;
+ break;
+#if CFG_PCIE_NR_PORTS > 2
+ case 2:
+ mbase = (u32 *)CFG_PCIE2_XCFGBASE;
+ rmbase = (u32 *)CFG_PCIE2_CFGBASE;
+ hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE;
+ break;
+#endif
+ }
+
+ /*
+ * Set bus numbers on our root port
+ */
+ out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
+ out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
+ out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
+
+ /*
+ * Set up outbound translation to hose->mem_space from PLB
+ * addresses at an offset of 0xd_0000_0000. We set the low
+ * bits of the mask to 11 to turn off splitting into 8
+ * subregions and to enable the outbound translation.
+ */
+ out_le32(mbase + PECFG_POM0LAH, 0x00000000);
+ out_le32(mbase + PECFG_POM0LAL, CFG_PCIE_MEMBASE +
+ port * CFG_PCIE_MEMSIZE);
+ debug("PECFG_POM0LA=%08x.%08x\n", in_le32(mbase + PECFG_POM0LAH),
+ in_le32(mbase + PECFG_POM0LAL));
+
+ switch (port) {
+ case 0:
+ mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CFG_PCIE_ADDR_HIGH);
+ mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
+ port * CFG_PCIE_MEMSIZE);
+ mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
+ mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
+ ~(CFG_PCIE_MEMSIZE - 1) | 3);
+ debug("0:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
+ mfdcr(DCRN_PEGPL_OMR1BAH(PCIE0)),
+ mfdcr(DCRN_PEGPL_OMR1BAL(PCIE0)),
+ mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE0)),
+ mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE0)));
+ break;
+ case 1:
+ mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CFG_PCIE_ADDR_HIGH);
+ mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CFG_PCIE_MEMBASE +
+ port * CFG_PCIE_MEMSIZE);
+ mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
+ mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
+ ~(CFG_PCIE_MEMSIZE - 1) | 3);
+ debug("1:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
+ mfdcr(DCRN_PEGPL_OMR1BAH(PCIE1)),
+ mfdcr(DCRN_PEGPL_OMR1BAL(PCIE1)),
+ mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE1)),
+ mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE1)));
+ break;
+#if CFG_PCIE_NR_PORTS > 2
+ case 2:
+ mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CFG_PCIE_ADDR_HIGH);
+ mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CFG_PCIE_MEMBASE +
+ port * CFG_PCIE_MEMSIZE);
+ mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
+ mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
+ ~(CFG_PCIE_MEMSIZE - 1) | 3);
+ debug("2:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
+ mfdcr(DCRN_PEGPL_OMR1BAH(PCIE2)),
+ mfdcr(DCRN_PEGPL_OMR1BAL(PCIE2)),
+ mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE2)),
+ mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE2)));
+ break;
+#endif
+ }
+
+ /* Set up 16GB inbound memory window at 0 */
+ out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
+ out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
+ out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc);
+ out_le32(mbase + PECFG_BAR0LMPA, 0);
+
+ out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
+ out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
+ out_le32(mbase + PECFG_PIM0LAL, 0);
+ out_le32(mbase + PECFG_PIM0LAH, 0);
+ out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
+ out_le32(mbase + PECFG_PIM1LAH, 0x00000004);
+ out_le32(mbase + PECFG_PIMEN, 0x1);
+
+ /* Enable I/O, Mem, and Busmaster cycles */
+ out_le16((u16 *)(mbase + PCI_COMMAND),
+ in_le16((u16 *)(mbase + PCI_COMMAND)) |
+ PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+
+ /* Set Device and Vendor Id */
+ out_le16(mbase + 0x200, 0xaaa0 + port);
+ out_le16(mbase + 0x202, 0xbed0 + port);
+
+ /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
+ out_le32(mbase + 0x208, 0x06040001);
+
+ printf("PCIE%d: successfully set as root-complex\n", port);
+}
+
+int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port)
+{
+ volatile void *mbase = NULL;
+ int attempts = 0;
+
+ pci_set_ops(hose,
+ pcie_read_config_byte,
+ pcie_read_config_word,
+ pcie_read_config_dword,
+ pcie_write_config_byte,
+ pcie_write_config_word,
+ pcie_write_config_dword);
+
+ switch (port) {
+ case 0:
+ mbase = (u32 *)CFG_PCIE0_XCFGBASE;
+ hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE;
+ break;
+ case 1:
+ mbase = (u32 *)CFG_PCIE1_XCFGBASE;
+ hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE;
+ break;
+#if defined(CFG_PCIE2_CFGBASE)
+ case 2:
+ mbase = (u32 *)CFG_PCIE2_XCFGBASE;
+ hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE;
+ break;
+#endif
+ }
+
+ /*
+ * Set up outbound translation to hose->mem_space from PLB
+ * addresses at an offset of 0xd_0000_0000. We set the low
+ * bits of the mask to 11 to turn off splitting into 8
+ * subregions and to enable the outbound translation.
+ */
+ out_le32(mbase + PECFG_POM0LAH, 0x00001ff8);
+ out_le32(mbase + PECFG_POM0LAL, 0x00001000);
+
+ switch (port) {
+ case 0:
+ mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CFG_PCIE_ADDR_HIGH);
+ mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
+ port * CFG_PCIE_MEMSIZE);
+ mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
+ mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
+ ~(CFG_PCIE_MEMSIZE - 1) | 3);
+ break;
+ case 1:
+ mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CFG_PCIE_ADDR_HIGH);
+ mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CFG_PCIE_MEMBASE +
+ port * CFG_PCIE_MEMSIZE);
+ mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
+ mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
+ ~(CFG_PCIE_MEMSIZE - 1) | 3);
+ break;
+#if CFG_PCIE_NR_PORTS > 2
+ case 2:
+ mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CFG_PCIE_ADDR_HIGH);
+ mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CFG_PCIE_MEMBASE +
+ port * CFG_PCIE_MEMSIZE);
+ mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
+ mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
+ ~(CFG_PCIE_MEMSIZE - 1) | 3);
+ break;
+#endif
+ }
+
+ /* Set up 64MB inbound memory window at 0 */
+ out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
+ out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
+
+ out_le32(mbase + PECFG_PIM01SAH, 0xffffffff);
+ out_le32(mbase + PECFG_PIM01SAL, 0xfc000000);
+
+ /* Setup BAR0 */
+ out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffff);
+ out_le32(mbase + PECFG_BAR0LMPA, 0xfc000000 | PCI_BASE_ADDRESS_MEM_TYPE_64);
+
+ /* Disable BAR1 & BAR2 */
+ out_le32(mbase + PECFG_BAR1MPA, 0);
+ out_le32(mbase + PECFG_BAR2HMPA, 0);
+ out_le32(mbase + PECFG_BAR2LMPA, 0);
+
+ out_le32(mbase + PECFG_PIM0LAL, U64_TO_U32_LOW(CFG_PCIE_INBOUND_BASE));
+ out_le32(mbase + PECFG_PIM0LAH, U64_TO_U32_HIGH(CFG_PCIE_INBOUND_BASE));
+ out_le32(mbase + PECFG_PIMEN, 0x1);
+
+ /* Enable I/O, Mem, and Busmaster cycles */
+ out_le16((u16 *)(mbase + PCI_COMMAND),
+ in_le16((u16 *)(mbase + PCI_COMMAND)) |
+ PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+ out_le16(mbase + 0x200, 0xcaad); /* Setting vendor ID */
+ out_le16(mbase + 0x202, 0xfeed); /* Setting device ID */
+
+ /* Set Class Code to Processor/PPC */
+ out_le32(mbase + 0x208, 0x0b200001);
+
+ attempts = 10;
+ while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 8))) {
+ if (!(attempts--)) {
+ printf("PCIE%d: BME not active\n", port);
+ return -1;
+ }
+ mdelay(1000);
+ }
+
+ printf("PCIE%d: successfully set as endpoint\n", port);
+
+ return 0;
+}
+#endif /* CONFIG_440SPE && CONFIG_PCI */
--- /dev/null
+/*
+ * (C) Copyright 2000-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This source code has been made available to you by IBM on an AS-IS
+ * basis. Anyone receiving this source is licensed under IBM
+ * copyrights to use it in any way he or she deems fit, including
+ * copying it, modifying it, compiling it, and redistributing it either
+ * with or without modifications. No license under IBM patents or
+ * patent applications is to be implied by the copyright license.
+ *
+ * Any user of this software should understand that IBM cannot provide
+ * technical support for this software and will not be responsible for
+ * any consequences resulting from the use of this software.
+ *
+ * Any person who transfers this source code or any derivative work
+ * must include the IBM copyright notice, this paragraph, and the
+ * preceding two paragraphs in the transferred software.
+ *
+ * COPYRIGHT I B M CORPORATION 1995
+ * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
+ */
+
+#include <common.h>
+#include <commproc.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <watchdog.h>
+#include "vecnum.h"
+
+#ifdef CONFIG_SERIAL_MULTI
+#include <serial.h>
+#endif
+
+#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
+#include <malloc.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
+ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
+ defined(CONFIG_405EX) || defined(CONFIG_440)
+
+#if defined(CONFIG_440)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300
+#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400
+#else
+#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200
+#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300
+#endif
+
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000600
+#endif
+
+#if defined(CONFIG_440GP)
+#define CR0_MASK 0x3fff0000
+#define CR0_EXTCLK_ENA 0x00600000
+#define CR0_UDIV_POS 16
+#define UDIV_SUBTRACT 1
+#define UART0_SDR cntrl0
+#define MFREG(a, d) d = mfdcr(a)
+#define MTREG(a, d) mtdcr(a, d)
+#else /* #if defined(CONFIG_440GP) */
+/* all other 440 PPC's access clock divider via sdr register */
+#define CR0_MASK 0xdfffffff
+#define CR0_EXTCLK_ENA 0x00800000
+#define CR0_UDIV_POS 0
+#define UDIV_SUBTRACT 0
+#define UART0_SDR sdr_uart0
+#define UART1_SDR sdr_uart1
+#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \
+ defined(CONFIG_440GR) || defined(CONFIG_440GRx) || \
+ defined(CONFIG_440SP) || defined(CONFIG_440SPe)
+#define UART2_SDR sdr_uart2
+#endif
+#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \
+ defined(CONFIG_440GR) || defined(CONFIG_440GRx)
+#define UART3_SDR sdr_uart3
+#endif
+#define MFREG(a, d) mfsdr(a, d)
+#define MTREG(a, d) mtsdr(a, d)
+#endif /* #if defined(CONFIG_440GP) */
+#elif defined(CONFIG_405EP) || defined(CONFIG_405EZ)
+#define UART0_BASE 0xef600300
+#define UART1_BASE 0xef600400
+#define UCR0_MASK 0x0000007f
+#define UCR1_MASK 0x00007f00
+#define UCR0_UDIV_POS 0
+#define UCR1_UDIV_POS 8
+#define UDIV_MAX 127
+#elif defined(CONFIG_405EX)
+#define UART0_BASE 0xef600200
+#define UART1_BASE 0xef600300
+#define CR0_MASK 0x000000ff
+#define CR0_EXTCLK_ENA 0x00800000
+#define CR0_UDIV_POS 0
+#define UDIV_SUBTRACT 0
+#define UART0_SDR sdr_uart0
+#define UART1_SDR sdr_uart1
+#else /* CONFIG_405GP || CONFIG_405CR */
+#define UART0_BASE 0xef600300
+#define UART1_BASE 0xef600400
+#define CR0_MASK 0x00001fff
+#define CR0_EXTCLK_ENA 0x000000c0
+#define CR0_UDIV_POS 1
+#define UDIV_MAX 32
+#endif
+
+/* using serial port 0 or 1 as U-Boot console ? */
+#if defined(CONFIG_UART1_CONSOLE)
+#define ACTING_UART0_BASE UART1_BASE
+#define ACTING_UART1_BASE UART0_BASE
+#else
+#define ACTING_UART0_BASE UART0_BASE
+#define ACTING_UART1_BASE UART1_BASE
+#endif
+
+#if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK)
+#error "External serial clock not supported on AMCC PPC405EP!"
+#endif
+
+#define UART_RBR 0x00
+#define UART_THR 0x00
+#define UART_IER 0x01
+#define UART_IIR 0x02
+#define UART_FCR 0x02
+#define UART_LCR 0x03
+#define UART_MCR 0x04
+#define UART_LSR 0x05
+#define UART_MSR 0x06
+#define UART_SCR 0x07
+#define UART_DLL 0x00
+#define UART_DLM 0x01
+
+/*-----------------------------------------------------------------------------+
+ | Line Status Register.
+ +-----------------------------------------------------------------------------*/
+#define asyncLSRDataReady1 0x01
+#define asyncLSROverrunError1 0x02
+#define asyncLSRParityError1 0x04
+#define asyncLSRFramingError1 0x08
+#define asyncLSRBreakInterrupt1 0x10
+#define asyncLSRTxHoldEmpty1 0x20
+#define asyncLSRTxShiftEmpty1 0x40
+#define asyncLSRRxFifoError1 0x80
+
+#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
+/*-----------------------------------------------------------------------------+
+ | Fifo
+ +-----------------------------------------------------------------------------*/
+typedef struct {
+ char *rx_buffer;
+ ulong rx_put;
+ ulong rx_get;
+} serial_buffer_t;
+
+volatile static serial_buffer_t buf_info;
+#endif
+
+static void serial_init_common(u32 base, u32 udiv, u16 bdiv)
+{
+ PPC4xx_SYS_INFO sys_info;
+ u8 val;
+
+ get_sys_info(&sys_info);
+
+ /* Correct UART frequency in bd-info struct now that
+ * the UART divisor is available
+ */
+#ifdef CFG_EXT_SERIAL_CLOCK
+ gd->uart_clk = CFG_EXT_SERIAL_CLOCK;
+#else
+ gd->uart_clk = sys_info.freqUART / udiv;
+#endif
+
+ out_8((u8 *)base + UART_LCR, 0x80); /* set DLAB bit */
+ out_8((u8 *)base + UART_DLL, bdiv); /* set baudrate divisor */
+ out_8((u8 *)base + UART_DLM, bdiv >> 8); /* set baudrate divisor */
+ out_8((u8 *)base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
+ out_8((u8 *)base + UART_FCR, 0x00); /* disable FIFO */
+ out_8((u8 *)base + UART_MCR, 0x00); /* no modem control DTR RTS */
+ val = in_8((u8 *)base + UART_LSR); /* clear line status */
+ val = in_8((u8 *)base + UART_RBR); /* read receive buffer */
+ out_8((u8 *)base + UART_SCR, 0x00); /* set scratchpad */
+ out_8((u8 *)base + UART_IER, 0x00); /* set interrupt enable reg */
+}
+
+#if (defined(CONFIG_440) || defined(CONFIG_405EX)) && \
+ !defined(CFG_EXT_SERIAL_CLOCK)
+static void serial_divs (int baudrate, unsigned long *pudiv,
+ unsigned short *pbdiv)
+{
+ sys_info_t sysinfo;
+ unsigned long div; /* total divisor udiv * bdiv */
+ unsigned long umin; /* minimum udiv */
+ unsigned short diff; /* smallest diff */
+ unsigned long udiv; /* best udiv */
+ unsigned short idiff; /* current diff */
+ unsigned short ibdiv; /* current bdiv */
+ unsigned long i;
+ unsigned long est; /* current estimate */
+
+ get_sys_info(&sysinfo);
+
+ udiv = 32; /* Assume lowest possible serial clk */
+ div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */
+ umin = sysinfo.pllOpbDiv << 1; /* 2 x OPB divisor */
+ diff = 32; /* highest possible */
+
+ /* i is the test udiv value -- start with the largest
+ * possible (32) to minimize serial clock and constrain
+ * search to umin.
+ */
+ for (i = 32; i > umin; i--) {
+ ibdiv = div / i;
+ est = i * ibdiv;
+ idiff = (est > div) ? (est-div) : (div-est);
+ if (idiff == 0) {
+ udiv = i;
+ break; /* can't do better */
+ } else if (idiff < diff) {
+ udiv = i; /* best so far */
+ diff = idiff; /* update lowest diff*/
+ }
+ }
+
+ *pudiv = udiv;
+ *pbdiv = div / udiv;
+}
+
+#elif defined(CONFIG_405EZ)
+
+static void serial_divs (int baudrate, unsigned long *pudiv,
+ unsigned short *pbdiv)
+{
+ sys_info_t sysinfo;
+ unsigned long div; /* total divisor udiv * bdiv */
+ unsigned long umin; /* minimum udiv */
+ unsigned short diff; /* smallest diff */
+ unsigned long udiv; /* best udiv */
+ unsigned short idiff; /* current diff */
+ unsigned short ibdiv; /* current bdiv */
+ unsigned long i;
+ unsigned long est; /* current estimate */
+ unsigned long plloutb;
+ unsigned long cpr_pllc;
+ u32 reg;
+
+ /* check the pll feedback source */
+ mfcpr(cprpllc, cpr_pllc);
+
+ get_sys_info(&sysinfo);
+
+ plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ?
+ sysinfo.pllFwdDivB : sysinfo.pllFwdDiv) *
+ sysinfo.pllFbkDiv) / sysinfo.pllFwdDivB);
+ udiv = 256; /* Assume lowest possible serial clk */
+ div = plloutb / (16 * baudrate); /* total divisor */
+ umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */
+ diff = 256; /* highest possible */
+
+ /* i is the test udiv value -- start with the largest
+ * possible (256) to minimize serial clock and constrain
+ * search to umin.
+ */
+ for (i = 256; i > umin; i--) {
+ ibdiv = div / i;
+ est = i * ibdiv;
+ idiff = (est > div) ? (est-div) : (div-est);
+ if (idiff == 0) {
+ udiv = i;
+ break; /* can't do better */
+ } else if (idiff < diff) {
+ udiv = i; /* best so far */
+ diff = idiff; /* update lowest diff*/
+ }
+ }
+
+ *pudiv = udiv;
+ mfcpr(cprperd0, reg);
+ reg &= ~0x0000ffff;
+ reg |= ((udiv - 0) << 8) | (udiv - 0);
+ mtcpr(cprperd0, reg);
+ *pbdiv = div / udiv;
+}
+#endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK) */
+
+/*
+ * Minimal serial functions needed to use one of the SMC ports
+ * as serial console interface.
+ */
+
+#if defined(CONFIG_440)
+int serial_init_dev(unsigned long base)
+{
+ unsigned long reg;
+ unsigned long udiv;
+ unsigned short bdiv;
+#ifdef CFG_EXT_SERIAL_CLOCK
+ unsigned long tmp;
+#endif
+
+ MFREG(UART0_SDR, reg);
+ reg &= ~CR0_MASK;
+
+#ifdef CFG_EXT_SERIAL_CLOCK
+ reg |= CR0_EXTCLK_ENA;
+ udiv = 1;
+ tmp = gd->baudrate * 16;
+ bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
+#else
+ /* For 440, the cpu clock is on divider chain A, UART on divider
+ * chain B ... so cpu clock is irrelevant. Get the "optimized"
+ * values that are subject to the 1/2 opb clock constraint
+ */
+ serial_divs (gd->baudrate, &udiv, &bdiv);
+#endif
+
+ reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */
+
+ /*
+ * Configure input clock to baudrate generator for all
+ * available serial ports here
+ */
+ MTREG(UART0_SDR, reg);
+#if defined(UART1_SDR)
+ MTREG(UART1_SDR, reg);
+#endif
+#if defined(UART2_SDR)
+ MTREG(UART2_SDR, reg);
+#endif
+#if defined(UART3_SDR)
+ MTREG(UART3_SDR, reg);
+#endif
+
+ serial_init_common(base, udiv, bdiv);
+
+ return (0);
+}
+
+#else /* !defined(CONFIG_440) */
+
+int serial_init_dev (unsigned long base)
+{
+ unsigned long reg;
+ unsigned long tmp;
+ unsigned long clk;
+ unsigned long udiv;
+ unsigned short bdiv;
+
+#ifdef CONFIG_405EX
+ clk = tmp = 0;
+ mfsdr(UART0_SDR, reg);
+ reg &= ~CR0_MASK;
+#ifdef CFG_EXT_SERIAL_CLOCK
+ reg |= CR0_EXTCLK_ENA;
+ udiv = 1;
+ tmp = gd->baudrate * 16;
+ bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
+#else
+ serial_divs(gd->baudrate, &udiv, &bdiv);
+#endif
+ reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */
+
+ /*
+ * Configure input clock to baudrate generator for all
+ * available serial ports here
+ */
+ mtsdr(UART0_SDR, reg);
+
+#if defined(UART1_SDR)
+ mtsdr(UART1_SDR, reg);
+#endif
+
+#elif defined(CONFIG_405EZ)
+ serial_divs(gd->baudrate, &udiv, &bdiv);
+ clk = tmp = reg = 0;
+#else
+#ifdef CONFIG_405EP
+ reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK);
+ clk = gd->cpu_clk;
+ tmp = CFG_BASE_BAUD * 16;
+ udiv = (clk + tmp / 2) / tmp;
+ if (udiv > UDIV_MAX) /* max. n bits for udiv */
+ udiv = UDIV_MAX;
+ reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */
+ reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */
+ mtdcr (cpc0_ucr, reg);
+#else /* CONFIG_405EP */
+ reg = mfdcr(cntrl0) & ~CR0_MASK;
+#ifdef CFG_EXT_SERIAL_CLOCK
+ clk = CFG_EXT_SERIAL_CLOCK;
+ udiv = 1;
+ reg |= CR0_EXTCLK_ENA;
+#else
+ clk = gd->cpu_clk;
+#ifdef CFG_405_UART_ERRATA_59
+ udiv = 31; /* Errata 59: stuck at 31 */
+#else
+ tmp = CFG_BASE_BAUD * 16;
+ udiv = (clk + tmp / 2) / tmp;
+ if (udiv > UDIV_MAX) /* max. n bits for udiv */
+ udiv = UDIV_MAX;
+#endif
+#endif
+ reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
+ mtdcr (cntrl0, reg);
+#endif /* CONFIG_405EP */
+ tmp = gd->baudrate * udiv * 16;
+ bdiv = (clk + tmp / 2) / tmp;
+#endif /* CONFIG_405EX */
+
+ serial_init_common(base, udiv, bdiv);
+
+ return (0);
+}
+
+#endif /* if defined(CONFIG_440) */
+
+void serial_setbrg_dev(unsigned long base)
+{
+ serial_init_dev(base);
+}
+
+void serial_putc_dev(unsigned long base, const char c)
+{
+ int i;
+
+ if (c == '\n')
+ serial_putc_dev(base, '\r');
+
+ /* check THRE bit, wait for transmiter available */
+ for (i = 1; i < 3500; i++) {
+ if ((in_8((u8 *)base + UART_LSR) & 0x20) == 0x20)
+ break;
+ udelay (100);
+ }
+
+ out_8((u8 *)base + UART_THR, c); /* put character out */
+}
+
+void serial_puts_dev (unsigned long base, const char *s)
+{
+ while (*s)
+ serial_putc_dev (base, *s++);
+}
+
+int serial_getc_dev (unsigned long base)
+{
+ unsigned char status = 0;
+
+ while (1) {
+#if defined(CONFIG_HW_WATCHDOG)
+ WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
+#endif /* CONFIG_HW_WATCHDOG */
+
+ status = in_8((u8 *)base + UART_LSR);
+ if ((status & asyncLSRDataReady1) != 0x0)
+ break;
+
+ if ((status & ( asyncLSRFramingError1 |
+ asyncLSROverrunError1 |
+ asyncLSRParityError1 |
+ asyncLSRBreakInterrupt1 )) != 0) {
+ out_8((u8 *)base + UART_LSR,
+ asyncLSRFramingError1 |
+ asyncLSROverrunError1 |
+ asyncLSRParityError1 |
+ asyncLSRBreakInterrupt1);
+ }
+ }
+
+ return (0x000000ff & (int) in_8((u8 *)base));
+}
+
+int serial_tstc_dev (unsigned long base)
+{
+ unsigned char status;
+
+ status = in_8((u8 *)base + UART_LSR);
+ if ((status & asyncLSRDataReady1) != 0x0)
+ return (1);
+
+ if ((status & ( asyncLSRFramingError1 |
+ asyncLSROverrunError1 |
+ asyncLSRParityError1 |
+ asyncLSRBreakInterrupt1 )) != 0) {
+ out_8((u8 *)base + UART_LSR,
+ asyncLSRFramingError1 |
+ asyncLSROverrunError1 |
+ asyncLSRParityError1 |
+ asyncLSRBreakInterrupt1);
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
+
+void serial_isr (void *arg)
+{
+ int space;
+ int c;
+ const int rx_get = buf_info.rx_get;
+ int rx_put = buf_info.rx_put;
+
+ if (rx_get <= rx_put)
+ space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
+ else
+ space = rx_get - rx_put;
+
+ while (serial_tstc_dev (ACTING_UART0_BASE)) {
+ c = serial_getc_dev (ACTING_UART0_BASE);
+ if (space) {
+ buf_info.rx_buffer[rx_put++] = c;
+ space--;
+ }
+ if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO)
+ rx_put = 0;
+ if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) {
+ /* Stop flow by setting RTS inactive */
+ out_8((u8 *)ACTING_UART0_BASE + UART_MCR,
+ in_8((u8 *)ACTING_UART0_BASE + UART_MCR) &
+ (0xFF ^ 0x02));
+ }
+ }
+ buf_info.rx_put = rx_put;
+}
+
+void serial_buffered_init (void)
+{
+ serial_puts ("Switching to interrupt driven serial input mode.\n");
+ buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO);
+ buf_info.rx_put = 0;
+ buf_info.rx_get = 0;
+
+ if (in_8((u8 *)ACTING_UART0_BASE + UART_MSR) & 0x10)
+ serial_puts ("Check CTS signal present on serial port: OK.\n");
+ else
+ serial_puts ("WARNING: CTS signal not present on serial port.\n");
+
+ irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ ,
+ serial_isr /*interrupt_handler_t *handler */ ,
+ (void *) &buf_info /*void *arg */ );
+
+ /* Enable "RX Data Available" Interrupt on UART */
+ out_8(ACTING_UART0_BASE + UART_IER, 0x01);
+ /* Set DTR active */
+ out_8(ACTING_UART0_BASE + UART_MCR,
+ in_8((u8 *)ACTING_UART0_BASE + UART_MCR) | 0x01);
+ /* Start flow by setting RTS active */
+ out_8(ACTING_UART0_BASE + UART_MCR,
+ in_8((u8 *)ACTING_UART0_BASE + UART_MCR) | 0x02);
+ /* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */
+ out_8(ACTING_UART0_BASE + UART_FCR, (1 << 6) | 1);
+}
+
+void serial_buffered_putc (const char c)
+{
+ /* Wait for CTS */
+#if defined(CONFIG_HW_WATCHDOG)
+ while (!(in_8((u8 *)ACTING_UART0_BASE + UART_MSR) & 0x10))
+ WATCHDOG_RESET ();
+#else
+ while (!(in_8((u8 *)ACTING_UART0_BASE + UART_MSR) & 0x10));
+#endif
+ serial_putc (c);
+}
+
+void serial_buffered_puts (const char *s)
+{
+ serial_puts (s);
+}
+
+int serial_buffered_getc (void)
+{
+ int space;
+ int c;
+ int rx_get = buf_info.rx_get;
+ int rx_put;
+
+#if defined(CONFIG_HW_WATCHDOG)
+ while (rx_get == buf_info.rx_put)
+ WATCHDOG_RESET ();
+#else
+ while (rx_get == buf_info.rx_put);
+#endif
+ c = buf_info.rx_buffer[rx_get++];
+ if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO)
+ rx_get = 0;
+ buf_info.rx_get = rx_get;
+
+ rx_put = buf_info.rx_put;
+ if (rx_get <= rx_put)
+ space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
+ else
+ space = rx_get - rx_put;
+
+ if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) {
+ /* Start flow by setting RTS active */
+ out_8(ACTING_UART0_BASE + UART_MCR,
+ in_8((u8 *)ACTING_UART0_BASE + UART_MCR) | 0x02);
+ }
+
+ return c;
+}
+
+int serial_buffered_tstc (void)
+{
+ return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0;
+}
+
+#endif /* CONFIG_SERIAL_SOFTWARE_FIFO */
+
+#if defined(CONFIG_CMD_KGDB)
+/*
+ AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port
+ number 0 or number 1
+ - if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 :
+ configuration has been already done
+ - if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 :
+ configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE
+*/
+#if (CONFIG_KGDB_SER_INDEX & 2)
+void kgdb_serial_init (void)
+{
+ u8 val;
+ u16 br_reg;
+
+ get_clocks ();
+ br_reg = (((((gd->cpu_clk / 16) / 18) * 10) / CONFIG_KGDB_BAUDRATE) +
+ 5) / 10;
+ /*
+ * Init onboard 16550 UART
+ */
+ out_8((u8 *)ACTING_UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */
+ out_8((u8 *)ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */
+ out_8((u8 *)ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */
+ out_8((u8 *)ACTING_UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */
+ out_8((u8 *)ACTING_UART1_BASE + UART_FCR, 0x00); /* disable FIFO */
+ out_8((u8 *)ACTING_UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
+ val = in_8((u8 *)ACTING_UART1_BASE + UART_LSR); /* clear line status */
+ val = in_8((u8 *)ACTING_UART1_BASE + UART_RBR); /* read receive buffer */
+ out_8((u8 *)ACTING_UART1_BASE + UART_SCR, 0x00); /* set scratchpad */
+ out_8((u8 *)ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */
+}
+
+void putDebugChar (const char c)
+{
+ if (c == '\n')
+ serial_putc ('\r');
+
+ out_8((u8 *)ACTING_UART1_BASE + UART_THR, c); /* put character out */
+
+ /* check THRE bit, wait for transfer done */
+ while ((in_8((u8 *)ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20);
+}
+
+void putDebugStr (const char *s)
+{
+ while (*s)
+ serial_putc (*s++);
+}
+
+int getDebugChar (void)
+{
+ unsigned char status = 0;
+
+ while (1) {
+ status = in_8((u8 *)ACTING_UART1_BASE + UART_LSR);
+ if ((status & asyncLSRDataReady1) != 0x0)
+ break;
+
+ if ((status & (asyncLSRFramingError1 |
+ asyncLSROverrunError1 |
+ asyncLSRParityError1 |
+ asyncLSRBreakInterrupt1 )) != 0) {
+ out_8((u8 *)ACTING_UART1_BASE + UART_LSR,
+ asyncLSRFramingError1 |
+ asyncLSROverrunError1 |
+ asyncLSRParityError1 |
+ asyncLSRBreakInterrupt1);
+ }
+ }
+
+ return (0x000000ff & (int) in_8((u8 *)ACTING_UART1_BASE));
+}
+
+void kgdb_interruptible (int yes)
+{
+ return;
+}
+
+#else /* ! (CONFIG_KGDB_SER_INDEX & 2) */
+
+void kgdb_serial_init (void)
+{
+ serial_printf ("[on serial] ");
+}
+
+void putDebugChar (int c)
+{
+ serial_putc (c);
+}
+
+void putDebugStr (const char *str)
+{
+ serial_puts (str);
+}
+
+int getDebugChar (void)
+{
+ return serial_getc ();
+}
+
+void kgdb_interruptible (int yes)
+{
+ return;
+}
+#endif /* (CONFIG_KGDB_SER_INDEX & 2) */
+#endif
+
+
+#if defined(CONFIG_SERIAL_MULTI)
+int serial0_init(void)
+{
+ return (serial_init_dev(UART0_BASE));
+}
+
+int serial1_init(void)
+{
+ return (serial_init_dev(UART1_BASE));
+}
+
+void serial0_setbrg (void)
+{
+ serial_setbrg_dev(UART0_BASE);
+}
+
+void serial1_setbrg (void)
+{
+ serial_setbrg_dev(UART1_BASE);
+}
+
+void serial0_putc(const char c)
+{
+ serial_putc_dev(UART0_BASE,c);
+}
+
+void serial1_putc(const char c)
+{
+ serial_putc_dev(UART1_BASE, c);
+}
+
+void serial0_puts(const char *s)
+{
+ serial_puts_dev(UART0_BASE, s);
+}
+
+void serial1_puts(const char *s)
+{
+ serial_puts_dev(UART1_BASE, s);
+}
+
+int serial0_getc(void)
+{
+ return(serial_getc_dev(UART0_BASE));
+}
+
+int serial1_getc(void)
+{
+ return(serial_getc_dev(UART1_BASE));
+}
+
+int serial0_tstc(void)
+{
+ return (serial_tstc_dev(UART0_BASE));
+}
+
+int serial1_tstc(void)
+{
+ return (serial_tstc_dev(UART1_BASE));
+}
+
+struct serial_device serial0_device =
+{
+ "serial0",
+ "UART0",
+ serial0_init,
+ serial0_setbrg,
+ serial0_getc,
+ serial0_tstc,
+ serial0_putc,
+ serial0_puts,
+};
+
+struct serial_device serial1_device =
+{
+ "serial1",
+ "UART1",
+ serial1_init,
+ serial1_setbrg,
+ serial1_getc,
+ serial1_tstc,
+ serial1_putc,
+ serial1_puts,
+};
+#else
+/*
+ * Wrapper functions
+ */
+int serial_init(void)
+{
+ return serial_init_dev(ACTING_UART0_BASE);
+}
+
+void serial_setbrg(void)
+{
+ serial_setbrg_dev(ACTING_UART0_BASE);
+}
+
+void serial_putc(const char c)
+{
+ serial_putc_dev(ACTING_UART0_BASE, c);
+}
+
+void serial_puts(const char *s)
+{
+ serial_puts_dev(ACTING_UART0_BASE, s);
+}
+
+int serial_getc(void)
+{
+ return serial_getc_dev(ACTING_UART0_BASE);
+}
+
+int serial_tstc(void)
+{
+ return serial_tstc_dev(ACTING_UART0_BASE);
+}
+#endif /* CONFIG_SERIAL_MULTI */
+
+#endif /* CONFIG_405GP || CONFIG_405CR */
LIB = $(obj)lib$(CPU).a
-START = start.o resetvec.o kgdb.o
-SOBJS = dcr.o
-COBJS = 405gp_pci.o 440spe_pcie.o 4xx_enet.o \
- bedbug_405.o commproc.o \
- cpu.o cpu_init.o gpio.o i2c.o interrupts.o \
- miiphy.o ndfc.o sdram.o serial.o \
- 40x_spd_sdram.o 44x_spd_ddr.o 44x_spd_ddr2.o speed.o \
- tlb.o traps.o usb_ohci.o usb.o usbdev.o \
- 440spe_pcie.o
+START := resetvec.o
+START += start.o
+
+SOBJS := cache.o
+SOBJS += dcr.o
+SOBJS += kgdb.o
+
+COBJS := 40x_spd_sdram.o
+COBJS += 44x_spd_ddr.o
+COBJS += 44x_spd_ddr2.o
+COBJS += 4xx_enet.o
+COBJS += 4xx_pci.o
+COBJS += 4xx_pcie.o
+COBJS += 4xx_uart.o
+COBJS += bedbug_405.o
+COBJS += commproc.o
+COBJS += cpu.o
+COBJS += cpu_init.o
+COBJS += denali_data_eye.o
+COBJS += denali_spd_ddr2.o
+COBJS += fdt.o
+COBJS += gpio.o
+COBJS += i2c.o
+COBJS += interrupts.o
+COBJS += iop480_uart.o
+COBJS += miiphy.o
+COBJS += ndfc.o
+COBJS += sdram.o
+COBJS += speed.o
+COBJS += tlb.o
+COBJS += traps.o
+COBJS += usb.o
+COBJS += usb_ohci.o
+COBJS += usbdev.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
--- /dev/null
+/*
+ * This file contains miscellaneous low-level functions.
+ * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
+ *
+ * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
+ * and Paul Mackerras.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ */
+
+#include <config.h>
+#include <config.h>
+#include <ppc4xx.h>
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+/*
+ * Flush instruction cache.
+ */
+_GLOBAL(invalidate_icache)
+ iccci r0,r0
+ isync
+ blr
+
+/*
+ * Write any modified data cache blocks out to memory
+ * and invalidate the corresponding instruction cache blocks.
+ *
+ * flush_icache_range(unsigned long start, unsigned long stop)
+ */
+_GLOBAL(flush_icache_range)
+ li r5,L1_CACHE_BYTES-1
+ andc r3,r3,r5
+ subf r4,r3,r4
+ add r4,r4,r5
+ srwi. r4,r4,L1_CACHE_SHIFT
+ beqlr
+ mtctr r4
+ mr r6,r3
+1: dcbst 0,r3
+ addi r3,r3,L1_CACHE_BYTES
+ bdnz 1b
+ sync /* wait for dcbst's to get to ram */
+ mtctr r4
+2: icbi 0,r6
+ addi r6,r6,L1_CACHE_BYTES
+ bdnz 2b
+ sync /* additional sync needed on g4 */
+ isync
+ blr
+
+/*
+ * Write any modified data cache blocks out to memory.
+ * Does not invalidate the corresponding cache lines (especially for
+ * any corresponding instruction cache).
+ *
+ * clean_dcache_range(unsigned long start, unsigned long stop)
+ */
+_GLOBAL(clean_dcache_range)
+ li r5,L1_CACHE_BYTES-1
+ andc r3,r3,r5
+ subf r4,r3,r4
+ add r4,r4,r5
+ srwi. r4,r4,L1_CACHE_SHIFT
+ beqlr
+ mtctr r4
+
+1: dcbst 0,r3
+ addi r3,r3,L1_CACHE_BYTES
+ bdnz 1b
+ sync /* wait for dcbst's to get to ram */
+ blr
+
+/*
+ * Write any modified data cache blocks out to memory and invalidate them.
+ * Does not invalidate the corresponding instruction cache blocks.
+ *
+ * flush_dcache_range(unsigned long start, unsigned long stop)
+ */
+_GLOBAL(flush_dcache_range)
+ li r5,L1_CACHE_BYTES-1
+ andc r3,r3,r5
+ subf r4,r3,r4
+ add r4,r4,r5
+ srwi. r4,r4,L1_CACHE_SHIFT
+ beqlr
+ mtctr r4
+
+1: dcbf 0,r3
+ addi r3,r3,L1_CACHE_BYTES
+ bdnz 1b
+ sync /* wait for dcbst's to get to ram */
+ blr
+
+/*
+ * Like above, but invalidate the D-cache. This is used by the 8xx
+ * to invalidate the cache so the PPC core doesn't get stale data
+ * from the CPM (no cache snooping here :-).
+ *
+ * invalidate_dcache_range(unsigned long start, unsigned long stop)
+ */
+_GLOBAL(invalidate_dcache_range)
+ li r5,L1_CACHE_BYTES-1
+ andc r3,r3,r5
+ subf r4,r3,r4
+ add r4,r4,r5
+ srwi. r4,r4,L1_CACHE_SHIFT
+ beqlr
+ mtctr r4
+
+1: dcbi 0,r3
+ addi r3,r3,L1_CACHE_BYTES
+ bdnz 1b
+ sync /* wait for dcbi's to get to ram */
+ blr
+
+/*
+ * 40x cores have 8K or 16K dcache and 32 byte line size.
+ * 44x has a 32K dcache and 32 byte line size.
+ * 8xx has 1, 2, 4, 8K variants.
+ * For now, cover the worst case of the 44x.
+ * Must be called with external interrupts disabled.
+ */
+#define CACHE_NWAYS 64
+#define CACHE_NLINES 32
+
+_GLOBAL(flush_dcache)
+ li r4,(2 * CACHE_NWAYS * CACHE_NLINES)
+ mtctr r4
+ lis r5,0
+1: lwz r3,0(r5) /* Load one word from every line */
+ addi r5,r5,L1_CACHE_BYTES
+ bdnz 1b
+ sync
+ blr
+
+_GLOBAL(invalidate_dcache)
+ addi r6,0,0x0000 /* clear GPR 6 */
+ /* Do loop for # of dcache congruence classes. */
+ lis r7,(CFG_DCACHE_SIZE / L1_CACHE_BYTES / 2)@ha /* TBS for large sized cache */
+ ori r7,r7,(CFG_DCACHE_SIZE / L1_CACHE_BYTES / 2)@l
+ /* NOTE: dccci invalidates both */
+ mtctr r7 /* ways in the D cache */
+..dcloop:
+ dccci 0,r6 /* invalidate line */
+ addi r6,r6,L1_CACHE_BYTES /* bump to next line */
+ bdnz ..dcloop
+ sync
+ blr
+
+/*
+ * Cache functions.
+ *
+ * NOTE: currently the 440s run with dcache _disabled_ once relocated to DRAM,
+ * although for some cache-ralated calls stubs have to be provided to satisfy
+ * symbols resolution.
+ * Icache-related functions are used in POST framework.
+ *
+ */
+#ifdef CONFIG_440
+
+ .globl dcache_disable
+ .globl icache_disable
+ .globl icache_enable
+dcache_disable:
+icache_disable:
+icache_enable:
+ blr
+
+ .globl dcache_status
+ .globl icache_status
+dcache_status:
+icache_status:
+ mr r3, 0
+ blr
+
+#else /* CONFIG_440 */
+
+ .globl icache_enable
+icache_enable:
+ mflr r8
+ bl invalidate_icache
+ mtlr r8
+ isync
+ addis r3,r0, 0xc000 /* set bit 0 */
+ mticcr r3
+ blr
+
+ .globl icache_disable
+icache_disable:
+ addis r3,r0, 0x0000 /* clear bit 0 */
+ mticcr r3
+ isync
+ blr
+
+ .globl icache_status
+icache_status:
+ mficcr r3
+ srwi r3, r3, 31 /* >>31 => select bit 0 */
+ blr
+
+ .globl dcache_enable
+dcache_enable:
+ mflr r8
+ bl invalidate_dcache
+ mtlr r8
+ isync
+ addis r3,r0, 0x8000 /* set bit 0 */
+ mtdccr r3
+ blr
+
+ .globl dcache_disable
+dcache_disable:
+ mflr r8
+ bl flush_dcache
+ mtlr r8
+ addis r3,r0, 0x0000 /* clear bit 0 */
+ mtdccr r3
+ blr
+
+ .globl dcache_status
+dcache_status:
+ mfdccr r3
+ srwi r3, r3, 31 /* >>31 => select bit 0 */
+ blr
+
+#endif /* CONFIG_440 */
/*
- * (C) Copyright 2000-2006
+ * (C) Copyright 2000-2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
#include <asm/cache.h>
#include <ppc4xx.h>
-#if !defined(CONFIG_405)
DECLARE_GLOBAL_DATA_PTR;
-#endif
-#if defined(CONFIG_BOARD_RESET)
void board_reset(void);
-#endif
-
-#if defined(CONFIG_440)
-#define FREQ_EBC (sys_info.freqEPB)
-#elif defined(CONFIG_405EZ)
-#define FREQ_EBC ((CONFIG_SYS_CLK_FREQ * sys_info.pllFbkDiv) / \
- sys_info.pllExtBusDiv)
-#else
-#define FREQ_EBC (sys_info.freqPLB / sys_info.pllExtBusDiv)
-#endif
#if defined(CONFIG_405GP) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
#define PCI_ASYNC
-int pci_async_enabled(void)
+static int pci_async_enabled(void)
{
#if defined(CONFIG_405GP)
return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
}
#endif
-#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && !defined(CONFIG_405)
-int pci_arbiter_enabled(void)
+#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \
+ !defined(CONFIG_405) && !defined(CONFIG_405EX)
+static int pci_arbiter_enabled(void)
{
#if defined(CONFIG_405GP)
return (mfdcr(strap) & PSR_PCI_ARBIT_EN);
}
#endif
-#if defined(CONFIG_405EP) || defined(CONFIG_440GX) || \
- defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_440SP) || defined(CONFIG_440SPE)
-
+#if defined(CONFIG_405EP)
#define I2C_BOOTROM
-int i2c_bootrom_enabled(void)
+static int i2c_bootrom_enabled(void)
{
#if defined(CONFIG_405EP)
return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
'I', 'x', 'K', 'L', 'M', 'N', 'O', 'P' };
#endif
+#if defined(CONFIG_405EX)
+#define SDR0_PINSTP_SHIFT 29
+static char *bootstrap_str[] = {
+ "EBC (8 bits)",
+ "EBC (16 bits)",
+ "EBC (16 bits)",
+ "NAND (8 bits)",
+ "NAND (8 bits)",
+ "I2C (Addr 0x54)",
+ "EBC (8 bits)",
+ "I2C (Addr 0x52)",
+};
+static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
+#endif
+
#if defined(SDR0_PINSTP_SHIFT)
static int bootstrap_option(void)
{
#if defined(CONFIG_440)
-static int do_chip_reset(unsigned long sys0, unsigned long sys1);
+static int do_chip_reset (unsigned long sys0, unsigned long sys1)
+{
+ /* Changes to cpc0_sys0 and cpc0_sys1 require chip
+ * reset.
+ */
+ mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000); /* Set SWE */
+ mtdcr (cpc0_sys0, sys0);
+ mtdcr (cpc0_sys1, sys1);
+ mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */
+ mtspr (dbcr0, 0x20000000); /* Reset the chip */
+
+ return 1;
+}
#endif
puts("AMCC PowerPC 4");
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
- defined(CONFIG_405EP) || defined(CONFIG_405EZ)
+ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
+ defined(CONFIG_405EX)
puts("05");
#endif
#if defined(CONFIG_440)
puts("EZ Rev. A");
break;
+ case PVR_405EX1_RA:
+ puts("EX Rev. A");
+ strcpy(addstr, "Security support");
+ break;
+
+ case PVR_405EX2_RA:
+ puts("EX Rev. A");
+ strcpy(addstr, "No Security support");
+ break;
+
+ case PVR_405EXR1_RA:
+ puts("EXr Rev. A");
+ strcpy(addstr, "Security support");
+ break;
+
+ case PVR_405EXR2_RA:
+ puts("EXr Rev. A");
+ strcpy(addstr, "No Security support");
+ break;
+
#if defined(CONFIG_440)
case PVR_440GP_RB:
puts("GP Rev. B");
printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
sys_info.freqPLB / 1000000,
get_OPB_freq() / 1000000,
- FREQ_EBC / 1000000);
+ sys_info.freqEBC / 1000000);
if (addstr[0] != 0)
printf(" %s\n", addstr);
printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]);
#endif /* SDR0_PINSTP_SHIFT */
-#if defined(CONFIG_PCI)
+#if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
#endif
}
#endif
-#if defined(CONFIG_PCI)
+#if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
putc('\n');
#endif
-#if defined(CONFIG_405EP) || defined(CONFIG_405EZ)
+#if defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX)
printf (" 16 kB I-Cache 16 kB D-Cache");
#elif defined(CONFIG_440)
printf (" 32 kB I-Cache 32 kB D-Cache");
return 0;
}
-#if defined (CONFIG_440SPE)
int ppc440spe_revB() {
unsigned int pvr;
else
return 0;
}
-#endif
/* ------------------------------------------------------------------------- */
return 1;
}
-#if defined(CONFIG_440)
-static int do_chip_reset (unsigned long sys0, unsigned long sys1)
-{
- /* Changes to cpc0_sys0 and cpc0_sys1 require chip
- * reset.
- */
- mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000); /* Set SWE */
- mtdcr (cpc0_sys0, sys0);
- mtdcr (cpc0_sys1, sys1);
- mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */
- mtspr (dbcr0, 0x20000000); /* Reset the chip */
-
- return 1;
-}
-#endif
-
/*
* Get timebase clock frequency
#if defined(CONFIG_WATCHDOG)
-void
-watchdog_reset(void)
+void watchdog_reset(void)
{
int re_enable = disable_interrupts();
reset_4xx_watchdog();
if (re_enable) enable_interrupts();
}
-void
-reset_4xx_watchdog(void)
+void reset_4xx_watchdog(void)
{
/*
* Clear TSR(WIS) bit
/*
- * (C) Copyright 2000-2006
+ * (C) Copyright 2000-2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
unsigned long val;
#endif
-#if defined(CONFIG_405EP)
+#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CFG_4xx_GPIO_TABLE)
/*
* GPIO0 setup (select GPIO or alternate function)
*/
out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */
out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
+#if defined(CFG_GPIO0_ISR2H)
+ out32(GPIO0_ISR2H, CFG_GPIO0_ISR2H);
+ out32(GPIO0_ISR2L, CFG_GPIO0_ISR2L);
+#endif
+#if defined (CFG_GPIO0_TCR)
out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
+#endif
+#if defined (CONFIG_405EP)
/*
* Set EMAC noise filter bits
*/
mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE);
+
+ /*
+ * Enable the internal PCI arbiter
+ */
+ mtdcr(cpc0_pci, mfdcr(cpc0_pci) | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
+#endif /* CONFIG_405EP */
#endif /* CONFIG_405EP */
-#if defined(CFG_440_GPIO_TABLE)
+#if defined(CFG_4xx_GPIO_TABLE)
gpio_set_chip_configuration();
-#endif /* CFG_440_GPIO_TABLE */
+#endif /* CFG_4xx_GPIO_TABLE */
/*
* External Bus Controller (EBC) Setup
#if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
#if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
- defined(CONFIG_405))
+ defined(CONFIG_405EX) || defined(CONFIG_405))
/*
* Move the next instructions into icache, since these modify the flash
* we are running from!
--- /dev/null
+/*
+ * cpu/ppc4xx/denali_data_eye.c
+ * Extracted from board/amcc/sequoia/sdram.c by Larry Johnson <lrj@acm.org>.
+ *
+ * (C) Copyright 2006
+ * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
+ * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
+ * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
+ *
+ * (C) Copyright 2006-2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* define DEBUG for debugging output (obviously ;-)) */
+#if 0
+#define DEBUG
+#endif
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <ppc4xx.h>
+
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+/*-----------------------------------------------------------------------------+
+ * denali_wait_for_dlllock.
+ +----------------------------------------------------------------------------*/
+int denali_wait_for_dlllock(void)
+{
+ u32 val;
+ int wait;
+
+ /* -----------------------------------------------------------+
+ * Wait for the DCC master delay line to finish calibration
+ * ----------------------------------------------------------*/
+ for (wait = 0; wait != 0xffff; ++wait) {
+ mfsdram(DDR0_17, val);
+ if (DDR0_17_DLLLOCKREG_DECODE(val)) {
+ /* dlllockreg bit on */
+ return 0;
+ }
+ }
+ debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
+ debug("Waiting for dlllockreg bit to raise\n");
+ return -1;
+}
+
+#if defined(CONFIG_DDR_DATA_EYE)
+#define DDR_DCR_BASE 0x10
+#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */
+#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */
+
+/*-----------------------------------------------------------------------------+
+ * wait_for_dram_init_complete.
+ +----------------------------------------------------------------------------*/
+static int wait_for_dram_init_complete(void)
+{
+ unsigned long val;
+ int wait = 0;
+
+ /* --------------------------------------------------------------+
+ * Wait for 'DRAM initialization complete' bit in status register
+ * -------------------------------------------------------------*/
+ mtdcr(ddrcfga, DDR0_00);
+
+ while (wait != 0xffff) {
+ val = mfdcr(ddrcfgd);
+ if ((val & DDR0_00_INT_STATUS_BIT6) == DDR0_00_INT_STATUS_BIT6)
+ /* 'DRAM initialization complete' bit */
+ return 0;
+ else
+ wait++;
+ }
+ debug("DRAM initialization complete bit in status register did not "
+ "rise\n");
+ return -1;
+}
+
+#define NUM_TRIES 64
+#define NUM_READS 10
+
+/*-----------------------------------------------------------------------------+
+ * denali_core_search_data_eye.
+ +----------------------------------------------------------------------------*/
+/*
+ * Avoid conflict with implementations of denali_core_search_data_eye in board-
+ * specific code.
+ */
+void denali_core_search_data_eye(void)
+ __attribute__ ((weak, alias("__denali_core_search_data_eye")));
+
+void __denali_core_search_data_eye(void)
+{
+ int k, j;
+ u32 val;
+ u32 wr_dqs_shift, dqs_out_shift, dll_dqs_delay_X;
+ u32 max_passing_cases = 0, wr_dqs_shift_with_max_passing_cases = 0;
+ u32 passing_cases = 0, dll_dqs_delay_X_sw_val = 0;
+ u32 dll_dqs_delay_X_start_window = 0, dll_dqs_delay_X_end_window = 0;
+ volatile u32 *ram_pointer;
+ u32 test[NUM_TRIES] = {
+ 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
+ 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
+ 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
+ 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
+ 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
+ 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
+ 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
+ 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
+ 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
+ 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
+ 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
+ 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
+ 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55
+ };
+
+ ram_pointer = (volatile u32 *)(CFG_SDRAM_BASE);
+
+ for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) {
+ /* for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) { */
+
+ /* -----------------------------------------------------------+
+ * De-assert 'start' parameter.
+ * ----------------------------------------------------------*/
+ mtdcr(ddrcfga, DDR0_02);
+ val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) |
+ DDR0_02_START_OFF;
+ mtdcr(ddrcfgd, val);
+
+ /* -----------------------------------------------------------+
+ * Set 'wr_dqs_shift'
+ * ----------------------------------------------------------*/
+ mtdcr(ddrcfga, DDR0_09);
+ val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) |
+ DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
+ mtdcr(ddrcfgd, val);
+
+ /* -----------------------------------------------------------+
+ * Set 'dqs_out_shift' = wr_dqs_shift + 32
+ * ----------------------------------------------------------*/
+ dqs_out_shift = wr_dqs_shift + 32;
+ mtdcr(ddrcfga, DDR0_22);
+ val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) |
+ DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
+ mtdcr(ddrcfgd, val);
+
+ passing_cases = 0;
+
+ for (dll_dqs_delay_X = 1; dll_dqs_delay_X < 64;
+ dll_dqs_delay_X++) {
+ /* for (dll_dqs_delay_X=1; dll_dqs_delay_X<128;
+ dll_dqs_delay_X++) { */
+ /* -----------------------------------------------------------+
+ * Set 'dll_dqs_delay_X'.
+ * ----------------------------------------------------------*/
+ /* dll_dqs_delay_0 */
+ mtdcr(ddrcfga, DDR0_17);
+ val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
+ | DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
+ mtdcr(ddrcfgd, val);
+ /* dll_dqs_delay_1 to dll_dqs_delay_4 */
+ mtdcr(ddrcfga, DDR0_18);
+ val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
+ | DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
+ | DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
+ | DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
+ | DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
+ mtdcr(ddrcfgd, val);
+ /* dll_dqs_delay_5 to dll_dqs_delay_8 */
+ mtdcr(ddrcfga, DDR0_19);
+ val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
+ | DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
+ | DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
+ | DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
+ | DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
+ mtdcr(ddrcfgd, val);
+ /* clear any ECC errors */
+ mtdcr(ddrcfga, DDR0_00);
+ mtdcr(ddrcfgd,
+ mfdcr(ddrcfgd) | DDR0_00_INT_ACK_ENCODE(0x3C));
+
+ sync();
+ eieio();
+
+ /* -----------------------------------------------------------+
+ * Assert 'start' parameter.
+ * ----------------------------------------------------------*/
+ mtdcr(ddrcfga, DDR0_02);
+ val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) |
+ DDR0_02_START_ON;
+ mtdcr(ddrcfgd, val);
+
+ sync();
+ eieio();
+
+ /* -----------------------------------------------------------+
+ * Wait for the DCC master delay line to finish calibration
+ * ----------------------------------------------------------*/
+ if (denali_wait_for_dlllock() != 0) {
+ printf("dll lock did not occur !!!\n");
+ printf("denali_core_search_data_eye!!!\n");
+ printf("wr_dqs_shift = %d - dll_dqs_delay_X = "
+ "%d\n", wr_dqs_shift, dll_dqs_delay_X);
+ hang();
+ }
+ sync();
+ eieio();
+
+ if (wait_for_dram_init_complete() != 0) {
+ printf("dram init complete did not occur!!!\n");
+ printf("denali_core_search_data_eye!!!\n");
+ printf("wr_dqs_shift = %d - dll_dqs_delay_X = "
+ "%d\n", wr_dqs_shift, dll_dqs_delay_X);
+ hang();
+ }
+ udelay(100); /* wait 100us to ensure init is really completed !!! */
+
+ /* write values */
+ for (j = 0; j < NUM_TRIES; j++) {
+ ram_pointer[j] = test[j];
+
+ /* clear any cache at ram location */
+ __asm__("dcbf 0,%0": :"r"(&ram_pointer[j]));
+ }
+
+ /* read values back */
+ for (j = 0; j < NUM_TRIES; j++) {
+ for (k = 0; k < NUM_READS; k++) {
+ /* clear any cache at ram location */
+ __asm__("dcbf 0,%0": :"r"(&ram_pointer
+ [j]));
+
+ if (ram_pointer[j] != test[j])
+ break;
+ }
+
+ /* read error */
+ if (k != NUM_READS)
+ break;
+ }
+
+ /* See if the dll_dqs_delay_X value passed. */
+ mtdcr(ddrcfga, DDR0_00);
+ if (j < NUM_TRIES
+ || (DDR0_00_INT_STATUS_DECODE(mfdcr(ddrcfgd)) &
+ 0x3F)) {
+ /* Failed */
+ passing_cases = 0;
+ /* break; */
+ } else {
+ /* Passed */
+ if (passing_cases == 0)
+ dll_dqs_delay_X_sw_val =
+ dll_dqs_delay_X;
+ passing_cases++;
+ if (passing_cases >= max_passing_cases) {
+ max_passing_cases = passing_cases;
+ wr_dqs_shift_with_max_passing_cases =
+ wr_dqs_shift;
+ dll_dqs_delay_X_start_window =
+ dll_dqs_delay_X_sw_val;
+ dll_dqs_delay_X_end_window =
+ dll_dqs_delay_X;
+ }
+ }
+
+ /* -----------------------------------------------------------+
+ * De-assert 'start' parameter.
+ * ----------------------------------------------------------*/
+ mtdcr(ddrcfga, DDR0_02);
+ val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) |
+ DDR0_02_START_OFF;
+ mtdcr(ddrcfgd, val);
+ } /* for (dll_dqs_delay_X=0; dll_dqs_delay_X<128; dll_dqs_delay_X++) */
+ } /* for (wr_dqs_shift=0; wr_dqs_shift<96; wr_dqs_shift++) */
+
+ /* -----------------------------------------------------------+
+ * Largest passing window is now detected.
+ * ----------------------------------------------------------*/
+
+ /* Compute dll_dqs_delay_X value */
+ dll_dqs_delay_X = (dll_dqs_delay_X_end_window +
+ dll_dqs_delay_X_start_window) / 2;
+ wr_dqs_shift = wr_dqs_shift_with_max_passing_cases;
+
+ debug("DQS calibration - Window detected:\n");
+ debug("max_passing_cases = %d\n", max_passing_cases);
+ debug("wr_dqs_shift = %d\n", wr_dqs_shift);
+ debug("dll_dqs_delay_X = %d\n", dll_dqs_delay_X);
+ debug("dll_dqs_delay_X window = %d - %d\n",
+ dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window);
+
+ /* -----------------------------------------------------------+
+ * De-assert 'start' parameter.
+ * ----------------------------------------------------------*/
+ mtdcr(ddrcfga, DDR0_02);
+ val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
+ mtdcr(ddrcfgd, val);
+
+ /* -----------------------------------------------------------+
+ * Set 'wr_dqs_shift'
+ * ----------------------------------------------------------*/
+ mtdcr(ddrcfga, DDR0_09);
+ val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
+ | DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
+ mtdcr(ddrcfgd, val);
+ debug("DDR0_09=0x%08lx\n", val);
+
+ /* -----------------------------------------------------------+
+ * Set 'dqs_out_shift' = wr_dqs_shift + 32
+ * ----------------------------------------------------------*/
+ dqs_out_shift = wr_dqs_shift + 32;
+ mtdcr(ddrcfga, DDR0_22);
+ val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
+ | DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
+ mtdcr(ddrcfgd, val);
+ debug("DDR0_22=0x%08lx\n", val);
+
+ /* -----------------------------------------------------------+
+ * Set 'dll_dqs_delay_X'.
+ * ----------------------------------------------------------*/
+ /* dll_dqs_delay_0 */
+ mtdcr(ddrcfga, DDR0_17);
+ val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
+ | DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
+ mtdcr(ddrcfgd, val);
+ debug("DDR0_17=0x%08lx\n", val);
+
+ /* dll_dqs_delay_1 to dll_dqs_delay_4 */
+ mtdcr(ddrcfga, DDR0_18);
+ val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
+ | DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
+ | DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
+ | DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
+ | DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
+ mtdcr(ddrcfgd, val);
+ debug("DDR0_18=0x%08lx\n", val);
+
+ /* dll_dqs_delay_5 to dll_dqs_delay_8 */
+ mtdcr(ddrcfga, DDR0_19);
+ val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
+ | DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
+ | DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
+ | DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
+ | DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
+ mtdcr(ddrcfgd, val);
+ debug("DDR0_19=0x%08lx\n", val);
+
+ /* -----------------------------------------------------------+
+ * Assert 'start' parameter.
+ * ----------------------------------------------------------*/
+ mtdcr(ddrcfga, DDR0_02);
+ val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
+ mtdcr(ddrcfgd, val);
+
+ sync();
+ eieio();
+
+ /* -----------------------------------------------------------+
+ * Wait for the DCC master delay line to finish calibration
+ * ----------------------------------------------------------*/
+ if (denali_wait_for_dlllock() != 0) {
+ printf("dll lock did not occur !!!\n");
+ hang();
+ }
+ sync();
+ eieio();
+
+ if (wait_for_dram_init_complete() != 0) {
+ printf("dram init complete did not occur !!!\n");
+ hang();
+ }
+ udelay(100); /* wait 100us to ensure init is really completed !!! */
+}
+#endif /* defined(CONFIG_DDR_DATA_EYE) */
+#endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */
--- /dev/null
+/*
+ * cpu/ppc4xx/denali_spd_ddr2.c
+ * This SPD SDRAM detection code supports AMCC PPC44x CPUs with a Denali-core
+ * DDR2 controller, specifically the 440EPx/GRx.
+ *
+ * (C) Copyright 2007
+ * Larry Johnson, lrj@acm.org.
+ *
+ * Based primarily on cpu/ppc4xx/4xx_spd_ddr2.c, which is...
+ *
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * COPYRIGHT AMCC CORPORATION 2004
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/* define DEBUG for debugging output (obviously ;-)) */
+#if 0
+#define DEBUG
+#endif
+
+#include <common.h>
+#include <command.h>
+#include <ppc4xx.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+
+#if defined(CONFIG_SPD_EEPROM) && \
+ (defined(CONFIG_440EPX) || defined(CONFIG_440GRX))
+
+/*-----------------------------------------------------------------------------+
+ * Defines
+ *-----------------------------------------------------------------------------*/
+#ifndef TRUE
+#define TRUE 1
+#endif
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+#define MAXDIMMS 2
+#define MAXRANKS 2
+
+#define ONE_BILLION 1000000000
+
+#define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
+
+#define DLL_DQS_DELAY 0x19
+#define DLL_DQS_BYPASS 0x0B
+#define DQS_OUT_SHIFT 0x7F
+
+/*
+ * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
+ * region. Right now the cache should still be disabled in U-Boot because of the
+ * EMAC driver, that need it's buffer descriptor to be located in non cached
+ * memory.
+ *
+ * If at some time this restriction doesn't apply anymore, just define
+ * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup
+ * everything correctly.
+ */
+#if defined(CFG_ENABLE_SDRAM_CACHE)
+#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
+#else
+#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
+#endif
+
+/*-----------------------------------------------------------------------------+
+ * Prototypes
+ *-----------------------------------------------------------------------------*/
+extern int denali_wait_for_dlllock(void);
+extern void denali_core_search_data_eye(void);
+extern void dcbz_area(u32 start_address, u32 num_bytes);
+extern void dflush(void);
+
+/*
+ * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
+ */
+void __spd_ddr_init_hang(void)
+{
+ hang();
+}
+void spd_ddr_init_hang(void)
+ __attribute__ ((weak, alias("__spd_ddr_init_hang")));
+
+#if defined(DEBUG)
+static void print_mcsr(void)
+{
+ printf("MCSR = 0x%08X\n", mfspr(SPRN_MCSR));
+}
+
+static void denali_sdram_register_dump(void)
+{
+ unsigned int sdram_data;
+
+ printf("\n Register Dump:\n");
+ mfsdram(DDR0_00, sdram_data);
+ printf(" DDR0_00 = 0x%08X", sdram_data);
+ mfsdram(DDR0_01, sdram_data);
+ printf(" DDR0_01 = 0x%08X\n", sdram_data);
+ mfsdram(DDR0_02, sdram_data);
+ printf(" DDR0_02 = 0x%08X", sdram_data);
+ mfsdram(DDR0_03, sdram_data);
+ printf(" DDR0_03 = 0x%08X\n", sdram_data);
+ mfsdram(DDR0_04, sdram_data);
+ printf(" DDR0_04 = 0x%08X", sdram_data);
+ mfsdram(DDR0_05, sdram_data);
+ printf(" DDR0_05 = 0x%08X\n", sdram_data);
+ mfsdram(DDR0_06, sdram_data);
+ printf(" DDR0_06 = 0x%08X", sdram_data);
+ mfsdram(DDR0_07, sdram_data);
+ printf(" DDR0_07 = 0x%08X\n", sdram_data);
+ mfsdram(DDR0_08, sdram_data);
+ printf(" DDR0_08 = 0x%08X", sdram_data);
+ mfsdram(DDR0_09, sdram_data);
+ printf(" DDR0_09 = 0x%08X\n", sdram_data);
+ mfsdram(DDR0_10, sdram_data);
+ printf(" DDR0_10 = 0x%08X", sdram_data);
+ mfsdram(DDR0_11, sdram_data);
+ printf(" DDR0_11 = 0x%08X\n", sdram_data);
+ mfsdram(DDR0_12, sdram_data);
+ printf(" DDR0_12 = 0x%08X", sdram_data);
+ mfsdram(DDR0_14, sdram_data);
+ printf(" DDR0_14 = 0x%08X\n", sdram_data);
+ mfsdram(DDR0_17, sdram_data);
+ printf(" DDR0_17 = 0x%08X", sdram_data);
+ mfsdram(DDR0_18, sdram_data);
+ printf(" DDR0_18 = 0x%08X\n", sdram_data);
+ mfsdram(DDR0_19, sdram_data);
+ printf(" DDR0_19 = 0x%08X", sdram_data);
+ mfsdram(DDR0_20, sdram_data);
+ printf(" DDR0_20 = 0x%08X\n", sdram_data);
+ mfsdram(DDR0_21, sdram_data);
+ printf(" DDR0_21 = 0x%08X", sdram_data);
+ mfsdram(DDR0_22, sdram_data);
+ printf(" DDR0_22 = 0x%08X\n", sdram_data);
+ mfsdram(DDR0_23, sdram_data);
+ printf(" DDR0_23 = 0x%08X", sdram_data);
+ mfsdram(DDR0_24, sdram_data);
+ printf(" DDR0_24 = 0x%08X\n", sdram_data);
+ mfsdram(DDR0_25, sdram_data);
+ printf(" DDR0_25 = 0x%08X", sdram_data);
+ mfsdram(DDR0_26, sdram_data);
+ printf(" DDR0_26 = 0x%08X\n", sdram_data);
+ mfsdram(DDR0_27, sdram_data);
+ printf(" DDR0_27 = 0x%08X", sdram_data);
+ mfsdram(DDR0_28, sdram_data);
+ printf(" DDR0_28 = 0x%08X\n", sdram_data);
+ mfsdram(DDR0_31, sdram_data);
+ printf(" DDR0_31 = 0x%08X", sdram_data);
+ mfsdram(DDR0_32, sdram_data);
+ printf(" DDR0_32 = 0x%08X\n", sdram_data);
+ mfsdram(DDR0_33, sdram_data);
+ printf(" DDR0_33 = 0x%08X", sdram_data);
+ mfsdram(DDR0_34, sdram_data);
+ printf(" DDR0_34 = 0x%08X\n", sdram_data);
+ mfsdram(DDR0_35, sdram_data);
+ printf(" DDR0_35 = 0x%08X", sdram_data);
+ mfsdram(DDR0_36, sdram_data);
+ printf(" DDR0_36 = 0x%08X\n", sdram_data);
+ mfsdram(DDR0_37, sdram_data);
+ printf(" DDR0_37 = 0x%08X", sdram_data);
+ mfsdram(DDR0_38, sdram_data);
+ printf(" DDR0_38 = 0x%08X\n", sdram_data);
+ mfsdram(DDR0_39, sdram_data);
+ printf(" DDR0_39 = 0x%08X", sdram_data);
+ mfsdram(DDR0_40, sdram_data);
+ printf(" DDR0_40 = 0x%08X\n", sdram_data);
+ mfsdram(DDR0_41, sdram_data);
+ printf(" DDR0_41 = 0x%08X", sdram_data);
+ mfsdram(DDR0_42, sdram_data);
+ printf(" DDR0_42 = 0x%08X\n", sdram_data);
+ mfsdram(DDR0_43, sdram_data);
+ printf(" DDR0_43 = 0x%08X", sdram_data);
+ mfsdram(DDR0_44, sdram_data);
+ printf(" DDR0_44 = 0x%08X\n", sdram_data);
+}
+#else
+static inline void denali_sdram_register_dump(void)
+{
+}
+
+inline static void print_mcsr(void)
+{
+}
+#endif /* defined(DEBUG) */
+
+static int is_ecc_enabled(void)
+{
+ u32 val;
+
+ mfsdram(DDR0_22, val);
+ return 0x3 == DDR0_22_CTRL_RAW_DECODE(val);
+}
+
+static unsigned char spd_read(u8 chip, unsigned int addr)
+{
+ u8 data[2];
+
+ if (0 != i2c_probe(chip) || 0 != i2c_read(chip, addr, 1, data, 1)) {
+ debug("spd_read(0x%02X, 0x%02X) failed\n", chip, addr);
+ return 0;
+ }
+ debug("spd_read(0x%02X, 0x%02X) returned 0x%02X\n",
+ chip, addr, data[0]);
+ return data[0];
+}
+
+static unsigned long get_tcyc(unsigned char reg)
+{
+ /*
+ * Byte 9, et al: Cycle time for CAS Latency=X, is split into two
+ * nibbles: the higher order nibble (bits 4-7) designates the cycle time
+ * to a granularity of 1ns; the value presented by the lower order
+ * nibble (bits 0-3) has a granularity of .1ns and is added to the value
+ * designated by the higher nibble. In addition, four lines of the lower
+ * order nibble are assigned to support +.25, +.33, +.66, and +.75.
+ */
+
+ unsigned char subfield_b = reg & 0x0F;
+
+ switch (subfield_b & 0x0F) {
+ case 0x0:
+ case 0x1:
+ case 0x2:
+ case 0x3:
+ case 0x4:
+ case 0x5:
+ case 0x6:
+ case 0x7:
+ case 0x8:
+ case 0x9:
+ return 1000 * (reg >> 4) + 100 * subfield_b;
+ case 0xA:
+ return 1000 * (reg >> 4) + 250;
+ case 0xB:
+ return 1000 * (reg >> 4) + 333;
+ case 0xC:
+ return 1000 * (reg >> 4) + 667;
+ case 0xD:
+ return 1000 * (reg >> 4) + 750;
+ }
+ return 0;
+}
+
+/*------------------------------------------------------------------
+ * Find the installed DIMMs, make sure that the are DDR2, and fill
+ * in the dimm_ranks array. Then dimm_ranks[dimm_num] > 0 iff the
+ * DIMM and dimm_num is present.
+ * Note: Because there are only two chip-select lines, it is assumed
+ * that a board with a single socket can support two ranks on that
+ * socket, while a board with two sockets can support only one rank
+ * on each socket.
+ *-----------------------------------------------------------------*/
+static void get_spd_info(unsigned long dimm_ranks[],
+ unsigned long *ranks,
+ unsigned char const iic0_dimm_addr[],
+ unsigned long num_dimm_banks)
+{
+ unsigned long dimm_num;
+ unsigned long dimm_found = FALSE;
+ unsigned long const max_ranks_per_dimm = (1 == num_dimm_banks) ? 2 : 1;
+ unsigned char num_of_bytes;
+ unsigned char total_size;
+
+ *ranks = 0;
+ for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
+ num_of_bytes = 0;
+ total_size = 0;
+
+ num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
+ total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
+ if ((num_of_bytes != 0) && (total_size != 0)) {
+ unsigned char const dimm_type =
+ spd_read(iic0_dimm_addr[dimm_num], 2);
+
+ unsigned long ranks_on_dimm =
+ (spd_read(iic0_dimm_addr[dimm_num], 5) & 0x07) + 1;
+
+ if (8 != dimm_type) {
+ switch (dimm_type) {
+ case 1:
+ printf("ERROR: Standard Fast Page Mode "
+ "DRAM DIMM");
+ break;
+ case 2:
+ printf("ERROR: EDO DIMM");
+ break;
+ case 3:
+ printf("ERROR: Pipelined Nibble DIMM");
+ break;
+ case 4:
+ printf("ERROR: SDRAM DIMM");
+ break;
+ case 5:
+ printf("ERROR: Multiplexed ROM DIMM");
+ break;
+ case 6:
+ printf("ERROR: SGRAM DIMM");
+ break;
+ case 7:
+ printf("ERROR: DDR1 DIMM");
+ break;
+ default:
+ printf("ERROR: Unknown DIMM (type %d)",
+ (unsigned int)dimm_type);
+ break;
+ }
+ printf(" detected in slot %lu.\n", dimm_num);
+ printf("Only DDR2 SDRAM DIMMs are supported."
+ "\n");
+ printf("Replace the module with a DDR2 DIMM."
+ "\n\n");
+ spd_ddr_init_hang();
+ }
+ dimm_found = TRUE;
+ debug("DIMM slot %lu: populated with %lu-rank DDR2 DIMM"
+ "\n", dimm_num, ranks_on_dimm);
+ if (ranks_on_dimm > max_ranks_per_dimm) {
+ printf("WARNING: DRAM DIMM in slot %lu has %lu "
+ "ranks.\n");
+ if (1 == max_ranks_per_dimm) {
+ printf("Only one rank will be used.\n");
+ } else {
+ printf
+ ("Only two ranks will be used.\n");
+ }
+ ranks_on_dimm = max_ranks_per_dimm;
+ }
+ dimm_ranks[dimm_num] = ranks_on_dimm;
+ *ranks += ranks_on_dimm;
+ } else {
+ dimm_ranks[dimm_num] = 0;
+ debug("DIMM slot %lu: Not populated\n", dimm_num);
+ }
+ }
+ if (dimm_found == FALSE) {
+ printf("ERROR: No memory installed.\n");
+ printf("Install at least one DDR2 DIMM.\n\n");
+ spd_ddr_init_hang();
+ }
+ debug("Total number of ranks = %d\n", *ranks);
+}
+
+/*------------------------------------------------------------------
+ * For the memory DIMMs installed, this routine verifies that
+ * frequency previously calculated is supported.
+ *-----------------------------------------------------------------*/
+static void check_frequency(unsigned long *dimm_ranks,
+ unsigned char const iic0_dimm_addr[],
+ unsigned long num_dimm_banks,
+ unsigned long sdram_freq)
+{
+ unsigned long dimm_num;
+ unsigned long cycle_time;
+ unsigned long calc_cycle_time;
+
+ /*
+ * calc_cycle_time is calculated from DDR frequency set by board/chip
+ * and is expressed in picoseconds to match the way DIMM cycle time is
+ * calculated below.
+ */
+ calc_cycle_time = MULDIV64(ONE_BILLION, 1000, sdram_freq);
+
+ for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
+ if (dimm_ranks[dimm_num]) {
+ cycle_time =
+ get_tcyc(spd_read(iic0_dimm_addr[dimm_num], 9));
+ debug("cycle_time=%d ps\n", cycle_time);
+
+ if (cycle_time > (calc_cycle_time + 10)) {
+ /*
+ * the provided sdram cycle_time is too small
+ * for the available DIMM cycle_time. The
+ * additionnal 10ps is here to accept a small
+ * incertainty.
+ */
+ printf
+ ("ERROR: DRAM DIMM detected with cycle_time %d ps in "
+ "slot %d \n while calculated cycle time is %d ps.\n",
+ (unsigned int)cycle_time,
+ (unsigned int)dimm_num,
+ (unsigned int)calc_cycle_time);
+ printf
+ ("Replace the DIMM, or change DDR frequency via "
+ "strapping bits.\n\n");
+ spd_ddr_init_hang();
+ }
+ }
+ }
+}
+
+/*------------------------------------------------------------------
+ * This routine gets size information for the installed memory
+ * DIMMs.
+ *-----------------------------------------------------------------*/
+static void get_dimm_size(unsigned long dimm_ranks[],
+ unsigned char const iic0_dimm_addr[],
+ unsigned long num_dimm_banks,
+ unsigned long *const rows,
+ unsigned long *const banks,
+ unsigned long *const cols, unsigned long *const width)
+{
+ unsigned long dimm_num;
+
+ *rows = 0;
+ *banks = 0;
+ *cols = 0;
+ *width = 0;
+ for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
+ if (dimm_ranks[dimm_num]) {
+ unsigned long t;
+
+ /* Rows */
+ t = spd_read(iic0_dimm_addr[dimm_num], 3);
+ if (0 == *rows) {
+ *rows = t;
+ } else if (t != *rows) {
+ printf("ERROR: DRAM DIMM modules do not all "
+ "have the same number of rows.\n\n");
+ spd_ddr_init_hang();
+ }
+ /* Banks */
+ t = spd_read(iic0_dimm_addr[dimm_num], 17);
+ if (0 == *banks) {
+ *banks = t;
+ } else if (t != *banks) {
+ printf("ERROR: DRAM DIMM modules do not all "
+ "have the same number of banks.\n\n");
+ spd_ddr_init_hang();
+ }
+ /* Columns */
+ t = spd_read(iic0_dimm_addr[dimm_num], 4);
+ if (0 == *cols) {
+ *cols = t;
+ } else if (t != *cols) {
+ printf("ERROR: DRAM DIMM modules do not all "
+ "have the same number of columns.\n\n");
+ spd_ddr_init_hang();
+ }
+ /* Data width */
+ t = spd_read(iic0_dimm_addr[dimm_num], 6);
+ if (0 == *width) {
+ *width = t;
+ } else if (t != *width) {
+ printf("ERROR: DRAM DIMM modules do not all "
+ "have the same data width.\n\n");
+ spd_ddr_init_hang();
+ }
+ }
+ }
+ debug("Number of rows = %d\n", *rows);
+ debug("Number of columns = %d\n", *cols);
+ debug("Number of banks = %d\n", *banks);
+ debug("Data width = %d\n", *width);
+ if (*rows > 14) {
+ printf("ERROR: DRAM DIMM modules have %lu address rows.\n",
+ *rows);
+ printf("Only modules with 14 or fewer rows are supported.\n\n");
+ spd_ddr_init_hang();
+ }
+ if (4 != *banks && 8 != *banks) {
+ printf("ERROR: DRAM DIMM modules have %lu banks.\n", *banks);
+ printf("Only modules with 4 or 8 banks are supported.\n\n");
+ spd_ddr_init_hang();
+ }
+ if (*cols > 12) {
+ printf("ERROR: DRAM DIMM modules have %lu address columns.\n",
+ *cols);
+ printf("Only modules with 12 or fewer columns are "
+ "supported.\n\n");
+ spd_ddr_init_hang();
+ }
+ if (32 != *width && 40 != *width && 64 != *width && 72 != *width) {
+ printf("ERROR: DRAM DIMM modules have a width of %lu bit.\n",
+ *width);
+ printf("Only modules with widths of 32, 40, 64, and 72 bits "
+ "are supported.\n\n");
+ spd_ddr_init_hang();
+ }
+}
+
+/*------------------------------------------------------------------
+ * Only 1.8V modules are supported. This routine verifies this.
+ *-----------------------------------------------------------------*/
+static void check_voltage_type(unsigned long dimm_ranks[],
+ unsigned char const iic0_dimm_addr[],
+ unsigned long num_dimm_banks)
+{
+ unsigned long dimm_num;
+ unsigned long voltage_type;
+
+ for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
+ if (dimm_ranks[dimm_num]) {
+ voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
+ if (0x05 != voltage_type) { /* 1.8V for DDR2 */
+ printf("ERROR: Slot %lu provides 1.8V for DDR2 "
+ "DIMMs.\n", dimm_num);
+ switch (voltage_type) {
+ case 0x00:
+ printf("This DIMM is 5.0 Volt/TTL.\n");
+ break;
+ case 0x01:
+ printf("This DIMM is LVTTL.\n");
+ break;
+ case 0x02:
+ printf("This DIMM is 1.5 Volt.\n");
+ break;
+ case 0x03:
+ printf("This DIMM is 3.3 Volt/TTL.\n");
+ break;
+ case 0x04:
+ printf("This DIMM is 2.5 Volt.\n");
+ break;
+ default:
+ printf("This DIMM is an unknown "
+ "voltage.\n");
+ break;
+ }
+ printf("Replace it with a 1.8V DDR2 DIMM.\n\n");
+ spd_ddr_init_hang();
+ }
+ }
+ }
+}
+
+static void program_ddr0_03(unsigned long dimm_ranks[],
+ unsigned char const iic0_dimm_addr[],
+ unsigned long num_dimm_banks,
+ unsigned long sdram_freq,
+ unsigned long rows, unsigned long *cas_latency)
+{
+ unsigned long dimm_num;
+ unsigned long cas_index;
+ unsigned long cycle_2_0_clk;
+ unsigned long cycle_3_0_clk;
+ unsigned long cycle_4_0_clk;
+ unsigned long cycle_5_0_clk;
+ unsigned long max_2_0_tcyc_ps = 100;
+ unsigned long max_3_0_tcyc_ps = 100;
+ unsigned long max_4_0_tcyc_ps = 100;
+ unsigned long max_5_0_tcyc_ps = 100;
+ unsigned char cas_available = 0x3C; /* value for DDR2 */
+ u32 ddr0_03 = DDR0_03_BSTLEN_ENCODE(0x2) | DDR0_03_INITAREF_ENCODE(0x2);
+ unsigned int const tcyc_addr[3] = { 9, 23, 25 };
+
+ /*------------------------------------------------------------------
+ * Get the board configuration info.
+ *-----------------------------------------------------------------*/
+ debug("sdram_freq = %d\n", sdram_freq);
+
+ /*------------------------------------------------------------------
+ * Handle the timing. We need to find the worst case timing of all
+ * the dimm modules installed.
+ *-----------------------------------------------------------------*/
+ /* loop through all the DIMM slots on the board */
+ for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
+ /* If a dimm is installed in a particular slot ... */
+ if (dimm_ranks[dimm_num]) {
+ unsigned char const cas_bit =
+ spd_read(iic0_dimm_addr[dimm_num], 18);
+ unsigned char cas_mask;
+
+ cas_available &= cas_bit;
+ for (cas_mask = 0x80; cas_mask; cas_mask >>= 1) {
+ if (cas_bit & cas_mask)
+ break;
+ }
+ debug("cas_bit (SPD byte 18) = %02X, cas_mask = %02X\n",
+ cas_bit, cas_mask);
+
+ for (cas_index = 0; cas_index < 3;
+ cas_mask >>= 1, cas_index++) {
+ unsigned long cycle_time_ps;
+
+ if (!(cas_available & cas_mask)) {
+ continue;
+ }
+ cycle_time_ps =
+ get_tcyc(spd_read(iic0_dimm_addr[dimm_num],
+ tcyc_addr[cas_index]));
+
+ debug("cas_index = %d: cycle_time_ps = %d\n",
+ cas_index, cycle_time_ps);
+ /*
+ * DDR2 devices use the following bitmask for CAS latency:
+ * Bit 7 6 5 4 3 2 1 0
+ * TBD 6.0 5.0 4.0 3.0 2.0 TBD TBD
+ */
+ switch (cas_mask) {
+ case 0x20:
+ max_5_0_tcyc_ps =
+ max(max_5_0_tcyc_ps, cycle_time_ps);
+ break;
+ case 0x10:
+ max_4_0_tcyc_ps =
+ max(max_4_0_tcyc_ps, cycle_time_ps);
+ break;
+ case 0x08:
+ max_3_0_tcyc_ps =
+ max(max_3_0_tcyc_ps, cycle_time_ps);
+ break;
+ case 0x04:
+ max_2_0_tcyc_ps =
+ max(max_2_0_tcyc_ps, cycle_time_ps);
+ break;
+ }
+ }
+ }
+ }
+ debug("cas_available (bit map) = 0x%02X\n", cas_available);
+
+ /*------------------------------------------------------------------
+ * Set the SDRAM mode, SDRAM_MMODE
+ *-----------------------------------------------------------------*/
+
+ /* add 10 here because of rounding problems */
+ cycle_2_0_clk = MULDIV64(ONE_BILLION, 1000, max_2_0_tcyc_ps) + 10;
+ cycle_3_0_clk = MULDIV64(ONE_BILLION, 1000, max_3_0_tcyc_ps) + 10;
+ cycle_4_0_clk = MULDIV64(ONE_BILLION, 1000, max_4_0_tcyc_ps) + 10;
+ cycle_5_0_clk = MULDIV64(ONE_BILLION, 1000, max_5_0_tcyc_ps) + 10;
+ debug("cycle_2_0_clk = %d\n", cycle_2_0_clk);
+ debug("cycle_3_0_clk = %d\n", cycle_3_0_clk);
+ debug("cycle_4_0_clk = %d\n", cycle_4_0_clk);
+ debug("cycle_5_0_clk = %d\n", cycle_5_0_clk);
+
+ if ((cas_available & 0x04) && (sdram_freq <= cycle_2_0_clk)) {
+ *cas_latency = 2;
+ ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x2) |
+ DDR0_03_CASLAT_LIN_ENCODE(0x4);
+ } else if ((cas_available & 0x08) && (sdram_freq <= cycle_3_0_clk)) {
+ *cas_latency = 3;
+ ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x3) |
+ DDR0_03_CASLAT_LIN_ENCODE(0x6);
+ } else if ((cas_available & 0x10) && (sdram_freq <= cycle_4_0_clk)) {
+ *cas_latency = 4;
+ ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x4) |
+ DDR0_03_CASLAT_LIN_ENCODE(0x8);
+ } else if ((cas_available & 0x20) && (sdram_freq <= cycle_5_0_clk)) {
+ *cas_latency = 5;
+ ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x5) |
+ DDR0_03_CASLAT_LIN_ENCODE(0xA);
+ } else {
+ printf("ERROR: Cannot find a supported CAS latency with the "
+ "installed DIMMs.\n");
+ printf("Only DDR2 DIMMs with CAS latencies of 2.0, 3.0, 4.0, "
+ "and 5.0 are supported.\n");
+ printf("Make sure the PLB speed is within the supported range "
+ "of the DIMMs.\n");
+ printf("sdram_freq=%d cycle2=%d cycle3=%d cycle4=%d "
+ "cycle5=%d\n\n", sdram_freq, cycle_2_0_clk,
+ cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
+ spd_ddr_init_hang();
+ }
+ debug("CAS latency = %d\n", *cas_latency);
+ mtsdram(DDR0_03, ddr0_03);
+}
+
+static void program_ddr0_04(unsigned long dimm_ranks[],
+ unsigned char const iic0_dimm_addr[],
+ unsigned long num_dimm_banks,
+ unsigned long sdram_freq)
+{
+ unsigned long dimm_num;
+ unsigned long t_rc_ps = 0;
+ unsigned long t_rrd_ps = 0;
+ unsigned long t_rtp_ps = 0;
+ unsigned long t_rc_clk;
+ unsigned long t_rrd_clk;
+ unsigned long t_rtp_clk;
+
+ /*------------------------------------------------------------------
+ * Handle the timing. We need to find the worst case timing of all
+ * the dimm modules installed.
+ *-----------------------------------------------------------------*/
+ /* loop through all the DIMM slots on the board */
+ for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
+ /* If a dimm is installed in a particular slot ... */
+ if (dimm_ranks[dimm_num]) {
+ unsigned long ps;
+
+ /* tRC */
+ ps = 1000 * spd_read(iic0_dimm_addr[dimm_num], 41);
+ switch (spd_read(iic0_dimm_addr[dimm_num], 40) >> 4) {
+ case 0x1:
+ ps += 250;
+ break;
+ case 0x2:
+ ps += 333;
+ break;
+ case 0x3:
+ ps += 500;
+ break;
+ case 0x4:
+ ps += 667;
+ break;
+ case 0x5:
+ ps += 750;
+ break;
+ }
+ t_rc_ps = max(t_rc_ps, ps);
+ /* tRRD */
+ ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 28);
+ t_rrd_ps = max(t_rrd_ps, ps);
+ /* tRTP */
+ ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 38);
+ t_rtp_ps = max(t_rtp_ps, ps);
+ }
+ }
+ debug("t_rc_ps = %d\n", t_rc_ps);
+ t_rc_clk = (MULDIV64(sdram_freq, t_rc_ps, ONE_BILLION) + 999) / 1000;
+ debug("t_rrd_ps = %d\n", t_rrd_ps);
+ t_rrd_clk = (MULDIV64(sdram_freq, t_rrd_ps, ONE_BILLION) + 999) / 1000;
+ debug("t_rtp_ps = %d\n", t_rtp_ps);
+ t_rtp_clk = (MULDIV64(sdram_freq, t_rtp_ps, ONE_BILLION) + 999) / 1000;
+ mtsdram(DDR0_04, DDR0_04_TRC_ENCODE(t_rc_clk) |
+ DDR0_04_TRRD_ENCODE(t_rrd_clk) |
+ DDR0_04_TRTP_ENCODE(t_rtp_clk));
+}
+
+static void program_ddr0_05(unsigned long dimm_ranks[],
+ unsigned char const iic0_dimm_addr[],
+ unsigned long num_dimm_banks,
+ unsigned long sdram_freq)
+{
+ unsigned long dimm_num;
+ unsigned long t_rp_ps = 0;
+ unsigned long t_ras_ps = 0;
+ unsigned long t_rp_clk;
+ unsigned long t_ras_clk;
+ u32 ddr0_05 = DDR0_05_TMRD_ENCODE(0x2) | DDR0_05_TEMRS_ENCODE(0x2);
+
+ /*------------------------------------------------------------------
+ * Handle the timing. We need to find the worst case timing of all
+ * the dimm modules installed.
+ *-----------------------------------------------------------------*/
+ /* loop through all the DIMM slots on the board */
+ for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
+ /* If a dimm is installed in a particular slot ... */
+ if (dimm_ranks[dimm_num]) {
+ unsigned long ps;
+
+ /* tRP */
+ ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 27);
+ t_rp_ps = max(t_rp_ps, ps);
+ /* tRAS */
+ ps = 1000 * spd_read(iic0_dimm_addr[dimm_num], 30);
+ t_ras_ps = max(t_ras_ps, ps);
+ }
+ }
+ debug("t_rp_ps = %d\n", t_rp_ps);
+ t_rp_clk = (MULDIV64(sdram_freq, t_rp_ps, ONE_BILLION) + 999) / 1000;
+ debug("t_ras_ps = %d\n", t_ras_ps);
+ t_ras_clk = (MULDIV64(sdram_freq, t_ras_ps, ONE_BILLION) + 999) / 1000;
+ mtsdram(DDR0_05, ddr0_05 | DDR0_05_TRP_ENCODE(t_rp_clk) |
+ DDR0_05_TRAS_MIN_ENCODE(t_ras_clk));
+}
+
+static void program_ddr0_06(unsigned long dimm_ranks[],
+ unsigned char const iic0_dimm_addr[],
+ unsigned long num_dimm_banks,
+ unsigned long sdram_freq)
+{
+ unsigned long dimm_num;
+ unsigned char spd_40;
+ unsigned long t_wtr_ps = 0;
+ unsigned long t_rfc_ps = 0;
+ unsigned long t_wtr_clk;
+ unsigned long t_rfc_clk;
+ u32 ddr0_06 =
+ DDR0_06_WRITEINTERP_ENCODE(0x1) | DDR0_06_TDLL_ENCODE(200);
+
+ /*------------------------------------------------------------------
+ * Handle the timing. We need to find the worst case timing of all
+ * the dimm modules installed.
+ *-----------------------------------------------------------------*/
+ /* loop through all the DIMM slots on the board */
+ for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
+ /* If a dimm is installed in a particular slot ... */
+ if (dimm_ranks[dimm_num]) {
+ unsigned long ps;
+
+ /* tWTR */
+ ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 37);
+ t_wtr_ps = max(t_wtr_ps, ps);
+ /* tRFC */
+ ps = 1000 * spd_read(iic0_dimm_addr[dimm_num], 42);
+ spd_40 = spd_read(iic0_dimm_addr[dimm_num], 40);
+ ps += 256000 * (spd_40 & 0x01);
+ switch ((spd_40 & 0x0E) >> 1) {
+ case 0x1:
+ ps += 250;
+ break;
+ case 0x2:
+ ps += 333;
+ break;
+ case 0x3:
+ ps += 500;
+ break;
+ case 0x4:
+ ps += 667;
+ break;
+ case 0x5:
+ ps += 750;
+ break;
+ }
+ t_rfc_ps = max(t_rfc_ps, ps);
+ }
+ }
+ debug("t_wtr_ps = %d\n", t_wtr_ps);
+ t_wtr_clk = (MULDIV64(sdram_freq, t_wtr_ps, ONE_BILLION) + 999) / 1000;
+ debug("t_rfc_ps = %d\n", t_rfc_ps);
+ t_rfc_clk = (MULDIV64(sdram_freq, t_rfc_ps, ONE_BILLION) + 999) / 1000;
+ mtsdram(DDR0_06, ddr0_06 | DDR0_06_TWTR_ENCODE(t_wtr_clk) |
+ DDR0_06_TRFC_ENCODE(t_rfc_clk));
+}
+
+static void program_ddr0_10(unsigned long dimm_ranks[], unsigned long ranks)
+{
+ unsigned long csmap;
+
+ if (2 == ranks) {
+ /* Both chip selects in use */
+ csmap = 0x03;
+ } else {
+ /* One chip select in use */
+ csmap = (1 == dimm_ranks[0]) ? 0x1 : 0x2;
+ }
+ mtsdram(DDR0_10, DDR0_10_WRITE_MODEREG_ENCODE(0x0) |
+ DDR0_10_CS_MAP_ENCODE(csmap) |
+ DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(0));
+}
+
+static void program_ddr0_11(unsigned long sdram_freq)
+{
+ unsigned long const t_xsnr_ps = 200000; /* 200 ns */
+ unsigned long t_xsnr_clk;
+
+ debug("t_xsnr_ps = %d\n", t_xsnr_ps);
+ t_xsnr_clk =
+ (MULDIV64(sdram_freq, t_xsnr_ps, ONE_BILLION) + 999) / 1000;
+ mtsdram(DDR0_11, DDR0_11_SREFRESH_ENCODE(0) |
+ DDR0_11_TXSNR_ENCODE(t_xsnr_clk) | DDR0_11_TXSR_ENCODE(200));
+}
+
+static void program_ddr0_22(unsigned long dimm_ranks[],
+ unsigned char const iic0_dimm_addr[],
+ unsigned long num_dimm_banks, unsigned long width)
+{
+#if defined(CONFIG_DDR_ECC)
+ unsigned long dimm_num;
+ unsigned long ecc_available = width >= 64;
+ u32 ddr0_22 = DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(0x26) |
+ DDR0_22_DQS_OUT_SHIFT_ENCODE(DQS_OUT_SHIFT) |
+ DDR0_22_DLL_DQS_BYPASS_8_ENCODE(DLL_DQS_BYPASS);
+
+ /* loop through all the DIMM slots on the board */
+ for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
+ /* If a dimm is installed in a particular slot ... */
+ if (dimm_ranks[dimm_num]) {
+ /* Check for ECC */
+ if (0 == (spd_read(iic0_dimm_addr[dimm_num], 11) &
+ 0x02)) {
+ ecc_available = FALSE;
+ }
+ }
+ }
+ if (ecc_available) {
+ debug("ECC found on all DIMMs present\n");
+ mtsdram(DDR0_22, ddr0_22 | DDR0_22_CTRL_RAW_ENCODE(0x3));
+ } else {
+ debug("ECC not found on some or all DIMMs present\n");
+ mtsdram(DDR0_22, ddr0_22 | DDR0_22_CTRL_RAW_ENCODE(0x0));
+ }
+#else
+ mtsdram(DDR0_22, DDR0_22_CTRL_RAW_ENCODE(0x0) |
+ DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(0x26) |
+ DDR0_22_DQS_OUT_SHIFT_ENCODE(DQS_OUT_SHIFT) |
+ DDR0_22_DLL_DQS_BYPASS_8_ENCODE(DLL_DQS_BYPASS));
+#endif /* defined(CONFIG_DDR_ECC) */
+}
+
+static void program_ddr0_24(unsigned long ranks)
+{
+ u32 ddr0_24 = DDR0_24_RTT_PAD_TERMINATION_ENCODE(0x1) | /* 75 ohm */
+ DDR0_24_ODT_RD_MAP_CS1_ENCODE(0x0);
+
+ if (2 == ranks) {
+ /* Both chip selects in use */
+ ddr0_24 |= DDR0_24_ODT_WR_MAP_CS1_ENCODE(0x1) |
+ DDR0_24_ODT_WR_MAP_CS0_ENCODE(0x2);
+ } else {
+ /* One chip select in use */
+ /* One of the two fields added to ddr0_24 is a "don't care" */
+ ddr0_24 |= DDR0_24_ODT_WR_MAP_CS1_ENCODE(0x2) |
+ DDR0_24_ODT_WR_MAP_CS0_ENCODE(0x1);
+ }
+ mtsdram(DDR0_24, ddr0_24);
+}
+
+static void program_ddr0_26(unsigned long sdram_freq)
+{
+ unsigned long const t_ref_ps = 7800000; /* 7.8 us. refresh */
+ /* TODO: check definition of tRAS_MAX */
+ unsigned long const t_ras_max_ps = 9 * t_ref_ps;
+ unsigned long t_ras_max_clk;
+ unsigned long t_ref_clk;
+
+ /* Round down t_ras_max_clk and t_ref_clk */
+ debug("t_ras_max_ps = %d\n", t_ras_max_ps);
+ t_ras_max_clk = MULDIV64(sdram_freq, t_ras_max_ps, ONE_BILLION) / 1000;
+ debug("t_ref_ps = %d\n", t_ref_ps);
+ t_ref_clk = MULDIV64(sdram_freq, t_ref_ps, ONE_BILLION) / 1000;
+ mtsdram(DDR0_26, DDR0_26_TRAS_MAX_ENCODE(t_ras_max_clk) |
+ DDR0_26_TREF_ENCODE(t_ref_clk));
+}
+
+static void program_ddr0_27(unsigned long sdram_freq)
+{
+ unsigned long const t_init_ps = 200000000; /* 200 us. init */
+ unsigned long t_init_clk;
+
+ debug("t_init_ps = %d\n", t_init_ps);
+ t_init_clk =
+ (MULDIV64(sdram_freq, t_init_ps, ONE_BILLION) + 999) / 1000;
+ mtsdram(DDR0_27, DDR0_27_EMRS_DATA_ENCODE(0x0000) |
+ DDR0_27_TINIT_ENCODE(t_init_clk));
+}
+
+static void program_ddr0_43(unsigned long dimm_ranks[],
+ unsigned char const iic0_dimm_addr[],
+ unsigned long num_dimm_banks,
+ unsigned long sdram_freq,
+ unsigned long cols, unsigned long banks)
+{
+ unsigned long dimm_num;
+ unsigned long t_wr_ps = 0;
+ unsigned long t_wr_clk;
+ u32 ddr0_43 = DDR0_43_APREBIT_ENCODE(10) |
+ DDR0_43_COLUMN_SIZE_ENCODE(12 - cols) |
+ DDR0_43_EIGHT_BANK_MODE_ENCODE(8 == banks ? 1 : 0);
+
+ /*------------------------------------------------------------------
+ * Handle the timing. We need to find the worst case timing of all
+ * the dimm modules installed.
+ *-----------------------------------------------------------------*/
+ /* loop through all the DIMM slots on the board */
+ for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
+ /* If a dimm is installed in a particular slot ... */
+ if (dimm_ranks[dimm_num]) {
+ unsigned long ps;
+
+ ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 36);
+ t_wr_ps = max(t_wr_ps, ps);
+ }
+ }
+ debug("t_wr_ps = %d\n", t_wr_ps);
+ t_wr_clk = (MULDIV64(sdram_freq, t_wr_ps, ONE_BILLION) + 999) / 1000;
+ mtsdram(DDR0_43, ddr0_43 | DDR0_43_TWR_ENCODE(t_wr_clk));
+}
+
+static void program_ddr0_44(unsigned long dimm_ranks[],
+ unsigned char const iic0_dimm_addr[],
+ unsigned long num_dimm_banks,
+ unsigned long sdram_freq)
+{
+ unsigned long dimm_num;
+ unsigned long t_rcd_ps = 0;
+ unsigned long t_rcd_clk;
+
+ /*------------------------------------------------------------------
+ * Handle the timing. We need to find the worst case timing of all
+ * the dimm modules installed.
+ *-----------------------------------------------------------------*/
+ /* loop through all the DIMM slots on the board */
+ for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
+ /* If a dimm is installed in a particular slot ... */
+ if (dimm_ranks[dimm_num]) {
+ unsigned long ps;
+
+ ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 29);
+ t_rcd_ps = max(t_rcd_ps, ps);
+ }
+ }
+ debug("t_rcd_ps = %d\n", t_rcd_ps);
+ t_rcd_clk = (MULDIV64(sdram_freq, t_rcd_ps, ONE_BILLION) + 999) / 1000;
+ mtsdram(DDR0_44, DDR0_44_TRCD_ENCODE(t_rcd_clk));
+}
+
+/*-----------------------------------------------------------------------------+
+ * initdram. Initializes the 440EPx/GPx DDR SDRAM controller.
+ * Note: This routine runs from flash with a stack set up in the chip's
+ * sram space. It is important that the routine does not require .sbss, .bss or
+ * .data sections. It also cannot call routines that require these sections.
+ *-----------------------------------------------------------------------------*/
+/*-----------------------------------------------------------------------------
+ * Function: initdram
+ * Description: Configures SDRAM memory banks for DDR operation.
+ * Auto Memory Configuration option reads the DDR SDRAM EEPROMs
+ * via the IIC bus and then configures the DDR SDRAM memory
+ * banks appropriately. If Auto Memory Configuration is
+ * not used, it is assumed that no DIMM is plugged
+ *-----------------------------------------------------------------------------*/
+long int initdram(int board_type)
+{
+ unsigned char const iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
+ unsigned long dimm_ranks[MAXDIMMS];
+ unsigned long ranks;
+ unsigned long rows;
+ unsigned long banks;
+ unsigned long cols;
+ unsigned long width;
+ unsigned long const sdram_freq = get_bus_freq(0);
+ unsigned long const num_dimm_banks = sizeof(iic0_dimm_addr); /* on board dimm banks */
+ unsigned long cas_latency = 0; /* to quiet initialization warning */
+ unsigned long dram_size;
+
+ debug("\nEntering initdram()\n");
+
+ /*------------------------------------------------------------------
+ * Stop the DDR-SDRAM controller.
+ *-----------------------------------------------------------------*/
+ mtsdram(DDR0_02, DDR0_02_START_ENCODE(0));
+
+ /*
+ * Make sure I2C controller is initialized
+ * before continuing.
+ */
+ /* switch to correct I2C bus */
+ I2C_SET_BUS(CFG_SPD_BUS_NUM);
+ i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+
+ /*------------------------------------------------------------------
+ * Clear out the serial presence detect buffers.
+ * Perform IIC reads from the dimm. Fill in the spds.
+ * Check to see if the dimm slots are populated
+ *-----------------------------------------------------------------*/
+ get_spd_info(dimm_ranks, &ranks, iic0_dimm_addr, num_dimm_banks);
+
+ /*------------------------------------------------------------------
+ * Check the frequency supported for the dimms plugged.
+ *-----------------------------------------------------------------*/
+ check_frequency(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
+
+ /*------------------------------------------------------------------
+ * Check and get size information.
+ *-----------------------------------------------------------------*/
+ get_dimm_size(dimm_ranks, iic0_dimm_addr, num_dimm_banks, &rows, &banks,
+ &cols, &width);
+
+ /*------------------------------------------------------------------
+ * Check the voltage type for the dimms plugged.
+ *-----------------------------------------------------------------*/
+ check_voltage_type(dimm_ranks, iic0_dimm_addr, num_dimm_banks);
+
+ /*------------------------------------------------------------------
+ * Program registers for SDRAM controller.
+ *-----------------------------------------------------------------*/
+ mtsdram(DDR0_00, DDR0_00_DLL_INCREMENT_ENCODE(0x19) |
+ DDR0_00_DLL_START_POINT_DECODE(0x0A));
+
+ mtsdram(DDR0_01, DDR0_01_PLB0_DB_CS_LOWER_ENCODE(0x01) |
+ DDR0_01_PLB0_DB_CS_UPPER_ENCODE(0x00) |
+ DDR0_01_INT_MASK_ENCODE(0xFF));
+
+ program_ddr0_03(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq,
+ rows, &cas_latency);
+
+ program_ddr0_04(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
+
+ program_ddr0_05(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
+
+ program_ddr0_06(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
+
+ /*------------------------------------------------------------------
+ * TODO: tFAW not found in SPD. Value of 13 taken from Sequoia
+ * board SDRAM, but may be overly concervate.
+ *-----------------------------------------------------------------*/
+ mtsdram(DDR0_07, DDR0_07_NO_CMD_INIT_ENCODE(0) |
+ DDR0_07_TFAW_ENCODE(13) |
+ DDR0_07_AUTO_REFRESH_MODE_ENCODE(1) |
+ DDR0_07_AREFRESH_ENCODE(0));
+
+ mtsdram(DDR0_08, DDR0_08_WRLAT_ENCODE(cas_latency - 1) |
+ DDR0_08_TCPD_ENCODE(200) | DDR0_08_DQS_N_EN_ENCODE(0) |
+ DDR0_08_DDRII_ENCODE(1));
+
+ mtsdram(DDR0_09, DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(0x00) |
+ DDR0_09_RTT_0_ENCODE(0x1) |
+ DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(0x1D) |
+ DDR0_09_WR_DQS_SHIFT_ENCODE(DQS_OUT_SHIFT - 0x20));
+
+ program_ddr0_10(dimm_ranks, ranks);
+
+ program_ddr0_11(sdram_freq);
+
+ mtsdram(DDR0_12, DDR0_12_TCKE_ENCODE(3));
+
+ mtsdram(DDR0_14, DDR0_14_DLL_BYPASS_MODE_ENCODE(0) |
+ DDR0_14_REDUC_ENCODE(width <= 40 ? 1 : 0) |
+ DDR0_14_REG_DIMM_ENABLE_ENCODE(0));
+
+ mtsdram(DDR0_17, DDR0_17_DLL_DQS_DELAY_0_ENCODE(DLL_DQS_DELAY));
+
+ mtsdram(DDR0_18, DDR0_18_DLL_DQS_DELAY_4_ENCODE(DLL_DQS_DELAY) |
+ DDR0_18_DLL_DQS_DELAY_3_ENCODE(DLL_DQS_DELAY) |
+ DDR0_18_DLL_DQS_DELAY_2_ENCODE(DLL_DQS_DELAY) |
+ DDR0_18_DLL_DQS_DELAY_1_ENCODE(DLL_DQS_DELAY));
+
+ mtsdram(DDR0_19, DDR0_19_DLL_DQS_DELAY_8_ENCODE(DLL_DQS_DELAY) |
+ DDR0_19_DLL_DQS_DELAY_7_ENCODE(DLL_DQS_DELAY) |
+ DDR0_19_DLL_DQS_DELAY_6_ENCODE(DLL_DQS_DELAY) |
+ DDR0_19_DLL_DQS_DELAY_5_ENCODE(DLL_DQS_DELAY));
+
+ mtsdram(DDR0_20, DDR0_20_DLL_DQS_BYPASS_3_ENCODE(DLL_DQS_BYPASS) |
+ DDR0_20_DLL_DQS_BYPASS_2_ENCODE(DLL_DQS_BYPASS) |
+ DDR0_20_DLL_DQS_BYPASS_1_ENCODE(DLL_DQS_BYPASS) |
+ DDR0_20_DLL_DQS_BYPASS_0_ENCODE(DLL_DQS_BYPASS));
+
+ mtsdram(DDR0_21, DDR0_21_DLL_DQS_BYPASS_7_ENCODE(DLL_DQS_BYPASS) |
+ DDR0_21_DLL_DQS_BYPASS_6_ENCODE(DLL_DQS_BYPASS) |
+ DDR0_21_DLL_DQS_BYPASS_5_ENCODE(DLL_DQS_BYPASS) |
+ DDR0_21_DLL_DQS_BYPASS_4_ENCODE(DLL_DQS_BYPASS));
+
+ program_ddr0_22(dimm_ranks, iic0_dimm_addr, num_dimm_banks, width);
+
+ mtsdram(DDR0_23, DDR0_23_ODT_RD_MAP_CS0_ENCODE(0x0) |
+ DDR0_23_FWC_ENCODE(0));
+
+ program_ddr0_24(ranks);
+
+ program_ddr0_26(sdram_freq);
+
+ program_ddr0_27(sdram_freq);
+
+ mtsdram(DDR0_28, DDR0_28_EMRS3_DATA_ENCODE(0x0000) |
+ DDR0_28_EMRS2_DATA_ENCODE(0x0000));
+
+ mtsdram(DDR0_31, DDR0_31_XOR_CHECK_BITS_ENCODE(0x0000));
+
+ mtsdram(DDR0_42, DDR0_42_ADDR_PINS_DECODE(14 - rows) |
+ DDR0_42_CASLAT_LIN_GATE_ENCODE(2 * cas_latency));
+
+ program_ddr0_43(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq,
+ cols, banks);
+
+ program_ddr0_44(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
+
+ denali_sdram_register_dump();
+
+ dram_size = (width >= 64) ? 8 : 4;
+ dram_size *= 1 << cols;
+ dram_size *= banks;
+ dram_size *= 1 << rows;
+ dram_size *= ranks;
+ debug("dram_size = %lu\n", dram_size);
+
+ /* Start the SDRAM controler */
+ mtsdram(DDR0_02, DDR0_02_START_ENCODE(1));
+ denali_wait_for_dlllock();
+
+#if defined(CONFIG_DDR_DATA_EYE)
+ /* -----------------------------------------------------------+
+ * Perform data eye search if requested.
+ * ----------------------------------------------------------*/
+ program_tlb(0, CFG_SDRAM_BASE, dram_size, TLB_WORD2_I_ENABLE);
+ denali_core_search_data_eye();
+ denali_sdram_register_dump();
+ remove_tlb(CFG_SDRAM_BASE, dram_size);
+#endif
+
+#if defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC)
+ program_tlb(0, CFG_SDRAM_BASE, dram_size, 0);
+ sync();
+ eieio();
+ /* Zero the memory */
+ debug("Zeroing SDRAM...");
+ dcbz_area(CFG_SDRAM_BASE, dram_size);
+ dflush();
+ debug("Completed\n");
+ sync();
+ eieio();
+ remove_tlb(CFG_SDRAM_BASE, dram_size);
+
+#if defined(CONFIG_DDR_ECC)
+ /*
+ * If ECC is enabled, clear and enable interrupts
+ */
+ if (is_ecc_enabled()) {
+ u32 val;
+
+ sync();
+ eieio();
+ /* Clear error status */
+ mfsdram(DDR0_00, val);
+ mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
+ /* Set 'int_mask' parameter to functionnal value */
+ mfsdram(DDR0_01, val);
+ mtsdram(DDR0_01, (val & ~DDR0_01_INT_MASK_MASK) |
+ DDR0_01_INT_MASK_ALL_OFF);
+#if defined(CONFIG_DDR_DATA_EYE)
+ /*
+ * Running denali_core_search_data_eye() when ECC is enabled
+ * causes non-ECC machine checks. This clears them.
+ */
+ print_mcsr();
+ mtspr(SPRN_MCSR, mfspr(SPRN_MCSR));
+ print_mcsr();
+#endif
+ sync();
+ eieio();
+ }
+#endif /* defined(CONFIG_DDR_ECC) */
+#endif /* defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) */
+
+ program_tlb(0, CFG_SDRAM_BASE, dram_size, MY_TLB_WORD2_I_ENABLE);
+ return dram_size;
+}
+
+void board_add_ram_info(int use_default)
+{
+ u32 val;
+
+ printf(" (ECC");
+ if (!is_ecc_enabled()) {
+ printf(" not");
+ }
+ printf(" enabled, %d MHz", (2 * get_bus_freq(0)) / 1000000);
+
+ mfsdram(DDR0_03, val);
+ printf(", CL%d)", DDR0_03_CASLAT_LIN_DECODE(val) >> 1);
+}
+#endif /* CONFIG_SPD_EEPROM */
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <command.h>
+#include <asm/cache.h>
+#include <ppc4xx.h>
+
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#include <libfdt_env.h>
+#include <fdt_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void ft_cpu_setup(void *blob, bd_t *bd)
+{
+ sys_info_t sys_info;
+
+ get_sys_info(&sys_info);
+
+ do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "timebase-frequency",
+ bd->bi_intfreq, 1);
+ do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "clock-frequency",
+ bd->bi_intfreq, 1);
+ do_fixup_by_path_u32(blob, "/plb", "clock-frequency", sys_info.freqPLB, 1);
+ do_fixup_by_path_u32(blob, "/plb/opb", "clock-frequency", sys_info.freqOPB, 1);
+ do_fixup_by_path_u32(blob, "/plb/opb/ebc", "clock-frequency",
+ sys_info.freqEBC, 1);
+ fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
+
+ /*
+ * Setup all baudrates for the UARTs
+ */
+ do_fixup_by_compat_u32(blob, "ns16550", "clock-frequency", gd->uart_clk, 1);
+
+ /*
+ * Fixup all ethernet nodes
+ * Note: aliases in the dts are required for this
+ */
+ fdt_fixup_ethernet(blob, bd);
+}
+#endif /* CONFIG_OF_LIBFDT */
#include <asm/io.h>
#include <asm/gpio.h>
-#if defined(CFG_440_GPIO_TABLE)
-gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_440_GPIO_TABLE;
+#if defined(CFG_4xx_GPIO_TABLE)
+gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_4xx_GPIO_TABLE;
#endif
#if defined(GPIO0_OSRL)
}
if (pin >= GPIO_MAX/2) {
- offs2 = 0x100;
+ offs2 = 0x4;
pin2 = (pin - GPIO_MAX/2) << 1;
}
mask2 = 0xc0000000 >> (pin2 << 1);
/* first set TCR to 0 */
- out32(GPIO0_TCR + offs, in32(GPIO0_TCR + offs) & ~mask);
+ out_be32((void *)GPIO0_TCR + offs, in_be32((void *)GPIO0_TCR + offs) & ~mask);
if (in_out == GPIO_OUT) {
- val = in32(GPIO0_OSRL + offs + offs2) & ~mask2;
+ val = in_be32((void *)GPIO0_OSRL + offs + offs2) & ~mask2;
switch (gpio_alt) {
case GPIO_ALT1:
val |= GPIO_ALT1_SEL >> pin2;
val |= GPIO_ALT3_SEL >> pin2;
break;
}
- out32(GPIO0_OSRL + offs + offs2, val);
+ out_be32((void *)GPIO0_OSRL + offs + offs2, val);
/* setup requested output value */
if (out_val == GPIO_OUT_0)
- out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) & ~mask);
+ out_be32((void *)GPIO0_OR + offs,
+ in_be32((void *)GPIO0_OR + offs) & ~mask);
else if (out_val == GPIO_OUT_1)
- out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) | mask);
+ out_be32((void *)GPIO0_OR + offs,
+ in_be32((void *)GPIO0_OR + offs) | mask);
/* now configure TCR to drive output if selected */
- out32(GPIO0_TCR + offs, in32(GPIO0_TCR + offs) | mask);
+ out_be32((void *)GPIO0_TCR + offs,
+ in_be32((void *)GPIO0_TCR + offs) | mask);
} else {
- val = in32(GPIO0_ISR1L + offs + offs2) & ~mask2;
+ val = in_be32((void *)GPIO0_ISR1L + offs + offs2) & ~mask2;
val |= GPIO_IN_SEL >> pin2;
- out32(GPIO0_ISR1L + offs + offs2, val);
+ out_be32((void *)GPIO0_ISR1L + offs + offs2, val);
}
}
#endif /* GPIO_OSRL */
}
if (val)
- out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) | GPIO_VAL(pin));
+ out_be32((void *)GPIO0_OR + offs,
+ in_be32((void *)GPIO0_OR + offs) | GPIO_VAL(pin));
else
- out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) & ~GPIO_VAL(pin));
+ out_be32((void *)GPIO0_OR + offs,
+ in_be32((void *)GPIO0_OR + offs) & ~GPIO_VAL(pin));
}
int gpio_read_out_bit(int pin)
pin -= GPIO_MAX;
}
- return (in32(GPIO0_OR + offs) & GPIO_VAL(pin) ? 1 : 0);
+ return (in_be32((void *)GPIO0_OR + offs) & GPIO_VAL(pin) ? 1 : 0);
}
-#if defined(CFG_440_GPIO_TABLE)
+#if defined(CFG_4xx_GPIO_TABLE)
void gpio_set_chip_configuration(void)
{
unsigned char i=0, j=0, offs=0, gpio_core;
break;
case GPIO_ALT1:
- reg = in32(GPIO_IS1(core_add+offs))
+ reg = in_be32((void *)GPIO_IS1(core_add+offs))
& ~(GPIO_MASK >> (j*2));
reg = reg | (GPIO_IN_SEL >> (j*2));
- out32(GPIO_IS1(core_add+offs), reg);
+ out_be32((void *)GPIO_IS1(core_add+offs), reg);
break;
case GPIO_ALT2:
- reg = in32(GPIO_IS2(core_add+offs))
+ reg = in_be32((void *)GPIO_IS2(core_add+offs))
& ~(GPIO_MASK >> (j*2));
reg = reg | (GPIO_IN_SEL >> (j*2));
- out32(GPIO_IS2(core_add+offs), reg);
+ out_be32((void *)GPIO_IS2(core_add+offs), reg);
break;
case GPIO_ALT3:
- reg = in32(GPIO_IS3(core_add+offs))
+ reg = in_be32((void *)GPIO_IS3(core_add+offs))
& ~(GPIO_MASK >> (j*2));
reg = reg | (GPIO_IN_SEL >> (j*2));
- out32(GPIO_IS3(core_add+offs), reg);
+ out_be32((void *)GPIO_IS3(core_add+offs), reg);
break;
}
}
switch (gpio_tab[gpio_core][i].alt_nb) {
case GPIO_SEL:
- if (gpio_core == GPIO0) {
- /*
- * Setup output value
- * 1 -> high level
- * 0 -> low level
- * else -> don't touch
- */
- reg = in32(GPIO0_OR);
- if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1)
- reg |= (0x80000000 >> (i));
- else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0)
- reg &= ~(0x80000000 >> (i));
- out32(GPIO0_OR, reg);
-
- reg = in32(GPIO0_TCR) | (0x80000000 >> (i));
- out32(GPIO0_TCR, reg);
- }
-
-#ifdef GPIO1
- if (gpio_core == GPIO1) {
- /*
- * Setup output value
- * 1 -> high level
- * 0 -> low level
- * else -> don't touch
- */
- reg = in32(GPIO1_OR);
- if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1)
- reg |= (0x80000000 >> (i));
- else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0)
- reg &= ~(0x80000000 >> (i));
- out32(GPIO1_OR, reg);
-
- reg = in32(GPIO1_TCR) | (0x80000000 >> (i));
- out32(GPIO1_TCR, reg);
- }
-#endif /* GPIO1 */
-
- reg = in32(GPIO_OS(core_add+offs))
+ /*
+ * Setup output value
+ * 1 -> high level
+ * 0 -> low level
+ * else -> don't touch
+ */
+ reg = in_be32((void *)GPIO_OR(core_add));
+ if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1)
+ reg |= (0x80000000 >> (i));
+ else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0)
+ reg &= ~(0x80000000 >> (i));
+ out_be32((void *)GPIO_OR(core_add), reg);
+
+ reg = in_be32((void *)GPIO_TCR(core_add)) |
+ (0x80000000 >> (i));
+ out_be32((void *)GPIO_TCR(core_add), reg);
+
+ reg = in_be32((void *)GPIO_OS(core_add+offs))
& ~(GPIO_MASK >> (j*2));
- out32(GPIO_OS(core_add+offs), reg);
- reg = in32(GPIO_TS(core_add+offs))
+ out_be32((void *)GPIO_OS(core_add+offs), reg);
+ reg = in_be32((void *)GPIO_TS(core_add+offs))
& ~(GPIO_MASK >> (j*2));
- out32(GPIO_TS(core_add+offs), reg);
+ out_be32((void *)GPIO_TS(core_add+offs), reg);
break;
case GPIO_ALT1:
- reg = in32(GPIO_OS(core_add+offs))
+ reg = in_be32((void *)GPIO_OS(core_add+offs))
& ~(GPIO_MASK >> (j*2));
reg = reg | (GPIO_ALT1_SEL >> (j*2));
- out32(GPIO_OS(core_add+offs), reg);
- reg = in32(GPIO_TS(core_add+offs))
+ out_be32((void *)GPIO_OS(core_add+offs), reg);
+ reg = in_be32((void *)GPIO_TS(core_add+offs))
& ~(GPIO_MASK >> (j*2));
reg = reg | (GPIO_ALT1_SEL >> (j*2));
- out32(GPIO_TS(core_add+offs), reg);
+ out_be32((void *)GPIO_TS(core_add+offs), reg);
break;
case GPIO_ALT2:
- reg = in32(GPIO_OS(core_add+offs))
+ reg = in_be32((void *)GPIO_OS(core_add+offs))
& ~(GPIO_MASK >> (j*2));
reg = reg | (GPIO_ALT2_SEL >> (j*2));
- out32(GPIO_OS(core_add+offs), reg);
- reg = in32(GPIO_TS(core_add+offs))
+ out_be32((void *)GPIO_OS(core_add+offs), reg);
+ reg = in_be32((void *)GPIO_TS(core_add+offs))
& ~(GPIO_MASK >> (j*2));
reg = reg | (GPIO_ALT2_SEL >> (j*2));
- out32(GPIO_TS(core_add+offs), reg);
+ out_be32((void *)GPIO_TS(core_add+offs), reg);
break;
case GPIO_ALT3:
- reg = in32(GPIO_OS(core_add+offs))
+ reg = in_be32((void *)GPIO_OS(core_add+offs))
& ~(GPIO_MASK >> (j*2));
reg = reg | (GPIO_ALT3_SEL >> (j*2));
- out32(GPIO_OS(core_add+offs), reg);
- reg = in32(GPIO_TS(core_add+offs))
+ out_be32((void *)GPIO_OS(core_add+offs), reg);
+ reg = in_be32((void *)GPIO_TS(core_add+offs))
& ~(GPIO_MASK >> (j*2));
reg = reg | (GPIO_ALT3_SEL >> (j*2));
- out32(GPIO_TS(core_add+offs), reg);
+ out_be32((void *)GPIO_TS(core_add+offs), reg);
break;
}
}
}
}
}
-#endif /* CFG_440_GPIO_TABLE */
+#endif /* CFG_4xx_GPIO_TABLE */
static struct irq_action irq_vecs[32];
void uic0_interrupt( void * parms); /* UIC0 handler */
-#if defined(CONFIG_440)
+#if defined(CONFIG_440) || defined(CONFIG_405EX)
static struct irq_action irq_vecs1[32]; /* For UIC1 */
void uic1_interrupt( void * parms); /* UIC1 handler */
irq_vecs[vec].handler = NULL;
irq_vecs[vec].arg = NULL;
irq_vecs[vec].count = 0;
-#if defined(CONFIG_440)
+#if defined(CONFIG_440) || defined(CONFIG_405EX)
irq_vecs1[vec].handler = NULL;
irq_vecs1[vec].arg = NULL;
irq_vecs1[vec].count = 0;
*/
set_evpr(0x00000000);
-#if defined(CONFIG_440)
+#if defined(CONFIG_440) || defined(CONFIG_405EX)
#if !defined(CONFIG_440GX)
/* Install the UIC1 handlers */
irq_install_handler(VECNUM_UIC1NC, uic1_interrupt, 0);
#endif /* CONFIG_440GX */
-#if defined(CONFIG_440)
+#if defined(CONFIG_440) || defined(CONFIG_405EX)
/* Handler for UIC1 interrupt */
void uic1_interrupt( void * parms)
{
struct irq_action *irqa = irq_vecs;
int i = vec;
-#if defined(CONFIG_440)
+#if defined(CONFIG_440) || defined(CONFIG_405EX)
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
if ((vec > 31) && (vec < 64)) {
irqa[i].handler = handler;
irqa[i].arg = arg;
-#if defined(CONFIG_440)
+#if defined(CONFIG_440) || defined(CONFIG_405EX)
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
if ((vec > 31) && (vec < 64))
struct irq_action *irqa = irq_vecs;
int i = vec;
-#if defined(CONFIG_440)
+#if defined(CONFIG_440) || defined(CONFIG_405EX)
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
if ((vec > 31) && (vec < 64)) {
vec, irq_vecs[vec].handler);
#endif
-#if defined(CONFIG_440)
+#if defined(CONFIG_440) || defined(CONFIG_405EX)
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
if ((vec > 31) && (vec < 64))
int vec;
printf ("\nInterrupt-Information:\n");
-#if defined(CONFIG_440)
+#if defined(CONFIG_440) || defined(CONFIG_405EX)
printf ("\nUIC 0\n");
#endif
printf ("Nr Routine Arg Count\n");
}
}
-#if defined(CONFIG_440)
+#if defined(CONFIG_440) || defined(CONFIG_405EX)
printf ("\nUIC 1\n");
printf ("Nr Routine Arg Count\n");
--- /dev/null
+/*
+ * (C) Copyright 2000-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <commproc.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <watchdog.h>
+#include "vecnum.h"
+
+#ifdef CONFIG_SERIAL_MULTI
+#include <serial.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_IOP480
+
+#define SPU_BASE 0x40000000
+
+#define spu_LineStat_rc 0x00 /* Line Status Register (Read/Clear) */
+#define spu_LineStat_w 0x04 /* Line Status Register (Set) */
+#define spu_Handshk_rc 0x08 /* Handshake Status Register (Read/Clear) */
+#define spu_Handshk_w 0x0c /* Handshake Status Register (Set) */
+#define spu_BRateDivh 0x10 /* Baud rate divisor high */
+#define spu_BRateDivl 0x14 /* Baud rate divisor low */
+#define spu_CtlReg 0x18 /* Control Register */
+#define spu_RxCmd 0x1c /* Rx Command Register */
+#define spu_TxCmd 0x20 /* Tx Command Register */
+#define spu_RxBuff 0x24 /* Rx data buffer */
+#define spu_TxBuff 0x24 /* Tx data buffer */
+
+/*-----------------------------------------------------------------------------+
+ | Line Status Register.
+ +-----------------------------------------------------------------------------*/
+#define asyncLSRport1 0x40000000
+#define asyncLSRport1set 0x40000004
+#define asyncLSRDataReady 0x80
+#define asyncLSRFramingError 0x40
+#define asyncLSROverrunError 0x20
+#define asyncLSRParityError 0x10
+#define asyncLSRBreakInterrupt 0x08
+#define asyncLSRTxHoldEmpty 0x04
+#define asyncLSRTxShiftEmpty 0x02
+
+/*-----------------------------------------------------------------------------+
+ | Handshake Status Register.
+ +-----------------------------------------------------------------------------*/
+#define asyncHSRport1 0x40000008
+#define asyncHSRport1set 0x4000000c
+#define asyncHSRDsr 0x80
+#define asyncLSRCts 0x40
+
+/*-----------------------------------------------------------------------------+
+ | Control Register.
+ +-----------------------------------------------------------------------------*/
+#define asyncCRport1 0x40000018
+#define asyncCRNormal 0x00
+#define asyncCRLoopback 0x40
+#define asyncCRAutoEcho 0x80
+#define asyncCRDtr 0x20
+#define asyncCRRts 0x10
+#define asyncCRWordLength7 0x00
+#define asyncCRWordLength8 0x08
+#define asyncCRParityDisable 0x00
+#define asyncCRParityEnable 0x04
+#define asyncCREvenParity 0x00
+#define asyncCROddParity 0x02
+#define asyncCRStopBitsOne 0x00
+#define asyncCRStopBitsTwo 0x01
+#define asyncCRDisableDtrRts 0x00
+
+/*-----------------------------------------------------------------------------+
+ | Receiver Command Register.
+ +-----------------------------------------------------------------------------*/
+#define asyncRCRport1 0x4000001c
+#define asyncRCRDisable 0x00
+#define asyncRCREnable 0x80
+#define asyncRCRIntDisable 0x00
+#define asyncRCRIntEnabled 0x20
+#define asyncRCRDMACh2 0x40
+#define asyncRCRDMACh3 0x60
+#define asyncRCRErrorInt 0x10
+#define asyncRCRPauseEnable 0x08
+
+/*-----------------------------------------------------------------------------+
+ | Transmitter Command Register.
+ +-----------------------------------------------------------------------------*/
+#define asyncTCRport1 0x40000020
+#define asyncTCRDisable 0x00
+#define asyncTCREnable 0x80
+#define asyncTCRIntDisable 0x00
+#define asyncTCRIntEnabled 0x20
+#define asyncTCRDMACh2 0x40
+#define asyncTCRDMACh3 0x60
+#define asyncTCRTxEmpty 0x10
+#define asyncTCRErrorInt 0x08
+#define asyncTCRStopPause 0x04
+#define asyncTCRBreakGen 0x02
+
+/*-----------------------------------------------------------------------------+
+ | Miscellanies defines.
+ +-----------------------------------------------------------------------------*/
+#define asyncTxBufferport1 0x40000024
+#define asyncRxBufferport1 0x40000024
+#define asyncDLABLsbport1 0x40000014
+#define asyncDLABMsbport1 0x40000010
+#define asyncXOFFchar 0x13
+#define asyncXONchar 0x11
+
+/*
+ * Minimal serial functions needed to use one of the SMC ports
+ * as serial console interface.
+ */
+
+int serial_init (void)
+{
+ volatile char val;
+ unsigned short br_reg;
+
+ br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
+
+ /*
+ * Init onboard UART
+ */
+ out_8((u8 *)SPU_BASE + spu_LineStat_rc, 0x78); /* Clear all bits in Line Status Reg */
+ out_8((u8 *)SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
+ out_8((u8 *)SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
+ out_8((u8 *)SPU_BASE + spu_CtlReg, 0x08); /* Set 8 bits, no parity and 1 stop bit */
+ out_8((u8 *)SPU_BASE + spu_RxCmd, 0xb0); /* Enable Rx */
+ out_8((u8 *)SPU_BASE + spu_TxCmd, 0x9c); /* Enable Tx */
+ out_8((u8 *)SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
+ val = in_8((u8 *)SPU_BASE + spu_RxBuff); /* Dummy read, to clear receiver */
+
+ return (0);
+}
+
+void serial_setbrg (void)
+{
+ unsigned short br_reg;
+
+ br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
+
+ out_8((u8 *)SPU_BASE + spu_BRateDivl,
+ (br_reg & 0x00ff)); /* Set baud rate divisor... */
+ out_8((u8 *)SPU_BASE + spu_BRateDivh,
+ ((br_reg & 0xff00) >> 8)); /* ... */
+}
+
+void serial_putc (const char c)
+{
+ if (c == '\n')
+ serial_putc ('\r');
+
+ /* load status from handshake register */
+ if (in_8((u8 *)SPU_BASE + spu_Handshk_rc) != 00)
+ out_8((u8 *)SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
+
+ out_8((u8 *)SPU_BASE + spu_TxBuff, c); /* Put char */
+
+ while ((in_8((u8 *)SPU_BASE + spu_LineStat_rc) & 04) != 04) {
+ if (in_8((u8 *)SPU_BASE + spu_Handshk_rc) != 00)
+ out_8((u8 *)SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
+ }
+}
+
+void serial_puts (const char *s)
+{
+ while (*s) {
+ serial_putc (*s++);
+ }
+}
+
+int serial_getc ()
+{
+ unsigned char status = 0;
+
+ while (1) {
+ status = in_8((u8 *)asyncLSRport1);
+ if ((status & asyncLSRDataReady) != 0x0) {
+ break;
+ }
+ if ((status & ( asyncLSRFramingError |
+ asyncLSROverrunError |
+ asyncLSRParityError |
+ asyncLSRBreakInterrupt )) != 0) {
+ (void) out_8((u8 *)asyncLSRport1,
+ asyncLSRFramingError |
+ asyncLSROverrunError |
+ asyncLSRParityError |
+ asyncLSRBreakInterrupt );
+ }
+ }
+ return (0x000000ff & (int) in_8((u8 *)asyncRxBufferport1));
+}
+
+int serial_tstc ()
+{
+ unsigned char status;
+
+ status = in_8((u8 *)asyncLSRport1);
+ if ((status & asyncLSRDataReady) != 0x0) {
+ return (1);
+ }
+ if ((status & ( asyncLSRFramingError |
+ asyncLSROverrunError |
+ asyncLSRParityError |
+ asyncLSRBreakInterrupt )) != 0) {
+ (void) out_8((u8 *)asyncLSRport1,
+ asyncLSRFramingError |
+ asyncLSROverrunError |
+ asyncLSRParityError |
+ asyncLSRBreakInterrupt);
+ }
+ return 0;
+}
+
+#endif /* CONFIG_IOP480 */
.globl kgdb_flush_cache_range
kgdb_flush_cache_range:
- li r5,CFG_CACHELINE_SIZE-1
+ li r5,L1_CACHE_BYTES-1
andc r3,r3,r5
subf r4,r3,r4
add r4,r4,r5
- srwi. r4,r4,CFG_CACHELINE_SHIFT
+ srwi. r4,r4,L1_CACHE_SHIFT
beqlr
mtctr r4
mr r6,r3
1: dcbst 0,r3
- addi r3,r3,CFG_CACHELINE_SIZE
+ addi r3,r3,L1_CACHE_BYTES
bdnz 1b
sync /* wait for dcbst's to get to ram */
mtctr r4
2: icbi 0,r6
- addi r6,r6,CFG_CACHELINE_SIZE
+ addi r6,r6,L1_CACHE_BYTES
bdnz 2b
SYNC
blr
|
| Author: Mark Wisner
|
- | Change Activity-
- |
- | Date Description of Change BY
- | --------- --------------------- ---
- | 05-May-99 Created MKW
- | 01-Jul-99 Changed clock setting of sta_reg from 66Mhz to 50Mhz to
- | better match OPB speed. Also modified delay times. JWB
- | 29-Jul-99 Added Full duplex support MKW
- | 24-Aug-99 Removed printf from dp83843_duplex() JWB
- | 19-Jul-00 Ported to esd cpci405 sr
- | 23-Dec-03 Ported from miiphy.c to 440GX Travis Sawyer TBS
- | <travis.sawyer@sandburst.com>
- |
+-----------------------------------------------------------------------------*/
#include <common.h>
#include <asm/processor.h>
+#include <asm/io.h>
#include <ppc_asm.tmpl>
#include <commproc.h>
#include <ppc4xx_enet.h>
unsigned long i;
unsigned short data;
-
for (i = 0; i < 0x1A; i++) {
if (miiphy_read (devname, addr, i, &data)) {
printf ("read error for reg %lx\n", i);
} /* end for loop */
} /* end dump */
-
/***********************************************************/
/* (Re)start autonegotiation */
/***********************************************************/
int phy_setup_aneg (char *devname, unsigned char addr)
{
- unsigned short ctl, adv;
+ u16 bmcr;
+
+#if defined(CONFIG_PHY_DYNAMIC_ANEG)
+ /*
+ * Set up advertisement based on capablilities reported by the PHY.
+ * This should work for both copper and fiber.
+ */
+ u16 bmsr;
+#if defined(CONFIG_PHY_GIGE)
+ u16 exsr = 0x0000;
+#endif
+
+ miiphy_read (devname, addr, PHY_BMSR, &bmsr);
+
+#if defined(CONFIG_PHY_GIGE)
+ if (bmsr & PHY_BMSR_EXT_STAT)
+ miiphy_read (devname, addr, PHY_EXSR, &exsr);
+
+ if (exsr & (PHY_EXSR_1000XF | PHY_EXSR_1000XH)) {
+ /* 1000BASE-X */
+ u16 anar = 0x0000;
+
+ if (exsr & PHY_EXSR_1000XF)
+ anar |= PHY_X_ANLPAR_FD;
+
+ if (exsr & PHY_EXSR_1000XH)
+ anar |= PHY_X_ANLPAR_HD;
+
+ miiphy_write (devname, addr, PHY_ANAR, anar);
+ } else
+#endif
+ {
+ u16 anar, btcr;
+
+ miiphy_read (devname, addr, PHY_ANAR, &anar);
+ anar &= ~(0x5000 | PHY_ANLPAR_T4 | PHY_ANLPAR_TXFD |
+ PHY_ANLPAR_TX | PHY_ANLPAR_10FD | PHY_ANLPAR_10);
+
+ miiphy_read (devname, addr, PHY_1000BTCR, &btcr);
+ btcr &= ~(0x00FF | PHY_1000BTCR_1000FD | PHY_1000BTCR_1000HD);
+
+ if (bmsr & PHY_BMSR_100T4)
+ anar |= PHY_ANLPAR_T4;
+
+ if (bmsr & PHY_BMSR_100TXF)
+ anar |= PHY_ANLPAR_TXFD;
+
+ if (bmsr & PHY_BMSR_100TXH)
+ anar |= PHY_ANLPAR_TX;
+
+ if (bmsr & PHY_BMSR_10TF)
+ anar |= PHY_ANLPAR_10FD;
+
+ if (bmsr & PHY_BMSR_10TH)
+ anar |= PHY_ANLPAR_10;
+
+ miiphy_write (devname, addr, PHY_ANAR, anar);
+
+#if defined(CONFIG_PHY_GIGE)
+ if (exsr & PHY_EXSR_1000TF)
+ btcr |= PHY_1000BTCR_1000FD;
+
+ if (exsr & PHY_EXSR_1000TH)
+ btcr |= PHY_1000BTCR_1000HD;
+
+ miiphy_write (devname, addr, PHY_1000BTCR, btcr);
+#endif
+ }
+
+#else /* defined(CONFIG_PHY_DYNAMIC_ANEG) */
+ /*
+ * Set up standard advertisement
+ */
+ u16 adv;
- /* Setup standard advertise */
miiphy_read (devname, addr, PHY_ANAR, &adv);
adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 |
PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD |
adv |= (0x0300);
miiphy_write (devname, addr, PHY_1000BTCR, adv);
+#endif /* defined(CONFIG_PHY_DYNAMIC_ANEG) */
+
/* Start/Restart aneg */
- miiphy_read (devname, addr, PHY_BMCR, &ctl);
- ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
- miiphy_write (devname, addr, PHY_BMCR, ctl);
+ miiphy_read (devname, addr, PHY_BMCR, &bmcr);
+ bmcr |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+ miiphy_write (devname, addr, PHY_BMCR, bmcr);
return 0;
}
-
/***********************************************************/
/* read a phy reg and return the value with a rc */
/***********************************************************/
unsigned long eoffset;
/* Need to find out which mdi port we're using */
- zmii = in32 (ZMII_FER);
+ zmii = in_be32((void *)ZMII_FER);
- if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0))) {
+ if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0)))
/* using port 0 */
eoffset = 0;
- } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (1))) {
+
+ else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (1)))
/* using port 1 */
eoffset = 0x100;
- } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (2))) {
+
+ else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (2)))
/* using port 2 */
eoffset = 0x400;
- } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (3))) {
+
+ else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (3)))
/* using port 3 */
eoffset = 0x600;
- } else {
+
+ else {
/* None of the mdi ports are enabled! */
/* enable port 0 */
zmii |= ZMII_FER_MDI << ZMII_FER_V (0);
- out32 (ZMII_FER, zmii);
+ out_be32((void *)ZMII_FER, zmii);
eoffset = 0;
/* need to soft reset port 0 */
- zmii = in32 (EMAC_M0);
+ zmii = in_be32((void *)EMAC_M0);
zmii |= EMAC_M0_SRST;
- out32 (EMAC_M0, zmii);
+ out_be32((void *)EMAC_M0, zmii);
}
return (eoffset);
#else
+
+#if defined(CONFIG_NET_MULTI) && defined(CONFIG_405EX)
+ unsigned long rgmii;
+ int devnum = 1;
+
+ rgmii = in_be32((void *)RGMII_FER);
+ if (rgmii & (1 << (19 - devnum)))
+ return 0x100;
+#endif
+
return 0;
#endif
}
-
-int emac4xx_miiphy_read (char *devname, unsigned char addr,
- unsigned char reg, unsigned short *value)
+int emac4xx_miiphy_read (char *devname, unsigned char addr, unsigned char reg,
+ unsigned short *value)
{
unsigned long sta_reg; /* STA scratch area */
unsigned long i;
unsigned long emac_reg;
-
emac_reg = miiphy_getemac_offset ();
/* see if it is ready for 1000 nsec */
i = 0;
/* see if it is ready for sec */
- while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) {
+ while ((in_be32((void *)EMAC_STACR + emac_reg) & EMAC_STACR_OC) ==
+ EMAC_STACR_OC_MASK) {
udelay (7);
if (i > 5) {
#ifdef ET_DEBUG
- sta_reg = in32 (EMAC_STACR + emac_reg);
+ sta_reg = in_be32((void *)EMAC_STACR + emac_reg);
printf ("read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
printf ("read err 1\n");
#endif
sta_reg = reg; /* reg address */
/* set clock (50Mhz) and read flags */
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-#if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */
- sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_READ;
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_405EX)
+#if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */
+ sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_READ;
#else
- sta_reg |= EMAC_STACR_READ;
+ sta_reg |= EMAC_STACR_READ;
#endif
#else
sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ;
#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && \
!defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
- !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
+ !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
+ !defined(CONFIG_405EX)
sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
#endif
sta_reg = sta_reg | (addr << 5); /* Phy address */
sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */
- out32 (EMAC_STACR + emac_reg, sta_reg);
+ out_be32((void *)EMAC_STACR + emac_reg, sta_reg);
#ifdef ET_DEBUG
printf ("a2: write: EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
#endif
- sta_reg = in32 (EMAC_STACR + emac_reg);
+ sta_reg = in_be32((void *)EMAC_STACR + emac_reg);
#ifdef ET_DEBUG
- printf ("a21: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
+ printf ("a21: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
#endif
i = 0;
while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) {
udelay (7);
- if (i > 5) {
+ if (i > 5)
return -1;
- }
+
i++;
- sta_reg = in32 (EMAC_STACR + emac_reg);
+ sta_reg = in_be32((void *)EMAC_STACR + emac_reg);
#ifdef ET_DEBUG
printf ("a22: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
#endif
}
- if ((sta_reg & EMAC_STACR_PHYE) != 0) {
+ if ((sta_reg & EMAC_STACR_PHYE) != 0)
return -1;
- }
- *value = *(short *) (&sta_reg);
+ *value = *(short *)(&sta_reg);
return 0;
-
} /* phy_read */
-
/***********************************************************/
/* write a phy reg and return the value with a rc */
/***********************************************************/
-int emac4xx_miiphy_write (char *devname, unsigned char addr,
- unsigned char reg, unsigned short value)
+int emac4xx_miiphy_write (char *devname, unsigned char addr, unsigned char reg,
+ unsigned short value)
{
unsigned long sta_reg; /* STA scratch area */
unsigned long i;
/* see if it is ready for 1000 nsec */
i = 0;
- while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) {
+ while ((in_be32((void *)EMAC_STACR + emac_reg) & EMAC_STACR_OC) ==
+ EMAC_STACR_OC_MASK) {
if (i > 5)
return -1;
+
udelay (7);
i++;
}
sta_reg = reg; /* reg address */
/* set clock (50Mhz) and read flags */
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-#if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */
- sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_WRITE;
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_405EX)
+#if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */
+ sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_WRITE;
#else
- sta_reg |= EMAC_STACR_WRITE;
+ sta_reg |= EMAC_STACR_WRITE;
#endif
#else
sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ;
#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && \
!defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
- !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
+ !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
+ !defined(CONFIG_405EX)
sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */
#endif
- sta_reg = sta_reg | ((unsigned long) addr << 5);/* Phy address */
- sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */
+ sta_reg = sta_reg | ((unsigned long)addr << 5); /* Phy address */
+ sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */
memcpy (&sta_reg, &value, 2); /* put in data */
- out32 (EMAC_STACR + emac_reg, sta_reg);
+ out_be32((void *)EMAC_STACR + emac_reg, sta_reg);
/* wait for completion */
i = 0;
- sta_reg = in32 (EMAC_STACR + emac_reg);
+ sta_reg = in_be32((void *)EMAC_STACR + emac_reg);
#ifdef ET_DEBUG
- printf ("a31: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
+ printf ("a31: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
#endif
while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) {
udelay (7);
if (i > 5)
return -1;
+
i++;
- sta_reg = in32 (EMAC_STACR + emac_reg);
+ sta_reg = in_be32((void *)EMAC_STACR + emac_reg);
#ifdef ET_DEBUG
printf ("a32: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
#endif
if ((sta_reg & EMAC_STACR_PHYE) != 0)
return -1;
+
return 0;
-} /* phy_write */
+} /* phy_write */
#if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY) && \
(defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_405EZ))
+ defined(CONFIG_405EZ) || defined(CONFIG_405EX))
#include <nand.h>
#include <linux/mtd/ndfc.h>
*/
board_nand_select_device(nand, cs);
out_be32((u32 *)(base + NDFC_BCFG0 + (cs << 2)), 0x80002222);
+
return 0;
}
+++ /dev/null
-/*
- * (C) Copyright 2000-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-/*------------------------------------------------------------------------------+ */
-/*
- * This source code has been made available to you by IBM on an AS-IS
- * basis. Anyone receiving this source is licensed under IBM
- * copyrights to use it in any way he or she deems fit, including
- * copying it, modifying it, compiling it, and redistributing it either
- * with or without modifications. No license under IBM patents or
- * patent applications is to be implied by the copyright license.
- *
- * Any user of this software should understand that IBM cannot provide
- * technical support for this software and will not be responsible for
- * any consequences resulting from the use of this software.
- *
- * Any person who transfers this source code or any derivative work
- * must include the IBM copyright notice, this paragraph, and the
- * preceding two paragraphs in the transferred software.
- *
- * COPYRIGHT I B M CORPORATION 1995
- * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
- */
-/*------------------------------------------------------------------------------- */
-/*
- * Travis Sawyer 15 September 2004
- * Added CONFIG_SERIAL_MULTI support
- */
-#include <common.h>
-#include <commproc.h>
-#include <asm/processor.h>
-#include <watchdog.h>
-#include "vecnum.h"
-
-#ifdef CONFIG_SERIAL_MULTI
-#include <serial.h>
-#endif
-
-#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
-#include <malloc.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*****************************************************************************/
-#ifdef CONFIG_IOP480
-
-#define SPU_BASE 0x40000000
-
-#define spu_LineStat_rc 0x00 /* Line Status Register (Read/Clear) */
-#define spu_LineStat_w 0x04 /* Line Status Register (Set) */
-#define spu_Handshk_rc 0x08 /* Handshake Status Register (Read/Clear) */
-#define spu_Handshk_w 0x0c /* Handshake Status Register (Set) */
-#define spu_BRateDivh 0x10 /* Baud rate divisor high */
-#define spu_BRateDivl 0x14 /* Baud rate divisor low */
-#define spu_CtlReg 0x18 /* Control Register */
-#define spu_RxCmd 0x1c /* Rx Command Register */
-#define spu_TxCmd 0x20 /* Tx Command Register */
-#define spu_RxBuff 0x24 /* Rx data buffer */
-#define spu_TxBuff 0x24 /* Tx data buffer */
-
-/*-----------------------------------------------------------------------------+
- | Line Status Register.
- +-----------------------------------------------------------------------------*/
-#define asyncLSRport1 0x40000000
-#define asyncLSRport1set 0x40000004
-#define asyncLSRDataReady 0x80
-#define asyncLSRFramingError 0x40
-#define asyncLSROverrunError 0x20
-#define asyncLSRParityError 0x10
-#define asyncLSRBreakInterrupt 0x08
-#define asyncLSRTxHoldEmpty 0x04
-#define asyncLSRTxShiftEmpty 0x02
-
-/*-----------------------------------------------------------------------------+
- | Handshake Status Register.
- +-----------------------------------------------------------------------------*/
-#define asyncHSRport1 0x40000008
-#define asyncHSRport1set 0x4000000c
-#define asyncHSRDsr 0x80
-#define asyncLSRCts 0x40
-
-/*-----------------------------------------------------------------------------+
- | Control Register.
- +-----------------------------------------------------------------------------*/
-#define asyncCRport1 0x40000018
-#define asyncCRNormal 0x00
-#define asyncCRLoopback 0x40
-#define asyncCRAutoEcho 0x80
-#define asyncCRDtr 0x20
-#define asyncCRRts 0x10
-#define asyncCRWordLength7 0x00
-#define asyncCRWordLength8 0x08
-#define asyncCRParityDisable 0x00
-#define asyncCRParityEnable 0x04
-#define asyncCREvenParity 0x00
-#define asyncCROddParity 0x02
-#define asyncCRStopBitsOne 0x00
-#define asyncCRStopBitsTwo 0x01
-#define asyncCRDisableDtrRts 0x00
-
-/*-----------------------------------------------------------------------------+
- | Receiver Command Register.
- +-----------------------------------------------------------------------------*/
-#define asyncRCRport1 0x4000001c
-#define asyncRCRDisable 0x00
-#define asyncRCREnable 0x80
-#define asyncRCRIntDisable 0x00
-#define asyncRCRIntEnabled 0x20
-#define asyncRCRDMACh2 0x40
-#define asyncRCRDMACh3 0x60
-#define asyncRCRErrorInt 0x10
-#define asyncRCRPauseEnable 0x08
-
-/*-----------------------------------------------------------------------------+
- | Transmitter Command Register.
- +-----------------------------------------------------------------------------*/
-#define asyncTCRport1 0x40000020
-#define asyncTCRDisable 0x00
-#define asyncTCREnable 0x80
-#define asyncTCRIntDisable 0x00
-#define asyncTCRIntEnabled 0x20
-#define asyncTCRDMACh2 0x40
-#define asyncTCRDMACh3 0x60
-#define asyncTCRTxEmpty 0x10
-#define asyncTCRErrorInt 0x08
-#define asyncTCRStopPause 0x04
-#define asyncTCRBreakGen 0x02
-
-/*-----------------------------------------------------------------------------+
- | Miscellanies defines.
- +-----------------------------------------------------------------------------*/
-#define asyncTxBufferport1 0x40000024
-#define asyncRxBufferport1 0x40000024
-#define asyncDLABLsbport1 0x40000014
-#define asyncDLABMsbport1 0x40000010
-#define asyncXOFFchar 0x13
-#define asyncXONchar 0x11
-
-/*
- * Minimal serial functions needed to use one of the SMC ports
- * as serial console interface.
- */
-
-int serial_init (void)
-{
- volatile char val;
- unsigned short br_reg;
-
- br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
-
- /*
- * Init onboard UART
- */
- out8 (SPU_BASE + spu_LineStat_rc, 0x78); /* Clear all bits in Line Status Reg */
- out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
- out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
- out8 (SPU_BASE + spu_CtlReg, 0x08); /* Set 8 bits, no parity and 1 stop bit */
- out8 (SPU_BASE + spu_RxCmd, 0xb0); /* Enable Rx */
- out8 (SPU_BASE + spu_TxCmd, 0x9c); /* Enable Tx */
- out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
- val = in8 (SPU_BASE + spu_RxBuff); /* Dummy read, to clear receiver */
-
- return (0);
-}
-
-void serial_setbrg (void)
-{
- unsigned short br_reg;
-
- br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
-
- out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
- out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
-}
-
-void serial_putc (const char c)
-{
- if (c == '\n')
- serial_putc ('\r');
-
- /* load status from handshake register */
- if (in8 (SPU_BASE + spu_Handshk_rc) != 00)
- out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
-
- out8 (SPU_BASE + spu_TxBuff, c); /* Put char */
-
- while ((in8 (SPU_BASE + spu_LineStat_rc) & 04) != 04) {
- if (in8 (SPU_BASE + spu_Handshk_rc) != 00)
- out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
- }
-}
-
-void serial_puts (const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
-int serial_getc ()
-{
- unsigned char status = 0;
-
- while (1) {
- status = in8 (asyncLSRport1);
- if ((status & asyncLSRDataReady) != 0x0) {
- break;
- }
- if ((status & ( asyncLSRFramingError |
- asyncLSROverrunError |
- asyncLSRParityError |
- asyncLSRBreakInterrupt )) != 0) {
- (void) out8 (asyncLSRport1,
- asyncLSRFramingError |
- asyncLSROverrunError |
- asyncLSRParityError |
- asyncLSRBreakInterrupt );
- }
- }
- return (0x000000ff & (int) in8 (asyncRxBufferport1));
-}
-
-int serial_tstc ()
-{
- unsigned char status;
-
- status = in8 (asyncLSRport1);
- if ((status & asyncLSRDataReady) != 0x0) {
- return (1);
- }
- if ((status & ( asyncLSRFramingError |
- asyncLSROverrunError |
- asyncLSRParityError |
- asyncLSRBreakInterrupt )) != 0) {
- (void) out8 (asyncLSRport1,
- asyncLSRFramingError |
- asyncLSROverrunError |
- asyncLSRParityError |
- asyncLSRBreakInterrupt);
- }
- return 0;
-}
-
-#endif /* CONFIG_IOP480 */
-
-/*****************************************************************************/
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
- defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
- defined(CONFIG_440)
-
-#if defined(CONFIG_440)
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300
-#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400
-#else
-#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200
-#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300
-#endif
-
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
-#define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000600
-#endif
-
-#if defined(CONFIG_440GP)
-#define CR0_MASK 0x3fff0000
-#define CR0_EXTCLK_ENA 0x00600000
-#define CR0_UDIV_POS 16
-#define UDIV_SUBTRACT 1
-#define UART0_SDR cntrl0
-#define MFREG(a, d) d = mfdcr(a)
-#define MTREG(a, d) mtdcr(a, d)
-#else /* #if defined(CONFIG_440GP) */
-/* all other 440 PPC's access clock divider via sdr register */
-#define CR0_MASK 0xdfffffff
-#define CR0_EXTCLK_ENA 0x00800000
-#define CR0_UDIV_POS 0
-#define UDIV_SUBTRACT 0
-#define UART0_SDR sdr_uart0
-#define UART1_SDR sdr_uart1
-#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \
- defined(CONFIG_440GR) || defined(CONFIG_440GRx) || \
- defined(CONFIG_440SP) || defined(CONFIG_440SPe)
-#define UART2_SDR sdr_uart2
-#endif
-#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \
- defined(CONFIG_440GR) || defined(CONFIG_440GRx)
-#define UART3_SDR sdr_uart3
-#endif
-#define MFREG(a, d) mfsdr(a, d)
-#define MTREG(a, d) mtsdr(a, d)
-#endif /* #if defined(CONFIG_440GP) */
-#elif defined(CONFIG_405EP) || defined(CONFIG_405EZ)
-#define UART0_BASE 0xef600300
-#define UART1_BASE 0xef600400
-#define UCR0_MASK 0x0000007f
-#define UCR1_MASK 0x00007f00
-#define UCR0_UDIV_POS 0
-#define UCR1_UDIV_POS 8
-#define UDIV_MAX 127
-#else /* CONFIG_405GP || CONFIG_405CR */
-#define UART0_BASE 0xef600300
-#define UART1_BASE 0xef600400
-#define CR0_MASK 0x00001fff
-#define CR0_EXTCLK_ENA 0x000000c0
-#define CR0_UDIV_POS 1
-#define UDIV_MAX 32
-#endif
-
-/* using serial port 0 or 1 as U-Boot console ? */
-#if defined(CONFIG_UART1_CONSOLE)
-#define ACTING_UART0_BASE UART1_BASE
-#define ACTING_UART1_BASE UART0_BASE
-#else
-#define ACTING_UART0_BASE UART0_BASE
-#define ACTING_UART1_BASE UART1_BASE
-#endif
-
-#if defined(CONFIG_SERIAL_MULTI)
-#define UART_BASE dev_base
-#else
-#define UART_BASE ACTING_UART0_BASE
-#endif
-
-#if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK)
-#error "External serial clock not supported on AMCC PPC405EP!"
-#endif
-
-#define UART_RBR 0x00
-#define UART_THR 0x00
-#define UART_IER 0x01
-#define UART_IIR 0x02
-#define UART_FCR 0x02
-#define UART_LCR 0x03
-#define UART_MCR 0x04
-#define UART_LSR 0x05
-#define UART_MSR 0x06
-#define UART_SCR 0x07
-#define UART_DLL 0x00
-#define UART_DLM 0x01
-
-/*-----------------------------------------------------------------------------+
- | Line Status Register.
- +-----------------------------------------------------------------------------*/
-/*#define asyncLSRport1 ACTING_UART0_BASE+0x05 */
-#define asyncLSRDataReady1 0x01
-#define asyncLSROverrunError1 0x02
-#define asyncLSRParityError1 0x04
-#define asyncLSRFramingError1 0x08
-#define asyncLSRBreakInterrupt1 0x10
-#define asyncLSRTxHoldEmpty1 0x20
-#define asyncLSRTxShiftEmpty1 0x40
-#define asyncLSRRxFifoError1 0x80
-
-/*-----------------------------------------------------------------------------+
- | Miscellanies defines.
- +-----------------------------------------------------------------------------*/
-/*#define asyncTxBufferport1 ACTING_UART0_BASE+0x00 */
-/*#define asyncRxBufferport1 ACTING_UART0_BASE+0x00 */
-
-#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
-/*-----------------------------------------------------------------------------+
- | Fifo
- +-----------------------------------------------------------------------------*/
-typedef struct {
- char *rx_buffer;
- ulong rx_put;
- ulong rx_get;
-} serial_buffer_t;
-
-volatile static serial_buffer_t buf_info;
-#endif
-
-#if defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLOCK)
-static void serial_divs (int baudrate, unsigned long *pudiv,
- unsigned short *pbdiv)
-{
- sys_info_t sysinfo;
- unsigned long div; /* total divisor udiv * bdiv */
- unsigned long umin; /* minimum udiv */
- unsigned short diff; /* smallest diff */
- unsigned long udiv; /* best udiv */
- unsigned short idiff; /* current diff */
- unsigned short ibdiv; /* current bdiv */
- unsigned long i;
- unsigned long est; /* current estimate */
-
- get_sys_info(&sysinfo);
-
- udiv = 32; /* Assume lowest possible serial clk */
- div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */
- umin = sysinfo.pllOpbDiv << 1; /* 2 x OPB divisor */
- diff = 32; /* highest possible */
-
- /* i is the test udiv value -- start with the largest
- * possible (32) to minimize serial clock and constrain
- * search to umin.
- */
- for (i = 32; i > umin; i--) {
- ibdiv = div / i;
- est = i * ibdiv;
- idiff = (est > div) ? (est-div) : (div-est);
- if (idiff == 0) {
- udiv = i;
- break; /* can't do better */
- } else if (idiff < diff) {
- udiv = i; /* best so far */
- diff = idiff; /* update lowest diff*/
- }
- }
-
- *pudiv = udiv;
- *pbdiv = div / udiv;
-}
-
-#elif defined(CONFIG_405EZ)
-
-static void serial_divs (int baudrate, unsigned long *pudiv,
- unsigned short *pbdiv)
-{
- sys_info_t sysinfo;
- unsigned long div; /* total divisor udiv * bdiv */
- unsigned long umin; /* minimum udiv */
- unsigned short diff; /* smallest diff */
- unsigned long udiv; /* best udiv */
- unsigned short idiff; /* current diff */
- unsigned short ibdiv; /* current bdiv */
- unsigned long i;
- unsigned long est; /* current estimate */
- unsigned long plloutb;
- unsigned long cpr_pllc;
- u32 reg;
-
- /* check the pll feedback source */
- mfcpr(cprpllc, cpr_pllc);
-
- get_sys_info(&sysinfo);
-
- plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ?
- sysinfo.pllFwdDivB : sysinfo.pllFwdDiv) * sysinfo.pllFbkDiv) /
- sysinfo.pllFwdDivB);
- udiv = 256; /* Assume lowest possible serial clk */
- div = plloutb / (16 * baudrate); /* total divisor */
- umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */
- diff = 256; /* highest possible */
-
- /* i is the test udiv value -- start with the largest
- * possible (256) to minimize serial clock and constrain
- * search to umin.
- */
- for (i = 256; i > umin; i--) {
- ibdiv = div / i;
- est = i * ibdiv;
- idiff = (est > div) ? (est-div) : (div-est);
- if (idiff == 0) {
- udiv = i;
- break; /* can't do better */
- } else if (idiff < diff) {
- udiv = i; /* best so far */
- diff = idiff; /* update lowest diff*/
- }
- }
-
- *pudiv = udiv;
- mfcpr(cprperd0, reg);
- reg &= ~0x0000ffff;
- reg |= ((udiv - 0) << 8) | (udiv - 0);
- mtcpr(cprperd0, reg);
- *pbdiv = div / udiv;
-}
-#endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK) */
-
-/*
- * Minimal serial functions needed to use one of the SMC ports
- * as serial console interface.
- */
-
-#if defined(CONFIG_440)
-#if defined(CONFIG_SERIAL_MULTI)
-int serial_init_dev (unsigned long dev_base)
-#else
-int serial_init(void)
-#endif
-{
- unsigned long reg;
- unsigned long udiv;
- unsigned short bdiv;
- volatile char val;
-#ifdef CFG_EXT_SERIAL_CLOCK
- unsigned long tmp;
-#endif
-
- MFREG(UART0_SDR, reg);
- reg &= ~CR0_MASK;
-
-#ifdef CFG_EXT_SERIAL_CLOCK
- reg |= CR0_EXTCLK_ENA;
- udiv = 1;
- tmp = gd->baudrate * 16;
- bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
-#else
- /* For 440, the cpu clock is on divider chain A, UART on divider
- * chain B ... so cpu clock is irrelevant. Get the "optimized"
- * values that are subject to the 1/2 opb clock constraint
- */
- serial_divs (gd->baudrate, &udiv, &bdiv);
-#endif
-
- reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */
-
- /*
- * Configure input clock to baudrate generator for all
- * available serial ports here
- */
- MTREG(UART0_SDR, reg);
-#if defined(UART1_SDR)
- MTREG(UART1_SDR, reg);
-#endif
-#if defined(UART2_SDR)
- MTREG(UART2_SDR, reg);
-#endif
-#if defined(UART3_SDR)
- MTREG(UART3_SDR, reg);
-#endif
-
- out8(UART_BASE + UART_LCR, 0x80); /* set DLAB bit */
- out8(UART_BASE + UART_DLL, bdiv); /* set baudrate divisor */
- out8(UART_BASE + UART_DLM, bdiv >> 8); /* set baudrate divisor */
- out8(UART_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
- out8(UART_BASE + UART_FCR, 0x00); /* disable FIFO */
- out8(UART_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
- val = in8(UART_BASE + UART_LSR); /* clear line status */
- val = in8(UART_BASE + UART_RBR); /* read receive buffer */
- out8(UART_BASE + UART_SCR, 0x00); /* set scratchpad */
- out8(UART_BASE + UART_IER, 0x00); /* set interrupt enable reg */
-
- return (0);
-}
-
-#else /* !defined(CONFIG_440) */
-
-#if defined(CONFIG_SERIAL_MULTI)
-int serial_init_dev (unsigned long dev_base)
-#else
-int serial_init (void)
-#endif
-{
- unsigned long reg;
- unsigned long tmp;
- unsigned long clk;
- unsigned long udiv;
- unsigned short bdiv;
- volatile char val;
-
-#if defined(CONFIG_405EZ)
- serial_divs(gd->baudrate, &udiv, &bdiv);
- clk = tmp = reg = 0;
-#else
-#ifdef CONFIG_405EP
- reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK);
- clk = gd->cpu_clk;
- tmp = CFG_BASE_BAUD * 16;
- udiv = (clk + tmp / 2) / tmp;
- if (udiv > UDIV_MAX) /* max. n bits for udiv */
- udiv = UDIV_MAX;
- reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */
- reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */
- mtdcr (cpc0_ucr, reg);
-#else /* CONFIG_405EP */
- reg = mfdcr(cntrl0) & ~CR0_MASK;
-#ifdef CFG_EXT_SERIAL_CLOCK
- clk = CFG_EXT_SERIAL_CLOCK;
- udiv = 1;
- reg |= CR0_EXTCLK_ENA;
-#else
- clk = gd->cpu_clk;
-#ifdef CFG_405_UART_ERRATA_59
- udiv = 31; /* Errata 59: stuck at 31 */
-#else
- tmp = CFG_BASE_BAUD * 16;
- udiv = (clk + tmp / 2) / tmp;
- if (udiv > UDIV_MAX) /* max. n bits for udiv */
- udiv = UDIV_MAX;
-#endif
-#endif
- reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
- mtdcr (cntrl0, reg);
-#endif /* CONFIG_405EP */
- tmp = gd->baudrate * udiv * 16;
- bdiv = (clk + tmp / 2) / tmp;
-#endif /* CONFIG_405EZ */
-
- out8(UART_BASE + UART_LCR, 0x80); /* set DLAB bit */
- out8(UART_BASE + UART_DLL, bdiv); /* set baudrate divisor */
- out8(UART_BASE + UART_DLM, bdiv >> 8); /* set baudrate divisor */
- out8(UART_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
- out8(UART_BASE + UART_FCR, 0x00); /* disable FIFO */
- out8(UART_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
- val = in8(UART_BASE + UART_LSR); /* clear line status */
- val = in8(UART_BASE + UART_RBR); /* read receive buffer */
- out8(UART_BASE + UART_SCR, 0x00); /* set scratchpad */
- out8(UART_BASE + UART_IER, 0x00); /* set interrupt enable reg */
-
- return (0);
-}
-
-#endif /* if defined(CONFIG_440) */
-
-#if defined(CONFIG_SERIAL_MULTI)
-void serial_setbrg_dev (unsigned long dev_base)
-#else
-void serial_setbrg (void)
-#endif
-{
-#if defined(CONFIG_SERIAL_MULTI)
- serial_init_dev(dev_base);
-#else
- serial_init();
-#endif
-}
-
-#if defined(CONFIG_SERIAL_MULTI)
-void serial_putc_dev (unsigned long dev_base, const char c)
-#else
-void serial_putc (const char c)
-#endif
-{
- int i;
-
- if (c == '\n')
-#if defined(CONFIG_SERIAL_MULTI)
- serial_putc_dev (dev_base, '\r');
-#else
- serial_putc ('\r');
-#endif
-
- /* check THRE bit, wait for transmiter available */
- for (i = 1; i < 3500; i++) {
- if ((in8 (UART_BASE + UART_LSR) & 0x20) == 0x20)
- break;
- udelay (100);
- }
- out8 (UART_BASE + UART_THR, c); /* put character out */
-}
-
-#if defined(CONFIG_SERIAL_MULTI)
-void serial_puts_dev (unsigned long dev_base, const char *s)
-#else
-void serial_puts (const char *s)
-#endif
-{
- while (*s) {
-#if defined(CONFIG_SERIAL_MULTI)
- serial_putc_dev (dev_base, *s++);
-#else
- serial_putc (*s++);
-#endif
- }
-}
-
-#if defined(CONFIG_SERIAL_MULTI)
-int serial_getc_dev (unsigned long dev_base)
-#else
-int serial_getc (void)
-#endif
-{
- unsigned char status = 0;
-
- while (1) {
-#if defined(CONFIG_HW_WATCHDOG)
- WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
-#endif /* CONFIG_HW_WATCHDOG */
- status = in8 (UART_BASE + UART_LSR);
- if ((status & asyncLSRDataReady1) != 0x0) {
- break;
- }
- if ((status & ( asyncLSRFramingError1 |
- asyncLSROverrunError1 |
- asyncLSRParityError1 |
- asyncLSRBreakInterrupt1 )) != 0) {
- out8 (UART_BASE + UART_LSR,
- asyncLSRFramingError1 |
- asyncLSROverrunError1 |
- asyncLSRParityError1 |
- asyncLSRBreakInterrupt1);
- }
- }
- return (0x000000ff & (int) in8 (UART_BASE));
-}
-
-#if defined(CONFIG_SERIAL_MULTI)
-int serial_tstc_dev (unsigned long dev_base)
-#else
-int serial_tstc (void)
-#endif
-{
- unsigned char status;
-
- status = in8 (UART_BASE + UART_LSR);
- if ((status & asyncLSRDataReady1) != 0x0) {
- return (1);
- }
- if ((status & ( asyncLSRFramingError1 |
- asyncLSROverrunError1 |
- asyncLSRParityError1 |
- asyncLSRBreakInterrupt1 )) != 0) {
- out8 (UART_BASE + UART_LSR,
- asyncLSRFramingError1 |
- asyncLSROverrunError1 |
- asyncLSRParityError1 |
- asyncLSRBreakInterrupt1);
- }
- return 0;
-}
-
-#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
-
-void serial_isr (void *arg)
-{
- int space;
- int c;
- const int rx_get = buf_info.rx_get;
- int rx_put = buf_info.rx_put;
-
- if (rx_get <= rx_put) {
- space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
- } else {
- space = rx_get - rx_put;
- }
- while (serial_tstc_dev (ACTING_UART0_BASE)) {
- c = serial_getc_dev (ACTING_UART0_BASE);
- if (space) {
- buf_info.rx_buffer[rx_put++] = c;
- space--;
- }
- if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO)
- rx_put = 0;
- if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) {
- /* Stop flow by setting RTS inactive */
- out8 (ACTING_UART0_BASE + UART_MCR,
- in8 (ACTING_UART0_BASE + UART_MCR) & (0xFF ^ 0x02));
- }
- }
- buf_info.rx_put = rx_put;
-}
-
-void serial_buffered_init (void)
-{
- serial_puts ("Switching to interrupt driven serial input mode.\n");
- buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO);
- buf_info.rx_put = 0;
- buf_info.rx_get = 0;
-
- if (in8 (ACTING_UART0_BASE + UART_MSR) & 0x10) {
- serial_puts ("Check CTS signal present on serial port: OK.\n");
- } else {
- serial_puts ("WARNING: CTS signal not present on serial port.\n");
- }
-
- irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ ,
- serial_isr /*interrupt_handler_t *handler */ ,
- (void *) &buf_info /*void *arg */ );
-
- /* Enable "RX Data Available" Interrupt on UART */
- /* out8(ACTING_UART0_BASE + UART_IER, in8(ACTING_UART0_BASE + UART_IER) |0x01); */
- out8 (ACTING_UART0_BASE + UART_IER, 0x01);
- /* Set DTR active */
- out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x01);
- /* Start flow by setting RTS active */
- out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02);
- /* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */
- out8 (ACTING_UART0_BASE + UART_FCR, (1 << 6) | 1);
-}
-
-void serial_buffered_putc (const char c)
-{
- /* Wait for CTS */
-#if defined(CONFIG_HW_WATCHDOG)
- while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10))
- WATCHDOG_RESET ();
-#else
- while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10));
-#endif
- serial_putc (c);
-}
-
-void serial_buffered_puts (const char *s)
-{
- serial_puts (s);
-}
-
-int serial_buffered_getc (void)
-{
- int space;
- int c;
- int rx_get = buf_info.rx_get;
- int rx_put;
-
-#if defined(CONFIG_HW_WATCHDOG)
- while (rx_get == buf_info.rx_put)
- WATCHDOG_RESET ();
-#else
- while (rx_get == buf_info.rx_put);
-#endif
- c = buf_info.rx_buffer[rx_get++];
- if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO)
- rx_get = 0;
- buf_info.rx_get = rx_get;
-
- rx_put = buf_info.rx_put;
- if (rx_get <= rx_put) {
- space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
- } else {
- space = rx_get - rx_put;
- }
- if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) {
- /* Start flow by setting RTS active */
- out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02);
- }
-
- return c;
-}
-
-int serial_buffered_tstc (void)
-{
- return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0;
-}
-
-#endif /* CONFIG_SERIAL_SOFTWARE_FIFO */
-
-#if defined(CONFIG_CMD_KGDB)
-/*
- AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port
- number 0 or number 1
- - if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 :
- configuration has been already done
- - if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 :
- configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE
-*/
-#if (CONFIG_KGDB_SER_INDEX & 2)
-void kgdb_serial_init (void)
-{
- volatile char val;
- unsigned short br_reg;
-
- get_clocks ();
- br_reg = (((((gd->cpu_clk / 16) / 18) * 10) / CONFIG_KGDB_BAUDRATE) +
- 5) / 10;
- /*
- * Init onboard 16550 UART
- */
- out8 (ACTING_UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */
- out8 (ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */
- out8 (ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */
- out8 (ACTING_UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */
- out8 (ACTING_UART1_BASE + UART_FCR, 0x00); /* disable FIFO */
- out8 (ACTING_UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
- val = in8 (ACTING_UART1_BASE + UART_LSR); /* clear line status */
- val = in8 (ACTING_UART1_BASE + UART_RBR); /* read receive buffer */
- out8 (ACTING_UART1_BASE + UART_SCR, 0x00); /* set scratchpad */
- out8 (ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */
-}
-
-void putDebugChar (const char c)
-{
- if (c == '\n')
- serial_putc ('\r');
-
- out8 (ACTING_UART1_BASE + UART_THR, c); /* put character out */
-
- /* check THRE bit, wait for transfer done */
- while ((in8 (ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20);
-}
-
-void putDebugStr (const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
-int getDebugChar (void)
-{
- unsigned char status = 0;
-
- while (1) {
- status = in8 (ACTING_UART1_BASE + UART_LSR);
- if ((status & asyncLSRDataReady1) != 0x0) {
- break;
- }
- if ((status & ( asyncLSRFramingError1 |
- asyncLSROverrunError1 |
- asyncLSRParityError1 |
- asyncLSRBreakInterrupt1 )) != 0) {
- out8 (ACTING_UART1_BASE + UART_LSR,
- asyncLSRFramingError1 |
- asyncLSROverrunError1 |
- asyncLSRParityError1 |
- asyncLSRBreakInterrupt1);
- }
- }
- return (0x000000ff & (int) in8 (ACTING_UART1_BASE));
-}
-
-void kgdb_interruptible (int yes)
-{
- return;
-}
-
-#else /* ! (CONFIG_KGDB_SER_INDEX & 2) */
-
-void kgdb_serial_init (void)
-{
- serial_printf ("[on serial] ");
-}
-
-void putDebugChar (int c)
-{
- serial_putc (c);
-}
-
-void putDebugStr (const char *str)
-{
- serial_puts (str);
-}
-
-int getDebugChar (void)
-{
- return serial_getc ();
-}
-
-void kgdb_interruptible (int yes)
-{
- return;
-}
-#endif /* (CONFIG_KGDB_SER_INDEX & 2) */
-#endif
-
-
-#if defined(CONFIG_SERIAL_MULTI)
-int serial0_init(void)
-{
- return (serial_init_dev(UART0_BASE));
-}
-
-int serial1_init(void)
-{
- return (serial_init_dev(UART1_BASE));
-}
-void serial0_setbrg (void)
-{
- serial_setbrg_dev(UART0_BASE);
-}
-void serial1_setbrg (void)
-{
- serial_setbrg_dev(UART1_BASE);
-}
-
-void serial0_putc(const char c)
-{
- serial_putc_dev(UART0_BASE,c);
-}
-
-void serial1_putc(const char c)
-{
- serial_putc_dev(UART1_BASE, c);
-}
-void serial0_puts(const char *s)
-{
- serial_puts_dev(UART0_BASE, s);
-}
-
-void serial1_puts(const char *s)
-{
- serial_puts_dev(UART1_BASE, s);
-}
-
-int serial0_getc(void)
-{
- return(serial_getc_dev(UART0_BASE));
-}
-
-int serial1_getc(void)
-{
- return(serial_getc_dev(UART1_BASE));
-}
-int serial0_tstc(void)
-{
- return (serial_tstc_dev(UART0_BASE));
-}
-
-int serial1_tstc(void)
-{
- return (serial_tstc_dev(UART1_BASE));
-}
-
-struct serial_device serial0_device =
-{
- "serial0",
- "UART0",
- serial0_init,
- serial0_setbrg,
- serial0_getc,
- serial0_tstc,
- serial0_putc,
- serial0_puts,
-};
-
-struct serial_device serial1_device =
-{
- "serial1",
- "UART1",
- serial1_init,
- serial1_setbrg,
- serial1_getc,
- serial1_tstc,
- serial1_putc,
- serial1_puts,
-};
-#endif /* CONFIG_SERIAL_MULTI */
-
-#endif /* CONFIG_405GP || CONFIG_405CR */
/*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
#if defined(CONFIG_405GP) || defined(CONFIG_405CR)
-void get_sys_info (PPC405_SYS_INFO * sysInfo)
+void get_sys_info (PPC4xx_SYS_INFO * sysInfo)
{
unsigned long pllmr;
unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ / 1000);
sysInfo->freqProcessor = sysInfo->freqPLB * sysInfo->pllPlbDiv;
}
}
+
+ sysInfo->freqUART = sysInfo->freqProcessor;
}
{
ulong val = 0;
- PPC405_SYS_INFO sys_info;
+ PPC4xx_SYS_INFO sys_info;
get_sys_info (&sys_info);
val = sys_info.freqPLB / sys_info.pllOpbDiv;
ulong get_PCI_freq (void)
{
ulong val;
- PPC405_SYS_INFO sys_info;
+ PPC4xx_SYS_INFO sys_info;
get_sys_info (&sys_info);
val = sys_info.freqPLB / sys_info.pllPciDiv;
*/
/* Decode CPR0_PLLD0 for divisors */
- mfclk(clk_plld, reg);
+ mfcpr(clk_plld, reg);
temp = (reg & PLLD_FWDVA_MASK) >> 16;
sysInfo->pllFwdDivA = temp ? temp : 16;
temp = (reg & PLLD_FWDVB_MASK) >> 8;
sysInfo->pllFbkDiv = temp ? temp : 32;
lfdiv = reg & PLLD_LFBDV_MASK;
- mfclk(clk_opbd, reg);
+ mfcpr(clk_opbd, reg);
temp = (reg & OPBDDV_MASK) >> 24;
sysInfo->pllOpbDiv = temp ? temp : 4;
- mfclk(clk_perd, reg);
+ mfcpr(clk_perd, reg);
temp = (reg & PERDV_MASK) >> 24;
sysInfo->pllExtBusDiv = temp ? temp : 8;
- mfclk(clk_primbd, reg);
+ mfcpr(clk_primbd, reg);
temp = (reg & PRBDV_MASK) >> 24;
prbdv0 = temp ? temp : 8;
- mfclk(clk_spcid, reg);
+ mfcpr(clk_spcid, reg);
temp = (reg & SPCID_MASK) >> 24;
sysInfo->pllPciDiv = temp ? temp : 4;
temp = (reg & PLLSYS0_SEL_MASK) >> 27;
if (temp == 0) { /* PLL output */
/* Figure which pll to use */
- mfclk(clk_pllc, reg);
+ mfcpr(clk_pllc, reg);
temp = (reg & PLLC_SRC_MASK) >> 29;
if (!temp) /* PLLOUTA */
m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivA;
sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB/prbdv0;
sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
- sysInfo->freqEPB = sysInfo->freqPLB/sysInfo->pllExtBusDiv;
+ sysInfo->freqEBC = sysInfo->freqPLB/sysInfo->pllExtBusDiv;
sysInfo->freqPCI = sysInfo->freqPLB/sysInfo->pllPciDiv;
+ sysInfo->freqUART = sysInfo->freqPLB;
/* Figure which timer source to use */
if (mfspr(ccr1) & 0x0080) { /* External Clock, assume same as SYS_CLK */
else /* Internal clock */
sysInfo->freqTmrClk = sysInfo->freqProcessor;
}
+
/********************************************
* get_PCI_freq
* return PCI bus freq in Hz
if( get_pvr() == PVR_440GP_RB ) /* Rev B divs an extra 2 -- geez! */
sysInfo->freqPLB >>= 1;
sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
- sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv;
-
+ sysInfo->freqEBC = sysInfo->freqOPB/sysInfo->pllExtBusDiv;
+ sysInfo->freqUART = sysInfo->freqPLB;
}
#else
void get_sys_info (sys_info_t * sysInfo)
sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB/prbdv0;
sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
- sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv;
+ sysInfo->freqEBC = sysInfo->freqOPB/sysInfo->pllExtBusDiv;
#if defined(CONFIG_YUCCA)
/* Determine PCI Clock Period */
sysInfo->freqDDR = ((sysInfo->freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
#endif
-
+ sysInfo->freqUART = sysInfo->freqPLB;
}
#endif
extern ulong get_PCI_freq (void);
#elif defined(CONFIG_AP1000)
-void get_sys_info (sys_info_t * sysInfo) {
+void get_sys_info (sys_info_t * sysInfo)
+{
sysInfo->freqProcessor = 240 * 1000 * 1000;
sysInfo->freqPLB = 80 * 1000 * 1000;
sysInfo->freqPCI = 33 * 1000 * 1000;
#elif defined(CONFIG_405)
-void get_sys_info (sys_info_t * sysInfo) {
-
+void get_sys_info (sys_info_t * sysInfo)
+{
sysInfo->freqVCOMhz=3125000;
sysInfo->freqProcessor=12*1000*1000;
sysInfo->freqPLB=50*1000*1000;
sysInfo->freqPCI=66*1000*1000;
-
}
#elif defined(CONFIG_405EP)
-void get_sys_info (PPC405_SYS_INFO * sysInfo)
+void get_sys_info (PPC4xx_SYS_INFO * sysInfo)
{
unsigned long pllmr0;
unsigned long pllmr1;
* Determine FBK_DIV.
*/
sysInfo->pllFbkDiv = ((pllmr1 & PLLMR1_FBMUL_MASK) >> 20);
- if (sysInfo->pllFbkDiv == 0) {
+ if (sysInfo->pllFbkDiv == 0)
sysInfo->pllFbkDiv = 16;
- }
/*
* Determine PLB_DIV.
* Determine PLB clock frequency
*/
sysInfo->freqPLB = sysInfo->freqProcessor / sysInfo->pllPlbDiv;
+
+ sysInfo->freqEBC = sysInfo->freqPLB / sysInfo->pllExtBusDiv;
+
+ sysInfo->freqUART = sysInfo->freqProcessor * pllmr0_ccdv;
}
{
ulong val = 0;
- PPC405_SYS_INFO sys_info;
+ PPC4xx_SYS_INFO sys_info;
get_sys_info (&sys_info);
val = sys_info.freqPLB / sys_info.pllOpbDiv;
ulong get_PCI_freq (void)
{
ulong val;
- PPC405_SYS_INFO sys_info;
+ PPC4xx_SYS_INFO sys_info;
get_sys_info (&sys_info);
val = sys_info.freqPLB / sys_info.pllPciDiv;
}
#elif defined(CONFIG_405EZ)
-void get_sys_info (PPC405_SYS_INFO * sysInfo)
+void get_sys_info (PPC4xx_SYS_INFO * sysInfo)
{
unsigned long cpr_plld;
unsigned long cpr_pllc;
* Read CPR_PRIMAD register
*/
mfcpr(cprprimad, cpr_primad);
+
/*
* Determine PLB_DIV.
*/
*/
sysInfo->freqPLB = (CONFIG_SYS_CLK_FREQ * m) /
sysInfo->pllFwdDiv / sysInfo->pllPlbDiv;
+
+ sysInfo->freqEBC = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) /
+ sysInfo->pllExtBusDiv;
+
+ sysInfo->freqUART = sysInfo->freqVCOHz;
}
/********************************************
{
ulong val = 0;
- PPC405_SYS_INFO sys_info;
+ PPC4xx_SYS_INFO sys_info;
get_sys_info (&sys_info);
val = (CONFIG_SYS_CLK_FREQ * sys_info.pllFbkDiv) / sys_info.pllOpbDiv;
return val;
}
+#elif defined(CONFIG_405EX)
+
+/*
+ * TODO: We need to get the CPR registers and calculate these values correctly!!!!
+ * We need the specs!!!!
+ */
+static unsigned char get_fbdv(unsigned char index)
+{
+ unsigned char ret = 0;
+ /* This is table should be 256 bytes.
+ * Only take first 52 values.
+ */
+ unsigned char fbdv_tb[] = {
+ 0x00, 0xff, 0x7f, 0xfd,
+ 0x7a, 0xf5, 0x6a, 0xd5,
+ 0x2a, 0xd4, 0x29, 0xd3,
+ 0x26, 0xcc, 0x19, 0xb3,
+ 0x67, 0xce, 0x1d, 0xbb,
+ 0x77, 0xee, 0x5d, 0xba,
+ 0x74, 0xe9, 0x52, 0xa5,
+ 0x4b, 0x96, 0x2c, 0xd8,
+ 0x31, 0xe3, 0x46, 0x8d,
+ 0x1b, 0xb7, 0x6f, 0xde,
+ 0x3d, 0xfb, 0x76, 0xed,
+ 0x5a, 0xb5, 0x6b, 0xd6,
+ 0x2d, 0xdb, 0x36, 0xec,
+
+ };
+
+ if ((index & 0x7f) == 0)
+ return 1;
+ while (ret < sizeof (fbdv_tb)) {
+ if (fbdv_tb[ret] == index)
+ break;
+ ret++;
+ }
+ ret++;
+
+ return ret;
+}
+
+#define PLL_FBK_PLL_LOCAL 0
+#define PLL_FBK_CPU 1
+#define PLL_FBK_PERCLK 5
+
+void get_sys_info (sys_info_t * sysInfo)
+{
+ unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ / 1000);
+ unsigned long m = 1;
+ unsigned int tmp;
+ unsigned char fwdva[16] = {
+ 1, 2, 14, 9, 4, 11, 16, 13,
+ 12, 5, 6, 15, 10, 7, 8, 3,
+ };
+ unsigned char sel, cpudv0, plb2xDiv;
+
+ mfcpr(cpr0_plld, tmp);
+
+ /*
+ * Determine forward divider A
+ */
+ sysInfo->pllFwdDiv = fwdva[((tmp >> 16) & 0x0f)]; /* FWDVA */
+
+ /*
+ * Determine FBK_DIV.
+ */
+ sysInfo->pllFbkDiv = get_fbdv(((tmp >> 24) & 0x0ff)); /* FBDV */
+
+ /*
+ * Determine PLBDV0
+ */
+ sysInfo->pllPlbDiv = 2;
+
+ /*
+ * Determine PERDV0
+ */
+ mfcpr(cpr0_perd, tmp);
+ tmp = (tmp >> 24) & 0x03;
+ sysInfo->pllExtBusDiv = (tmp == 0) ? 4 : tmp;
+
+ /*
+ * Determine OPBDV0
+ */
+ mfcpr(cpr0_opbd, tmp);
+ tmp = (tmp >> 24) & 0x03;
+ sysInfo->pllOpbDiv = (tmp == 0) ? 4 : tmp;
+
+ /* Determine PLB2XDV0 */
+ mfcpr(cpr0_plbd, tmp);
+ tmp = (tmp >> 16) & 0x07;
+ plb2xDiv = (tmp == 0) ? 8 : tmp;
+
+ /* Determine CPUDV0 */
+ mfcpr(cpr0_cpud, tmp);
+ tmp = (tmp >> 24) & 0x07;
+ cpudv0 = (tmp == 0) ? 8 : tmp;
+
+ /* Determine SEL(5:7) in CPR0_PLLC */
+ mfcpr(cpr0_pllc, tmp);
+ sel = (tmp >> 24) & 0x07;
+
+ /*
+ * Determine the M factor
+ * PLL local: M = FBDV
+ * CPU clock: M = FBDV * FWDVA * CPUDV0
+ * PerClk : M = FBDV * FWDVA * PLB2XDV0 * PLBDV0(2) * OPBDV0 * PERDV0
+ *
+ */
+ switch (sel) {
+ case PLL_FBK_CPU:
+ m = sysInfo->pllFwdDiv * cpudv0;
+ break;
+ case PLL_FBK_PERCLK:
+ m = sysInfo->pllFwdDiv * plb2xDiv * 2
+ * sysInfo->pllOpbDiv * sysInfo->pllExtBusDiv;
+ break;
+ case PLL_FBK_PLL_LOCAL:
+ break;
+ default:
+ printf("%s unknown m\n", __FUNCTION__);
+ return;
+
+ }
+ m *= sysInfo->pllFbkDiv;
+
+ /*
+ * Determine VCO clock frequency
+ */
+ sysInfo->freqVCOHz = (1000000000000LL * (unsigned long long)m) /
+ (unsigned long long)sysClkPeriodPs;
+
+ /*
+ * Determine CPU clock frequency
+ */
+ sysInfo->freqProcessor = sysInfo->freqVCOHz / (sysInfo->pllFwdDiv * cpudv0);
+
+ /*
+ * Determine PLB clock frequency, ddr1x should be the same
+ */
+ sysInfo->freqPLB = sysInfo->freqVCOHz / (sysInfo->pllFwdDiv * plb2xDiv * 2);
+ sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
+ sysInfo->freqDDR = sysInfo->freqPLB;
+ sysInfo->freqEBC = sysInfo->freqOPB / sysInfo->pllExtBusDiv;
+ sysInfo->freqUART = sysInfo->freqPLB;
+}
+
+/********************************************
+ * get_OPB_freq
+ * return OPB bus freq in Hz
+ *********************************************/
+ulong get_OPB_freq (void)
+{
+ ulong val = 0;
+
+ PPC4xx_SYS_INFO sys_info;
+
+ get_sys_info (&sys_info);
+ val = sys_info.freqPLB / sys_info.pllOpbDiv;
+
+ return val;
+}
+
#endif
int get_clocks (void)
{
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
- defined(CONFIG_440) || defined(CONFIG_405)
+ defined(CONFIG_405EX) || defined(CONFIG_405) || \
+ defined(CONFIG_440)
sys_info_t sys_info;
get_sys_info (&sys_info);
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
- defined(CONFIG_440) || defined(CONFIG_405)
+ defined(CONFIG_405EX) || defined(CONFIG_405) || \
+ defined(CONFIG_440)
sys_info_t sys_info;
get_sys_info (&sys_info);
/*----------------------------------------------------------------------- */
/* Enable two 128MB cachable regions. */
/*----------------------------------------------------------------------- */
- addis r1,r0,0x8000
+ addis r1,r0,0xc000
addi r1,r1,0x0001
mticcr r1 /* instruction cache */
/*****************************************************************************/
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
- defined(CONFIG_405)
+ defined(CONFIG_405EX) || defined(CONFIG_405)
/*----------------------------------------------------------------------- */
/* Clear and set up some registers. */
/*----------------------------------------------------------------------- */
addi r4,r0,0x0000
+#if !defined(CONFIG_405EX)
mtspr sgr,r4
+#else
+ /*
+ * On 405EX, completely clearing the SGR leads to PPC hangup
+ * upon PCIe configuration access. The PCIe memory regions
+ * need to be guarded!
+ */
+ lis r3,0x0000
+ ori r3,r3,0x7FFC
+ mtspr sgr,r3
+#endif
mtspr dcwr,r4
mtesr r4 /* clear Exception Syndrome Reg */
mttcr r4 /* clear Timer Control Reg */
/*----------------------------------------------------------------------- */
/* Enable two 128MB cachable regions. */
/*----------------------------------------------------------------------- */
- lis r4,0x8000
+ lis r4,0xc000
ori r4,r4,0x0001
mticcr r4 /* instruction cache */
isync
ori r4,r4,0x0000
mtdccr r4 /* data cache */
-#if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
+#if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) || defined(CONFIG_405EX)
/*----------------------------------------------------------------------- */
/* Tune the speed and size for flash CS0 */
/*----------------------------------------------------------------------- */
bl ext_bus_cntlr_init
#endif
+#if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM))
+ /*
+ * Boards like the Kilauea (405EX) don't have OCM and can't use
+ * DCache for init-ram. So setup stack here directly after the
+ * SDRAM is initialized.
+ */
+ lis r1, CFG_INIT_RAM_ADDR@h
+ ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */
+
+ li r0, 0 /* Make room for stack frame header and */
+ stwu r0, -4(r1) /* clear final stack frame so that */
+ stwu r0, -4(r1) /* stack backtraces terminate cleanly */
+ /*
+ * Set up a dummy frame to store reset vector as return address.
+ * this causes stack underflow to reset board.
+ */
+ stwu r1, -8(r1) /* Save back chain and move SP */
+ lis r0, RESET_VECTOR@h /* Address of reset vector */
+ ori r0, r0, RESET_VECTOR@l
+ stwu r1, -8(r1) /* Save back chain and move SP */
+ stw r0, +12(r1) /* Save return addr (underflow vect) */
+#endif /* !(CFG_INIT_DCACHE_CS || !CFG_TEM_STACK_OCM) */
#if defined(CONFIG_405EP)
/*----------------------------------------------------------------------- */
ori r4,r4,0xa000
mtdcr ebccfgd,r4
- /* turn on data chache for this region */
+ /* turn on data cache for this region */
lis r4,0x0080
mtdccr r4
/*----------------------------------------------------------------------- */
bl sdram_init
- /*
- * Setup temporary stack pointer only for boards
- * that do not use SDRAM SPD I2C stuff since it
- * is already initialized to use DCACHE or OCM
- * stacks.
- */
-#if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM))
- lis r1, CFG_INIT_RAM_ADDR@h
- ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */
-
- li r0, 0 /* Make room for stack frame header and */
- stwu r0, -4(r1) /* clear final stack frame so that */
- stwu r0, -4(r1) /* stack backtraces terminate cleanly */
- /*
- * Set up a dummy frame to store reset vector as return address.
- * this causes stack underflow to reset board.
- */
- stwu r1, -8(r1) /* Save back chain and move SP */
- lis r0, RESET_VECTOR@h /* Address of reset vector */
- ori r0, r0, RESET_VECTOR@l
- stwu r1, -8(r1) /* Save back chain and move SP */
- stw r0, +12(r1) /* Save return addr (underflow vect) */
-#endif /* !(CFG_INIT_DCACHE_CS || !CFG_TEM_STACK_OCM) */
-
#ifdef CONFIG_NAND_SPL
bl nand_boot /* will not return */
#else
#endif /* CONFIG_440 */
-/*
- * Cache functions.
- *
- * NOTE: currently the 440s run with dcache _disabled_ once relocated to DRAM,
- * although for some cache-ralated calls stubs have to be provided to satisfy
- * symbols resolution.
- * Icache-related functions are used in POST framework.
- *
- */
-#ifdef CONFIG_440
- .globl dcache_disable
- .globl icache_disable
- .globl icache_enable
-dcache_disable:
-icache_disable:
-icache_enable:
- blr
-
- .globl dcache_status
- .globl icache_status
-dcache_status:
-icache_status:
- mr r3, 0
- blr
-#else
-flush_dcache:
- addis r9,r0,0x0002 /* set mask for EE and CE msr bits */
- ori r9,r9,0x8000
- mfmsr r12 /* save msr */
- andc r9,r12,r9
- mtmsr r9 /* disable EE and CE */
- addi r10,r0,0x0001 /* enable data cache for unused memory */
- mfdccr r9 /* region 0xF8000000-0xFFFFFFFF via */
- or r10,r10,r9 /* bit 31 in dccr */
- mtdccr r10
-
- /* do loop for # of congruence classes. */
- lis r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS: for large cache sizes */
- ori r10,r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
- lis r11,(CFG_DCACHE_SIZE / 2)@ha /* D cache set size - 2 way sets */
- ori r11,r11,(CFG_DCACHE_SIZE / 2)@l /* D cache set size - 2 way sets */
- mtctr r10
- addi r10,r0,(0xE000-0x10000) /* start at 0xFFFFE000 */
- add r11,r10,r11 /* add to get to other side of cache line */
-..flush_dcache_loop:
- lwz r3,0(r10) /* least recently used side */
- lwz r3,0(r11) /* the other side */
- dccci r0,r11 /* invalidate both sides */
- addi r10,r10,CFG_CACHELINE_SIZE /* bump to next line */
- addi r11,r11,CFG_CACHELINE_SIZE /* bump to next line */
- bdnz ..flush_dcache_loop
- sync /* allow memory access to complete */
- mtdccr r9 /* restore dccr */
- mtmsr r12 /* restore msr */
- blr
-
- .globl icache_enable
-icache_enable:
- mflr r8
- bl invalidate_icache
- mtlr r8
- isync
- addis r3,r0, 0x8000 /* set bit 0 */
- mticcr r3
- blr
-
- .globl icache_disable
-icache_disable:
- addis r3,r0, 0x0000 /* clear bit 0 */
- mticcr r3
- isync
- blr
-
- .globl icache_status
-icache_status:
- mficcr r3
- srwi r3, r3, 31 /* >>31 => select bit 0 */
- blr
-
- .globl dcache_enable
-dcache_enable:
- mflr r8
- bl invalidate_dcache
- mtlr r8
- isync
- addis r3,r0, 0x8000 /* set bit 0 */
- mtdccr r3
- blr
-
- .globl dcache_disable
-dcache_disable:
- mflr r8
- bl flush_dcache
- mtlr r8
- addis r3,r0, 0x0000 /* clear bit 0 */
- mtdccr r3
- blr
-
- .globl dcache_status
-dcache_status:
- mfdccr r3
- srwi r3, r3, 31 /* >>31 => select bit 0 */
- blr
-#endif
-
.globl get_pvr
get_pvr:
mfspr r3, PVR
*/
.globl relocate_code
relocate_code:
+#ifdef CONFIG_4xx_DCACHE
+ /*
+ * We need to flush the Init Data before the dcache will be
+ * invalidated
+ */
+
+ /* save regs */
+ mr r9,r3
+ mr r10,r4
+ mr r11,r5
+
+ mr r3,r4
+ addi r4,r4,0x200 /* should be enough for init data */
+ bl flush_dcache_range
+
+ /* restore regs */
+ mr r3,r9
+ mr r4,r10
+ mr r5,r11
+#endif
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
dccci 0,0 /* Invalidate data cache, now no longer our stack */
sync
isync
- addi r1,r0,0x0000 /* TLB entry #0 */
+#ifdef CFG_TLB_FOR_BOOT_FLASH
+ addi r1,r0,CFG_TLB_FOR_BOOT_FLASH /* Use defined TLB */
+#else
+ addi r1,r0,0x0000 /* Default TLB entry is #0 */
+#endif
tlbre r0,r1,0x0002 /* Read contents */
ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
tlbwe r0,r1,0x0002 /* Save it out */
ori r4, r4, CFG_MONITOR_BASE@l
lwz r5, GOT(__init_end)
sub r5, r5, r4
- li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
+ li r6, L1_CACHE_BYTES /* Cache Line Size */
/*
* Fix GOT pointer:
lwz r4,GOT(_end)
cmplw 0, r3, r4
- beq 6f
+ beq 7f
li r0, 0
-5:
+
+ andi. r5, r4, 3
+ beq 6f
+ sub r4, r4, r5
+ mtctr r5
+ mr r5, r4
+5: stb r0, 0(r5)
+ addi r5, r5, 1
+ bdnz 5b
+6:
stw r0, 0(r3)
addi r3, r3, 4
cmplw 0, r3, r4
- bne 5b
-6:
+ bne 6b
+7:
mr r3, r9 /* Init Data pointer */
mr r4, r10 /* Destination Address */
bl board_init_r
lwz 3,0x0000(3)
blr
-invalidate_icache:
- iccci r0,r0 /* for 405, iccci invalidates the */
- blr /* entire I cache */
-
-invalidate_dcache:
- addi r6,0,0x0000 /* clear GPR 6 */
- /* Do loop for # of dcache congruence classes. */
- lis r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS for large sized cache */
- ori r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
- /* NOTE: dccci invalidates both */
- mtctr r7 /* ways in the D cache */
-..dcloop:
- dccci 0,r6 /* invalidate line */
- addi r6,r6, CFG_CACHELINE_SIZE /* bump to next line */
- bdnz ..dcloop
- blr
-
/**************************************************************************/
/* PPC405EP specific stuff */
/**************************************************************************/
#if defined(CONFIG_440)
#include <ppc440.h>
+#include <asm/cache.h>
#include <asm/io.h>
#include <asm/mmu.h>
u32 tlb_vaddr;
u32 tlb_size = 0;
- /* First, find the index of a TLB entry not being used */
for (i=0; i<PPC4XX_TLB_SIZE; i++) {
tlb_word0_value = mftlb1(i);
tlb_vaddr = TLB_WORD0_EPN_DECODE(tlb_word0_value);
asm("isync");
}
+/*
+ * Change the I attribute (cache inhibited) of a TLB or multiple TLB's.
+ * This function is used to either turn cache on or off in a specific
+ * memory area.
+ */
+void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value)
+{
+ int i;
+ u32 tlb_word0_value;
+ u32 tlb_word2_value;
+ u32 tlb_vaddr;
+ u32 tlb_size = 0;
+
+ for (i=0; i<PPC4XX_TLB_SIZE; i++) {
+ tlb_word0_value = mftlb1(i);
+ tlb_vaddr = TLB_WORD0_EPN_DECODE(tlb_word0_value);
+ if (((tlb_word0_value & TLB_WORD0_V_MASK) == TLB_WORD0_V_ENABLE) &&
+ (tlb_vaddr >= vaddr)) {
+ /*
+ * TLB is enabled and start address is lower or equal
+ * than the area we are looking for. Now we only have
+ * to check the size/end address for a match.
+ */
+ switch (tlb_word0_value & TLB_WORD0_SIZE_MASK) {
+ case TLB_WORD0_SIZE_1KB:
+ tlb_size = 1 << 10;
+ break;
+ case TLB_WORD0_SIZE_4KB:
+ tlb_size = 4 << 10;
+ break;
+ case TLB_WORD0_SIZE_16KB:
+ tlb_size = 16 << 10;
+ break;
+ case TLB_WORD0_SIZE_64KB:
+ tlb_size = 64 << 10;
+ break;
+ case TLB_WORD0_SIZE_256KB:
+ tlb_size = 256 << 10;
+ break;
+ case TLB_WORD0_SIZE_1MB:
+ tlb_size = 1 << 20;
+ break;
+ case TLB_WORD0_SIZE_16MB:
+ tlb_size = 16 << 20;
+ break;
+ case TLB_WORD0_SIZE_256MB:
+ tlb_size = 256 << 20;
+ break;
+ }
+
+ /*
+ * Now check the end-address if it's in the range
+ */
+ if ((tlb_vaddr + tlb_size - 1) <= (vaddr + size - 1)) {
+ /*
+ * Found a TLB in the range.
+ * Change cache attribute in tlb2 word.
+ */
+ tlb_word2_value =
+ TLB_WORD2_U0_DISABLE | TLB_WORD2_U1_DISABLE |
+ TLB_WORD2_U2_DISABLE | TLB_WORD2_U3_DISABLE |
+ TLB_WORD2_W_DISABLE | tlb_word2_i_value |
+ TLB_WORD2_M_DISABLE | TLB_WORD2_G_DISABLE |
+ TLB_WORD2_E_DISABLE | TLB_WORD2_UX_ENABLE |
+ TLB_WORD2_UW_ENABLE | TLB_WORD2_UR_ENABLE |
+ TLB_WORD2_SX_ENABLE | TLB_WORD2_SW_ENABLE |
+ TLB_WORD2_SR_ENABLE;
+
+ /*
+ * Now either flush or invalidate the dcache
+ */
+ if (tlb_word2_i_value)
+ flush_dcache();
+ else
+ invalidate_dcache();
+
+ mttlb3(i, tlb_word2_value);
+ asm("iccci 0,0");
+ }
+ }
+ }
+
+ /* Execute an ISYNC instruction so that the new TLB entry takes effect */
+ asm("isync");
+}
+
static int add_tlb_entry(unsigned long phys_addr,
unsigned long virt_addr,
unsigned long tlb_word0_size_value,
#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT)
+#ifdef CONFIG_4xx_DCACHE
+#include <asm/mmu.h>
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
#include "usbdev.h"
int usb_cpu_init(void)
{
+#ifdef CONFIG_4xx_DCACHE
+ /* disable cache */
+ change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, TLB_WORD2_I_ENABLE);
+#endif
#if defined(CONFIG_440EP) || defined(CONFIG_440EPX)
usb_dev_init();
#endif
-
return 0;
}
int usb_cpu_stop(void)
{
+#ifdef CONFIG_4xx_DCACHE
+ /* enable cache */
+ change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, 0);
+#endif
return 0;
}
int usb_cpu_init_fail(void)
{
+#ifdef CONFIG_4xx_DCACHE
+ /* enable cache */
+ change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, 0);
+#endif
return 0;
}
#define VECNUM_EIR3 30 /* External interrupt 3 */
#define VECNUM_EIR4 31 /* External interrupt 4 */
+#elif defined(CONFIG_405EX)
+
+/* UIC 0 */
+#define VECNUM_U0 00
+#define VECNUM_U1 01
+#define VECNUM_IIC0 02
+#define VECNUM_PKA 03
+#define VECNUM_TRNG 04
+#define VECNUM_EBM 05
+#define VECNUM_BGI 06
+#define VECNUM_IIC1 07
+#define VECNUM_SPI 08
+#define VECNUM_EIR0 09
+#define VECNUM_MTE 10 /* MAL Tx EOB */
+#define VECNUM_MRE 11 /* MAL Rx EOB */
+#define VECNUM_DMA0 12
+#define VECNUM_DMA1 13
+#define VECNUM_DMA2 14
+#define VECNUM_DMA3 15
+#define VECNUM_PCIE0AL 16
+#define VECNUM_PCIE0VPD 17
+#define VECNUM_RPCIE0HRST 18
+#define VECNUM_FPCIE0HRST 19
+#define VECNUM_PCIE0TCR 20
+#define VECNUM_PCIEMSI0 21
+#define VECNUM_PCIEMSI1 22
+#define VECNUM_SECURITY 23
+#define VECNUM_ETH0 24
+#define VECNUM_ETH1 25
+#define VECNUM_PCIEMSI2 26
+#define VECNUM_EIR4 27
+#define VECNUM_UIC2NC 28
+#define VECNUM_UIC2C 29
+#define VECNUM_UIC1NC 30
+#define VECNUM_UIC1C 31
+
+/* UIC 1 */
+#define VECNUM_MS (32 + 00) /* MAL SERR */
+#define VECNUM_TXDE (32 + 01) /* MAL TXDE */
+#define VECNUM_RXDE (32 + 02) /* MAL RXDE */
+#define VECNUM_PCIE0BMVC0 (32 + 03)
+#define VECNUM_PCIE0DCRERR (32 + 04)
+#define VECNUM_EBC (32 + 05)
+#define VECNUM_NDFC (32 + 06)
+#define VECNUM_PCEI1DCRERR (32 + 07)
+#define VECNUM_CT8 (32 + 08)
+#define VECNUM_CT9 (32 + 09)
+#define VECNUM_PCIE1AL (32 + 10)
+#define VECNUM_PCIE1VPD (32 + 11)
+#define VECNUM_RPCE1HRST (32 + 12)
+#define VECNUM_FPCE1HRST (32 + 13)
+#define VECNUM_PCIE1TCR (32 + 14)
+#define VECNUM_PCIE1VC0 (32 + 15)
+#define VECNUM_CT3 (32 + 16)
+#define VECNUM_CT4 (32 + 17)
+#define VECNUM_EIR7 (32 + 18)
+#define VECNUM_EIR8 (32 + 19)
+#define VECNUM_EIR9 (32 + 20)
+#define VECNUM_CT5 (32 + 21)
+#define VECNUM_CT6 (32 + 22)
+#define VECNUM_CT7 (32 + 23)
+#define VECNUM_SROM (32 + 24) /* SERIAL ROM */
+#define VECNUM_GPTDECPULS (32 + 25) /* GPT Decrement pulse */
+#define VECNUM_EIR2 (32 + 26)
+#define VECNUM_EIR5 (32 + 27)
+#define VECNUM_EIR6 (32 + 28)
+#define VECNUM_EMAC0WAKE (32 + 29)
+#define VECNUM_EIR1 (32 + 30)
+#define VECNUM_EMAC1WAKE (32 + 31)
+
+/* UIC 2 */
+#define VECNUM_PCIE0INTA (64 + 00) /* PCIE0 INTA */
+#define VECNUM_PCIE0INTB (64 + 01) /* PCIE0 INTB */
+#define VECNUM_PCIE0INTC (64 + 02) /* PCIE0 INTC */
+#define VECNUM_PCIE0INTD (64 + 03) /* PCIE0 INTD */
+#define VECNUM_EIR3 (64 + 04) /* External IRQ 3 */
+#define VECNUM_DDRMCUE (64 + 05)
+#define VECNUM_DDRMCCE (64 + 06)
+#define VECNUM_MALINTCOATX0 (64 + 07) /* Interrupt coalecence TX0 */
+#define VECNUM_MALINTCOATX1 (64 + 08) /* Interrupt coalecence TX1 */
+#define VECNUM_MALINTCOARX0 (64 + 09) /* Interrupt coalecence RX0 */
+#define VECNUM_MALINTCOARX1 (64 + 10) /* Interrupt coalecence RX1 */
+#define VECNUM_PCIE1INTA (64 + 11) /* PCIE0 INTA */
+#define VECNUM_PCIE1INTB (64 + 12) /* PCIE0 INTB */
+#define VECNUM_PCIE1INTC (64 + 13) /* PCIE0 INTC */
+#define VECNUM_PCIE1INTD (64 + 14) /* PCIE0 INTD */
+#define VECNUM_RPCIEMSI2 (64 + 15) /* MSI level 2 */
+#define VECNUM_PCIEMSI3 (64 + 16) /* MSI level 2 */
+#define VECNUM_PCIEMSI4 (64 + 17) /* MSI level 2 */
+#define VECNUM_PCIEMSI5 (64 + 18) /* MSI level 2 */
+#define VECNUM_PCIEMSI6 (64 + 19) /* MSI level 2 */
+#define VECNUM_PCIEMSI7 (64 + 20) /* MSI level 2 */
+#define VECNUM_PCIEMSI8 (64 + 21) /* MSI level 2 */
+#define VECNUM_PCIEMSI9 (64 + 22) /* MSI level 2 */
+#define VECNUM_PCIEMSI10 (64 + 23) /* MSI level 2 */
+#define VECNUM_PCIEMSI11 (64 + 24) /* MSI level 2 */
+#define VECNUM_PCIEMSI12 (64 + 25) /* MSI level 2 */
+#define VECNUM_PCIEMSI13 (64 + 26) /* MSI level 2 */
+#define VECNUM_PCIEMSI14 (64 + 27) /* MSI level 2 */
+#define VECNUM_PCIEMSI15 (64 + 28) /* MSI level 2 */
+#define VECNUM_PLB4XAHB (64 + 29) /* PLBxAHB bridge */
+#define VECNUM_USBWAKE (64 + 30) /* USB wakup */
+#define VECNUM_USBOTG (64 + 31) /* USB OTG */
+
#else /* !CONFIG_405EZ */
#define VECNUM_U0 0 /* UART0 */
--- /dev/null
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(CPU).a
+
+START = start.o
+OBJS = cpu.o interrupts.o watchdog.o time.o cache.o
+
+all: .depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+/*
+ * Jump to P2 area.
+ * When handling TLB or caches, we need to do it from P2 area.
+ */
+#define jump_to_P2() \
+ do { \
+ unsigned long __dummy; \
+ __asm__ __volatile__( \
+ "mov.l 1f, %0\n\t" \
+ "or %1, %0\n\t" \
+ "jmp @%0\n\t" \
+ " nop\n\t" \
+ ".balign 4\n" \
+ "1: .long 2f\n" \
+ "2:" \
+ : "=&r" (__dummy) \
+ : "r" (0x20000000)); \
+ } while (0)
+
+/*
+ * Back to P1 area.
+ */
+#define back_to_P1() \
+ do { \
+ unsigned long __dummy; \
+ __asm__ __volatile__( \
+ "nop;nop;nop;nop;nop;nop;nop\n\t" \
+ "mov.l 1f, %0\n\t" \
+ "jmp @%0\n\t" \
+ " nop\n\t" \
+ ".balign 4\n" \
+ "1: .long 2f\n" \
+ "2:" \
+ : "=&r" (__dummy)); \
+ } while (0)
+
+#define CACHE_VALID 1
+#define CACHE_UPDATED 2
+
+static inline void cache_wback_all(void)
+{
+ unsigned long addr, data, i, j;
+
+ jump_to_P2();
+ for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++){
+ for (j = 0; j < CACHE_OC_NUM_WAYS; j++) {
+ addr = CACHE_OC_ADDRESS_ARRAY | (j << CACHE_OC_WAY_SHIFT)
+ | (i << CACHE_OC_ENTRY_SHIFT);
+ data = inl(addr);
+ if (data & CACHE_UPDATED) {
+ data &= ~CACHE_UPDATED;
+ outl(data, addr);
+ }
+ }
+ }
+ back_to_P1();
+}
+
+
+#define CACHE_ENABLE 0
+#define CACHE_DISABLE 1
+
+int cache_control(unsigned int cmd)
+{
+ unsigned long ccr;
+
+ jump_to_P2();
+ ccr = inl(CCR);
+
+ if (ccr & CCR_CACHE_ENABLE)
+ cache_wback_all();
+
+ if (cmd == CACHE_DISABLE)
+ outl(CCR_CACHE_STOP, CCR);
+ else
+ outl(CCR_CACHE_INIT, CCR);
+ back_to_P1();
+
+ return 0;
+}
--- /dev/null
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+PLATFORM_CPPFLAGS += -m4-nofpu
+PLATFORM_RELFLAGS += -ffixed-r13
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+
+int checkcpu(void)
+{
+ puts("CPU: SH4\n");
+ return 0;
+}
+
+int cpu_init (void)
+{
+ return 0;
+}
+
+int cleanup_before_linux (void)
+{
+ disable_interrupts();
+ return 0;
+}
+
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ disable_interrupts();
+ reset_cpu (0);
+ return 0;
+}
+
+void flush_cache (unsigned long addr, unsigned long size)
+{
+
+}
+
+void icache_enable (void)
+{
+ cache_control(0);
+}
+
+void icache_disable (void)
+{
+ cache_control(1);
+}
+
+int icache_status (void)
+{
+ return 0;
+}
+
+void dcache_enable (void)
+{
+}
+
+void dcache_disable (void)
+{
+}
+
+int dcache_status (void)
+{
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+int interrupt_init (void)
+{
+ return 0;
+}
+
+void enable_interrupts (void)
+{
+
+}
+
+int disable_interrupts (void){
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+ .text
+ .align 2
+
+ .global _start
+_start:
+ mov.l ._lowlevel_init, r0
+100: bsrf r0
+ nop
+
+ bsr 1f
+ nop
+1: sts pr, r5
+ mov.l ._reloc_dst, r4
+ add #(_start-1b), r5
+ mov.l ._reloc_dst_end, r6
+
+2: mov.l @r5+, r1
+ mov.l r1, @r4
+ add #4, r4
+ cmp/hs r6, r4
+ bf 2b
+
+ mov.l ._bss_start, r4
+ mov.l ._bss_end, r5
+ mov #0, r1
+
+3: mov.l r1, @r4 /* bss clear */
+ add #4, r4
+ cmp/hs r5, r4
+ bf 3b
+
+ mov.l ._gd_init, r13 /* global data */
+ mov.l ._stack_init, r15 /* stack */
+
+ mov.l ._sh_generic_init, r0
+ jsr @r0
+ nop
+
+loop:
+ bra loop
+
+ .align 2
+
+._lowlevel_init: .long (lowlevel_init - (100b + 4))
+._reloc_dst: .long reloc_dst
+._reloc_dst_end: .long reloc_dst_end
+._bss_start: .long bss_start
+._bss_end: .long bss_end
+._gd_init: .long (_start - CFG_GBL_DATA_SIZE)
+._stack_init: .long (_start - CFG_GBL_DATA_SIZE - CFG_MALLOC_LEN - 16)
+._sh_generic_init: .long sh_generic_init
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Nobobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#define TMU_MAX_COUNTER (~0UL)
+
+static void tmu_timer_start (unsigned int timer)
+{
+ if (timer > 2)
+ return;
+
+ *((volatile unsigned char *) TSTR) |= (1 << timer);
+}
+
+static void tmu_timer_stop (unsigned int timer)
+{
+ u8 val = *((volatile u8 *)TSTR);
+ if (timer > 2)
+ return;
+ *((volatile unsigned char *)TSTR) = val &~(1 << timer);
+}
+
+int timer_init (void)
+{
+ /* Divide clock by 4 */
+ *(volatile u16 *)TCR0 = 0;
+
+ tmu_timer_stop(0);
+ tmu_timer_start(0);
+ return 0;
+}
+
+/*
+ In theory we should return a true 64bit value (ie something that doesn't
+ overflow). However, we don't. Therefore if TMU runs at fastest rate of
+ 6.75 MHz this value will wrap after u-boot has been running for approx
+ 10 minutes.
+*/
+unsigned long long get_ticks (void)
+{
+ return (0 - *((volatile u32 *) TCNT0));
+}
+
+unsigned long get_timer (unsigned long base)
+{
+ return ((0 - *((volatile u32 *) TCNT0)) - base);
+}
+
+void set_timer (unsigned long t)
+{
+ *((volatile unsigned int *) TCNT0) = (0 - t);
+}
+
+void reset_timer (void)
+{
+ tmu_timer_stop(0);
+ set_timer (0);
+ tmu_timer_start(0);
+}
+
+void udelay (unsigned long usec)
+{
+ unsigned int start = get_timer (0);
+ unsigned int end = start + (usec * ((CFG_HZ + 500000) / 1000000));
+
+ while (get_timer (0) < end)
+ continue;
+}
+
+unsigned long get_tbclk (void)
+{
+ return CFG_HZ;
+}
--- /dev/null
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#define WDT_BASE WTCNT
+
+static unsigned char cnt_read (void){
+ return *((volatile unsigned char *)(WDT_BASE + 0x00));
+}
+
+static unsigned char csr_read (void){
+ return *((volatile unsigned char *)(WDT_BASE + 0x04));
+}
+
+static void cnt_write (unsigned char value){
+ while (csr_read() & (1 << 5)) {
+ /* delay */
+ }
+ *((volatile unsigned short *)(WDT_BASE + 0x00))
+ = ((unsigned short) value) | 0x5A00;
+}
+
+static void csr_write (unsigned char value){
+ *((volatile unsigned short *)(WDT_BASE + 0x04))
+ = ((unsigned short) value) | 0xA500;
+}
+
+
+int watchdog_init (void){ return 0; }
+
+void reset_cpu (unsigned long ignored)
+{
+ while(1);
+}
--- /dev/null
+
+U-Boot MARUBUN MR-SHPC-01 PCMCIA controller driver
+ Last update 21/11/2007 by Nobuhiro Iwamatsu
+
+========================================================================================
+
+0. What's this?
+ This driver supports MARUBUN MR-SHPC-01.
+ url: http://www.marubun.co.jp/product/semicon/devices/qgc18e0000002n2z.html
+ (Sorry Japanese only.)
+
+ This chip is used with SuperH well, and adopted by the
+ reference board.
+ ex. * MS7750SE01
+ * MS7722SE01
+ * other
+
+ This chip doesn't support CardBus.
+
+1. base source code
+ The code is based on sources from the Linux kernel
+ ( arch/sh/kernel/cf-enabler.c ).
+
+2. How to use
+ The options you have to specify in the config file are (with the
+ value for my board as an example):
+
+ * CONFIG_MARUBUN_PCCARD
+ If you want to use this device driver, should define CONFIG_MARUBUN_PCCARD.
+ ex. #define CONFIG_MARUBUN_PCCARD
+
+ * CONFIG_PCMCIA_SLOT_A
+ Most devices have only one slot. You should define CONFIG_PCMCIA_SLOT_A .
+ ex. #define CONFIG_PCMCIA_SLOT_A 1
+
+ * CFG_MARUBUN_MRSHPC
+ This is MR-SHPC-01 PCMCIA controler base address.
+ You should do the setting matched to your environment.
+ ex. #define CFG_MARUBUN_MRSHPC 0xb03fffe0
+ ( for MS7722SE01 environment )
+
+ * CFG_MARUBUN_MW1
+ This is MR-SHPC-01 memory window base address.
+ You should do the setting matched to your environment.
+ ex. #define CFG_MARUBUN_MW1 0xb0400000
+ ( for MS7722SE01 environment )
+
+ * CFG_MARUBUN_MW1
+ This is MR-SHPC-01 attribute window base address.
+ You should do the setting matched to your environment.
+ ex. #define CFG_MARUBUN_MW2 0xb0500000
+ ( for MS7722SE01 environment )
+
+ * CFG_MARUBUN_MW1
+ This is MR-SHPC-01 I/O window base address.
+ You should do the setting matched to your environment.
+ ex. #define CFG_MARUBUN_IO 0xb0600000
+ ( for MS7722SE01 environment )
+
+3. Other
+ * Check Compact Flash only.
+ * Maybe, NE2000 compatible NIC is sure to move.
+
+Copyright (c) 2007
+ Nobuhiro Iwamatsu <iwamatsu@nigaur.org>
--- /dev/null
+
+U-Boot for Renesas SuperH
+ Last update 08/10/2007 by Nobuhiro Iwamatsu
+
+================================================================================
+0. What's this?
+ This file contains status information for the port of U-Boot to the
+ Renesas SuperH series of CPUs.
+
+================================================================================
+1. Overview
+ SuperH has an original boot loader. However, source code is dirty, and
+ maintenance is not done.
+ To improve sharing and the maintenance of the code, Nobuhiro Iwamatsu
+ started the porting to u-boot in 2007.
+
+================================================================================
+2. Supported CPUs
+
+ 2.1. Renesas SH7750/SH7750R
+ 2.2. Renesas SH7722
+
+================================================================================
+3. Supported Boards
+
+ 3.1. Hitachi UL MS7750SE01/MS7750RSE01
+ Board specific code is in board/ms7750se
+ To use this board, type "make ms7750se_config".
+
+ 3.2. Hitachi UL MS7722SE01
+ Board specific code is in board/ms7722se
+ To use this board, type "make ms7722se_config".
+
+ ** README **
+ In SuperH, S-record and binary of made u-boot work on the memory.
+ When u-boot is written in the flash, it is necessary to change the
+ address by using 'objcopy'.
+ ex) shX-linux-objcopy -Ibinary -Osrec u-boot.bin u-boot.flash.srec
+
+================================================================================
+4. Compiler
+ You can use the following of u-boot to compile.
+ - SuperH Linux Open site
+ http://www.superh-linux.org/
+ - KPIT GNU tools
+ http://www.kpitgnutools.com/
+
+================================================================================
+5. Future
+ I plan to support the following CPUs and boards.
+ 5.1. CPUs
+ - SH7710/SH7712 (SH3)
+ - SH7780(SH4)
+ - SH7785(SH4)
+
+ 5.2. Boards
+ - Many boards ;-)
+
+================================================================================
+Copyright (c) 2007
+ Nobuhiro Iwamatsu <iwamatsu@nigaur.org>
COBJS-y += ds1621.o
COBJS-y += ds1722.o
COBJS-y += ds1775.o
+COBJS-y += lm73.o
COBJS-y += lm75.o
COBJS-y += lm81.o
#include <i2c.h>
#include <dtt.h>
-#define DTT_I2C_DEV_CODE 0x49 /* Dallas Semi's DS1775 device code */
+#define DTT_I2C_DEV_CODE CFG_I2C_DTT_ADDR /* Dallas Semi's DS1775 device code */
int dtt_read(int sensor, int reg)
{
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Larry Johnson, lrj@acm.org
+ *
+ * based on dtt/lm75.c which is ...
+ *
+ * (C) Copyright 2001
+ * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * National Semiconductor LM73 Temperature Sensor
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_DTT_LM73
+#if !defined(CFG_EEPROM_PAGE_WRITE_ENABLE) || \
+ (CFG_EEPROM_PAGE_WRITE_BITS < 1)
+# error "CFG_EEPROM_PAGE_WRITE_ENABLE must be defined and CFG_EEPROM_PAGE_WRITE_BITS must be greater than 1 to use CONFIG_DTT_LM73"
+#endif
+
+#include <i2c.h>
+#include <dtt.h>
+
+/*
+ * Device code
+ */
+#define DTT_I2C_DEV_CODE 0x48 /* National Semi's LM73 device */
+
+int dtt_read(int sensor, int reg)
+{
+ int dlen;
+ uchar data[2];
+
+ /*
+ * Validate 'reg' param and get register size.
+ */
+ switch (reg) {
+ case DTT_CONFIG:
+ case DTT_CONTROL:
+ dlen = 1;
+ break;
+ case DTT_READ_TEMP:
+ case DTT_TEMP_HIGH:
+ case DTT_TEMP_LOW:
+ case DTT_ID:
+ dlen = 2;
+ break;
+ default:
+ return -1;
+ }
+ /*
+ * Calculate sensor address and register.
+ */
+ sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); /* calculate LM73 addr */
+ /*
+ * Now try to read the register.
+ */
+ if (i2c_read(sensor, reg, 1, data, dlen) != 0)
+ return -1;
+ /*
+ * Handle 2 byte result.
+ */
+ if (2 == dlen)
+ return ((int)((short)data[1] + (((short)data[0]) << 8)));
+
+ return (int)data[0];
+} /* dtt_read() */
+
+int dtt_write(int sensor, int reg, int val)
+{
+ int dlen;
+ uchar data[2];
+
+ /*
+ * Validate 'reg' param and handle register size
+ */
+ switch (reg) {
+ case DTT_CONFIG:
+ case DTT_CONTROL:
+ dlen = 1;
+ data[0] = (char)(val & 0xff);
+ break;
+ case DTT_TEMP_HIGH:
+ case DTT_TEMP_LOW:
+ dlen = 2;
+ data[0] = (char)((val >> 8) & 0xff); /* MSB first */
+ data[1] = (char)(val & 0xff);
+ break;
+ default:
+ return -1;
+ }
+ /*
+ * Calculate sensor address and register.
+ */
+ sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); /* calculate LM73 addr */
+ /*
+ * Write value to register.
+ */
+ return i2c_write(sensor, reg, 1, data, dlen) != 0;
+} /* dtt_write() */
+
+static int _dtt_init(int sensor)
+{
+ int val;
+
+ /*
+ * Validate the Identification register
+ */
+ if (0x0190 != dtt_read(sensor, DTT_ID))
+ return 1;
+ /*
+ * Setup THIGH (upper-limit) and TLOW (lower-limit) registers
+ */
+ val = CFG_DTT_MAX_TEMP << 7;
+ if (dtt_write(sensor, DTT_TEMP_HIGH, val))
+ return 1;
+
+ val = CFG_DTT_MIN_TEMP << 7;
+ if (dtt_write(sensor, DTT_TEMP_LOW, val))
+ return 1;
+ /*
+ * Setup configuraton register
+ */
+ /* config = alert active low, disabled, and reset */
+ val = 0x64;
+ if (dtt_write(sensor, DTT_CONFIG, val))
+ return 1;
+ /*
+ * Setup control/status register
+ */
+ /* control = temp resolution 0.25C */
+ val = 0x00;
+ if (dtt_write(sensor, DTT_CONTROL, val))
+ return 1;
+
+ dtt_read(sensor, DTT_CONTROL); /* clear temperature flags */
+ return 0;
+} /* _dtt_init() */
+
+int dtt_init(void)
+{
+ int i;
+ unsigned char sensors[] = CONFIG_DTT_SENSORS;
+ const char *const header = "DTT: ";
+
+ for (i = 0; i < sizeof(sensors); i++) {
+ if (_dtt_init(sensors[i]) != 0)
+ printf("%s%d FAILED INIT\n", header, i + 1);
+ else
+ printf("%s%d is %i C\n", header, i + 1,
+ dtt_get_temp(sensors[i]));
+ }
+ return 0;
+} /* dtt_init() */
+
+int dtt_get_temp(int sensor)
+{
+ return (dtt_read(sensor, DTT_READ_TEMP) + 0x0040) >> 7;
+} /* dtt_get_temp() */
+
+#endif /* CONFIG_DTT_LM73 */
COBJS-y += cfi_flash.o
COBJS-y += dataflash.o
COBJS-y += mw_eeprom.o
+COBJS-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
#ifdef CFG_FLASH_CFI_DRIVER
/*
- * This file implements a Common Flash Interface (CFI) driver for U-Boot.
- * The width of the port and the width of the chips are determined at initialization.
- * These widths are used to calculate the address for access CFI data structures.
+ * This file implements a Common Flash Interface (CFI) driver for
+ * U-Boot.
+ *
+ * The width of the port and the width of the chips are determined at
+ * initialization. These widths are used to calculate the address for
+ * access CFI data structures.
*
* References
* JEDEC Standard JESD68 - Common Flash Interface (CFI)
* AMD/Spansion Application Note: Migration from Single-byte to Three-byte
* Device IDs, Publication Number 25538 Revision A, November 8, 2001
*
- * define CFG_WRITE_SWAPPED_DATA, if you have to swap the Bytes between
+ * Define CFG_WRITE_SWAPPED_DATA, if you have to swap the Bytes between
* reading and writing ... (yes there is such a Hardware).
*/
#define AMD_STATUS_TOGGLE 0x40
#define AMD_STATUS_ERROR 0x20
-#define AMD_ADDR_ERASE_START ((info->portwidth == FLASH_CFI_8BIT) ? 0xAAA : 0x555)
-#define AMD_ADDR_START ((info->portwidth == FLASH_CFI_8BIT) ? 0xAAA : 0x555)
-#define AMD_ADDR_ACK ((info->portwidth == FLASH_CFI_8BIT) ? 0x555 : 0x2AA)
-
#define FLASH_OFFSET_MANUFACTURER_ID 0x00
#define FLASH_OFFSET_DEVICE_ID 0x01
#define FLASH_OFFSET_DEVICE_ID2 0x0E
#define FLASH_OFFSET_CFI_ALT 0x555
#define FLASH_OFFSET_CFI_RESP 0x10
#define FLASH_OFFSET_PRIMARY_VENDOR 0x13
-#define FLASH_OFFSET_EXT_QUERY_T_P_ADDR 0x15 /* extended query table primary addr */
+/* extended query table primary address */
+#define FLASH_OFFSET_EXT_QUERY_T_P_ADDR 0x15
#define FLASH_OFFSET_WTOUT 0x1F
#define FLASH_OFFSET_WBTOUT 0x20
#define FLASH_OFFSET_ETOUT 0x21
unsigned long long ll;
} cfiword_t;
-typedef union {
- volatile unsigned char *cp;
- volatile unsigned short *wp;
- volatile unsigned long *lp;
- volatile unsigned long long *llp;
-} cfiptr_t;
-
#define NUM_ERASE_REGIONS 4 /* max. number of erase regions */
-static uint flash_offset_cfi[2]={FLASH_OFFSET_CFI,FLASH_OFFSET_CFI_ALT};
+static uint flash_offset_cfi[2] = { FLASH_OFFSET_CFI, FLASH_OFFSET_CFI_ALT };
/* use CFG_MAX_FLASH_BANKS_DETECT if defined */
#ifdef CFG_MAX_FLASH_BANKS_DETECT
#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
#endif
+typedef unsigned long flash_sect_t;
+
+/* CFI standard query structure */
+struct cfi_qry {
+ u8 qry[3];
+ u16 p_id;
+ u16 p_adr;
+ u16 a_id;
+ u16 a_adr;
+ u8 vcc_min;
+ u8 vcc_max;
+ u8 vpp_min;
+ u8 vpp_max;
+ u8 word_write_timeout_typ;
+ u8 buf_write_timeout_typ;
+ u8 block_erase_timeout_typ;
+ u8 chip_erase_timeout_typ;
+ u8 word_write_timeout_max;
+ u8 buf_write_timeout_max;
+ u8 block_erase_timeout_max;
+ u8 chip_erase_timeout_max;
+ u8 dev_size;
+ u16 interface_desc;
+ u16 max_buf_write_size;
+ u8 num_erase_regions;
+ u32 erase_region_info[NUM_ERASE_REGIONS];
+} __attribute__((packed));
+
+struct cfi_pri_hdr {
+ u8 pri[3];
+ u8 major_version;
+ u8 minor_version;
+} __attribute__((packed));
+
+static void flash_write8(u8 value, void *addr)
+{
+ __raw_writeb(value, addr);
+}
+
+static void flash_write16(u16 value, void *addr)
+{
+ __raw_writew(value, addr);
+}
+
+static void flash_write32(u32 value, void *addr)
+{
+ __raw_writel(value, addr);
+}
+
+static void flash_write64(u64 value, void *addr)
+{
+ /* No architectures currently implement __raw_writeq() */
+ *(volatile u64 *)addr = value;
+}
+
+static u8 flash_read8(void *addr)
+{
+ return __raw_readb(addr);
+}
+
+static u16 flash_read16(void *addr)
+{
+ return __raw_readw(addr);
+}
+
+static u32 flash_read32(void *addr)
+{
+ return __raw_readl(addr);
+}
+
+static u64 flash_read64(void *addr)
+{
+ /* No architectures currently implement __raw_readq() */
+ return *(volatile u64 *)addr;
+}
/*-----------------------------------------------------------------------
- * Functions
*/
+#if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
+static flash_info_t *flash_get_info(ulong base)
+{
+ int i;
+ flash_info_t * info = 0;
-typedef unsigned long flash_sect_t;
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+ info = & flash_info[i];
+ if (info->size && info->start[0] <= base &&
+ base <= info->start[0] + info->size - 1)
+ break;
+ }
-static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c);
-static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf);
-static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
-static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect);
-static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
-static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
-static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
-static void flash_read_jedec_ids (flash_info_t * info);
-static int flash_detect_cfi (flash_info_t * info);
-static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword);
-static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
- ulong tout, char *prompt);
-ulong flash_get_size (ulong base, int banknum);
-#if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
-static flash_info_t *flash_get_info(ulong base);
-#endif
-#ifdef CFG_FLASH_USE_BUFFER_WRITE
-static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, int len);
+ return i == CFG_MAX_FLASH_BANKS ? 0 : info;
+}
#endif
+unsigned long flash_sector_size(flash_info_t *info, flash_sect_t sect)
+{
+ if (sect != (info->sector_count - 1))
+ return info->start[sect + 1] - info->start[sect];
+ else
+ return info->start[0] + info->size - info->start[sect];
+}
+
/*-----------------------------------------------------------------------
* create an address based on the offset and the port width
*/
-inline uchar *flash_make_addr (flash_info_t * info, flash_sect_t sect, uint offset)
+static inline void *
+flash_map (flash_info_t * info, flash_sect_t sect, uint offset)
+{
+ unsigned int byte_offset = offset * info->portwidth;
+
+ return map_physmem(info->start[sect] + byte_offset,
+ flash_sector_size(info, sect) - byte_offset,
+ MAP_NOCACHE);
+}
+
+static inline void flash_unmap(flash_info_t *info, flash_sect_t sect,
+ unsigned int offset, void *addr)
+{
+ unsigned int byte_offset = offset * info->portwidth;
+
+ unmap_physmem(addr, flash_sector_size(info, sect) - byte_offset);
+}
+
+/*-----------------------------------------------------------------------
+ * make a proper sized command based on the port and chip widths
+ */
+static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf)
{
- return ((uchar *) (info->start[sect] + (offset * info->portwidth)));
+ int i;
+ uchar *cp = (uchar *) cmdbuf;
+
+#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA)
+ for (i = info->portwidth; i > 0; i--)
+#else
+ for (i = 1; i <= info->portwidth; i++)
+#endif
+ *cp++ = (i & (info->chipwidth - 1)) ? '\0' : cmd;
}
#ifdef DEBUG
/*-----------------------------------------------------------------------
* Debug support
*/
-void print_longlong (char *str, unsigned long long data)
+static void print_longlong (char *str, unsigned long long data)
{
int i;
char *cp;
for (i = 0; i < 8; i++)
sprintf (&str[i * 2], "%2.2x", *cp++);
}
-static void flash_printqry (flash_info_t * info, flash_sect_t sect)
+
+static void flash_printqry (struct cfi_qry *qry)
{
- cfiptr_t cptr;
+ u8 *p = (u8 *)qry;
int x, y;
- for (x = 0; x < 0x40; x += 16U / info->portwidth) {
- cptr.cp =
- flash_make_addr (info, sect,
- x + FLASH_OFFSET_CFI_RESP);
- debug ("%p : ", cptr.cp);
+ for (x = 0; x < sizeof(struct cfi_qry); x += 16) {
+ debug("%02x : ", x);
+ for (y = 0; y < 16; y++)
+ debug("%2.2x ", p[x + y]);
+ debug(" ");
for (y = 0; y < 16; y++) {
- debug ("%2.2x ", cptr.cp[y]);
- }
- debug (" ");
- for (y = 0; y < 16; y++) {
- if (cptr.cp[y] >= 0x20 && cptr.cp[y] <= 0x7e) {
- debug ("%c", cptr.cp[y]);
- } else {
- debug (".");
- }
+ unsigned char c = p[x + y];
+ if (c >= 0x20 && c <= 0x7e)
+ debug("%c", c);
+ else
+ debug(".");
}
- debug ("\n");
+ debug("\n");
}
}
#endif
/*-----------------------------------------------------------------------
* read a character at a port width address
*/
-inline uchar flash_read_uchar (flash_info_t * info, uint offset)
+static inline uchar flash_read_uchar (flash_info_t * info, uint offset)
{
uchar *cp;
+ uchar retval;
- cp = flash_make_addr (info, 0, offset);
-#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA)
- return (cp[0]);
-#else
- return (cp[info->portwidth - 1]);
-#endif
-}
-
-/*-----------------------------------------------------------------------
- * read a short word by swapping for ppc format.
- */
-ushort flash_read_ushort (flash_info_t * info, flash_sect_t sect, uint offset)
-{
- uchar *addr;
- ushort retval;
-
-#ifdef DEBUG
- int x;
-#endif
- addr = flash_make_addr (info, sect, offset);
-
-#ifdef DEBUG
- debug ("ushort addr is at %p info->portwidth = %d\n", addr,
- info->portwidth);
- for (x = 0; x < 2 * info->portwidth; x++) {
- debug ("addr[%x] = 0x%x\n", x, addr[x]);
- }
-#endif
+ cp = flash_map (info, 0, offset);
#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA)
- retval = ((addr[(info->portwidth)] << 8) | addr[0]);
+ retval = flash_read8(cp);
#else
- retval = ((addr[(2 * info->portwidth) - 1] << 8) |
- addr[info->portwidth - 1]);
+ retval = flash_read8(cp + info->portwidth - 1);
#endif
-
- debug ("retval = 0x%x\n", retval);
+ flash_unmap (info, 0, offset, cp);
return retval;
}
* read a long word by picking the least significant byte of each maximum
* port size word. Swap for ppc format.
*/
-ulong flash_read_long (flash_info_t * info, flash_sect_t sect, uint offset)
+static ulong flash_read_long (flash_info_t * info, flash_sect_t sect,
+ uint offset)
{
uchar *addr;
ulong retval;
#ifdef DEBUG
int x;
#endif
- addr = flash_make_addr (info, sect, offset);
+ addr = flash_map (info, sect, offset);
#ifdef DEBUG
debug ("long addr is at %p info->portwidth = %d\n", addr,
info->portwidth);
for (x = 0; x < 4 * info->portwidth; x++) {
- debug ("addr[%x] = 0x%x\n", x, addr[x]);
+ debug ("addr[%x] = 0x%x\n", x, flash_read8(addr + x));
}
#endif
#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA)
- retval = (addr[0] << 16) | (addr[(info->portwidth)] << 24) |
- (addr[(2 * info->portwidth)]) | (addr[(3 * info->portwidth)] << 8);
+ retval = ((flash_read8(addr) << 16) |
+ (flash_read8(addr + info->portwidth) << 24) |
+ (flash_read8(addr + 2 * info->portwidth)) |
+ (flash_read8(addr + 3 * info->portwidth) << 8));
#else
- retval = (addr[(2 * info->portwidth) - 1] << 24) |
- (addr[(info->portwidth) - 1] << 16) |
- (addr[(4 * info->portwidth) - 1] << 8) |
- addr[(3 * info->portwidth) - 1];
+ retval = ((flash_read8(addr + 2 * info->portwidth - 1) << 24) |
+ (flash_read8(addr + info->portwidth - 1) << 16) |
+ (flash_read8(addr + 4 * info->portwidth - 1) << 8) |
+ (flash_read8(addr + 3 * info->portwidth - 1)));
#endif
+ flash_unmap(info, sect, offset, addr);
+
return retval;
}
-
-/*-----------------------------------------------------------------------
+/*
+ * Write a proper sized command to the correct address
*/
-unsigned long flash_init (void)
+static void flash_write_cmd (flash_info_t * info, flash_sect_t sect,
+ uint offset, uchar cmd)
{
- unsigned long size = 0;
- int i;
-
-#ifdef CFG_FLASH_PROTECTION
- char *s = getenv("unlock");
-#endif
-
- /* Init: no FLASHes known */
- for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- size += flash_info[i].size = flash_get_size (bank_base[i], i);
- if (flash_info[i].flash_id == FLASH_UNKNOWN) {
-#ifndef CFG_FLASH_QUIET_TEST
- printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
- i+1, flash_info[i].size, flash_info[i].size << 20);
-#endif /* CFG_FLASH_QUIET_TEST */
- }
-#ifdef CFG_FLASH_PROTECTION
- else if ((s != NULL) && (strcmp(s, "yes") == 0)) {
- /*
- * Only the U-Boot image and it's environment is protected,
- * all other sectors are unprotected (unlocked) if flash
- * hardware protection is used (CFG_FLASH_PROTECTION) and
- * the environment variable "unlock" is set to "yes".
- */
- if (flash_info[i].legacy_unlock) {
- int k;
- /*
- * Disable legacy_unlock temporarily, since
- * flash_real_protect would relock all other sectors
- * again otherwise.
- */
- flash_info[i].legacy_unlock = 0;
+ void *addr;
+ cfiword_t cword;
- /*
- * Legacy unlocking (e.g. Intel J3) -> unlock only one
- * sector. This will unlock all sectors.
- */
- flash_real_protect (&flash_info[i], 0, 0);
+ addr = flash_map (info, sect, offset);
+ flash_make_cmd (info, cmd, &cword);
+ switch (info->portwidth) {
+ case FLASH_CFI_8BIT:
+ debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr, cmd,
+ cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
+ flash_write8(cword.c, addr);
+ break;
+ case FLASH_CFI_16BIT:
+ debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr,
+ cmd, cword.w,
+ info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
+ flash_write16(cword.w, addr);
+ break;
+ case FLASH_CFI_32BIT:
+ debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr,
+ cmd, cword.l,
+ info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
+ flash_write32(cword.l, addr);
+ break;
+ case FLASH_CFI_64BIT:
+#ifdef DEBUG
+ {
+ char str[20];
- flash_info[i].legacy_unlock = 1;
+ print_longlong (str, cword.ll);
- /*
- * Manually mark other sectors as unlocked (unprotected)
- */
- for (k = 1; k < flash_info[i].sector_count; k++)
- flash_info[i].protect[k] = 0;
- } else {
- /*
- * No legancy unlocking -> unlock all sectors
- */
- flash_protect (FLAG_PROTECT_CLEAR,
- flash_info[i].start[0],
- flash_info[i].start[0] + flash_info[i].size - 1,
- &flash_info[i]);
- }
+ debug ("fwrite addr %p cmd %x %s 64 bit x %d bit\n",
+ addr, cmd, str,
+ info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
}
-#endif /* CFG_FLASH_PROTECTION */
+#endif
+ flash_write64(cword.ll, addr);
+ break;
}
- /* Monitor protection ON by default */
-#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
- flash_protect (FLAG_PROTECT_SET,
- CFG_MONITOR_BASE,
- CFG_MONITOR_BASE + monitor_flash_len - 1,
- flash_get_info(CFG_MONITOR_BASE));
-#endif
+ /* Ensure all the instructions are fully finished */
+ sync();
- /* Environment protection ON by default */
-#ifdef CFG_ENV_IS_IN_FLASH
- flash_protect (FLAG_PROTECT_SET,
- CFG_ENV_ADDR,
- CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
- flash_get_info(CFG_ENV_ADDR));
-#endif
+ flash_unmap(info, sect, offset, addr);
+}
- /* Redundant environment protection ON by default */
-#ifdef CFG_ENV_ADDR_REDUND
- flash_protect (FLAG_PROTECT_SET,
- CFG_ENV_ADDR_REDUND,
- CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
- flash_get_info(CFG_ENV_ADDR_REDUND));
-#endif
- return (size);
+static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect)
+{
+ flash_write_cmd (info, sect, info->addr_unlock1, AMD_CMD_UNLOCK_START);
+ flash_write_cmd (info, sect, info->addr_unlock2, AMD_CMD_UNLOCK_ACK);
}
/*-----------------------------------------------------------------------
*/
-#if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
-static flash_info_t *flash_get_info(ulong base)
+static int flash_isequal (flash_info_t * info, flash_sect_t sect,
+ uint offset, uchar cmd)
{
- int i;
- flash_info_t * info = 0;
+ void *addr;
+ cfiword_t cword;
+ int retval;
- for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
- info = & flash_info[i];
- if (info->size && info->start[0] <= base &&
- base <= info->start[0] + info->size - 1)
- break;
+ addr = flash_map (info, sect, offset);
+ flash_make_cmd (info, cmd, &cword);
+
+ debug ("is= cmd %x(%c) addr %p ", cmd, cmd, addr);
+ switch (info->portwidth) {
+ case FLASH_CFI_8BIT:
+ debug ("is= %x %x\n", flash_read8(addr), cword.c);
+ retval = (flash_read8(addr) == cword.c);
+ break;
+ case FLASH_CFI_16BIT:
+ debug ("is= %4.4x %4.4x\n", flash_read16(addr), cword.w);
+ retval = (flash_read16(addr) == cword.w);
+ break;
+ case FLASH_CFI_32BIT:
+ debug ("is= %8.8lx %8.8lx\n", flash_read32(addr), cword.l);
+ retval = (flash_read32(addr) == cword.l);
+ break;
+ case FLASH_CFI_64BIT:
+#ifdef DEBUG
+ {
+ char str1[20];
+ char str2[20];
+
+ print_longlong (str1, flash_read64(addr));
+ print_longlong (str2, cword.ll);
+ debug ("is= %s %s\n", str1, str2);
+ }
+#endif
+ retval = (flash_read64(addr) == cword.ll);
+ break;
+ default:
+ retval = 0;
+ break;
}
+ flash_unmap(info, sect, offset, addr);
- return i == CFG_MAX_FLASH_BANKS ? 0 : info;
+ return retval;
}
-#endif
/*-----------------------------------------------------------------------
*/
-int flash_erase (flash_info_t * info, int s_first, int s_last)
+static int flash_isset (flash_info_t * info, flash_sect_t sect,
+ uint offset, uchar cmd)
{
- int rcode = 0;
- int prot;
- flash_sect_t sect;
+ void *addr;
+ cfiword_t cword;
+ int retval;
- if (info->flash_id != FLASH_MAN_CFI) {
- puts ("Can't erase unknown flash type - aborted\n");
- return 1;
- }
- if ((s_first < 0) || (s_first > s_last)) {
- puts ("- no sectors to erase\n");
- return 1;
+ addr = flash_map (info, sect, offset);
+ flash_make_cmd (info, cmd, &cword);
+ switch (info->portwidth) {
+ case FLASH_CFI_8BIT:
+ retval = ((flash_read8(addr) & cword.c) == cword.c);
+ break;
+ case FLASH_CFI_16BIT:
+ retval = ((flash_read16(addr) & cword.w) == cword.w);
+ break;
+ case FLASH_CFI_32BIT:
+ retval = ((flash_read32(addr) & cword.l) == cword.l);
+ break;
+ case FLASH_CFI_64BIT:
+ retval = ((flash_read64(addr) & cword.ll) == cword.ll);
+ break;
+ default:
+ retval = 0;
+ break;
}
+ flash_unmap(info, sect, offset, addr);
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
+ return retval;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_toggle (flash_info_t * info, flash_sect_t sect,
+ uint offset, uchar cmd)
+{
+ void *addr;
+ cfiword_t cword;
+ int retval;
+
+ addr = flash_map (info, sect, offset);
+ flash_make_cmd (info, cmd, &cword);
+ switch (info->portwidth) {
+ case FLASH_CFI_8BIT:
+ retval = ((flash_read8(addr) & cword.c) !=
+ (flash_read8(addr) & cword.c));
+ break;
+ case FLASH_CFI_16BIT:
+ retval = ((flash_read16(addr) & cword.w) !=
+ (flash_read16(addr) & cword.w));
+ break;
+ case FLASH_CFI_32BIT:
+ retval = ((flash_read32(addr) & cword.l) !=
+ (flash_read32(addr) & cword.l));
+ break;
+ case FLASH_CFI_64BIT:
+ retval = ((flash_read64(addr) & cword.ll) !=
+ (flash_read64(addr) & cword.ll));
+ break;
+ default:
+ retval = 0;
+ break;
+ }
+ flash_unmap(info, sect, offset, addr);
+
+ return retval;
+}
+
+/*
+ * flash_is_busy - check to see if the flash is busy
+ *
+ * This routine checks the status of the chip and returns true if the
+ * chip is busy.
+ */
+static int flash_is_busy (flash_info_t * info, flash_sect_t sect)
+{
+ int retval;
+
+ switch (info->vendor) {
+ case CFI_CMDSET_INTEL_STANDARD:
+ case CFI_CMDSET_INTEL_EXTENDED:
+ retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE);
+ break;
+ case CFI_CMDSET_AMD_STANDARD:
+ case CFI_CMDSET_AMD_EXTENDED:
+#ifdef CONFIG_FLASH_CFI_LEGACY
+ case CFI_CMDSET_AMD_LEGACY:
+#endif
+ retval = flash_toggle (info, sect, 0, AMD_STATUS_TOGGLE);
+ break;
+ default:
+ retval = 0;
+ }
+ debug ("flash_is_busy: %d\n", retval);
+ return retval;
+}
+
+/*-----------------------------------------------------------------------
+ * wait for XSR.7 to be set. Time out with an error if it does not.
+ * This routine does not set the flash to read-array mode.
+ */
+static int flash_status_check (flash_info_t * info, flash_sect_t sector,
+ ulong tout, char *prompt)
+{
+ ulong start;
+
+#if CFG_HZ != 1000
+ tout *= CFG_HZ/1000;
+#endif
+
+ /* Wait for command completion */
+ start = get_timer (0);
+ while (flash_is_busy (info, sector)) {
+ if (get_timer (start) > tout) {
+ printf ("Flash %s timeout at address %lx data %lx\n",
+ prompt, info->start[sector],
+ flash_read_long (info, sector, 0));
+ flash_write_cmd (info, sector, 0, info->cmd_reset);
+ return ERR_TIMOUT;
+ }
+ udelay (1); /* also triggers watchdog */
+ }
+ return ERR_OK;
+}
+
+/*-----------------------------------------------------------------------
+ * Wait for XSR.7 to be set, if it times out print an error, otherwise
+ * do a full status check.
+ *
+ * This routine sets the flash to read-array mode.
+ */
+static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
+ ulong tout, char *prompt)
+{
+ int retcode;
+
+ retcode = flash_status_check (info, sector, tout, prompt);
+ switch (info->vendor) {
+ case CFI_CMDSET_INTEL_EXTENDED:
+ case CFI_CMDSET_INTEL_STANDARD:
+ if ((retcode == ERR_OK)
+ && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) {
+ retcode = ERR_INVAL;
+ printf ("Flash %s error at address %lx\n", prompt,
+ info->start[sector]);
+ if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS |
+ FLASH_STATUS_PSLBS)) {
+ puts ("Command Sequence Error.\n");
+ } else if (flash_isset (info, sector, 0,
+ FLASH_STATUS_ECLBS)) {
+ puts ("Block Erase Error.\n");
+ retcode = ERR_NOT_ERASED;
+ } else if (flash_isset (info, sector, 0,
+ FLASH_STATUS_PSLBS)) {
+ puts ("Locking Error\n");
+ }
+ if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) {
+ puts ("Block locked.\n");
+ retcode = ERR_PROTECTED;
+ }
+ if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS))
+ puts ("Vpp Low Error.\n");
+ }
+ flash_write_cmd (info, sector, 0, info->cmd_reset);
+ break;
+ default:
+ break;
+ }
+ return retcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
+{
+#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA)
+ unsigned short w;
+ unsigned int l;
+ unsigned long long ll;
+#endif
+
+ switch (info->portwidth) {
+ case FLASH_CFI_8BIT:
+ cword->c = c;
+ break;
+ case FLASH_CFI_16BIT:
+#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA)
+ w = c;
+ w <<= 8;
+ cword->w = (cword->w >> 8) | w;
+#else
+ cword->w = (cword->w << 8) | c;
+#endif
+ break;
+ case FLASH_CFI_32BIT:
+#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA)
+ l = c;
+ l <<= 24;
+ cword->l = (cword->l >> 8) | l;
+#else
+ cword->l = (cword->l << 8) | c;
+#endif
+ break;
+ case FLASH_CFI_64BIT:
+#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA)
+ ll = c;
+ ll <<= 56;
+ cword->ll = (cword->ll >> 8) | ll;
+#else
+ cword->ll = (cword->ll << 8) | c;
+#endif
+ break;
+ }
+}
+
+/* loop through the sectors from the highest address when the passed
+ * address is greater or equal to the sector address we have a match
+ */
+static flash_sect_t find_sector (flash_info_t * info, ulong addr)
+{
+ flash_sect_t sector;
+
+ for (sector = info->sector_count - 1; sector >= 0; sector--) {
+ if (addr >= info->start[sector])
+ break;
+ }
+ return sector;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_write_cfiword (flash_info_t * info, ulong dest,
+ cfiword_t cword)
+{
+ void *dstaddr;
+ int flag;
+
+ dstaddr = map_physmem(dest, info->portwidth, MAP_NOCACHE);
+
+ /* Check if Flash is (sufficiently) erased */
+ switch (info->portwidth) {
+ case FLASH_CFI_8BIT:
+ flag = ((flash_read8(dstaddr) & cword.c) == cword.c);
+ break;
+ case FLASH_CFI_16BIT:
+ flag = ((flash_read16(dstaddr) & cword.w) == cword.w);
+ break;
+ case FLASH_CFI_32BIT:
+ flag = ((flash_read32(dstaddr) & cword.l) == cword.l);
+ break;
+ case FLASH_CFI_64BIT:
+ flag = ((flash_read64(dstaddr) & cword.ll) == cword.ll);
+ break;
+ default:
+ flag = 0;
+ break;
+ }
+ if (!flag) {
+ unmap_physmem(dstaddr, info->portwidth);
+ return ERR_NOT_ERASED;
+ }
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts ();
+
+ switch (info->vendor) {
+ case CFI_CMDSET_INTEL_EXTENDED:
+ case CFI_CMDSET_INTEL_STANDARD:
+ flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS);
+ flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE);
+ break;
+ case CFI_CMDSET_AMD_EXTENDED:
+ case CFI_CMDSET_AMD_STANDARD:
+#ifdef CONFIG_FLASH_CFI_LEGACY
+ case CFI_CMDSET_AMD_LEGACY:
+#endif
+ flash_unlock_seq (info, 0);
+ flash_write_cmd (info, 0, info->addr_unlock1, AMD_CMD_WRITE);
+ break;
+ }
+
+ switch (info->portwidth) {
+ case FLASH_CFI_8BIT:
+ flash_write8(cword.c, dstaddr);
+ break;
+ case FLASH_CFI_16BIT:
+ flash_write16(cword.w, dstaddr);
+ break;
+ case FLASH_CFI_32BIT:
+ flash_write32(cword.l, dstaddr);
+ break;
+ case FLASH_CFI_64BIT:
+ flash_write64(cword.ll, dstaddr);
+ break;
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts ();
+
+ unmap_physmem(dstaddr, info->portwidth);
+
+ return flash_full_status_check (info, find_sector (info, dest),
+ info->write_tout, "write");
+}
+
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+
+static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
+ int len)
+{
+ flash_sect_t sector;
+ int cnt;
+ int retcode;
+ void *src = cp;
+ void *dst = map_physmem(dest, len, MAP_NOCACHE);
+ void *dst2 = dst;
+ int flag = 0;
+
+ switch (info->portwidth) {
+ case FLASH_CFI_8BIT:
+ cnt = len;
+ break;
+ case FLASH_CFI_16BIT:
+ cnt = len >> 1;
+ break;
+ case FLASH_CFI_32BIT:
+ cnt = len >> 2;
+ break;
+ case FLASH_CFI_64BIT:
+ cnt = len >> 3;
+ break;
+ default:
+ retcode = ERR_INVAL;
+ goto out_unmap;
+ }
+
+ while ((cnt-- > 0) && (flag == 0)) {
+ switch (info->portwidth) {
+ case FLASH_CFI_8BIT:
+ flag = ((flash_read8(dst2) & flash_read8(src)) ==
+ flash_read8(src));
+ src += 1, dst2 += 1;
+ break;
+ case FLASH_CFI_16BIT:
+ flag = ((flash_read16(dst2) & flash_read16(src)) ==
+ flash_read16(src));
+ src += 2, dst2 += 2;
+ break;
+ case FLASH_CFI_32BIT:
+ flag = ((flash_read32(dst2) & flash_read32(src)) ==
+ flash_read32(src));
+ src += 4, dst2 += 4;
+ break;
+ case FLASH_CFI_64BIT:
+ flag = ((flash_read64(dst2) & flash_read64(src)) ==
+ flash_read64(src));
+ src += 8, dst2 += 8;
+ break;
+ }
+ }
+ if (!flag) {
+ retcode = ERR_NOT_ERASED;
+ goto out_unmap;
+ }
+
+ src = cp;
+ sector = find_sector (info, dest);
+
+ switch (info->vendor) {
+ case CFI_CMDSET_INTEL_STANDARD:
+ case CFI_CMDSET_INTEL_EXTENDED:
+ flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+ flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
+ retcode = flash_status_check (info, sector,
+ info->buffer_write_tout,
+ "write to buffer");
+ if (retcode == ERR_OK) {
+ /* reduce the number of loops by the width of
+ * the port */
+ switch (info->portwidth) {
+ case FLASH_CFI_8BIT:
+ cnt = len;
+ break;
+ case FLASH_CFI_16BIT:
+ cnt = len >> 1;
+ break;
+ case FLASH_CFI_32BIT:
+ cnt = len >> 2;
+ break;
+ case FLASH_CFI_64BIT:
+ cnt = len >> 3;
+ break;
+ default:
+ retcode = ERR_INVAL;
+ goto out_unmap;
+ }
+ flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
+ while (cnt-- > 0) {
+ switch (info->portwidth) {
+ case FLASH_CFI_8BIT:
+ flash_write8(flash_read8(src), dst);
+ src += 1, dst += 1;
+ break;
+ case FLASH_CFI_16BIT:
+ flash_write16(flash_read16(src), dst);
+ src += 2, dst += 2;
+ break;
+ case FLASH_CFI_32BIT:
+ flash_write32(flash_read32(src), dst);
+ src += 4, dst += 4;
+ break;
+ case FLASH_CFI_64BIT:
+ flash_write64(flash_read64(src), dst);
+ src += 8, dst += 8;
+ break;
+ default:
+ retcode = ERR_INVAL;
+ goto out_unmap;
+ }
+ }
+ flash_write_cmd (info, sector, 0,
+ FLASH_CMD_WRITE_BUFFER_CONFIRM);
+ retcode = flash_full_status_check (
+ info, sector, info->buffer_write_tout,
+ "buffer write");
+ }
+
+ break;
+
+ case CFI_CMDSET_AMD_STANDARD:
+ case CFI_CMDSET_AMD_EXTENDED:
+ flash_unlock_seq(info,0);
+ flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_TO_BUFFER);
+
+ switch (info->portwidth) {
+ case FLASH_CFI_8BIT:
+ cnt = len;
+ flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
+ while (cnt-- > 0) {
+ flash_write8(flash_read8(src), dst);
+ src += 1, dst += 1;
+ }
+ break;
+ case FLASH_CFI_16BIT:
+ cnt = len >> 1;
+ flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
+ while (cnt-- > 0) {
+ flash_write16(flash_read16(src), dst);
+ src += 2, dst += 2;
+ }
+ break;
+ case FLASH_CFI_32BIT:
+ cnt = len >> 2;
+ flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
+ while (cnt-- > 0) {
+ flash_write32(flash_read32(src), dst);
+ src += 4, dst += 4;
+ }
+ break;
+ case FLASH_CFI_64BIT:
+ cnt = len >> 3;
+ flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
+ while (cnt-- > 0) {
+ flash_write64(flash_read64(src), dst);
+ src += 8, dst += 8;
+ }
+ break;
+ default:
+ retcode = ERR_INVAL;
+ goto out_unmap;
+ }
+
+ flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_BUFFER_CONFIRM);
+ retcode = flash_full_status_check (info, sector,
+ info->buffer_write_tout,
+ "buffer write");
+ break;
+
+ default:
+ debug ("Unknown Command Set\n");
+ retcode = ERR_INVAL;
+ break;
+ }
+
+out_unmap:
+ unmap_physmem(dst, len);
+ return retcode;
+}
+#endif /* CFG_FLASH_USE_BUFFER_WRITE */
+
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+ int rcode = 0;
+ int prot;
+ flash_sect_t sect;
+
+ if (info->flash_id != FLASH_MAN_CFI) {
+ puts ("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+ if ((s_first < 0) || (s_first > s_last)) {
+ puts ("- no sectors to erase\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
} else {
putc ('\n');
}
switch (info->vendor) {
case CFI_CMDSET_INTEL_STANDARD:
case CFI_CMDSET_INTEL_EXTENDED:
- flash_write_cmd (info, sect, 0, FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd (info, sect, 0, FLASH_CMD_BLOCK_ERASE);
- flash_write_cmd (info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
+ flash_write_cmd (info, sect, 0,
+ FLASH_CMD_CLEAR_STATUS);
+ flash_write_cmd (info, sect, 0,
+ FLASH_CMD_BLOCK_ERASE);
+ flash_write_cmd (info, sect, 0,
+ FLASH_CMD_ERASE_CONFIRM);
break;
case CFI_CMDSET_AMD_STANDARD:
case CFI_CMDSET_AMD_EXTENDED:
flash_unlock_seq (info, sect);
- flash_write_cmd (info, sect, AMD_ADDR_ERASE_START,
- AMD_CMD_ERASE_START);
+ flash_write_cmd (info, sect,
+ info->addr_unlock1,
+ AMD_CMD_ERASE_START);
flash_unlock_seq (info, sect);
- flash_write_cmd (info, sect, 0, AMD_CMD_ERASE_SECTOR);
+ flash_write_cmd (info, sect, 0,
+ AMD_CMD_ERASE_SECTOR);
+ break;
+#ifdef CONFIG_FLASH_CFI_LEGACY
+ case CFI_CMDSET_AMD_LEGACY:
+ flash_unlock_seq (info, 0);
+ flash_write_cmd (info, 0, info->addr_unlock1,
+ AMD_CMD_ERASE_START);
+ flash_unlock_seq (info, 0);
+ flash_write_cmd (info, sect, 0,
+ AMD_CMD_ERASE_SECTOR);
break;
+#endif
default:
debug ("Unkown flash vendor %d\n",
info->vendor);
return;
}
- printf ("CFI conformant FLASH (%d x %d)",
+ printf ("%s FLASH (%d x %d)",
+ info->name,
(info->portwidth << 3), (info->chipwidth << 3));
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
+ if (info->size < 1024*1024)
+ printf (" Size: %ld kB in %d Sectors\n",
+ info->size >> 10, info->sector_count);
+ else
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
printf (" ");
switch (info->vendor) {
case CFI_CMDSET_INTEL_STANDARD:
case CFI_CMDSET_AMD_EXTENDED:
printf ("AMD Extended");
break;
+#ifdef CONFIG_FLASH_CFI_LEGACY
+ case CFI_CMDSET_AMD_LEGACY:
+ printf ("AMD Legacy");
+ break;
+#endif
default:
printf ("Unknown (%d)", info->vendor);
break;
info->erase_blk_tout,
info->write_tout);
if (info->buffer_size > 1) {
- printf (" Buffer write timeout: %ld ms, buffer size: %d bytes\n",
+ printf (" Buffer write timeout: %ld ms, "
+ "buffer size: %d bytes\n",
info->buffer_write_tout,
info->buffer_size);
}
/*
* Check if whole sector is erased
*/
- if (i != (info->sector_count - 1))
- size = info->start[i + 1] - info->start[i];
- else
- size = info->start[0] + info->size - info->start[i];
+ size = flash_sector_size(info, i);
erased = 1;
flash = (volatile unsigned long *) info->start[i];
size = size >> 2; /* divide by 4 for longword access */
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
ulong wp;
- ulong cp;
+ uchar *p;
int aln;
cfiword_t cword;
int i, rc;
#ifdef CFG_FLASH_USE_BUFFER_WRITE
int buffered_size;
#endif
- /* get lower aligned address */
/* get lower aligned address */
wp = (addr & ~(info->portwidth - 1));
/* handle unaligned start */
if ((aln = addr - wp) != 0) {
cword.l = 0;
- cp = wp;
- for (i = 0; i < aln; ++i, ++cp)
- flash_add_byte (info, &cword, (*(uchar *) cp));
+ p = map_physmem(wp, info->portwidth, MAP_NOCACHE);
+ for (i = 0; i < aln; ++i)
+ flash_add_byte (info, &cword, flash_read8(p + i));
for (; (i < info->portwidth) && (cnt > 0); i++) {
flash_add_byte (info, &cword, *src++);
cnt--;
- cp++;
}
- for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
- flash_add_byte (info, &cword, (*(uchar *) cp));
- if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
+ for (; (cnt == 0) && (i < info->portwidth); ++i)
+ flash_add_byte (info, &cword, flash_read8(p + i));
+
+ rc = flash_write_cfiword (info, wp, cword);
+ unmap_physmem(p, info->portwidth);
+ if (rc != 0)
return rc;
- wp = cp;
+
+ wp += i;
}
/* handle the aligned part */
* handle unaligned tail bytes
*/
cword.l = 0;
- for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) {
+ p = map_physmem(wp, info->portwidth, MAP_NOCACHE);
+ for (i = 0; (i < info->portwidth) && (cnt > 0); ++i) {
flash_add_byte (info, &cword, *src++);
--cnt;
}
- for (; i < info->portwidth; ++i, ++cp) {
- flash_add_byte (info, &cword, (*(uchar *) cp));
- }
+ for (; i < info->portwidth; ++i)
+ flash_add_byte (info, &cword, flash_read8(p + i));
+ unmap_physmem(p, info->portwidth);
return flash_write_cfiword (info, wp, cword);
}
else
flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
- if ((retcode =
- flash_full_status_check (info, sector, info->erase_blk_tout,
- prot ? "protect" : "unprotect")) == 0) {
-
- info->protect[sector] = prot;
-
- /*
- * On some of Intel's flash chips (marked via legacy_unlock)
- * unprotect unprotects all locking.
- */
- if ((prot == 0) && (info->legacy_unlock)) {
- flash_sect_t i;
-
- for (i = 0; i < info->sector_count; i++) {
- if (info->protect[i])
- flash_real_protect (info, i, 1);
- }
- }
- }
- return retcode;
-}
-
-/*-----------------------------------------------------------------------
- * flash_read_user_serial - read the OneTimeProgramming cells
- */
-void flash_read_user_serial (flash_info_t * info, void *buffer, int offset,
- int len)
-{
- uchar *src;
- uchar *dst;
-
- dst = buffer;
- src = flash_make_addr (info, 0, FLASH_OFFSET_USER_PROTECTION);
- flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
- memcpy (dst, src + offset, len);
- flash_write_cmd (info, 0, 0, info->cmd_reset);
-}
-
-/*
- * flash_read_factory_serial - read the device Id from the protection area
- */
-void flash_read_factory_serial (flash_info_t * info, void *buffer, int offset,
- int len)
-{
- uchar *src;
-
- src = flash_make_addr (info, 0, FLASH_OFFSET_INTEL_PROTECTION);
- flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
- memcpy (buffer, src + offset, len);
- flash_write_cmd (info, 0, 0, info->cmd_reset);
-}
-
-#endif /* CFG_FLASH_PROTECTION */
-
-/*
- * flash_is_busy - check to see if the flash is busy
- * This routine checks the status of the chip and returns true if the chip is busy
- */
-static int flash_is_busy (flash_info_t * info, flash_sect_t sect)
-{
- int retval;
-
- switch (info->vendor) {
- case CFI_CMDSET_INTEL_STANDARD:
- case CFI_CMDSET_INTEL_EXTENDED:
- retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE);
- break;
- case CFI_CMDSET_AMD_STANDARD:
- case CFI_CMDSET_AMD_EXTENDED:
- retval = flash_toggle (info, sect, 0, AMD_STATUS_TOGGLE);
- break;
- default:
- retval = 0;
- }
- debug ("flash_is_busy: %d\n", retval);
- return retval;
-}
-
-/*-----------------------------------------------------------------------
- * wait for XSR.7 to be set. Time out with an error if it does not.
- * This routine does not set the flash to read-array mode.
- */
-static int flash_status_check (flash_info_t * info, flash_sect_t sector,
- ulong tout, char *prompt)
-{
- ulong start;
-
-#if CFG_HZ != 1000
- tout *= CFG_HZ/1000;
-#endif
-
- /* Wait for command completion */
- start = get_timer (0);
- while (flash_is_busy (info, sector)) {
- if (get_timer (start) > tout) {
- printf ("Flash %s timeout at address %lx data %lx\n",
- prompt, info->start[sector],
- flash_read_long (info, sector, 0));
- flash_write_cmd (info, sector, 0, info->cmd_reset);
- return ERR_TIMOUT;
- }
- udelay (1); /* also triggers watchdog */
- }
- return ERR_OK;
-}
-
-/*-----------------------------------------------------------------------
- * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
- * This routine sets the flash to read-array mode.
- */
-static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
- ulong tout, char *prompt)
-{
- int retcode;
-
- retcode = flash_status_check (info, sector, tout, prompt);
- switch (info->vendor) {
- case CFI_CMDSET_INTEL_EXTENDED:
- case CFI_CMDSET_INTEL_STANDARD:
- if ((retcode == ERR_OK)
- && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) {
- retcode = ERR_INVAL;
- printf ("Flash %s error at address %lx\n", prompt,
- info->start[sector]);
- if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) {
- puts ("Command Sequence Error.\n");
- } else if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS)) {
- puts ("Block Erase Error.\n");
- retcode = ERR_NOT_ERASED;
- } else if (flash_isset (info, sector, 0, FLASH_STATUS_PSLBS)) {
- puts ("Locking Error\n");
- }
- if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) {
- puts ("Block locked.\n");
- retcode = ERR_PROTECTED;
+ if ((retcode =
+ flash_full_status_check (info, sector, info->erase_blk_tout,
+ prot ? "protect" : "unprotect")) == 0) {
+
+ info->protect[sector] = prot;
+
+ /*
+ * On some of Intel's flash chips (marked via legacy_unlock)
+ * unprotect unprotects all locking.
+ */
+ if ((prot == 0) && (info->legacy_unlock)) {
+ flash_sect_t i;
+
+ for (i = 0; i < info->sector_count; i++) {
+ if (info->protect[i])
+ flash_real_protect (info, i, 1);
}
- if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS))
- puts ("Vpp Low Error.\n");
}
- flash_write_cmd (info, sector, 0, info->cmd_reset);
- break;
- default:
- break;
}
return retcode;
}
/*-----------------------------------------------------------------------
+ * flash_read_user_serial - read the OneTimeProgramming cells
*/
-static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
+void flash_read_user_serial (flash_info_t * info, void *buffer, int offset,
+ int len)
{
-#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA)
- unsigned short w;
- unsigned int l;
- unsigned long long ll;
-#endif
+ uchar *src;
+ uchar *dst;
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- cword->c = c;
- break;
- case FLASH_CFI_16BIT:
-#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA)
- w = c;
- w <<= 8;
- cword->w = (cword->w >> 8) | w;
-#else
- cword->w = (cword->w << 8) | c;
-#endif
- break;
- case FLASH_CFI_32BIT:
-#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA)
- l = c;
- l <<= 24;
- cword->l = (cword->l >> 8) | l;
-#else
- cword->l = (cword->l << 8) | c;
-#endif
- break;
- case FLASH_CFI_64BIT:
-#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA)
- ll = c;
- ll <<= 56;
- cword->ll = (cword->ll >> 8) | ll;
-#else
- cword->ll = (cword->ll << 8) | c;
-#endif
- break;
- }
+ dst = buffer;
+ src = flash_map (info, 0, FLASH_OFFSET_USER_PROTECTION);
+ flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
+ memcpy (dst, src + offset, len);
+ flash_write_cmd (info, 0, 0, info->cmd_reset);
+ flash_unmap(info, 0, FLASH_OFFSET_USER_PROTECTION, src);
+}
+
+/*
+ * flash_read_factory_serial - read the device Id from the protection area
+ */
+void flash_read_factory_serial (flash_info_t * info, void *buffer, int offset,
+ int len)
+{
+ uchar *src;
+
+ src = flash_map (info, 0, FLASH_OFFSET_INTEL_PROTECTION);
+ flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
+ memcpy (buffer, src + offset, len);
+ flash_write_cmd (info, 0, 0, info->cmd_reset);
+ flash_unmap(info, 0, FLASH_OFFSET_INTEL_PROTECTION, src);
}
+#endif /* CFG_FLASH_PROTECTION */
/*-----------------------------------------------------------------------
- * make a proper sized command based on the port and chip widths
+ * Reverse the order of the erase regions in the CFI QRY structure.
+ * This is needed for chips that are either a) correctly detected as
+ * top-boot, or b) buggy.
*/
-static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf)
+static void cfi_reverse_geometry(struct cfi_qry *qry)
{
- int i;
- uchar *cp = (uchar *) cmdbuf;
+ unsigned int i, j;
+ u32 tmp;
-#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA)
- for (i = info->portwidth; i > 0; i--)
-#else
- for (i = 1; i <= info->portwidth; i++)
-#endif
- *cp++ = (i & (info->chipwidth - 1)) ? '\0' : cmd;
+ for (i = 0, j = qry->num_erase_regions - 1; i < j; i++, j--) {
+ tmp = qry->erase_region_info[i];
+ qry->erase_region_info[i] = qry->erase_region_info[j];
+ qry->erase_region_info[j] = tmp;
+ }
}
-/*
- * Write a proper sized command to the correct address
+/*-----------------------------------------------------------------------
+ * read jedec ids from device and set corresponding fields in info struct
+ *
+ * Note: assume cfi->vendor, cfi->portwidth and cfi->chipwidth are correct
+ *
*/
-static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
+static void cmdset_intel_read_jedec_ids(flash_info_t *info)
{
+ flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+ flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID);
+ udelay(1000); /* some flash are slow to respond */
+ info->manufacturer_id = flash_read_uchar (info,
+ FLASH_OFFSET_MANUFACTURER_ID);
+ info->device_id = flash_read_uchar (info,
+ FLASH_OFFSET_DEVICE_ID);
+ flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+}
- volatile cfiptr_t addr;
- cfiword_t cword;
-
- addr.cp = flash_make_addr (info, sect, offset);
- flash_make_cmd (info, cmd, &cword);
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr.cp, cmd,
- cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
- *addr.cp = cword.c;
- break;
- case FLASH_CFI_16BIT:
- debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr.wp,
- cmd, cword.w,
- info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
- *addr.wp = cword.w;
- break;
- case FLASH_CFI_32BIT:
- debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr.lp,
- cmd, cword.l,
- info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
- *addr.lp = cword.l;
- break;
- case FLASH_CFI_64BIT:
-#ifdef DEBUG
- {
- char str[20];
+static int cmdset_intel_init(flash_info_t *info, struct cfi_qry *qry)
+{
+ info->cmd_reset = FLASH_CMD_RESET;
- print_longlong (str, cword.ll);
+ cmdset_intel_read_jedec_ids(info);
+ flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI);
- debug ("fwrite addr %p cmd %x %s 64 bit x %d bit\n",
- addr.llp, cmd, str,
- info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
- }
-#endif
- *addr.llp = cword.ll;
- break;
+#ifdef CFG_FLASH_PROTECTION
+ /* read legacy lock/unlock bit from intel flash */
+ if (info->ext_addr) {
+ info->legacy_unlock = flash_read_uchar (info,
+ info->ext_addr + 5) & 0x08;
}
+#endif
- /* Ensure all the instructions are fully finished */
- sync();
+ return 0;
}
-static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect)
+static void cmdset_amd_read_jedec_ids(flash_info_t *info)
{
- flash_write_cmd (info, sect, AMD_ADDR_START, AMD_CMD_UNLOCK_START);
- flash_write_cmd (info, sect, AMD_ADDR_ACK, AMD_CMD_UNLOCK_ACK);
+ flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
+ flash_unlock_seq(info, 0);
+ flash_write_cmd(info, 0, info->addr_unlock1, FLASH_CMD_READ_ID);
+ udelay(1000); /* some flash are slow to respond */
+ info->manufacturer_id = flash_read_uchar (info,
+ FLASH_OFFSET_MANUFACTURER_ID);
+ info->device_id = flash_read_uchar (info,
+ FLASH_OFFSET_DEVICE_ID);
+ if (info->device_id == 0x7E) {
+ /* AMD 3-byte (expanded) device ids */
+ info->device_id2 = flash_read_uchar (info,
+ FLASH_OFFSET_DEVICE_ID2);
+ info->device_id2 <<= 8;
+ info->device_id2 |= flash_read_uchar (info,
+ FLASH_OFFSET_DEVICE_ID3);
+ }
+ flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
}
-/*-----------------------------------------------------------------------
- */
-static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
+static int cmdset_amd_init(flash_info_t *info, struct cfi_qry *qry)
{
- cfiptr_t cptr;
- cfiword_t cword;
- int retval;
+ info->cmd_reset = AMD_CMD_RESET;
- cptr.cp = flash_make_addr (info, sect, offset);
- flash_make_cmd (info, cmd, &cword);
+ cmdset_amd_read_jedec_ids(info);
+ flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI);
- debug ("is= cmd %x(%c) addr %p ", cmd, cmd, cptr.cp);
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- debug ("is= %x %x\n", cptr.cp[0], cword.c);
- retval = (cptr.cp[0] == cword.c);
- break;
- case FLASH_CFI_16BIT:
- debug ("is= %4.4x %4.4x\n", cptr.wp[0], cword.w);
- retval = (cptr.wp[0] == cword.w);
- break;
- case FLASH_CFI_32BIT:
- debug ("is= %8.8lx %8.8lx\n", cptr.lp[0], cword.l);
- retval = (cptr.lp[0] == cword.l);
- break;
- case FLASH_CFI_64BIT:
-#ifdef DEBUG
- {
- char str1[20];
- char str2[20];
+ return 0;
+}
- print_longlong (str1, cptr.llp[0]);
- print_longlong (str2, cword.ll);
- debug ("is= %s %s\n", str1, str2);
- }
-#endif
- retval = (cptr.llp[0] == cword.ll);
+#ifdef CONFIG_FLASH_CFI_LEGACY
+static void flash_read_jedec_ids (flash_info_t * info)
+{
+ info->manufacturer_id = 0;
+ info->device_id = 0;
+ info->device_id2 = 0;
+
+ switch (info->vendor) {
+ case CFI_CMDSET_INTEL_STANDARD:
+ case CFI_CMDSET_INTEL_EXTENDED:
+ flash_read_jedec_ids_intel(info);
+ break;
+ case CFI_CMDSET_AMD_STANDARD:
+ case CFI_CMDSET_AMD_EXTENDED:
+ flash_read_jedec_ids_amd(info);
break;
default:
- retval = 0;
break;
}
- return retval;
}
/*-----------------------------------------------------------------------
+ * Call board code to request info about non-CFI flash.
+ * board_flash_get_legacy needs to fill in at least:
+ * info->portwidth, info->chipwidth and info->interface for Jedec probing.
*/
-static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
+static int flash_detect_legacy(ulong base, int banknum)
{
- cfiptr_t cptr;
- cfiword_t cword;
- int retval;
+ flash_info_t *info = &flash_info[banknum];
- cptr.cp = flash_make_addr (info, sect, offset);
- flash_make_cmd (info, cmd, &cword);
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- retval = ((cptr.cp[0] & cword.c) == cword.c);
- break;
- case FLASH_CFI_16BIT:
- retval = ((cptr.wp[0] & cword.w) == cword.w);
- break;
- case FLASH_CFI_32BIT:
- retval = ((cptr.lp[0] & cword.l) == cword.l);
- break;
- case FLASH_CFI_64BIT:
- retval = ((cptr.llp[0] & cword.ll) == cword.ll);
- break;
- default:
- retval = 0;
- break;
+ if (board_flash_get_legacy(base, banknum, info)) {
+ /* board code may have filled info completely. If not, we
+ use JEDEC ID probing. */
+ if (!info->vendor) {
+ int modes[] = {
+ CFI_CMDSET_AMD_STANDARD,
+ CFI_CMDSET_INTEL_STANDARD
+ };
+ int i;
+
+ for (i = 0; i < sizeof(modes) / sizeof(modes[0]); i++) {
+ info->vendor = modes[i];
+ info->start[0] = base;
+ if (info->portwidth == FLASH_CFI_8BIT
+ && info->interface == FLASH_CFI_X8X16) {
+ info->addr_unlock1 = 0x2AAA;
+ info->addr_unlock2 = 0x5555;
+ } else {
+ info->addr_unlock1 = 0x5555;
+ info->addr_unlock2 = 0x2AAA;
+ }
+ flash_read_jedec_ids(info);
+ debug("JEDEC PROBE: ID %x %x %x\n",
+ info->manufacturer_id,
+ info->device_id,
+ info->device_id2);
+ if (jedec_flash_match(info, base))
+ break;
+ }
+ }
+
+ switch(info->vendor) {
+ case CFI_CMDSET_INTEL_STANDARD:
+ case CFI_CMDSET_INTEL_EXTENDED:
+ info->cmd_reset = FLASH_CMD_RESET;
+ break;
+ case CFI_CMDSET_AMD_STANDARD:
+ case CFI_CMDSET_AMD_EXTENDED:
+ case CFI_CMDSET_AMD_LEGACY:
+ info->cmd_reset = AMD_CMD_RESET;
+ break;
+ }
+ info->flash_id = FLASH_MAN_CFI;
+ return 1;
}
- return retval;
+ return 0; /* use CFI */
+}
+#else
+static inline int flash_detect_legacy(ulong base, int banknum)
+{
+ return 0; /* use CFI */
}
+#endif
/*-----------------------------------------------------------------------
+ * detect if flash is compatible with the Common Flash Interface (CFI)
+ * http://www.jedec.org/download/search/jesd68.pdf
*/
-static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
+static void flash_read_cfi (flash_info_t *info, void *buf,
+ unsigned int start, size_t len)
{
- cfiptr_t cptr;
- cfiword_t cword;
- int retval;
+ u8 *p = buf;
+ unsigned int i;
- cptr.cp = flash_make_addr (info, sect, offset);
- flash_make_cmd (info, cmd, &cword);
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- retval = ((cptr.cp[0] & cword.c) != (cptr.cp[0] & cword.c));
- break;
- case FLASH_CFI_16BIT:
- retval = ((cptr.wp[0] & cword.w) != (cptr.wp[0] & cword.w));
- break;
- case FLASH_CFI_32BIT:
- retval = ((cptr.lp[0] & cword.l) != (cptr.lp[0] & cword.l));
- break;
- case FLASH_CFI_64BIT:
- retval = ((cptr.llp[0] & cword.ll) !=
- (cptr.llp[0] & cword.ll));
- break;
- default:
- retval = 0;
- break;
- }
- return retval;
+ for (i = 0; i < len; i++)
+ p[i] = flash_read_uchar(info, start + i);
}
-/*-----------------------------------------------------------------------
- * read jedec ids from device and set corresponding fields in info struct
- *
- * Note: assume cfi->vendor, cfi->portwidth and cfi->chipwidth are correct
- *
-*/
-static void flash_read_jedec_ids (flash_info_t * info)
+static int __flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry)
{
- info->manufacturer_id = 0;
- info->device_id = 0;
- info->device_id2 = 0;
+ int cfi_offset;
- switch (info->vendor) {
- case CFI_CMDSET_INTEL_STANDARD:
- case CFI_CMDSET_INTEL_EXTENDED:
- flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
- flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID);
- udelay(1000); /* some flash are slow to respond */
- info->manufacturer_id = flash_read_uchar (info,
- FLASH_OFFSET_MANUFACTURER_ID);
- info->device_id = flash_read_uchar (info,
- FLASH_OFFSET_DEVICE_ID);
- flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
- break;
- case CFI_CMDSET_AMD_STANDARD:
- case CFI_CMDSET_AMD_EXTENDED:
- flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
- flash_unlock_seq(info, 0);
- flash_write_cmd(info, 0, AMD_ADDR_START, FLASH_CMD_READ_ID);
- udelay(1000); /* some flash are slow to respond */
- info->manufacturer_id = flash_read_uchar (info,
- FLASH_OFFSET_MANUFACTURER_ID);
- info->device_id = flash_read_uchar (info,
- FLASH_OFFSET_DEVICE_ID);
- if (info->device_id == 0x7E) {
- /* AMD 3-byte (expanded) device ids */
- info->device_id2 = flash_read_uchar (info,
- FLASH_OFFSET_DEVICE_ID2);
- info->device_id2 <<= 8;
- info->device_id2 |= flash_read_uchar (info,
- FLASH_OFFSET_DEVICE_ID3);
- }
- flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
- break;
- default:
- break;
+ flash_write_cmd (info, 0, 0, info->cmd_reset);
+ for (cfi_offset=0;
+ cfi_offset < sizeof(flash_offset_cfi) / sizeof(uint);
+ cfi_offset++) {
+ flash_write_cmd (info, 0, flash_offset_cfi[cfi_offset],
+ FLASH_CMD_CFI);
+ if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
+ && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R')
+ && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) {
+ flash_read_cfi(info, qry, FLASH_OFFSET_CFI_RESP,
+ sizeof(struct cfi_qry));
+ info->interface = le16_to_cpu(qry->interface_desc);
+
+ info->cfi_offset = flash_offset_cfi[cfi_offset];
+ debug ("device interface is %d\n",
+ info->interface);
+ debug ("found port %d chip %d ",
+ info->portwidth, info->chipwidth);
+ debug ("port %d bits chip %d bits\n",
+ info->portwidth << CFI_FLASH_SHIFT_WIDTH,
+ info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
+
+ /* calculate command offsets as in the Linux driver */
+ info->addr_unlock1 = 0x555;
+ info->addr_unlock2 = 0x2aa;
+
+ /*
+ * modify the unlock address if we are
+ * in compatibility mode
+ */
+ if ( /* x8/x16 in x8 mode */
+ ((info->chipwidth == FLASH_CFI_BY8) &&
+ (info->interface == FLASH_CFI_X8X16)) ||
+ /* x16/x32 in x16 mode */
+ ((info->chipwidth == FLASH_CFI_BY16) &&
+ (info->interface == FLASH_CFI_X16X32)))
+ {
+ info->addr_unlock1 = 0xaaa;
+ info->addr_unlock2 = 0x555;
+ }
+
+ info->name = "CFI conformant";
+ return 1;
+ }
}
+
+ return 0;
}
-/*-----------------------------------------------------------------------
- * detect if flash is compatible with the Common Flash Interface (CFI)
- * http://www.jedec.org/download/search/jesd68.pdf
- *
-*/
-static int flash_detect_cfi (flash_info_t * info)
+static int flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry)
{
- int cfi_offset;
debug ("flash detect cfi\n");
for (info->portwidth = CFG_FLASH_CFI_WIDTH;
info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) {
for (info->chipwidth = FLASH_CFI_BY8;
info->chipwidth <= info->portwidth;
- info->chipwidth <<= 1) {
- flash_write_cmd (info, 0, 0, info->cmd_reset);
- for (cfi_offset=0; cfi_offset < sizeof(flash_offset_cfi)/sizeof(uint); cfi_offset++) {
- flash_write_cmd (info, 0, flash_offset_cfi[cfi_offset], FLASH_CMD_CFI);
- if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
- && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R')
- && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) {
- info->interface = flash_read_ushort (info, 0, FLASH_OFFSET_INTERFACE);
- info->cfi_offset=flash_offset_cfi[cfi_offset];
- debug ("device interface is %d\n",
- info->interface);
- debug ("found port %d chip %d ",
- info->portwidth, info->chipwidth);
- debug ("port %d bits chip %d bits\n",
- info->portwidth << CFI_FLASH_SHIFT_WIDTH,
- info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
- return 1;
- }
- }
- }
+ info->chipwidth <<= 1)
+ if (__flash_detect_cfi(info, qry))
+ return 1;
}
debug ("not found\n");
return 0;
}
+/*
+ * Manufacturer-specific quirks. Add workarounds for geometry
+ * reversal, etc. here.
+ */
+static void flash_fixup_amd(flash_info_t *info, struct cfi_qry *qry)
+{
+ /* check if flash geometry needs reversal */
+ if (qry->num_erase_regions > 1) {
+ /* reverse geometry if top boot part */
+ if (info->cfi_version < 0x3131) {
+ /* CFI < 1.1, try to guess from device id */
+ if ((info->device_id & 0x80) != 0)
+ cfi_reverse_geometry(qry);
+ } else if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) {
+ /* CFI >= 1.1, deduct from top/bottom flag */
+ /* note: ext_addr is valid since cfi_version > 0 */
+ cfi_reverse_geometry(qry);
+ }
+ }
+}
+
+static void flash_fixup_atmel(flash_info_t *info, struct cfi_qry *qry)
+{
+ int reverse_geometry = 0;
+
+ /* Check the "top boot" bit in the PRI */
+ if (info->ext_addr && !(flash_read_uchar(info, info->ext_addr + 6) & 1))
+ reverse_geometry = 1;
+
+ /* AT49BV6416(T) list the erase regions in the wrong order.
+ * However, the device ID is identical with the non-broken
+ * AT49BV642D since u-boot only reads the low byte (they
+ * differ in the high byte.) So leave out this fixup for now.
+ */
+#if 0
+ if (info->device_id == 0xd6 || info->device_id == 0xd2)
+ reverse_geometry = !reverse_geometry;
+#endif
+
+ if (reverse_geometry)
+ cfi_reverse_geometry(qry);
+}
+
/*
* The following code cannot be run from FLASH!
*
uchar num_erase_regions;
int erase_region_size;
int erase_region_count;
- int geometry_reversed = 0;
+ struct cfi_qry qry;
info->ext_addr = 0;
info->cfi_version = 0;
info->start[0] = base;
- if (flash_detect_cfi (info)) {
- info->vendor = flash_read_ushort (info, 0,
- FLASH_OFFSET_PRIMARY_VENDOR);
- flash_read_jedec_ids (info);
- flash_write_cmd (info, 0, info->cfi_offset, FLASH_CMD_CFI);
- num_erase_regions = flash_read_uchar (info,
- FLASH_OFFSET_NUM_ERASE_REGIONS);
- info->ext_addr = flash_read_ushort (info, 0,
- FLASH_OFFSET_EXT_QUERY_T_P_ADDR);
+ if (flash_detect_cfi (info, &qry)) {
+ info->vendor = le16_to_cpu(qry.p_id);
+ info->ext_addr = le16_to_cpu(qry.p_adr);
+ num_erase_regions = qry.num_erase_regions;
+
if (info->ext_addr) {
info->cfi_version = (ushort) flash_read_uchar (info,
info->ext_addr + 3) << 8;
info->cfi_version |= (ushort) flash_read_uchar (info,
info->ext_addr + 4);
}
+
#ifdef DEBUG
- flash_printqry (info, 0);
+ flash_printqry (&qry);
#endif
+
switch (info->vendor) {
case CFI_CMDSET_INTEL_STANDARD:
case CFI_CMDSET_INTEL_EXTENDED:
- default:
- info->cmd_reset = FLASH_CMD_RESET;
-#ifdef CFG_FLASH_PROTECTION
- /* read legacy lock/unlock bit from intel flash */
- if (info->ext_addr) {
- info->legacy_unlock = flash_read_uchar (info,
- info->ext_addr + 5) & 0x08;
- }
-#endif
+ cmdset_intel_init(info, &qry);
break;
case CFI_CMDSET_AMD_STANDARD:
case CFI_CMDSET_AMD_EXTENDED:
- info->cmd_reset = AMD_CMD_RESET;
- /* check if flash geometry needs reversal */
- if (num_erase_regions <= 1)
- break;
- /* reverse geometry if top boot part */
- if (info->cfi_version < 0x3131) {
- /* CFI < 1.1, try to guess from device id */
- if ((info->device_id & 0x80) != 0) {
- geometry_reversed = 1;
- }
- break;
- }
- /* CFI >= 1.1, deduct from top/bottom flag */
- /* note: ext_addr is valid since cfi_version > 0 */
- if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) {
- geometry_reversed = 1;
- }
+ cmdset_amd_init(info, &qry);
+ break;
+ default:
+ printf("CFI: Unknown command set 0x%x\n",
+ info->vendor);
+ /*
+ * Unfortunately, this means we don't know how
+ * to get the chip back to Read mode. Might
+ * as well try an Intel-style reset...
+ */
+ flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+ return 0;
+ }
+
+ /* Do manufacturer-specific fixups */
+ switch (info->manufacturer_id) {
+ case 0x0001:
+ flash_fixup_amd(info, &qry);
+ break;
+ case 0x001f:
+ flash_fixup_atmel(info, &qry);
break;
}
num_erase_regions, NUM_ERASE_REGIONS);
break;
}
- if (geometry_reversed)
- tmp = flash_read_long (info, 0,
- FLASH_OFFSET_ERASE_REGIONS +
- (num_erase_regions - 1 - i) * 4);
- else
- tmp = flash_read_long (info, 0,
- FLASH_OFFSET_ERASE_REGIONS +
- i * 4);
+
+ tmp = le32_to_cpu(qry.erase_region_info[i]);
+ debug("erase region %u: 0x%08lx\n", i, tmp);
+
+ erase_region_count = (tmp & 0xffff) + 1;
+ tmp >>= 16;
erase_region_size =
(tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128;
- tmp >>= 16;
- erase_region_count = (tmp & 0xffff) + 1;
debug ("erase_region_count = %d erase_region_size = %d\n",
erase_region_count, erase_region_size);
for (j = 0; j < erase_region_count; j++) {
+ if (sect_cnt >= CFG_MAX_FLASH_SECT) {
+ printf("ERROR: too many flash sectors\n");
+ break;
+ }
info->start[sect_cnt] = sector;
sector += (erase_region_size * size_ratio);
/*
- * Only read protection status from supported devices (intel...)
+ * Only read protection status from
+ * supported devices (intel...)
*/
switch (info->vendor) {
case CFI_CMDSET_INTEL_EXTENDED:
FLASH_STATUS_PROTECT);
break;
default:
- info->protect[sect_cnt] = 0; /* default: not protected */
+ /* default: not protected */
+ info->protect[sect_cnt] = 0;
}
sect_cnt++;
}
info->sector_count = sect_cnt;
+ info->size = 1 << qry.dev_size;
/* multiply the size by the number of chips */
- info->size = (1 << flash_read_uchar (info, FLASH_OFFSET_SIZE)) * size_ratio;
- info->buffer_size = (1 << flash_read_ushort (info, 0, FLASH_OFFSET_BUFFER_SIZE));
- tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_ETOUT);
- info->erase_blk_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_EMAX_TOUT)));
- tmp = (1 << flash_read_uchar (info, FLASH_OFFSET_WBTOUT)) *
- (1 << flash_read_uchar (info, FLASH_OFFSET_WBMAX_TOUT));
- info->buffer_write_tout = tmp / 1000 + (tmp % 1000 ? 1 : 0); /* round up when converting to ms */
- tmp = (1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT)) *
- (1 << flash_read_uchar (info, FLASH_OFFSET_WMAX_TOUT));
- info->write_tout = tmp / 1000 + (tmp % 1000 ? 1 : 0); /* round up when converting to ms */
+ info->size *= size_ratio;
+ info->buffer_size = 1 << le16_to_cpu(qry.max_buf_write_size);
+ tmp = 1 << qry.block_erase_timeout_typ;
+ info->erase_blk_tout = tmp *
+ (1 << qry.block_erase_timeout_max);
+ tmp = (1 << qry.buf_write_timeout_typ) *
+ (1 << qry.buf_write_timeout_max);
+
+ /* round up when converting to ms */
+ info->buffer_write_tout = (tmp + 999) / 1000;
+ tmp = (1 << qry.word_write_timeout_typ) *
+ (1 << qry.word_write_timeout_max);
+ /* round up when converting to ms */
+ info->write_tout = (tmp + 999) / 1000;
info->flash_id = FLASH_MAN_CFI;
- if ((info->interface == FLASH_CFI_X8X16) && (info->chipwidth == FLASH_CFI_BY8)) {
- info->portwidth >>= 1; /* XXX - Need to test on x8/x16 in parallel. */
+ if ((info->interface == FLASH_CFI_X8X16) &&
+ (info->chipwidth == FLASH_CFI_BY8)) {
+ /* XXX - Need to test on x8/x16 in parallel. */
+ info->portwidth >>= 1;
}
}
return (info->size);
}
-/* loop through the sectors from the highest address
- * when the passed address is greater or equal to the sector address
- * we have a match
- */
-static flash_sect_t find_sector (flash_info_t * info, ulong addr)
-{
- flash_sect_t sector;
-
- for (sector = info->sector_count - 1; sector >= 0; sector--) {
- if (addr >= info->start[sector])
- break;
- }
- return sector;
-}
-
/*-----------------------------------------------------------------------
*/
-static int flash_write_cfiword (flash_info_t * info, ulong dest,
- cfiword_t cword)
+unsigned long flash_init (void)
{
- cfiptr_t ctladdr;
- cfiptr_t cptr;
- int flag;
-
- ctladdr.cp = flash_make_addr (info, 0, 0);
- cptr.cp = (uchar *) dest;
-
- /* Check if Flash is (sufficiently) erased */
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- flag = ((cptr.cp[0] & cword.c) == cword.c);
- break;
- case FLASH_CFI_16BIT:
- flag = ((cptr.wp[0] & cword.w) == cword.w);
- break;
- case FLASH_CFI_32BIT:
- flag = ((cptr.lp[0] & cword.l) == cword.l);
- break;
- case FLASH_CFI_64BIT:
- flag = ((cptr.llp[0] & cword.ll) == cword.ll);
- break;
- default:
- return 2;
- }
- if (!flag)
- return 2;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
+ unsigned long size = 0;
+ int i;
- switch (info->vendor) {
- case CFI_CMDSET_INTEL_EXTENDED:
- case CFI_CMDSET_INTEL_STANDARD:
- flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE);
- break;
- case CFI_CMDSET_AMD_EXTENDED:
- case CFI_CMDSET_AMD_STANDARD:
- flash_unlock_seq (info, 0);
- flash_write_cmd (info, 0, AMD_ADDR_START, AMD_CMD_WRITE);
- break;
- }
+#ifdef CFG_FLASH_PROTECTION
+ char *s = getenv("unlock");
+#endif
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- cptr.cp[0] = cword.c;
- break;
- case FLASH_CFI_16BIT:
- cptr.wp[0] = cword.w;
- break;
- case FLASH_CFI_32BIT:
- cptr.lp[0] = cword.l;
- break;
- case FLASH_CFI_64BIT:
- cptr.llp[0] = cword.ll;
- break;
- }
+ /* Init: no FLASHes known */
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
+ if (!flash_detect_legacy (bank_base[i], i))
+ flash_get_size (bank_base[i], i);
+ size += flash_info[i].size;
+ if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+#ifndef CFG_FLASH_QUIET_TEST
+ printf ("## Unknown FLASH on Bank %d "
+ "- Size = 0x%08lx = %ld MB\n",
+ i+1, flash_info[i].size,
+ flash_info[i].size << 20);
+#endif /* CFG_FLASH_QUIET_TEST */
+ }
+#ifdef CFG_FLASH_PROTECTION
+ else if ((s != NULL) && (strcmp(s, "yes") == 0)) {
+ /*
+ * Only the U-Boot image and it's environment
+ * is protected, all other sectors are
+ * unprotected (unlocked) if flash hardware
+ * protection is used (CFG_FLASH_PROTECTION)
+ * and the environment variable "unlock" is
+ * set to "yes".
+ */
+ if (flash_info[i].legacy_unlock) {
+ int k;
- return flash_full_status_check (info, find_sector (info, dest),
- info->write_tout, "write");
-}
+ /*
+ * Disable legacy_unlock temporarily,
+ * since flash_real_protect would
+ * relock all other sectors again
+ * otherwise.
+ */
+ flash_info[i].legacy_unlock = 0;
-#ifdef CFG_FLASH_USE_BUFFER_WRITE
+ /*
+ * Legacy unlocking (e.g. Intel J3) ->
+ * unlock only one sector. This will
+ * unlock all sectors.
+ */
+ flash_real_protect (&flash_info[i], 0, 0);
-static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
- int len)
-{
- flash_sect_t sector;
- int cnt;
- int retcode;
- volatile cfiptr_t src;
- volatile cfiptr_t dst;
+ flash_info[i].legacy_unlock = 1;
- switch (info->vendor) {
- case CFI_CMDSET_INTEL_STANDARD:
- case CFI_CMDSET_INTEL_EXTENDED:
- src.cp = cp;
- dst.cp = (uchar *) dest;
- sector = find_sector (info, dest);
- flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
- if ((retcode = flash_status_check (info, sector, info->buffer_write_tout,
- "write to buffer")) == ERR_OK) {
- /* reduce the number of loops by the width of the port */
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- cnt = len;
- break;
- case FLASH_CFI_16BIT:
- cnt = len >> 1;
- break;
- case FLASH_CFI_32BIT:
- cnt = len >> 2;
- break;
- case FLASH_CFI_64BIT:
- cnt = len >> 3;
- break;
- default:
- return ERR_INVAL;
- break;
- }
- flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
- while (cnt-- > 0) {
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- *dst.cp++ = *src.cp++;
- break;
- case FLASH_CFI_16BIT:
- *dst.wp++ = *src.wp++;
- break;
- case FLASH_CFI_32BIT:
- *dst.lp++ = *src.lp++;
- break;
- case FLASH_CFI_64BIT:
- *dst.llp++ = *src.llp++;
- break;
- default:
- return ERR_INVAL;
- break;
- }
+ /*
+ * Manually mark other sectors as
+ * unlocked (unprotected)
+ */
+ for (k = 1; k < flash_info[i].sector_count; k++)
+ flash_info[i].protect[k] = 0;
+ } else {
+ /*
+ * No legancy unlocking -> unlock all sectors
+ */
+ flash_protect (FLAG_PROTECT_CLEAR,
+ flash_info[i].start[0],
+ flash_info[i].start[0]
+ + flash_info[i].size - 1,
+ &flash_info[i]);
}
- flash_write_cmd (info, sector, 0,
- FLASH_CMD_WRITE_BUFFER_CONFIRM);
- retcode = flash_full_status_check (info, sector,
- info->buffer_write_tout,
- "buffer write");
}
- return retcode;
-
- case CFI_CMDSET_AMD_STANDARD:
- case CFI_CMDSET_AMD_EXTENDED:
- src.cp = cp;
- dst.cp = (uchar *) dest;
- sector = find_sector (info, dest);
-
- flash_unlock_seq(info,0);
- flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_TO_BUFFER);
+#endif /* CFG_FLASH_PROTECTION */
+ }
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- cnt = len;
- flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
- while (cnt-- > 0) *dst.cp++ = *src.cp++;
- break;
- case FLASH_CFI_16BIT:
- cnt = len >> 1;
- flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
- while (cnt-- > 0) *dst.wp++ = *src.wp++;
- break;
- case FLASH_CFI_32BIT:
- cnt = len >> 2;
- flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
- while (cnt-- > 0) *dst.lp++ = *src.lp++;
- break;
- case FLASH_CFI_64BIT:
- cnt = len >> 3;
- flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
- while (cnt-- > 0) *dst.llp++ = *src.llp++;
- break;
- default:
- return ERR_INVAL;
- }
+ /* Monitor protection ON by default */
+#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
+ flash_protect (FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE + monitor_flash_len - 1,
+ flash_get_info(CFG_MONITOR_BASE));
+#endif
- flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_BUFFER_CONFIRM);
- retcode = flash_full_status_check (info, sector, info->buffer_write_tout,
- "buffer write");
- return retcode;
+ /* Environment protection ON by default */
+#ifdef CFG_ENV_IS_IN_FLASH
+ flash_protect (FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+ flash_get_info(CFG_ENV_ADDR));
+#endif
- default:
- debug ("Unknown Command Set\n");
- return ERR_INVAL;
- }
+ /* Redundant environment protection ON by default */
+#ifdef CFG_ENV_ADDR_REDUND
+ flash_protect (FLAG_PROTECT_SET,
+ CFG_ENV_ADDR_REDUND,
+ CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
+ flash_get_info(CFG_ENV_ADDR_REDUND));
+#endif
+ return (size);
}
-#endif /* CFG_FLASH_USE_BUFFER_WRITE */
#endif /* CFG_FLASH_CFI */
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Michael Schwingen, <michael@schwingen.org>
+ *
+ * based in great part on jedec_probe.c from linux kernel:
+ * (C) 2000 Red Hat. GPL'd.
+ * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/* The DEBUG define must be before common to enable debugging */
+/*#define DEBUG*/
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/byteorder.h>
+#include <environment.h>
+
+#define P_ID_AMD_STD CFI_CMDSET_AMD_LEGACY
+
+/* Manufacturers */
+#define MANUFACTURER_AMD 0x0001
+#define MANUFACTURER_SST 0x00BF
+
+/* AMD */
+#define AM29DL800BB 0x22C8
+#define AM29DL800BT 0x224A
+
+#define AM29F800BB 0x2258
+#define AM29F800BT 0x22D6
+#define AM29LV400BB 0x22BA
+#define AM29LV400BT 0x22B9
+#define AM29LV800BB 0x225B
+#define AM29LV800BT 0x22DA
+#define AM29LV160DT 0x22C4
+#define AM29LV160DB 0x2249
+#define AM29F017D 0x003D
+#define AM29F016D 0x00AD
+#define AM29F080 0x00D5
+#define AM29F040 0x00A4
+#define AM29LV040B 0x004F
+#define AM29F032B 0x0041
+#define AM29F002T 0x00B0
+
+/* SST */
+#define SST39LF800 0x2781
+#define SST39LF160 0x2782
+#define SST39VF1601 0x234b
+#define SST39LF512 0x00D4
+#define SST39LF010 0x00D5
+#define SST39LF020 0x00D6
+#define SST39LF040 0x00D7
+#define SST39SF010A 0x00B5
+#define SST39SF020A 0x00B6
+
+
+/*
+ * Unlock address sets for AMD command sets.
+ * Intel command sets use the MTD_UADDR_UNNECESSARY.
+ * Each identifier, except MTD_UADDR_UNNECESSARY, and
+ * MTD_UADDR_NO_SUPPORT must be defined below in unlock_addrs[].
+ * MTD_UADDR_NOT_SUPPORTED must be 0 so that structure
+ * initialization need not require initializing all of the
+ * unlock addresses for all bit widths.
+ */
+enum uaddr {
+ MTD_UADDR_NOT_SUPPORTED = 0, /* data width not supported */
+ MTD_UADDR_0x0555_0x02AA,
+ MTD_UADDR_0x0555_0x0AAA,
+ MTD_UADDR_0x5555_0x2AAA,
+ MTD_UADDR_0x0AAA_0x0555,
+ MTD_UADDR_DONT_CARE, /* Requires an arbitrary address */
+ MTD_UADDR_UNNECESSARY, /* Does not require any address */
+};
+
+
+struct unlock_addr {
+ u32 addr1;
+ u32 addr2;
+};
+
+
+/*
+ * I don't like the fact that the first entry in unlock_addrs[]
+ * exists, but is for MTD_UADDR_NOT_SUPPORTED - and, therefore,
+ * should not be used. The problem is that structures with
+ * initializers have extra fields initialized to 0. It is _very_
+ * desireable to have the unlock address entries for unsupported
+ * data widths automatically initialized - that means that
+ * MTD_UADDR_NOT_SUPPORTED must be 0 and the first entry here
+ * must go unused.
+ */
+static const struct unlock_addr unlock_addrs[] = {
+ [MTD_UADDR_NOT_SUPPORTED] = {
+ .addr1 = 0xffff,
+ .addr2 = 0xffff
+ },
+
+ [MTD_UADDR_0x0555_0x02AA] = {
+ .addr1 = 0x0555,
+ .addr2 = 0x02aa
+ },
+
+ [MTD_UADDR_0x0555_0x0AAA] = {
+ .addr1 = 0x0555,
+ .addr2 = 0x0aaa
+ },
+
+ [MTD_UADDR_0x5555_0x2AAA] = {
+ .addr1 = 0x5555,
+ .addr2 = 0x2aaa
+ },
+
+ [MTD_UADDR_0x0AAA_0x0555] = {
+ .addr1 = 0x0AAA,
+ .addr2 = 0x0555
+ },
+
+ [MTD_UADDR_DONT_CARE] = {
+ .addr1 = 0x0000, /* Doesn't matter which address */
+ .addr2 = 0x0000 /* is used - must be last entry */
+ },
+
+ [MTD_UADDR_UNNECESSARY] = {
+ .addr1 = 0x0000,
+ .addr2 = 0x0000
+ }
+};
+
+
+struct amd_flash_info {
+ const __u16 mfr_id;
+ const __u16 dev_id;
+ const char *name;
+ const int DevSize;
+ const int NumEraseRegions;
+ const int CmdSet;
+ const __u8 uaddr[4]; /* unlock addrs for 8, 16, 32, 64 */
+ const ulong regions[6];
+};
+
+#define ERASEINFO(size,blocks) (size<<8)|(blocks-1)
+
+#define SIZE_64KiB 16
+#define SIZE_128KiB 17
+#define SIZE_256KiB 18
+#define SIZE_512KiB 19
+#define SIZE_1MiB 20
+#define SIZE_2MiB 21
+#define SIZE_4MiB 22
+#define SIZE_8MiB 23
+
+static const struct amd_flash_info jedec_table[] = {
+#ifdef CFG_FLASH_LEGACY_256Kx8
+ {
+ .mfr_id = MANUFACTURER_SST,
+ .dev_id = SST39LF020,
+ .name = "SST 39LF020",
+ .uaddr = {
+ [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
+ },
+ .DevSize = SIZE_256KiB,
+ .CmdSet = P_ID_AMD_STD,
+ .NumEraseRegions= 1,
+ .regions = {
+ ERASEINFO(0x01000,64),
+ }
+ },
+#endif
+#ifdef CFG_FLASH_LEGACY_512Kx8
+ {
+ .mfr_id = MANUFACTURER_AMD,
+ .dev_id = AM29LV040B,
+ .name = "AMD AM29LV040B",
+ .uaddr = {
+ [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
+ },
+ .DevSize = SIZE_512KiB,
+ .CmdSet = P_ID_AMD_STD,
+ .NumEraseRegions= 1,
+ .regions = {
+ ERASEINFO(0x10000,8),
+ }
+ },
+ {
+ .mfr_id = MANUFACTURER_SST,
+ .dev_id = SST39LF040,
+ .name = "SST 39LF040",
+ .uaddr = {
+ [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
+ },
+ .DevSize = SIZE_512KiB,
+ .CmdSet = P_ID_AMD_STD,
+ .NumEraseRegions= 1,
+ .regions = {
+ ERASEINFO(0x01000,128),
+ }
+ },
+#endif
+};
+
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+
+static inline void fill_info(flash_info_t *info, const struct amd_flash_info *jedec_entry, ulong base)
+{
+ int i,j;
+ int sect_cnt;
+ int size_ratio;
+ int total_size;
+ enum uaddr uaddr_idx;
+
+ size_ratio = info->portwidth / info->chipwidth;
+
+ debug("Found JEDEC Flash: %s\n", jedec_entry->name);
+ info->vendor = jedec_entry->CmdSet;
+ /* Todo: do we need device-specific timeouts? */
+ info->erase_blk_tout = 30000;
+ info->buffer_write_tout = 1000;
+ info->write_tout = 100;
+ info->name = jedec_entry->name;
+
+ /* copy unlock addresses from device table to CFI info struct. This
+ is just here because the addresses are in the table anyway - if
+ the flash is not detected due to wrong unlock addresses,
+ flash_detect_legacy would have to try all of them before we even
+ get here. */
+ switch(info->chipwidth) {
+ case FLASH_CFI_8BIT:
+ uaddr_idx = jedec_entry->uaddr[0];
+ break;
+ case FLASH_CFI_16BIT:
+ uaddr_idx = jedec_entry->uaddr[1];
+ break;
+ case FLASH_CFI_32BIT:
+ uaddr_idx = jedec_entry->uaddr[2];
+ break;
+ default:
+ uaddr_idx = MTD_UADDR_NOT_SUPPORTED;
+ break;
+ }
+
+ debug("unlock address index %d\n", uaddr_idx);
+ info->addr_unlock1 = unlock_addrs[uaddr_idx].addr1;
+ info->addr_unlock2 = unlock_addrs[uaddr_idx].addr2;
+ debug("unlock addresses are 0x%x/0x%x\n", info->addr_unlock1, info->addr_unlock2);
+
+ sect_cnt = 0;
+ total_size = 0;
+ for (i = 0; i < jedec_entry->NumEraseRegions; i++) {
+ ulong erase_region_size = jedec_entry->regions[i] >> 8;
+ ulong erase_region_count = (jedec_entry->regions[i] & 0xff) + 1;
+
+ total_size += erase_region_size * erase_region_count;
+ debug ("erase_region_count = %d erase_region_size = %d\n",
+ erase_region_count, erase_region_size);
+ for (j = 0; j < erase_region_count; j++) {
+ if (sect_cnt >= CFG_MAX_FLASH_SECT) {
+ printf("ERROR: too many flash sectors\n");
+ break;
+ }
+ info->start[sect_cnt] = base;
+ base += (erase_region_size * size_ratio);
+ sect_cnt++;
+ }
+ }
+ info->sector_count = sect_cnt;
+ info->size = total_size * size_ratio;
+}
+
+/*-----------------------------------------------------------------------
+ * match jedec ids against table. If a match is found, fill flash_info entry
+ */
+int jedec_flash_match(flash_info_t *info, ulong base)
+{
+ int ret = 0;
+ int i;
+ ulong mask = 0xFFFF;
+ if (info->chipwidth == 1)
+ mask = 0xFF;
+
+ for (i = 0; i < ARRAY_SIZE(jedec_table); i++) {
+ if ((jedec_table[i].mfr_id & mask) == (info->manufacturer_id & mask) &&
+ (jedec_table[i].dev_id & mask) == (info->device_id & mask)) {
+ fill_info(info, &jedec_table[i], base);
+ ret = 1;
+ break;
+ }
+ }
+ return ret;
+}
pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm);
enabled = ltssm >= PCI_LTSSM_L0;
+#ifdef CONFIG_FSL_PCIE_RESET
+ if (ltssm == 1) {
+ int i;
+ debug("....PCIe link error. "
+ "LTSSM=0x%02x.", ltssm);
+ pci->pdb_stat |= 0x08000000; /* assert PCIe reset */
+ temp32 = pci->pdb_stat;
+ udelay(100);
+ debug(" Asserting PCIe reset @%x = %x\n",
+ &pci->pdb_stat, pci->pdb_stat);
+ pci->pdb_stat &= ~0x08000000; /* clear reset */
+ asm("sync;isync");
+ for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) {
+ pci_hose_read_config_word(hose, dev, PCI_LTSSM,
+ <ssm);
+ udelay(1000);
+ debug("....PCIe link error. "
+ "LTSSM=0x%02x.\n", ltssm);
+ }
+ enabled = ltssm >= PCI_LTSSM_L0;
+ }
+#endif
+
if (!enabled) {
debug("....PCIE link error. Skipping scan."
"LTSSM=0x%02x\n", ltssm);
COBJS-y += rpx_pcmcia.o
COBJS-y += ti_pci1410a.o
COBJS-y += tqm8xx_pcmcia.o
+COBJS-y += marubun_pcmcia.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
--- /dev/null
+/*
+ * Marubun MR-SHPC-01 PCMCIA controller device driver
+ *
+ * (c) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <pcmcia.h>
+#include <asm/io.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+#define CONFIG_PCMCIA
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_IDE)
+#define CONFIG_PCMCIA
+#endif
+
+#if defined(CONFIG_PCMCIA) \
+ && (defined(CONFIG_MARUBUN_PCCARD))
+
+/* MR-SHPC-01 register */
+#define MRSHPC_MODE (CFG_MARUBUN_MRSHPC + 4)
+#define MRSHPC_OPTION (CFG_MARUBUN_MRSHPC + 6)
+#define MRSHPC_CSR (CFG_MARUBUN_MRSHPC + 8)
+#define MRSHPC_ISR (CFG_MARUBUN_MRSHPC + 10)
+#define MRSHPC_ICR (CFG_MARUBUN_MRSHPC + 12)
+#define MRSHPC_CPWCR (CFG_MARUBUN_MRSHPC + 14)
+#define MRSHPC_MW0CR1 (CFG_MARUBUN_MRSHPC + 16)
+#define MRSHPC_MW1CR1 (CFG_MARUBUN_MRSHPC + 18)
+#define MRSHPC_IOWCR1 (CFG_MARUBUN_MRSHPC + 20)
+#define MRSHPC_MW0CR2 (CFG_MARUBUN_MRSHPC + 22)
+#define MRSHPC_MW1CR2 (CFG_MARUBUN_MRSHPC + 24)
+#define MRSHPC_IOWCR2 (CFG_MARUBUN_MRSHPC + 26)
+#define MRSHPC_CDCR (CFG_MARUBUN_MRSHPC + 28)
+#define MRSHPC_PCIC_INFO (CFG_MARUBUN_MRSHPC + 30)
+
+int pcmcia_on (void)
+{
+ printf("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
+
+ /* Init */
+ outw( 0x0000 , MRSHPC_MODE );
+
+ if ((inw(MRSHPC_CSR) & 0x000c) == 0){ /* if card detect is true */
+ if ((inw(MRSHPC_CSR) & 0x0080) == 0){
+ outw(0x0674 ,MRSHPC_CPWCR); /* Card Vcc is 3.3v? */
+ }else{
+ outw(0x0678 ,MRSHPC_CPWCR); /* Card Vcc is 5V */
+ }
+ udelay( 100000 ); /* wait for power on */
+ }else{
+ return 1;
+ }
+ /*
+ * PC-Card window open
+ * flag == COMMON/ATTRIBUTE/IO
+ */
+ /* common window open */
+ outw(0x8a84,MRSHPC_MW0CR1); /* window 0xb8400000 */
+ if ((inw(MRSHPC_CSR) & 0x4000) != 0)
+ outw(0x0b00,MRSHPC_MW0CR2); /* common mode & bus width 16bit SWAP = 1 */
+ else
+ outw(0x0300,MRSHPC_MW0CR2); /* common mode & bus width 16bit SWAP = 0 */
+
+ /* attribute window open */
+ outw(0x8a85,MRSHPC_MW1CR1); /* window 0xb8500000 */
+ if ((inw(MRSHPC_CSR) & 0x4000) != 0)
+ outw(0x0a00,MRSHPC_MW1CR2); /* attribute mode & bus width 16bit SWAP = 1 */
+ else
+ outw(0x0200,MRSHPC_MW1CR2); /* attribute mode & bus width 16bit SWAP = 0 */
+
+ /* I/O window open */
+ outw(0x8a86,MRSHPC_IOWCR1); /* I/O window 0xb8600000 */
+ outw(0x0008,MRSHPC_CDCR); /* I/O card mode */
+ if ((inw(MRSHPC_CSR) & 0x4000) != 0)
+ outw(0x0a00,MRSHPC_IOWCR2); /* bus width 16bit SWAP = 1 */
+ else
+ outw(0x0200,MRSHPC_IOWCR2); /* bus width 16bit SWAP = 0 */
+
+ outw(0x0000,MRSHPC_ISR);
+ outw(0x2000,MRSHPC_ICR);
+ outb(0x00,(CFG_MARUBUN_MW2 + 0x206));
+ outb(0x42,(CFG_MARUBUN_MW2 + 0x200));
+
+ return 0;
+}
+
+int pcmcia_off (void)
+{
+ printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n");
+
+ return 0;
+}
+
+#endif /* CONFIG_MARUBUN_PCCARD */
COBJS-y += ds174x.o
COBJS-y += ds3231.o
COBJS-y += m41t11.o
+COBJS-y += m41t60.o
COBJS-y += max6900.o
COBJS-y += m48t35ax.o
COBJS-y += mc146818.o
COBJS-y += s3c24x0_rtc.o
COBJS-y += rs5c372.o
COBJS-y += mcfrtc.o
+COBJS-y += x1205.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Larry Johnson, lrj@acm.org
+ *
+ * based on rtc/m41t11.c which is ...
+ *
+ * (C) Copyright 2002
+ * Andrew May, Viasat Inc, amay@viasat.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * STMicroelectronics M41T60 serial access real-time clock
+ */
+
+/* #define DEBUG 1 */
+
+#include <common.h>
+#include <command.h>
+#include <rtc.h>
+#include <i2c.h>
+
+#if defined(CONFIG_RTC_M41T60) && defined(CFG_I2C_RTC_ADDR) && \
+ defined(CONFIG_CMD_DATE)
+
+static unsigned bcd2bin(uchar n)
+{
+ return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F));
+}
+
+static unsigned char bin2bcd(unsigned int n)
+{
+ return (((n / 10) << 4) | (n % 10));
+}
+
+/*
+ * Convert between century and "century bits" (CB1 and CB0). These routines
+ * assume years are in the range 1900 - 2299.
+ */
+
+static unsigned char year2cb(unsigned const year)
+{
+ if (year < 1900 || year >= 2300)
+ printf("M41T60 RTC: year %d out of range\n", year);
+
+ return (year / 100) & 0x3;
+}
+
+static unsigned cb2year(unsigned const cb)
+{
+ return 1900 + 100 * ((cb + 1) & 0x3);
+}
+
+/*
+ * These are simple defines for the chip local to here so they aren't too
+ * verbose. DAY/DATE aren't nice but that is how they are on the data sheet.
+ */
+#define RTC_SEC 0x0
+#define RTC_MIN 0x1
+#define RTC_HOUR 0x2
+#define RTC_DAY 0x3
+#define RTC_DATE 0x4
+#define RTC_MONTH 0x5
+#define RTC_YEAR 0x6
+
+#define RTC_REG_CNT 7
+
+#define RTC_CTRL 0x7
+
+#if defined(DEBUG)
+static void rtc_dump(char const *const label)
+{
+ uchar data[8];
+
+ if (i2c_read(CFG_I2C_RTC_ADDR, 0, 1, data, sizeof(data))) {
+ printf("I2C read failed in rtc_dump()\n");
+ return;
+ }
+ printf("RTC dump %s: %02X-%02X-%02X-%02X-%02X-%02X-%02X-%02X\n",
+ label, data[0], data[1], data[2], data[3],
+ data[4], data[5], data[6], data[7]);
+}
+#else
+#define rtc_dump(label)
+#endif
+
+static uchar *rtc_validate(void)
+{
+ /*
+ * This routine uses the OUT bit and the validity of the time values to
+ * determine whether there has been an initial power-up since the last
+ * time the routine was run. It assumes that the OUT bit is not being
+ * used for any other purpose.
+ */
+ static const uchar daysInMonth[0x13] = {
+ 0x00, 0x31, 0x29, 0x31, 0x30, 0x31, 0x30, 0x31,
+ 0x31, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x31, 0x30, 0x31
+ };
+ static uchar data[8];
+ uchar min, date, month, years;
+
+ rtc_dump("begin validate");
+ if (i2c_read(CFG_I2C_RTC_ADDR, 0, 1, data, sizeof(data))) {
+ printf("I2C read failed in rtc_validate()\n");
+ return 0;
+ }
+ /*
+ * If the OUT bit is "1", there has been a loss of power, so stop the
+ * oscillator so it can be "kick-started" as per data sheet.
+ */
+ if (0x00 != (data[RTC_CTRL] & 0x80)) {
+ printf("M41T60 RTC clock lost power.\n");
+ data[RTC_SEC] = 0x80;
+ if (i2c_write(CFG_I2C_RTC_ADDR, RTC_SEC, 1, data, 1)) {
+ printf("I2C write failed in rtc_validate()\n");
+ return 0;
+ }
+ }
+ /*
+ * If the oscillator is stopped or the date is invalid, then reset the
+ * OUT bit to "0", reset the date registers, and start the oscillator.
+ */
+ min = data[RTC_MIN] & 0x7F;
+ date = data[RTC_DATE];
+ month = data[RTC_MONTH] & 0x3F;
+ years = data[RTC_YEAR];
+ if (0x59 < data[RTC_SEC] || 0x09 < (data[RTC_SEC] & 0x0F) ||
+ 0x59 < min || 0x09 < (min & 0x0F) ||
+ 0x23 < data[RTC_HOUR] || 0x09 < (data[RTC_HOUR] & 0x0F) ||
+ 0x07 < data[RTC_DAY] || 0x00 == data[RTC_DAY] ||
+ 0x12 < month ||
+ 0x99 < years || 0x09 < (years & 0x0F) ||
+ daysInMonth[month] < date || 0x09 < (date & 0x0F) || 0x00 == date ||
+ (0x29 == date && 0x02 == month &&
+ ((0x00 != (years & 0x03)) ||
+ (0x00 == years && 0x00 != (data[RTC_MONTH] & 0xC0))))) {
+ printf("Resetting M41T60 RTC clock.\n");
+ /*
+ * Set to 00:00:00 1900-01-01 (Monday)
+ */
+ data[RTC_SEC] = 0x00;
+ data[RTC_MIN] &= 0x80; /* preserve OFIE bit */
+ data[RTC_HOUR] = 0x00;
+ data[RTC_DAY] = 0x02;
+ data[RTC_DATE] = 0x01;
+ data[RTC_MONTH] = 0xC1;
+ data[RTC_YEAR] = 0x00;
+ data[RTC_CTRL] &= 0x7F; /* reset OUT bit */
+
+ if (i2c_write(CFG_I2C_RTC_ADDR, 0, 1, data, sizeof(data))) {
+ printf("I2C write failed in rtc_validate()\n");
+ return 0;
+ }
+ }
+ return data;
+}
+
+void rtc_get(struct rtc_time *tmp)
+{
+ uchar const *const data = rtc_validate();
+
+ if (!data)
+ return;
+
+ tmp->tm_sec = bcd2bin(data[RTC_SEC] & 0x7F);
+ tmp->tm_min = bcd2bin(data[RTC_MIN] & 0x7F);
+ tmp->tm_hour = bcd2bin(data[RTC_HOUR] & 0x3F);
+ tmp->tm_mday = bcd2bin(data[RTC_DATE] & 0x3F);
+ tmp->tm_mon = bcd2bin(data[RTC_MONTH] & 0x1F);
+ tmp->tm_year = cb2year(data[RTC_MONTH] >> 6) + bcd2bin(data[RTC_YEAR]);
+ tmp->tm_wday = bcd2bin(data[RTC_DAY] & 0x07) - 1;
+ tmp->tm_yday = 0;
+ tmp->tm_isdst = 0;
+
+ debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+ tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+}
+
+void rtc_set(struct rtc_time *tmp)
+{
+ uchar *const data = rtc_validate();
+
+ if (!data)
+ return;
+
+ debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+ tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+
+ data[RTC_SEC] = (data[RTC_SEC] & 0x80) | (bin2bcd(tmp->tm_sec) & 0x7F);
+ data[RTC_MIN] = (data[RTC_MIN] & 0X80) | (bin2bcd(tmp->tm_min) & 0X7F);
+ data[RTC_HOUR] = bin2bcd(tmp->tm_hour) & 0x3F;
+ data[RTC_DATE] = bin2bcd(tmp->tm_mday) & 0x3F;
+ data[RTC_MONTH] = bin2bcd(tmp->tm_mon) & 0x1F;
+ data[RTC_YEAR] = bin2bcd(tmp->tm_year % 100);
+ data[RTC_MONTH] |= year2cb(tmp->tm_year) << 6;
+ data[RTC_DAY] = bin2bcd(tmp->tm_wday + 1) & 0x07;
+ if (i2c_write(CFG_I2C_RTC_ADDR, 0, 1, data, RTC_REG_CNT)) {
+ printf("I2C write failed in rtc_set()\n");
+ return;
+ }
+}
+
+void rtc_reset(void)
+{
+ uchar *const data = rtc_validate();
+ char const *const s = getenv("rtccal");
+
+ if (!data)
+ return;
+
+ rtc_dump("begin reset");
+ /*
+ * If environmental variable "rtccal" is present, it must be a hex value
+ * between 0x00 and 0x3F, inclusive. The five least-significan bits
+ * represent the calibration magnitude, and the sixth bit the sign bit.
+ * If these do not match the contents of the hardware register, that
+ * register is updated. The value 0x00 imples no correction. Consult
+ * the M41T60 documentation for further details.
+ */
+ if (s) {
+ unsigned long const l = simple_strtoul(s, 0, 16);
+
+ if (l <= 0x3F) {
+ if ((data[RTC_CTRL] & 0x3F) != l) {
+ printf("Setting RTC calibration to 0x%02X\n",
+ l);
+ data[RTC_CTRL] &= 0xC0;
+ data[RTC_CTRL] |= (uchar) l;
+ }
+ } else
+ printf("environment parameter \"rtccal\" not valid: "
+ "ignoring\n");
+ }
+ /*
+ * Turn off frequency test.
+ */
+ data[RTC_CTRL] &= 0xBF;
+ if (i2c_write(CFG_I2C_RTC_ADDR, RTC_CTRL, 1, data + RTC_CTRL, 1)) {
+ printf("I2C write failed in rtc_reset()\n");
+ return;
+ }
+ rtc_dump("end reset");
+}
+#endif /* CONFIG_RTC_M41T60 && CFG_I2C_RTC_ADDR && CONFIG_CMD_DATE */
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * based on a the Linux rtc-x1207.c driver which is:
+ * Copyright 2004 Karen Spearel
+ * Copyright 2005 Alessandro Zummo
+ *
+ * Information and datasheet:
+ * http://www.intersil.com/cda/deviceinfo/0,1477,X1205,00.html
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Date & Time support for Xicor/Intersil X1205 RTC
+ */
+
+/* #define DEBUG */
+
+#include <common.h>
+#include <command.h>
+#include <rtc.h>
+#include <i2c.h>
+#include <bcd.h>
+
+#if defined(CONFIG_RTC_X1205) && defined(CONFIG_CMD_DATE)
+
+#define CCR_SEC 0
+#define CCR_MIN 1
+#define CCR_HOUR 2
+#define CCR_MDAY 3
+#define CCR_MONTH 4
+#define CCR_YEAR 5
+#define CCR_WDAY 6
+#define CCR_Y2K 7
+
+#define X1205_REG_SR 0x3F /* status register */
+#define X1205_REG_Y2K 0x37
+#define X1205_REG_DW 0x36
+#define X1205_REG_YR 0x35
+#define X1205_REG_MO 0x34
+#define X1205_REG_DT 0x33
+#define X1205_REG_HR 0x32
+#define X1205_REG_MN 0x31
+#define X1205_REG_SC 0x30
+#define X1205_REG_DTR 0x13
+#define X1205_REG_ATR 0x12
+#define X1205_REG_INT 0x11
+#define X1205_REG_0 0x10
+#define X1205_REG_Y2K1 0x0F
+#define X1205_REG_DWA1 0x0E
+#define X1205_REG_YRA1 0x0D
+#define X1205_REG_MOA1 0x0C
+#define X1205_REG_DTA1 0x0B
+#define X1205_REG_HRA1 0x0A
+#define X1205_REG_MNA1 0x09
+#define X1205_REG_SCA1 0x08
+#define X1205_REG_Y2K0 0x07
+#define X1205_REG_DWA0 0x06
+#define X1205_REG_YRA0 0x05
+#define X1205_REG_MOA0 0x04
+#define X1205_REG_DTA0 0x03
+#define X1205_REG_HRA0 0x02
+#define X1205_REG_MNA0 0x01
+#define X1205_REG_SCA0 0x00
+
+#define X1205_CCR_BASE 0x30 /* Base address of CCR */
+#define X1205_ALM0_BASE 0x00 /* Base address of ALARM0 */
+
+#define X1205_SR_RTCF 0x01 /* Clock failure */
+#define X1205_SR_WEL 0x02 /* Write Enable Latch */
+#define X1205_SR_RWEL 0x04 /* Register Write Enable */
+
+#define X1205_DTR_DTR0 0x01
+#define X1205_DTR_DTR1 0x02
+#define X1205_DTR_DTR2 0x04
+
+#define X1205_HR_MIL 0x80 /* Set in ccr.hour for 24 hr mode */
+
+static void rtc_write(int reg, u8 val)
+{
+ i2c_write(CFG_I2C_RTC_ADDR, reg, 2, &val, 1);
+}
+
+/*
+ * In the routines that deal directly with the x1205 hardware, we use
+ * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch
+ * Epoch is initialized as 2000. Time is set to UTC.
+ */
+void rtc_get(struct rtc_time *tm)
+{
+ u8 buf[8];
+
+ i2c_read(CFG_I2C_RTC_ADDR, X1205_CCR_BASE, 2, buf, 8);
+
+ debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, "
+ "mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n",
+ __FUNCTION__,
+ buf[0], buf[1], buf[2], buf[3],
+ buf[4], buf[5], buf[6], buf[7]);
+
+ tm->tm_sec = BCD2BIN(buf[CCR_SEC]);
+ tm->tm_min = BCD2BIN(buf[CCR_MIN]);
+ tm->tm_hour = BCD2BIN(buf[CCR_HOUR] & 0x3F); /* hr is 0-23 */
+ tm->tm_mday = BCD2BIN(buf[CCR_MDAY]);
+ tm->tm_mon = BCD2BIN(buf[CCR_MONTH]); /* mon is 0-11 */
+ tm->tm_year = BCD2BIN(buf[CCR_YEAR])
+ + (BCD2BIN(buf[CCR_Y2K]) * 100);
+ tm->tm_wday = buf[CCR_WDAY];
+
+ debug("%s: tm is secs=%d, mins=%d, hours=%d, "
+ "mday=%d, mon=%d, year=%d, wday=%d\n",
+ __FUNCTION__,
+ tm->tm_sec, tm->tm_min, tm->tm_hour,
+ tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
+}
+
+void rtc_set(struct rtc_time *tm)
+{
+ int i;
+ u8 buf[8];
+
+ debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
+ tm->tm_hour, tm->tm_min, tm->tm_sec);
+
+ buf[CCR_SEC] = BIN2BCD(tm->tm_sec);
+ buf[CCR_MIN] = BIN2BCD(tm->tm_min);
+
+ /* set hour and 24hr bit */
+ buf[CCR_HOUR] = BIN2BCD(tm->tm_hour) | X1205_HR_MIL;
+
+ buf[CCR_MDAY] = BIN2BCD(tm->tm_mday);
+
+ /* month, 1 - 12 */
+ buf[CCR_MONTH] = BIN2BCD(tm->tm_mon);
+
+ /* year, since the rtc epoch*/
+ buf[CCR_YEAR] = BIN2BCD(tm->tm_year % 100);
+ buf[CCR_WDAY] = tm->tm_wday & 0x07;
+ buf[CCR_Y2K] = BIN2BCD(tm->tm_year / 100);
+
+ /* this sequence is required to unlock the chip */
+ rtc_write(X1205_REG_SR, X1205_SR_WEL);
+ rtc_write(X1205_REG_SR, X1205_SR_WEL | X1205_SR_RWEL);
+
+ /* write register's data */
+ for (i = 0; i < 8; i++)
+ rtc_write(X1205_CCR_BASE + i, buf[i]);
+
+ rtc_write(X1205_REG_SR, 0);
+}
+
+void rtc_reset(void)
+{
+ /*
+ * Nothing to do
+ */
+}
+
+#endif
COBJS-y += serial_pl010.o
COBJS-y += serial_pl011.o
COBJS-y += serial_xuartlite.o
+COBJS-y += serial_sh.o
COBJS-y += usbtty.o
COBJS := $(COBJS-y)
--- /dev/null
+/*
+ * SuperH SCIF device driver.
+ * Copyright (c) 2007 Nobuhiro Iwamatsu
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#ifdef CFG_SCIF_CONSOLE
+
+#if defined (CONFIG_CONS_SCIF0)
+#define SCIF_BASE SCIF0_BASE
+#elif defined (CONFIG_CONS_SCIF1)
+#define SCIF_BASE SCIF1_BASE
+#else
+#error "Default SCIF doesn't set....."
+#endif
+
+#define SCSMR (vu_short *)(SCIF_BASE + 0x0)
+#define SCBRR (vu_char *)(SCIF_BASE + 0x4)
+#define SCSCR (vu_short *)(SCIF_BASE + 0x8)
+#define SCFTDR (vu_char *)(SCIF_BASE + 0xC)
+#define SCFSR (vu_short *)(SCIF_BASE + 0x10)
+#define SCFRDR (vu_char *)(SCIF_BASE + 0x14)
+#define SCFCR (vu_short *)(SCIF_BASE + 0x18)
+#define SCFDR (vu_short *)(SCIF_BASE + 0x1C)
+#if defined(CONFIG_SH4A)
+#define SCRFDR (vu_short *)(SCIF_BASE + 0x20)
+#define SCSPTR (vu_short *)(SCIF_BASE + 0x24)
+#define SCLSR (vu_short *)(SCIF_BASE + 0x28)
+#define SCRER (vu_short *)(SCIF_BASE + 0x2C)
+#elif defined (CONFIG_SH4)
+#define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
+#define SCLSR (vu_short *)(SCIF_BASE + 0x24)
+#elif defined (CONFIG_SH3)
+#define SCLSR (vu_short *)(SCIF_BASE + 0x24)
+#endif
+
+#define SCR_RE (1 << 4)
+#define SCR_TE (1 << 5)
+#define FCR_RFRST (1 << 1) /* RFCL */
+#define FCR_TFRST (1 << 2) /* TFCL */
+#define FSR_DR (1 << 0)
+#define FSR_RDF (1 << 1)
+#define FSR_FER (1 << 3)
+#define FSR_BRK (1 << 4)
+#define FSR_FER (1 << 3)
+#define FSR_TEND (1 << 6)
+#define FSR_ER (1 << 7)
+
+/*----------------------------------------------------------------------*/
+
+void serial_setbrg (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ int divisor = gd->baudrate * 32;
+
+ *SCBRR = (CONFIG_SYS_CLK_FREQ + (divisor / 2)) /
+ (gd->baudrate * 32) - 1;
+}
+
+int serial_init (void)
+{
+ *SCSCR = (SCR_RE | SCR_TE);
+ *SCSMR = 0 ;
+ *SCSMR = 0;
+ *SCFCR = (FCR_RFRST | FCR_TFRST);
+ *SCFCR;
+ *SCFCR = 0;
+
+ serial_setbrg();
+ return 0;
+}
+
+static int serial_tx_fifo_level (void)
+{
+ return (*SCFDR >> 8) & 0x1F;
+}
+
+static int serial_rx_fifo_level (void)
+{
+ return (*SCFDR >> 0) & 0x1F;
+}
+
+void serial_raw_putc (const char c)
+{
+ unsigned int fsr_bits_to_clear;
+
+ while (1) {
+ if (*SCFSR & FSR_TEND) { /* Tx fifo is empty */
+ fsr_bits_to_clear = FSR_TEND;
+ break;
+ }
+ }
+
+ *SCFTDR = c;
+ if (fsr_bits_to_clear != 0)
+ *SCFSR &= ~fsr_bits_to_clear;
+}
+
+void serial_putc (const char c)
+{
+ if (c == '\n')
+ serial_raw_putc ('\r');
+ serial_raw_putc (c);
+}
+
+void serial_puts (const char *s)
+{
+ char c;
+ while ((c = *s++) != 0)
+ serial_putc (c);
+}
+
+int serial_tstc (void)
+{
+ return serial_rx_fifo_level() ? 1 : 0;
+}
+
+#define FSR_ERR_CLEAR 0x0063
+#define RDRF_CLEAR 0x00fc
+#define LSR_ORER 1
+void handle_error( void ){
+
+ (void)*SCFSR ;
+ *SCFSR = FSR_ERR_CLEAR ;
+ (void)*SCLSR ;
+ *SCLSR = 0x00 ;
+}
+
+int serial_getc_check( void ){
+ unsigned short status;
+
+ status = *SCFSR ;
+
+ if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK))
+ handle_error();
+ if( *SCLSR & LSR_ORER )
+ handle_error();
+ return (status & ( FSR_DR | FSR_RDF ));
+}
+
+int serial_getc (void)
+{
+ unsigned short status ;
+ char ch;
+ while(!serial_getc_check());
+
+ ch = *SCFRDR;
+ status = *SCFSR ;
+
+ *SCFSR = RDRF_CLEAR ;
+
+ if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK))
+ handle_error();
+
+ if( *SCLSR & LSR_ORER )
+ handle_error();
+
+ return ch ;
+}
+
+#endif /* CFG_SCIF_CONSOLE */
LOAD_ADDR = 0x00000000
endif
+ifeq ($(ARCH),sh)
+LOAD_ADDR = 0x8C000000
+endif
+
+
include $(TOPDIR)/config.mk
ELF = hello_world
*/
#define EXPORT_FUNC(x) \
asm volatile ( \
-" .globl _" #x "\n_" \
+" .globl _" #x "\n_" \
#x ":\n" \
" P0 = [P5 + %0]\n" \
" P0 = [P0 + %1]\n" \
: \
: "i"(offsetof(gd_t, jt)), "i"(XF_ ##x) \
: "r8");
+#elif defined(CONFIG_SH)
+/*
+ * r13 holds the pointer to the global_data. r1 is a call clobbered.
+ */
+#define EXPORT_FUNC(x) \
+ asm volatile ( \
+ " .align 2\n" \
+ " .globl " #x "\n" \
+ #x ":\n" \
+ " mov r13, r1\n" \
+ " add %0, r1\n" \
+ " add %1, r1\n" \
+ " jmp @r1\n" \
+ " nop\n" \
+ " nop\n" \
+ : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r1");
#else
#error stubs definition missing for this architecture
#endif
#define MAL_ESR_PBEI 0x00000001
/* ^^ ^^ */
/* Mal IER */
-#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#if defined(CONFIG_440SPE) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_405EX)
#define MAL_IER_PT 0x00000080
#define MAL_IER_PRE 0x00000040
#define MAL_IER_PWE 0x00000020
+++ /dev/null
-#ifndef _405GP_PCI_H
-#define _405GP_PCI_H
-
-/*----------------------------------------------------------------------------+
-| 405GP PCI core memory map defines.
-+----------------------------------------------------------------------------*/
-#define MIN_PCI_MEMADDR1 0x80000000
-#define MIN_PCI_MEMADDR2 0x00000000
-#define MIN_PLB_PCI_IOADDR 0xE8000000 /* PLB side of PCI I/O address space */
-#define MIN_PCI_PCI_IOADDR 0x00000000 /* PCI side of PCI I/O address space */
-#define MAX_PCI_DEVICES 32
-
-/*----------------------------------------------------------------------------+
-| Defines for the 405GP PCI Config address and data registers followed by
-| defines for the standard PCI device configuration header.
-+----------------------------------------------------------------------------*/
-#define PCICFGADR 0xEEC00000
-#define PCICFGDATA 0xEEC00004
-
-#define PCIBUSNUM 0x40 /* 405GP specific parameters */
-#define PCISUBBUSNUM 0x41
-#define PCIDISCOUNT 0x42
-#define PCIBRDGOPT1 0x4A
-#define PCIBRDGOPT2 0x60
-
-/*----------------------------------------------------------------------------+
-| Defines for 405GP PCI Master local configuration regs.
-+----------------------------------------------------------------------------*/
-#define PMM0LA 0xEF400000
-#define PMM0MA 0xEF400004
-#define PMM0PCILA 0xEF400008
-#define PMM0PCIHA 0xEF40000C
-#define PMM1LA 0xEF400010
-#define PMM1MA 0xEF400014
-#define PMM1PCILA 0xEF400018
-#define PMM1PCIHA 0xEF40001C
-#define PMM2LA 0xEF400020
-#define PMM2MA 0xEF400024
-#define PMM2PCILA 0xEF400028
-#define PMM2PCIHA 0xEF40002C
-
-/*----------------------------------------------------------------------------+
-| Defines for 405GP PCI Target local configuration regs.
-+----------------------------------------------------------------------------*/
-#define PTM1MS 0xEF400030
-#define PTM1LA 0xEF400034
-#define PTM2MS 0xEF400038
-#define PTM2LA 0xEF40003C
-
-#define PCIDEVID_405GP 0x0
-
-#endif
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000700 + I2C_BUS_OFFS)
-#elif defined(CONFIG_440)
+#elif defined(CONFIG_440) || defined(CONFIG_405EX)
/* all remaining 440 variants */
#define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000400 + I2C_BUS_OFFS)
#else
{
}
+/*
+ * Given a physical address and a length, return a virtual address
+ * that can be used to access the memory range with the caching
+ * properties specified by "flags".
+ */
+typedef unsigned long phys_addr_t;
+
+#define MAP_NOCACHE (0)
+#define MAP_WRCOMBINE (0)
+#define MAP_WRBACK (0)
+#define MAP_WRTHROUGH (0)
+
+static inline void *
+map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
+{
+ return (void *)paddr;
+}
+
+/*
+ * Take down a mapping set up by map_physmem().
+ */
+static inline void unmap_physmem(void *vaddr, unsigned long flags)
+{
+
+}
+
/*
* Generic virtual read/write. Note that we don't support half-word
* read/writes. We define __arch_*[bl] here, and leave __arch_*w
+++ /dev/null
-/*
- * Copyright (C) 2006 Atmel Corporation
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef __ASM_AVR32_ARCH_CLK_H__
-#define __ASM_AVR32_ARCH_CLK_H__
-
-#ifdef CONFIG_PLL
-#define MAIN_CLK_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL)
-#else
-#define MAIN_CLK_RATE (CFG_OSC0_HZ)
-#endif
-
-static inline unsigned long get_cpu_clk_rate(void)
-{
- return MAIN_CLK_RATE >> CFG_CLKDIV_CPU;
-}
-static inline unsigned long get_hsb_clk_rate(void)
-{
- return MAIN_CLK_RATE >> CFG_CLKDIV_HSB;
-}
-static inline unsigned long get_pba_clk_rate(void)
-{
- return MAIN_CLK_RATE >> CFG_CLKDIV_PBA;
-}
-static inline unsigned long get_pbb_clk_rate(void)
-{
- return MAIN_CLK_RATE >> CFG_CLKDIV_PBB;
-}
-
-/* Accessors for specific devices. More will be added as needed. */
-static inline unsigned long get_sdram_clk_rate(void)
-{
- return get_hsb_clk_rate();
-}
-static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
-{
- return get_pba_clk_rate();
-}
-static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
-{
- return get_pbb_clk_rate();
-}
-static inline unsigned long get_macb_hclk_rate(unsigned int dev_id)
-{
- return get_hsb_clk_rate();
-}
-static inline unsigned long get_mci_clk_rate(void)
-{
- return get_pbb_clk_rate();
-}
-
-#endif /* __ASM_AVR32_ARCH_CLK_H__ */
+++ /dev/null
-/*
- * Copyright (C) 2006 Atmel Corporation
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef __ASM_AVR32_ARCH_GPIO_H__
-#define __ASM_AVR32_ARCH_GPIO_H__
-
-#include <asm/arch/memory-map.h>
-
-#define NR_GPIO_CONTROLLERS 5
-
-/*
- * Pin numbers identifying specific GPIO pins on the chip.
- */
-#define GPIO_PIOA_BASE (0)
-#define GPIO_PIN_PA0 (GPIO_PIOA_BASE + 0)
-#define GPIO_PIN_PA1 (GPIO_PIOA_BASE + 1)
-#define GPIO_PIN_PA2 (GPIO_PIOA_BASE + 2)
-#define GPIO_PIN_PA3 (GPIO_PIOA_BASE + 3)
-#define GPIO_PIN_PA4 (GPIO_PIOA_BASE + 4)
-#define GPIO_PIN_PA5 (GPIO_PIOA_BASE + 5)
-#define GPIO_PIN_PA6 (GPIO_PIOA_BASE + 6)
-#define GPIO_PIN_PA7 (GPIO_PIOA_BASE + 7)
-#define GPIO_PIN_PA8 (GPIO_PIOA_BASE + 8)
-#define GPIO_PIN_PA9 (GPIO_PIOA_BASE + 9)
-#define GPIO_PIN_PA10 (GPIO_PIOA_BASE + 10)
-#define GPIO_PIN_PA11 (GPIO_PIOA_BASE + 11)
-#define GPIO_PIN_PA12 (GPIO_PIOA_BASE + 12)
-#define GPIO_PIN_PA13 (GPIO_PIOA_BASE + 13)
-#define GPIO_PIN_PA14 (GPIO_PIOA_BASE + 14)
-#define GPIO_PIN_PA15 (GPIO_PIOA_BASE + 15)
-#define GPIO_PIN_PA16 (GPIO_PIOA_BASE + 16)
-#define GPIO_PIN_PA17 (GPIO_PIOA_BASE + 17)
-#define GPIO_PIN_PA18 (GPIO_PIOA_BASE + 18)
-#define GPIO_PIN_PA19 (GPIO_PIOA_BASE + 19)
-#define GPIO_PIN_PA20 (GPIO_PIOA_BASE + 20)
-#define GPIO_PIN_PA21 (GPIO_PIOA_BASE + 21)
-#define GPIO_PIN_PA22 (GPIO_PIOA_BASE + 22)
-#define GPIO_PIN_PA23 (GPIO_PIOA_BASE + 23)
-#define GPIO_PIN_PA24 (GPIO_PIOA_BASE + 24)
-#define GPIO_PIN_PA25 (GPIO_PIOA_BASE + 25)
-#define GPIO_PIN_PA26 (GPIO_PIOA_BASE + 26)
-#define GPIO_PIN_PA27 (GPIO_PIOA_BASE + 27)
-#define GPIO_PIN_PA28 (GPIO_PIOA_BASE + 28)
-#define GPIO_PIN_PA29 (GPIO_PIOA_BASE + 29)
-#define GPIO_PIN_PA30 (GPIO_PIOA_BASE + 30)
-#define GPIO_PIN_PA31 (GPIO_PIOA_BASE + 31)
-
-#define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32)
-#define GPIO_PIN_PB0 (GPIO_PIOB_BASE + 0)
-#define GPIO_PIN_PB1 (GPIO_PIOB_BASE + 1)
-#define GPIO_PIN_PB2 (GPIO_PIOB_BASE + 2)
-#define GPIO_PIN_PB3 (GPIO_PIOB_BASE + 3)
-#define GPIO_PIN_PB4 (GPIO_PIOB_BASE + 4)
-#define GPIO_PIN_PB5 (GPIO_PIOB_BASE + 5)
-#define GPIO_PIN_PB6 (GPIO_PIOB_BASE + 6)
-#define GPIO_PIN_PB7 (GPIO_PIOB_BASE + 7)
-#define GPIO_PIN_PB8 (GPIO_PIOB_BASE + 8)
-#define GPIO_PIN_PB9 (GPIO_PIOB_BASE + 9)
-#define GPIO_PIN_PB10 (GPIO_PIOB_BASE + 10)
-#define GPIO_PIN_PB11 (GPIO_PIOB_BASE + 11)
-#define GPIO_PIN_PB12 (GPIO_PIOB_BASE + 12)
-#define GPIO_PIN_PB13 (GPIO_PIOB_BASE + 13)
-#define GPIO_PIN_PB14 (GPIO_PIOB_BASE + 14)
-#define GPIO_PIN_PB15 (GPIO_PIOB_BASE + 15)
-#define GPIO_PIN_PB16 (GPIO_PIOB_BASE + 16)
-#define GPIO_PIN_PB17 (GPIO_PIOB_BASE + 17)
-#define GPIO_PIN_PB18 (GPIO_PIOB_BASE + 18)
-#define GPIO_PIN_PB19 (GPIO_PIOB_BASE + 19)
-#define GPIO_PIN_PB20 (GPIO_PIOB_BASE + 20)
-#define GPIO_PIN_PB21 (GPIO_PIOB_BASE + 21)
-#define GPIO_PIN_PB22 (GPIO_PIOB_BASE + 22)
-#define GPIO_PIN_PB23 (GPIO_PIOB_BASE + 23)
-#define GPIO_PIN_PB24 (GPIO_PIOB_BASE + 24)
-#define GPIO_PIN_PB25 (GPIO_PIOB_BASE + 25)
-#define GPIO_PIN_PB26 (GPIO_PIOB_BASE + 26)
-#define GPIO_PIN_PB27 (GPIO_PIOB_BASE + 27)
-#define GPIO_PIN_PB28 (GPIO_PIOB_BASE + 28)
-#define GPIO_PIN_PB29 (GPIO_PIOB_BASE + 29)
-#define GPIO_PIN_PB30 (GPIO_PIOB_BASE + 30)
-
-#define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32)
-#define GPIO_PIN_PC0 (GPIO_PIOC_BASE + 0)
-#define GPIO_PIN_PC1 (GPIO_PIOC_BASE + 1)
-#define GPIO_PIN_PC2 (GPIO_PIOC_BASE + 2)
-#define GPIO_PIN_PC3 (GPIO_PIOC_BASE + 3)
-#define GPIO_PIN_PC4 (GPIO_PIOC_BASE + 4)
-#define GPIO_PIN_PC5 (GPIO_PIOC_BASE + 5)
-#define GPIO_PIN_PC6 (GPIO_PIOC_BASE + 6)
-#define GPIO_PIN_PC7 (GPIO_PIOC_BASE + 7)
-#define GPIO_PIN_PC8 (GPIO_PIOC_BASE + 8)
-#define GPIO_PIN_PC9 (GPIO_PIOC_BASE + 9)
-#define GPIO_PIN_PC10 (GPIO_PIOC_BASE + 10)
-#define GPIO_PIN_PC11 (GPIO_PIOC_BASE + 11)
-#define GPIO_PIN_PC12 (GPIO_PIOC_BASE + 12)
-#define GPIO_PIN_PC13 (GPIO_PIOC_BASE + 13)
-#define GPIO_PIN_PC14 (GPIO_PIOC_BASE + 14)
-#define GPIO_PIN_PC15 (GPIO_PIOC_BASE + 15)
-#define GPIO_PIN_PC16 (GPIO_PIOC_BASE + 16)
-#define GPIO_PIN_PC17 (GPIO_PIOC_BASE + 17)
-#define GPIO_PIN_PC18 (GPIO_PIOC_BASE + 18)
-#define GPIO_PIN_PC19 (GPIO_PIOC_BASE + 19)
-#define GPIO_PIN_PC20 (GPIO_PIOC_BASE + 20)
-#define GPIO_PIN_PC21 (GPIO_PIOC_BASE + 21)
-#define GPIO_PIN_PC22 (GPIO_PIOC_BASE + 22)
-#define GPIO_PIN_PC23 (GPIO_PIOC_BASE + 23)
-#define GPIO_PIN_PC24 (GPIO_PIOC_BASE + 24)
-#define GPIO_PIN_PC25 (GPIO_PIOC_BASE + 25)
-#define GPIO_PIN_PC26 (GPIO_PIOC_BASE + 26)
-#define GPIO_PIN_PC27 (GPIO_PIOC_BASE + 27)
-#define GPIO_PIN_PC28 (GPIO_PIOC_BASE + 28)
-#define GPIO_PIN_PC29 (GPIO_PIOC_BASE + 29)
-#define GPIO_PIN_PC30 (GPIO_PIOC_BASE + 30)
-#define GPIO_PIN_PC31 (GPIO_PIOC_BASE + 31)
-
-#define GPIO_PIOD_BASE (GPIO_PIOC_BASE + 32)
-#define GPIO_PIN_PD0 (GPIO_PIOD_BASE + 0)
-#define GPIO_PIN_PD1 (GPIO_PIOD_BASE + 1)
-#define GPIO_PIN_PD2 (GPIO_PIOD_BASE + 2)
-#define GPIO_PIN_PD3 (GPIO_PIOD_BASE + 3)
-#define GPIO_PIN_PD4 (GPIO_PIOD_BASE + 4)
-#define GPIO_PIN_PD5 (GPIO_PIOD_BASE + 5)
-#define GPIO_PIN_PD6 (GPIO_PIOD_BASE + 6)
-#define GPIO_PIN_PD7 (GPIO_PIOD_BASE + 7)
-#define GPIO_PIN_PD8 (GPIO_PIOD_BASE + 8)
-#define GPIO_PIN_PD9 (GPIO_PIOD_BASE + 9)
-#define GPIO_PIN_PD10 (GPIO_PIOD_BASE + 10)
-#define GPIO_PIN_PD11 (GPIO_PIOD_BASE + 11)
-#define GPIO_PIN_PD12 (GPIO_PIOD_BASE + 12)
-#define GPIO_PIN_PD13 (GPIO_PIOD_BASE + 13)
-#define GPIO_PIN_PD14 (GPIO_PIOD_BASE + 14)
-#define GPIO_PIN_PD15 (GPIO_PIOD_BASE + 15)
-#define GPIO_PIN_PD16 (GPIO_PIOD_BASE + 16)
-#define GPIO_PIN_PD17 (GPIO_PIOD_BASE + 17)
-
-#define GPIO_PIOE_BASE (GPIO_PIOD_BASE + 32)
-#define GPIO_PIN_PE0 (GPIO_PIOE_BASE + 0)
-#define GPIO_PIN_PE1 (GPIO_PIOE_BASE + 1)
-#define GPIO_PIN_PE2 (GPIO_PIOE_BASE + 2)
-#define GPIO_PIN_PE3 (GPIO_PIOE_BASE + 3)
-#define GPIO_PIN_PE4 (GPIO_PIOE_BASE + 4)
-#define GPIO_PIN_PE5 (GPIO_PIOE_BASE + 5)
-#define GPIO_PIN_PE6 (GPIO_PIOE_BASE + 6)
-#define GPIO_PIN_PE7 (GPIO_PIOE_BASE + 7)
-#define GPIO_PIN_PE8 (GPIO_PIOE_BASE + 8)
-#define GPIO_PIN_PE9 (GPIO_PIOE_BASE + 9)
-#define GPIO_PIN_PE10 (GPIO_PIOE_BASE + 10)
-#define GPIO_PIN_PE11 (GPIO_PIOE_BASE + 11)
-#define GPIO_PIN_PE12 (GPIO_PIOE_BASE + 12)
-#define GPIO_PIN_PE13 (GPIO_PIOE_BASE + 13)
-#define GPIO_PIN_PE14 (GPIO_PIOE_BASE + 14)
-#define GPIO_PIN_PE15 (GPIO_PIOE_BASE + 15)
-#define GPIO_PIN_PE16 (GPIO_PIOE_BASE + 16)
-#define GPIO_PIN_PE17 (GPIO_PIOE_BASE + 17)
-#define GPIO_PIN_PE18 (GPIO_PIOE_BASE + 18)
-#define GPIO_PIN_PE19 (GPIO_PIOE_BASE + 19)
-#define GPIO_PIN_PE20 (GPIO_PIOE_BASE + 20)
-#define GPIO_PIN_PE21 (GPIO_PIOE_BASE + 21)
-#define GPIO_PIN_PE22 (GPIO_PIOE_BASE + 22)
-#define GPIO_PIN_PE23 (GPIO_PIOE_BASE + 23)
-#define GPIO_PIN_PE24 (GPIO_PIOE_BASE + 24)
-#define GPIO_PIN_PE25 (GPIO_PIOE_BASE + 25)
-#define GPIO_PIN_PE26 (GPIO_PIOE_BASE + 26)
-
-static inline void *gpio_pin_to_addr(unsigned int pin)
-{
- switch (pin >> 5) {
- case 0:
- return (void *)PIOA_BASE;
- case 1:
- return (void *)PIOB_BASE;
- case 2:
- return (void *)PIOC_BASE;
- case 3:
- return (void *)PIOD_BASE;
- case 4:
- return (void *)PIOE_BASE;
- default:
- return NULL;
- }
-}
-
-void gpio_select_periph_A(unsigned int pin, int use_pullup);
-void gpio_select_periph_B(unsigned int pin, int use_pullup);
-
-void gpio_enable_ebi(void);
-void gpio_enable_usart0(void);
-void gpio_enable_usart1(void);
-void gpio_enable_usart2(void);
-void gpio_enable_usart3(void);
-void gpio_enable_macb0(void);
-void gpio_enable_macb1(void);
-void gpio_enable_mmci(void);
-
-#endif /* __ASM_AVR32_ARCH_GPIO_H__ */
+++ /dev/null
-/*
- * Register definition for the High-speed Bus Matrix
- */
-#ifndef __ASM_AVR32_HMATRIX2_H__
-#define __ASM_AVR32_HMATRIX2_H__
-
-/* HMATRIX2 register offsets */
-#define HMATRIX2_MCFG0 0x0000
-#define HMATRIX2_MCFG1 0x0004
-#define HMATRIX2_MCFG2 0x0008
-#define HMATRIX2_MCFG3 0x000c
-#define HMATRIX2_MCFG4 0x0010
-#define HMATRIX2_MCFG5 0x0014
-#define HMATRIX2_MCFG6 0x0018
-#define HMATRIX2_MCFG7 0x001c
-#define HMATRIX2_MCFG8 0x0020
-#define HMATRIX2_MCFG9 0x0024
-#define HMATRIX2_MCFG10 0x0028
-#define HMATRIX2_MCFG11 0x002c
-#define HMATRIX2_MCFG12 0x0030
-#define HMATRIX2_MCFG13 0x0034
-#define HMATRIX2_MCFG14 0x0038
-#define HMATRIX2_MCFG15 0x003c
-#define HMATRIX2_SCFG0 0x0040
-#define HMATRIX2_SCFG1 0x0044
-#define HMATRIX2_SCFG2 0x0048
-#define HMATRIX2_SCFG3 0x004c
-#define HMATRIX2_SCFG4 0x0050
-#define HMATRIX2_SCFG5 0x0054
-#define HMATRIX2_SCFG6 0x0058
-#define HMATRIX2_SCFG7 0x005c
-#define HMATRIX2_SCFG8 0x0060
-#define HMATRIX2_SCFG9 0x0064
-#define HMATRIX2_SCFG10 0x0068
-#define HMATRIX2_SCFG11 0x006c
-#define HMATRIX2_SCFG12 0x0070
-#define HMATRIX2_SCFG13 0x0074
-#define HMATRIX2_SCFG14 0x0078
-#define HMATRIX2_SCFG15 0x007c
-#define HMATRIX2_PRAS0 0x0080
-#define HMATRIX2_PRBS0 0x0084
-#define HMATRIX2_PRAS1 0x0088
-#define HMATRIX2_PRBS1 0x008c
-#define HMATRIX2_PRAS2 0x0090
-#define HMATRIX2_PRBS2 0x0094
-#define HMATRIX2_PRAS3 0x0098
-#define HMATRIX2_PRBS3 0x009c
-#define HMATRIX2_PRAS4 0x00a0
-#define HMATRIX2_PRBS4 0x00a4
-#define HMATRIX2_PRAS5 0x00a8
-#define HMATRIX2_PRBS5 0x00ac
-#define HMATRIX2_PRAS6 0x00b0
-#define HMATRIX2_PRBS6 0x00b4
-#define HMATRIX2_PRAS7 0x00b8
-#define HMATRIX2_PRBS7 0x00bc
-#define HMATRIX2_PRAS8 0x00c0
-#define HMATRIX2_PRBS8 0x00c4
-#define HMATRIX2_PRAS9 0x00c8
-#define HMATRIX2_PRBS9 0x00cc
-#define HMATRIX2_PRAS10 0x00d0
-#define HMATRIX2_PRBS10 0x00d4
-#define HMATRIX2_PRAS11 0x00d8
-#define HMATRIX2_PRBS11 0x00dc
-#define HMATRIX2_PRAS12 0x00e0
-#define HMATRIX2_PRBS12 0x00e4
-#define HMATRIX2_PRAS13 0x00e8
-#define HMATRIX2_PRBS13 0x00ec
-#define HMATRIX2_PRAS14 0x00f0
-#define HMATRIX2_PRBS14 0x00f4
-#define HMATRIX2_PRAS15 0x00f8
-#define HMATRIX2_PRBS15 0x00fc
-#define HMATRIX2_MRCR 0x0100
-#define HMATRIX2_SFR0 0x0110
-#define HMATRIX2_SFR1 0x0114
-#define HMATRIX2_SFR2 0x0118
-#define HMATRIX2_SFR3 0x011c
-#define HMATRIX2_SFR4 0x0120
-#define HMATRIX2_SFR5 0x0124
-#define HMATRIX2_SFR6 0x0128
-#define HMATRIX2_SFR7 0x012c
-#define HMATRIX2_SFR8 0x0130
-#define HMATRIX2_SFR9 0x0134
-#define HMATRIX2_SFR10 0x0138
-#define HMATRIX2_SFR11 0x013c
-#define HMATRIX2_SFR12 0x0140
-#define HMATRIX2_SFR13 0x0144
-#define HMATRIX2_SFR14 0x0148
-#define HMATRIX2_SFR15 0x014c
-#define HMATRIX2_VERSION 0x01fc
-
-/* Bitfields in MCFG0 */
-#define HMATRIX2_ULBT_OFFSET 0
-#define HMATRIX2_ULBT_SIZE 3
-
-/* Bitfields in SCFG0 */
-#define HMATRIX2_SLOT_CYCLE_OFFSET 0
-#define HMATRIX2_SLOT_CYCLE_SIZE 8
-#define HMATRIX2_DEFMSTR_TYPE_OFFSET 16
-#define HMATRIX2_DEFMSTR_TYPE_SIZE 2
-#define HMATRIX2_FIXED_DEFMSTR_OFFSET 18
-#define HMATRIX2_FIXED_DEFMSTR_SIZE 4
-#define HMATRIX2_ARBT_OFFSET 24
-#define HMATRIX2_ARBT_SIZE 2
-
-/* Bitfields in PRAS0 */
-#define HMATRIX2_M0PR_OFFSET 0
-#define HMATRIX2_M0PR_SIZE 4
-#define HMATRIX2_M1PR_OFFSET 4
-#define HMATRIX2_M1PR_SIZE 4
-#define HMATRIX2_M2PR_OFFSET 8
-#define HMATRIX2_M2PR_SIZE 4
-#define HMATRIX2_M3PR_OFFSET 12
-#define HMATRIX2_M3PR_SIZE 4
-#define HMATRIX2_M4PR_OFFSET 16
-#define HMATRIX2_M4PR_SIZE 4
-#define HMATRIX2_M5PR_OFFSET 20
-#define HMATRIX2_M5PR_SIZE 4
-#define HMATRIX2_M6PR_OFFSET 24
-#define HMATRIX2_M6PR_SIZE 4
-#define HMATRIX2_M7PR_OFFSET 28
-#define HMATRIX2_M7PR_SIZE 4
-
-/* Bitfields in PRBS0 */
-#define HMATRIX2_M8PR_OFFSET 0
-#define HMATRIX2_M8PR_SIZE 4
-#define HMATRIX2_M9PR_OFFSET 4
-#define HMATRIX2_M9PR_SIZE 4
-#define HMATRIX2_M10PR_OFFSET 8
-#define HMATRIX2_M10PR_SIZE 4
-#define HMATRIX2_M11PR_OFFSET 12
-#define HMATRIX2_M11PR_SIZE 4
-#define HMATRIX2_M12PR_OFFSET 16
-#define HMATRIX2_M12PR_SIZE 4
-#define HMATRIX2_M13PR_OFFSET 20
-#define HMATRIX2_M13PR_SIZE 4
-#define HMATRIX2_M14PR_OFFSET 24
-#define HMATRIX2_M14PR_SIZE 4
-#define HMATRIX2_M15PR_OFFSET 28
-#define HMATRIX2_M15PR_SIZE 4
-
-/* Bitfields in MRCR */
-#define HMATRIX2_RBC0_OFFSET 0
-#define HMATRIX2_RBC0_SIZE 1
-#define HMATRIX2_RBC1_OFFSET 1
-#define HMATRIX2_RBC1_SIZE 1
-#define HMATRIX2_RBC2_OFFSET 2
-#define HMATRIX2_RBC2_SIZE 1
-#define HMATRIX2_RBC3_OFFSET 3
-#define HMATRIX2_RBC3_SIZE 1
-#define HMATRIX2_RBC4_OFFSET 4
-#define HMATRIX2_RBC4_SIZE 1
-#define HMATRIX2_RBC5_OFFSET 5
-#define HMATRIX2_RBC5_SIZE 1
-#define HMATRIX2_RBC6_OFFSET 6
-#define HMATRIX2_RBC6_SIZE 1
-#define HMATRIX2_RBC7_OFFSET 7
-#define HMATRIX2_RBC7_SIZE 1
-#define HMATRIX2_RBC8_OFFSET 8
-#define HMATRIX2_RBC8_SIZE 1
-#define HMATRIX2_RBC9_OFFSET 9
-#define HMATRIX2_RBC9_SIZE 1
-#define HMATRIX2_RBC10_OFFSET 10
-#define HMATRIX2_RBC10_SIZE 1
-#define HMATRIX2_RBC11_OFFSET 11
-#define HMATRIX2_RBC11_SIZE 1
-#define HMATRIX2_RBC12_OFFSET 12
-#define HMATRIX2_RBC12_SIZE 1
-#define HMATRIX2_RBC13_OFFSET 13
-#define HMATRIX2_RBC13_SIZE 1
-#define HMATRIX2_RBC14_OFFSET 14
-#define HMATRIX2_RBC14_SIZE 1
-#define HMATRIX2_RBC15_OFFSET 15
-#define HMATRIX2_RBC15_SIZE 1
-
-/* Bitfields in SFR0 */
-#define HMATRIX2_SFR_OFFSET 0
-#define HMATRIX2_SFR_SIZE 32
-
-/* Bitfields in SFR4 */
-#define HMATRIX2_CS1A_OFFSET 1
-#define HMATRIX2_CS1A_SIZE 1
-#define HMATRIX2_CS3A_OFFSET 3
-#define HMATRIX2_CS3A_SIZE 1
-#define HMATRIX2_CS4A_OFFSET 4
-#define HMATRIX2_CS4A_SIZE 1
-#define HMATRIX2_CS5A_OFFSET 5
-#define HMATRIX2_CS5A_SIZE 1
-#define HMATRIX2_DBPUC_OFFSET 8
-#define HMATRIX2_DBPUC_SIZE 1
-
-/* Bitfields in VERSION */
-#define HMATRIX2_VERSION_OFFSET 0
-#define HMATRIX2_VERSION_SIZE 12
-#define HMATRIX2_MFN_OFFSET 16
-#define HMATRIX2_MFN_SIZE 3
-
-/* Constants for ULBT */
-#define HMATRIX2_ULBT_INFINITE 0
-#define HMATRIX2_ULBT_SINGLE 1
-#define HMATRIX2_ULBT_FOUR_BEAT 2
-#define HMATRIX2_ULBT_SIXTEEN_BEAT 4
-
-/* Constants for DEFMSTR_TYPE */
-#define HMATRIX2_DEFMSTR_TYPE_NO_DEFAULT 0
-#define HMATRIX2_DEFMSTR_TYPE_LAST_DEFAULT 1
-#define HMATRIX2_DEFMSTR_TYPE_FIXED_DEFAULT 2
-
-/* Constants for ARBT */
-#define HMATRIX2_ARBT_ROUND_ROBIN 0
-#define HMATRIX2_ARBT_FIXED_PRIORITY 1
-
-/* Bit manipulation macros */
-#define HMATRIX2_BIT(name) \
- (1 << HMATRIX2_##name##_OFFSET)
-#define HMATRIX2_BF(name,value) \
- (((value) & ((1 << HMATRIX2_##name##_SIZE) - 1)) \
- << HMATRIX2_##name##_OFFSET)
-#define HMATRIX2_BFEXT(name,value) \
- (((value) >> HMATRIX2_##name##_OFFSET) \
- & ((1 << HMATRIX2_##name##_SIZE) - 1))
-#define HMATRIX2_BFINS(name,value,old) \
- (((old) & ~(((1 << HMATRIX2_##name##_SIZE) - 1) \
- << HMATRIX2_##name##_OFFSET)) \
- | HMATRIX2_BF(name,value))
-
-/* Register access macros */
-#define hmatrix2_readl(reg) \
- readl((void *)HMATRIX_BASE + HMATRIX2_##reg)
-#define hmatrix2_writel(reg,value) \
- writel((value), (void *)HMATRIX_BASE + HMATRIX2_##reg)
-
-#endif /* __ASM_AVR32_HMATRIX2_H__ */
+++ /dev/null
-/*
- * Copyright (C) 2005-2006 Atmel Corporation
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef __AT32AP7000_MEMORY_MAP_H__
-#define __AT32AP7000_MEMORY_MAP_H__
-
-/* Devices on the High Speed Bus (HSB) */
-#define LCDC_BASE 0xFF000000
-#define DMAC_BASE 0xFF200000
-#define USB_FIFO 0xFF300000
-
-/* Devices on Peripheral Bus A (PBA) */
-#define SPI0_BASE 0xFFE00000
-#define SPI1_BASE 0xFFE00400
-#define TWI_BASE 0xFFE00800
-#define USART0_BASE 0xFFE00C00
-#define USART1_BASE 0xFFE01000
-#define USART2_BASE 0xFFE01400
-#define USART3_BASE 0xFFE01800
-#define SSC0_BASE 0xFFE01C00
-#define SSC1_BASE 0xFFE02000
-#define SSC2_BASE 0xFFE02400
-#define PIOA_BASE 0xFFE02800
-#define PIOB_BASE 0xFFE02C00
-#define PIOC_BASE 0xFFE03000
-#define PIOD_BASE 0xFFE03400
-#define PIOE_BASE 0xFFE03800
-#define PSIF_BASE 0xFFE03C00
-
-/* Devices on Peripheral Bus B (PBB) */
-#define SM_BASE 0xFFF00000
-#define INTC_BASE 0xFFF00400
-#define HMATRIX_BASE 0xFFF00800
-#define TIMER0_BASE 0xFFF00C00
-#define TIMER1_BASE 0xFFF01000
-#define PWM_BASE 0xFFF01400
-#define MACB0_BASE 0xFFF01800
-#define MACB1_BASE 0xFFF01C00
-#define DAC_BASE 0xFFF02000
-#define MMCI_BASE 0xFFF02400
-#define AUDIOC_BASE 0xFFF02800
-#define HISI_BASE 0xFFF02C00
-#define USB_BASE 0xFFF03000
-#define HSMC_BASE 0xFFF03400
-#define HSDRAMC_BASE 0xFFF03800
-#define ECC_BASE 0xFFF03C00
-
-#endif /* __AT32AP7000_MEMORY_MAP_H__ */
+++ /dev/null
-/*
- * Copyright (C) 2004-2006 Atmel Corporation
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef __ASM_AVR32_MMC_H
-#define __ASM_AVR32_MMC_H
-
-struct mmc_cid {
- unsigned long psn;
- unsigned short oid;
- unsigned char mid;
- unsigned char prv;
- unsigned char mdt;
- char pnm[7];
-};
-
-struct mmc_csd
-{
- u8 csd_structure:2,
- spec_vers:4,
- rsvd1:2;
- u8 taac;
- u8 nsac;
- u8 tran_speed;
- u16 ccc:12,
- read_bl_len:4;
- u64 read_bl_partial:1,
- write_blk_misalign:1,
- read_blk_misalign:1,
- dsr_imp:1,
- rsvd2:2,
- c_size:12,
- vdd_r_curr_min:3,
- vdd_r_curr_max:3,
- vdd_w_curr_min:3,
- vdd_w_curr_max:3,
- c_size_mult:3,
- sector_size:5,
- erase_grp_size:5,
- wp_grp_size:5,
- wp_grp_enable:1,
- default_ecc:2,
- r2w_factor:3,
- write_bl_len:4,
- write_bl_partial:1,
- rsvd3:5;
- u8 file_format_grp:1,
- copy:1,
- perm_write_protect:1,
- tmp_write_protect:1,
- file_format:2,
- ecc:2;
- u8 crc:7;
- u8 one:1;
-};
-
-/* MMC Command numbers */
-#define MMC_CMD_GO_IDLE_STATE 0
-#define MMC_CMD_SEND_OP_COND 1
-#define MMC_CMD_ALL_SEND_CID 2
-#define MMC_CMD_SET_RELATIVE_ADDR 3
-#define MMC_CMD_SD_SEND_RELATIVE_ADDR 3
-#define MMC_CMD_SET_DSR 4
-#define MMC_CMD_SELECT_CARD 7
-#define MMC_CMD_SEND_CSD 9
-#define MMC_CMD_SEND_CID 10
-#define MMC_CMD_SEND_STATUS 13
-#define MMC_CMD_SET_BLOCKLEN 16
-#define MMC_CMD_READ_SINGLE_BLOCK 17
-#define MMC_CMD_READ_MULTIPLE_BLOCK 18
-#define MMC_CMD_WRITE_BLOCK 24
-#define MMC_CMD_APP_CMD 55
-
-#define MMC_ACMD_SD_SEND_OP_COND 41
-
-#define R1_ILLEGAL_COMMAND (1 << 22)
-#define R1_APP_CMD (1 << 5)
-
-#endif /* __ASM_AVR32_MMC_H */
--- /dev/null
+/*
+ * Copyright (C) 2007 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_ARCH_CHIP_FEATURES_H__
+#define __ASM_AVR32_ARCH_CHIP_FEATURES_H__
+
+/* Currently, all the AP700x chips have these */
+#define AT32AP700x_CHIP_HAS_USART
+#define AT32AP700x_CHIP_HAS_MMCI
+
+/* Only AP7000 has ethernet interface */
+#ifdef CONFIG_AT32AP7000
+#define AT32AP700x_CHIP_HAS_MACB
+#endif
+
+#endif /* __ASM_AVR32_ARCH_CHIP_FEATURES_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_ARCH_CLK_H__
+#define __ASM_AVR32_ARCH_CLK_H__
+
+#include <asm/arch/chip-features.h>
+
+#ifdef CONFIG_PLL
+#define MAIN_CLK_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL)
+#else
+#define MAIN_CLK_RATE (CFG_OSC0_HZ)
+#endif
+
+static inline unsigned long get_cpu_clk_rate(void)
+{
+ return MAIN_CLK_RATE >> CFG_CLKDIV_CPU;
+}
+static inline unsigned long get_hsb_clk_rate(void)
+{
+ return MAIN_CLK_RATE >> CFG_CLKDIV_HSB;
+}
+static inline unsigned long get_pba_clk_rate(void)
+{
+ return MAIN_CLK_RATE >> CFG_CLKDIV_PBA;
+}
+static inline unsigned long get_pbb_clk_rate(void)
+{
+ return MAIN_CLK_RATE >> CFG_CLKDIV_PBB;
+}
+
+/* Accessors for specific devices. More will be added as needed. */
+static inline unsigned long get_sdram_clk_rate(void)
+{
+ return get_hsb_clk_rate();
+}
+#ifdef AT32AP700x_CHIP_HAS_USART
+static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
+{
+ return get_pba_clk_rate();
+}
+#endif
+#ifdef AT32AP700x_CHIP_HAS_USART
+static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
+{
+ return get_pbb_clk_rate();
+}
+static inline unsigned long get_macb_hclk_rate(unsigned int dev_id)
+{
+ return get_hsb_clk_rate();
+}
+#endif
+#ifdef AT32AP700x_CHIP_HAS_MMCI
+static inline unsigned long get_mci_clk_rate(void)
+{
+ return get_pbb_clk_rate();
+}
+#endif
+
+#endif /* __ASM_AVR32_ARCH_CLK_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_ARCH_GPIO_H__
+#define __ASM_AVR32_ARCH_GPIO_H__
+
+#include <asm/arch/chip-features.h>
+#include <asm/arch/memory-map.h>
+
+#define NR_GPIO_CONTROLLERS 5
+
+/*
+ * Pin numbers identifying specific GPIO pins on the chip.
+ */
+#define GPIO_PIOA_BASE (0)
+#define GPIO_PIN_PA0 (GPIO_PIOA_BASE + 0)
+#define GPIO_PIN_PA1 (GPIO_PIOA_BASE + 1)
+#define GPIO_PIN_PA2 (GPIO_PIOA_BASE + 2)
+#define GPIO_PIN_PA3 (GPIO_PIOA_BASE + 3)
+#define GPIO_PIN_PA4 (GPIO_PIOA_BASE + 4)
+#define GPIO_PIN_PA5 (GPIO_PIOA_BASE + 5)
+#define GPIO_PIN_PA6 (GPIO_PIOA_BASE + 6)
+#define GPIO_PIN_PA7 (GPIO_PIOA_BASE + 7)
+#define GPIO_PIN_PA8 (GPIO_PIOA_BASE + 8)
+#define GPIO_PIN_PA9 (GPIO_PIOA_BASE + 9)
+#define GPIO_PIN_PA10 (GPIO_PIOA_BASE + 10)
+#define GPIO_PIN_PA11 (GPIO_PIOA_BASE + 11)
+#define GPIO_PIN_PA12 (GPIO_PIOA_BASE + 12)
+#define GPIO_PIN_PA13 (GPIO_PIOA_BASE + 13)
+#define GPIO_PIN_PA14 (GPIO_PIOA_BASE + 14)
+#define GPIO_PIN_PA15 (GPIO_PIOA_BASE + 15)
+#define GPIO_PIN_PA16 (GPIO_PIOA_BASE + 16)
+#define GPIO_PIN_PA17 (GPIO_PIOA_BASE + 17)
+#define GPIO_PIN_PA18 (GPIO_PIOA_BASE + 18)
+#define GPIO_PIN_PA19 (GPIO_PIOA_BASE + 19)
+#define GPIO_PIN_PA20 (GPIO_PIOA_BASE + 20)
+#define GPIO_PIN_PA21 (GPIO_PIOA_BASE + 21)
+#define GPIO_PIN_PA22 (GPIO_PIOA_BASE + 22)
+#define GPIO_PIN_PA23 (GPIO_PIOA_BASE + 23)
+#define GPIO_PIN_PA24 (GPIO_PIOA_BASE + 24)
+#define GPIO_PIN_PA25 (GPIO_PIOA_BASE + 25)
+#define GPIO_PIN_PA26 (GPIO_PIOA_BASE + 26)
+#define GPIO_PIN_PA27 (GPIO_PIOA_BASE + 27)
+#define GPIO_PIN_PA28 (GPIO_PIOA_BASE + 28)
+#define GPIO_PIN_PA29 (GPIO_PIOA_BASE + 29)
+#define GPIO_PIN_PA30 (GPIO_PIOA_BASE + 30)
+#define GPIO_PIN_PA31 (GPIO_PIOA_BASE + 31)
+
+#define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32)
+#define GPIO_PIN_PB0 (GPIO_PIOB_BASE + 0)
+#define GPIO_PIN_PB1 (GPIO_PIOB_BASE + 1)
+#define GPIO_PIN_PB2 (GPIO_PIOB_BASE + 2)
+#define GPIO_PIN_PB3 (GPIO_PIOB_BASE + 3)
+#define GPIO_PIN_PB4 (GPIO_PIOB_BASE + 4)
+#define GPIO_PIN_PB5 (GPIO_PIOB_BASE + 5)
+#define GPIO_PIN_PB6 (GPIO_PIOB_BASE + 6)
+#define GPIO_PIN_PB7 (GPIO_PIOB_BASE + 7)
+#define GPIO_PIN_PB8 (GPIO_PIOB_BASE + 8)
+#define GPIO_PIN_PB9 (GPIO_PIOB_BASE + 9)
+#define GPIO_PIN_PB10 (GPIO_PIOB_BASE + 10)
+#define GPIO_PIN_PB11 (GPIO_PIOB_BASE + 11)
+#define GPIO_PIN_PB12 (GPIO_PIOB_BASE + 12)
+#define GPIO_PIN_PB13 (GPIO_PIOB_BASE + 13)
+#define GPIO_PIN_PB14 (GPIO_PIOB_BASE + 14)
+#define GPIO_PIN_PB15 (GPIO_PIOB_BASE + 15)
+#define GPIO_PIN_PB16 (GPIO_PIOB_BASE + 16)
+#define GPIO_PIN_PB17 (GPIO_PIOB_BASE + 17)
+#define GPIO_PIN_PB18 (GPIO_PIOB_BASE + 18)
+#define GPIO_PIN_PB19 (GPIO_PIOB_BASE + 19)
+#define GPIO_PIN_PB20 (GPIO_PIOB_BASE + 20)
+#define GPIO_PIN_PB21 (GPIO_PIOB_BASE + 21)
+#define GPIO_PIN_PB22 (GPIO_PIOB_BASE + 22)
+#define GPIO_PIN_PB23 (GPIO_PIOB_BASE + 23)
+#define GPIO_PIN_PB24 (GPIO_PIOB_BASE + 24)
+#define GPIO_PIN_PB25 (GPIO_PIOB_BASE + 25)
+#define GPIO_PIN_PB26 (GPIO_PIOB_BASE + 26)
+#define GPIO_PIN_PB27 (GPIO_PIOB_BASE + 27)
+#define GPIO_PIN_PB28 (GPIO_PIOB_BASE + 28)
+#define GPIO_PIN_PB29 (GPIO_PIOB_BASE + 29)
+#define GPIO_PIN_PB30 (GPIO_PIOB_BASE + 30)
+
+#define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32)
+#define GPIO_PIN_PC0 (GPIO_PIOC_BASE + 0)
+#define GPIO_PIN_PC1 (GPIO_PIOC_BASE + 1)
+#define GPIO_PIN_PC2 (GPIO_PIOC_BASE + 2)
+#define GPIO_PIN_PC3 (GPIO_PIOC_BASE + 3)
+#define GPIO_PIN_PC4 (GPIO_PIOC_BASE + 4)
+#define GPIO_PIN_PC5 (GPIO_PIOC_BASE + 5)
+#define GPIO_PIN_PC6 (GPIO_PIOC_BASE + 6)
+#define GPIO_PIN_PC7 (GPIO_PIOC_BASE + 7)
+#define GPIO_PIN_PC8 (GPIO_PIOC_BASE + 8)
+#define GPIO_PIN_PC9 (GPIO_PIOC_BASE + 9)
+#define GPIO_PIN_PC10 (GPIO_PIOC_BASE + 10)
+#define GPIO_PIN_PC11 (GPIO_PIOC_BASE + 11)
+#define GPIO_PIN_PC12 (GPIO_PIOC_BASE + 12)
+#define GPIO_PIN_PC13 (GPIO_PIOC_BASE + 13)
+#define GPIO_PIN_PC14 (GPIO_PIOC_BASE + 14)
+#define GPIO_PIN_PC15 (GPIO_PIOC_BASE + 15)
+#define GPIO_PIN_PC16 (GPIO_PIOC_BASE + 16)
+#define GPIO_PIN_PC17 (GPIO_PIOC_BASE + 17)
+#define GPIO_PIN_PC18 (GPIO_PIOC_BASE + 18)
+#define GPIO_PIN_PC19 (GPIO_PIOC_BASE + 19)
+#define GPIO_PIN_PC20 (GPIO_PIOC_BASE + 20)
+#define GPIO_PIN_PC21 (GPIO_PIOC_BASE + 21)
+#define GPIO_PIN_PC22 (GPIO_PIOC_BASE + 22)
+#define GPIO_PIN_PC23 (GPIO_PIOC_BASE + 23)
+#define GPIO_PIN_PC24 (GPIO_PIOC_BASE + 24)
+#define GPIO_PIN_PC25 (GPIO_PIOC_BASE + 25)
+#define GPIO_PIN_PC26 (GPIO_PIOC_BASE + 26)
+#define GPIO_PIN_PC27 (GPIO_PIOC_BASE + 27)
+#define GPIO_PIN_PC28 (GPIO_PIOC_BASE + 28)
+#define GPIO_PIN_PC29 (GPIO_PIOC_BASE + 29)
+#define GPIO_PIN_PC30 (GPIO_PIOC_BASE + 30)
+#define GPIO_PIN_PC31 (GPIO_PIOC_BASE + 31)
+
+#define GPIO_PIOD_BASE (GPIO_PIOC_BASE + 32)
+#define GPIO_PIN_PD0 (GPIO_PIOD_BASE + 0)
+#define GPIO_PIN_PD1 (GPIO_PIOD_BASE + 1)
+#define GPIO_PIN_PD2 (GPIO_PIOD_BASE + 2)
+#define GPIO_PIN_PD3 (GPIO_PIOD_BASE + 3)
+#define GPIO_PIN_PD4 (GPIO_PIOD_BASE + 4)
+#define GPIO_PIN_PD5 (GPIO_PIOD_BASE + 5)
+#define GPIO_PIN_PD6 (GPIO_PIOD_BASE + 6)
+#define GPIO_PIN_PD7 (GPIO_PIOD_BASE + 7)
+#define GPIO_PIN_PD8 (GPIO_PIOD_BASE + 8)
+#define GPIO_PIN_PD9 (GPIO_PIOD_BASE + 9)
+#define GPIO_PIN_PD10 (GPIO_PIOD_BASE + 10)
+#define GPIO_PIN_PD11 (GPIO_PIOD_BASE + 11)
+#define GPIO_PIN_PD12 (GPIO_PIOD_BASE + 12)
+#define GPIO_PIN_PD13 (GPIO_PIOD_BASE + 13)
+#define GPIO_PIN_PD14 (GPIO_PIOD_BASE + 14)
+#define GPIO_PIN_PD15 (GPIO_PIOD_BASE + 15)
+#define GPIO_PIN_PD16 (GPIO_PIOD_BASE + 16)
+#define GPIO_PIN_PD17 (GPIO_PIOD_BASE + 17)
+
+#define GPIO_PIOE_BASE (GPIO_PIOD_BASE + 32)
+#define GPIO_PIN_PE0 (GPIO_PIOE_BASE + 0)
+#define GPIO_PIN_PE1 (GPIO_PIOE_BASE + 1)
+#define GPIO_PIN_PE2 (GPIO_PIOE_BASE + 2)
+#define GPIO_PIN_PE3 (GPIO_PIOE_BASE + 3)
+#define GPIO_PIN_PE4 (GPIO_PIOE_BASE + 4)
+#define GPIO_PIN_PE5 (GPIO_PIOE_BASE + 5)
+#define GPIO_PIN_PE6 (GPIO_PIOE_BASE + 6)
+#define GPIO_PIN_PE7 (GPIO_PIOE_BASE + 7)
+#define GPIO_PIN_PE8 (GPIO_PIOE_BASE + 8)
+#define GPIO_PIN_PE9 (GPIO_PIOE_BASE + 9)
+#define GPIO_PIN_PE10 (GPIO_PIOE_BASE + 10)
+#define GPIO_PIN_PE11 (GPIO_PIOE_BASE + 11)
+#define GPIO_PIN_PE12 (GPIO_PIOE_BASE + 12)
+#define GPIO_PIN_PE13 (GPIO_PIOE_BASE + 13)
+#define GPIO_PIN_PE14 (GPIO_PIOE_BASE + 14)
+#define GPIO_PIN_PE15 (GPIO_PIOE_BASE + 15)
+#define GPIO_PIN_PE16 (GPIO_PIOE_BASE + 16)
+#define GPIO_PIN_PE17 (GPIO_PIOE_BASE + 17)
+#define GPIO_PIN_PE18 (GPIO_PIOE_BASE + 18)
+#define GPIO_PIN_PE19 (GPIO_PIOE_BASE + 19)
+#define GPIO_PIN_PE20 (GPIO_PIOE_BASE + 20)
+#define GPIO_PIN_PE21 (GPIO_PIOE_BASE + 21)
+#define GPIO_PIN_PE22 (GPIO_PIOE_BASE + 22)
+#define GPIO_PIN_PE23 (GPIO_PIOE_BASE + 23)
+#define GPIO_PIN_PE24 (GPIO_PIOE_BASE + 24)
+#define GPIO_PIN_PE25 (GPIO_PIOE_BASE + 25)
+#define GPIO_PIN_PE26 (GPIO_PIOE_BASE + 26)
+
+static inline void *gpio_pin_to_addr(unsigned int pin)
+{
+ switch (pin >> 5) {
+ case 0:
+ return (void *)PIOA_BASE;
+ case 1:
+ return (void *)PIOB_BASE;
+ case 2:
+ return (void *)PIOC_BASE;
+ case 3:
+ return (void *)PIOD_BASE;
+ case 4:
+ return (void *)PIOE_BASE;
+ default:
+ return NULL;
+ }
+}
+
+void gpio_select_periph_A(unsigned int pin, int use_pullup);
+void gpio_select_periph_B(unsigned int pin, int use_pullup);
+
+void gpio_enable_ebi(void);
+
+#ifdef AT32AP700x_CHIP_HAS_USART
+void gpio_enable_usart0(void);
+void gpio_enable_usart1(void);
+void gpio_enable_usart2(void);
+void gpio_enable_usart3(void);
+#endif
+#ifdef AT32AP700x_CHIP_HAS_MACB
+void gpio_enable_macb0(void);
+void gpio_enable_macb1(void);
+#endif
+#ifdef AT32AP700x_CHIP_HAS_MMCI
+void gpio_enable_mmci(void);
+#endif
+
+#endif /* __ASM_AVR32_ARCH_GPIO_H__ */
--- /dev/null
+/*
+ * Register definition for the High-speed Bus Matrix
+ */
+#ifndef __ASM_AVR32_HMATRIX2_H__
+#define __ASM_AVR32_HMATRIX2_H__
+
+/* HMATRIX2 register offsets */
+#define HMATRIX2_MCFG0 0x0000
+#define HMATRIX2_MCFG1 0x0004
+#define HMATRIX2_MCFG2 0x0008
+#define HMATRIX2_MCFG3 0x000c
+#define HMATRIX2_MCFG4 0x0010
+#define HMATRIX2_MCFG5 0x0014
+#define HMATRIX2_MCFG6 0x0018
+#define HMATRIX2_MCFG7 0x001c
+#define HMATRIX2_MCFG8 0x0020
+#define HMATRIX2_MCFG9 0x0024
+#define HMATRIX2_MCFG10 0x0028
+#define HMATRIX2_MCFG11 0x002c
+#define HMATRIX2_MCFG12 0x0030
+#define HMATRIX2_MCFG13 0x0034
+#define HMATRIX2_MCFG14 0x0038
+#define HMATRIX2_MCFG15 0x003c
+#define HMATRIX2_SCFG0 0x0040
+#define HMATRIX2_SCFG1 0x0044
+#define HMATRIX2_SCFG2 0x0048
+#define HMATRIX2_SCFG3 0x004c
+#define HMATRIX2_SCFG4 0x0050
+#define HMATRIX2_SCFG5 0x0054
+#define HMATRIX2_SCFG6 0x0058
+#define HMATRIX2_SCFG7 0x005c
+#define HMATRIX2_SCFG8 0x0060
+#define HMATRIX2_SCFG9 0x0064
+#define HMATRIX2_SCFG10 0x0068
+#define HMATRIX2_SCFG11 0x006c
+#define HMATRIX2_SCFG12 0x0070
+#define HMATRIX2_SCFG13 0x0074
+#define HMATRIX2_SCFG14 0x0078
+#define HMATRIX2_SCFG15 0x007c
+#define HMATRIX2_PRAS0 0x0080
+#define HMATRIX2_PRBS0 0x0084
+#define HMATRIX2_PRAS1 0x0088
+#define HMATRIX2_PRBS1 0x008c
+#define HMATRIX2_PRAS2 0x0090
+#define HMATRIX2_PRBS2 0x0094
+#define HMATRIX2_PRAS3 0x0098
+#define HMATRIX2_PRBS3 0x009c
+#define HMATRIX2_PRAS4 0x00a0
+#define HMATRIX2_PRBS4 0x00a4
+#define HMATRIX2_PRAS5 0x00a8
+#define HMATRIX2_PRBS5 0x00ac
+#define HMATRIX2_PRAS6 0x00b0
+#define HMATRIX2_PRBS6 0x00b4
+#define HMATRIX2_PRAS7 0x00b8
+#define HMATRIX2_PRBS7 0x00bc
+#define HMATRIX2_PRAS8 0x00c0
+#define HMATRIX2_PRBS8 0x00c4
+#define HMATRIX2_PRAS9 0x00c8
+#define HMATRIX2_PRBS9 0x00cc
+#define HMATRIX2_PRAS10 0x00d0
+#define HMATRIX2_PRBS10 0x00d4
+#define HMATRIX2_PRAS11 0x00d8
+#define HMATRIX2_PRBS11 0x00dc
+#define HMATRIX2_PRAS12 0x00e0
+#define HMATRIX2_PRBS12 0x00e4
+#define HMATRIX2_PRAS13 0x00e8
+#define HMATRIX2_PRBS13 0x00ec
+#define HMATRIX2_PRAS14 0x00f0
+#define HMATRIX2_PRBS14 0x00f4
+#define HMATRIX2_PRAS15 0x00f8
+#define HMATRIX2_PRBS15 0x00fc
+#define HMATRIX2_MRCR 0x0100
+#define HMATRIX2_SFR0 0x0110
+#define HMATRIX2_SFR1 0x0114
+#define HMATRIX2_SFR2 0x0118
+#define HMATRIX2_SFR3 0x011c
+#define HMATRIX2_SFR4 0x0120
+#define HMATRIX2_SFR5 0x0124
+#define HMATRIX2_SFR6 0x0128
+#define HMATRIX2_SFR7 0x012c
+#define HMATRIX2_SFR8 0x0130
+#define HMATRIX2_SFR9 0x0134
+#define HMATRIX2_SFR10 0x0138
+#define HMATRIX2_SFR11 0x013c
+#define HMATRIX2_SFR12 0x0140
+#define HMATRIX2_SFR13 0x0144
+#define HMATRIX2_SFR14 0x0148
+#define HMATRIX2_SFR15 0x014c
+#define HMATRIX2_VERSION 0x01fc
+
+/* Bitfields in MCFG0 */
+#define HMATRIX2_ULBT_OFFSET 0
+#define HMATRIX2_ULBT_SIZE 3
+
+/* Bitfields in SCFG0 */
+#define HMATRIX2_SLOT_CYCLE_OFFSET 0
+#define HMATRIX2_SLOT_CYCLE_SIZE 8
+#define HMATRIX2_DEFMSTR_TYPE_OFFSET 16
+#define HMATRIX2_DEFMSTR_TYPE_SIZE 2
+#define HMATRIX2_FIXED_DEFMSTR_OFFSET 18
+#define HMATRIX2_FIXED_DEFMSTR_SIZE 4
+#define HMATRIX2_ARBT_OFFSET 24
+#define HMATRIX2_ARBT_SIZE 2
+
+/* Bitfields in PRAS0 */
+#define HMATRIX2_M0PR_OFFSET 0
+#define HMATRIX2_M0PR_SIZE 4
+#define HMATRIX2_M1PR_OFFSET 4
+#define HMATRIX2_M1PR_SIZE 4
+#define HMATRIX2_M2PR_OFFSET 8
+#define HMATRIX2_M2PR_SIZE 4
+#define HMATRIX2_M3PR_OFFSET 12
+#define HMATRIX2_M3PR_SIZE 4
+#define HMATRIX2_M4PR_OFFSET 16
+#define HMATRIX2_M4PR_SIZE 4
+#define HMATRIX2_M5PR_OFFSET 20
+#define HMATRIX2_M5PR_SIZE 4
+#define HMATRIX2_M6PR_OFFSET 24
+#define HMATRIX2_M6PR_SIZE 4
+#define HMATRIX2_M7PR_OFFSET 28
+#define HMATRIX2_M7PR_SIZE 4
+
+/* Bitfields in PRBS0 */
+#define HMATRIX2_M8PR_OFFSET 0
+#define HMATRIX2_M8PR_SIZE 4
+#define HMATRIX2_M9PR_OFFSET 4
+#define HMATRIX2_M9PR_SIZE 4
+#define HMATRIX2_M10PR_OFFSET 8
+#define HMATRIX2_M10PR_SIZE 4
+#define HMATRIX2_M11PR_OFFSET 12
+#define HMATRIX2_M11PR_SIZE 4
+#define HMATRIX2_M12PR_OFFSET 16
+#define HMATRIX2_M12PR_SIZE 4
+#define HMATRIX2_M13PR_OFFSET 20
+#define HMATRIX2_M13PR_SIZE 4
+#define HMATRIX2_M14PR_OFFSET 24
+#define HMATRIX2_M14PR_SIZE 4
+#define HMATRIX2_M15PR_OFFSET 28
+#define HMATRIX2_M15PR_SIZE 4
+
+/* Bitfields in MRCR */
+#define HMATRIX2_RBC0_OFFSET 0
+#define HMATRIX2_RBC0_SIZE 1
+#define HMATRIX2_RBC1_OFFSET 1
+#define HMATRIX2_RBC1_SIZE 1
+#define HMATRIX2_RBC2_OFFSET 2
+#define HMATRIX2_RBC2_SIZE 1
+#define HMATRIX2_RBC3_OFFSET 3
+#define HMATRIX2_RBC3_SIZE 1
+#define HMATRIX2_RBC4_OFFSET 4
+#define HMATRIX2_RBC4_SIZE 1
+#define HMATRIX2_RBC5_OFFSET 5
+#define HMATRIX2_RBC5_SIZE 1
+#define HMATRIX2_RBC6_OFFSET 6
+#define HMATRIX2_RBC6_SIZE 1
+#define HMATRIX2_RBC7_OFFSET 7
+#define HMATRIX2_RBC7_SIZE 1
+#define HMATRIX2_RBC8_OFFSET 8
+#define HMATRIX2_RBC8_SIZE 1
+#define HMATRIX2_RBC9_OFFSET 9
+#define HMATRIX2_RBC9_SIZE 1
+#define HMATRIX2_RBC10_OFFSET 10
+#define HMATRIX2_RBC10_SIZE 1
+#define HMATRIX2_RBC11_OFFSET 11
+#define HMATRIX2_RBC11_SIZE 1
+#define HMATRIX2_RBC12_OFFSET 12
+#define HMATRIX2_RBC12_SIZE 1
+#define HMATRIX2_RBC13_OFFSET 13
+#define HMATRIX2_RBC13_SIZE 1
+#define HMATRIX2_RBC14_OFFSET 14
+#define HMATRIX2_RBC14_SIZE 1
+#define HMATRIX2_RBC15_OFFSET 15
+#define HMATRIX2_RBC15_SIZE 1
+
+/* Bitfields in SFR0 */
+#define HMATRIX2_SFR_OFFSET 0
+#define HMATRIX2_SFR_SIZE 32
+
+/* Bitfields in SFR4 */
+#define HMATRIX2_CS1A_OFFSET 1
+#define HMATRIX2_CS1A_SIZE 1
+#define HMATRIX2_CS3A_OFFSET 3
+#define HMATRIX2_CS3A_SIZE 1
+#define HMATRIX2_CS4A_OFFSET 4
+#define HMATRIX2_CS4A_SIZE 1
+#define HMATRIX2_CS5A_OFFSET 5
+#define HMATRIX2_CS5A_SIZE 1
+#define HMATRIX2_DBPUC_OFFSET 8
+#define HMATRIX2_DBPUC_SIZE 1
+
+/* Bitfields in VERSION */
+#define HMATRIX2_VERSION_OFFSET 0
+#define HMATRIX2_VERSION_SIZE 12
+#define HMATRIX2_MFN_OFFSET 16
+#define HMATRIX2_MFN_SIZE 3
+
+/* Constants for ULBT */
+#define HMATRIX2_ULBT_INFINITE 0
+#define HMATRIX2_ULBT_SINGLE 1
+#define HMATRIX2_ULBT_FOUR_BEAT 2
+#define HMATRIX2_ULBT_SIXTEEN_BEAT 4
+
+/* Constants for DEFMSTR_TYPE */
+#define HMATRIX2_DEFMSTR_TYPE_NO_DEFAULT 0
+#define HMATRIX2_DEFMSTR_TYPE_LAST_DEFAULT 1
+#define HMATRIX2_DEFMSTR_TYPE_FIXED_DEFAULT 2
+
+/* Constants for ARBT */
+#define HMATRIX2_ARBT_ROUND_ROBIN 0
+#define HMATRIX2_ARBT_FIXED_PRIORITY 1
+
+/* Bit manipulation macros */
+#define HMATRIX2_BIT(name) \
+ (1 << HMATRIX2_##name##_OFFSET)
+#define HMATRIX2_BF(name,value) \
+ (((value) & ((1 << HMATRIX2_##name##_SIZE) - 1)) \
+ << HMATRIX2_##name##_OFFSET)
+#define HMATRIX2_BFEXT(name,value) \
+ (((value) >> HMATRIX2_##name##_OFFSET) \
+ & ((1 << HMATRIX2_##name##_SIZE) - 1))
+#define HMATRIX2_BFINS(name,value,old) \
+ (((old) & ~(((1 << HMATRIX2_##name##_SIZE) - 1) \
+ << HMATRIX2_##name##_OFFSET)) \
+ | HMATRIX2_BF(name,value))
+
+/* Register access macros */
+#define hmatrix2_readl(reg) \
+ readl((void *)HMATRIX_BASE + HMATRIX2_##reg)
+#define hmatrix2_writel(reg,value) \
+ writel((value), (void *)HMATRIX_BASE + HMATRIX2_##reg)
+
+#endif /* __ASM_AVR32_HMATRIX2_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __AT32AP7000_MEMORY_MAP_H__
+#define __AT32AP7000_MEMORY_MAP_H__
+
+/* Devices on the High Speed Bus (HSB) */
+#define LCDC_BASE 0xFF000000
+#define DMAC_BASE 0xFF200000
+#define USB_FIFO 0xFF300000
+
+/* Devices on Peripheral Bus A (PBA) */
+#define SPI0_BASE 0xFFE00000
+#define SPI1_BASE 0xFFE00400
+#define TWI_BASE 0xFFE00800
+#define USART0_BASE 0xFFE00C00
+#define USART1_BASE 0xFFE01000
+#define USART2_BASE 0xFFE01400
+#define USART3_BASE 0xFFE01800
+#define SSC0_BASE 0xFFE01C00
+#define SSC1_BASE 0xFFE02000
+#define SSC2_BASE 0xFFE02400
+#define PIOA_BASE 0xFFE02800
+#define PIOB_BASE 0xFFE02C00
+#define PIOC_BASE 0xFFE03000
+#define PIOD_BASE 0xFFE03400
+#define PIOE_BASE 0xFFE03800
+#define PSIF_BASE 0xFFE03C00
+
+/* Devices on Peripheral Bus B (PBB) */
+#define SM_BASE 0xFFF00000
+#define INTC_BASE 0xFFF00400
+#define HMATRIX_BASE 0xFFF00800
+#define TIMER0_BASE 0xFFF00C00
+#define TIMER1_BASE 0xFFF01000
+#define PWM_BASE 0xFFF01400
+#define MACB0_BASE 0xFFF01800
+#define MACB1_BASE 0xFFF01C00
+#define DAC_BASE 0xFFF02000
+#define MMCI_BASE 0xFFF02400
+#define AUDIOC_BASE 0xFFF02800
+#define HISI_BASE 0xFFF02C00
+#define USB_BASE 0xFFF03000
+#define HSMC_BASE 0xFFF03400
+#define HSDRAMC_BASE 0xFFF03800
+#define ECC_BASE 0xFFF03C00
+
+#endif /* __AT32AP7000_MEMORY_MAP_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_MMC_H
+#define __ASM_AVR32_MMC_H
+
+struct mmc_cid {
+ unsigned long psn;
+ unsigned short oid;
+ unsigned char mid;
+ unsigned char prv;
+ unsigned char mdt;
+ char pnm[7];
+};
+
+struct mmc_csd
+{
+ u8 csd_structure:2,
+ spec_vers:4,
+ rsvd1:2;
+ u8 taac;
+ u8 nsac;
+ u8 tran_speed;
+ u16 ccc:12,
+ read_bl_len:4;
+ u64 read_bl_partial:1,
+ write_blk_misalign:1,
+ read_blk_misalign:1,
+ dsr_imp:1,
+ rsvd2:2,
+ c_size:12,
+ vdd_r_curr_min:3,
+ vdd_r_curr_max:3,
+ vdd_w_curr_min:3,
+ vdd_w_curr_max:3,
+ c_size_mult:3,
+ sector_size:5,
+ erase_grp_size:5,
+ wp_grp_size:5,
+ wp_grp_enable:1,
+ default_ecc:2,
+ r2w_factor:3,
+ write_bl_len:4,
+ write_bl_partial:1,
+ rsvd3:5;
+ u8 file_format_grp:1,
+ copy:1,
+ perm_write_protect:1,
+ tmp_write_protect:1,
+ file_format:2,
+ ecc:2;
+ u8 crc:7;
+ u8 one:1;
+};
+
+/* MMC Command numbers */
+#define MMC_CMD_GO_IDLE_STATE 0
+#define MMC_CMD_SEND_OP_COND 1
+#define MMC_CMD_ALL_SEND_CID 2
+#define MMC_CMD_SET_RELATIVE_ADDR 3
+#define MMC_CMD_SD_SEND_RELATIVE_ADDR 3
+#define MMC_CMD_SET_DSR 4
+#define MMC_CMD_SELECT_CARD 7
+#define MMC_CMD_SEND_CSD 9
+#define MMC_CMD_SEND_CID 10
+#define MMC_CMD_SEND_STATUS 13
+#define MMC_CMD_SET_BLOCKLEN 16
+#define MMC_CMD_READ_SINGLE_BLOCK 17
+#define MMC_CMD_READ_MULTIPLE_BLOCK 18
+#define MMC_CMD_WRITE_BLOCK 24
+#define MMC_CMD_APP_CMD 55
+
+#define MMC_ACMD_SD_SEND_OP_COND 41
+
+#define R1_ILLEGAL_COMMAND (1 << 22)
+#define R1_APP_CMD (1 << 5)
+
+#endif /* __ASM_AVR32_MMC_H */
{
}
+/*
+ * Given a physical address and a length, return a virtual address
+ * that can be used to access the memory range with the caching
+ * properties specified by "flags".
+ *
+ * This implementation works for memory below 512MiB (flash, etc.) as
+ * well as above 3.5GiB (internal peripherals.)
+ */
+typedef unsigned long phys_addr_t;
+
+#define MAP_NOCACHE (0)
+#define MAP_WRCOMBINE (1 << 7)
+#define MAP_WRBACK (MAP_WRCOMBINE | (1 << 9))
+#define MAP_WRTHROUGH (MAP_WRBACK | (1 << 0))
+
+static inline void *
+map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
+{
+ if (flags == MAP_WRBACK)
+ return (void *)P1SEGADDR(paddr);
+ else
+ return (void *)P2SEGADDR(paddr);
+}
+
+/*
+ * Take down a mapping set up by map_physmem().
+ */
+static inline void unmap_physmem(void *vaddr, unsigned long len)
+{
+
+}
+
#endif /* __ASM_AVR32_IO_H */
__builtin_bfin_ssync();
}
+/*
+ * Given a physical address and a length, return a virtual address
+ * that can be used to access the memory range with the caching
+ * properties specified by "flags".
+ */
+typedef unsigned long phys_addr_t;
+
+#define MAP_NOCACHE (0)
+#define MAP_WRCOMBINE (0)
+#define MAP_WRBACK (0)
+#define MAP_WRTHROUGH (0)
+
+static inline void *
+map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
+{
+ return (void *)paddr;
+}
+
+/*
+ * Take down a mapping set up by map_physmem().
+ */
+static inline void unmap_physmem(void *vaddr, unsigned long flags)
+{
+
+}
+
/*
* These are for ISA/PCI shared memory _only_ and should never be used
* on any other type of memory, including Zorro memory. They are meant to
{
}
+/*
+ * Given a physical address and a length, return a virtual address
+ * that can be used to access the memory range with the caching
+ * properties specified by "flags".
+ */
+typedef unsigned long phys_addr_t;
+
+#define MAP_NOCACHE (0)
+#define MAP_WRCOMBINE (0)
+#define MAP_WRBACK (0)
+#define MAP_WRTHROUGH (0)
+
+static inline void *
+map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
+{
+ return (void *)paddr;
+}
+
+/*
+ * Take down a mapping set up by map_physmem().
+ */
+static inline void unmap_physmem(void *vaddr, unsigned long flags)
+{
+
+}
+
#endif
#include <asm/byteorder.h>
+/* ++roman: The assignments to temp. vars avoid that gcc sometimes generates
+ * two accesses to memory, which may be undesirable for some devices.
+ */
+#define __raw_readb(addr) \
+ ({ u8 __v = (*(volatile u8 *) (addr)); __v; })
+#define __raw_readw(addr) \
+ ({ u16 __v = (*(volatile u16 *) (addr)); __v; })
+#define __raw_readl(addr) \
+ ({ u32 __v = (*(volatile u32 *) (addr)); __v; })
+
+#define __raw_writeb(addr,b) (void)((*(volatile u8 *) (addr)) = (b))
+#define __raw_writew(addr,w) (void)((*(volatile u16 *) (addr)) = (w))
+#define __raw_writel(addr,l) (void)((*(volatile u32 *) (addr)) = (l))
+
#define readb(addr) in_8((volatile u8 *)(addr))
#define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
#if !defined(__BIG_ENDIAN)
* compatibility (CFI driver)
*/
}
+
+/*
+ * Given a physical address and a length, return a virtual address
+ * that can be used to access the memory range with the caching
+ * properties specified by "flags".
+ */
+typedef unsigned long phys_addr_t;
+
+#define MAP_NOCACHE (0)
+#define MAP_WRCOMBINE (0)
+#define MAP_WRBACK (0)
+#define MAP_WRTHROUGH (0)
+
+static inline void *
+map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
+{
+ return (void *)paddr;
+}
+
+/*
+ * Take down a mapping set up by map_physmem().
+ */
+static inline void unmap_physmem(void *vaddr, unsigned long flags)
+{
+
+}
+
#endif /* __ASM_M68K_IO_H__ */
{
}
+/*
+ * Given a physical address and a length, return a virtual address
+ * that can be used to access the memory range with the caching
+ * properties specified by "flags".
+ */
+typedef unsigned long phys_addr_t;
+
+#define MAP_NOCACHE (0)
+#define MAP_WRCOMBINE (0)
+#define MAP_WRBACK (0)
+#define MAP_WRTHROUGH (0)
+
+static inline void *
+map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
+{
+ return (void *)paddr;
+}
+
+/*
+ * Take down a mapping set up by map_physmem().
+ */
+static inline void unmap_physmem(void *vaddr, unsigned long flags)
+{
+
+}
+
#endif /* __MICROBLAZE_IO_H__ */
{
}
+/*
+ * Given a physical address and a length, return a virtual address
+ * that can be used to access the memory range with the caching
+ * properties specified by "flags".
+ */
+typedef unsigned long phys_addr_t;
+
+#define MAP_NOCACHE (0)
+#define MAP_WRCOMBINE (0)
+#define MAP_WRBACK (0)
+#define MAP_WRTHROUGH (0)
+
+static inline void *
+map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
+{
+ return (void *)paddr;
+}
+
+/*
+ * Take down a mapping set up by map_physmem().
+ */
+static inline void unmap_physmem(void *vaddr, unsigned long flags)
+{
+
+}
+
#endif /* _ASM_IO_H */
#ifndef __ASM_NIOS_IO_H_
#define __ASM_NIOS_IO_H_
+#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v))
+#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v))
+#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v))
+
+#define __raw_readb(a) (*(volatile unsigned char *)(a))
+#define __raw_readw(a) (*(volatile unsigned short *)(a))
+#define __raw_readl(a) (*(volatile unsigned int *)(a))
+
#define readb(addr)\
({unsigned char val;\
asm volatile( " pfxio 0 \n"\
{
}
+/*
+ * Given a physical address and a length, return a virtual address
+ * that can be used to access the memory range with the caching
+ * properties specified by "flags".
+ */
+typedef unsigned long phys_addr_t;
+
+#define MAP_NOCACHE (0)
+#define MAP_WRCOMBINE (0)
+#define MAP_WRBACK (0)
+#define MAP_WRTHROUGH (0)
+
+static inline void *
+map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
+{
+ return (void *)paddr;
+}
+
+/*
+ * Take down a mapping set up by map_physmem().
+ */
+static inline void unmap_physmem(void *vaddr, unsigned long flags)
+{
+
+}
+
#endif /* __ASM_NIOS_IO_H_ */
__asm__ __volatile__ ("sync" : : : "memory");
}
+/*
+ * Given a physical address and a length, return a virtual address
+ * that can be used to access the memory range with the caching
+ * properties specified by "flags".
+ */
+typedef unsigned long phys_addr_t;
+
+#define MAP_NOCACHE (0)
+#define MAP_WRCOMBINE (0)
+#define MAP_WRBACK (0)
+#define MAP_WRTHROUGH (0)
+
+static inline void *
+map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
+{
+ return (void *)paddr;
+}
+
+/*
+ * Take down a mapping set up by map_physmem().
+ */
+static inline void unmap_physmem(void *vaddr, unsigned long flags)
+{
+
+}
+
extern unsigned char inb (unsigned char *port);
extern unsigned short inw (unsigned short *port);
extern unsigned inl (unsigned port);
+#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v))
+#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v))
+#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v))
+
+#define __raw_readb(a) (*(volatile unsigned char *)(a))
+#define __raw_readw(a) (*(volatile unsigned short *)(a))
+#define __raw_readl(a) (*(volatile unsigned int *)(a))
+
#define readb(addr)\
({unsigned char val;\
asm volatile( "ldbio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;})
--- /dev/null
+#ifndef _405GP_PCI_H
+#define _405GP_PCI_H
+
+/*----------------------------------------------------------------------------+
+| 405GP PCI core memory map defines.
++----------------------------------------------------------------------------*/
+#define MIN_PCI_MEMADDR1 0x80000000
+#define MIN_PCI_MEMADDR2 0x00000000
+#define MIN_PLB_PCI_IOADDR 0xE8000000 /* PLB side of PCI I/O address space */
+#define MIN_PCI_PCI_IOADDR 0x00000000 /* PCI side of PCI I/O address space */
+#define MAX_PCI_DEVICES 32
+
+/*----------------------------------------------------------------------------+
+| Defines for the 405GP PCI Config address and data registers followed by
+| defines for the standard PCI device configuration header.
++----------------------------------------------------------------------------*/
+#define PCICFGADR 0xEEC00000
+#define PCICFGDATA 0xEEC00004
+
+#define PCIBUSNUM 0x40 /* 405GP specific parameters */
+#define PCISUBBUSNUM 0x41
+#define PCIDISCOUNT 0x42
+#define PCIBRDGOPT1 0x4A
+#define PCIBRDGOPT2 0x60
+
+/*----------------------------------------------------------------------------+
+| Defines for 405GP PCI Master local configuration regs.
++----------------------------------------------------------------------------*/
+#define PMM0LA 0xEF400000
+#define PMM0MA 0xEF400004
+#define PMM0PCILA 0xEF400008
+#define PMM0PCIHA 0xEF40000C
+#define PMM1LA 0xEF400010
+#define PMM1MA 0xEF400014
+#define PMM1PCILA 0xEF400018
+#define PMM1PCIHA 0xEF40001C
+#define PMM2LA 0xEF400020
+#define PMM2MA 0xEF400024
+#define PMM2PCILA 0xEF400028
+#define PMM2PCIHA 0xEF40002C
+
+/*----------------------------------------------------------------------------+
+| Defines for 405GP PCI Target local configuration regs.
++----------------------------------------------------------------------------*/
+#define PTM1MS 0xEF400030
+#define PTM1LA 0xEF400034
+#define PTM2MS 0xEF400038
+#define PTM2LA 0xEF40003C
+
+#define PCIDEVID_405GP 0x0
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2005 Cisco Systems. All rights reserved.
+ * Roland Dreier <rolandd@cisco.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <ppc4xx.h>
+#ifndef __4XX_PCIE_H
+#define __4XX_PCIE_H
+
+#define DCRN_SDR0_CFGADDR 0x00e
+#define DCRN_SDR0_CFGDATA 0x00f
+
+#if defined(CONFIG_440SPE)
+#define CFG_PCIE_NR_PORTS 3
+
+#define CFG_PCIE_ADDR_HIGH 0x0000000d
+
+#define DCRN_PCIE0_BASE 0x100
+#define DCRN_PCIE1_BASE 0x120
+#define DCRN_PCIE2_BASE 0x140
+
+#define PCIE0_SDR 0x300
+#define PCIE1_SDR 0x340
+#define PCIE2_SDR 0x370
+#endif
+
+#if defined(CONFIG_405EX)
+#define CFG_PCIE_NR_PORTS 2
+
+#define CFG_PCIE_ADDR_HIGH 0x00000000
+
+#define DCRN_PCIE0_BASE 0x040
+#define DCRN_PCIE1_BASE 0x060
+
+#define PCIE0_SDR 0x400
+#define PCIE1_SDR 0x440
+#endif
+
+#define PCIE0 DCRN_PCIE0_BASE
+#define PCIE1 DCRN_PCIE1_BASE
+#define PCIE2 DCRN_PCIE2_BASE
+
+#define DCRN_PEGPL_CFGBAH(base) (base + 0x00)
+#define DCRN_PEGPL_CFGBAL(base) (base + 0x01)
+#define DCRN_PEGPL_CFGMSK(base) (base + 0x02)
+#define DCRN_PEGPL_MSGBAH(base) (base + 0x03)
+#define DCRN_PEGPL_MSGBAL(base) (base + 0x04)
+#define DCRN_PEGPL_MSGMSK(base) (base + 0x05)
+#define DCRN_PEGPL_OMR1BAH(base) (base + 0x06)
+#define DCRN_PEGPL_OMR1BAL(base) (base + 0x07)
+#define DCRN_PEGPL_OMR1MSKH(base) (base + 0x08)
+#define DCRN_PEGPL_OMR1MSKL(base) (base + 0x09)
+#define DCRN_PEGPL_REGBAH(base) (base + 0x12)
+#define DCRN_PEGPL_REGBAL(base) (base + 0x13)
+#define DCRN_PEGPL_REGMSK(base) (base + 0x14)
+#define DCRN_PEGPL_SPECIAL(base) (base + 0x15)
+#define DCRN_PEGPL_CFG(base) (base + 0x16)
+
+/*
+ * System DCRs (SDRs)
+ */
+#define PESDR0_PLLLCT1 0x03a0
+#define PESDR0_PLLLCT2 0x03a1
+#define PESDR0_PLLLCT3 0x03a2
+
+/* common regs, at least for 405EX and 440SPe */
+#define SDRN_PESDR_UTLSET1(n) (sdr_base(n) + 0x00)
+#define SDRN_PESDR_UTLSET2(n) (sdr_base(n) + 0x01)
+#define SDRN_PESDR_DLPSET(n) (sdr_base(n) + 0x02)
+#define SDRN_PESDR_LOOP(n) (sdr_base(n) + 0x03)
+#define SDRN_PESDR_RCSSET(n) (sdr_base(n) + 0x04)
+#define SDRN_PESDR_RCSSTS(n) (sdr_base(n) + 0x05)
+
+#if defined(CONFIG_440SPE)
+#define SDRN_PESDR_HSSL0SET1(n) (sdr_base(n) + 0x06)
+#define SDRN_PESDR_HSSL0SET2(n) (sdr_base(n) + 0x07)
+#define SDRN_PESDR_HSSL0STS(n) (sdr_base(n) + 0x08)
+#define SDRN_PESDR_HSSL1SET1(n) (sdr_base(n) + 0x09)
+#define SDRN_PESDR_HSSL1SET2(n) (sdr_base(n) + 0x0a)
+#define SDRN_PESDR_HSSL1STS(n) (sdr_base(n) + 0x0b)
+#define SDRN_PESDR_HSSL2SET1(n) (sdr_base(n) + 0x0c)
+#define SDRN_PESDR_HSSL2SET2(n) (sdr_base(n) + 0x0d)
+#define SDRN_PESDR_HSSL2STS(n) (sdr_base(n) + 0x0e)
+#define SDRN_PESDR_HSSL3SET1(n) (sdr_base(n) + 0x0f)
+#define SDRN_PESDR_HSSL3SET2(n) (sdr_base(n) + 0x10)
+#define SDRN_PESDR_HSSL3STS(n) (sdr_base(n) + 0x11)
+
+#define PESDR0_UTLSET1 0x0300
+#define PESDR0_UTLSET2 0x0301
+#define PESDR0_DLPSET 0x0302
+#define PESDR0_LOOP 0x0303
+#define PESDR0_RCSSET 0x0304
+#define PESDR0_RCSSTS 0x0305
+#define PESDR0_HSSL0SET1 0x0306
+#define PESDR0_HSSL0SET2 0x0307
+#define PESDR0_HSSL0STS 0x0308
+#define PESDR0_HSSL1SET1 0x0309
+#define PESDR0_HSSL1SET2 0x030a
+#define PESDR0_HSSL1STS 0x030b
+#define PESDR0_HSSL2SET1 0x030c
+#define PESDR0_HSSL2SET2 0x030d
+#define PESDR0_HSSL2STS 0x030e
+#define PESDR0_HSSL3SET1 0x030f
+#define PESDR0_HSSL3SET2 0x0310
+#define PESDR0_HSSL3STS 0x0311
+#define PESDR0_HSSL4SET1 0x0312
+#define PESDR0_HSSL4SET2 0x0313
+#define PESDR0_HSSL4STS 0x0314
+#define PESDR0_HSSL5SET1 0x0315
+#define PESDR0_HSSL5SET2 0x0316
+#define PESDR0_HSSL5STS 0x0317
+#define PESDR0_HSSL6SET1 0x0318
+#define PESDR0_HSSL6SET2 0x0319
+#define PESDR0_HSSL6STS 0x031a
+#define PESDR0_HSSL7SET1 0x031b
+#define PESDR0_HSSL7SET2 0x031c
+#define PESDR0_HSSL7STS 0x031d
+#define PESDR0_HSSCTLSET 0x031e
+#define PESDR0_LANE_ABCD 0x031f
+#define PESDR0_LANE_EFGH 0x0320
+
+#define PESDR1_UTLSET1 0x0340
+#define PESDR1_UTLSET2 0x0341
+#define PESDR1_DLPSET 0x0342
+#define PESDR1_LOOP 0x0343
+#define PESDR1_RCSSET 0x0344
+#define PESDR1_RCSSTS 0x0345
+#define PESDR1_HSSL0SET1 0x0346
+#define PESDR1_HSSL0SET2 0x0347
+#define PESDR1_HSSL0STS 0x0348
+#define PESDR1_HSSL1SET1 0x0349
+#define PESDR1_HSSL1SET2 0x034a
+#define PESDR1_HSSL1STS 0x034b
+#define PESDR1_HSSL2SET1 0x034c
+#define PESDR1_HSSL2SET2 0x034d
+#define PESDR1_HSSL2STS 0x034e
+#define PESDR1_HSSL3SET1 0x034f
+#define PESDR1_HSSL3SET2 0x0350
+#define PESDR1_HSSL3STS 0x0351
+#define PESDR1_HSSCTLSET 0x0352
+#define PESDR1_LANE_ABCD 0x0353
+
+#define PESDR2_UTLSET1 0x0370
+#define PESDR2_UTLSET2 0x0371
+#define PESDR2_DLPSET 0x0372
+#define PESDR2_LOOP 0x0373
+#define PESDR2_RCSSET 0x0374
+#define PESDR2_RCSSTS 0x0375
+#define PESDR2_HSSL0SET1 0x0376
+#define PESDR2_HSSL0SET2 0x0377
+#define PESDR2_HSSL0STS 0x0378
+#define PESDR2_HSSL1SET1 0x0379
+#define PESDR2_HSSL1SET2 0x037a
+#define PESDR2_HSSL1STS 0x037b
+#define PESDR2_HSSL2SET1 0x037c
+#define PESDR2_HSSL2SET2 0x037d
+#define PESDR2_HSSL2STS 0x037e
+#define PESDR2_HSSL3SET1 0x037f
+#define PESDR2_HSSL3SET2 0x0380
+#define PESDR2_HSSL3STS 0x0381
+#define PESDR2_HSSCTLSET 0x0382
+#define PESDR2_LANE_ABCD 0x0383
+
+#elif defined(CONFIG_405EX)
+
+#define SDRN_PESDR_PHYSET1(n) (sdr_base(n) + 0x06)
+#define SDRN_PESDR_PHYSET2(n) (sdr_base(n) + 0x07)
+#define SDRN_PESDR_BIST(n) (sdr_base(n) + 0x08)
+#define SDRN_PESDR_LPB(n) (sdr_base(n) + 0x0b)
+#define SDRN_PESDR_PHYSTA(n) (sdr_base(n) + 0x0c)
+
+#define PESDR0_UTLSET1 0x0400
+#define PESDR0_UTLSET2 0x0401
+#define PESDR0_DLPSET 0x0402
+#define PESDR0_LOOP 0x0403
+#define PESDR0_RCSSET 0x0404
+#define PESDR0_RCSSTS 0x0405
+#define PESDR0_PHYSET1 0x0406
+#define PESDR0_PHYSET2 0x0407
+#define PESDR0_BIST 0x0408
+#define PESDR0_LPB 0x040B
+#define PESDR0_PHYSTA 0x040C
+
+#define PESDR1_UTLSET1 0x0440
+#define PESDR1_UTLSET2 0x0441
+#define PESDR1_DLPSET 0x0442
+#define PESDR1_LOOP 0x0443
+#define PESDR1_RCSSET 0x0444
+#define PESDR1_RCSSTS 0x0445
+#define PESDR1_PHYSET1 0x0446
+#define PESDR1_PHYSET2 0x0447
+#define PESDR1_BIST 0x0448
+#define PESDR1_LPB 0x044B
+#define PESDR1_PHYSTA 0x044C
+
+#endif
+
+/*
+ * UTL register offsets
+ */
+#define PEUTL_PBCTL 0x00
+#define PEUTL_PBBSZ 0x20
+#define PEUTL_OPDBSZ 0x68
+#define PEUTL_IPHBSZ 0x70
+#define PEUTL_IPDBSZ 0x78
+#define PEUTL_OUTTR 0x90
+#define PEUTL_INTR 0x98
+#define PEUTL_PCTL 0xa0
+#define PEUTL_RCSTA 0xb0
+#define PEUTL_RCIRQEN 0xb8
+
+/*
+ * Config space register offsets
+ */
+#define PECFG_BAR0LMPA 0x210
+#define PECFG_BAR0HMPA 0x214
+#define PECFG_BAR1MPA 0x218
+#define PECFG_BAR2LMPA 0x220
+#define PECFG_BAR2HMPA 0x224
+
+#define PECFG_PIMEN 0x33c
+#define PECFG_PIM0LAL 0x340
+#define PECFG_PIM0LAH 0x344
+#define PECFG_PIM1LAL 0x348
+#define PECFG_PIM1LAH 0x34c
+#define PECFG_PIM01SAL 0x350
+#define PECFG_PIM01SAH 0x354
+
+#define PECFG_POM0LAL 0x380
+#define PECFG_POM0LAH 0x384
+
+#define SDR_READ(offset) ({\
+ mtdcr(DCRN_SDR0_CFGADDR, offset); \
+ mfdcr(DCRN_SDR0_CFGDATA);})
+
+#define SDR_WRITE(offset, data) ({\
+ mtdcr(DCRN_SDR0_CFGADDR, offset); \
+ mtdcr(DCRN_SDR0_CFGDATA,data);})
+
+#define GPL_DMER_MASK_DISA 0x02000000
+
+#define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL))
+#define U64_TO_U32_HIGH(val) ((u32)((val) >> 32))
+
+/*
+ * Prototypes
+ */
+int ppc4xx_init_pcie(void);
+int ppc4xx_init_pcie_rootport(int port);
+int ppc4xx_init_pcie_endport(int port);
+void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port);
+int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port);
+int pcie_hose_scan(struct pci_controller *hose, int bus);
+
+/*
+ * Function to determine root port or endport from env variable.
+ */
+static inline int is_end_point(int port)
+{
+ char s[10], *tk;
+ char *pcie_mode = getenv("pcie_mode");
+
+ if (pcie_mode == NULL)
+ return 0;
+
+ strcpy(s, pcie_mode);
+ tk = strtok(s, ":");
+
+ switch (port) {
+ case 0:
+ if (tk != NULL) {
+ if (!(strcmp(tk, "ep") && strcmp(tk, "EP")))
+ return 1;
+ else
+ return 0;
+ }
+ else
+ return 0;
+
+ case 1:
+ tk = strtok(NULL, ":");
+ if (tk != NULL) {
+ if (!(strcmp(tk, "ep") && strcmp(tk, "EP")))
+ return 1;
+ else
+ return 0;
+ }
+ else
+ return 0;
+
+ case 2:
+ tk = strtok(NULL, ":");
+ if (tk != NULL)
+ tk = strtok(NULL, ":");
+ if (tk != NULL) {
+ if (!(strcmp(tk, "ep") && strcmp(tk, "EP")))
+ return 1;
+ else
+ return 0;
+ }
+ else
+ return 0;
+ }
+
+ return 0;
+}
+
+static inline void mdelay(int n)
+{
+ u32 ms = n;
+
+ while (ms--)
+ udelay(1000);
+}
+
+static inline u32 sdr_base(int port)
+{
+ switch (port) {
+ default: /* to satisfy compiler */
+ case 0:
+ return PCIE0_SDR;
+ case 1:
+ return PCIE1_SDR;
+#if CFG_PCIE_NR_PORTS > 2
+ case 2:
+ return PCIE2_SDR;
+#endif
+ }
+}
+
+#endif /* __4XX_PCIE_H */
#include <asm/processor.h>
/* bytes per L1 cache line */
-#if !defined(CONFIG_8xx) || defined(CONFIG_8260)
+#if !(defined(CONFIG_8xx) || defined(CONFIG_IOP480))
#if defined(CONFIG_PPC64BRIDGE)
-#define L1_CACHE_BYTES 128
+#define L1_CACHE_SHIFT 7
#else
-#define L1_CACHE_BYTES 32
+#define L1_CACHE_SHIFT 5
#endif /* PPC64 */
#else
-#define L1_CACHE_BYTES 16
-#endif /* !8xx || 8260 */
+#define L1_CACHE_SHIFT 4
+#endif /* !(8xx || IOP480) */
+
+#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
+
+/*
+ * For compatibility reasons support the CFG_CACHELINE_SIZE too
+ */
+#ifndef CFG_CACHELINE_SIZE
+#define CFG_CACHELINE_SIZE L1_CACHE_BYTES
+#endif
#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
#define L1_CACHE_PAGES 8
extern void flush_dcache_range(unsigned long start, unsigned long stop);
extern void clean_dcache_range(unsigned long start, unsigned long stop);
extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
+extern void flush_dcache(void);
+extern void invalidate_dcache(void);
#ifdef CFG_INIT_RAM_LOCK
extern void unlock_ram_in_cache(void);
#endif /* CFG_INIT_RAM_LOCK */
unsigned int dp_alloc_base;
unsigned int dp_alloc_top;
#endif
+#if defined(CONFIG_4xx)
+ u32 uart_clk;
+#endif /* CONFIG_4xx */
#if defined(CFG_GT_6426x)
unsigned int mirror_hack[16];
#endif
* MA 02111-1307 USA
*/
+#ifndef __ASM_PPC_GPIO_H
+#define __ASM_PPC_GPIO_H
+
/* 4xx PPC's have 2 GPIO controllers */
#if defined(CONFIG_405EZ) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
#define GPIO_GROUP_MAX 1
#endif
+/* Offsets */
+#define GPIOx_OR 0x00 /* GPIO Output Register */
+#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */
+#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */
+#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */
+#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */
+#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */
+#define GPIOx_ODR 0x18 /* GPIO Open drain Register */
+#define GPIOx_IR 0x1C /* GPIO Input Register */
+#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */
+#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */
+#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */
+#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */
+#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */
+#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */
+#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */
+#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */
+#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */
+
+#define GPIO_OR(x) (x+GPIOx_OR) /* GPIO Output Register */
+#define GPIO_TCR(x) (x+GPIOx_TCR) /* GPIO Three-State Control Register */
+#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Select Register High or Low */
+#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */
+#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */
+#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */
+#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */
+
+#define GPIO0 0
+#define GPIO1 1
+
#define GPIO_MAX 32
#define GPIO_ALT1_SEL 0x40000000
#define GPIO_ALT2_SEL 0x80000000
void gpio_write_bit(int pin, int val);
int gpio_read_out_bit(int pin);
void gpio_set_chip_configuration(void);
+
+#endif /* __ASM_PPC_GPIO_H */
} ccsr_tsec_t;
/*
- * PIC Registers(0x2_6000-0x4_0000-0x8_0000)
+ * PIC Registers(0x4_0000-0x8_0000)
*/
typedef struct ccsr_pic {
- char res0[106496]; /* 0x26000-0x40000 */
- char res1[64];
+ char res1[64]; /* 0x40000 */
uint ipidr0; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */
char res2[12];
uint ipidr1; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */
#define PORDEVSR_PCI (0x00800000) /* PCI Mode */
-typedef struct immap {
- ccsr_local_ecm_t im_local_ecm;
- ccsr_ddr_t im_ddr;
- ccsr_i2c_t im_i2c;
- ccsr_duart_t im_duart;
- ccsr_lbc_t im_lbc;
- ccsr_pcix_t im_pcix;
- ccsr_pcix_t im_pcix2;
- char reserved[90112];
- ccsr_l2cache_t im_l2cache;
- ccsr_dma_t im_dma;
- ccsr_tsec_t im_tsec1;
- ccsr_tsec_t im_tsec2;
- ccsr_pic_t im_pic;
- ccsr_cpm_t im_cpm;
- ccsr_rio_t im_rio;
- ccsr_gur_t im_gur;
-} immap_t;
-
-extern immap_t *immr;
+#define CFG_MPC85xx_GUTS_OFFSET (0xE0000)
+#define CFG_MPC85xx_GUTS_ADDR (CFG_IMMR + CFG_MPC85xx_GUTS_OFFSET)
+#define CFG_MPC85xx_ECM_OFFSET (0x0000)
+#define CFG_MPC85xx_ECM_ADDR (CFG_IMMR + CFG_MPC85xx_ECM_OFFSET)
+#define CFG_MPC85xx_DDR_OFFSET (0x2000)
+#define CFG_MPC85xx_DDR_ADDR (CFG_IMMR + CFG_MPC85xx_DDR_OFFSET)
+#define CFG_MPC85xx_LBC_OFFSET (0x5000)
+#define CFG_MPC85xx_LBC_ADDR (CFG_IMMR + CFG_MPC85xx_LBC_OFFSET)
+#define CFG_MPC85xx_PCIX_OFFSET (0x8000)
+#define CFG_MPC85xx_PCIX_ADDR (CFG_IMMR + CFG_MPC85xx_PCIX_OFFSET)
+#define CFG_MPC85xx_PCIX2_OFFSET (0x9000)
+#define CFG_MPC85xx_PCIX2_ADDR (CFG_IMMR + CFG_MPC85xx_PCIX2_OFFSET)
+#define CFG_MPC85xx_L2_OFFSET (0x20000)
+#define CFG_MPC85xx_L2_ADDR (CFG_IMMR + CFG_MPC85xx_L2_OFFSET)
+#define CFG_MPC85xx_DMA_OFFSET (0x21000)
+#define CFG_MPC85xx_DMA_ADDR (CFG_IMMR + CFG_MPC85xx_DMA_OFFSET)
+#define CFG_MPC85xx_PIC_OFFSET (0x40000)
+#define CFG_MPC85xx_PIC_ADDR (CFG_IMMR + CFG_MPC85xx_PIC_OFFSET)
+#define CFG_MPC85xx_CPM_OFFSET (0x80000)
+#define CFG_MPC85xx_CPM_ADDR (CFG_IMMR + CFG_MPC85xx_CPM_OFFSET)
#endif /*__IMMAP_85xx__*/
u32 perr_cap1; /* 0xe2c - PCIE Error Capture Register 1 */
u32 perr_cap2; /* 0xe30 - PCIE Error Capture Register 2 */
u32 perr_cap3; /* 0xe34 - PCIE Error Capture Register 3 */
- char res23[456]; /* (- #x1000 #xe38) 456 */
+ char res23[200];
+ u32 pdb_stat; /* 0xf00 - PCIE Debug Status */
+ char res24[252];
} ccsr_fsl_pci_t;
#endif /*__IMMAP_fsl_pci__*/
#define iobarrier_r() eieio()
#define iobarrier_w() eieio()
+/*
+ * Non ordered and non-swapping "raw" accessors
+ */
+#define __iomem
+#define PCI_FIX_ADDR(addr) (addr)
+
+static inline unsigned char __raw_readb(const volatile void __iomem *addr)
+{
+ return *(volatile unsigned char *)PCI_FIX_ADDR(addr);
+}
+static inline unsigned short __raw_readw(const volatile void __iomem *addr)
+{
+ return *(volatile unsigned short *)PCI_FIX_ADDR(addr);
+}
+static inline unsigned int __raw_readl(const volatile void __iomem *addr)
+{
+ return *(volatile unsigned int *)PCI_FIX_ADDR(addr);
+}
+static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
+{
+ *(volatile unsigned char *)PCI_FIX_ADDR(addr) = v;
+}
+static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
+{
+ *(volatile unsigned short *)PCI_FIX_ADDR(addr) = v;
+}
+static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
+{
+ *(volatile unsigned int *)PCI_FIX_ADDR(addr) = v;
+}
+
/*
* 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
*
* is actually performed (i.e. the data has come back) before we start
* executing any following instructions.
*/
-#define __iomem
extern inline int in_8(const volatile unsigned char __iomem *addr)
{
int ret;
__asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
}
+/*
+ * Given a physical address and a length, return a virtual address
+ * that can be used to access the memory range with the caching
+ * properties specified by "flags".
+ */
+typedef unsigned long phys_addr_t;
+
+#define MAP_NOCACHE (0)
+#define MAP_WRCOMBINE (0)
+#define MAP_WRBACK (0)
+#define MAP_WRTHROUGH (0)
+
+static inline void *
+map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
+{
+ return (void *)paddr;
+}
+
+/*
+ * Take down a mapping set up by map_physmem().
+ */
+static inline void unmap_physmem(void *vaddr, unsigned long flags)
+{
+
+}
+
#endif
extern __inline__ void iopin_set_high (iopin_t * iopin)
{
- volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata;
+ volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
datp[iopin->port * 8] |= (1 << (31 - iopin->pin));
}
extern __inline__ void iopin_set_low (iopin_t * iopin)
{
- volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata;
+ volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
}
extern __inline__ uint iopin_is_high (iopin_t * iopin)
{
- volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata;
+ volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
}
extern __inline__ uint iopin_is_low (iopin_t * iopin)
{
- volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata;
+ volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
}
extern __inline__ void iopin_set_out (iopin_t * iopin)
{
- volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira;
+ volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
dirp[iopin->port * 8] |= (1 << (31 - iopin->pin));
}
extern __inline__ void iopin_set_in (iopin_t * iopin)
{
- volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira;
+ volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
}
extern __inline__ uint iopin_is_out (iopin_t * iopin)
{
- volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira;
+ volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
}
extern __inline__ uint iopin_is_in (iopin_t * iopin)
{
- volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira;
+ volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
}
extern __inline__ void iopin_set_odr (iopin_t * iopin)
{
- volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra;
+ volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
odrp[iopin->port * 8] |= (1 << (31 - iopin->pin));
}
extern __inline__ void iopin_set_act (iopin_t * iopin)
{
- volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra;
+ volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
}
extern __inline__ uint iopin_is_odr (iopin_t * iopin)
{
- volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra;
+ volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
}
extern __inline__ uint iopin_is_act (iopin_t * iopin)
{
- volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra;
+ volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
}
extern __inline__ void iopin_set_ded (iopin_t * iopin)
{
- volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara;
+ volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
parp[iopin->port * 8] |= (1 << (31 - iopin->pin));
}
extern __inline__ void iopin_set_gen (iopin_t * iopin)
{
- volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara;
+ volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
}
extern __inline__ uint iopin_is_ded (iopin_t * iopin)
{
- volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara;
+ volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
}
extern __inline__ uint iopin_is_gen (iopin_t * iopin)
{
- volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara;
+ volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
}
extern __inline__ void iopin_set_opt2 (iopin_t * iopin)
{
- volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora;
+ volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
sorp[iopin->port * 8] |= (1 << (31 - iopin->pin));
}
extern __inline__ void iopin_set_opt1 (iopin_t * iopin)
{
- volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora;
+ volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
}
extern __inline__ uint iopin_is_opt2 (iopin_t * iopin)
{
- volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora;
+ volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
}
extern __inline__ uint iopin_is_opt1 (iopin_t * iopin)
{
- volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora;
+ volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
return ((sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
}
#define LAWAR_TRGT_IF_PCI1 0x00000000
#define LAWAR_TRGT_IF_PCIX 0x00000000
#define LAWAR_TRGT_IF_PCI2 0x00100000
-#define LAWAR_TRGT_IF_PEX 0x00200000
+#define LAWAR_TRGT_IF_PCIE1 0x00200000
+#define LAWAR_TRGT_IF_PCIE2 0x00100000
+#define LAWAR_TRGT_IF_PCIE3 0x00300000
#define LAWAR_TRGT_IF_LBC 0x00400000
#define LAWAR_TRGT_IF_CCSR 0x00800000
#define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000
void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
void remove_tlb(u32 vaddr, u32 size);
+void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value);
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_440 */
/* Special Purpose Registers (SPRNs)*/
+/* PPC440 Architecture is BOOK-E */
+#ifdef CONFIG_440
+#define CONFIG_BOOKE
+#endif
+
#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
#define SPRN_CTR 0x009 /* Count Register */
#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
#define PVR_405EP_RA 0x51210950
#define PVR_405GPR_RB 0x50910951
#define PVR_405EZ_RA 0x41511460
+#define PVR_405EXR1_RA 0x12911473 /* 405EXr rev A with Security */
+#define PVR_405EXR2_RA 0x12911471 /* 405EXr rev A without Security */
+#define PVR_405EX1_RA 0x12911477 /* 405EX rev A with Security */
+#define PVR_405EX2_RA 0x12911475 /* 405EX rev A without Security */
#define PVR_440GP_RB 0x40120440
#define PVR_440GP_RC 0x40120481
#define PVR_440EP_RA 0x42221850
defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || \
defined(CONFIG_405EZ) || \
+ defined(CONFIG_405EX) || \
defined(CONFIG_440)
unsigned char bi_s_version[4]; /* Version of this structure */
unsigned char bi_r_version[32]; /* Version of the ROM (AMCC) */
--- /dev/null
+#ifndef __ASM_SH_BITOPS_H
+#define __ASM_SH_BITOPS_H
+
+#ifdef __KERNEL__
+#include <asm/irqflags.h>
+/* For __swab32 */
+#include <asm/byteorder.h>
+
+static inline void set_bit(int nr, volatile void * addr)
+{
+ int mask;
+ volatile unsigned int *a = addr;
+ unsigned long flags;
+
+ a += nr >> 5;
+ mask = 1 << (nr & 0x1f);
+ local_irq_save(flags);
+ *a |= mask;
+ local_irq_restore(flags);
+}
+
+/*
+ * clear_bit() doesn't provide any barrier for the compiler.
+ */
+#define smp_mb__before_clear_bit() barrier()
+#define smp_mb__after_clear_bit() barrier()
+static inline void clear_bit(int nr, volatile void * addr)
+{
+ int mask;
+ volatile unsigned int *a = addr;
+ unsigned long flags;
+
+ a += nr >> 5;
+ mask = 1 << (nr & 0x1f);
+ local_irq_save(flags);
+ *a &= ~mask;
+ local_irq_restore(flags);
+}
+
+static inline void change_bit(int nr, volatile void * addr)
+{
+ int mask;
+ volatile unsigned int *a = addr;
+ unsigned long flags;
+
+ a += nr >> 5;
+ mask = 1 << (nr & 0x1f);
+ local_irq_save(flags);
+ *a ^= mask;
+ local_irq_restore(flags);
+}
+
+static inline int test_and_set_bit(int nr, volatile void * addr)
+{
+ int mask, retval;
+ volatile unsigned int *a = addr;
+ unsigned long flags;
+
+ a += nr >> 5;
+ mask = 1 << (nr & 0x1f);
+ local_irq_save(flags);
+ retval = (mask & *a) != 0;
+ *a |= mask;
+ local_irq_restore(flags);
+
+ return retval;
+}
+
+static inline int test_and_clear_bit(int nr, volatile void * addr)
+{
+ int mask, retval;
+ volatile unsigned int *a = addr;
+ unsigned long flags;
+
+ a += nr >> 5;
+ mask = 1 << (nr & 0x1f);
+ local_irq_save(flags);
+ retval = (mask & *a) != 0;
+ *a &= ~mask;
+ local_irq_restore(flags);
+
+ return retval;
+}
+
+static inline int test_and_change_bit(int nr, volatile void * addr)
+{
+ int mask, retval;
+ volatile unsigned int *a = addr;
+ unsigned long flags;
+
+ a += nr >> 5;
+ mask = 1 << (nr & 0x1f);
+ local_irq_save(flags);
+ retval = (mask & *a) != 0;
+ *a ^= mask;
+ local_irq_restore(flags);
+
+ return retval;
+}
+
+static inline unsigned long ffz(unsigned long word)
+{
+ unsigned long result;
+
+ __asm__("1:\n\t"
+ "shlr %1\n\t"
+ "bt/s 1b\n\t"
+ " add #1, %0"
+ : "=r" (result), "=r" (word)
+ : "0" (~0L), "1" (word)
+ : "t");
+ return result;
+}
+
+/**
+ * ffs - find first bit in word.
+ * @word: The word to search
+ *
+ * Undefined if no bit exists, so code should check against 0 first.
+ */
+static inline int ffs (int x)
+{
+ int r = 1;
+
+ if (!x)
+ return 0;
+ if (!(x & 0xffff)) {
+ x >>= 16;
+ r += 16;
+ }
+ if (!(x & 0xff)) {
+ x >>= 8;
+ r += 8;
+ }
+ if (!(x & 0xf)) {
+ x >>= 4;
+ r += 4;
+ }
+ if (!(x & 3)) {
+ x >>= 2;
+ r += 2;
+ }
+ if (!(x & 1)) {
+ x >>= 1;
+ r += 1;
+ }
+ return r;
+}
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_SH_BITOPS_H */
--- /dev/null
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_SH_BYTEORDER_H_
+#define __ASM_SH_BYTEORDER_H_
+
+#include <config.h>
+#include <asm/types.h>
+
+#ifdef __LITTLE_ENDIAN__
+#include <linux/byteorder/little_endian.h>
+#else
+#include <linux/byteorder/big_endian.h>
+#endif
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_CPU_SH4_H_
+#define _ASM_CPU_SH4_H_
+
+/* cache control */
+#define CCR_CACHE_STOP 0x00000808
+#define CCR_CACHE_ENABLE 0x00000101
+#define CCR_CACHE_ICI 0x00000800
+
+#define CACHE_OC_ADDRESS_ARRAY 0xf4000000
+#define CACHE_OC_WAY_SHIFT 14
+#define CACHE_OC_NUM_ENTRIES 512
+#define CACHE_OC_ENTRY_SHIFT 5
+
+#if defined (CONFIG_CPU_SH7750)
+#include <asm/cpu_sh7750.h>
+#elif defined (CONFIG_CPU_SH7722)
+#include <asm/cpu_sh7722.h>
+#else
+#error "Unknown SH4 variant"
+#endif
+
+#endif /* _ASM_CPU_SH4_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * SH7722 Internal I/O register
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_CPU_SH7722_H_
+#define _ASM_CPU_SH7722_H_
+
+#define CACHE_OC_NUM_WAYS 4
+#define CCR_CACHE_INIT 0x0000090d
+
+/* EXP */
+#define TRA 0xFF000020
+#define EXPEVT 0xFF000024
+#define INTEVT 0xFF000028
+
+/* MMU */
+#define PTEH 0xFF000000
+#define PTEL 0xFF000004
+#define TTB 0xFF000008
+#define TEA 0xFF00000C
+#define MMUCR 0xFF000010
+#define PASCR 0xFF000070
+#define IRMCR 0xFF000078
+
+/* CACHE */
+#define CCR 0xFF00001C
+#define RAMCR 0xFF000074
+
+/* XY MEMORY */
+#define XSA 0xFF000050
+#define YSA 0xFF000054
+#define XDA 0xFF000058
+#define YDA 0xFF00005C
+#define XPR 0xFF000060
+#define YPR 0xFF000064
+#define XEA 0xFF000068
+#define YEA 0xFF00006C
+
+/* INTC */
+#define ICR0 0xA4140000
+#define ICR1 0xA414001C
+#define INTPRI0 0xA4140010
+#define INTREQ0 0xA4140024
+#define INTMSK0 0xA4140044
+#define INTMSKCLR0 0xA4140064
+#define NMIFCR 0xA41400C0
+#define USERIMASK 0xA4700000
+#define IPRA 0xA4080000
+#define IPRB 0xA4080004
+#define IPRC 0xA4080008
+#define IPRD 0xA408000C
+#define IPRE 0xA4080010
+#define IPRF 0xA4080014
+#define IPRG 0xA4080018
+#define IPRH 0xA408001C
+#define IPRI 0xA4080020
+#define IPRJ 0xA4080024
+#define IPRK 0xA4080028
+#define IPRL 0xA408002C
+#define IMR0 0xA4080080
+#define IMR1 0xA4080084
+#define IMR2 0xA4080088
+#define IMR3 0xA408008C
+#define IMR4 0xA4080090
+#define IMR5 0xA4080094
+#define IMR6 0xA4080098
+#define IMR7 0xA408009C
+#define IMR8 0xA40800A0
+#define IMR9 0xA40800A4
+#define IMR10 0xA40800A8
+#define IMR11 0xA40800AC
+#define IMCR0 0xA40800C0
+#define IMCR1 0xA40800C4
+#define IMCR2 0xA40800C8
+#define IMCR3 0xA40800CC
+#define IMCR4 0xA40800D0
+#define IMCR5 0xA40800D4
+#define IMCR6 0xA40800D8
+#define IMCR7 0xA40800DC
+#define IMCR8 0xA40800E0
+#define IMCR9 0xA40800E4
+#define IMCR10 0xA40800E8
+#define IMCR11 0xA40800EC
+#define MFI_IPRA 0xA40B0000
+#define MFI_IPRB 0xA40B0004
+#define MFI_IPRC 0xA40B0008
+#define MFI_IPRD 0xA40B000C
+#define MFI_IPRE 0xA40B0010
+#define MFI_IPRF 0xA40B0014
+#define MFI_IPRG 0xA40B0018
+#define MFI_IPRH 0xA40B001C
+#define MFI_IPRI 0xA40B0020
+#define MFI_IPRJ 0xA40B0024
+#define MFI_IPRK 0xA40B0028
+#define MFI_IPRL 0xA40B002C
+#define MFI_IMR0 0xA40B0080
+#define MFI_IMR1 0xA40B0084
+#define MFI_IMR2 0xA40B0088
+#define MFI_IMR3 0xA40B008C
+#define MFI_IMR4 0xA40B0090
+#define MFI_IMR5 0xA40B0094
+#define MFI_IMR6 0xA40B0098
+#define MFI_IMR7 0xA40B009C
+#define MFI_IMR8 0xA40B00A0
+#define MFI_IMR9 0xA40B00A4
+#define MFI_IMR10 0xA40B00A8
+#define MFI_IMR11 0xA40B00AC
+#define MFI_IMCR0 0xA40B00C0
+#define MFI_IMCR1 0xA40B00C4
+#define MFI_IMCR2 0xA40B00C8
+#define MFI_IMCR3 0xA40B00CC
+#define MFI_IMCR4 0xA40B00D0
+#define MFI_IMCR5 0xA40B00D4
+#define MFI_IMCR6 0xA40B00D8
+#define MFI_IMCR7 0xA40B00DC
+#define MFI_IMCR8 0xA40B00E0
+#define MFI_IMCR9 0xA40B00E4
+#define MFI_IMCR10 0xA40B00E8
+#define MFI_IMCR11 0xA40B00EC
+
+/* BSC */
+#define CMNCR 0xFEC10000
+#define CS0BCR 0xFEC10004
+#define CS2BCR 0xFEC10008
+#define CS4BCR 0xFEC10010
+#define CS5ABCR 0xFEC10014
+#define CS5BBCR 0xFEC10018
+#define CS6ABCR 0xFEC1001C
+#define CS6BBCR 0xFEC10020
+#define CS0WCR 0xFEC10024
+#define CS2WCR 0xFEC10028
+#define CS4WCR 0xFEC10030
+#define CS5AWCR 0xFEC10034
+#define CS5BWCR 0xFEC10038
+#define CS6AWCR 0xFEC1003C
+#define CS6BWCR 0xFEC10040
+#define RBWTCNT 0xFEC10054
+
+/* SBSC */
+#define SBSC_SDCR 0xFE400008
+#define SBSC_SDWCR 0xFE40000C
+#define SBSC_SDPCR 0xFE400010
+#define SBSC_RTCSR 0xFE400014
+#define SBSC_RTCNT 0xFE400018
+#define SBSC_RTCOR 0xFE40001C
+#define SBSC_RFCR 0xFE400020
+
+/* DMAC */
+#define SAR_0 0xFE008020
+#define DAR_0 0xFE008024
+#define TCR_0 0xFE008028
+#define CHCR_0 0xFE00802C
+#define SAR_1 0xFE008030
+#define DAR_1 0xFE008034
+#define TCR_1 0xFE008038
+#define CHCR_1 0xFE00803C
+#define SAR_2 0xFE008040
+#define DAR_2 0xFE008044
+#define TCR_2 0xFE008048
+#define CHCR_2 0xFE00804C
+#define SAR_3 0xFE008050
+#define DAR_3 0xFE008054
+#define TCR_3 0xFE008058
+#define CHCR_3 0xFE00805C
+#define SAR_4 0xFE008070
+#define DAR_4 0xFE008074
+#define TCR_4 0xFE008078
+#define CHCR_4 0xFE00807C
+#define SAR_5 0xFE008080
+#define DAR_5 0xFE008084
+#define TCR_5 0xFE008088
+#define CHCR_5 0xFE00808C
+#define SARB_0 0xFE008120
+#define DARB_0 0xFE008124
+#define TCRB_0 0xFE008128
+#define SARB_1 0xFE008130
+#define DARB_1 0xFE008134
+#define TCRB_1 0xFE008138
+#define SARB_2 0xFE008140
+#define DARB_2 0xFE008144
+#define TCRB_2 0xFE008148
+#define SARB_3 0xFE008150
+#define DARB_3 0xFE008154
+#define TCRB_3 0xFE008158
+#define DMAOR 0xFE008060
+#define DMARS_0 0xFE009000
+#define DMARS_1 0xFE009004
+#define DMARS_2 0xFE009008
+
+/* CPG */
+#define FRQCR 0xA4150000
+#define VCLKCR 0xA4150004
+#define SCLKACR 0xA4150008
+#define SCLKBCR 0xA415000C
+#define PLLCR 0xA4150024
+#define DLLFRQ 0xA4150050
+
+/* LOW POWER MODE */
+#define STBCR 0xA4150020
+#define MSTPCR0 0xA4150030
+#define MSTPCR1 0xA4150034
+#define MSTPCR2 0xA4150038
+#define BAR 0xA4150040
+
+/* RWDT */
+#define RWTCNT 0xA4520000
+#define RWTCSR 0xA4520004
+#define WTCNT RWTCNT
+
+
+/* TMU */
+#define TSTR 0xFFD80004
+#define TCOR0 0xFFD80008
+#define TCNT0 0xFFD8000C
+#define TCR0 0xFFD80010
+#define TCOR1 0xFFD80014
+#define TCNT1 0xFFD80018
+#define TCR1 0xFFD8001C
+#define TCOR2 0xFFD80020
+#define TCNT2 0xFFD80024
+#define TCR2 0xFFD80028
+
+/* TPU */
+#define TPU_TSTR 0xA4C90000
+#define TPU_TCR0 0xA4C90010
+#define TPU_TMDR0 0xA4C90014
+#define TPU_TIOR0 0xA4C90018
+#define TPU_TIER0 0xA4C9001C
+#define TPU_TSR0 0xA4C90020
+#define TPU_TCNT0 0xA4C90024
+#define TPU_TGR0A 0xA4C90028
+#define TPU_TGR0B 0xA4C9002C
+#define TPU_TGR0C 0xA4C90030
+#define TPU_TGR0D 0xA4C90034
+#define TPU_TCR1 0xA4C90050
+#define TPU_TMDR1 0xA4C90054
+#define TPU_TIER1 0xA4C9005C
+#define TPU_TSR1 0xA4C90060
+#define TPU_TCNT1 0xA4C90064
+#define TPU_TGR1A 0xA4C90068
+#define TPU_TGR1B 0xA4C9006C
+#define TPU_TGR1C 0xA4C90070
+#define TPU_TGR1D 0xA4C90074
+#define TPU_TCR2 0xA4C90090
+#define TPU_TMDR2 0xA4C90094
+#define TPU_TIER2 0xA4C9009C
+#define TPU_TSR2 0xA4C900A0
+#define TPU_TCNT2 0xA4C900A4
+#define TPU_TGR2A 0xA4C900A8
+#define TPU_TGR2B 0xA4C900AC
+#define TPU_TGR2C 0xA4C900B0
+#define TPU_TGR2D 0xA4C900B4
+#define TPU_TCR3 0xA4C900D0
+#define TPU_TMDR3 0xA4C900D4
+#define TPU_TIER3 0xA4C900DC
+#define TPU_TSR3 0xA4C900E0
+#define TPU_TCNT3 0xA4C900E4
+#define TPU_TGR3A 0xA4C900E8
+#define TPU_TGR3B 0xA4C900EC
+#define TPU_TGR3C 0xA4C900F0
+#define TPU_TGR3D 0xA4C900F4
+
+/* CMT */
+#define CMSTR 0xA44A0000
+#define CMCSR 0xA44A0060
+#define CMCNT 0xA44A0064
+#define CMCOR 0xA44A0068
+
+/* SIO */
+#define SIOMDR 0xA4500000
+#define SIOCTR 0xA4500004
+#define SIOSTBCR0 0xA4500008
+#define SIOSTBCR1 0xA450000C
+#define SIOTDR 0xA4500014
+#define SIORDR 0xA4500018
+#define SIOSTR 0xA450001C
+#define SIOIER 0xA4500020
+#define SIOSCR 0xA4500024
+
+/* SIOF */
+#define SIMDR0 0xA4410000
+#define SISCR0 0xA4410002
+#define SITDAR0 0xA4410004
+#define SIRDAR0 0xA4410006
+#define SICDAR0 0xA4410008
+#define SICTR0 0xA441000C
+#define SIFCTR0 0xA4410010
+#define SISTR0 0xA4410014
+#define SIIER0 0xA4410016
+#define SITDR0 0xA4410020
+#define SIRDR0 0xA4410024
+#define SITCR0 0xA4410028
+#define SIRCR0 0xA441002C
+#define SPICR0 0xA4410030
+#define SIMDR1 0xA4420000
+#define SISCR1 0xA4420002
+#define SITDAR1 0xA4420004
+#define SIRDAR1 0xA4420006
+#define SICDAR1 0xA4420008
+#define SICTR1 0xA442000C
+#define SIFCTR1 0xA4420010
+#define SISTR1 0xA4420014
+#define SIIER1 0xA4420016
+#define SITDR1 0xA4420020
+#define SIRDR1 0xA4420024
+#define SITCR1 0xA4420028
+#define SIRCR1 0xA442002C
+#define SPICR1 0xA4420030
+
+/* SCIF */
+/*
+#define SCSMR 0xFFE00000
+#define SCBRR 0xFFE00004
+#define SCSCR 0xFFE00008
+#define SCFTDR 0xFFE0000C
+#define SCFSR 0xFFE00010
+#define SCFRDR 0xFFE00014
+#define SCFCR 0xFFE00018
+#define SCFDR 0xFFE0001C
+#define SCLSR 0xFFE00024
+#define SCSMR1 0xFFE10000
+#define SCBRR1 0xFFE10004
+#define SCSCR1 0xFFE10008
+#define SCFTDR1 0xFFE1000C
+#define SCFSR1 0xFFE10010
+#define SCFRDR1 0xFFE10014
+#define SCFCR1 0xFFE10018
+#define SCFDR1 0xFFE1001C
+#define SCLSR1 0xFFE10024
+#define SCSMR2 0xFFE20000
+#define SCBRR2 0xFFE20004
+#define SCSCR2 0xFFE20008
+#define SCFTDR2 0xFFE2000C
+#define SCFSR2 0xFFE20010
+#define SCFRDR2 0xFFE20014
+#define SCFCR2 0xFFE20018
+#define SCFDR2 0xFFE2001C
+#define SCLSR2 0xFFE20024
+#define SCSMR3 0xFFE30000
+#define SCBRR3 0xFFE30004
+#define SCSCR3 0xFFE30008
+#define SCFTDR3 0xFFE3000C
+#define SCFSR3 0xFFE30010
+#define SCFRDR3 0xFFE30014
+#define SCFCR3 0xFFE30018
+#define SCFDR3 0xFFE3001C
+#define SCLSR3 0xFFE30024
+*/
+#define SCIF0_BASE 0xFFE00000
+
+/* SIM */
+#define SIM_SCSMR 0xA4490000
+#define SIM_SCBRR 0xA4490002
+#define SIM_SCSCR 0xA4490004
+#define SIM_SCTDR 0xA4490006
+#define SIM_SCSSR 0xA4490008
+#define SIM_SCRDR 0xA449000A
+#define SIM_SCSCMR 0xA449000C
+#define SIM_SCSC2R 0xA449000E
+#define SIM_SCWAIT 0xA4490010
+#define SIM_SCGRD 0xA4490012
+#define SIM_SCSMPL 0xA4490014
+#define SIM_SCDMAEN 0xA4490016
+
+/* IrDA */
+#define IRIF_INIT1 0xA45D0012
+#define IRIF_INIT2 0xA45D0014
+#define IRIF_RINTCLR 0xA45D0016
+#define IRIF_TINTCLR 0xA45D0018
+#define IRIF_SIR0 0xA45D0020
+#define IRIF_SIR1 0xA45D0022
+#define IRIF_SIR2 0xA45D0024
+#define IRIF_SIR3 0xA45D0026
+#define IRIF_SIR_FRM 0xA45D0028
+#define IRIF_SIR_EOF 0xA45D002A
+#define IRIF_SIR_FLG 0xA45D002C
+#define IRIF_SIR_STS2 0xA45D002E
+#define IRIF_UART0 0xA45D0030
+#define IRIF_UART1 0xA45D0032
+#define IRIF_UART2 0xA45D0034
+#define IRIF_UART3 0xA45D0036
+#define IRIF_UART4 0xA45D0038
+#define IRIF_UART5 0xA45D003A
+#define IRIF_UART6 0xA45D003C
+#define IRIF_UART7 0xA45D003E
+#define IRIF_CRC0 0xA45D0040
+#define IRIF_CRC1 0xA45D0042
+#define IRIF_CRC2 0xA45D0044
+#define IRIF_CRC3 0xA45D0046
+#define IRIF_CRC4 0xA45D0048
+
+/* IIC */
+#define ICDR0 0xA4470000
+#define ICCR0 0xA4470004
+#define ICSR0 0xA4470008
+#define ICIC0 0xA447000C
+#define ICCL0 0xA4470010
+#define ICCH0 0xA4470014
+#define ICDR1 0xA4750000
+#define ICCR1 0xA4750004
+#define ICSR1 0xA4750008
+#define ICIC1 0xA475000C
+#define ICCL1 0xA4750010
+#define ICCH1 0xA4750014
+
+/* FLCTL */
+#define FLCMNCR 0xA4530000
+#define FLCMDCR 0xA4530004
+#define FLCMCDR 0xA4530008
+#define FLADR 0xA453000C
+#define FLDATAR 0xA4530010
+#define FLDTCNTR 0xA4530014
+#define FLINTDMACR 0xA4530018
+#define FLBSYTMR 0xA453001C
+#define FLBSYCNT 0xA4530020
+#define FLDTFIFO 0xA4530024
+#define FLECFIFO 0xA4530028
+#define FLTRCR 0xA453002C
+#define FLADR2 0xA453003C
+
+/* MFI */
+#define MFIIDX 0xA4C10000
+#define MFIGSR 0xA4C10004
+#define MFISCR 0xA4C10008
+#define MFIMCR 0xA4C1000C
+#define MFIIICR 0xA4C10010
+#define MFIEICR 0xA4C10014
+#define MFIADR 0xA4C10018
+#define MFIDATA 0xA4C1001C
+#define MFIRCR 0xA4C10020
+#define MFIINTEVT 0xA4C1002C
+#define MFIIMASK 0xA4C10030
+#define MFIBCR 0xA4C10040
+#define MFIADRW 0xA4C10044
+#define MFIADRR 0xA4C10048
+#define MFIDATAW 0xA4C1004C
+#define MFIDATAR 0xA4C10050
+#define MFIMCRW 0xA4C10054
+#define MFIMCRR 0xA4C10058
+#define MFIDNRW 0xA4C1005C
+#define MFIDNRR 0xA4C10060
+#define MFISIZEW 0xA4C10064
+#define MFISIZER 0xA4C10068
+#define MFIDEVCR 0xA4C10038
+#define MFISM4 0xA4C10080
+
+/* VPU */
+#define VP4_CTRL 0xFE900000
+#define VP4_VOL_CTRL 0xFE900004
+#define VP4_IMAGE_SIZE 0xFE900008
+#define VP4_MB_NUM 0xFE90000C
+#define VP4_DWY_ADDR 0xFE900010
+#define VP4_DWC_ADDR 0xFE900014
+#define VP4_D2WY_ADDR 0xFE900018
+#define VP4_D2WC_ADDR 0xFE90001C
+#define VP4_DP1_ADDR 0xFE900020
+#define VP4_DP2_ADDR 0xFE900024
+#define VP4_STRS_ADDR 0xFE900028
+#define VP4_STRE_ADDR 0xFE90002C
+#define VP4_VOP_CTRL 0xFE900030
+#define VP4_VOP_TIME 0xFE900034
+#define VP4_263_CTRL 0xFE900038
+#define VP4_264_CTRL 0xFE90003C
+#define VP4_VLC_CTRL 0xFE900040
+#define VP4_ENDIAN 0xFE900044
+#define VP4_CMD 0xFE900048
+#define VP4_ME_TH1 0xFE90004C
+#define VP4_ME_TH2 0xFE900050
+#define VP4_ME_COSTMB 0xFE900054
+#define VP4_ME_SKIP 0xFE900058
+#define VP4_ME_CTRL 0xFE90005C
+#define VP4_MBRF_CTRL 0xFE900060
+#define VP4_MC_CTRL 0xFE900064
+#define VP4_PRED_CTRL 0xFE900068
+#define VP4_SLC_SIZE 0xFE90006C
+#define VP4_VOP_MINBIT 0xFE900070
+#define VP4_MB_MAXBIT 0xFE900074
+#define VP4_MB_TBIT 0xFE900078
+#define VP4_RCQNT 0xFE90007C
+#define VP4_RCRP 0xFE900080
+#define VP4_RCDJ 0xFE900084
+#define VP4_RCWQ 0xFE900088
+#define VP4_FWD_TIME 0xFE900094
+#define VP4_BWD_TIME 0xFE900098
+#define VP4_PST_TIME 0xFE90009C
+#define VP4_ILTFRAME 0xFE9000A0
+#define VP4_EC_REF 0xFE9000A4
+#define VP4_STATUS 0xFE900100
+#define VP4_IRQ_ENB 0xFE900104
+#define VP4_IRQ_STA 0xFE900108
+#define VP4_VOP_BIT 0xFE90010C
+#define VP4_PRV_BIT 0xFE900110
+#define VP4_SLC_MB 0xFE900114
+#define VP4_QSUM 0xFE900118
+#define VP4_DEC_ERR 0xFE90011C
+#define VP4_ERR_AREA 0xFE900120
+#define VP4_NEXT_CODE 0xFE900124
+#define VP4_MB_ATTR 0xFE900128
+#define VP4_DBMON 0xFE90012C
+#define VP4_DEBUG 0xFE900130
+#define VP4_ERR_DET 0xFE900134
+#define VP4_CLK_STOP 0xFE900138
+#define VP4_MB_SADA 0xFE90013C
+#define VP4_MB_SADR 0xFE900140
+#define VP4_MAT_RAM 0xFE901000
+#define VP4_NC_RAM 0xFE902000
+#define WT 0xFE9020CC
+#define VP4_CPY_ADDR 0xFE902264
+#define VP4_CPC_ADDR 0xFE902268
+#define VP4_R0Y_ADDR 0xFE90226C
+#define VP4_R0C_ADDR 0xFE902270
+#define VP4_R1Y_ADDR 0xFE902274
+#define VP4_R1C_ADDR 0xFE902278
+#define VP4_R2Y_ADDR 0xFE90227C
+#define VP4_R2C_ADDR 0xFE902280
+#define VP4_R3Y_ADDR 0xFE902284
+#define VP4_R3C_ADDR 0xFE902288
+#define VP4_R4Y_ADDR 0xFE90228C
+#define VP4_R4C_ADDR 0xFE902290
+#define VP4_R5Y_ADDR 0xFE902294
+#define VP4_R5C_ADDR 0xFE902298
+#define VP4_R6Y_ADDR 0xFE90229C
+#define VP4_R6C_ADDR 0xFE9022A0
+#define VP4_R7Y_ADDR 0xFE9022A4
+#define VP4_R7C_ADDR 0xFE9022A8
+#define VP4_R8Y_ADDR 0xFE9022AC
+#define VP4_R8C_ADDR 0xFE9022B0
+#define VP4_R9Y_ADDR 0xFE9022B4
+#define VP4_R9C_ADDR 0xFE9022B8
+#define VP4_RAY_ADDR 0xFE9022BC
+#define VP4_RAC_ADDR 0xFE9022C0
+#define VP4_RBY_ADDR 0xFE9022C4
+#define VP4_RBC_ADDR 0xFE9022C8
+#define VP4_RCY_ADDR 0xFE9022CC
+#define VP4_RCC_ADDR 0xFE9022D0
+#define VP4_RDY_ADDR 0xFE9022D4
+#define VP4_RDC_ADDR 0xFE9022D8
+#define VP4_REY_ADDR 0xFE9022DC
+#define VP4_REC_ADDR 0xFE9022E0
+#define VP4_RFY_ADDR 0xFE9022E4
+#define VP4_RFC_ADDR 0xFE9022E8
+
+/* VIO(CEU) */
+#define CAPSR 0xFE910000
+#define CAPCR 0xFE910004
+#define CAMCR 0xFE910008
+#define CMCYR 0xFE91000C
+#define CAMOR 0xFE910010
+#define CAPWR 0xFE910014
+#define CAIFR 0xFE910018
+#define CSTCR 0xFE910020
+#define CSECR 0xFE910024
+#define CRCNTR 0xFE910028
+#define CRCMPR 0xFE91002C
+#define CFLCR 0xFE910030
+#define CFSZR 0xFE910034
+#define CDWDR 0xFE910038
+#define CDAYR 0xFE91003C
+#define CDACR 0xFE910040
+#define CDBYR 0xFE910044
+#define CDBCR 0xFE910048
+#define CBDSR 0xFE91004C
+#define CLFCR 0xFE910060
+#define CDOCR 0xFE910064
+#define CDDCR 0xFE910068
+#define CDDAR 0xFE91006C
+#define CEIER 0xFE910070
+#define CETCR 0xFE910074
+#define CSTSR 0xFE91007C
+#define CSRTR 0xFE910080
+#define CDAYR2 0xFE910090
+#define CDACR2 0xFE910094
+#define CDBYR2 0xFE910098
+#define CDBCR2 0xFE91009C
+
+/* VIO(VEU) */
+#define VESTR 0xFE920000
+#define VESWR 0xFE920010
+#define VESSR 0xFE920014
+#define VSAYR 0xFE920018
+#define VSACR 0xFE92001C
+#define VBSSR 0xFE920020
+#define VEDWR 0xFE920030
+#define VDAYR 0xFE920034
+#define VDACR 0xFE920038
+#define VTRCR 0xFE920050
+#define VRFCR 0xFE920054
+#define VRFSR 0xFE920058
+#define VENHR 0xFE92005C
+#define VFMCR 0xFE920070
+#define VVTCR 0xFE920074
+#define VHTCR 0xFE920078
+#define VAPCR 0xFE920080
+#define VECCR 0xFE920084
+#define VAFXR 0xFE920090
+#define VSWPR 0xFE920094
+#define VEIER 0xFE9200A0
+#define VEVTR 0xFE9200A4
+#define VSTAR 0xFE9200B0
+#define VBSRR 0xFE9200B4
+
+/* VIO(BEU) */
+#define BESTR 0xFE930000
+#define BSMWR1 0xFE930010
+#define BSSZR1 0xFE930014
+#define BSAYR1 0xFE930018
+#define BSACR1 0xFE93001C
+#define BSAAR1 0xFE930020
+#define BSIFR1 0xFE930024
+#define BSMWR2 0xFE930028
+#define BSSZR2 0xFE93002C
+#define BSAYR2 0xFE930030
+#define BSACR2 0xFE930034
+#define BSAAR2 0xFE930038
+#define BSIFR2 0xFE93003C
+#define BSMWR3 0xFE930040
+#define BSSZR3 0xFE930044
+#define BSAYR3 0xFE930048
+#define BSACR3 0xFE93004C
+#define BSAAR3 0xFE930050
+#define BSIFR3 0xFE930054
+#define BTPSR 0xFE930058
+#define BMSMWR1 0xFE930070
+#define BMSSZR1 0xFE930074
+#define BMSAYR1 0xFE930078
+#define BMSACR1 0xFE93007C
+#define BMSMWR2 0xFE930080
+#define BMSSZR2 0xFE930084
+#define BMSAYR2 0xFE930088
+#define BMSACR2 0xFE93008C
+#define BMSMWR3 0xFE930090
+#define BMSSZR3 0xFE930094
+#define BMSAYR3 0xFE930098
+#define BMSACR3 0xFE93009C
+#define BMSMWR4 0xFE9300A0
+#define BMSSZR4 0xFE9300A4
+#define BMSAYR4 0xFE9300A8
+#define BMSACR4 0xFE9300AC
+#define BMSIFR 0xFE9300F0
+#define BBLCR0 0xFE930100
+#define BBLCR1 0xFE930104
+#define BPROCR 0xFE930108
+#define BMWCR0 0xFE93010C
+#define BLOCR1 0xFE930114
+#define BLOCR2 0xFE930118
+#define BLOCR3 0xFE93011C
+#define BMLOCR1 0xFE930120
+#define BMLOCR2 0xFE930124
+#define BMLOCR3 0xFE930128
+#define BMLOCR4 0xFE93012C
+#define BMPCCR1 0xFE930130
+#define BMPCCR2 0xFE930134
+#define BPKFR 0xFE930140
+#define BPCCR0 0xFE930144
+#define BPCCR11 0xFE930148
+#define BPCCR12 0xFE93014C
+#define BPCCR21 0xFE930150
+#define BPCCR22 0xFE930154
+#define BPCCR31 0xFE930158
+#define BPCCR32 0xFE93015C
+#define BDMWR 0xFE930160
+#define BDAYR 0xFE930164
+#define BDACR 0xFE930168
+#define BAFXR 0xFE930180
+#define BSWPR 0xFE930184
+#define BEIER 0xFE930188
+#define BEVTR 0xFE93018C
+#define BRCNTR 0xFE930194
+#define BSTAR 0xFE930198
+#define BBRSTR 0xFE93019C
+#define BRCHR 0xFE9301A0
+#define CLUT 0xFE933000
+
+/* JPU */
+#define JCMOD 0xFEA00000
+#define JCCMD 0xFEA00004
+#define JCSTS 0xFEA00008
+#define JCQTN 0xFEA0000C
+#define JCHTN 0xFEA00010
+#define JCDRIU 0xFEA00014
+#define JCDRID 0xFEA00018
+#define JCVSZU 0xFEA0001C
+#define JCVSZD 0xFEA00020
+#define JCHSZU 0xFEA00024
+#define JCHSZD 0xFEA00028
+#define JCDTCU 0xFEA0002C
+#define JCDTCM 0xFEA00030
+#define JCDTCD 0xFEA00034
+#define JINTE 0xFEA00038
+#define JINTS 0xFEA0003C
+#define JCDERR 0xFEA00040
+#define JCRST 0xFEA00044
+#define JIFCNT 0xFEA00060
+#define JIFECNT 0xFEA00070
+#define JIFESYA1 0xFEA00074
+#define JIFESCA1 0xFEA00078
+#define JIFESYA2 0xFEA0007C
+#define JIFESCA2 0xFEA00080
+#define JIFESMW 0xFEA00084
+#define JIFESVSZ 0xFEA00088
+#define JIFESHSZ 0xFEA0008C
+#define JIFEDA1 0xFEA00090
+#define JIFEDA2 0xFEA00094
+#define JIFEDRSZ 0xFEA00098
+#define JIFDCNT 0xFEA000A0
+#define JIFDSA1 0xFEA000A4
+#define JIFDSA2 0xFEA000A8
+#define JIFDDRSZ 0xFEA000AC
+#define JIFDDMW 0xFEA000B0
+#define JIFDDVSZ 0xFEA000B4
+#define JIFDDHSZ 0xFEA000B8
+#define JIFDDYA1 0xFEA000BC
+#define JIFDDCA1 0xFEA000C0
+#define JIFDDYA2 0xFEA000C4
+#define JIFDDCA2 0xFEA000C8
+#define JCQTBL0 0xFEA10000
+#define JCQTBL1 0xFEA10040
+#define JCQTBL2 0xFEA10080
+#define JCQTBL3 0xFEA100C0
+#define JCHTBD0 0xFEA10100
+#define JCHTBA0 0xFEA10120
+#define JCHTBD1 0xFEA10200
+#define JCHTBA1 0xFEA10220
+
+/* LCDC */
+#define MLDDCKPAT1R 0xFE940400
+#define MLDDCKPAT2R 0xFE940404
+#define SLDDCKPAT1R 0xFE940408
+#define SLDDCKPAT2R 0xFE94040C
+#define LDDCKR 0xFE940410
+#define LDDCKSTPR 0xFE940414
+#define MLDMT1R 0xFE940418
+#define MLDMT2R 0xFE94041C
+#define MLDMT3R 0xFE940420
+#define MLDDFR 0xFE940424
+#define MLDSM1R 0xFE940428
+#define MLDSM2R 0xFE94042C
+#define MLDSA1R 0xFE940430
+#define MLDSA2R 0xFE940434
+#define MLDMLSR 0xFE940438
+#define MLDWBFR 0xFE94043C
+#define MLDWBCNTR 0xFE940440
+#define MLDWBAR 0xFE940444
+#define MLDHCNR 0xFE940448
+#define MLDHSYNR 0xFE94044C
+#define MLDVLNR 0xFE940450
+#define MLDVSYNR 0xFE940454
+#define MLDHPDR 0xFE940458
+#define MLDVPDR 0xFE94045C
+#define MLDPMR 0xFE940460
+#define LDPALCR 0xFE940464
+#define LDINTR 0xFE940468
+#define LDSR 0xFE94046C
+#define LDCNT1R 0xFE940470
+#define LDCNT2R 0xFE940474
+#define LDRCNTR 0xFE940478
+#define LDDDSR 0xFE94047C
+#define LDRCR 0xFE940484
+#define LDCMRKRGBR 0xFE9404C4
+#define LDCMRKCMYR 0xFE9404C8
+#define LDCMRK1R 0xFE9404CC
+#define LDCMRK2R 0xFE9404D0
+#define LDCMGKRGBR 0xFE9404D4
+#define LDCMGKCMYR 0xFE9404D8
+#define LDCMGK1R 0xFE9404DC
+#define LDCMGK2R 0xFE9404E0
+#define LDCMBKRGBR 0xFE9404E4
+#define LDCMBKCMYR 0xFE9404E8
+#define LDCMBK1R 0xFE9404EC
+#define LDCMBK2R 0xFE9404F0
+#define LDCMHKPR 0xFE9404F4
+#define LDCMHKQR 0xFE9404F8
+#define LDCMSELR 0xFE9404FC
+#define LDCMTVR 0xFE940500
+#define LDCMTVSELR 0xFE940504
+#define LDCMDTHR 0xFE940508
+#define LDCMCNTR 0xFE94050C
+#define SLDMT1R 0xFE940600
+#define SLDMT2R 0xFE940604
+#define SLDMT3R 0xFE940608
+#define SLDDFR 0xFE94060C
+#define SLDSM1R 0xFE940610
+#define SLDSM2R 0xFE940614
+#define SLDSA1R 0xFE940618
+#define SLDSA2R 0xFE94061C
+#define SLDMLSR 0xFE940620
+#define SLDHCNR 0xFE940624
+#define SLDHSYNR 0xFE940628
+#define SLDVLNR 0xFE94062C
+#define SLDVSYNR 0xFE940630
+#define SLDHPDR 0xFE940634
+#define SLDVPDR 0xFE940638
+#define SLDPMR 0xFE94063C
+#define LDDWD0R 0xFE940800
+#define LDDWD1R 0xFE940804
+#define LDDWD2R 0xFE940808
+#define LDDWD3R 0xFE94080C
+#define LDDWD4R 0xFE940810
+#define LDDWD5R 0xFE940814
+#define LDDWD6R 0xFE940818
+#define LDDWD7R 0xFE94081C
+#define LDDWD8R 0xFE940820
+#define LDDWD9R 0xFE940824
+#define LDDWDAR 0xFE940828
+#define LDDWDBR 0xFE94082C
+#define LDDWDCR 0xFE940830
+#define LDDWDDR 0xFE940834
+#define LDDWDER 0xFE940838
+#define LDDWDFR 0xFE94083C
+#define LDDRDR 0xFE940840
+#define LDDWAR 0xFE940900
+#define LDDRAR 0xFE940904
+#define LDPR00 0xFE940000
+
+/* VOU */
+#define VOUER 0xFE960000
+#define VOUCR 0xFE960004
+#define VOUSTR 0xFE960008
+#define VOUVCR 0xFE96000C
+#define VOUISR 0xFE960010
+#define VOUBCR 0xFE960014
+#define VOUDPR 0xFE960018
+#define VOUDSR 0xFE96001C
+#define VOUVPR 0xFE960020
+#define VOUIR 0xFE960024
+#define VOUSRR 0xFE960028
+#define VOUMSR 0xFE96002C
+#define VOUHIR 0xFE960030
+#define VOUDFR 0xFE960034
+#define VOUAD1R 0xFE960038
+#define VOUAD2R 0xFE96003C
+#define VOUAIR 0xFE960040
+#define VOUSWR 0xFE960044
+#define VOURCR 0xFE960048
+#define VOURPR 0xFE960050
+
+/* TSIF */
+#define TSCTLR 0xA4C80000
+#define TSPIDR 0xA4C80004
+#define TSCMDR 0xA4C80008
+#define TSSTR 0xA4C8000C
+#define TSTSDR 0xA4C80010
+#define TSBUFCLRR 0xA4C80014
+#define TSINTER 0xA4C80018
+#define TSPSCALER 0xA4C80020
+#define TSPSCALERR 0xA4C80024
+#define TSPCRADCMDR 0xA4C80028
+#define TSPCRADCR 0xA4C8002C
+#define TSTRPCRADCR 0xA4C80030
+#define TSDPCRADCR 0xA4C80034
+
+/* SIU */
+#define IFCTL 0xA454C000
+#define SRCTL 0xA454C004
+#define SFORM 0xA454C008
+#define CKCTL 0xA454C00C
+#define TRDAT 0xA454C010
+#define STFIFO 0xA454C014
+#define DPAK 0xA454C01C
+#define CKREV 0xA454C020
+#define EVNTC 0xA454C028
+#define SBCTL 0xA454C040
+#define SBPSET 0xA454C044
+#define SBBUS 0xA454C048
+#define SBWFLG 0xA454C058
+#define SBRFLG 0xA454C05C
+#define SBWDAT 0xA454C060
+#define SBRDAT 0xA454C064
+#define SBFSTS 0xA454C068
+#define SBDVCA 0xA454C06C
+#define SBDVCB 0xA454C070
+#define SBACTIV 0xA454C074
+#define DMAIA 0xA454C090
+#define DMAIB 0xA454C094
+#define DMAOA 0xA454C098
+#define DMAOB 0xA454C09C
+#define SPLRI 0xA454C0B8
+#define SPRRI 0xA454C0BC
+#define SPURI 0xA454C0C4
+#define SPTIS 0xA454C0C8
+#define SPSTS 0xA454C0CC
+#define SPCTL 0xA454C0D0
+#define SPIRI 0xA454C0D4
+#define SPQCF 0xA454C0D8
+#define SPQCS 0xA454C0DC
+#define SPQCT 0xA454C0E0
+#define DPEAK 0xA454C0F0
+#define DSLPD 0xA454C0F4
+#define DSLLV 0xA454C0F8
+#define BRGASEL 0xA454C100
+#define BRRA 0xA454C104
+#define BRGBSEL 0xA454C108
+#define BRRB 0xA454C10C
+
+/* USB */
+#define IFR0 0xA4480000
+#define ISR0 0xA4480010
+#define IER0 0xA4480020
+#define EPDR0I 0xA4480030
+#define EPDR0O 0xA4480034
+#define EPDR0S 0xA4480038
+#define EPDR1 0xA448003C
+#define EPDR2 0xA4480040
+#define EPDR3 0xA4480044
+#define EPDR4 0xA4480048
+#define EPDR5 0xA448004C
+#define EPDR6 0xA4480050
+#define EPDR7 0xA4480054
+#define EPDR8 0xA4480058
+#define EPDR9 0xA448005C
+#define EPSZ0O 0xA4480080
+#define EPSZ3 0xA4480084
+#define EPSZ6 0xA4480088
+#define EPSZ9 0xA448008C
+#define TRG 0xA44800A0
+#define DASTS 0xA44800A4
+#define FCLR 0xA44800AA
+#define DMA 0xA44800AC
+#define EPSTL 0xA44800B2
+#define CVR 0xA44800B4
+#define TSR 0xA44800B8
+#define CTLR 0xA44800BC
+#define EPIR 0xA44800C0
+#define XVERCR 0xA44800D0
+#define STLMR 0xA44800D4
+
+/* KEYSC */
+#define KYCR1 0xA44B0000
+#define KYCR2 0xA44B0004
+#define KYINDR 0xA44B0008
+#define KYOUTDR 0xA44B000C
+
+/* MMCIF */
+#define CMDR0 0xA4448000
+#define CMDR1 0xA4448001
+#define CMDR2 0xA4448002
+#define CMDR3 0xA4448003
+#define CMDR4 0xA4448004
+#define CMDR5 0xA4448005
+#define CMDSTRT 0xA4448006
+#define OPCR 0xA444800A
+#define CSTR 0xA444800B
+#define INTCR0 0xA444800C
+#define INTCR1 0xA444800D
+#define INTSTR0 0xA444800E
+#define INTSTR1 0xA444800F
+#define CLKON 0xA4448010
+#define CTOCR 0xA4448011
+#define VDCNT 0xA4448012
+#define TBCR 0xA4448014
+#define MODER 0xA4448016
+#define CMDTYR 0xA4448018
+#define RSPTYR 0xA4448019
+#define TBNCR 0xA444801A
+#define RSPR0 0xA4448020
+#define RSPR1 0xA4448021
+#define RSPR2 0xA4448022
+#define RSPR3 0xA4448023
+#define RSPR4 0xA4448024
+#define RSPR5 0xA4448025
+#define RSPR6 0xA4448026
+#define RSPR7 0xA4448027
+#define RSPR8 0xA4448028
+#define RSPR9 0xA4448029
+#define RSPR10 0xA444802A
+#define RSPR11 0xA444802B
+#define RSPR12 0xA444802C
+#define RSPR13 0xA444802D
+#define RSPR14 0xA444802E
+#define RSPR15 0xA444802F
+#define RSPR16 0xA4448030
+#define RSPRD 0xA4448031
+#define DTOUTR 0xA4448032
+#define DR 0xA4448040
+#define FIFOCLR 0xA4448042
+#define DMACR 0xA4448044
+#define INTCR2 0xA4448046
+#define INTSTR2 0xA4448048
+
+/* Z3D3 */
+#define DLBI 0xFD980000
+#define DLBD0 0xFD980080
+#define DLBD1 0xFD980100
+#define GEWM 0xFD984000
+#define ICD0 0xFD988000
+#define ICD1 0xFD989000
+#define ICT 0xFD98A000
+#define ILM 0xFD98C000
+#define FLM0 0xFD98C800
+#define FLM1 0xFD98D000
+#define FLUT 0xFD98D800
+#define Z3D_PC 0xFD98E400
+#define Z3D_PCSP 0xFD98E404
+#define Z3D_PAR 0xFD98E408
+#define Z3D_IMADR 0xFD98E40C
+#define Z3D_BTR0 0xFD98E410
+#define Z3D_BTR1 0xFD98E414
+#define Z3D_BTR2 0xFD98E418
+#define Z3D_BTR3 0xFD98E41C
+#define Z3D_LC0 0xFD98E420
+#define Z3D_LC1 0xFD98E424
+#define Z3D_LC2 0xFD98E428
+#define Z3D_LC3 0xFD98E42C
+#define Z3D_FR0 0xFD98E430
+#define Z3D_FR1 0xFD98E434
+#define Z3D_FR2 0xFD98E438
+#define Z3D_SR 0xFD98E440
+#define Z3D_SMDR 0xFD98E444
+#define Z3D_PBIR 0xFD98E448
+#define Z3D_DMDR 0xFD98E44C
+#define Z3D_IREG 0xFD98E460
+#define Z3D_AR00 0xFD98E480
+#define Z3D_AR01 0xFD98E484
+#define Z3D_AR02 0xFD98E488
+#define Z3D_AR03 0xFD98E48C
+#define Z3D_BR00 0xFD98E490
+#define Z3D_BR01 0xFD98E494
+#define Z3D_IXR00 0xFD98E4A0
+#define Z3D_IXR01 0xFD98E4A4
+#define Z3D_IXR02 0xFD98E4A8
+#define Z3D_IXR03 0xFD98E4AC
+#define Z3D_AR10 0xFD98E4C0
+#define Z3D_AR11 0xFD98E4C4
+#define Z3D_AR12 0xFD98E4C8
+#define Z3D_AR13 0xFD98E4CC
+#define Z3D_BR10 0xFD98E4D0
+#define Z3D_BR11 0xFD98E4D4
+#define Z3D_IXR10 0xFD98E4E0
+#define Z3D_IXR11 0xFD98E4E4
+#define Z3D_IXR12 0xFD98E4E8
+#define Z3D_IXR13 0xFD98E4EC
+#define Z3D_AR20 0xFD98E500
+#define Z3D_AR21 0xFD98E504
+#define Z3D_AR22 0xFD98E508
+#define Z3D_AR23 0xFD98E50C
+#define Z3D_BR20 0xFD98E510
+#define Z3D_BR21 0xFD98E514
+#define Z3D_IXR20 0xFD98E520
+#define Z3D_IXR21 0xFD98E524
+#define Z3D_IXR22 0xFD98E528
+#define Z3D_IXR23 0xFD98E52C
+#define Z3D_MR0 0xFD98E540
+#define Z3D_MR1 0xFD98E544
+#define Z3D_MR2 0xFD98E548
+#define Z3D_MR3 0xFD98E54C
+#define Z3D_WORKRST 0xFD98E558
+#define Z3D_WORKWST 0xFD98E55C
+#define Z3D_DBADR 0xFD98E560
+#define Z3D_DLBPRST 0xFD98E564
+#define Z3D_DLBRST 0xFD98E568
+#define Z3D_DLBWST 0xFD98E56C
+#define Z3D_UDR0 0xFD98E570
+#define Z3D_UDR1 0xFD98E574
+#define Z3D_UDR2 0xFD98E578
+#define Z3D_UDR3 0xFD98E57C
+#define Z3D_CCR0 0xFD98E580
+#define Z3D_CCR1 0xFD98E584
+#define Z3D_EXPR 0xFD98E588
+#define Z3D_V0_X 0xFD9A0000
+#define Z3D_V0_Y 0xFD9A0004
+#define Z3D_V0_Z 0xFD9A0008
+#define Z3D_V0_W 0xFD9A000C
+#define Z3D_V0_A 0xFD9A0010
+#define Z3D_V0_R 0xFD9A0014
+#define Z3D_V0_G 0xFD9A0018
+#define Z3D_V0_B 0xFD9A001C
+#define Z3D_V0_F 0xFD9A0020
+#define Z3D_V0_SR 0xFD9A0024
+#define Z3D_V0_SG 0xFD9A0028
+#define Z3D_V0_SB 0xFD9A002C
+#define Z3D_V0_U0 0xFD9A0030
+#define Z3D_V0_V0 0xFD9A0034
+#define Z3D_V0_U1 0xFD9A0038
+#define Z3D_V0_V1 0xFD9A003C
+#define Z3D_V1_X 0xFD9A0080
+#define Z3D_V1_Y 0xFD9A0084
+#define Z3D_V1_Z 0xFD9A0088
+#define Z3D_V1_W 0xFD9A008C
+#define Z3D_V1_A 0xFD9A0090
+#define Z3D_V1_R 0xFD9A0094
+#define Z3D_V1_G 0xFD9A0098
+#define Z3D_V1_B 0xFD9A009C
+#define Z3D_V1_F 0xFD9A00A0
+#define Z3D_V1_SR 0xFD9A00A4
+#define Z3D_V1_SG 0xFD9A00A8
+#define Z3D_V1_SB 0xFD9A00AC
+#define Z3D_V1_U0 0xFD9A00B0
+#define Z3D_V1_V0 0xFD9A00B4
+#define Z3D_V1_U1 0xFD9A00B8
+#define Z3D_V1_V1 0xFD9A00BC
+#define Z3D_V2_X 0xFD9A0100
+#define Z3D_V2_Y 0xFD9A0104
+#define Z3D_V2_Z 0xFD9A0108
+#define Z3D_V2_W 0xFD9A010C
+#define Z3D_V2_A 0xFD9A0110
+#define Z3D_V2_R 0xFD9A0114
+#define Z3D_V2_G 0xFD9A0118
+#define Z3D_V2_B 0xFD9A011C
+#define Z3D_V2_F 0xFD9A0120
+#define Z3D_V2_SR 0xFD9A0124
+#define Z3D_V2_SG 0xFD9A0128
+#define Z3D_V2_SB 0xFD9A012C
+#define Z3D_V2_U0 0xFD9A0130
+#define Z3D_V2_V0 0xFD9A0134
+#define Z3D_V2_U1 0xFD9A0138
+#define Z3D_V2_V1 0xFD9A013C
+#define Z3D_RENDER 0xFD9A0180
+#define Z3D_POLYGON_OFFSET 0xFD9A0184
+#define Z3D_VERTEX_CONTROL 0xFD9A0200
+#define Z3D_STATE_MODE 0xFD9A0204
+#define Z3D_FPU_MODE 0xFD9A0318
+#define Z3D_SCISSOR_MIN 0xFD9A0400
+#define Z3D_SCISSOR_MAX 0xFD9A0404
+#define Z3D_TEXTURE_MODE_A 0xFD9A0408
+#define Z3D_TEXTURE_MODE_B 0xFD9A040C
+#define Z3D_TEXTURE_BASE_HI_A 0xFD9A0418
+#define Z3D_TEXTURE_BASE_LO_A 0xFD9A041C
+#define Z3D_TEXTURE_BASE_HI_B 0xFD9A0420
+#define Z3D_TEXTURE_BASE_LO_B 0xFD9A0424
+#define Z3D_TEXTURE_ALPHA_A0 0xFD9A0438
+#define Z3D_TEXTURE_ALPHA_A1 0xFD9A043C
+#define Z3D_TEXTURE_ALPHA_A2 0xFD9A0440
+#define Z3D_TEXTURE_ALPHA_A3 0xFD9A0444
+#define Z3D_TEXTURE_ALPHA_A4 0xFD9A0448
+#define Z3D_TEXTURE_ALPHA_A5 0xFD9A044C
+#define Z3D_TEXTURE_ALPHA_B0 0xFD9A0450
+#define Z3D_TEXTURE_ALPHA_B1 0xFD9A0454
+#define Z3D_TEXTURE_ALPHA_B2 0xFD9A0458
+#define Z3D_TEXTURE_ALPHA_B3 0xFD9A045C
+#define Z3D_TEXTURE_ALPHA_B4 0xFD9A0460
+#define Z3D_TEXTURE_ALPHA_B5 0xFD9A0464
+#define Z3D_TEXTURE_FLUSH 0xFD9A0498
+#define Z3D_GAMMA_TABLE0 0xFD9A049C
+#define Z3D_GAMMA_TABLE1 0xFD9A04A0
+#define Z3D_GAMMA_TABLE2 0xFD9A04A4
+#define Z3D_ALPHA_TEST 0xFD9A0800
+#define Z3D_STENCIL_TEST 0xFD9A0804
+#define Z3D_DEPTH_ROP_BLEND_DITHER 0xFD9A0808
+#define Z3D_MASK 0xFD9A080C
+#define Z3D_FBUS_MODE 0xFD9A0810
+#define Z3D_GNT_SET 0xFD9A0814
+#define Z3D_BETWEEN_TEST 0xFD9A0818
+#define Z3D_FB_BASE 0xFD9A081C
+#define Z3D_LCD_SIZE 0xFD9A0820
+#define Z3D_FB_FLUSH 0xFD9A0824
+#define Z3D_CACHE_INVALID 0xFD9A0828
+#define Z3D_SC_MODE 0xFD9A0830
+#define Z3D_SC0_MIN 0xFD9A0834
+#define Z3D_SC0_MAX 0xFD9A0838
+#define Z3D_SC1_MIN 0xFD9A083C
+#define Z3D_SC1_MAX 0xFD9A0840
+#define Z3D_SC2_MIN 0xFD9A0844
+#define Z3D_SC2_MAX 0xFD9A0848
+#define Z3D_SC3_MIN 0xFD9A084C
+#define Z3D_SC3_MAX 0xFD9A0850
+#define Z3D_READRESET 0xFD9A0854
+#define Z3D_DET_MIN 0xFD9A0858
+#define Z3D_DET_MAX 0xFD9A085C
+#define Z3D_FB_BASE_SR 0xFD9A0860
+#define Z3D_LCD_SIZE_SR 0xFD9A0864
+#define Z3D_2D_CTRL_STATUS 0xFD9A0C00
+#define Z3D_2D_SIZE 0xFD9A0C04
+#define Z3D_2D_SRCLOC 0xFD9A0C08
+#define Z3D_2D_DSTLOC 0xFD9A0C0C
+#define Z3D_2D_DMAPORT 0xFD9A0C10
+#define Z3D_2D_CONSTANT_SOURCE0 0xFD9A0C14
+#define Z3D_2D_CONSTANT_SOURCE1 0xFD9A0C18
+#define Z3D_2D_STPCOLOR0 0xFD9A0C1C
+#define Z3D_2D_STPCOLOR1 0xFD9A0C20
+#define Z3D_2D_STPPARAMETER_SET0 0xFD9A0C24
+#define Z3D_2D_STPPARAMETER_SET1 0xFD9A0C28
+#define Z3D_2D_STPPAT_0 0xFD9A0C40
+#define Z3D_2D_STPPAT_1 0xFD9A0C44
+#define Z3D_2D_STPPAT_2 0xFD9A0C48
+#define Z3D_2D_STPPAT_3 0xFD9A0C4C
+#define Z3D_2D_STPPAT_4 0xFD9A0C50
+#define Z3D_2D_STPPAT_5 0xFD9A0C54
+#define Z3D_2D_STPPAT_6 0xFD9A0C58
+#define Z3D_2D_STPPAT_7 0xFD9A0C5C
+#define Z3D_2D_STPPAT_8 0xFD9A0C60
+#define Z3D_2D_STPPAT_9 0xFD9A0C64
+#define Z3D_2D_STPPAT_10 0xFD9A0C68
+#define Z3D_2D_STPPAT_11 0xFD9A0C6C
+#define Z3D_2D_STPPAT_12 0xFD9A0C70
+#define Z3D_2D_STPPAT_13 0xFD9A0C74
+#define Z3D_2D_STPPAT_14 0xFD9A0C78
+#define Z3D_2D_STPPAT_15 0xFD9A0C7C
+#define Z3D_2D_STPPAT_16 0xFD9A0C80
+#define Z3D_2D_STPPAT_17 0xFD9A0C84
+#define Z3D_2D_STPPAT_18 0xFD9A0C88
+#define Z3D_2D_STPPAT_19 0xFD9A0C8C
+#define Z3D_2D_STPPAT_20 0xFD9A0C90
+#define Z3D_2D_STPPAT_21 0xFD9A0C94
+#define Z3D_2D_STPPAT_22 0xFD9A0C98
+#define Z3D_2D_STPPAT_23 0xFD9A0C9C
+#define Z3D_2D_STPPAT_24 0xFD9A0CA0
+#define Z3D_2D_STPPAT_25 0xFD9A0CA4
+#define Z3D_2D_STPPAT_26 0xFD9A0CA8
+#define Z3D_2D_STPPAT_27 0xFD9A0CAC
+#define Z3D_2D_STPPAT_28 0xFD9A0CB0
+#define Z3D_2D_STPPAT_29 0xFD9A0CB4
+#define Z3D_2D_STPPAT_30 0xFD9A0CB8
+#define Z3D_2D_STPPAT_31 0xFD9A0CBC
+#define Z3D_WR_CTRL 0xFD9A1000
+#define Z3D_WR_P0 0xFD9A1004
+#define Z3D_WR_P1 0xFD9A1008
+#define Z3D_WR_P2 0xFD9A100C
+#define Z3D_WR_FGC 0xFD9A1010
+#define Z3D_WR_BGC 0xFD9A1014
+#define Z3D_WR_SZ 0xFD9A1018
+#define Z3D_WR_PATPARAM 0xFD9A101C
+#define Z3D_WR_PAT 0xFD9A1020
+#define Z3D_SYS_STATUS 0xFD9A1400
+#define Z3D_SYS_RESET 0xFD9A1404
+#define Z3D_SYS_CLK 0xFD9A1408
+#define Z3D_SYS_CONF 0xFD9A140C
+#define Z3D_SYS_VERSION 0xFD9A1410
+#define Z3D_SYS_DBINV 0xFD9A1418
+#define Z3D_SYS_I2F_FMT 0xFD9A1420
+#define Z3D_SYS_I2F_SRC 0xFD9A1424
+#define Z3D_SYS_I2F_DST 0xFD9A1428
+#define Z3D_SYS_GBCNT 0xFD9A1430
+#define Z3D_SYS_BSYCNT 0xFD9A1434
+#define Z3D_SYS_INT_STATUS 0xFD9A1450
+#define Z3D_SYS_INT_MASK 0xFD9A1454
+#define Z3D_SYS_INT_CLEAR 0xFD9A1458
+#define TCD0 0xFD9C0000
+#define TCD1 0xFD9C0400
+#define TCD2 0xFD9C0800
+#define TCD3 0xFD9C0C00
+#define TCT0 0xFD9C1000
+#define TCT1 0xFD9C1400
+#define TCT2 0xFD9C1800
+#define TCT3 0xFD9C1C00
+
+/* PFC */
+#define PACR 0xA4050100
+#define PBCR 0xA4050102
+#define PCCR 0xA4050104
+#define PDCR 0xA4050106
+#define PECR 0xA4050108
+#define PFCR 0xA405010A
+#define PGCR 0xA405010C
+#define PHCR 0xA405010E
+#define PJCR 0xA4050110
+#define PKCR 0xA4050112
+#define PLCR 0xA4050114
+#define PMCR 0xA4050116
+#define PNCR 0xA4050118
+#define PQCR 0xA405011A
+#define PRCR 0xA405011C
+#define PSCR 0xA405011E
+#define PTCR 0xA4050140
+#define PUCR 0xA4050142
+#define PVCR 0xA4050144
+#define PWCR 0xA4050146
+#define PXCR 0xA4050148
+#define PYCR 0xA405014A
+#define PZCR 0xA405014C
+#define PSELA 0xA405014E
+#define PSELB 0xA4050150
+#define PSELC 0xA4050152
+#define PSELD 0xA4050154
+#define PSELE 0xA4050156
+#define HIZCRA 0xA4050158
+#define HIZCRB 0xA405015A
+#define HIZCRC 0xA405015C
+#define MSELCR 0xA405015C
+#define PULCR 0xA405015E
+#define DRVCR 0xA4050180
+#define SBSCR 0xA4050182
+#define AUDTHCR 0xA4050184
+#define PSELF 0xA4050186
+
+/* I/O Port */
+#define PADR 0xA4050120
+#define PBDR 0xA4050122
+#define PCDR 0xA4050124
+#define PDDR 0xA4050126
+#define PEDR 0xA4050128
+#define PFDR 0xA405012A
+#define PGDR 0xA405012C
+#define PHDR 0xA405012E
+#define PJDR 0xA4050130
+#define PKDR 0xA4050132
+#define PLDR 0xA4050134
+#define PMDR 0xA4050136
+#define PNDR 0xA4050138
+#define PQDR 0xA405013A
+#define PRDR 0xA405013C
+#define PSDR 0xA405013E
+#define PTDR 0xA4050160
+#define PUDR 0xA4050162
+#define PVDR 0xA4050164
+#define PWDR 0xA4050166
+#define PYDR 0xA4050168
+#define PZDR 0xA405016A
+
+/* UBC */
+#define CBR0 0xFF200000
+#define CRR0 0xFF200004
+#define CAR0 0xFF200008
+#define CAMR0 0xFF20000C
+#define CBR1 0xFF200020
+#define CRR1 0xFF200024
+#define CAR1 0xFF200028
+#define CAMR1 0xFF20002C
+#define CDR1 0xFF200030
+#define CDMR1 0xFF200034
+#define CETR1 0xFF200038
+#define CCMFR 0xFF200600
+#define CBCR 0xFF200620
+
+/* H-UDI */
+#define SDIR 0xFC110000
+#define SDDRH 0xFC110008
+#define SDDRL 0xFC11000A
+#define SDINT 0xFC110018
+
+#endif /* _ASM_CPU_SH7722_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * SH7750/SH7750S/SH7750R/SH7751/SH7751R
+ * Internal I/O register
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_CPU_SH7750_H_
+#define _ASM_CPU_SH7750_H_
+
+#ifdef CONFIG_CPU_TYPE_R
+#define CACHE_OC_NUM_WAYS 2
+#define CCR_CACHE_INIT 0x8000090d /* EMODE,ICI,ICE(16k),OCI,P1-wb,OCE(32k) */
+#else
+#define CACHE_OC_NUM_WAYS 1
+#define CCR_CACHE_INIT 0x0000090b
+#endif
+
+/* OCN */
+#define PTEH 0xFF000000
+#define PTEL 0xFF000004
+#define TTB 0xFF000008
+#define TEA 0xFF00000C
+#define MMUCR 0xFF000010
+#define BASRA 0xFF000014
+#define BASRB 0xFF000018
+#define CCR 0xFF00001C
+#define TRA 0xFF000020
+#define EXPEVT 0xFF000024
+#define INTEVT 0xFF000028
+#define PTEA 0xFF000034
+#define QACR0 0xFF000038
+#define QACR1 0xFF00003C
+
+/* UBC */
+#define BARA 0xFF200000
+#define BAMRA 0xFF200004
+#define BBRA 0xFF200008
+#define BARB 0xFF20000C
+#define BAMRB 0xFF200010
+#define BBRB 0xFF200014
+#define BDRB 0xFF200018
+#define BDMRB 0xFF20001C
+#define BRCR 0xFF200020
+
+/* BSC */
+#define BCR1 0xFF800000
+#define BCR2 0xFF800004
+#define BCR3 0xFF800050
+#define BCR4 0xFE0A00F0
+#define WCR1 0xFF800008
+#define WCR2 0xFF80000C
+#define WCR3 0xFF800010
+#define MCR 0xFF800014
+#define PCR 0xFF800018
+#define RTCSR 0xFF80001C
+#define RTCNT 0xFF800020
+#define RTCOR 0xFF800024
+#define RFCR 0xFF800028
+#define PCTRA 0xFF80002C
+#define PDTRA 0xFF800030
+#define PCTRB 0xFF800040
+#define PDTRB 0xFF800044
+#define GPIOIC 0xFF800048
+
+/* DMAC */
+#define SAR0 0xFFA00000
+#define DAR0 0xFFA00004
+#define DMATCR0 0xFFA00008
+#define CHCR0 0xFFA0000C
+#define SAR1 0xFFA00010
+#define DAR1 0xFFA00014
+#define DMATCR1 0xFFA00018
+#define CHCR1 0xFFA0001C
+#define SAR2 0xFFA00020
+#define DAR2 0xFFA00024
+#define DMATCR2 0xFFA00028
+#define CHCR2 0xFFA0002C
+#define SAR3 0xFFA00030
+#define DAR3 0xFFA00034
+#define DMATCR3 0xFFA00038
+#define CHCR3 0xFFA0003C
+#define DMAOR 0xFFA00040
+#define SAR4 0xFFA00050
+#define DAR4 0xFFA00054
+#define DMATCR4 0xFFA00058
+
+/* CPG */
+#define FRQCR 0xFFC00000
+#define STBCR 0xFFC00004
+#define WTCNT 0xFFC00008
+#define WTCSR 0xFFC0000C
+#define STBCR2 0xFFC00010
+
+/* RTC */
+#define R64CNT 0xFFC80000
+#define RSECCNT 0xFFC80004
+#define RMINCNT 0xFFC80008
+#define RHRCNT 0xFFC8000C
+#define RWKCNT 0xFFC80010
+#define RDAYCNT 0xFFC80014
+#define RMONCNT 0xFFC80018
+#define RYRCNT 0xFFC8001C
+#define RSECAR 0xFFC80020
+#define RMINAR 0xFFC80024
+#define RHRAR 0xFFC80028
+#define RWKAR 0xFFC8002C
+#define RDAYAR 0xFFC80030
+#define RMONAR 0xFFC80034
+#define RCR1 0xFFC80038
+#define RCR2 0xFFC8003C
+#define RCR3 0xFFC80050
+#define RYRAR 0xFFC80054
+
+/* ICR */
+#define ICR 0xFFD00000
+#define IPRA 0xFFD00004
+#define IPRB 0xFFD00008
+#define IPRC 0xFFD0000C
+#define IPRD 0xFFD00010
+#define INTPRI 0xFE080000
+#define INTREQ 0xFE080020
+#define INTMSK 0xFE080040
+#define INTMSKCL 0xFE080060
+
+/* CPG */
+#define CLKSTP 0xFE0A0000
+#define CLKSTPCLR 0xFE0A0008
+
+/* TMU */
+#define TSTR2 0xFE100004
+#define TCOR3 0xFE100008
+#define TCNT3 0xFE10000C
+#define TCR3 0xFE100010
+#define TCOR4 0xFE100014
+#define TCNT4 0xFE100018
+#define TCR4 0xFE10001C
+#define TOCR 0xFFD80000
+#define TSTR0 0xFFD80004
+#define TCOR0 0xFFD80008
+#define TCNT0 0xFFD8000C
+#define TCR0 0xFFD80010
+#define TCOR1 0xFFD80014
+#define TCNT1 0xFFD80018
+#define TCR1 0xFFD8001C
+#define TCOR2 0xFFD80020
+#define TCNT2 0xFFD80024
+#define TCR2 0xFFD80028
+#define TCPR2 0xFFD8002C
+#define TSTR TSTR0
+
+/* SCI */
+#define SCSMR1 0xFFE00000
+#define SCBRR1 0xFFE00004
+#define SCSCR1 0xFFE00008
+#define SCTDR1 0xFFE0000C
+#define SCSSR1 0xFFE00010
+#define SCRDR1 0xFFE00014
+#define SCSCMR1 0xFFE00018
+#define SCSPTR1 0xFFE0001C
+#define SCF0_BASE SCSMR1
+
+/* SCIF */
+#define SCSMR2 0xFFE80000
+#define SCBRR2 0xFFE80004
+#define SCSCR2 0xFFE80008
+#define SCFTDR2 0xFFE8000C
+#define SCFSR2 0xFFE80010
+#define SCFRDR2 0xFFE80014
+#define SCFCR2 0xFFE80018
+#define SCFDR2 0xFFE8001C
+#define SCSPTR2 0xFFE80020
+#define SCLSR2 0xFFE80024
+#define SCIF1_BASE SCSMR2
+
+/* H-UDI */
+#define SDIR 0xFFF00000
+#define SDDR 0xFFF00008
+#define SDINT 0xFFF00014
+
+#endif /* _ASM_CPU_SH7750_H_ */
--- /dev/null
+/*
+ * U-boot - errno.h Error number defines
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _BLACKFIN_ERRNO_H
+#define _BLACKFIN_ERRNO_H
+
+#define EPERM 1 /* Operation not permitted */
+#define ENOENT 2 /* No such file or directory */
+#define ESRCH 3 /* No such process */
+#define EINTR 4 /* Interrupted system call */
+#define EIO 5 /* I/O error */
+#define ENXIO 6 /* No such device or address */
+#define E2BIG 7 /* Arg list too long */
+#define ENOEXEC 8 /* Exec format error */
+#define EBADF 9 /* Bad file number */
+#define ECHILD 10 /* No child processes */
+#define EAGAIN 11 /* Try again */
+#define ENOMEM 12 /* Out of memory */
+#define EACCES 13 /* Permission denied */
+#define EFAULT 14 /* Bad address */
+#define ENOTBLK 15 /* Block device required */
+#define EBUSY 16 /* Device or resource busy */
+#define EEXIST 17 /* File exists */
+#define EXDEV 18 /* Cross-device link */
+#define ENODEV 19 /* No such device */
+#define ENOTDIR 20 /* Not a directory */
+#define EISDIR 21 /* Is a directory */
+#define EINVAL 22 /* Invalid argument */
+#define ENFILE 23 /* File table overflow */
+#define EMFILE 24 /* Too many open files */
+#define ENOTTY 25 /* Not a typewriter */
+#define ETXTBSY 26 /* Text file busy */
+#define EFBIG 27 /* File too large */
+#define ENOSPC 28 /* No space left on device */
+#define ESPIPE 29 /* Illegal seek */
+#define EROFS 30 /* Read-only file system */
+#define EMLINK 31 /* Too many links */
+#define EPIPE 32 /* Broken pipe */
+#define EDOM 33 /* Math argument out of domain of func */
+#define ERANGE 34 /* Math result not representable */
+#define EDEADLK 35 /* Resource deadlock would occur */
+#define ENAMETOOLONG 36 /* File name too long */
+#define ENOLCK 37 /* No record locks available */
+#define ENOSYS 38 /* Function not implemented */
+#define ENOTEMPTY 39 /* Directory not empty */
+#define ELOOP 40 /* Too many symbolic links encountered */
+#define EWOULDBLOCK EAGAIN /* Operation would block */
+#define ENOMSG 42 /* No message of desired type */
+#define EIDRM 43 /* Identifier removed */
+#define ECHRNG 44 /* Channel number out of range */
+#define EL2NSYNC 45 /* Level 2 not synchronized */
+#define EL3HLT 46 /* Level 3 halted */
+#define EL3RST 47 /* Level 3 reset */
+#define ELNRNG 48 /* Link number out of range */
+#define EUNATCH 49 /* Protocol driver not attached */
+#define ENOCSI 50 /* No CSI structure available */
+#define EL2HLT 51 /* Level 2 halted */
+#define EBADE 52 /* Invalid exchange */
+#define EBADR 53 /* Invalid request descriptor */
+#define EXFULL 54 /* Exchange full */
+#define ENOANO 55 /* No anode */
+#define EBADRQC 56 /* Invalid request code */
+#define EBADSLT 57 /* Invalid slot */
+
+#define EDEADLOCK EDEADLK
+
+#define EBFONT 59 /* Bad font file format */
+#define ENOSTR 60 /* Device not a stream */
+#define ENODATA 61 /* No data available */
+#define ETIME 62 /* Timer expired */
+#define ENOSR 63 /* Out of streams resources */
+#define ENONET 64 /* Machine is not on the network */
+#define ENOPKG 65 /* Package not installed */
+#define EREMOTE 66 /* Object is remote */
+#define ENOLINK 67 /* Link has been severed */
+#define EADV 68 /* Advertise error */
+#define ESRMNT 69 /* Srmount error */
+#define ECOMM 70 /* Communication error on send */
+#define EPROTO 71 /* Protocol error */
+#define EMULTIHOP 72 /* Multihop attempted */
+#define EDOTDOT 73 /* RFS specific error */
+#define EBADMSG 74 /* Not a data message */
+#define EOVERFLOW 75 /* Value too large for defined data type */
+#define ENOTUNIQ 76 /* Name not unique on network */
+#define EBADFD 77 /* File descriptor in bad state */
+#define EREMCHG 78 /* Remote address changed */
+#define ELIBACC 79 /* Can not access a needed shared library */
+#define ELIBBAD 80 /* Accessing a corrupted shared library */
+#define ELIBSCN 81 /* .lib section in a.out corrupted */
+#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
+#define ELIBEXEC 83 /* Cannot exec a shared library directly */
+#define EILSEQ 84 /* Illegal byte sequence */
+#define ERESTART 85 /* Interrupted system call should be restarted */
+#define ESTRPIPE 86 /* Streams pipe error */
+#define EUSERS 87 /* Too many users */
+#define ENOTSOCK 88 /* Socket operation on non-socket */
+#define EDESTADDRREQ 89 /* Destination address required */
+#define EMSGSIZE 90 /* Message too long */
+#define EPROTOTYPE 91 /* Protocol wrong type for socket */
+#define ENOPROTOOPT 92 /* Protocol not available */
+#define EPROTONOSUPPORT 93 /* Protocol not supported */
+#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
+#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
+#define EPFNOSUPPORT 96 /* Protocol family not supported */
+#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
+#define EADDRINUSE 98 /* Address already in use */
+#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
+#define ENETDOWN 100 /* Network is down */
+#define ENETUNREACH 101 /* Network is unreachable */
+#define ENETRESET 102 /* Network dropped connection because of reset */
+#define ECONNABORTED 103 /* Software caused connection abort */
+#define ECONNRESET 104 /* Connection reset by peer */
+#define ENOBUFS 105 /* No buffer space available */
+#define EISCONN 106 /* Transport endpoint is already connected */
+#define ENOTCONN 107 /* Transport endpoint is not connected */
+#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
+#define ETOOMANYREFS 109 /* Too many references: cannot splice */
+#define ETIMEDOUT 110 /* Connection timed out */
+#define ECONNREFUSED 111 /* Connection refused */
+#define EHOSTDOWN 112 /* Host is down */
+#define EHOSTUNREACH 113 /* No route to host */
+#define EALREADY 114 /* Operation already in progress */
+#define EINPROGRESS 115 /* Operation now in progress */
+#define ESTALE 116 /* Stale NFS file handle */
+#define EUCLEAN 117 /* Structure needs cleaning */
+#define ENOTNAM 118 /* Not a XENIX named type file */
+#define ENAVAIL 119 /* No XENIX semaphores available */
+#define EISNAM 120 /* Is a named type file */
+#define EREMOTEIO 121 /* Remote I/O error */
+#define EDQUOT 122 /* Quota exceeded */
+
+#define ENOMEDIUM 123 /* No medium found */
+#define EMEDIUMTYPE 124 /* Wrong medium type */
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_SH_GLOBALDATA_H_
+#define __ASM_SH_GLOBALDATA_H_
+
+typedef struct global_data
+{
+ bd_t *bd;
+ unsigned long flags;
+ unsigned long baudrate;
+ unsigned long cpu_clk; /* CPU clock in Hz! */
+ unsigned long have_console; /* serial_init() was called */
+ unsigned long ram_size; /* RAM size */
+ unsigned long reloc_off; /* Relocation Offset */
+ unsigned long env_addr; /* Address of Environment struct */
+ unsigned long env_valid; /* Checksum of Environment valid */
+ void **jt; /* Standalone app jump table */
+}gd_t;
+
+#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */
+#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
+#define GD_FLG_SILENT 0x00004 /* Silent mode */
+
+#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("r13")
+
+#endif /* __ASM_SH_GLOBALDATA_H_ */
--- /dev/null
+/*
+ * linux/include/asm-sh/io.h
+ *
+ * Copyright (C) 1996-2000 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both
+ * constant addresses and variable addresses.
+ * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture
+ * specific IO header files.
+ * 27-Mar-1999 PJB Second parameter of memcpy_toio is const..
+ * 04-Apr-1999 PJB Added check_signature.
+ * 12-Dec-1999 RMK More cleanups
+ * 18-Jun-2000 RMK Removed virt_to_* and friends definitions
+ */
+#ifndef __ASM_SH_IO_H
+#define __ASM_SH_IO_H
+
+#ifdef __KERNEL__
+
+#include <linux/types.h>
+#include <asm/byteorder.h>
+
+/*
+ * Generic virtual read/write. Note that we don't support half-word
+ * read/writes. We define __arch_*[bl] here, and leave __arch_*w
+ * to the architecture specific code.
+ */
+#define __arch_getb(a) (*(volatile unsigned char *)(a))
+#define __arch_getw(a) (*(volatile unsigned short *)(a))
+#define __arch_getl(a) (*(volatile unsigned int *)(a))
+
+#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v))
+#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v))
+#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v))
+
+extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
+extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
+extern void __raw_writesl(unsigned int addr, const void *data, int longlen);
+
+extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
+extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
+extern void __raw_readsl(unsigned int addr, void *data, int longlen);
+
+#define __raw_writeb(v,a) __arch_putb(v,a)
+#define __raw_writew(v,a) __arch_putw(v,a)
+#define __raw_writel(v,a) __arch_putl(v,a)
+
+#define __raw_readb(a) __arch_getb(a)
+#define __raw_readw(a) __arch_getw(a)
+#define __raw_readl(a) __arch_getl(a)
+
+/*
+ * The compiler seems to be incapable of optimising constants
+ * properly. Spell it out to the compiler in some cases.
+ * These are only valid for small values of "off" (< 1<<12)
+ */
+#define __raw_base_writeb(val,base,off) __arch_base_putb(val,base,off)
+#define __raw_base_writew(val,base,off) __arch_base_putw(val,base,off)
+#define __raw_base_writel(val,base,off) __arch_base_putl(val,base,off)
+
+#define __raw_base_readb(base,off) __arch_base_getb(base,off)
+#define __raw_base_readw(base,off) __arch_base_getw(base,off)
+#define __raw_base_readl(base,off) __arch_base_getl(base,off)
+
+/*
+ * Now, pick up the machine-defined IO definitions
+ */
+#if 0 /* XXX###XXX */
+#include <asm/arch/io.h>
+#endif /* XXX###XXX */
+
+/*
+ * IO port access primitives
+ * -------------------------
+ *
+ * The SH doesn't have special IO access instructions; all IO is memory
+ * mapped. Note that these are defined to perform little endian accesses
+ * only. Their primary purpose is to access PCI and ISA peripherals.
+ *
+ * The machine specific io.h include defines __io to translate an "IO"
+ * address to a memory address.
+ *
+ * Note that we prevent GCC re-ordering or caching values in expressions
+ * by introducing sequence points into the in*() definitions. Note that
+ * __raw_* do not guarantee this behaviour.
+ *
+ * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
+ */
+#define outb(v,p) __raw_writeb(v, p)
+#define outw(v,p) __raw_writew(cpu_to_le16(v),p)
+#define outl(v,p) __raw_writel(cpu_to_le32(v),p)
+
+#define inb(p) ({ unsigned int __v = __raw_readb(p); __v; })
+#define inw(p) ({ unsigned int __v = __le16_to_cpu(__raw_readw(p)); __v; })
+#define inl(p) ({ unsigned int __v = __le32_to_cpu(__raw_readl(p)); __v; })
+
+#define outsb(p,d,l) __raw_writesb(p,d,l)
+#define outsw(p,d,l) __raw_writesw(p,d,l)
+#define outsl(p,d,l) __raw_writesl(p,d,l)
+
+#define insb(p,d,l) __raw_readsb(p,d,l)
+#define insw(p,d,l) __raw_readsw(p,d,l)
+#define insl(p,d,l) __raw_readsl(p,d,l)
+
+#define outb_p(val,port) outb((val),(port))
+#define outw_p(val,port) outw((val),(port))
+#define outl_p(val,port) outl((val),(port))
+#define inb_p(port) inb((port))
+#define inw_p(port) inw((port))
+#define inl_p(port) inl((port))
+
+#define outsb_p(port,from,len) outsb(port,from,len)
+#define outsw_p(port,from,len) outsw(port,from,len)
+#define outsl_p(port,from,len) outsl(port,from,len)
+#define insb_p(port,to,len) insb(port,to,len)
+#define insw_p(port,to,len) insw(port,to,len)
+#define insl_p(port,to,len) insl(port,to,len)
+
+/*
+ * ioremap and friends.
+ *
+ * ioremap takes a PCI memory address, as specified in
+ * linux/Documentation/IO-mapping.txt. If you want a
+ * physical address, use __ioremap instead.
+ */
+extern void * __ioremap(unsigned long offset, size_t size, unsigned long flags);
+extern void __iounmap(void *addr);
+
+/*
+ * Generic ioremap support.
+ *
+ * Define:
+ * iomem_valid_addr(off,size)
+ * iomem_to_phys(off)
+ */
+#ifdef iomem_valid_addr
+#define __arch_ioremap(off,sz,nocache) \
+ ({ \
+ unsigned long _off = (off), _size = (sz); \
+ void *_ret = (void *)0; \
+ if (iomem_valid_addr(_off, _size)) \
+ _ret = __ioremap(iomem_to_phys(_off),_size,0); \
+ _ret; \
+ })
+
+#define __arch_iounmap __iounmap
+#endif
+
+#define ioremap(off,sz) __arch_ioremap((off),(sz),0)
+#define ioremap_nocache(off,sz) __arch_ioremap((off),(sz),1)
+#define iounmap(_addr) __arch_iounmap(_addr)
+
+/*
+ * DMA-consistent mapping functions. These allocate/free a region of
+ * uncached, unwrite-buffered mapped memory space for use with DMA
+ * devices. This is the "generic" version. The PCI specific version
+ * is in pci.h
+ */
+extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
+extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle);
+extern void consistent_sync(void *vaddr, size_t size, int rw);
+
+/*
+ * String version of IO memory access ops:
+ */
+extern void _memcpy_fromio(void *, unsigned long, size_t);
+extern void _memcpy_toio(unsigned long, const void *, size_t);
+extern void _memset_io(unsigned long, int, size_t);
+
+/*
+ * If this architecture has PCI memory IO, then define the read/write
+ * macros. These should only be used with the cookie passed from
+ * ioremap.
+ */
+#ifdef __mem_pci
+
+#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; })
+#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
+#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
+
+#define writeb(v,c) __raw_writeb(v,__mem_pci(c))
+#define writew(v,c) __raw_writew(cpu_to_le16(v),__mem_pci(c))
+#define writel(v,c) __raw_writel(cpu_to_le32(v),__mem_pci(c))
+
+#define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l))
+#define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l))
+#define memcpy_toio(c,a,l) _memcpy_toio(__mem_pci(c),(a),(l))
+
+#define eth_io_copy_and_sum(s,c,l,b) \
+ eth_copy_and_sum((s),__mem_pci(c),(l),(b))
+
+static inline int
+check_signature(unsigned long io_addr, const unsigned char *signature,
+ int length)
+{
+ int retval = 0;
+ do {
+ if (readb(io_addr) != *signature)
+ goto out;
+ io_addr++;
+ signature++;
+ length--;
+ } while (length);
+ retval = 1;
+out:
+ return retval;
+}
+
+#elif !defined(readb)
+
+#define readb(addr) __raw_readb(addr)
+#define readw(addr) __raw_readw(addr)
+#define readl(addr) __raw_readl(addr)
+#define writeb(v,addr) __raw_writeb(v, addr)
+#define writew(v,addr) __raw_writew(v, addr)
+#define writel(v,addr) __raw_writel(v, addr)
+
+#define check_signature(io,sig,len) (0)
+
+#endif /* __mem_pci */
+
+static inline void sync(void)
+{
+}
+#endif /* __KERNEL__ */
+#endif /* __ASM_SH_IO_H */
--- /dev/null
+#ifndef __ASM_SH_IRQFLAGS_H
+#define __ASM_SH_IRQFLAGS_H
+
+static inline void raw_local_irq_enable(void)
+{
+ unsigned long __dummy0, __dummy1;
+
+ __asm__ __volatile__ (
+ "stc sr, %0\n\t"
+ "and %1, %0\n\t"
+#ifdef CONFIG_CPU_HAS_SR_RB
+ "stc r6_bank, %1\n\t"
+ "or %1, %0\n\t"
+#endif
+ "ldc %0, sr\n\t"
+ : "=&r" (__dummy0), "=r" (__dummy1)
+ : "1" (~0x000000f0)
+ : "memory"
+ );
+}
+
+static inline void raw_local_irq_disable(void)
+{
+ unsigned long flags;
+
+ __asm__ __volatile__ (
+ "stc sr, %0\n\t"
+ "or #0xf0, %0\n\t"
+ "ldc %0, sr\n\t"
+ : "=&z" (flags)
+ : /* no inputs */
+ : "memory"
+ );
+}
+
+static inline void set_bl_bit(void)
+{
+ unsigned long __dummy0, __dummy1;
+
+ __asm__ __volatile__ (
+ "stc sr, %0\n\t"
+ "or %2, %0\n\t"
+ "and %3, %0\n\t"
+ "ldc %0, sr\n\t"
+ : "=&r" (__dummy0), "=r" (__dummy1)
+ : "r" (0x10000000), "r" (0xffffff0f)
+ : "memory"
+ );
+}
+
+static inline void clear_bl_bit(void)
+{
+ unsigned long __dummy0, __dummy1;
+
+ __asm__ __volatile__ (
+ "stc sr, %0\n\t"
+ "and %2, %0\n\t"
+ "ldc %0, sr\n\t"
+ : "=&r" (__dummy0), "=r" (__dummy1)
+ : "1" (~0x10000000)
+ : "memory"
+ );
+}
+
+static inline unsigned long __raw_local_save_flags(void)
+{
+ unsigned long flags;
+
+ __asm__ __volatile__ (
+ "stc sr, %0\n\t"
+ "and #0xf0, %0\n\t"
+ : "=&z" (flags)
+ : /* no inputs */
+ : "memory"
+ );
+
+ return flags;
+}
+
+#define raw_local_save_flags(flags) \
+ do { (flags) = __raw_local_save_flags(); } while (0)
+
+static inline int raw_irqs_disabled_flags(unsigned long flags)
+{
+ return (flags != 0);
+}
+
+static inline int raw_irqs_disabled(void)
+{
+ unsigned long flags = __raw_local_save_flags();
+
+ return raw_irqs_disabled_flags(flags);
+}
+
+static inline unsigned long __raw_local_irq_save(void)
+{
+ unsigned long flags, __dummy;
+
+ __asm__ __volatile__ (
+ "stc sr, %1\n\t"
+ "mov %1, %0\n\t"
+ "or #0xf0, %0\n\t"
+ "ldc %0, sr\n\t"
+ "mov %1, %0\n\t"
+ "and #0xf0, %0\n\t"
+ : "=&z" (flags), "=&r" (__dummy)
+ : /* no inputs */
+ : "memory"
+ );
+
+ return flags;
+}
+
+#define raw_local_irq_save(flags) \
+ do { (flags) = __raw_local_irq_save(); } while (0)
+
+#define local_irq_save raw_local_irq_save
+
+static inline void raw_local_irq_restore(unsigned long flags)
+{
+ if ((flags & 0xf0) != 0xf0)
+ raw_local_irq_enable();
+}
+#define local_irq_restore raw_local_irq_restore
+
+#endif /* __ASM_SH_IRQFLAGS_H */
--- /dev/null
+#ifndef __ASM_SH_POSIX_TYPES_H
+#define __ASM_SH_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc. Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned short __kernel_dev_t;
+typedef unsigned long __kernel_ino_t;
+typedef unsigned short __kernel_mode_t;
+typedef unsigned short __kernel_nlink_t;
+typedef long __kernel_off_t;
+typedef int __kernel_pid_t;
+typedef unsigned short __kernel_ipc_pid_t;
+typedef unsigned short __kernel_uid_t;
+typedef unsigned short __kernel_gid_t;
+typedef unsigned int __kernel_size_t;
+typedef int __kernel_ssize_t;
+typedef int __kernel_ptrdiff_t;
+typedef long __kernel_time_t;
+typedef long __kernel_suseconds_t;
+typedef long __kernel_clock_t;
+typedef int __kernel_timer_t;
+typedef int __kernel_clockid_t;
+typedef int __kernel_daddr_t;
+typedef char * __kernel_caddr_t;
+typedef unsigned short __kernel_uid16_t;
+typedef unsigned short __kernel_gid16_t;
+typedef unsigned int __kernel_uid32_t;
+typedef unsigned int __kernel_gid32_t;
+
+typedef unsigned short __kernel_old_uid_t;
+typedef unsigned short __kernel_old_gid_t;
+typedef unsigned short __kernel_old_dev_t;
+
+#ifdef __GNUC__
+typedef long long __kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+ int val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+ int __val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef __FD_SET
+static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp)
+{
+ unsigned long __tmp = __fd / __NFDBITS;
+ unsigned long __rem = __fd % __NFDBITS;
+ __fdsetp->fds_bits[__tmp] |= (1UL<<__rem);
+}
+
+#undef __FD_CLR
+static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp)
+{
+ unsigned long __tmp = __fd / __NFDBITS;
+ unsigned long __rem = __fd % __NFDBITS;
+ __fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem);
+}
+
+
+#undef __FD_ISSET
+static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p)
+{
+ unsigned long __tmp = __fd / __NFDBITS;
+ unsigned long __rem = __fd % __NFDBITS;
+ return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0;
+}
+
+/*
+ * This will unroll the loop for the normal constant case (8 ints,
+ * for a 256-bit fd_set)
+ */
+#undef __FD_ZERO
+static __inline__ void __FD_ZERO(__kernel_fd_set *__p)
+{
+ unsigned long *__tmp = __p->fds_bits;
+ int __i;
+
+ if (__builtin_constant_p(__FDSET_LONGS)) {
+ switch (__FDSET_LONGS) {
+ case 16:
+ __tmp[ 0] = 0; __tmp[ 1] = 0;
+ __tmp[ 2] = 0; __tmp[ 3] = 0;
+ __tmp[ 4] = 0; __tmp[ 5] = 0;
+ __tmp[ 6] = 0; __tmp[ 7] = 0;
+ __tmp[ 8] = 0; __tmp[ 9] = 0;
+ __tmp[10] = 0; __tmp[11] = 0;
+ __tmp[12] = 0; __tmp[13] = 0;
+ __tmp[14] = 0; __tmp[15] = 0;
+ return;
+
+ case 8:
+ __tmp[ 0] = 0; __tmp[ 1] = 0;
+ __tmp[ 2] = 0; __tmp[ 3] = 0;
+ __tmp[ 4] = 0; __tmp[ 5] = 0;
+ __tmp[ 6] = 0; __tmp[ 7] = 0;
+ return;
+
+ case 4:
+ __tmp[ 0] = 0; __tmp[ 1] = 0;
+ __tmp[ 2] = 0; __tmp[ 3] = 0;
+ return;
+ }
+ }
+ __i = __FDSET_LONGS;
+ while (__i) {
+ __i--;
+ *__tmp = 0;
+ __tmp++;
+ }
+}
+
+#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+
+#endif /* __ASM_SH_POSIX_TYPES_H */
--- /dev/null
+#ifndef _ASM_SH_PROCESSOR_H_
+#define _ASM_SH_PROCESSOR_H_
+#if defined CONFIG_SH3
+# include <asm/cpu_sh3.h>
+#elif defined (CONFIG_SH4)
+# include <asm/cpu_sh4.h>
+#endif
+#endif
--- /dev/null
+#ifndef __ASM_SH_PTRACE_H
+#define __ASM_SH_PTRACE_H
+
+/*
+ * Copyright (C) 1999, 2000 Niibe Yutaka
+ * from linux kernel code.
+ */
+
+/*
+ * GCC defines register number like this:
+ * -----------------------------
+ * 0 - 15 are integer registers
+ * 17 - 22 are control/special registers
+ * 24 - 39 fp registers
+ * 40 - 47 xd registers
+ * 48 - fpscr register
+ * -----------------------------
+ *
+ * We follows above, except:
+ * 16 --- program counter (PC)
+ * 22 --- syscall #
+ * 23 --- floating point communication register
+ */
+#define REG_REG0 0
+#define REG_REG15 15
+
+#define REG_PC 16
+
+#define REG_PR 17
+#define REG_SR 18
+#define REG_GBR 19
+#define REG_MACH 20
+#define REG_MACL 21
+
+#define REG_SYSCALL 22
+
+#define REG_FPREG0 23
+#define REG_FPREG15 38
+#define REG_XFREG0 39
+#define REG_XFREG15 54
+
+#define REG_FPSCR 55
+#define REG_FPUL 56
+
+/* options set using PTRACE_SETOPTIONS */
+#define PTRACE_O_TRACESYSGOOD 0x00000001
+
+/*
+ * This struct defines the way the registers are stored on the
+ * kernel stack during a system call or other kernel entry.
+ */
+struct pt_regs {
+ unsigned long regs[16];
+ unsigned long pc;
+ unsigned long pr;
+ unsigned long sr;
+ unsigned long gbr;
+ unsigned long mach;
+ unsigned long macl;
+ long tra;
+};
+
+/*
+ * This struct defines the way the DSP registers are stored on the
+ * kernel stack during a system call or other kernel entry.
+ */
+struct pt_dspregs {
+ unsigned long a1;
+ unsigned long a0g;
+ unsigned long a1g;
+ unsigned long m0;
+ unsigned long m1;
+ unsigned long a0;
+ unsigned long x0;
+ unsigned long x1;
+ unsigned long y0;
+ unsigned long y1;
+ unsigned long dsr;
+ unsigned long rs;
+ unsigned long re;
+ unsigned long mod;
+};
+
+#define PTRACE_GETDSPREGS 55
+#define PTRACE_SETDSPREGS 56
+
+#ifdef __KERNEL__
+#define user_mode(regs) (((regs)->sr & 0x40000000)==0)
+#define instruction_pointer(regs) ((regs)->pc)
+extern void show_regs(struct pt_regs *);
+
+#ifdef CONFIG_SH_DSP
+#define task_pt_regs(task) \
+ ((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \
+ - sizeof(struct pt_dspregs) - sizeof(unsigned long)) - 1)
+#else
+#define task_pt_regs(task) \
+ ((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \
+ - sizeof(unsigned long)) - 1)
+#endif
+
+static inline unsigned long profile_pc(struct pt_regs *regs)
+{
+ unsigned long pc = instruction_pointer(regs);
+
+ if (pc >= 0xa0000000UL && pc < 0xc0000000UL)
+ pc -= 0x20000000;
+ return pc;
+}
+#endif
+
+#endif /* __ASM_SH_PTRACE_H */
--- /dev/null
+#ifndef __ASM_SH_STRING_H
+#define __ASM_SH_STRING_H
+
+/*
+ * Copyright (C) 1999 Niibe Yutaka
+ * But consider these trivial functions to be public domain.
+ *
+ * from linux kernel code.
+ */
+
+#ifdef __KERNEL__ /* only set these up for kernel code */
+
+#define __HAVE_ARCH_STRCPY
+static inline char *strcpy(char *__dest, const char *__src)
+{
+ register char *__xdest = __dest;
+ unsigned long __dummy;
+
+ __asm__ __volatile__("1:\n\t"
+ "mov.b @%1+, %2\n\t"
+ "mov.b %2, @%0\n\t"
+ "cmp/eq #0, %2\n\t"
+ "bf/s 1b\n\t"
+ " add #1, %0\n\t"
+ : "=r" (__dest), "=r" (__src), "=&z" (__dummy)
+ : "0" (__dest), "1" (__src)
+ : "memory", "t");
+
+ return __xdest;
+}
+
+#define __HAVE_ARCH_STRNCPY
+static inline char *strncpy(char *__dest, const char *__src, size_t __n)
+{
+ register char *__xdest = __dest;
+ unsigned long __dummy;
+
+ if (__n == 0)
+ return __xdest;
+
+ __asm__ __volatile__(
+ "1:\n"
+ "mov.b @%1+, %2\n\t"
+ "mov.b %2, @%0\n\t"
+ "cmp/eq #0, %2\n\t"
+ "bt/s 2f\n\t"
+ " cmp/eq %5,%1\n\t"
+ "bf/s 1b\n\t"
+ " add #1, %0\n"
+ "2:"
+ : "=r" (__dest), "=r" (__src), "=&z" (__dummy)
+ : "0" (__dest), "1" (__src), "r" (__src+__n)
+ : "memory", "t");
+
+ return __xdest;
+}
+
+#define __HAVE_ARCH_STRCMP
+static inline int strcmp(const char *__cs, const char *__ct)
+{
+ register int __res;
+ unsigned long __dummy;
+
+ __asm__ __volatile__(
+ "mov.b @%1+, %3\n"
+ "1:\n\t"
+ "mov.b @%0+, %2\n\t"
+ "cmp/eq #0, %3\n\t"
+ "bt 2f\n\t"
+ "cmp/eq %2, %3\n\t"
+ "bt/s 1b\n\t"
+ " mov.b @%1+, %3\n\t"
+ "add #-2, %1\n\t"
+ "mov.b @%1, %3\n\t"
+ "sub %3, %2\n"
+ "2:"
+ : "=r" (__cs), "=r" (__ct), "=&r" (__res), "=&z" (__dummy)
+ : "0" (__cs), "1" (__ct)
+ : "t");
+
+ return __res;
+}
+
+#define __HAVE_ARCH_STRNCMP
+static inline int strncmp(const char *__cs, const char *__ct, size_t __n)
+{
+ register int __res;
+ unsigned long __dummy;
+
+ if (__n == 0)
+ return 0;
+
+ __asm__ __volatile__(
+ "mov.b @%1+, %3\n"
+ "1:\n\t"
+ "mov.b @%0+, %2\n\t"
+ "cmp/eq %6, %0\n\t"
+ "bt/s 2f\n\t"
+ " cmp/eq #0, %3\n\t"
+ "bt/s 3f\n\t"
+ " cmp/eq %3, %2\n\t"
+ "bt/s 1b\n\t"
+ " mov.b @%1+, %3\n\t"
+ "add #-2, %1\n\t"
+ "mov.b @%1, %3\n"
+ "2:\n\t"
+ "sub %3, %2\n"
+ "3:"
+ :"=r" (__cs), "=r" (__ct), "=&r" (__res), "=&z" (__dummy)
+ : "0" (__cs), "1" (__ct), "r" (__cs+__n)
+ : "t");
+
+ return __res;
+}
+
+#undef __HAVE_ARCH_MEMSET
+extern void *memset(void *__s, int __c, size_t __count);
+
+#undef __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *__to, __const__ void *__from, size_t __n);
+
+#undef __HAVE_ARCH_MEMMOVE
+extern void *memmove(void *__dest, __const__ void *__src, size_t __n);
+
+#undef __HAVE_ARCH_MEMCHR
+extern void *memchr(const void *__s, int __c, size_t __n);
+
+#undef __HAVE_ARCH_STRLEN
+extern size_t strlen(const char *);
+
+/* arch/sh/lib/strcasecmp.c */
+extern int strcasecmp(const char *, const char *);
+
+#else /* KERNEL */
+
+/*
+ * let user libraries deal with these,
+ * IMHO the kernel has no place defining these functions for user apps
+ */
+
+#define __HAVE_ARCH_STRCPY 1
+#define __HAVE_ARCH_STRNCPY 1
+#define __HAVE_ARCH_STRCAT 1
+#define __HAVE_ARCH_STRNCAT 1
+#define __HAVE_ARCH_STRCMP 1
+#define __HAVE_ARCH_STRNCMP 1
+#define __HAVE_ARCH_STRNICMP 1
+#define __HAVE_ARCH_STRCHR 1
+#define __HAVE_ARCH_STRRCHR 1
+#define __HAVE_ARCH_STRSTR 1
+#define __HAVE_ARCH_STRLEN 1
+#define __HAVE_ARCH_STRNLEN 1
+#define __HAVE_ARCH_MEMSET 1
+#define __HAVE_ARCH_MEMCPY 1
+#define __HAVE_ARCH_MEMMOVE 1
+#define __HAVE_ARCH_MEMSCAN 1
+#define __HAVE_ARCH_MEMCMP 1
+#define __HAVE_ARCH_MEMCHR 1
+#define __HAVE_ARCH_STRTOK 1
+
+#endif /* KERNEL */
+#endif /* __ASM_SH_STRING_H */
--- /dev/null
+#ifndef __ASM_SH_SYSTEM_H
+#define __ASM_SH_SYSTEM_H
+
+/*
+ * Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima
+ * Copyright (C) 2002 Paul Mundt
+ *
+ * from linux kernel code.
+ */
+
+#include <linux/irqflags.h>
+#include <asm/types.h>
+
+/*
+ * switch_to() should switch tasks to task nr n, first
+ */
+
+#define switch_to(prev, next, last) do { \
+ struct task_struct *__last; \
+ register unsigned long *__ts1 __asm__ ("r1") = &prev->thread.sp; \
+ register unsigned long *__ts2 __asm__ ("r2") = &prev->thread.pc; \
+ register unsigned long *__ts4 __asm__ ("r4") = (unsigned long *)prev; \
+ register unsigned long *__ts5 __asm__ ("r5") = (unsigned long *)next; \
+ register unsigned long *__ts6 __asm__ ("r6") = &next->thread.sp; \
+ register unsigned long __ts7 __asm__ ("r7") = next->thread.pc; \
+ __asm__ __volatile__ (".balign 4\n\t" \
+ "stc.l gbr, @-r15\n\t" \
+ "sts.l pr, @-r15\n\t" \
+ "mov.l r8, @-r15\n\t" \
+ "mov.l r9, @-r15\n\t" \
+ "mov.l r10, @-r15\n\t" \
+ "mov.l r11, @-r15\n\t" \
+ "mov.l r12, @-r15\n\t" \
+ "mov.l r13, @-r15\n\t" \
+ "mov.l r14, @-r15\n\t" \
+ "mov.l r15, @r1 ! save SP\n\t" \
+ "mov.l @r6, r15 ! change to new stack\n\t" \
+ "mova 1f, %0\n\t" \
+ "mov.l %0, @r2 ! save PC\n\t" \
+ "mov.l 2f, %0\n\t" \
+ "jmp @%0 ! call __switch_to\n\t" \
+ " lds r7, pr ! with return to new PC\n\t" \
+ ".balign 4\n" \
+ "2:\n\t" \
+ ".long __switch_to\n" \
+ "1:\n\t" \
+ "mov.l @r15+, r14\n\t" \
+ "mov.l @r15+, r13\n\t" \
+ "mov.l @r15+, r12\n\t" \
+ "mov.l @r15+, r11\n\t" \
+ "mov.l @r15+, r10\n\t" \
+ "mov.l @r15+, r9\n\t" \
+ "mov.l @r15+, r8\n\t" \
+ "lds.l @r15+, pr\n\t" \
+ "ldc.l @r15+, gbr\n\t" \
+ : "=z" (__last) \
+ : "r" (__ts1), "r" (__ts2), "r" (__ts4), \
+ "r" (__ts5), "r" (__ts6), "r" (__ts7) \
+ : "r3", "t"); \
+ last = __last; \
+} while (0)
+
+/*
+ * On SMP systems, when the scheduler does migration-cost autodetection,
+ * it needs a way to flush as much of the CPU's caches as possible.
+ *
+ * TODO: fill this in!
+ */
+static inline void sched_cacheflush(void)
+{
+}
+
+#ifdef CONFIG_CPU_SH4A
+#define __icbi() \
+{ \
+ unsigned long __addr; \
+ __addr = 0xa8000000; \
+ __asm__ __volatile__( \
+ "icbi %0\n\t" \
+ : /* no output */ \
+ : "m" (__m(__addr))); \
+}
+#endif
+
+static inline unsigned long tas(volatile int *m)
+{
+ unsigned long retval;
+
+ __asm__ __volatile__ ("tas.b @%1\n\t"
+ "movt %0"
+ : "=r" (retval): "r" (m): "t", "memory");
+ return retval;
+}
+
+/*
+ * A brief note on ctrl_barrier(), the control register write barrier.
+ *
+ * Legacy SH cores typically require a sequence of 8 nops after
+ * modification of a control register in order for the changes to take
+ * effect. On newer cores (like the sh4a and sh5) this is accomplished
+ * with icbi.
+ *
+ * Also note that on sh4a in the icbi case we can forego a synco for the
+ * write barrier, as it's not necessary for control registers.
+ *
+ * Historically we have only done this type of barrier for the MMUCR, but
+ * it's also necessary for the CCR, so we make it generic here instead.
+ */
+#ifdef CONFIG_CPU_SH4A
+#define mb() __asm__ __volatile__ ("synco": : :"memory")
+#define rmb() mb()
+#define wmb() __asm__ __volatile__ ("synco": : :"memory")
+#define ctrl_barrier() __icbi()
+#define read_barrier_depends() do { } while(0)
+#else
+#define mb() __asm__ __volatile__ ("": : :"memory")
+#define rmb() mb()
+#define wmb() __asm__ __volatile__ ("": : :"memory")
+#define ctrl_barrier() __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop")
+#define read_barrier_depends() do { } while(0)
+#endif
+
+#ifdef CONFIG_SMP
+#define smp_mb() mb()
+#define smp_rmb() rmb()
+#define smp_wmb() wmb()
+#define smp_read_barrier_depends() read_barrier_depends()
+#else
+#define smp_mb() barrier()
+#define smp_rmb() barrier()
+#define smp_wmb() barrier()
+#define smp_read_barrier_depends() do { } while(0)
+#endif
+
+#define set_mb(var, value) do { xchg(&var, value); } while (0)
+
+/*
+ * Jump to P2 area.
+ * When handling TLB or caches, we need to do it from P2 area.
+ */
+#define jump_to_P2() \
+do { \
+ unsigned long __dummy; \
+ __asm__ __volatile__( \
+ "mov.l 1f, %0\n\t" \
+ "or %1, %0\n\t" \
+ "jmp @%0\n\t" \
+ " nop\n\t" \
+ ".balign 4\n" \
+ "1: .long 2f\n" \
+ "2:" \
+ : "=&r" (__dummy) \
+ : "r" (0x20000000)); \
+} while (0)
+
+/*
+ * Back to P1 area.
+ */
+#define back_to_P1() \
+do { \
+ unsigned long __dummy; \
+ ctrl_barrier(); \
+ __asm__ __volatile__( \
+ "mov.l 1f, %0\n\t" \
+ "jmp @%0\n\t" \
+ " nop\n\t" \
+ ".balign 4\n" \
+ "1: .long 2f\n" \
+ "2:" \
+ : "=&r" (__dummy)); \
+} while (0)
+
+static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val)
+{
+ unsigned long flags, retval;
+
+ local_irq_save(flags);
+ retval = *m;
+ *m = val;
+ local_irq_restore(flags);
+ return retval;
+}
+
+static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val)
+{
+ unsigned long flags, retval;
+
+ local_irq_save(flags);
+ retval = *m;
+ *m = val & 0xff;
+ local_irq_restore(flags);
+ return retval;
+}
+
+extern void __xchg_called_with_bad_pointer(void);
+
+#define __xchg(ptr, x, size) \
+({ \
+ unsigned long __xchg__res; \
+ volatile void *__xchg_ptr = (ptr); \
+ switch (size) { \
+ case 4: \
+ __xchg__res = xchg_u32(__xchg_ptr, x); \
+ break; \
+ case 1: \
+ __xchg__res = xchg_u8(__xchg_ptr, x); \
+ break; \
+ default: \
+ __xchg_called_with_bad_pointer(); \
+ __xchg__res = x; \
+ break; \
+ } \
+ \
+ __xchg__res; \
+})
+
+#define xchg(ptr,x) \
+ ((__typeof__(*(ptr)))__xchg((ptr),(unsigned long)(x), sizeof(*(ptr))))
+
+static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
+ unsigned long new)
+{
+ __u32 retval;
+ unsigned long flags;
+
+ local_irq_save(flags);
+ retval = *m;
+ if (retval == old)
+ *m = new;
+ local_irq_restore(flags); /* implies memory barrier */
+ return retval;
+}
+
+/* This function doesn't exist, so you'll get a linker error
+ * if something tries to do an invalid cmpxchg(). */
+extern void __cmpxchg_called_with_bad_pointer(void);
+
+#define __HAVE_ARCH_CMPXCHG 1
+
+static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
+ unsigned long new, int size)
+{
+ switch (size) {
+ case 4:
+ return __cmpxchg_u32(ptr, old, new);
+ }
+ __cmpxchg_called_with_bad_pointer();
+ return old;
+}
+
+#define cmpxchg(ptr,o,n) \
+ ({ \
+ __typeof__(*(ptr)) _o_ = (o); \
+ __typeof__(*(ptr)) _n_ = (n); \
+ (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
+ (unsigned long)_n_, sizeof(*(ptr))); \
+ })
+
+extern void *set_exception_table_vec(unsigned int vec, void *handler);
+
+static inline void *set_exception_table_evt(unsigned int evt, void *handler)
+{
+ return set_exception_table_vec(evt >> 5, handler);
+}
+
+/* XXX
+ * disable hlt during certain critical i/o operations
+ */
+#define HAVE_DISABLE_HLT
+void disable_hlt(void);
+void enable_hlt(void);
+
+#define arch_align_stack(x) (x)
+
+#endif
--- /dev/null
+#ifndef __ASM_SH_TYPES_H
+#define __ASM_SH_TYPES_H
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+#define BITS_PER_LONG 32
+
+#ifndef __ASSEMBLY__
+
+
+typedef __signed__ char s8;
+typedef unsigned char u8;
+
+typedef __signed__ short s16;
+typedef unsigned short u16;
+
+typedef __signed__ int s32;
+typedef unsigned int u32;
+
+typedef __signed__ long long s64;
+typedef unsigned long long u64;
+
+/* Dma addresses are 32-bits wide. */
+
+typedef u32 dma_addr_t;
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_SH_TYPES_H */
--- /dev/null
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef __ASM_SH_U_BOOT_H_
+#define __ASM_SH_U_BOOT_H_
+
+typedef struct bd_info {
+ unsigned long bi_memstart; /* start of DRAM memory */
+ unsigned long bi_memsize; /* size of DRAM memory in bytes */
+ unsigned long bi_flashstart; /* start of FLASH memory */
+ unsigned long bi_flashsize; /* size of FLASH memory */
+ unsigned long bi_flashoffset; /* reserved area for startup monitor */
+ unsigned long bi_sramstart; /* start of SRAM memory */
+ unsigned long bi_sramsize; /* size of SRAM memory */
+ unsigned long bi_ip_addr; /* IP Address */
+ unsigned char bi_enetaddr[6]; /* Ethernet adress */
+ unsigned long bi_baudrate; /* Console Baudrate */
+ unsigned long bi_boot_params; /* where this board expects params */
+} bd_t;
+
+#endif
--- /dev/null
+/* Permission is hereby granted to copy, modify and redistribute this code
+ * in terms of the GNU Library General Public License, Version 2 or later,
+ * at your option.
+ */
+
+/* macros to translate to/from binary and binary-coded decimal (frequently
+ * found in RTC chips).
+ */
+
+#ifndef _BCD_H
+#define _BCD_H
+
+#define BCD2BIN(val) (((val) & 0x0f) + ((val)>>4)*10)
+#define BIN2BCD(val) ((((val)/10)<<4) + (val)%10)
+
+/* backwards compat */
+#define BCD_TO_BIN(val) ((val)=BCD2BIN(val))
+#define BIN_TO_BCD(val) ((val)=BIN2BCD(val))
+
+#endif /* _BCD_H */
/*
* enable common handling for all TQM8xxL/M boards:
- * - CONFIG_TQM8xxM will be defined for all TQM8xxM and TQM885D boards
+ * - CONFIG_TQM8xxM will be defined for all TQM8xxM boards
* - CONFIG_TQM8xxL will be defined for all TQM8xxL _and_ TQM8xxM boards
+ * and for the TQM885D board
*/
#if defined(CONFIG_TQM823M) || defined(CONFIG_TQM850M) || \
defined(CONFIG_TQM855M) || defined(CONFIG_TQM860M) || \
- defined(CONFIG_TQM862M) || defined(CONFIG_TQM866M) || \
- defined(CONFIG_TQM885D)
+ defined(CONFIG_TQM862M) || defined(CONFIG_TQM866M)
# ifndef CONFIG_TQM8xxM
# define CONFIG_TQM8xxM
# endif
#endif
#if defined(CONFIG_TQM823L) || defined(CONFIG_TQM850L) || \
defined(CONFIG_TQM855L) || defined(CONFIG_TQM860L) || \
- defined(CONFIG_TQM862L) || defined(CONFIG_TQM8xxM)
+ defined(CONFIG_TQM862L) || defined(CONFIG_TQM8xxM) || \
+ defined(CONFIG_TQM885D)
# ifndef CONFIG_TQM8xxL
# define CONFIG_TQM8xxL
# endif
int pci_pre_init (struct pci_controller * );
#endif
-#if defined(CONFIG_PCI) && defined(CONFIG_440)
+#if defined(CONFIG_PCI) && (defined(CONFIG_440) || defined(CONFIG_405EX))
# if defined(CFG_PCI_TARGET_INIT)
void pci_target_init (struct pci_controller *);
# endif
void pci_master_init (struct pci_controller *);
# endif
int is_pci_host (struct pci_controller *);
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440SPE) || defined(CONFIG_405EX)
void pcie_setup_hoses(int busno);
#endif
#endif
#if defined(CONFIG_MPC85xx)
typedef MPC85xx_SYS_INFO sys_info_t;
void get_sys_info ( sys_info_t * );
+ulong get_ddr_freq (ulong);
#endif
#if defined(CONFIG_MPC86xx)
typedef MPC86xx_SYS_INFO sys_info_t;
#if defined(CONFIG_4xx) || defined(CONFIG_IOP480)
# if defined(CONFIG_440)
- typedef PPC440_SYS_INFO sys_info_t;
# if defined(CONFIG_440SPE)
unsigned long determine_sysper(void);
unsigned long determine_pci_clock_per(void);
- int ppc440spe_revB(void);
# endif
-# else
- typedef PPC405_SYS_INFO sys_info_t;
# endif
+typedef PPC4xx_SYS_INFO sys_info_t;
+int ppc440spe_revB(void);
void get_sys_info ( sys_info_t * );
#endif
#define CFG_ETH_DEV_FN 0x0000
#define CFG_ETH_IOBASE 0x0fff0000
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 2048 /* For PLX IOP480 */
-#define CFG_CACHELINE_SIZE 16 /* For AMCC 401/403 CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
/*
* Init Memory Controller:
*
#define CFG_ENV_ADDR \
(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */
#endif
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 16384
-#define CFG_CACHELINE_SIZE 32
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
/*
* Init Memory Controller:
#define CFG_ENV_ADDR_REDUND 0xFFFA0000
#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
- /* have only 8kB, 16kB is save here */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Init Memory Controller:
*
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
- /* have only 8kB, 16kB is save here */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Init Memory Controller:
*
/* mask of address bits that overflow into the "EEPROM chip address" */
#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Init Memory Controller:
*
#define CFG_EEPROM_WREN 1
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
- /* have only 8kB, 16kB is save here */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*/
#define CFG_EEPROM_WREN 1
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
- /* have only 8kB, 16kB is save here */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Init Memory Controller:
*
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Init Memory Controller:
*
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
- /* have only 8kB, 16kB is save here */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Init Memory Controller:
*
#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */
#define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
- /* have only 8kB, 16kB is save here */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Init Memory Controller:
*
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
- /* have only 8kB, 16kB is save here */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Init Memory Controller:
*
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************************************
- * board/config_CPCI440.h - configuration for esd CPCI-440 board
- ***********************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_CPCI440 1 /* Board is ebony */
-#define CONFIG_440GP 1 /* Specifc GP support */
-#define CONFIG_440 1 /* ... PPC440 family */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#undef CFG_DRAM_TEST /* Disable-takes long time! */
-#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */
-#if 1
-#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */
-#else
-#define CFG_MONITOR_BASE 0x01fc0000 /* start of monitor */
-#endif
-#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
-#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
-
-#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000)
-#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in internal SRAM)
- *----------------------------------------------------------------------*/
-#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
-#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
-
-#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-
-#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Mon */
-#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#undef CFG_EXT_SERIAL_CLOCK /* (1843200 * 6) / * Ext clk @ 11.059 MHz */
-#define CONFIG_BAUDRATE 9600
-
-#define CFG_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
-
-/*-----------------------------------------------------------------------
- * NVRAM/RTC
- *
- * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
- * The DS1743 code assumes this condition (i.e. -- it assumes the base
- * address for the RTC registers is:
- *
- * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
- *
- *----------------------------------------------------------------------*/
-#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */
-#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#if 1 /* test-only */
-
-#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_FLASH_INCREMENT 0 /* there is only one bank */
-#define CFG_FLASH_PROTECTION 1 /* use hardware protection */
-#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-#undef CFG_FLASH_BASE
-#define CFG_FLASH_BASE 0xFF800000 /* test-only...*/
-
-#else /* test-only */
-
-#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
-#define CFG_MAX_FLASH_SECT 32 /* sectors per device */
-
-#undef CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#endif
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-#if 0 /* test-only */
-#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */
-#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
-#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
-
-#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
-#define CFG_ENV_ADDR \
- (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)
-#else
-
-#if 0 /* test-only */
-#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET 0x010 /* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
- /* total size of a CAT24WC16 is 2048 bytes */
-#else
-#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
-#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-#endif
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_HARD_I2C /* I2c with hardware support */
-#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CFG_I2C_SLAVE 0x7F
-
-#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
-#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
- /* 16 byte page write mode using*/
- /* last 4 bits of the address */
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-
-#endif
-
-#undef CONFIG_BOOTARGS
-#undef CONFIG_BOOTCOMMAND
-
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
-#define CONFIG_BAUDRATE 9600
-
-#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 1 /* PHY address */
-#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_EEPROM
-
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#undef CONFIG_SPD_EEPROM /* don't use SPD EEPROM for setup */
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-
-#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
-#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CFG_LOAD_ADDR 0x100000 /* default load address */
-#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#if 0 /* test-only */
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CFG_I2C_SLAVE 0x7F
-#endif
-
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#if 0
-#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
- /* resource configuration */
-
-#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
-
-#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
-
-#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
-#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
-#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
-#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
-#endif
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-
-/* Configuration Port location */
-#define CONFIG_PORT_ADDR 0xF0000500
-
-/*-----------------------------------------------------------------------
- * Definitions for Serial Presence Detect EEPROM address
- * (to get SDRAM settings)
- */
-#define SPD_EEPROM_ADDRESS 0x50
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-#endif /* __CONFIG_H */
#define CFG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */
/* total size of a CAT24WC08 is 1024 bytes */
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Init Memory Controller:
*
#define CFG_MEMTEST_END (CFG_SDRAM_SIZE * 1024 * 1024 - CFG_MEM_END_USAGE)
/* END ENVIRONNEMENT FLASH */
-/*-----------------------------------------------------------------------
- * Cache Configuration. Only used to ..?? clear it, I guess..
- */
-#define CFG_DCACHE_SIZE 16384
-#define CFG_CACHELINE_SIZE 32
-
/*
* Init Memory Controller:
*
#define CFG_PCI9054_DEV_FN 0x0800
#define CFG_PCI9054_IOBASE 0x0eff0000
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 2048 /* For PLX IOP480 */
-#define CFG_CACHELINE_SIZE 16 /* For AMCC 401/403 CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
/*
* Init Memory Controller:
*
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
- /* have only 8kB, 16kB is save here */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*/
#define CFG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */
/* total size of a CAT24WC08 is 1024 bytes */
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Init Memory Controller:
*
#define CFG_ENV_ADDR \
(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */
#endif
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
/*
* Init Memory Controller:
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-/* Cache configuration */
-#define CFG_DCACHE_SIZE 8192
-#define CFG_CACHELINE_SIZE 32
-
/*
* Internal Definitions
*
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
- /* have only 8kB, 16kB is save here */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*/
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
- /* have only 8kB, 16kB is save here */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*/
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+/* use CFI flash driver */
+#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_USE_BUFFER_WRITE 1
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
- /* have only 8kB, 16kB is save here */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Init Memory Controller:
*
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 16384 /* For AMCC 405GPr CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Init Memory Controller:
*
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
-#define CFG_CACHELINE_SIZE 32
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */
-#endif
/*
* Internal Definitions
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
-#define CFG_CACHELINE_SIZE 32
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */
-#endif
/*
* Internal Definitions
#define MTDPARTS_DEFAULT "mtdparts=mip405-0:-(jffs2)"
*/
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 0x4000 /* For AMCC 405GPr CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*-----------------------------------------------------------------------
* Logbuffer Configuration
*/
#define CFG_ENV_ADDR \
(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */
#endif
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
/*
* Init Memory Controller:
#endif
/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE 1
-#define CONFIG_OF_BOARD_SETUP 1
-
-#define OF_CPU "PowerPC,8540@0"
-#define OF_SOC "soc8540@e0000000"
-#define OF_TBCLK (bd->bi_busfreq / 8)
-#define OF_STDOUT_PATH "/soc8540@e0000000/serial@4500"
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
#define CFG_64BIT_VSPRINTF 1
#define CFG_64BIT_STRTOUL 1
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
+#define CONFIG_CMD_ELF
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#endif
/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE 1
-#define CONFIG_OF_BOARD_SETUP 1
-
-#define OF_CPU "PowerPC,8541@0"
-#define OF_SOC "soc8541@e0000000"
-#define OF_TBCLK (bd->bi_busfreq / 8)
-#define OF_STDOUT_PATH "/soc8541@e0000000/serial@4600"
-#define OF_PCI "pci@e0008000"
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/*
* I2C
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#endif
/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE 1
-#define CONFIG_OF_BOARD_SETUP 1
-
-#define OF_CPU "PowerPC,8544@0"
-#define OF_SOC "soc8544@e0000000"
-#define OF_TBCLK (bd->bi_busfreq / 8)
-#define OF_STDOUT_PATH "/soc8544@e0000000/serial@4500"
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/* I2C */
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_ETHADDR 00:E0:0C:02:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
-#define CONFIG_HAS_ETH2
-#define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
-#define CONFIG_HAS_ETH3
-#define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
#endif
#define CONFIG_IPADDR 192.168.1.251
#define CONFIG_BOOTFILE 8544ds/uImage.uboot
#define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */
-#define CONFIG_SERVERIP 192.168.0.1
-#define CONFIG_GATEWAYIP 192.168.0.1
+#define CONFIG_SERVERIP 192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK 255.255.0.0
#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
#define CONFIG_BAUDRATE 115200
-#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
-#define PCIE_ENV \
- "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
- "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
- "pcieerr=md ${a}020 1; md ${a}e00 e;" \
- "pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
- "pci d.w $b.0 56 1;" \
- "pci d $b.0 104 1;pci d $b.0 110 1;pci d $b.0 130 1\0" \
- "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff;" \
- "pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff;" \
- "pci w $b.0 104 ffffffff; pci w $b.0 110 ffffffff;" \
- "pci w $b.0 130 ffffffff\0" \
- "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \
- "pcie1regs=setenv a e000a; run pciereg\0" \
- "pcie2regs=setenv a e0009; run pciereg\0" \
- "pcie3regs=setenv a e000b; run pciereg\0" \
- "pcie1cfg=setenv b 3; run pciecfg\0" \
- "pcie2cfg=setenv b 5; run pciecfg\0" \
- "pcie3cfg=setenv b 0; run pciecfg\0" \
- "pcie1err=setenv a e000a; setenv b 3; run pcieerr\0" \
- "pcie2err=setenv a e0009; setenv b 5; run pcieerr\0" \
- "pcie3err=setenv a e000b; setenv b 0; run pcieerr\0" \
- "pcie1errc=setenv a e000a; setenv b 3; run pcieerrc\0" \
- "pcie2errc=setenv a e0009; setenv b 5; run pcieerrc\0" \
- "pcie3errc=setenv a e000b; setenv b 0; run pcieerrc\0"
-#else
-#define PCIE_ENV ""
-#endif
-
-#if defined(CONFIG_PCI1)
-#define PCI_ENV \
- "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
- "echo e;md ${a}e00 9\0" \
- "pci1regs=setenv a e0008; run pcireg\0" \
- "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
- "pci d.w $b.0 56 1\0" \
- "pcierrc=mw ${a}e00 ffffffff; mw ${a}e0c 0; pci w.b $b.0 7 ff;" \
- "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff\0" \
- "pci1err=setenv a e0008; setenv b 7; run pcierr\0" \
- "pci1errc=setenv a e0008; setenv b 7; run pcierrc\0"
-#else
-#define PCI_ENV ""
-#endif
-
-#if defined(CONFIG_TSEC_ENET)
-#define ENET_ENV \
- "enetreg1=md ${a}000 2; md ${a}010 9; md ${a}050 4; md ${a}08c 1;" \
- "md ${a}098 2\0" \
- "enetregt=echo t;md ${a}100 6; md ${a}140 2; md ${a}180 10; md ${a}200 10\0" \
- "enetregr=echo r;md ${a}300 6; md ${a}330 5; md ${a}380 10; md ${a}400 10\0" \
- "enetregm=echo mac;md ${a}500 5; md ${a}520 28;echo fifo;md ${a}a00 1;" \
- "echo mib;md ${a}680 31\0" \
- "enetreg=run enetreg1; run enetregm; run enetregt; run enetregr\0" \
- "enet1regs=setenv a e0024; run enetreg\0" \
- "enet3regs=setenv a e0026; run enetreg\0"
-#else
-#define ENET_ENV ""
-#endif
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=8544ds/ramdisk.uboot\0" \
- "dtbaddr=c00000\0" \
- "dtbfile=8544ds/mpc8544ds.dtb\0" \
- "bdev=sda3\0" \
- "eoi=mw e00400b0 0\0" \
- "iack=md e00400a0 1\0" \
- "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \
- "md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \
- "ddrregs=setenv a e0002; run ddrreg\0" \
- "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \
- "md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \
- "guregs=setenv a e00e0; run gureg\0" \
- "ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \
- "ecmregs=setenv a e0001; run ecmreg\0" \
- "lawregs=md e0000c08 4b\0" \
- "lbcregs=md e0005000 36\0" \
- "dma0regs=md e0021100 12\0" \
- "dma1regs=md e0021180 12\0" \
- "dma2regs=md e0021200 12\0" \
- "dma3regs=md e0021280 12\0" \
- PCIE_ENV \
- PCI_ENV \
- ENET_ENV
-
+ "fdtaddr=c00000\0" \
+ "fdtfile=8544ds/mpc8544ds.dtb\0" \
+ "bdev=sda3\0"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
- "tftp $dtbaddr $dtbfile;" \
- "bootm $loadaddr - $dtbaddr"
-
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
- "tftp $dtbaddr $dtbfile;" \
- "bootm $loadaddr $ramdiskaddr $dtbaddr"
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
#define CONFIG_BOOTCOMMAND \
"setenv bootargs root=/dev/$bdev rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
- "tftp $dtbaddr $dtbfile;" \
- "bootm $loadaddr - $dtbaddr"
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
#endif /* __CONFIG_H */
#undef CONFIG_RIO
#undef CONFIG_PCI2
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#endif
/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE 1
-#define CONFIG_OF_BOARD_SETUP 1
-
-#define OF_CPU "PowerPC,8548@0"
-#define OF_SOC "soc8548@e0000000"
-#define OF_TBCLK (bd->bi_busfreq / 8)
-#define OF_STDOUT_PATH "/soc8548@e0000000/serial@4600"
-#define OF_PCI "pci@e0008000"
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/*
* I2C
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_BAUDRATE 115200
-#if defined(CONFIG_PCIE1)
-#define PCIE_ENV \
- "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
- "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
- "pcieerr=md ${a}020 1; md ${a}e00 e; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
- "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \
- "pci d $b.0 130 1\0" \
- "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;" \
- "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;"\
- "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \
- "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \
- "pcie1regs=setenv a e000a; run pciereg\0" \
- "pcie1cfg=setenv b 3; run pciecfg\0" \
- "pcie1err=setenv a e000a; setenv b 3; run pcieerr\0" \
- "pcie1errc=setenv a e000a; setenv b 3; run pcieerrc\0"
-#else
-#define PCIE_ENV ""
-#endif
-
-#if defined(CONFIG_PCI1) || defined(CONFIG_PCI2)
-#define PCI_ENV \
- "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
- "echo e;md ${a}e00 9\0" \
- "pcierr=md ${a}e00 8; pci d.b $b.0 7 1;pci d.w $b.0 1e 1;" \
- "pci d.w $b.0 56 1\0" \
- "pcierrc=mw ${a}e00 ffffffff; mw ${a}e0c 0; pci w.b $b.0 7 ff;" \
- "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff\0"
-#else
-#define PCI_ENV ""
-#endif
-
-#if defined(CONFIG_PCI1)
-#define PCI_ENV1 \
- "pci1regs=setenv a e0008; run pcireg\0" \
- "pci1err=setenv a e0008; setenv b 0; run pcierr\0" \
- "pci1errc=setenv a e0008; setenv b 0; run pcierrc\0"
-#else
-#define PCI_ENV1 ""
-#endif
-
-#if defined(CONFIG_PCI2)
-#define PCI_ENV2 \
- "pci2regs=setenv a e0009; run pcireg\0" \
- "pci2err=setenv a e0009; setenv b 123; run pcierr\0" \
- "pci2errc=setenv a e0009; setenv b 123; run pcierrc\0"
-#else
-#define PCI_ENV2 ""
-#endif
-
-#if defined(CONFIG_TSEC_ENET)
-#define ENET_ENV \
- "enetreg1=md ${a}000 2; md ${a}010 9; md ${a}050 4; md ${a}08c 1;" \
- "md ${a}098 2\0" \
- "enetregt=echo t;md ${a}100 6; md ${a}140 2; md ${a}180 10; md ${a}200 10\0" \
- "enetregr=echo r;md ${a}300 6; md ${a}330 5; md ${a}380 10; md ${a}400 10\0" \
- "enetregm=echo mac;md ${a}500 5; md ${a}520 28;echo fifo;md ${a}a00 1;" \
- "echo mib;md ${a}680 31\0" \
- "enetreg=run enetreg1; run enetregm; run enetregt; run enetregr\0" \
- "enet1regs=setenv a e0024; run enetreg\0" \
- "enet2regs=setenv a e0025; run enetreg\0" \
- "enet3regs=setenv a e0026; run enetreg\0" \
- "enet4regs=setenv a e0027; run enetreg\0"
-#else
-#define ENET_ENV ""
-#endif
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=ramdisk.uboot\0" \
"fdtaddr=c00000\0" \
- "fdtfile=mpc8548cds.dtb\0" \
- "eoi=mw e00400b0 0\0" \
- "iack=md e00400a0 1\0" \
- "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \
- "md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \
- "ddrregs=setenv a e0002; run ddrreg\0" \
- "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \
- "md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \
- "guregs=setenv a e00e0; run gureg\0" \
- "ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \
- "ecmregs=setenv a e0001; run ecmreg\0" \
- "lawregs=md e0000c08 4b\0" \
- "lbcregs=md e0005000 36\0" \
- "dma0regs=md e0021100 12\0" \
- "dma1regs=md e0021180 12\0" \
- "dma2regs=md e0021200 12\0" \
- "dma3regs=md e0021280 12\0" \
- PCIE_ENV \
- PCI_ENV \
- PCI_ENV1 \
- PCI_ENV2 \
- ENET_ENV
+ "fdtfile=mpc8548cds.dtb\0"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
#endif
/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE 1
-#define CONFIG_OF_BOARD_SETUP 1
-
-#define OF_CPU "PowerPC,8555@0"
-#define OF_SOC "soc8555@e0000000"
-#define OF_TBCLK (bd->bi_busfreq / 8)
-#define OF_STDOUT_PATH "/soc8555@e0000000/serial@4600"
-#define OF_PCI "pci@e0008000"
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/*
* I2C
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#endif
/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE 1
-#define CONFIG_OF_BOARD_SETUP 1
-
-#define OF_CPU "PowerPC,8560@0"
-#define OF_SOC "soc8560@e0000000"
-#define OF_TBCLK (bd->bi_busfreq / 8)
-#define OF_STDOUT_PATH "/soc8560@e0000000/serial@4500"
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/*
* I2C
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
+#define CONFIG_CMD_ELF
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CFG_LOAD_ADDR 0x1000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
#define CONFIG_HAS_ETH2
#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
+#define CONFIG_HAS_ETH3
+#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
#endif
#define CONFIG_IPADDR 192.168.1.253
#define CONFIG_MPC8568 1 /* MPC8568 specific */
#define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */
-#define CONFIG_PCI
+#define CONFIG_PCI 1 /* Enable PCI/PCIE */
+#define CONFIG_PCI1 1 /* PCI controller */
+#define CONFIG_PCIE1 1 /* PCIE controller */
+#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
+#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_QE /* Enable QE */
#define CONFIG_ENV_OVERWRITE
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
+#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
+#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000)
+
/*
* DDR Setup
*/
#endif
/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE 1
-#define CONFIG_OF_BOARD_SETUP 1
-
-#define OF_CPU "PowerPC,8568@0"
-#define OF_SOC "soc8568@e0000000"
-#define OF_QE "qe@e0080000"
-#define OF_TBCLK (bd->bi_busfreq / 8)
-#define OF_STDOUT_PATH "/soc8568@e0000000/serial@4500"
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/*
* I2C
#define CFG_PCI1_IO_PHYS 0xe2000000
#define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */
-#define CFG_PEX_MEM_BASE 0xa0000000
-#define CFG_PEX_MEM_PHYS CFG_PEX_MEM_BASE
-#define CFG_PEX_MEM_SIZE 0x10000000 /* 256M */
-#define CFG_PEX_IO_BASE 0x00000000
-#define CFG_PEX_IO_PHYS 0xe2800000
-#define CFG_PEX_IO_SIZE 0x00800000 /* 8M */
+#define CFG_PCIE1_MEM_BASE 0xa0000000
+#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE
+#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCIE1_IO_BASE 0x00000000
+#define CFG_PCIE1_IO_PHYS 0xe2800000
+#define CFG_PCIE1_IO_SIZE 0x00800000 /* 8M */
#define CFG_SRIO_MEM_BASE 0xc0000000
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
+/* PCI view of System Memory */
+#define CFG_PCI_MEMORY_BUS 0x00000000
+#define CFG_PCI_MEMORY_PHYS 0x00000000
+#define CFG_PCI_MEMORY_SIZE 0x80000000
+
#endif /* CONFIG_PCI */
#ifndef CONFIG_NET_MULTI
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Init Memory Controller:
*
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Init Memory Controller:
*
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Init Memory Controller:
*
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Init Memory Controller:
*/
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
+#define CFG_EEPROM_WREN 1
/* CAT24WC08/16... */
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
- /* have only 8kB, 16kB is save here */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*/
* GPIO0[28-29] - UART1 data signal input/output
* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
*/
-#define CFG_GPIO0_OSRH 0x40000550
+#define CFG_GPIO0_OSRH 0x00000550
#define CFG_GPIO0_OSRL 0x00000110
#define CFG_GPIO0_ISR1H 0x00000000
#define CFG_GPIO0_ISR1L 0x15555445
#define CFG_GPIO0_TSRH 0x00000000
#define CFG_GPIO0_TSRL 0x00000000
-#define CFG_GPIO0_TCR 0xF7FE0014
+#define CFG_GPIO0_TCR 0x77FE0014
#define CFG_DUART_RST (0x80000000 >> 14)
+#define CFG_EEPROM_WP (0x80000000 >> 0)
/*
* Internal Definitions
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
- /* have only 8kB, 16kB is save here */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*/
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
+ * Based on the sequoia configuration file.
+ *
+ * (C) Copyright 2006-2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2006
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * PMC440.h - configuration for esd PMC440 boards
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_440EPX 1 /* Specific PPC440EPx */
+#define CONFIG_440 1 /* ... PPC440 family */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+
+#define CONFIG_SYS_CLK_FREQ 33333400
+
+#define CONFIG_4xx_DCACHE /* enable dcache */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+#define CONFIG_BOARD_TYPES 1 /* support board types */
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
+#define CFG_MALLOC_LEN (1024 * 1024) /* Reserve 256 kB for malloc() */
+
+#define CONFIG_PRAM 0 /* use pram variable to overwrite */
+
+#define CFG_BOOT_BASE_ADDR 0xf0000000
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */
+#define CFG_OCM_BASE 0xe0010000 /* ocm */
+#define CFG_OCM_DATA_ADDR CFG_OCM_BASE
+#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
+#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
+#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
+#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
+#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
+#define CFG_PCI_MEMSIZE 0x80000000 /* 2GB! */
+
+/* Don't change either of these */
+#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
+
+#define CFG_USB2D0_BASE 0xe0000100
+#define CFG_USB_DEVICE 0xe0000000
+#define CFG_USB_HOST 0xe0000400
+#define CFG_FPGA_BASE0 0xef000000 /* 32 bit */
+#define CFG_FPGA_BASE1 0xef100000 /* 16 bit */
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer
+ *----------------------------------------------------------------------*/
+/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
+#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
+#define CFG_INIT_RAM_END (4 << 10)
+#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef CFG_EXT_SERIAL_CLOCK
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SERIAL_MULTI 1
+#undef CONFIG_UART1_CONSOLE /* console on front panel */
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#define CFG_ENV_IS_IN_EEPROM 1 /* use FLASH for environment vars */
+#else
+#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
+#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */
+#endif
+
+/*-----------------------------------------------------------------------
+ * RTC
+ *----------------------------------------------------------------------*/
+#define CONFIG_RTC_RX8025
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_CFI /* The flash is CFI compatible */
+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
+
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif
+
+#ifdef CFG_ENV_IS_IN_EEPROM
+#define CFG_ENV_OFFSET 0 /* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env vars */
+#endif
+
+/*
+ * IPL (Initial Program Loader, integrated inside CPU)
+ * Will load first 4k from NAND (SPL) into cache and execute it from there.
+ *
+ * SPL (Secondary Program Loader)
+ * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
+ * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
+ * controller and the NAND controller so that the special U-Boot image can be
+ * loaded from NAND to SDRAM.
+ *
+ * NUB (NAND U-Boot)
+ * This NAND U-Boot (NUB) is a special U-Boot version which can be started
+ * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
+ *
+ * On 440EPx the SPL is copied to SDRAM before the NAND controller is
+ * set up. While still running from cache, I experienced problems accessing
+ * the NAND controller. sr - 2006-08-25
+ */
+#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
+#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
+#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_BASE + (12 << 10)) /* Copy SPL here */
+#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
+#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
+#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
+
+/*
+ * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
+ */
+#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
+#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
+
+/*
+ * Now the NAND chip has to be defined (no autodetection used!)
+ */
+#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */
+#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
+#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */
+#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
+#undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
+
+#define CFG_NAND_ECCSIZE 256
+#define CFG_NAND_ECCBYTES 3
+#define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
+#define CFG_NAND_OOBSIZE 16
+#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
+#define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
+
+#ifdef CFG_ENV_IS_IN_NAND
+/*
+ * For NAND booting the environment is embedded in the U-Boot image. Please take
+ * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
+ */
+#define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE
+#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE)
+#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE)
+#endif
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CFG_MBYTES_SDRAM (256) /* 256MB */
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
+#endif
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+#define CONFIG_I2C_CMD_TREE 1
+#define CONFIG_I2C_MULTI_BUS 1
+
+#define CFG_I2C_MULTI_EEPROMS
+
+#define CFG_I2C_EEPROM_ADDR 0x54
+#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 5
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
+
+#define CFG_EEPROM_WREN 1
+#define CFG_I2C_BOOT_EEPROM_ADDR 0x52
+
+/*
+ * standard dtt sensor configuration - bottom bit will determine local or
+ * remote sensor of the TMP401
+ */
+#define CONFIG_DTT_SENSORS { 0, 1 }
+
+/*
+ * The PMC440 uses a TI TMP401 temperature sensor. This part
+ * is basically compatible to the ADM1021 that is supported
+ * by U-Boot.
+ *
+ * - i2c addr 0x4c
+ * - conversion rate 0x02 = 0.25 conversions/second
+ * - ALERT ouput disabled
+ * - local temp sensor enabled, min set to 0 deg, max set to 70 deg
+ * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
+ */
+#define CONFIG_DTT_ADM1021
+#define CFG_DTT_ADM1021 { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
+
+#define CONFIG_PREBOOT /* enable preboot variable */
+
+#undef CONFIG_BOOTARGS
+
+/* Setup some board specific values for the default environment variables */
+#define CONFIG_HOSTNAME pmc440
+#define CFG_BOOTFILE "bootfile=/tftpboot/pmc440/uImage\0"
+#define CFG_ROOTPATH "rootpath=/opt/eldk_410/ppc_4xx\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CFG_BOOTFILE \
+ CFG_ROOTPATH \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
+ "bootm\0" \
+ "kernel_addr=FC000000\0" \
+ "ramdisk_addr=FC180000\0" \
+ "load=tftp 200000 /tftpboot/pmc440/u-boot.bin\0" \
+ "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
+ "cp.b 200000 FFFA0000 60000\0" \
+ ""
+
+#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_IBM_EMAC4_V4 1
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
+
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+
+#define CONFIG_HAS_ETH0
+#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NET_MULTI 1
+#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
+#define CONFIG_PHY1_ADDR 1
+#define CONFIG_RESET_PHY_R 1
+
+/* USB */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_USB_STORAGE
+#define CFG_OHCI_BE_CONTROLLER
+
+#define CFG_USB_OHCI_BOARD_INIT 1
+#define CFG_USB_OHCI_CPU_INIT 1
+#define CFG_USB_OHCI_REGS_BASE CFG_USB_HOST
+#define CFG_USB_OHCI_SLOT_NAME "ppc440"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
+
+/* Comment this out to enable USB 1.1 device */
+#define USB_2_0_DEVICE
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+
+/* POST support */
+/* ethernet POST sometimes freezes the CPU.
+ * So disable it for now until issue is solved
+ */
+#if 0
+#define CONFIG_POST (CFG_POST_MEMORY | \
+ CFG_POST_CPU | \
+ CFG_POST_UART | \
+ CFG_POST_I2C | \
+ CFG_POST_CACHE | \
+ CFG_POST_FPU | \
+ CFG_POST_ETHER | \
+ CFG_POST_SPR)
+#else
+#define CONFIG_POST (CFG_POST_MEMORY | \
+ CFG_POST_CPU | \
+ CFG_POST_UART | \
+ CFG_POST_I2C | \
+ CFG_POST_CACHE | \
+ CFG_POST_FPU | \
+ CFG_POST_SPR)
+#endif
+
+#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
+
+/* esd expects pram at end of physical memory.
+ * So no logbuffer at the moment.
+ */
+#if 0
+#define CONFIG_LOGBUFFER
+#endif
+#define CFG_POST_CACHE_ADDR 0x10000000 /* free virtual address */
+
+#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
+
+#define CONFIG_SUPPORT_VFAT
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+#define CONFIG_AUTOBOOT_KEYED 1
+#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n"
+#undef CONFIG_AUTOBOOT_DELAY_STR
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *----------------------------------------------------------------------*/
+/* General PCI */
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
+#define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
+
+/* Board-specific PCI */
+#define CFG_PCI_TARGET_INIT
+#define CFG_PCI_MASTER_INIT
+
+/* PCI identification */
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
+#define CFG_PCI_SUBSYS_ID_NONMONARCH 0x0441 /* PCI Device ID: Non-Monarch */
+#define CFG_PCI_SUBSYS_ID_MONARCH 0x0440 /* PCI Device ID: Monarch */
+#define CFG_PCI_CLASSCODE_NONMONARCH PCI_CLASS_PROCESSOR_POWERPC
+#define CFG_PCI_CLASSCODE_MONARCH PCI_CLASS_BRIDGE_HOST
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ *----------------------------------------------------------------------*/
+#define CONFIG_FPGA
+#define CONFIG_FPGA_XILINX
+#define CONFIG_FPGA_SPARTAN2
+#define CONFIG_FPGA_SPARTAN3
+
+#define CONFIG_FPGA_COUNT 2
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+
+/*
+ * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
+ */
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#define CFG_NAND_CS 2 /* NAND chip connected to CSx */
+
+/* Memory Bank 0 (NOR-FLASH) initialization */
+#define CFG_EBC_PB0AP 0x03017200
+#define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0xda000)
+
+/* Memory Bank 2 (NAND-FLASH) initialization */
+#define CFG_EBC_PB2AP 0x018003c0
+#define CFG_EBC_PB2CR (CFG_NAND_ADDR | 0x1c000)
+#else
+#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
+/* Memory Bank 2 (NOR-FLASH) initialization */
+#define CFG_EBC_PB2AP 0x03017200
+#define CFG_EBC_PB2CR (CFG_FLASH_BASE | 0xda000)
+
+/* Memory Bank 0 (NAND-FLASH) initialization */
+#define CFG_EBC_PB0AP 0x018003c0
+#define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1c000)
+#endif
+
+/* Memory Bank 4 (FPGA / 32Bit) initialization */
+#define CFG_EBC_PB4AP 0x03840f40 /* BME=0,TWT=7,CSN=1,TH=7,RE=1,SOR=0,BEM=1 */
+#define CFG_EBC_PB4CR (CFG_FPGA_BASE0 | 0x1c000) /* BS=1M,BU=R/W,BW=32bit */
+
+/* Memory Bank 5 (FPGA / 16Bit) initialization */
+#define CFG_EBC_PB5AP 0x03840f40 /* BME=0,TWT=3,CSN=1,TH=0,RE=1,SOR=0,BEM=1 */
+#define CFG_EBC_PB5CR (CFG_FPGA_BASE1 | 0x1a000) /* BS=1M,BU=R/W,BW=16bit */
+
+/*-----------------------------------------------------------------------
+ * NAND FLASH
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_NAND_DEVICE 1
+#define NAND_MAX_CHIPS 1
+#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
+#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+#endif /* __CONFIG_H */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
- /* have only 8kB, 16kB is save here */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Init Memory Controller:
*
#else
#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
#endif /* CONFIG_TQM5200_B */
-#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
+#define CFG_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+/* use CFI flash driver */
+#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_USE_BUFFER_WRITE 1
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+/* use CFI flash driver */
+#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_USE_BUFFER_WRITE 1
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
-#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
+#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment */
#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+/* use CFI flash driver */
+#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_USE_BUFFER_WRITE 1
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+/* use CFI flash driver */
+#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_USE_BUFFER_WRITE 1
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
-#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
+#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment */
#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+/* use CFI flash driver */
+#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_USE_BUFFER_WRITE 1
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+/* use CFI flash driver */
+#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_USE_BUFFER_WRITE 1
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
-#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
+#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment */
#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+/* use CFI flash driver */
+#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_USE_BUFFER_WRITE 1
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+/* use CFI flash driver */
+#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_USE_BUFFER_WRITE 1
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
*/
#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
-#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
+#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB per bank */
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
#define CFG_OR_TIMING_SDRAM 0x00000A00
#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
+/* 10 column SDRAM */
+#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
+ MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \
+ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
/*
* Internal Definitions
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+/* use CFI flash driver */
+#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_USE_BUFFER_WRITE 1
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
#define CFG_ENV_IS_IN_FLASH 1
-
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+/* use CFI flash driver */
+#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_USE_BUFFER_WRITE 1
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CFG_ENV_IS_IN_FLASH 1
-
#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
-#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
+#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment */
#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+/* use CFI flash driver */
+#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_USE_BUFFER_WRITE 1
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */
#define CFG_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
#define CFG_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
-#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 50 MHz - CPU default clock */
+#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 66 MHz - CPU default clock */
/* (it will be used if there is no */
/* 'cpuclk' variable with valid value) */
-#define CFG_MEASURE_CPUCLK /* Measure real cpu clock */
- /* (function measure_gclk() */
- /* will be called) */
-#ifdef CFG_MEASURE_CPUCLK
-#define CFG_8XX_XIN 10000000 /* measure_gclk() needs this */
-#endif
-
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
- "bootfile=/tftpboot/TQM866M/uImage\0" \
- "kernel_addr=40080000\0" \
- "ramdisk_addr=40180000\0" \
+ "bootfile=/tftpboot/TQM885D/uImage\0" \
+ "fdt_addr=400C0000\0" \
+ "kernel_addr=40100000\0" \
+ "ramdisk_addr=40280000\0" \
+ "load=tftp 200000 ${u-boot}\0" \
+ "update=protect off 40000000 +${filesize};" \
+ "erase 40000000 +${filesize};" \
+ "cp.b 200000 40000000 ${filesize};" \
+ "protect on 40000000 +${filesize}\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
-#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */
+#undef CONFIG_RTC_MPC8xx /* MPC885 does not support RTC */
#define CONFIG_TIMESTAMP /* but print image timestmps */
#define CFG_FLASH_BASE 0x40000000
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_MONITOR_BASE CFG_FLASH_BASE
-#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#define CFG_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+/* use CFI flash driver */
+#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_USE_BUFFER_WRITE 1
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
-#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
-#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
+#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment */
+#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
/*
- * Memory Periodic Timer Prescaler
- * Periodic timer for refresh, start with refresh rate for 40 MHz clock
- * (CFG_8xx_CPUCLK_MIN / CFG_PTA_PER_CLK)
+ * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
+ *
+ * CPUclock(MHz) * 31.2
+ * CFG_MAMR_PTA = ----------------------------------- with DFBRG = 0
+ * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
+ *
+ * CPU clock = 15 MHz: CFG_MAMR_PTA = 29 -> 4 * 7.73 us
+ * CPU clock = 50 MHz: CFG_MAMR_PTA = 97 -> 4 * 7.76 us
+ * CPU clock = 66 MHz: CFG_MAMR_PTA = 128 -> 4 * 7.75 us
+ * CPU clock = 133 MHz: CFG_MAMR_PTA = 255 -> 4 * 7.67 us
+ *
+ * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
+ * be met also in the default configuration, i.e. if environment variable
+ * 'cpuclk' is not set.
*/
-#define CFG_MAMR_PTA 39
+#define CFG_MAMR_PTA 128
/*
- * For 16 MBit, refresh rates could be 31.3 us
- * (= 64 ms / 2K = 125 / quad bursts).
- * For a simpler initialization, 15.6 us is used instead.
- *
- * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
- * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
+ * Memory Periodic Timer Prescaler Register (MPTPR) values.
*/
-#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
-#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
-#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
+/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
+#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16
+/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
+#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8
/*
* MAMR settings for SDRAM
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+#define CONFIG_NET_MULTI 1
+#undef CONFIG_HAS_ETH1
+
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */
#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
-#define CONFIG_ATAPI 1 /* ATAPI for Travelstar */
-
#define CFG_ATA_BASE_ADDR 0xF0100000
#define CFG_ATA_IDE0_OFFSET 0x0000
#define CFG_ATA_IDE1_OFFSET 0x0010
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#if 0 /* test-only */
-#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
-#endif
-
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* I2C EEPROM (CAT24WC16) for environment
*/
#define CONFIG_HARD_I2C /* I2c with hardware support */
-#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
-#if 0 /* test-only */
-/* CAT24WC08/16... */
-#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
- /* 16 byte page write mode using*/
- /* last 4 bits of the address */
-#else
+#define CFG_EEPROM_WREN 1
+
/* CAT24WC32/64... */
#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
/* mask of address bits that overflow into the "EEPROM chip address" */
#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
/* 32 byte page write mode using*/
/* last 5 bits of the address */
-#endif
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
- /* have only 8kB, 16kB is save here */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*/
* GPIO0[28-29] - UART1 data signal input/output
* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs -> GPIO
*/
-#define CFG_GPIO0_OSRH 0x40000550
+#define CFG_GPIO0_OSRH 0x00000550
#define CFG_GPIO0_OSRL 0x00000110
#define CFG_GPIO0_ISR1H 0x00000000
#define CFG_GPIO0_ISR1L 0x15555440
#define CFG_GPIO0_TSRH 0x00000000
#define CFG_GPIO0_TSRL 0x00000000
-#define CFG_GPIO0_TCR 0xF7FE0017
+#define CFG_GPIO0_TCR 0x777E0017
#define CFG_DUART_RST (0x80000000 >> 14)
#define CFG_LCD_ENDIAN (0x80000000 >> 7)
+#define CFG_IIC_ON (0x80000000 >> 8)
#define CFG_LCD0_RST (0x80000000 >> 30)
#define CFG_LCD1_RST (0x80000000 >> 31)
+#define CFG_EEPROM_WP (0x80000000 >> 0)
/*
* Internal Definitions
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
- /* have only 8kB, 16kB is save here */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*/
*/
#define SPD_EEPROM_ADDRESS 0x50 /* XXX conflicting address!!! XXX */
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above val. */
-#endif
-
/*
* Init Memory Controller:
*/
*/
#define SPD_EEPROM_ADDRESS 0x50 /* XXX conflicting address!!! XXX */
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above val. */
-#endif
-
/*
* Init Memory Controller:
*/
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
- /* have only 8kB, 16kB is save here */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Init Memory Controller:
*
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 8192 /* For AMCC 440GX CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
/*
* Internal Definitions
#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 16384 /* For AMCC 405EZ CPU */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/
-#endif
-
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*----------------------------------------------------------------------*/
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
/*
* Internal Definitions
--- /dev/null
+/*
+ * Copyright (C) 2007 Atmel Corporation
+ *
+ * Configuration settings for the ATSTK1003 CPU daughterboard
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_AVR32 1
+#define CONFIG_AT32AP 1
+#define CONFIG_AT32AP7001 1
+#define CONFIG_ATSTK1003 1
+#define CONFIG_ATSTK1000 1
+
+#define CONFIG_ATSTK1000_EXT_FLASH 1
+
+/*
+ * Timer clock frequency. We're using the CPU-internal COUNT register
+ * for this, so this is equivalent to the CPU core clock frequency
+ */
+#define CFG_HZ 1000
+
+/*
+ * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
+ * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
+ * PLL frequency.
+ * (CFG_OSC0_HZ * CFG_PLL0_MUL) / CFG_PLL0_DIV = PLL MHz
+ */
+#define CONFIG_PLL 1
+#define CFG_POWER_MANAGER 1
+#define CFG_OSC0_HZ 20000000
+#define CFG_PLL0_DIV 1
+#define CFG_PLL0_MUL 7
+#define CFG_PLL0_SUPPRESS_CYCLES 16
+/*
+ * Set the CPU running at:
+ * PLL / (2^CFG_CLKDIV_CPU) = CPU MHz
+ */
+#define CFG_CLKDIV_CPU 0
+/*
+ * Set the HSB running at:
+ * PLL / (2^CFG_CLKDIV_HSB) = HSB MHz
+ */
+#define CFG_CLKDIV_HSB 1
+/*
+ * Set the PBA running at:
+ * PLL / (2^CFG_CLKDIV_PBA) = PBA MHz
+ */
+#define CFG_CLKDIV_PBA 2
+/*
+ * Set the PBB running at:
+ * PLL / (2^CFG_CLKDIV_PBB) = PBB MHz
+ */
+#define CFG_CLKDIV_PBB 1
+
+/*
+ * The PLLOPT register controls the PLL like this:
+ * icp = PLLOPT<2>
+ * ivco = PLLOPT<1:0>
+ *
+ * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
+ */
+#define CFG_PLL0_OPT 0x04
+
+#undef CONFIG_USART0
+#define CONFIG_USART1 1
+#undef CONFIG_USART2
+#undef CONFIG_USART3
+
+/* User serviceable stuff */
+#define CONFIG_DOS_PARTITION 1
+
+#define CONFIG_CMDLINE_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+#define CONFIG_STACKSIZE (2048)
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_BOOTARGS \
+ "console=ttyS0 root=/dev/mmcblk0p1 rootwait"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmcinit; ext2load mmc 0:1 0x10400000 /boot/uImage; bootm"
+
+/*
+ * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
+ * data on the serial line may interrupt the boot sequence.
+ */
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_AUTOBOOT 1
+#define CONFIG_AUTOBOOT_KEYED 1
+#define CONFIG_AUTOBOOT_PROMPT \
+ "Press SPACE to abort autoboot in %d seconds\n"
+#define CONFIG_AUTOBOOT_DELAY_STR "d"
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MMC
+
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
+#define CONFIG_ATMEL_USART 1
+#define CONFIG_PIO2 1
+#define CFG_HSDRAMC 1
+#define CONFIG_MMC 1
+
+#define CFG_DCACHE_LINESZ 32
+#define CFG_ICACHE_LINESZ 32
+
+#define CONFIG_NR_DRAM_BANKS 1
+
+/* External flash on STK1000 */
+#if 0
+#define CFG_FLASH_CFI 1
+#define CFG_FLASH_CFI_DRIVER 1
+#endif
+
+#define CFG_FLASH_BASE 0x00000000
+#define CFG_FLASH_SIZE 0x800000
+#define CFG_MAX_FLASH_BANKS 1
+#define CFG_MAX_FLASH_SECT 135
+
+#define CFG_MONITOR_BASE CFG_FLASH_BASE
+
+#define CFG_INTRAM_BASE 0x24000000
+#define CFG_INTRAM_SIZE 0x8000
+
+#define CFG_SDRAM_BASE 0x10000000
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_SIZE 65536
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE)
+
+#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
+
+#define CFG_MALLOC_LEN (256*1024)
+
+/* Allow 4MB for the kernel run-time image */
+#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00400000)
+#define CFG_BOOTPARAMS_LEN (16 * 1024)
+
+/* Other configuration settings that shouldn't have to change all that often */
+#define CFG_PROMPT "Uboot> "
+#define CFG_CBSIZE 256
+#define CFG_MAXARGS 16
+#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CFG_LONGHELP 1
+
+#define CFG_MEMTEST_START CFG_SDRAM_BASE
+#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x700000)
+#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Copyright (C) 2007 Atmel Corporation
+ *
+ * Configuration settings for the ATSTK1003 CPU daughterboard
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_AVR32 1
+#define CONFIG_AT32AP 1
+#define CONFIG_AT32AP7002 1
+#define CONFIG_ATSTK1004 1
+#define CONFIG_ATSTK1000 1
+
+#define CONFIG_ATSTK1000_EXT_FLASH 1
+
+/*
+ * Timer clock frequency. We're using the CPU-internal COUNT register
+ * for this, so this is equivalent to the CPU core clock frequency
+ */
+#define CFG_HZ 1000
+
+/*
+ * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
+ * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
+ * PLL frequency.
+ * (CFG_OSC0_HZ * CFG_PLL0_MUL) / CFG_PLL0_DIV = PLL MHz
+ */
+#define CONFIG_PLL 1
+#define CFG_POWER_MANAGER 1
+#define CFG_OSC0_HZ 20000000
+#define CFG_PLL0_DIV 1
+#define CFG_PLL0_MUL 7
+#define CFG_PLL0_SUPPRESS_CYCLES 16
+/*
+ * Set the CPU running at:
+ * PLL / (2^CFG_CLKDIV_CPU) = CPU MHz
+ */
+#define CFG_CLKDIV_CPU 0
+/*
+ * Set the HSB running at:
+ * PLL / (2^CFG_CLKDIV_HSB) = HSB MHz
+ */
+#define CFG_CLKDIV_HSB 1
+/*
+ * Set the PBA running at:
+ * PLL / (2^CFG_CLKDIV_PBA) = PBA MHz
+ */
+#define CFG_CLKDIV_PBA 2
+/*
+ * Set the PBB running at:
+ * PLL / (2^CFG_CLKDIV_PBB) = PBB MHz
+ */
+#define CFG_CLKDIV_PBB 1
+
+/*
+ * The PLLOPT register controls the PLL like this:
+ * icp = PLLOPT<2>
+ * ivco = PLLOPT<1:0>
+ *
+ * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
+ */
+#define CFG_PLL0_OPT 0x04
+
+#undef CONFIG_USART0
+#define CONFIG_USART1 1
+#undef CONFIG_USART2
+#undef CONFIG_USART3
+
+/* User serviceable stuff */
+#define CONFIG_DOS_PARTITION 1
+
+#define CONFIG_CMDLINE_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+#define CONFIG_STACKSIZE (2048)
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_BOOTARGS \
+ "console=ttyS0 root=/dev/mmcblk0p1 rootwait"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmcinit; ext2load mmc 0:1 0x10200000 /boot/uImage; bootm"
+
+/*
+ * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
+ * data on the serial line may interrupt the boot sequence.
+ */
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_AUTOBOOT 1
+#define CONFIG_AUTOBOOT_KEYED 1
+#define CONFIG_AUTOBOOT_PROMPT \
+ "Press SPACE to abort autoboot in %d seconds\n"
+#define CONFIG_AUTOBOOT_DELAY_STR "d"
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MMC
+
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
+#define CONFIG_ATMEL_USART 1
+#define CONFIG_PIO2 1
+#define CFG_HSDRAMC 1
+#define CONFIG_MMC 1
+
+#define CFG_DCACHE_LINESZ 32
+#define CFG_ICACHE_LINESZ 32
+
+#define CONFIG_NR_DRAM_BANKS 1
+
+/* External flash on STK1000 */
+#if 0
+#define CFG_FLASH_CFI 1
+#define CFG_FLASH_CFI_DRIVER 1
+#endif
+
+#define CFG_FLASH_BASE 0x00000000
+#define CFG_FLASH_SIZE 0x800000
+#define CFG_MAX_FLASH_BANKS 1
+#define CFG_MAX_FLASH_SECT 135
+
+#define CFG_MONITOR_BASE CFG_FLASH_BASE
+
+#define CFG_INTRAM_BASE 0x24000000
+#define CFG_INTRAM_SIZE 0x8000
+
+#define CFG_SDRAM_BASE 0x10000000
+#define CFG_SDRAM_16BIT 1
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_SIZE 65536
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE)
+
+#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
+
+#define CFG_MALLOC_LEN (256*1024)
+
+/* Allow 4MB for the kernel run-time image */
+#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00200000)
+#define CFG_BOOTPARAMS_LEN (16 * 1024)
+
+/* Other configuration settings that shouldn't have to change all that often */
+#define CFG_PROMPT "Uboot> "
+#define CFG_CBSIZE 256
+#define CFG_MAXARGS 16
+#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CFG_LONGHELP 1
+
+#define CFG_MEMTEST_START CFG_SDRAM_BASE
+#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x700000)
+#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
+
+#endif /* __CONFIG_H */
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Internal Definitions
*
#define CFG_ENV_ADDR \
(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */
#endif
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 16384 /* For AMCC 405EP CPU */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
/*
* Init Memory Controller:
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-/*
- * Cache configuration
- *
- */
-#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
- /* have only 8kB, 16kB is save here */
-#define CFG_CACHELINE_SIZE 32
-
/*
* Miscellaneous board specific definitions
*
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-/*
- * Cache configuration
- *
- */
-#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
- /* have only 8kB, 16kB is save here */
-#define CFG_CACHELINE_SIZE 32
-
/*
* Miscellaneous board specific definitions
*
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
/*
* Internal Definitions
#define CONFIG_PORT_ADDR 0xF0000500
-/*-----------------------------------------------------------------------
- * Cache Configuration
- *----------------------------------------------------------------------*/
-#define CFG_DCACHE_SIZE 16384 /* For IBM 405GPr CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-
/*
* Internal Definitions
*
#define HCU_CPLD_VERSION_REGISTER ( CFG_CPLD + 0x0F00000 )
#define HCU_HW_VERSION_REGISTER ( CFG_CPLD + 0x1400000 )
-/*-----------------------------------------------------------------------
- * Cache Configuration
- *----------------------------------------------------------------------*/
-#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-
/*
* Internal Definitions
*
#define CFG_PCI_TARGBASE CFG_PCI_MEMBASE
#define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
-#define CFG_PCIE_MEMSIZE 0x01000000
+#define CFG_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */
#define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
#define CFG_PCIE0_CFGBASE 0xc0000000
#define CFG_PCIE1_XCFGBASE 0xc3001000
#define CFG_PCIE2_XCFGBASE 0xc3002000
+/* base address of inbound PCIe window */
+#define CFG_PCIE_INBOUND_BASE 0x0000000000000000ULL
+
/* System RAM mapped to PCI space */
#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
- "rootpath=/opt/eldk/ppc_4xx\0" \
+ "net_nfs_fdt=tftp 200000 ${bootfile};" \
+ "tftp ${fdt_addr} ${fdt_file};" \
+ "run nfsargs addip addtty;" \
+ "bootm 200000 - ${fdt_addr}\0" \
+ "rootpath=/opt/eldk/ppc_4xx\0" \
"bootfile=katmai/uImage\0" \
+ "fdt_file=katmai/katmai.dtb\0" \
+ "fdt_addr=400000\0" \
"kernel_addr=fff10000\0" \
"ramdisk_addr=fff20000\0" \
"initrd_high=30000000\0" \
"upd=run load;run update\0" \
"kozio=bootm ffc60000\0" \
"pciconfighost=1\0" \
+ "pcie_mode=RP:RP:RP\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SDRAM
-
+#define CONFIG_CMD_SNTP
#define CONFIG_IBM_EMAC4_V4 1 /* 440SPe has this EMAC version */
#define CONFIG_MII 1 /* MII PHY management */
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /*Initial Memory map for Linux*/
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
/*
* Internal Definitions
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * kilauea.h - configuration for AMCC Kilauea (405EX)
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_KILAUEA 1 /* Board is Kilauea */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_405EX 1 /* Specifc 405EX support*/
+#define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+#define CONFIG_BOARD_EMAC_COUNT
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0xFC000000
+#define CFG_NAND_ADDR 0xF8000000
+#define CFG_FPGA_BASE 0xF0000000
+#define CFG_PERIPHERAL_BASE 0xEF600000 /* internal peripherals*/
+#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
+#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc() */
+#define CFG_MONITOR_BASE (TEXT_BASE)
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer
+ *----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_ADDR 0x02000000 /* inside of SDRAM */
+#define CFG_INIT_RAM_END (4 << 10)
+#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+/* reserve some memory for POST and BOOT limit info */
+#define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - 16)
+
+/* extra data in init-ram */
+#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4)
+#define CFG_POST_MAGIC (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 8)
+#define CFG_POST_VAL (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 12)
+#define CFG_OCM_DATA_ADDR CFG_INIT_RAM_ADDR /* for commproc.c */
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SERIAL_MULTI 1
+/* define this if you want console on UART1 */
+#undef CONFIG_UART1_CONSOLE
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+#else
+#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
+#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */
+#endif
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_CFI /* The flash is CFI compatible */
+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+
+#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+/*
+ * IPL (Initial Program Loader, integrated inside CPU)
+ * Will load first 4k from NAND (SPL) into cache and execute it from there.
+ *
+ * SPL (Secondary Program Loader)
+ * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
+ * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
+ * controller and the NAND controller so that the special U-Boot image can be
+ * loaded from NAND to SDRAM.
+ *
+ * NUB (NAND U-Boot)
+ * This NAND U-Boot (NUB) is a special U-Boot version which can be started
+ * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
+ *
+ * On 440EPx the SPL is copied to SDRAM before the NAND controller is
+ * set up. While still running from cache, I experienced problems accessing
+ * the NAND controller. sr - 2006-08-25
+ */
+#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
+#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
+#define CFG_NAND_BOOT_SPL_DST 0x00800000 /* Copy SPL here */
+#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
+#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
+#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
+
+/*
+ * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
+ */
+#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
+#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
+
+/*
+ * Now the NAND chip has to be defined (no autodetection used!)
+ */
+#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */
+#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
+#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */
+#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
+#define CFG_NAND_4_ADDR_CYCLE 1 /* Fourth addr used (>32MB) */
+
+#define CFG_NAND_ECCSIZE 256
+#define CFG_NAND_ECCBYTES 3
+#define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
+#define CFG_NAND_OOBSIZE 16
+#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
+#define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
+
+#ifdef CFG_ENV_IS_IN_NAND
+/*
+ * For NAND booting the environment is embedded in the U-Boot image. Please take
+ * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
+ */
+#define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE
+#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE)
+#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE)
+#endif
+
+/*-----------------------------------------------------------------------
+ * NAND FLASH
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_NAND_DEVICE 1
+#define NAND_MAX_CHIPS 1
+#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
+#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CFG_MBYTES_SDRAM (256) /* 256MB */
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
+#define CFG_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */
+#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
+
+/* Standard DTT sensor configuration */
+#define CONFIG_DTT_DS1775 1
+#define CONFIG_DTT_SENSORS { 0 }
+#define CFG_I2C_DTT_ADDR 0x48
+
+/* RTC configuration */
+#define CONFIG_RTC_DS1338 1
+#define CFG_I2C_RTC_ADDR 0x68
+
+/*-----------------------------------------------------------------------
+ * Ethernet
+ *----------------------------------------------------------------------*/
+#define CONFIG_M88E1111_PHY 1
+#define CONFIG_IBM_EMAC4_V4 1
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
+
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+
+#define CONFIG_HAS_ETH0 1
+
+#define CONFIG_NET_MULTI 1
+#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
+#define CONFIG_PHY1_ADDR 2
+
+#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "logversion=2\0" \
+ "netdev=eth0\0" \
+ "hostname=kilauea\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "net_nfs=tftp 200000 ${bootfile};" \
+ "run nfsargs addip addtty;" \
+ "bootm 200000\0" \
+ "net_nfs_fdt=tftp 200000 ${bootfile};" \
+ "tftp ${fdt_addr} ${fdt_file};" \
+ "run nfsargs addip addtty;" \
+ "bootm 200000 - ${fdt_addr}\0" \
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "rootpath=/opt/eldk/ppc_4xx\0" \
+ "bootfile=kilauea/uImage\0" \
+ "fdt_file=kilauea/kilauea.dtb\0" \
+ "fdt_addr=400000\0" \
+ "kernel_addr=fc000000\0" \
+ "ramdisk_addr=fc200000\0" \
+ "initrd_high=30000000\0" \
+ "load=tftp 200000 kilauea/u-boot.bin\0" \
+ "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \
+ "cp.b ${fileaddr} fffa0000 ${filesize};" \
+ "setenv filesize;saveenv\0" \
+ "upd=run load update\0" \
+ "nload=tftp 200000 kilauea/u-boot-nand.bin\0" \
+ "nupdate=nand erase 0 60000;nand write 200000 0 60000;" \
+ "setenv filesize;saveenv\0" \
+ "nupd=run nload nupdate\0" \
+ "pciconfighost=1\0" \
+ "pcie_mode=RP:RP\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_LOG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SNTP
+
+/* POST support */
+#define CONFIG_POST (CFG_POST_MEMORY | \
+ CFG_POST_CACHE | \
+ CFG_POST_CPU | \
+ CFG_POST_ETHER | \
+ CFG_POST_I2C | \
+ CFG_POST_MEMORY | \
+ CFG_POST_UART)
+
+/* Define here the base-addresses of the UARTs to test in POST */
+#define CFG_POST_UART_TABLE {UART0_BASE, UART1_BASE}
+
+#define CONFIG_LOGBUFFER
+#define CFG_POST_CACHE_ADDR 0x00800000 /* free virtual address */
+
+#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *----------------------------------------------------------------------*/
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE
+
+/*-----------------------------------------------------------------------
+ * PCIe stuff
+ *----------------------------------------------------------------------*/
+#define CFG_PCIE_MEMBASE 0x90000000 /* mapped PCIe memory */
+#define CFG_PCIE_MEMSIZE 0x08000000 /* 128 Meg, smallest incr per port */
+
+#define CFG_PCIE0_CFGBASE 0xa0000000 /* remote access */
+#define CFG_PCIE0_XCFGBASE 0xb0000000 /* local access */
+#define CFG_PCIE0_CFGMASK 0xe0000001 /* 512 Meg */
+
+#define CFG_PCIE1_CFGBASE 0xc0000000 /* remote access */
+#define CFG_PCIE1_XCFGBASE 0xd0000000 /* local access */
+#define CFG_PCIE1_CFGMASK 0xe0000001 /* 512 Meg */
+
+#define CFG_PCIE0_UTLBASE 0xef502000
+#define CFG_PCIE1_UTLBASE 0xef503000
+
+/* base address of inbound PCIe window */
+#define CFG_PCIE_INBOUND_BASE 0x0000000000000000ULL
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+/* booting from NAND, so NAND chips select has to be on CS 0 */
+#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
+
+/* Memory Bank 1 (NOR-FLASH) initialization */
+#define CFG_EBC_PB1AP 0x05806500
+#define CFG_EBC_PB1CR 0xFC0DA000 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
+
+/* Memory Bank 0 (NAND-FLASH) initialization */
+#define CFG_EBC_PB0AP 0x018003c0
+#define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1e000)
+#else
+#define CFG_NAND_CS 1 /* NAND chip connected to CSx */
+
+/* Memory Bank 0 (NOR-FLASH) initialization */
+#define CFG_EBC_PB0AP 0x05806500
+#define CFG_EBC_PB0CR 0xFC0DA000 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
+
+/* Memory Bank 1 (NAND-FLASH) initialization */
+#define CFG_EBC_PB1AP 0x018003c0
+#define CFG_EBC_PB1CR (CFG_NAND_ADDR | 0x1e000)
+#endif
+
+/* Memory Bank 2 (FPGA) initialization */
+#define CFG_EBC_PB2AP 0x9400C800
+#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0x800,BS=1MB,BU=R/W,BW=8bit */
+
+#define CFG_EBC_CFG 0x7FC00000 /* EBC0_CFG */
+
+/*-----------------------------------------------------------------------
+ * GPIO Setup
+ *----------------------------------------------------------------------*/
+#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
+{ \
+/* GPIO Core 0 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO0 EBC_DATA_PAR(0) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO1 EBC_DATA_PAR(1) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO2 EBC_DATA_PAR(2) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO3 EBC_DATA_PAR(3) */ \
+{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO4 EBC_DATA(20) USB2_DATA(4) */ \
+{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 EBC_DATA(21) USB2_DATA(5) */ \
+{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 EBC_DATA(22) USB2_DATA(6) */ \
+{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 EBC_DATA(23) USB2_DATA(7) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 CS(1)/NFCE(1) IRQ(7) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 CS(2)/NFCE(2) IRQ(8) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3) IRQ(9) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 IRQ(6) */ \
+{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16) USB2_DATA(0) */ \
+{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17) USB2_DATA(1) */ \
+{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 EBC_DATA(18) USB2_DATA(2) */ \
+{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 EBC_DATA(19) USB2_DATA(3) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD UART1_CTS */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR UART1_RTS */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO20 UART0_DTR UART1_TX */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0}, /* GPIO21 UART0_RI UART1_RX */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ DMA_ACK2 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK DMA_REQ2 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ DMA_EOT2 IRQ(4) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK DMA_ACK3 IRQ(3) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5) DMA_EOT0 TS(3) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ DMA_EOT3 IRQ(5) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO28 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0}, /* GPIO29 DMA_EOT1 IRQ(2) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO30 DMA_REQ1 IRQ(1) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO31 DMA_ACK1 IRQ(0) */ \
+} \
+}
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Some Kilauea stuff..., mainly fpga registers
+ */
+#define CFG_FPGA_REG_BASE CFG_FPGA_BASE
+#define CFG_FPGA_FIFO_BASE (in32(CFG_FPGA_BASE) | (1 << 11))
+
+/* interrupt */
+#define CFG_FPGA_SLIC0_R_DPRAM_INT 0x80000000
+#define CFG_FPGA_SLIC0_W_DPRAM_INT 0x40000000
+#define CFG_FPGA_SLIC1_R_DPRAM_INT 0x20000000
+#define CFG_FPGA_SLIC1_W_DPRAM_INT 0x10000000
+#define CFG_FPGA_PHY0_INT 0x08000000
+#define CFG_FPGA_PHY1_INT 0x04000000
+#define CFG_FPGA_SLIC0_INT 0x02000000
+#define CFG_FPGA_SLIC1_INT 0x01000000
+
+/* DPRAM setting */
+/* 00: 32B; 01: 64B; 10: 128B; 11: 256B */
+#define CFG_FPGA_DPRAM_R_INT_LINE 0x00400000 /* 64 B */
+#define CFG_FPGA_DPRAM_W_INT_LINE 0x00100000 /* 64 B */
+#define CFG_FPGA_DPRAM_RW_TYPE 0x00080000
+#define CFG_FPGA_DPRAM_RST 0x00040000
+#define CFG_FPGA_UART0_FO 0x00020000
+#define CFG_FPGA_UART1_FO 0x00010000
+
+/* loopback */
+#define CFG_FPGA_CHIPSIDE_LOOPBACK 0x00004000
+#define CFG_FPGA_LINESIDE_LOOPBACK 0x00008000
+#define CFG_FPGA_SLIC0_ENABLE 0x00002000
+#define CFG_FPGA_SLIC1_ENABLE 0x00001000
+#define CFG_FPGA_SLIC0_CS 0x00000800
+#define CFG_FPGA_SLIC1_CS 0x00000400
+#define CFG_FPGA_USER_LED0 0x00000200
+#define CFG_FPGA_USER_LED1 0x00000100
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Larry Johnson, lrj@acm.org
+ *
+ * (C) Copyright 2006-2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2006
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * korat.h - configuration for Korat board
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_440EPX 1 /* Specific PPC440EPx */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_SYS_CLK_FREQ 33333333
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+
+/*-----------------------------------------------------------------------
+ * Manufacturer's information serial EEPROM parameters
+ *----------------------------------------------------------------------*/
+#define MAN_DATA_EEPROM_ADDR 0x53 /* EEPROM I2C address */
+#define MAN_SERIAL_NO_FIELD 2
+#define MAN_SERIAL_NO_LENGTH 13
+#define MAN_MAC_ADDR_FIELD 3
+#define MAN_MAC_ADDR_LENGTH 17
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
+#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
+
+#define CFG_BOOT_BASE_ADDR 0xf0000000
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_OCM_BASE 0xe0010000 /* ocm */
+#define CFG_OCM_DATA_ADDR CFG_OCM_BASE
+#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
+#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
+#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
+#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
+#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
+
+/* Don't change either of these */
+#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
+
+#define CFG_USB2D0_BASE 0xe0000100
+#define CFG_USB_DEVICE 0xe0000000
+#define CFG_USB_HOST 0xe0000400
+#define CFG_CPLD_BASE 0xc0000000
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer
+ *----------------------------------------------------------------------*/
+/* 440EPx has 16KB of internal SRAM, so no need for D-Cache */
+#undef CFG_INIT_RAM_DCACHE
+#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
+#define CFG_INIT_RAM_END (4 << 10)
+#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SERIAL_MULTI 1
+/* define this if you want console on UART1 */
+#undef CONFIG_UART1_CONSOLE
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environ vars */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_CFI /* The flash is CFI compatible */
+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
+
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
+
+#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CFG_MBYTES_SDRAM (512) /* 512 MiB TODO: remove */
+#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
+#define CONFIG_ZERO_SDRAM /* Zero SDRAM after setup */
+#define CONFIG_DDR_ECC /* Use ECC when available */
+#define SPD_EEPROM_ADDRESS {0x50}
+#define CONFIG_PROG_SDRAM_TLB
+#define CFG_DRAM_TEST
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+#define CFG_I2C_MULTI_EEPROMS
+#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/* I2C RTC */
+#define CONFIG_RTC_M41T60 1
+#define CFG_I2C_RTC_ADDR 0x68
+
+/* I2C SYSMON (LM73) */
+#define CONFIG_DTT_LM73 1 /* National Semi's LM73 */
+#define CONFIG_DTT_SENSORS {2} /* Sensor addresses */
+#define CFG_DTT_MAX_TEMP 70
+#define CFG_DTT_MIN_TEMP -30
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+/* Setup some board specific values for the default environment variables */
+#define CONFIG_HOSTNAME korat
+#define CFG_BOOTFILE "bootfile=/tftpboot/korat/uImage\0"
+#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CFG_BOOTFILE \
+ CFG_ROOTPATH \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
+ "bootm\0" \
+ "kernel_addr=FC000000\0" \
+ "ramdisk_addr=FC180000\0" \
+ "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
+ "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
+ "cp.b 200000 FFFA0000 60000\0" \
+ "upd=run load;run update\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_IBM_EMAC4_V4 1
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 2 /* PHY address, See schematics */
+#define CONFIG_PHY_DYNAMIC_ANEG 1
+
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+
+#define CONFIG_HAS_ETH0
+#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NET_MULTI 1
+#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
+#define CONFIG_PHY1_ADDR 3
+
+/* USB */
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+
+/* Comment this out to enable USB 1.1 device */
+#define USB_2_0_DEVICE
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_SUBNETMASK
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_USB
+
+/* POST support */
+#define CONFIG_POST (CFG_POST_CACHE | \
+ CFG_POST_CPU | \
+ CFG_POST_ECC | \
+ CFG_POST_ETHER | \
+ CFG_POST_FPU | \
+ CFG_POST_I2C | \
+ CFG_POST_MEMORY | \
+ CFG_POST_RTC | \
+ CFG_POST_SPR | \
+ CFG_POST_UART)
+
+#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
+#define CONFIG_LOGBUFFER
+#define CFG_POST_CACHE_ADDR 0xC8000000 /* free virtual address */
+
+#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
+
+#define CONFIG_SUPPORT_VFAT
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *----------------------------------------------------------------------*/
+/* General PCI */
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
+
+/* Board-specific PCI */
+#define CFG_PCI_TARGET_INIT
+#define CFG_PCI_MASTER_INIT
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
+#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+
+/* Memory Bank 0 (NOR-FLASH) initialization */
+#define CFG_EBC_PB0AP 0x04017300
+#define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0x000DA000)
+
+/* Memory Bank 1 (NOR-FLASH) initialization */
+#define CFG_EBC_PB1AP 0x04017300
+#define CFG_EBC_PB1CR (0xF8000000 | 0x000DA000)
+
+/* Memory Bank 2 (CPLD) initialization */
+#define CFG_EBC_PB2AP 0x04017300
+#define CFG_EBC_PB2CR (CFG_CPLD_BASE | 0x00038000)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+#endif /* __CONFIG_H */
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Internal Definitions
*
CFG_POST_SPR | \
CFG_POST_UART)
-#define CFG_POST_CACHE_ADDR 0x10000000 /* free virtual address */
+#define CFG_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
#define CONFIG_LOGBUFFER
#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
/*-----------------------------------------------------------------------
* PPC440 GPIO Configuration
*/
-#define CFG_440_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
+#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
{ \
/* GPIO Core 0 */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
} \
}
-/*-----------------------------------------------------------------------
- * Cache Configuration
- *----------------------------------------------------------------------*/
-#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Internal Definitions
*
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * makalu.h - configuration for AMCC Makalu (405EX)
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_MAKALU 1 /* Board is Makalu */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_405EX 1 /* Specifc 405EX support*/
+#define CONFIG_SYS_CLK_FREQ 33330000 /* ext frequency to pll */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0xFC000000
+#define CFG_FPGA_BASE 0xF0000000
+#define CFG_PERIPHERAL_BASE 0xEF600000 /* internal peripherals*/
+#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
+#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc() */
+#define CFG_MONITOR_BASE (TEXT_BASE)
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer
+ *----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_ADDR 0x02000000 /* inside of SDRAM */
+#define CFG_INIT_RAM_END (4 << 10)
+#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+/* reserve some memory for POST and BOOT limit info */
+#define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - 16)
+
+/* extra data in init-ram */
+#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4)
+#define CFG_POST_MAGIC (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 8)
+#define CFG_POST_VAL (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 12)
+#define CFG_OCM_DATA_ADDR CFG_INIT_RAM_ADDR /* for commproc.c */
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef CFG_EXT_SERIAL_CLOCK /* no ext. clk */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SERIAL_MULTI 1
+/* define this if you want console on UART1 */
+#undef CONFIG_UART1_CONSOLE
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_CFI /* The flash is CFI compatible */
+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+
+#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CFG_MBYTES_SDRAM 256
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
+#define CFG_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */
+#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
+
+/* Standard DTT sensor configuration */
+#define CONFIG_DTT_DS1775 1
+#define CONFIG_DTT_SENSORS { 0 }
+#define CFG_I2C_DTT_ADDR 0x48
+
+/* RTC configuration */
+#define CONFIG_RTC_X1205 1
+#define CFG_I2C_RTC_ADDR 0x6f
+
+/*-----------------------------------------------------------------------
+ * Ethernet
+ *----------------------------------------------------------------------*/
+#define CONFIG_M88E1111_PHY 1
+#define CONFIG_IBM_EMAC4_V4 1
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 6 /* PHY address, See schematics */
+
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+
+#define CONFIG_HAS_ETH0 1
+
+#define CONFIG_NET_MULTI 1
+#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
+#define CONFIG_PHY1_ADDR 0
+
+#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "logversion=2\0" \
+ "netdev=eth0\0" \
+ "hostname=makalu\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "addmisc=setenv bootargs ${bootargs} rtc-x1205.probe=0,0x6f\0" \
+ "net_nfs=tftp 200000 ${bootfile};" \
+ "run nfsargs addip addtty addmisc;" \
+ "bootm 200000\0" \
+ "net_nfs_fdt=tftp 200000 ${bootfile};" \
+ "tftp ${fdt_addr} ${fdt_file};" \
+ "run nfsargs addip addtty addmisc;" \
+ "bootm 200000 - ${fdt_addr}\0" \
+ "flash_nfs=run nfsargs addip addtty addmisc;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip addtty addmisc;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "rootpath=/opt/eldk/ppc_4xx\0" \
+ "bootfile=makalu/uImage\0" \
+ "fdt_file=makalu/makalu.dtb\0" \
+ "fdt_addr=400000\0" \
+ "kernel_addr=fc000000\0" \
+ "ramdisk_addr=fc200000\0" \
+ "initrd_high=30000000\0" \
+ "load=tftp 200000 makalu/u-boot.bin\0" \
+ "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \
+ "cp.b ${fileaddr} fffa0000 ${filesize};" \
+ "setenv filesize;saveenv\0" \
+ "upd=run load update\0" \
+ "pciconfighost=1\0" \
+ "pcie_mode=RP:RP\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_LOG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SNTP
+
+/* POST support */
+#define CONFIG_POST (CFG_POST_MEMORY | \
+ CFG_POST_CACHE | \
+ CFG_POST_CPU | \
+ CFG_POST_ETHER | \
+ CFG_POST_I2C | \
+ CFG_POST_MEMORY | \
+ CFG_POST_UART)
+
+/* Define here the base-addresses of the UARTs to test in POST */
+#define CFG_POST_UART_TABLE {UART0_BASE, UART1_BASE}
+
+#define CONFIG_LOGBUFFER
+#define CFG_POST_CACHE_ADDR 0x00800000 /* free virtual address */
+
+#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *----------------------------------------------------------------------*/
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE
+
+/*-----------------------------------------------------------------------
+ * PCIe stuff
+ *----------------------------------------------------------------------*/
+#define CFG_PCIE_MEMBASE 0x90000000 /* mapped PCIe memory */
+#define CFG_PCIE_MEMSIZE 0x08000000 /* 128 Meg, smallest incr per port */
+
+#define CFG_PCIE0_CFGBASE 0xa0000000 /* remote access */
+#define CFG_PCIE0_XCFGBASE 0xb0000000 /* local access */
+#define CFG_PCIE0_CFGMASK 0xe0000001 /* 512 Meg */
+
+#define CFG_PCIE1_CFGBASE 0xc0000000 /* remote access */
+#define CFG_PCIE1_XCFGBASE 0xd0000000 /* local access */
+#define CFG_PCIE1_CFGMASK 0xe0000001 /* 512 Meg */
+
+#define CFG_PCIE0_UTLBASE 0xef502000
+#define CFG_PCIE1_UTLBASE 0xef503000
+
+/* base address of inbound PCIe window */
+#define CFG_PCIE_INBOUND_BASE 0x0000000000000000ULL
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+/* Memory Bank 0 (NOR-FLASH) initialization */
+#define CFG_EBC_PB0AP 0x08033700
+#define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0xda000)
+
+/* Memory Bank 2 (CPLD) initialization */
+#define CFG_EBC_PB2AP 0x9400C800
+#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0x800,BS=1MB,BU=R/W,BW=8bit */
+
+#define CFG_EBC_CFG 0x7FC00000 /* EBC0_CFG */
+
+/*-----------------------------------------------------------------------
+ * GPIO Setup
+ *----------------------------------------------------------------------*/
+#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
+{ \
+/* GPIO Core 0 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO0 EBC_DATA_PAR(0) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO1 EBC_DATA_PAR(1) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO2 EBC_DATA_PAR(2) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO3 EBC_DATA_PAR(3) */ \
+{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO4 EBC_DATA(20) USB2_DATA(4) */ \
+{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 EBC_DATA(21) USB2_DATA(5) */ \
+{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 EBC_DATA(22) USB2_DATA(6) */ \
+{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 EBC_DATA(23) USB2_DATA(7) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 CS(1)/NFCE(1) IRQ(7) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 CS(2)/NFCE(2) IRQ(8) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3) IRQ(9) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 IRQ(6) */ \
+{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16) USB2_DATA(0) */ \
+{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17) USB2_DATA(1) */ \
+{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 EBC_DATA(18) USB2_DATA(2) */ \
+{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 EBC_DATA(19) USB2_DATA(3) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD UART1_CTS */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR UART1_RTS */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO20 UART0_DTR UART1_TX */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO21 UART0_RI UART1_RX */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ DMA_ACK2 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK DMA_REQ2 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ DMA_EOT2 IRQ(4) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK DMA_ACK3 IRQ(3) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5) DMA_EOT0 TS(3) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ DMA_EOT3 IRQ(5) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO29 DMA_EOT1 IRQ(2) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO30 DMA_REQ1 IRQ(1) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0}, /* GPIO31 DMA_ACK1 IRQ(0) */ \
+} \
+}
+
+#define CFG_GPIO_PCIE_RST 23
+#define CFG_GPIO_PCIE_CLKREQ 27
+#define CFG_GPIO_PCIE_WAKE 28
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+#endif /* __CONFIG_H */
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
--- /dev/null
+/*
+ * Configuation settings for the Hitachi Solution Engine 7722
+ *
+ * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MS7722SE_H
+#define __MS7722SE_H
+
+#undef DEBUG
+#define CONFIG_SH 1
+#define CONFIG_SH4 1
+#define CONFIG_CPU_SH7722 1
+#define CONFIG_MS7722SE 1
+
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_ENV
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01"
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.0.22
+#define CONFIG_SERVERIP 192.168.0.1
+#define CONFIG_GATEWAYIP 192.168.0.1
+
+#define CONFIG_VERSION_VARIABLE
+#undef CONFIG_SHOW_BOOT_PROGRESS
+
+/* SMC9111 */
+#define CONFIG_DRIVER_SMC91111
+#define CONFIG_SMC91111_BASE (0xB8000000)
+
+/* MEMORY */
+#define MS7722SE_SDRAM_BASE (0x8C000000)
+#define MS7722SE_FLASH_BASE_1 (0xA0000000)
+#define MS7722SE_FLASH_BANK_SIZE (8*1024 * 1024)
+
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Buffer size for input from the Console */
+#define CFG_PBSIZE 256 /* Buffer size for Console output */
+#define CFG_MAXARGS 16 /* max args accepted for monitor commands */
+#define CFG_BARGSIZE 512 /* Buffer size for Boot Arguments passed to kernel */
+#define CFG_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */
+
+/* SCIF */
+#define CFG_SCIF_CONSOLE 1
+#define CONFIG_CONS_SCIF0 1
+#undef CFG_CONSOLE_INFO_QUIET /* Suppress display of console information at boot */
+#undef CFG_CONSOLE_OVERWRITE_ROUTINE
+#undef CFG_CONSOLE_ENV_OVERWRITE
+
+#define CFG_MEMTEST_START (MS7722SE_SDRAM_BASE)
+#define CFG_MEMTEST_END (CFG_MEMTEST_START + (60 * 1024 * 1024))
+
+#undef CFG_ALT_MEMTEST /* Enable alternate, more extensive, memory test */
+#undef CFG_MEMTEST_SCRATCH /* Scratch address used by the alternate memory test */
+
+#undef CFG_LOADS_BAUD_CHANGE /* Enable temporary baudrate change while serial download */
+
+#define CFG_SDRAM_BASE (MS7722SE_SDRAM_BASE)
+#define CFG_SDRAM_SIZE (64 * 1024 * 1024) /* maybe more, but if so u-boot doesn't know about it... */
+
+#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 4 * 1024 * 1024) /* default load address for scripts ?!? */
+
+#define CFG_MONITOR_BASE (MS7722SE_FLASH_BASE_1) /* Address of u-boot image
+ in Flash (NOT run time address in SDRAM) ?!? */
+#define CFG_MONITOR_LEN (128 * 1024) /* */
+#define CFG_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */
+#define CFG_GBL_DATA_SIZE (256) /* size in bytes reserved for initial data */
+#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
+
+/* FLASH */
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#undef CFG_FLASH_QUIET_TEST
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+
+#define CFG_FLASH_BASE (MS7722SE_FLASH_BASE_1) /* Physical start address of Flash memory */
+
+#define CFG_MAX_FLASH_SECT 150 /* Max number of sectors on each
+ Flash chip */
+
+/* if you use all NOR Flash , you change dip-switch. Please see MS7722SE01 Manual. */
+#define CFG_MAX_FLASH_BANKS 2
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE + (0 * MS7722SE_FLASH_BANK_SIZE), \
+ CFG_FLASH_BASE + (1 * MS7722SE_FLASH_BANK_SIZE), \
+ }
+
+#define CFG_FLASH_ERASE_TOUT (3 * 1000) /* Timeout for Flash erase operations (in ms) */
+#define CFG_FLASH_WRITE_TOUT (3 * 1000) /* Timeout for Flash write operations (in ms) */
+#define CFG_FLASH_LOCK_TOUT (3 * 1000) /* Timeout for Flash set sector lock bit operations (in ms) */
+#define CFG_FLASH_UNLOCK_TOUT (3 * 1000) /* Timeout for Flash clear lock bit operations (in ms) */
+
+#undef CFG_FLASH_PROTECTION /* Use hardware flash sectors protection instead of U-Boot software protection */
+
+#undef CFG_DIRECT_FLASH_TFTP
+
+#define CFG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE 1
+#define CFG_ENV_SECT_SIZE (8 * 1024)
+#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + (1 * CFG_ENV_SECT_SIZE))
+#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE) /* Offset of env Flash sector relative to CFG_FLASH_BASE */
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SECT_SIZE)
+#define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + (2 * CFG_ENV_SECT_SIZE))
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ 33333333
+#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */
+#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+
+#endif /* __MS7722SE_H */
--- /dev/null
+/*
+ * Configuation settings for the Hitachi Solution Engine 7750
+ *
+ * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MS7750SE_H
+#define __MS7750SE_H
+
+#undef DEBUG
+#define CONFIG_SH 1
+#define CONFIG_SH4 1
+#define CONFIG_CPU_SH7750 1
+/* #define CONFIG_CPU_SH7751 1 */
+/* #define CONFIG_CPU_TYPE_R 1 */
+#define CONFIG_MS7750SE 1
+#define __LITTLE_ENDIAN__ 1
+
+/*
+ * Command line configuration.
+ */
+/*#include <config_cmd_default.h>*/
+
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_ENV
+
+#define CFG_SCIF_CONSOLE 1
+#define CONFIG_BAUDRATE 38400
+#define CONFIG_CONS_SCIF1 1
+#define BOARD_LATE_INIT 1
+
+#define CONFIG_BOOTDELAY -1
+#define CONFIG_BOOTARGS "console=ttySC0,38400"
+#define CONFIG_ENV_OVERWRITE 1
+
+/* SDRAM */
+#define CFG_SDRAM_BASE (0x8C000000)
+#define CFG_SDRAM_SIZE (64 * 1024 * 1024)
+
+#define CFG_LONGHELP
+#define CFG_PROMPT "=> "
+#define CFG_CBSIZE 256
+#define CFG_PBSIZE 256
+#define CFG_MAXARGS 16
+#define CFG_BARGSIZE 512
+/* List of legal baudrate settings for this board */
+#define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
+
+#define CFG_MEMTEST_START (CFG_SDRAM_BASE)
+#define CFG_MEMTEST_END (TEXT_BASE - 0x100000)
+
+/* NOR Flash */
+/* #define CFG_FLASH_BASE (0xA1000000)*/
+#define CFG_FLASH_BASE (0xA0000000)
+#define CFG_MAX_FLASH_BANKS (1) /* Max number of
+ * Flash memory banks
+ */
+#define CFG_MAX_FLASH_SECT 142
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+
+#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 4 * 1024 * 1024)
+#define CFG_MONITOR_BASE (CFG_FLASH_BASE) /* Address of u-boot image in Flash */
+#define CFG_MONITOR_LEN (128 * 1024)
+#define CFG_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */
+
+#define CFG_GBL_DATA_SIZE (256) /* size in bytes reserved for initial data */
+#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
+#define CFG_RX_ETH_BUFFER (8)
+
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#undef CFG_FLASH_CFI_BROKEN_TABLE
+#undef CFG_FLASH_QUIET_TEST
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+
+
+#define CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x20000
+#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CFG_FLASH_ERASE_TOUT 120000
+#define CFG_FLASH_WRITE_TOUT 500
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ 33333333
+#define TMU_CLK_DIVIDER 4
+#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+
+#endif /* __MS7750SE_H */
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
/*
* Internal Definitions
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 405 CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
/*
* Internal Definitions
/*-----------------------------------------------------------------------
* PPC440 GPIO Configuration
*/
-#define CFG_440_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
+#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
{ \
/* GPIO Core 0 */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
} \
}
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Internal Definitions
*
#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */
#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
- /* have only 8kB, 16kB is save here */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*/
#define CONFIG_JFFS2_PART_SIZE 0x01000000
#define CONFIG_JFFS2_PART_OFFSET 0x00000000
-/*-----------------------------------------------------------------------
- * Cache Configuration
- *
- * CFG_DCACHE_SIZE -> size of data cache:
- * - 405GP 8k
- * - 405GPr 16k
- * How to handle the difference in chache size?
- * CFG_CACHELINE_SIZE -> size of one cache line: 32 bytes
- * (used in cpu/ppc4xx/start.S)
-*/
-#define CFG_DCACHE_SIZE 16384
-
-#define CFG_CACHELINE_SIZE 32
-
-#if defined(CONFIG_CMD_KGDB)
- #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Init Memory Controller:
*
#define CONFIG_SYS_CLK_FREQ ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \
33333333 : 33000000)
+#if 0
+/*
+ * 44x dcache supported is working now on sequoia, but we don't enable
+ * it yet since it needs further testing
+ */
+#define CONFIG_4xx_DCACHE /* enable dcache */
+#endif
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
/* USB */
#ifdef CONFIG_440EPX
-#define CONFIG_USB_OHCI
+#define CONFIG_USB_OHCI_NEW
#define CONFIG_USB_STORAGE
+#define CFG_OHCI_BE_CONTROLLER
+
+#undef CFG_USB_OHCI_BOARD_INIT
+#define CFG_USB_OHCI_CPU_INIT 1
+#define CFG_USB_OHCI_REGS_BASE CFG_USB_HOST
+#define CFG_USB_OHCI_SLOT_NAME "ppc440"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
/* Comment this out to enable USB 1.1 device */
#define USB_2_0_DEVICE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_SUBNETMASK
/*
#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
#define CONFIG_LOGBUFFER
-#define CFG_POST_CACHE_ADDR 0x10000000 /* free virtual address */
+#define CFG_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
-/*-----------------------------------------------------------------------
- * Cache Configuration
- *----------------------------------------------------------------------*/
-#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Internal Definitions
*
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
#endif /* __CONFIG_H */
"bootfile=/tftpboot/taihu/uImage\0" \
"rootpath=/opt/eldk/ppc_4xx\0" \
"netdev=eth0\0" \
+ "hostname=taihu\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
-#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
/*-----------------------------------------------------------------------
* I2C stuff
/* standard dtt sensor configuration */
#define CONFIG_DTT_DS1775 1
#define CONFIG_DTT_SENSORS { 0 }
+#define CFG_I2C_DTT_ADDR 0x49
/*-----------------------------------------------------------------------
* PCI stuff
/*-----------------------------------------------------------------------
* PPC405 GPIO Configuration
*/
-#define CFG_440_GPIO_TABLE { /* GPIO Alternate1 */ \
+#define CFG_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
{ \
/* GPIO Core 0 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast SPI CS */ \
} \
}
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 16384 /* For IBM 405EP CPU */
-#define CFG_CACHELINE_SIZE 32
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-
/*
* Init Memory Controller:
*
#define CFG_EBC_PB4AP 0x158FF600
#define CFG_EBC_PB4CR 0x5021A000
-/*-----------------------------------------------------------------------
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * GPIO0[0] - External Bus Controller BLAST output
- * GPIO0[1-9] - Instruction trace outputs
- * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
- * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[24-27] - UART0 control signal inputs/outputs
- * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
- */
-#define CFG_GPIO0_OSRH 0x15555550 /* output select high/low */
-#define CFG_GPIO0_OSRL 0x00000110
-#define CFG_GPIO0_ISR1H 0x00000001 /* input select high/low */
-#define CFG_GPIO0_ISR1L 0x15545440
-#define CFG_GPIO0_TSRH 0x00000000 /* three-state select high/low */
-#define CFG_GPIO0_TSRL 0x00000000
-#define CFG_GPIO0_TCR 0xFFFE8117 /* three-state control */
-#define CFG_GPIO0_ODR 0x00000000 /* open drain */
-
-#define GPIO0 0 /* GPIO controller 0 */
-
-/* the GPIO macros in include/ppc405.h for High/Low registers are backwards */
-
-#define GPIOx_OSL (GPIO0_OSRH-GPIO_BASE)
-#define GPIOx_TSL (GPIO0_TSRH-GPIO_BASE)
-#define GPIOx_IS1L (GPIO0_ISR1H-GPIO_BASE)
-#define GPIOx_IS2L (GPIO0_ISR1H-GPIO_BASE)
-#define GPIOx_IS3L (GPIO0_ISR1H-GPIO_BASE)
-
-#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO output select */
-#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO three-state select */
-#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO input select */
-#define GPIO_IS2(x) (x+GPIOx_IS1L)
-#define GPIO_IS3(x) (x+GPIOx_IS1L)
-
#define CPLD_REG0_ADDR 0x50100000
#define CPLD_REG1_ADDR 0x50100001
/*
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * Cache Configuration
- *----------------------------------------------------------------------*/
-#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Internal Definitions
*
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+/* use CFI flash driver */
+#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_USE_BUFFER_WRITE 1
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */
#endif
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
- /* have only 8kB, 16kB is save here */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*/
#define CFG_ENV_OFFSET 0x0
#endif /* CFG_ENV_IS_IN_EEPROM */
+/* I2C SYSMON (LM75, AD7414 is almost compatible) */
+#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
+#define CONFIG_DTT_AD7414 1 /* use AD7414 */
+#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
+#define CFG_DTT_MAX_TEMP 70
+#define CFG_DTT_LOW_TEMP -30
+#define CFG_DTT_HYSTERESIS 3
+
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_DTT
#define CONFIG_CMD_ELF
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CFG_BCSR5_PCI66EN 0x80
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Internal Definitions
*
#define CFG_PCI_TARGBASE CFG_PCI_MEMBASE
#define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
-#define CFG_PCIE_MEMSIZE 0x01000000
+#define CFG_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */
#define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
#define CFG_PCIE0_CFGBASE 0xc0000000
#define CFG_PCIE1_XCFGBASE 0xc3001000
#define CFG_PCIE2_XCFGBASE 0xc3002000
+/* base address of inbound PCIe window */
+#define CFG_PCIE_INBOUND_BASE 0x0000000400000000ULL
+
/* System RAM mapped to PCI space */
#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
"setenv filesize;saveenv\0" \
"upd=run load;run update\0" \
"pciconfighost=1\0" \
+ "pcie_mode=RP:EP:EP\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /*Initial Memory map for Linux*/
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
/*
* Internal Definitions
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#endif
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 16384 /* For IBM 405EP CPU */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in data cache)
*/
defined(CONFIG_DTT_DS1621) || \
defined(CONFIG_DTT_DS1775) || \
defined(CONFIG_DTT_LM81) || \
- defined(CONFIG_DTT_ADM1021)
+ defined(CONFIG_DTT_ADM1021) || \
+ defined(CONFIG_DTT_LM73)
#define CONFIG_DTT /* We have a DTT */
#define DTT_ADM1021_DEVID 0x41
#endif
+#if defined(CONFIG_DTT_LM73)
+#define DTT_READ_TEMP 0x0
+#define DTT_CONFIG 0x1
+#define DTT_TEMP_HIGH 0x2
+#define DTT_TEMP_LOW 0x3
+#define DTT_CONTROL 0x4
+#define DTT_ID 0x7
+#endif
+
#endif /* _DTT_H_ */
{
unsigned long freqProcessor;
unsigned long freqSystemBus;
+ unsigned long freqDDRBus;
} MPC85xx_SYS_INFO;
#endif /* _ASMLANGUAGE */
const char *prop, const void *val, int len, int create);
void do_fixup_by_compat_u32(void *fdt, const char *compat,
const char *prop, u32 val, int create);
+int fdt_fixup_memory(void *blob, u64 start, u64 size);
void fdt_fixup_ethernet(void *fdt, bd_t *bd);
#ifdef CONFIG_OF_HAS_UBOOT_ENV
ushort ext_addr; /* extended query table address */
ushort cfi_version; /* cfi version */
ushort cfi_offset; /* offset for cfi query */
+ ulong addr_unlock1; /* unlock address 1 for AMD flash roms */
+ ulong addr_unlock2; /* unlock address 2 for AMD flash roms */
+ const char *name; /* human-readable name */
#endif
} flash_info_t;
#define FLASH_CFI_X8 0x00
#define FLASH_CFI_X16 0x01
#define FLASH_CFI_X8X16 0x02
+#define FLASH_CFI_X16X32 0x05
/* convert between bit value and numeric value */
#define CFI_FLASH_SHIFT_WIDTH 3
extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int offset, int len);
#endif /* CFG_FLASH_PROTECTION */
+#ifdef CONFIG_FLASH_CFI_LEGACY
+extern ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info);
+extern int jedec_flash_match(flash_info_t *info, ulong base);
+#define CFI_CMDSET_AMD_LEGACY 0xFFF0
+#endif
+
+
/*-----------------------------------------------------------------------
* return codes from flash_write():
*/
* a 0x20 byte boundary
*/
#ifdef CONFIG_MPC85xx
-#define ioport_addr(im, idx) (ioport_t *)((uint)&((im)->im_cpm.im_cpm_iop) + ((idx)*0x20))
+#define ioport_addr(im, idx) (ioport_t *)((uint)&(im->im_cpm_iop) + ((idx)*0x20))
#else
#define ioport_addr(im, idx) (ioport_t *)((uint)&(im)->im_ioport + ((idx)*0x20))
#endif
* offset = fdt_node_offset_by_prop_value(fdt, -1, propname,
* propval, proplen);
* while (offset != -FDT_ERR_NOTFOUND) {
- * // other code here
+ * ... other code here ...
* offset = fdt_node_offset_by_prop_value(fdt, offset, propname,
* propval, proplen);
* }
* idiom can be used:
* offset = fdt_node_offset_by_compatible(fdt, -1, compatible);
* while (offset != -FDT_ERR_NOTFOUND) {
- * // other code here
+ * ... other code here ...
* offset = fdt_node_offset_by_compatible(fdt, offset, compatible);
* }
*
#ifndef __PPC405_H__
#define __PPC405_H__
+#ifndef CONFIG_IOP480
+#define CFG_DCACHE_SIZE (16 << 10) /* For AMCC 405 CPUs */
+#else
+#define CFG_DCACHE_SIZE (2 << 10) /* For PLX IOP480 (403) */
+#endif
+
/*--------------------------------------------------------------------- */
/* Special Purpose Registers */
/*--------------------------------------------------------------------- */
#define uicvr (UIC_DCR_BASE+0x7) /* UIC vector */
#define uicvcr (UIC_DCR_BASE+0x8) /* UIC vector configuration */
+#if defined(CONFIG_405EX)
+#define uic0sr uicsr /* UIC status */
+#define uic0srs uicsrs /* UIC status set */
+#define uic0er uicer /* UIC enable */
+#define uic0cr uiccr /* UIC critical */
+#define uic0pr uicpr /* UIC polarity */
+#define uic0tr uictr /* UIC triggering */
+#define uic0msr uicmsr /* UIC masked status */
+#define uic0vr uicvr /* UIC vector */
+#define uic0vcr uicvcr /* UIC vector configuration*/
+
+#define UIC_DCR_BASE1 0xd0
+#define uic1sr (UIC_DCR_BASE1+0x0) /* UIC status */
+#define uic1srs (UIC_DCR_BASE1+0x1) /* UIC status set */
+#define uic1er (UIC_DCR_BASE1+0x2) /* UIC enable */
+#define uic1cr (UIC_DCR_BASE1+0x3) /* UIC critical */
+#define uic1pr (UIC_DCR_BASE1+0x4) /* UIC polarity */
+#define uic1tr (UIC_DCR_BASE1+0x5) /* UIC triggering */
+#define uic1msr (UIC_DCR_BASE1+0x6) /* UIC masked status */
+#define uic1vr (UIC_DCR_BASE1+0x7) /* UIC vector */
+#define uic1vcr (UIC_DCR_BASE1+0x8) /* UIC vector configuration*/
+
+#define UIC_DCR_BASE2 0xe0
+#define uic2sr (UIC_DCR_BASE2+0x0) /* UIC status */
+#define uic2srs (UIC_DCR_BASE2+0x1) /* UIC status set */
+#define uic2er (UIC_DCR_BASE2+0x2) /* UIC enable */
+#define uic2cr (UIC_DCR_BASE2+0x3) /* UIC critical */
+#define uic2pr (UIC_DCR_BASE2+0x4) /* UIC polarity */
+#define uic2tr (UIC_DCR_BASE2+0x5) /* UIC triggering */
+#define uic2msr (UIC_DCR_BASE2+0x6) /* UIC masked status */
+#define uic2vr (UIC_DCR_BASE2+0x7) /* UIC vector */
+#define uic2vcr (UIC_DCR_BASE2+0x8) /* UIC vector configuration*/
+#endif
+
/*-----------------------------------------------------------------------------+
| Universal interrupt controller interrupts
+-----------------------------------------------------------------------------*/
#define UIC_EXT3 0x00000002 /* External interrupt 3 */
#define UIC_EXT4 0x00000001 /* External interrupt 4 */
+#elif defined(CONFIG_405EX)
+
+/* UIC 0 */
+#define UIC_U0 0x80000000 /* */
+#define UIC_U1 0x40000000 /* */
+#define UIC_IIC0 0x20000000 /* */
+#define UIC_PKA 0x10000000 /* */
+#define UIC_TRNG 0x08000000 /* */
+#define UIC_EBM 0x04000000 /* */
+#define UIC_BGI 0x02000000 /* */
+#define UIC_IIC1 0x01000000 /* */
+#define UIC_SPI 0x00800000 /* */
+#define UIC_EIRQ0 0x00400000 /**/
+#define UIC_MTE 0x00200000 /*MAL Tx EOB */
+#define UIC_MRE 0x00100000 /*MAL Rx EOB */
+#define UIC_DMA0 0x00080000 /* */
+#define UIC_DMA1 0x00040000 /* */
+#define UIC_DMA2 0x00020000 /* */
+#define UIC_DMA3 0x00010000 /* */
+#define UIC_PCIE0AL 0x00008000 /* */
+#define UIC_PCIE0VPD 0x00004000 /* */
+#define UIC_RPCIE0HRST 0x00002000 /* */
+#define UIC_FPCIE0HRST 0x00001000 /* */
+#define UIC_PCIE0TCR 0x00000800 /* */
+#define UIC_PCIEMSI0 0x00000400 /* */
+#define UIC_PCIEMSI1 0x00000200 /* */
+#define UIC_SECURITY 0x00000100 /* */
+#define UIC_ENET 0x00000080 /* */
+#define UIC_ENET1 0x00000040 /* */
+#define UIC_PCIEMSI2 0x00000020 /* */
+#define UIC_EIRQ4 0x00000010 /**/
+#define UIC_UIC2NC 0x00000008 /* */
+#define UIC_UIC2C 0x00000004 /* */
+#define UIC_UIC1NC 0x00000002 /* */
+#define UIC_UIC1C 0x00000001 /* */
+
+#define UIC_MAL_TXEOB UIC_MTE/* MAL TXEOB */
+#define UIC_MAL_RXEOB UIC_MRE/* MAL RXEOB */
+/* UIC 1 */
+#define UIC_MS 0x80000000 /* MAL SERR */
+#define UIC_MTDE 0x40000000 /* MAL TXDE */
+#define UIC_MRDE 0x20000000 /* MAL RXDE */
+#define UIC_PCIE0BMVC0 0x10000000 /* */
+#define UIC_PCIE0DCRERR 0x08000000 /* */
+#define UIC_EBC 0x04000000 /* */
+#define UIC_NDFC 0x02000000 /* */
+#define UIC_PCEI1DCRERR 0x01000000 /* */
+#define UIC_GPTCMPT8 0x00800000 /* */
+#define UIC_GPTCMPT9 0x00400000 /* */
+#define UIC_PCIE1AL 0x00200000 /* */
+#define UIC_PCIE1VPD 0x00100000 /* */
+#define UIC_RPCE1HRST 0x00080000 /* */
+#define UIC_FPCE1HRST 0x00040000 /* */
+#define UIC_PCIE1TCR 0x00020000 /* */
+#define UIC_PCIE1VC0 0x00010000 /* */
+#define UIC_GPTCMPT3 0x00008000 /* */
+#define UIC_GPTCMPT4 0x00004000 /* */
+#define UIC_EIRQ7 0x00002000 /* */
+#define UIC_EIRQ8 0x00001000 /* */
+#define UIC_EIRQ9 0x00000800 /* */
+#define UIC_GPTCMP5 0x00000400 /* */
+#define UIC_GPTCMP6 0x00000200 /* */
+#define UIC_GPTCMP7 0x00000100 /* */
+#define UIC_SROM 0x00000080 /* SERIAL ROM*/
+#define UIC_GPTDECPULS 0x00000040 /* GPT Decrement pulse*/
+#define UIC_EIRQ2 0x00000020 /* */
+#define UIC_EIRQ5 0x00000010 /* */
+#define UIC_EIRQ6 0x00000008 /* */
+#define UIC_EMAC0WAKE 0x00000004 /* */
+#define UIC_EIRQ1 0x00000002 /* */
+#define UIC_EMAC1WAKE 0x00000001 /* */
+#define UIC_MAL_SERR UIC_MS /* MAL SERR */
+#define UIC_MAL_TXDE UIC_MTDE /* MAL TXDE */
+#define UIC_MAL_RXDE UIC_MRDE /* MAL RXDE */
+/* UIC 2 */
+#define UIC_PCIE0INTA 0x80000000 /* PCIE0 INTA*/
+#define UIC_PCIE0INTB 0x40000000 /* PCIE0 INTB*/
+#define UIC_PCIE0INTC 0x20000000 /* PCIE0 INTC*/
+#define UIC_PCIE0INTD 0x10000000 /* PCIE0 INTD*/
+#define UIC_EIRQ3 0x08000000 /* External IRQ 3*/
+#define UIC_DDRMCUE 0x04000000 /* */
+#define UIC_DDRMCCE 0x02000000 /* */
+#define UIC_MALINTCOATX0 0x01000000 /* Interrupt coalecence TX0*/
+#define UIC_MALINTCOATX1 0x00800000 /* Interrupt coalecence TX1*/
+#define UIC_MALINTCOARX0 0x00400000 /* Interrupt coalecence RX0*/
+#define UIC_MALINTCOARX1 0x00200000 /* Interrupt coalecence RX1*/
+#define UIC_PCIE1INTA 0x00100000 /* PCIE0 INTA*/
+#define UIC_PCIE1INTB 0x00080000 /* PCIE0 INTB*/
+#define UIC_PCIE1INTC 0x00040000 /* PCIE0 INTC*/
+#define UIC_PCIE1INTD 0x00020000 /* PCIE0 INTD*/
+#define UIC_RPCIEMSI2 0x00010000 /* MSI level 2 Note this looks same as uic0-26*/
+#define UIC_PCIEMSI3 0x00008000 /* MSI level 2*/
+#define UIC_PCIEMSI4 0x00004000 /* MSI level 2*/
+#define UIC_PCIEMSI5 0x00002000 /* MSI level 2*/
+#define UIC_PCIEMSI6 0x00001000 /* MSI level 2*/
+#define UIC_PCIEMSI7 0x00000800 /* MSI level 2*/
+#define UIC_PCIEMSI8 0x00000400 /* MSI level 2*/
+#define UIC_PCIEMSI9 0x00000200 /* MSI level 2*/
+#define UIC_PCIEMSI10 0x00000100 /* MSI level 2*/
+#define UIC_PCIEMSI11 0x00000080 /* MSI level 2*/
+#define UIC_PCIEMSI12 0x00000040 /* MSI level 2*/
+#define UIC_PCIEMSI13 0x00000020 /* MSI level 2*/
+#define UIC_PCIEMSI14 0x00000010 /* MSI level 2*/
+#define UIC_PCIEMSI15 0x00000008 /* MSI level 2*/
+#define UIC_PLB4XAHB 0x00000004 /* PLBxAHB bridge*/
+#define UIC_USBWAKE 0x00000002 /* USB wakup*/
+#define UIC_USBOTG 0x00000001 /* USB OTG*/
+#define UIC_ETH0 UIC_ENET
+#define UIC_ETH1 UIC_ENET1
+
#else /* !defined(CONFIG_405EZ) */
#define UIC_UART0 0x80000000 /* UART 0 */
/******************************************************************************
* SDRAM Controller
******************************************************************************/
-#define SDRAM_DCR_BASE 0x10
-#define memcfga (SDRAM_DCR_BASE+0x0) /* Memory configuration address reg */
-#define memcfgd (SDRAM_DCR_BASE+0x1) /* Memory configuration data reg */
/* values for memcfga register - indirect addressing of these regs */
#ifndef CONFIG_405EP
#define mem_besra 0x00 /* bus error syndrome reg a */
/******************************************************************************
* Power Management
******************************************************************************/
+#ifdef CONFIG_405EX
+#define POWERMAN_DCR_BASE 0xb0
+#else
#define POWERMAN_DCR_BASE 0xb8
+#endif
#define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */
#define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */
#define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force */
/******************************************************************************
* Extrnal Bus Controller
******************************************************************************/
-#define EBC_DCR_BASE 0x12
-#define ebccfga (EBC_DCR_BASE+0x0) /* External bus controller addr reg */
-#define ebccfgd (EBC_DCR_BASE+0x1) /* External bus controller data reg */
/* values for ebccfga register - indirect addressing of these regs */
#define pb0cr 0x00 /* periph bank 0 config reg */
#define pb1cr 0x01 /* periph bank 1 config reg */
#define VCO_MIN 500
#define VCO_MAX 1000
#elif defined(CONFIG_405EZ)
-/******************************************************************************
- * SDR Registers
- ******************************************************************************/
-#define SDR_DCR_BASE 0x0E
-#define sdrcfga (SDR_DCR_BASE+0x0) /* ADDR */
-#define sdrcfgd (SDR_DCR_BASE+0x1) /* Data */
-
-#define mtsdr(reg, data) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); } while (0)
-#define mfsdr(reg, data) do { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); } while (0)
-
#define sdrnand0 0x4000
#define sdrultra0 0x4040
#define sdrultra1 0x4050
/******************************************************************************
* Control
******************************************************************************/
-#define CNTRL_DCR_BASE 0x0C
-#define cprcfga (CNTRL_DCR_BASE+0x0) /* CPR addr reg */
-#define cprcfgd (CNTRL_DCR_BASE+0x1) /* CPR data reg */
-
/* CPR Registers */
#define cprclkupd 0x020 /* CPR_CLKUPD */
#define cprpllc 0x040 /* CPR_PLLC */
#define cprmisc0 0x181 /* CPR_MISC0 */
#define cprmisc1 0x182 /* CPR_MISC1 */
-/*
- * Macro for accessing the indirect CPR register
- */
-#define mtcpr(reg, data) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,data); } while (0)
-#define mfcpr(reg, data) do { mtdcr(cprcfga,reg);data = mfdcr(cprcfgd); } while (0)
-
#define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */
#define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */
#define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */
#define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */
#define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */
-#if 0 /* Deprecated */
-#define CNTRL_DCR_BASE 0x0f0
-#define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */
-#define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */
-#define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */
-#define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */
-#define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */
-#define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */
-
-#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */
-#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
-#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
-#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/
-#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */
-#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */
-#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */
-#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */
-#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */
-#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */
-
-/* Bit definitions */
-#define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */
-#define PLLMR0_CPU_DIV_BYPASS 0x00000000
-#define PLLMR0_CPU_DIV_2 0x00100000
-#define PLLMR0_CPU_DIV_3 0x00200000
-#define PLLMR0_CPU_DIV_4 0x00300000
-
-#define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */
-#define PLLMR0_CPU_PLB_DIV_1 0x00000000
-#define PLLMR0_CPU_PLB_DIV_2 0x00010000
-#define PLLMR0_CPU_PLB_DIV_3 0x00020000
-#define PLLMR0_CPU_PLB_DIV_4 0x00030000
-
-#define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */
-#define PLLMR0_OPB_PLB_DIV_1 0x00000000
-#define PLLMR0_OPB_PLB_DIV_2 0x00001000
-#define PLLMR0_OPB_PLB_DIV_3 0x00002000
-#define PLLMR0_OPB_PLB_DIV_4 0x00003000
-
-#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */
-#define PLLMR0_EXB_PLB_DIV_2 0x00000000
-#define PLLMR0_EXB_PLB_DIV_3 0x00000100
-#define PLLMR0_EXB_PLB_DIV_4 0x00000200
-#define PLLMR0_EXB_PLB_DIV_5 0x00000300
-
-#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */
-#define PLLMR0_MAL_PLB_DIV_1 0x00000000
-#define PLLMR0_MAL_PLB_DIV_2 0x00000010
-#define PLLMR0_MAL_PLB_DIV_3 0x00000020
-#define PLLMR0_MAL_PLB_DIV_4 0x00000030
-
-#define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */
-#define PLLMR0_PCI_PLB_DIV_1 0x00000000
-#define PLLMR0_PCI_PLB_DIV_2 0x00000001
-#define PLLMR0_PCI_PLB_DIV_3 0x00000002
-#define PLLMR0_PCI_PLB_DIV_4 0x00000003
-
-#define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */
-#define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */
-#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */
-#define PLLMR1_FBMUL_DIV_16 0x00000000
-#define PLLMR1_FBMUL_DIV_1 0x00100000
-#define PLLMR1_FBMUL_DIV_2 0x00200000
-#define PLLMR1_FBMUL_DIV_3 0x00300000
-#define PLLMR1_FBMUL_DIV_4 0x00400000
-#define PLLMR1_FBMUL_DIV_5 0x00500000
-#define PLLMR1_FBMUL_DIV_6 0x00600000
-#define PLLMR1_FBMUL_DIV_7 0x00700000
-#define PLLMR1_FBMUL_DIV_8 0x00800000
-#define PLLMR1_FBMUL_DIV_9 0x00900000
-#define PLLMR1_FBMUL_DIV_10 0x00A00000
-#define PLLMR1_FBMUL_DIV_11 0x00B00000
-#define PLLMR1_FBMUL_DIV_12 0x00C00000
-#define PLLMR1_FBMUL_DIV_13 0x00D00000
-#define PLLMR1_FBMUL_DIV_14 0x00E00000
-#define PLLMR1_FBMUL_DIV_15 0x00F00000
-
-#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */
-#define PLLMR1_FWDVA_DIV_8 0x00000000
-#define PLLMR1_FWDVA_DIV_7 0x00010000
-#define PLLMR1_FWDVA_DIV_6 0x00020000
-#define PLLMR1_FWDVA_DIV_5 0x00030000
-#define PLLMR1_FWDVA_DIV_4 0x00040000
-#define PLLMR1_FWDVA_DIV_3 0x00050000
-#define PLLMR1_FWDVA_DIV_2 0x00060000
-#define PLLMR1_FWDVA_DIV_1 0x00070000
-#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */
-#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */
-
-/* Defines for CPC0_EPRCSR register */
-#define CPC0_EPRCSR_E0NFE 0x80000000
-#define CPC0_EPRCSR_E1NFE 0x40000000
-#define CPC0_EPRCSR_E1RPP 0x00000080
-#define CPC0_EPRCSR_E0RPP 0x00000040
-#define CPC0_EPRCSR_E1ERP 0x00000020
-#define CPC0_EPRCSR_E0ERP 0x00000010
-#define CPC0_EPRCSR_E1PCI 0x00000002
-#define CPC0_EPRCSR_E0PCI 0x00000001
-
-/* Defines for CPC0_BOOR Register */
-#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */
-
-/* Defines for CPC0_PLLMR1 Register fields */
-#define PLL_ACTIVE 0x80000000
-#define CPC0_PLLMR1_SSCS 0x80000000
-#define PLL_RESET 0x40000000
-#define CPC0_PLLMR1_PLLR 0x40000000
- /* Feedback multiplier */
-#define PLL_FBKDIV 0x00F00000
-#define CPC0_PLLMR1_FBDV 0x00F00000
-#define PLL_FBKDIV_16 0x00000000
-#define PLL_FBKDIV_1 0x00100000
-#define PLL_FBKDIV_2 0x00200000
-#define PLL_FBKDIV_3 0x00300000
-#define PLL_FBKDIV_4 0x00400000
-#define PLL_FBKDIV_5 0x00500000
-#define PLL_FBKDIV_6 0x00600000
-#define PLL_FBKDIV_7 0x00700000
-#define PLL_FBKDIV_8 0x00800000
-#define PLL_FBKDIV_9 0x00900000
-#define PLL_FBKDIV_10 0x00A00000
-#define PLL_FBKDIV_11 0x00B00000
-#define PLL_FBKDIV_12 0x00C00000
-#define PLL_FBKDIV_13 0x00D00000
-#define PLL_FBKDIV_14 0x00E00000
-#define PLL_FBKDIV_15 0x00F00000
- /* Forward A divisor */
-#define PLL_FWDDIVA 0x00070000
-#define CPC0_PLLMR1_FWDVA 0x00070000
-#define PLL_FWDDIVA_8 0x00000000
-#define PLL_FWDDIVA_7 0x00010000
-#define PLL_FWDDIVA_6 0x00020000
-#define PLL_FWDDIVA_5 0x00030000
-#define PLL_FWDDIVA_4 0x00040000
-#define PLL_FWDDIVA_3 0x00050000
-#define PLL_FWDDIVA_2 0x00060000
-#define PLL_FWDDIVA_1 0x00070000
- /* Forward B divisor */
-#define PLL_FWDDIVB 0x00007000
-#define CPC0_PLLMR1_FWDVB 0x00007000
-#define PLL_FWDDIVB_8 0x00000000
-#define PLL_FWDDIVB_7 0x00001000
-#define PLL_FWDDIVB_6 0x00002000
-#define PLL_FWDDIVB_5 0x00003000
-#define PLL_FWDDIVB_4 0x00004000
-#define PLL_FWDDIVB_3 0x00005000
-#define PLL_FWDDIVB_2 0x00006000
-#define PLL_FWDDIVB_1 0x00007000
- /* PLL tune bits */
-#define PLL_TUNE_MASK 0x000003FF
-#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
-#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
-#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
-#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
-#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
-#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
-#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
-
-/* Defines for CPC0_PLLMR0 Register fields */
- /* CPU divisor */
-#define PLL_CPUDIV 0x00300000
-#define CPC0_PLLMR0_CCDV 0x00300000
-#define PLL_CPUDIV_1 0x00000000
-#define PLL_CPUDIV_2 0x00100000
-#define PLL_CPUDIV_3 0x00200000
-#define PLL_CPUDIV_4 0x00300000
- /* PLB divisor */
-#define PLL_PLBDIV 0x00030000
-#define CPC0_PLLMR0_CBDV 0x00030000
-#define PLL_PLBDIV_1 0x00000000
-#define PLL_PLBDIV_2 0x00010000
-#define PLL_PLBDIV_3 0x00020000
-#define PLL_PLBDIV_4 0x00030000
- /* OPB divisor */
-#define PLL_OPBDIV 0x00003000
-#define CPC0_PLLMR0_OPDV 0x00003000
-#define PLL_OPBDIV_1 0x00000000
-#define PLL_OPBDIV_2 0x00001000
-#define PLL_OPBDIV_3 0x00002000
-#define PLL_OPBDIV_4 0x00003000
- /* EBC divisor */
-#define PLL_EXTBUSDIV 0x00000300
-#define CPC0_PLLMR0_EPDV 0x00000300
-#define PLL_EXTBUSDIV_2 0x00000000
-#define PLL_EXTBUSDIV_3 0x00000100
-#define PLL_EXTBUSDIV_4 0x00000200
-#define PLL_EXTBUSDIV_5 0x00000300
- /* MAL divisor */
-#define PLL_MALDIV 0x00000030
-#define CPC0_PLLMR0_MPDV 0x00000030
-#define PLL_MALDIV_1 0x00000000
-#define PLL_MALDIV_2 0x00000010
-#define PLL_MALDIV_3 0x00000020
-#define PLL_MALDIV_4 0x00000030
- /* PCI divisor */
-#define PLL_PCIDIV 0x00000003
-#define CPC0_PLLMR0_PPFD 0x00000003
-#define PLL_PCIDIV_1 0x00000000
-#define PLL_PCIDIV_2 0x00000001
-#define PLL_PCIDIV_3 0x00000002
-#define PLL_PCIDIV_4 0x00000003
-
-/*
- *-------------------------------------------------------------------------------
- * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
- * assuming a 33.3MHz input clock to the 405EP.
- *-------------------------------------------------------------------------------
- */
-#define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \
- PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-#define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \
- PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
- PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \
- PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-#define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
- PLL_MALDIV_1 | PLL_PCIDIV_2)
-#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \
- PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-/*
- * PLL Voltage Controlled Oscillator (VCO) definitions
- * Maximum and minimum values (in MHz) for correct PLL operation.
- */
-#define VCO_MIN 500
-#define VCO_MAX 1000
-#endif /* #if 0 */
#else /* #ifdef CONFIG_405EP */
/******************************************************************************
* Control
#define GPIO1_ISR3L (GPIO1_BASE+0x40)
#define GPIO1_ISR3H (GPIO1_BASE+0x44)
+#elif defined(CONFIG_405EX)
+#define GPIO_BASE 0xEF600800
+#define GPIO0_OR (GPIO_BASE+0x0)
+#define GPIO0_TCR (GPIO_BASE+0x4)
+#define GPIO0_OSRL (GPIO_BASE+0x8)
+#define GPIO0_OSRH (GPIO_BASE+0xC)
+#define GPIO0_TSRL (GPIO_BASE+0x10)
+#define GPIO0_TSRH (GPIO_BASE+0x14)
+#define GPIO0_ODR (GPIO_BASE+0x18)
+#define GPIO0_IR (GPIO_BASE+0x1C)
+#define GPIO0_RR1 (GPIO_BASE+0x20)
+#define GPIO0_RR2 (GPIO_BASE+0x24)
+#define GPIO0_ISR1L (GPIO_BASE+0x30)
+#define GPIO0_ISR1H (GPIO_BASE+0x34)
+#define GPIO0_ISR2L (GPIO_BASE+0x38)
+#define GPIO0_ISR2H (GPIO_BASE+0x3C)
+#define GPIO0_ISR3L (GPIO_BASE+0x40)
+#define GPIO0_ISR3H (GPIO_BASE+0x44)
+
#else /* !405EZ */
#define GPIO_BASE 0xEF600700
#endif /* CONFIG_405EZ */
-/*
- * Macro for accessing the indirect EBC register
- */
-#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
-#define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd)
-
-#define mtsdram(reg, data) do { mtdcr(memcfga,reg);mtdcr(memcfgd,data); } while (0)
-#define mfsdram(reg, data) do { mtdcr(memcfga,reg);data = mfdcr(memcfgd); } while (0)
-
-#ifndef __ASSEMBLY__
-
-typedef struct
-{
- unsigned long pllFwdDiv;
- unsigned long pllFwdDivB;
- unsigned long pllFbkDiv;
- unsigned long pllPlbDiv;
- unsigned long pllPciDiv;
- unsigned long pllExtBusDiv;
- unsigned long pllOpbDiv;
- unsigned long freqVCOMhz; /* in MHz */
- unsigned long freqProcessor;
- unsigned long freqPLB;
- unsigned long freqPCI;
- unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */
- unsigned long pciClkSync; /* PCI clock is synchronous */
- unsigned long freqVCOHz;
-} PPC405_SYS_INFO;
-
-#endif /* _ASMLANGUAGE */
-
-#define RESET_VECTOR 0xfffffffc
-#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache
- line aligned data. */
+#define GPIO0_BASE GPIO_BASE
+
+#if defined(CONFIG_405EX)
+#define SDR0_SRST 0x0200
+
+#define SDRAM_BESR0 0x00
+#define SDRAM_BEARL 0x02
+#define SDRAM_BEARU 0x03
+#define SDRAM_WMIRQ 0x06 /**/
+#define SDRAM_PLBOPT 0x08 /**/
+#define SDRAM_PUABA 0x09 /**/
+#define SDRAM_MCSTAT 0x1F /* memory controller status */
+#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */
+#define SDRAM_MCOPT2 0x21 /* memory controller options 2 */
+#define SDRAM_MODT0 0x22 /* on die termination for bank 0 */
+#define SDRAM_MODT1 0x23 /* on die termination for bank 1 */
+#define SDRAM_MODT2 0x24 /* on die termination for bank 2 */
+#define SDRAM_MODT3 0x25 /* on die termination for bank 3 */
+#define SDRAM_CODT 0x26 /* on die termination for controller */
+#define SDRAM_VVPR 0x27 /* variable VRef programmming */
+#define SDRAM_OPARS 0x28 /* on chip driver control setup */
+#define SDRAM_OPART 0x29 /* on chip driver control trigger */
+#define SDRAM_RTR 0x30 /* refresh timer */
+#define SDRAM_PMIT 0x34 /* power management idle timer */
+#define SDRAM_MB0CF 0x40 /* memory bank 0 configuration */
+#define SDRAM_MB1CF 0x44 /* memory bank 1 configuration */
+#define SDRAM_MB2CF 0x48 /* memory bank 2 configuration */
+#define SDRAM_MB3CF 0x4C /* memory bank 3 configuration */
+#define SDRAM_INITPLR0 0x50 /* manual initialization control */
+#define SDRAM_INITPLR1 0x51 /* manual initialization control */
+#define SDRAM_INITPLR2 0x52 /* manual initialization control */
+#define SDRAM_INITPLR3 0x53 /* manual initialization control */
+#define SDRAM_INITPLR4 0x54 /* manual initialization control */
+#define SDRAM_INITPLR5 0x55 /* manual initialization control */
+#define SDRAM_INITPLR6 0x56 /* manual initialization control */
+#define SDRAM_INITPLR7 0x57 /* manual initialization control */
+#define SDRAM_INITPLR8 0x58 /* manual initialization control */
+#define SDRAM_INITPLR9 0x59 /* manual initialization control */
+#define SDRAM_INITPLR10 0x5a /* manual initialization control */
+#define SDRAM_INITPLR11 0x5b /* manual initialization control */
+#define SDRAM_INITPLR12 0x5c /* manual initialization control */
+#define SDRAM_INITPLR13 0x5d /* manual initialization control */
+#define SDRAM_INITPLR14 0x5e /* manual initialization control */
+#define SDRAM_INITPLR15 0x5f /* manual initialization control */
+#define SDRAM_RQDC 0x70 /* read DQS delay control */
+#define SDRAM_RFDC 0x74 /* read feedback delay control */
+#define SDRAM_RDCC 0x78 /* read data capture control */
+#define SDRAM_DLCR 0x7A /* delay line calibration */
+#define SDRAM_CLKTR 0x80 /* DDR clock timing */
+#define SDRAM_WRDTR 0x81 /* write data, DQS, DM clock, timing */
+#define SDRAM_SDTR1 0x85 /* DDR SDRAM timing 1 */
+#define SDRAM_SDTR2 0x86 /* DDR SDRAM timing 2 */
+#define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */
+#define SDRAM_MMODE 0x88 /* memory mode */
+#define SDRAM_MEMODE 0x89 /* memory extended mode */
+#define SDRAM_ECCCR 0x98 /* ECC error status */
+#define SDRAM_RID 0xF8 /* revision ID */
+
+/*-----------------------------------------------------------------------------+
+| Memory Bank 0-7 configuration
++-----------------------------------------------------------------------------*/
+#define SDRAM_RXBAS_SDSZ_4 0x00000000 /* 4M */
+#define SDRAM_RXBAS_SDSZ_8 0x00001000 /* 8M */
+#define SDRAM_RXBAS_SDSZ_16 0x00002000 /* 16M */
+#define SDRAM_RXBAS_SDSZ_32 0x00003000 /* 32M */
+#define SDRAM_RXBAS_SDSZ_64 0x00004000 /* 64M */
+#define SDRAM_RXBAS_SDSZ_128 0x00005000 /* 128M */
+#define SDRAM_RXBAS_SDSZ_256 0x00006000 /* 256M */
+#define SDRAM_RXBAS_SDSZ_512 0x00007000 /* 512M */
+#define SDRAM_RXBAS_SDSZ_1024 0x00008000 /* 1024M */
+#define SDRAM_RXBAS_SDSZ_2048 0x00009000 /* 2048M */
+#define SDRAM_RXBAS_SDSZ_4096 0x0000a000 /* 4096M */
+#define SDRAM_RXBAS_SDSZ_8192 0x0000b000 /* 8192M */
+
+/*-----------------------------------------------------------------------------+
+| Memory Controller Status
++-----------------------------------------------------------------------------*/
+#define SDRAM_MCSTAT_MIC_MASK 0x80000000 /* Memory init status mask */
+#define SDRAM_MCSTAT_MIC_NOTCOMP 0x00000000 /* Mem init not complete */
+#define SDRAM_MCSTAT_MIC_COMP 0x80000000 /* Mem init complete */
+#define SDRAM_MCSTAT_SRMS_MASK 0x80000000 /* Mem self refresh stat mask */
+#define SDRAM_MCSTAT_SRMS_NOT_SF 0x00000000 /* Mem not in self refresh */
+#define SDRAM_MCSTAT_SRMS_SF 0x80000000 /* Mem in self refresh */
+
+/*-----------------------------------------------------------------------------+
+| Memory Controller Options 1
++-----------------------------------------------------------------------------*/
+#define SDRAM_MCOPT1_MCHK_MASK 0x30000000 /* Memory data err check mask */
+#define SDRAM_MCOPT1_MCHK_NON 0x00000000 /* No ECC generation */
+#define SDRAM_MCOPT1_MCHK_GEN 0x20000000 /* ECC generation */
+#define SDRAM_MCOPT1_MCHK_CHK 0x10000000 /* ECC generation and check */
+#define SDRAM_MCOPT1_MCHK_CHK_REP 0x30000000 /* ECC generation, chk, report*/
+#define SDRAM_MCOPT1_MCHK_CHK_DECODE(n) ((((unsigned long)(n))>>28)&0x3)
+#define SDRAM_MCOPT1_RDEN_MASK 0x08000000 /* Registered DIMM mask */
+#define SDRAM_MCOPT1_RDEN 0x08000000 /* Registered DIMM enable */
+#define SDRAM_MCOPT1_PMU_MASK 0x06000000 /* Page management unit mask */
+#define SDRAM_MCOPT1_PMU_CLOSE 0x00000000 /* PMU Close */
+#define SDRAM_MCOPT1_PMU_OPEN 0x04000000 /* PMU Open */
+#define SDRAM_MCOPT1_PMU_AUTOCLOSE 0x02000000 /* PMU AutoClose */
+#define SDRAM_MCOPT1_DMWD_MASK 0x01000000 /* DRAM width mask */
+#define SDRAM_MCOPT1_DMWD_32 0x00000000 /* 32 bits */
+#define SDRAM_MCOPT1_DMWD_64 0x01000000 /* 64 bits */
+#define SDRAM_MCOPT1_UIOS_MASK 0x00C00000 /* Unused IO State */
+#define SDRAM_MCOPT1_BCNT_MASK 0x00200000 /* Bank count */
+#define SDRAM_MCOPT1_4_BANKS 0x00000000 /* 4 Banks */
+#define SDRAM_MCOPT1_8_BANKS 0x00200000 /* 8 Banks */
+#define SDRAM_MCOPT1_DDR_TYPE_MASK 0x00100000 /* DDR Memory Type mask */
+#define SDRAM_MCOPT1_DDR1_TYPE 0x00000000 /* DDR1 Memory Type */
+#define SDRAM_MCOPT1_DDR2_TYPE 0x00100000 /* DDR2 Memory Type */
+#define SDRAM_MCOPT1_QDEP 0x00020000 /* 4 commands deep */
+#define SDRAM_MCOPT1_RWOO_MASK 0x00008000 /* Out of Order Read mask */
+#define SDRAM_MCOPT1_RWOO_DISABLED 0x00000000 /* disabled */
+#define SDRAM_MCOPT1_RWOO_ENABLED 0x00008000 /* enabled */
+#define SDRAM_MCOPT1_WOOO_MASK 0x00004000 /* Out of Order Write mask */
+#define SDRAM_MCOPT1_WOOO_DISABLED 0x00000000 /* disabled */
+#define SDRAM_MCOPT1_WOOO_ENABLED 0x00004000 /* enabled */
+#define SDRAM_MCOPT1_DCOO_MASK 0x00002000 /* All Out of Order mask */
+#define SDRAM_MCOPT1_DCOO_DISABLED 0x00002000 /* disabled */
+#define SDRAM_MCOPT1_DCOO_ENABLED 0x00000000 /* enabled */
+#define SDRAM_MCOPT1_DREF_MASK 0x00001000 /* Deferred refresh mask */
+#define SDRAM_MCOPT1_DREF_NORMAL 0x00000000 /* normal refresh */
+#define SDRAM_MCOPT1_DREF_DEFER_4 0x00001000 /* defer up to 4 refresh cmd */
+
+/*-----------------------------------------------------------------------------+
+| Memory Controller Options 2
++-----------------------------------------------------------------------------*/
+#define SDRAM_MCOPT2_SREN_MASK 0x80000000 /* Self Test mask */
+#define SDRAM_MCOPT2_SREN_EXIT 0x00000000 /* Self Test exit */
+#define SDRAM_MCOPT2_SREN_ENTER 0x80000000 /* Self Test enter */
+#define SDRAM_MCOPT2_PMEN_MASK 0x40000000 /* Power Management mask */
+#define SDRAM_MCOPT2_PMEN_DISABLE 0x00000000 /* disable */
+#define SDRAM_MCOPT2_PMEN_ENABLE 0x40000000 /* enable */
+#define SDRAM_MCOPT2_IPTR_MASK 0x20000000 /* Init Trigger Reg mask */
+#define SDRAM_MCOPT2_IPTR_IDLE 0x00000000 /* idle */
+#define SDRAM_MCOPT2_IPTR_EXECUTE 0x20000000 /* execute preloaded init */
+#define SDRAM_MCOPT2_XSRP_MASK 0x10000000 /* Exit Self Refresh Prevent */
+#define SDRAM_MCOPT2_XSRP_ALLOW 0x00000000 /* allow self refresh exit */
+#define SDRAM_MCOPT2_XSRP_PREVENT 0x10000000 /* prevent self refresh exit */
+#define SDRAM_MCOPT2_DCEN_MASK 0x08000000 /* SDRAM Controller Enable */
+#define SDRAM_MCOPT2_DCEN_DISABLE 0x00000000 /* SDRAM Controller Enable */
+#define SDRAM_MCOPT2_DCEN_ENABLE 0x08000000 /* SDRAM Controller Enable */
+#define SDRAM_MCOPT2_ISIE_MASK 0x04000000 /* Init Seq Interruptable mas*/
+#define SDRAM_MCOPT2_ISIE_DISABLE 0x00000000 /* disable */
+#define SDRAM_MCOPT2_ISIE_ENABLE 0x04000000 /* enable */
+
+/*-----------------------------------------------------------------------------+
+| SDRAM Refresh Timer Register
++-----------------------------------------------------------------------------*/
+#define SDRAM_RTR_RINT_MASK 0xFFF80000
+#define SDRAM_RTR_RINT_ENCODE(n) ((((unsigned long)(n))&0xFFF8)<<16)
+#define SDRAM_RTR_RINT_DECODE(n) ((((unsigned long)(n))>>16)&0xFFF8)
+
+/*-----------------------------------------------------------------------------+
+| SDRAM Read DQS Delay Control Register
++-----------------------------------------------------------------------------*/
+#define SDRAM_RQDC_RQDE_MASK 0x80000000
+#define SDRAM_RQDC_RQDE_DISABLE 0x00000000
+#define SDRAM_RQDC_RQDE_ENABLE 0x80000000
+#define SDRAM_RQDC_RQFD_MASK 0x000001FF
+#define SDRAM_RQDC_RQFD_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0)
+
+#define SDRAM_RQDC_RQFD_MAX 0xFF
+
+/*-----------------------------------------------------------------------------+
+| SDRAM Read Data Capture Control Register
++-----------------------------------------------------------------------------*/
+#define SDRAM_RDCC_RDSS_MASK 0xC0000000
+#define SDRAM_RDCC_RDSS_T1 0x00000000
+#define SDRAM_RDCC_RDSS_T2 0x40000000
+#define SDRAM_RDCC_RDSS_T3 0x80000000
+#define SDRAM_RDCC_RDSS_T4 0xC0000000
+#define SDRAM_RDCC_RSAE_MASK 0x00000001
+#define SDRAM_RDCC_RSAE_DISABLE 0x00000001
+#define SDRAM_RDCC_RSAE_ENABLE 0x00000000
+
+/*-----------------------------------------------------------------------------+
+| SDRAM Read Feedback Delay Control Register
++-----------------------------------------------------------------------------*/
+#define SDRAM_RFDC_ARSE_MASK 0x80000000
+#define SDRAM_RFDC_ARSE_DISABLE 0x80000000
+#define SDRAM_RFDC_ARSE_ENABLE 0x00000000
+#define SDRAM_RFDC_RFOS_MASK 0x007F0000
+#define SDRAM_RFDC_RFOS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
+#define SDRAM_RFDC_RFFD_MASK 0x000003FF
+#define SDRAM_RFDC_RFFD_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
+
+#define SDRAM_RFDC_RFFD_MAX 0x4FF
+
+/*-----------------------------------------------------------------------------+
+| SDRAM Delay Line Calibration Register
++-----------------------------------------------------------------------------*/
+#define SDRAM_DLCR_DCLM_MASK 0x80000000
+#define SDRAM_DLCR_DCLM_MANUEL 0x80000000
+#define SDRAM_DLCR_DCLM_AUTO 0x00000000
+#define SDRAM_DLCR_DLCR_MASK 0x08000000
+#define SDRAM_DLCR_DLCR_CALIBRATE 0x08000000
+#define SDRAM_DLCR_DLCR_IDLE 0x00000000
+#define SDRAM_DLCR_DLCS_MASK 0x07000000
+#define SDRAM_DLCR_DLCS_NOT_RUN 0x00000000
+#define SDRAM_DLCR_DLCS_IN_PROGRESS 0x01000000
+#define SDRAM_DLCR_DLCS_COMPLETE 0x02000000
+#define SDRAM_DLCR_DLCS_CONT_DONE 0x03000000
+#define SDRAM_DLCR_DLCS_ERROR 0x04000000
+#define SDRAM_DLCR_DLCV_MASK 0x000001FF
+#define SDRAM_DLCR_DLCV_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0)
+#define SDRAM_DLCR_DLCV_DECODE(n) ((((unsigned long)(n))>>0)&0x1FF)
+
+/*-----------------------------------------------------------------------------+
+| SDRAM Controller On Die Termination Register
++-----------------------------------------------------------------------------*/
+#define SDRAM_CODT_ODT_ON 0x80000000
+#define SDRAM_CODT_ODT_OFF 0x00000000
+#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK 0x00000020
+#define SDRAM_CODT_DQS_2_5_V_DDR1 0x00000000
+#define SDRAM_CODT_DQS_1_8_V_DDR2 0x00000020
+#define SDRAM_CODT_DQS_MASK 0x00000010
+#define SDRAM_CODT_DQS_DIFFERENTIAL 0x00000000
+#define SDRAM_CODT_DQS_SINGLE_END 0x00000010
+#define SDRAM_CODT_CKSE_DIFFERENTIAL 0x00000000
+#define SDRAM_CODT_CKSE_SINGLE_END 0x00000008
+#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004
+#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002
+#define SDRAM_CODT_IO_HIZ 0x00000000
+#define SDRAM_CODT_IO_NMODE 0x00000001
+
+/*-----------------------------------------------------------------------------+
+| SDRAM Mode Register
++-----------------------------------------------------------------------------*/
+#define SDRAM_MMODE_WR_MASK 0x00000E00
+#define SDRAM_MMODE_WR_DDR1 0x00000000
+#define SDRAM_MMODE_WR_DDR2_3_CYC 0x00000400
+#define SDRAM_MMODE_WR_DDR2_4_CYC 0x00000600
+#define SDRAM_MMODE_WR_DDR2_5_CYC 0x00000800
+#define SDRAM_MMODE_WR_DDR2_6_CYC 0x00000A00
+#define SDRAM_MMODE_DCL_MASK 0x00000070
+#define SDRAM_MMODE_DCL_DDR1_2_0_CLK 0x00000020
+#define SDRAM_MMODE_DCL_DDR1_2_5_CLK 0x00000060
+#define SDRAM_MMODE_DCL_DDR1_3_0_CLK 0x00000030
+#define SDRAM_MMODE_DCL_DDR2_2_0_CLK 0x00000020
+#define SDRAM_MMODE_DCL_DDR2_3_0_CLK 0x00000030
+#define SDRAM_MMODE_DCL_DDR2_4_0_CLK 0x00000040
+#define SDRAM_MMODE_DCL_DDR2_5_0_CLK 0x00000050
+#define SDRAM_MMODE_DCL_DDR2_6_0_CLK 0x00000060
+#define SDRAM_MMODE_DCL_DDR2_7_0_CLK 0x00000070
+
+/*-----------------------------------------------------------------------------+
+| SDRAM Extended Mode Register
++-----------------------------------------------------------------------------*/
+#define SDRAM_MEMODE_DIC_MASK 0x00000002
+#define SDRAM_MEMODE_DIC_NORMAL 0x00000000
+#define SDRAM_MEMODE_DIC_WEAK 0x00000002
+#define SDRAM_MEMODE_DLL_MASK 0x00000001
+#define SDRAM_MEMODE_DLL_DISABLE 0x00000001
+#define SDRAM_MEMODE_DLL_ENABLE 0x00000000
+#define SDRAM_MEMODE_RTT_MASK 0x00000044
+#define SDRAM_MEMODE_RTT_DISABLED 0x00000000
+#define SDRAM_MEMODE_RTT_75OHM 0x00000004
+#define SDRAM_MEMODE_RTT_150OHM 0x00000040
+#define SDRAM_MEMODE_DQS_MASK 0x00000400
+#define SDRAM_MEMODE_DQS_DISABLE 0x00000400
+#define SDRAM_MEMODE_DQS_ENABLE 0x00000000
+
+/*-----------------------------------------------------------------------------+
+| SDRAM Clock Timing Register
++-----------------------------------------------------------------------------*/
+#define SDRAM_CLKTR_CLKP_MASK 0xC0000000
+#define SDRAM_CLKTR_CLKP_0_DEG 0x00000000
+#define SDRAM_CLKTR_CLKP_180_DEG_ADV 0x80000000
+
+/*-----------------------------------------------------------------------------+
+| SDRAM Write Timing Register
++-----------------------------------------------------------------------------*/
+#define SDRAM_WRDTR_WDTP_1_CYC 0x80000000
+#define SDRAM_WRDTR_LLWP_MASK 0x10000000
+#define SDRAM_WRDTR_LLWP_DIS 0x10000000
+#define SDRAM_WRDTR_LLWP_1_CYC 0x00000000
+#define SDRAM_WRDTR_WTR_MASK 0x0E000000
+#define SDRAM_WRDTR_WTR_0_DEG 0x06000000
+#define SDRAM_WRDTR_WTR_180_DEG_ADV 0x02000000
+#define SDRAM_WRDTR_WTR_270_DEG_ADV 0x00000000
+
+/*-----------------------------------------------------------------------------+
+| SDRAM SDTR1 Options
++-----------------------------------------------------------------------------*/
+#define SDRAM_SDTR1_LDOF_MASK 0x80000000
+#define SDRAM_SDTR1_LDOF_1_CLK 0x00000000
+#define SDRAM_SDTR1_LDOF_2_CLK 0x80000000
+#define SDRAM_SDTR1_RTW_MASK 0x00F00000
+#define SDRAM_SDTR1_RTW_2_CLK 0x00200000
+#define SDRAM_SDTR1_RTW_3_CLK 0x00300000
+#define SDRAM_SDTR1_WTWO_MASK 0x000F0000
+#define SDRAM_SDTR1_WTWO_0_CLK 0x00000000
+#define SDRAM_SDTR1_WTWO_1_CLK 0x00010000
+#define SDRAM_SDTR1_RTRO_MASK 0x0000F000
+#define SDRAM_SDTR1_RTRO_1_CLK 0x00000000
+#define SDRAM_SDTR1_RTRO_2_CLK 0x00002000
+
+/*-----------------------------------------------------------------------------+
+| SDRAM SDTR2 Options
++-----------------------------------------------------------------------------*/
+#define SDRAM_SDTR2_RCD_MASK 0xF0000000
+#define SDRAM_SDTR2_RCD_1_CLK 0x10000000
+#define SDRAM_SDTR2_RCD_2_CLK 0x20000000
+#define SDRAM_SDTR2_RCD_3_CLK 0x30000000
+#define SDRAM_SDTR2_RCD_4_CLK 0x40000000
+#define SDRAM_SDTR2_RCD_5_CLK 0x50000000
+#define SDRAM_SDTR2_WTR_MASK 0x0F000000
+#define SDRAM_SDTR2_WTR_1_CLK 0x01000000
+#define SDRAM_SDTR2_WTR_2_CLK 0x02000000
+#define SDRAM_SDTR2_WTR_3_CLK 0x03000000
+#define SDRAM_SDTR2_WTR_4_CLK 0x04000000
+#define SDRAM_SDTR3_WTR_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
+#define SDRAM_SDTR2_XSNR_MASK 0x00FF0000
+#define SDRAM_SDTR2_XSNR_8_CLK 0x00080000
+#define SDRAM_SDTR2_XSNR_16_CLK 0x00100000
+#define SDRAM_SDTR2_XSNR_32_CLK 0x00200000
+#define SDRAM_SDTR2_XSNR_64_CLK 0x00400000
+#define SDRAM_SDTR2_WPC_MASK 0x0000F000
+#define SDRAM_SDTR2_WPC_2_CLK 0x00002000
+#define SDRAM_SDTR2_WPC_3_CLK 0x00003000
+#define SDRAM_SDTR2_WPC_4_CLK 0x00004000
+#define SDRAM_SDTR2_WPC_5_CLK 0x00005000
+#define SDRAM_SDTR2_WPC_6_CLK 0x00006000
+#define SDRAM_SDTR3_WPC_ENCODE(n) ((((unsigned long)(n))&0xF)<<12)
+#define SDRAM_SDTR2_RPC_MASK 0x00000F00
+#define SDRAM_SDTR2_RPC_2_CLK 0x00000200
+#define SDRAM_SDTR2_RPC_3_CLK 0x00000300
+#define SDRAM_SDTR2_RPC_4_CLK 0x00000400
+#define SDRAM_SDTR2_RP_MASK 0x000000F0
+#define SDRAM_SDTR2_RP_3_CLK 0x00000030
+#define SDRAM_SDTR2_RP_4_CLK 0x00000040
+#define SDRAM_SDTR2_RP_5_CLK 0x00000050
+#define SDRAM_SDTR2_RP_6_CLK 0x00000060
+#define SDRAM_SDTR2_RP_7_CLK 0x00000070
+#define SDRAM_SDTR2_RRD_MASK 0x0000000F
+#define SDRAM_SDTR2_RRD_2_CLK 0x00000002
+#define SDRAM_SDTR2_RRD_3_CLK 0x00000003
+
+/*-----------------------------------------------------------------------------+
+| SDRAM SDTR3 Options
++-----------------------------------------------------------------------------*/
+#define SDRAM_SDTR3_RAS_MASK 0x1F000000
+#define SDRAM_SDTR3_RAS_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
+#define SDRAM_SDTR3_RC_MASK 0x001F0000
+#define SDRAM_SDTR3_RC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
+#define SDRAM_SDTR3_XCS_MASK 0x00001F00
+#define SDRAM_SDTR3_XCS 0x00000D00
+#define SDRAM_SDTR3_RFC_MASK 0x0000003F
+#define SDRAM_SDTR3_RFC_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0)
+
+/*-----------------------------------------------------------------------------+
+| Memory Bank 0-1 configuration
++-----------------------------------------------------------------------------*/
+#define SDRAM_BXCF_M_AM_MASK 0x00000F00 /* Addressing mode */
+#define SDRAM_BXCF_M_AM_0 0x00000000 /* Mode 0 */
+#define SDRAM_BXCF_M_AM_1 0x00000100 /* Mode 1 */
+#define SDRAM_BXCF_M_AM_2 0x00000200 /* Mode 2 */
+#define SDRAM_BXCF_M_AM_3 0x00000300 /* Mode 3 */
+#define SDRAM_BXCF_M_AM_4 0x00000400 /* Mode 4 */
+#define SDRAM_BXCF_M_AM_5 0x00000500 /* Mode 5 */
+#define SDRAM_BXCF_M_AM_6 0x00000600 /* Mode 6 */
+#define SDRAM_BXCF_M_AM_7 0x00000700 /* Mode 7 */
+#define SDRAM_BXCF_M_AM_8 0x00000800 /* Mode 8 */
+#define SDRAM_BXCF_M_AM_9 0x00000900 /* Mode 9 */
+#define SDRAM_BXCF_M_BE_MASK 0x00000001 /* Memory Bank Enable */
+#define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */
+#define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */
+
+#define sdr_uart0 0x0120 /* UART0 Config */
+#define sdr_uart1 0x0121 /* UART1 Config */
+#define sdr_mfr 0x4300 /* SDR0_MFR reg */
+
+/* Defines for CPC0_EPRCSR register */
+#define CPC0_EPRCSR_E0NFE 0x80000000
+#define CPC0_EPRCSR_E1NFE 0x40000000
+#define CPC0_EPRCSR_E1RPP 0x00000080
+#define CPC0_EPRCSR_E0RPP 0x00000040
+#define CPC0_EPRCSR_E1ERP 0x00000020
+#define CPC0_EPRCSR_E0ERP 0x00000010
+#define CPC0_EPRCSR_E1PCI 0x00000002
+#define CPC0_EPRCSR_E0PCI 0x00000001
+
+#define cpr0_clkupd 0x020
+#define cpr0_pllc 0x040
+#define cpr0_plld 0x060
+#define cpr0_cpud 0x080
+#define cpr0_plbd 0x0a0
+#define cpr0_opbd 0x0c0
+#define cpr0_perd 0x0e0
+#define cpr0_ahbd 0x100
+#define cpr0_icfg 0x140
+
+#define SDR_PINSTP 0x0040
+#define sdr_sdcs 0x0060
+
+#define SDR0_SDCS_SDD (0x80000000 >> 31)
+
+/* CUST0 Customer Configuration Register0 */
+#define SDR0_CUST0 0x4000
+#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
+#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
+#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */
+#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */
+
+#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */
+#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */
+#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */
+
+#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */
+#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */
+#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */
+
+#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */
+#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
+#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
+
+#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */
+#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22)
+#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
+
+#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */
+#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */
+#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */
+
+#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
+#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
+#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
+
+#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */
+#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4)
+#define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF)
+
+#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */
+#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */
+#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */
+#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */
+#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */
+#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */
+#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */
+
+#define SDR0_PFC0 0x4100
+#define SDR0_PFC1 0x4101
+#define SDR0_PFC1_U1ME 0x02000000
+#define SDR0_PFC1_U0ME 0x00080000
+#define SDR0_PFC1_U0IM 0x00040000
+#define SDR0_PFC1_SIS 0x00020000
+#define SDR0_PFC1_DMAAEN 0x00010000
+#define SDR0_PFC1_DMADEN 0x00008000
+#define SDR0_PFC1_USBEN 0x00004000
+#define SDR0_PFC1_AHBSWAP 0x00000020
+#define SDR0_PFC1_USBBIGEN 0x00000010
+#define SDR0_PFC1_GPT_FREQ 0x0000000f
+#endif
#endif /* __PPC405_H__ */
| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
+----------------------------------------------------------------------------*/
+/*
+ * (C) Copyright 2006
+ * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
+ * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
+ * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
#ifndef __PPC440_H__
#define __PPC440_H__
+#define CFG_DCACHE_SIZE (32 << 10) /* For AMCC 440 CPUs */
+
/*--------------------------------------------------------------------- */
/* Special Purpose Registers */
/*--------------------------------------------------------------------- */
/*-----------------------------------------------------------------------------
| Clocking Controller
+----------------------------------------------------------------------------*/
-#define CLOCKING_DCR_BASE 0x0c
-#define clkcfga (CLOCKING_DCR_BASE+0x0)
-#define clkcfgd (CLOCKING_DCR_BASE+0x1)
-
/* values for clkcfga register - indirect addressing of these regs */
#define clk_clkukpd 0x0020
#define clk_pllc 0x0040
#define clk_icfg 0x0140
/* 440gx sdr register definations */
-#define SDR_DCR_BASE 0x0e
-#define sdrcfga (SDR_DCR_BASE+0x0)
-#define sdrcfgd (SDR_DCR_BASE+0x1)
#define sdr_sdstp0 0x0020 /* */
#define sdr_sdstp1 0x0021 /* */
#define SDR_PINSTP 0x0040
#define sdr_plbtr 0x4200
#define sdr_mfr 0x4300 /* SDR0_MFR reg */
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* test-only!!!! */
-#define DDR0_00 0x00
-#define DDR0_01 0x01
-#define DDR0_02 0x02
-#define DDR0_03 0x03
-#define DDR0_04 0x04
-#define DDR0_05 0x05
-#define DDR0_06 0x06
-#define DDR0_07 0x07
-#define DDR0_08 0x08
-#define DDR0_09 0x09
-#define DDR0_10 0x0A
-#define DDR0_11 0x0B
-#define DDR0_12 0x0C
-#define DDR0_13 0x0D
-#define DDR0_14 0x0E
-#define DDR0_15 0x0F
-#define DDR0_16 0x10
-#define DDR0_17 0x11
-#define DDR0_18 0x12
-#define DDR0_19 0x13
-#define DDR0_20 0x14
-#define DDR0_21 0x15
-#define DDR0_22 0x16
-#define DDR0_23 0x17
-#define DDR0_24 0x18
-#define DDR0_25 0x19
-#define DDR0_26 0x1A
-#define DDR0_27 0x1B
-#define DDR0_28 0x1C
-#define DDR0_29 0x1D
-#define DDR0_30 0x1E
-#define DDR0_31 0x1F
-#define DDR0_32 0x20
-#define DDR0_33 0x21
-#define DDR0_34 0x22
-#define DDR0_35 0x23
-#define DDR0_36 0x24
-#define DDR0_37 0x25
-#define DDR0_38 0x26
-#define DDR0_39 0x27
-#define DDR0_40 0x28
-#define DDR0_41 0x29
-#define DDR0_42 0x2A
-#define DDR0_43 0x2B
-#define DDR0_44 0x2C
-#endif /*CONFIG_440EPX*/
-
/*-----------------------------------------------------------------------------
| SDRAM Controller
+----------------------------------------------------------------------------*/
-#define SDRAM_DCR_BASE 0x10
-#define memcfga (SDRAM_DCR_BASE+0x0) /* Memory configuration address reg */
-#define memcfgd (SDRAM_DCR_BASE+0x1) /* Memory configuration data reg */
-
/* values for memcfga register - indirect addressing of these regs */
#define mem_besr0_clr 0x0000 /* bus error status reg 0 (clr) */
#define mem_besr0_set 0x0004 /* bus error status reg 0 (set) */
#define sdr_sdstp6 0x4005
#define sdr_sdstp7 0x4007
-#define SDR0_CFGADDR 0x00E
-#define SDR0_CFGDATA 0x00F
-
/******************************************************************************
* PCI express defines
******************************************************************************/
/*----------------------------------------------------------------------------+
| Memory controller defines
+----------------------------------------------------------------------------*/
-#define SDRAMC_DCR_BASE 0x010
-#define SDRAMC_CFGADDR (SDRAMC_DCR_BASE+0x0) /* Memory configuration add */
-#define SDRAMC_CFGDATA (SDRAMC_DCR_BASE+0x1) /* Memory configuration data */
-
/* A REVOIR versus specs 4 bank - SG*/
#define SDRAM_MCSTAT 0x14 /* memory controller status */
#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */
#define SDRAM_BXCF_M_BE_MASK 0x00000001 /* Memory Bank Enable */
#define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */
#define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */
+
+#define SDR0_MFR_FIXD 0x10000000 /* Workaround for PCI/DMA */
#endif /* CONFIG_440SPE */
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+/*-----------------------------------------------------------------------------
+ | SDRAM Controller
+ +----------------------------------------------------------------------------*/
+#define DDR0_00 0x00
+#define DDR0_00_INT_ACK_MASK 0x7F000000 /* Write only */
+#define DDR0_00_INT_ACK_ALL 0x7F000000
+#define DDR0_00_INT_ACK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
+#define DDR0_00_INT_ACK_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
+/* Status */
+#define DDR0_00_INT_STATUS_MASK 0x00FF0000 /* Read only */
+/* Bit0. A single access outside the defined PHYSICAL memory space detected. */
+#define DDR0_00_INT_STATUS_BIT0 0x00010000
+/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */
+#define DDR0_00_INT_STATUS_BIT1 0x00020000
+/* Bit2. Single correctable ECC event detected */
+#define DDR0_00_INT_STATUS_BIT2 0x00040000
+/* Bit3. Multiple correctable ECC events detected. */
+#define DDR0_00_INT_STATUS_BIT3 0x00080000
+/* Bit4. Single uncorrectable ECC event detected. */
+#define DDR0_00_INT_STATUS_BIT4 0x00100000
+/* Bit5. Multiple uncorrectable ECC events detected. */
+#define DDR0_00_INT_STATUS_BIT5 0x00200000
+/* Bit6. DRAM initialization complete. */
+#define DDR0_00_INT_STATUS_BIT6 0x00400000
+/* Bit7. Logical OR of all lower bits. */
+#define DDR0_00_INT_STATUS_BIT7 0x00800000
+
+#define DDR0_00_INT_STATUS_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
+#define DDR0_00_INT_STATUS_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
+#define DDR0_00_DLL_INCREMENT_MASK 0x00007F00
+#define DDR0_00_DLL_INCREMENT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
+#define DDR0_00_DLL_INCREMENT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
+#define DDR0_00_DLL_START_POINT_MASK 0x0000007F
+#define DDR0_00_DLL_START_POINT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
+#define DDR0_00_DLL_START_POINT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
+
+#define DDR0_01 0x01
+#define DDR0_01_PLB0_DB_CS_LOWER_MASK 0x1F000000
+#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
+#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
+#define DDR0_01_PLB0_DB_CS_UPPER_MASK 0x001F0000
+#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
+#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n) ((((unsigned long)(n))>>16)&0x1F)
+#define DDR0_01_OUT_OF_RANGE_TYPE_MASK 0x00000700 /* Read only */
+#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
+#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
+#define DDR0_01_INT_MASK_MASK 0x000000FF
+#define DDR0_01_INT_MASK_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
+#define DDR0_01_INT_MASK_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
+#define DDR0_01_INT_MASK_ALL_ON 0x000000FF
+#define DDR0_01_INT_MASK_ALL_OFF 0x00000000
+
+#define DDR0_02 0x02
+#define DDR0_02_MAX_CS_REG_MASK 0x02000000 /* Read only */
+#define DDR0_02_MAX_CS_REG_ENCODE(n) ((((unsigned long)(n))&0x2)<<24)
+#define DDR0_02_MAX_CS_REG_DECODE(n) ((((unsigned long)(n))>>24)&0x2)
+#define DDR0_02_MAX_COL_REG_MASK 0x000F0000 /* Read only */
+#define DDR0_02_MAX_COL_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<16)
+#define DDR0_02_MAX_COL_REG_DECODE(n) ((((unsigned long)(n))>>16)&0xF)
+#define DDR0_02_MAX_ROW_REG_MASK 0x00000F00 /* Read only */
+#define DDR0_02_MAX_ROW_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
+#define DDR0_02_MAX_ROW_REG_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
+#define DDR0_02_START_MASK 0x00000001
+#define DDR0_02_START_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
+#define DDR0_02_START_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
+#define DDR0_02_START_OFF 0x00000000
+#define DDR0_02_START_ON 0x00000001
+
+#define DDR0_03 0x03
+#define DDR0_03_BSTLEN_MASK 0x07000000
+#define DDR0_03_BSTLEN_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
+#define DDR0_03_BSTLEN_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
+#define DDR0_03_CASLAT_MASK 0x00070000
+#define DDR0_03_CASLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
+#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
+#define DDR0_03_CASLAT_LIN_MASK 0x00000F00
+#define DDR0_03_CASLAT_LIN_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
+#define DDR0_03_CASLAT_LIN_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
+#define DDR0_03_INITAREF_MASK 0x0000000F
+#define DDR0_03_INITAREF_ENCODE(n) ((((unsigned long)(n))&0xF)<<0)
+#define DDR0_03_INITAREF_DECODE(n) ((((unsigned long)(n))>>0)&0xF)
+
+#define DDR0_04 0x04
+#define DDR0_04_TRC_MASK 0x1F000000
+#define DDR0_04_TRC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
+#define DDR0_04_TRC_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
+#define DDR0_04_TRRD_MASK 0x00070000
+#define DDR0_04_TRRD_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
+#define DDR0_04_TRRD_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
+#define DDR0_04_TRTP_MASK 0x00000700
+#define DDR0_04_TRTP_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
+#define DDR0_04_TRTP_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
+
+#define DDR0_05 0x05
+#define DDR0_05_TMRD_MASK 0x1F000000
+#define DDR0_05_TMRD_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
+#define DDR0_05_TMRD_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
+#define DDR0_05_TEMRS_MASK 0x00070000
+#define DDR0_05_TEMRS_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
+#define DDR0_05_TEMRS_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
+#define DDR0_05_TRP_MASK 0x00000F00
+#define DDR0_05_TRP_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
+#define DDR0_05_TRP_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
+#define DDR0_05_TRAS_MIN_MASK 0x000000FF
+#define DDR0_05_TRAS_MIN_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
+#define DDR0_05_TRAS_MIN_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
+
+#define DDR0_06 0x06
+#define DDR0_06_WRITEINTERP_MASK 0x01000000
+#define DDR0_06_WRITEINTERP_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
+#define DDR0_06_WRITEINTERP_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
+#define DDR0_06_TWTR_MASK 0x00070000
+#define DDR0_06_TWTR_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
+#define DDR0_06_TWTR_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
+#define DDR0_06_TDLL_MASK 0x0000FF00
+#define DDR0_06_TDLL_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
+#define DDR0_06_TDLL_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
+#define DDR0_06_TRFC_MASK 0x0000007F
+#define DDR0_06_TRFC_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
+#define DDR0_06_TRFC_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
+
+#define DDR0_07 0x07
+#define DDR0_07_NO_CMD_INIT_MASK 0x01000000
+#define DDR0_07_NO_CMD_INIT_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
+#define DDR0_07_NO_CMD_INIT_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
+#define DDR0_07_TFAW_MASK 0x001F0000
+#define DDR0_07_TFAW_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
+#define DDR0_07_TFAW_DECODE(n) ((((unsigned long)(n))>>16)&0x1F)
+#define DDR0_07_AUTO_REFRESH_MODE_MASK 0x00000100
+#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
+#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
+#define DDR0_07_AREFRESH_MASK 0x00000001
+#define DDR0_07_AREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
+#define DDR0_07_AREFRESH_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
+
+#define DDR0_08 0x08
+#define DDR0_08_WRLAT_MASK 0x07000000
+#define DDR0_08_WRLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
+#define DDR0_08_WRLAT_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
+#define DDR0_08_TCPD_MASK 0x00FF0000
+#define DDR0_08_TCPD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
+#define DDR0_08_TCPD_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
+#define DDR0_08_DQS_N_EN_MASK 0x00000100
+#define DDR0_08_DQS_N_EN_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
+#define DDR0_08_DQS_N_EN_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
+#define DDR0_08_DDRII_SDRAM_MODE_MASK 0x00000001
+#define DDR0_08_DDRII_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
+#define DDR0_08_DDRII_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
+
+#define DDR0_09 0x09
+#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK 0x1F000000
+#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
+#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
+#define DDR0_09_RTT_0_MASK 0x00030000
+#define DDR0_09_RTT_0_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
+#define DDR0_09_RTT_0_DECODE(n) ((((unsigned long)(n))>>16)&0x3)
+#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK 0x00007F00
+#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
+#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
+#define DDR0_09_WR_DQS_SHIFT_MASK 0x0000007F
+#define DDR0_09_WR_DQS_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
+#define DDR0_09_WR_DQS_SHIFT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
+
+#define DDR0_10 0x0A
+#define DDR0_10_WRITE_MODEREG_MASK 0x00010000 /* Write only */
+#define DDR0_10_WRITE_MODEREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
+#define DDR0_10_WRITE_MODEREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
+#define DDR0_10_CS_MAP_MASK 0x00000300
+#define DDR0_10_CS_MAP_NO_MEM 0x00000000
+#define DDR0_10_CS_MAP_RANK0_INSTALLED 0x00000100
+#define DDR0_10_CS_MAP_RANK1_INSTALLED 0x00000200
+#define DDR0_10_CS_MAP_ENCODE(n) ((((unsigned long)(n))&0x3)<<8)
+#define DDR0_10_CS_MAP_DECODE(n) ((((unsigned long)(n))>>8)&0x3)
+#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK 0x0000001F
+#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<0)
+#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x1F)
+
+#define DDR0_11 0x0B
+#define DDR0_11_SREFRESH_MASK 0x01000000
+#define DDR0_11_SREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
+#define DDR0_11_SREFRESH_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
+#define DDR0_11_TXSNR_MASK 0x00FF0000
+#define DDR0_11_TXSNR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
+#define DDR0_11_TXSNR_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
+#define DDR0_11_TXSR_MASK 0x0000FF00
+#define DDR0_11_TXSR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
+#define DDR0_11_TXSR_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
+
+#define DDR0_12 0x0C
+#define DDR0_12_TCKE_MASK 0x0000007
+#define DDR0_12_TCKE_ENCODE(n) ((((unsigned long)(n))&0x7)<<0)
+#define DDR0_12_TCKE_DECODE(n) ((((unsigned long)(n))>>0)&0x7)
+
+#define DDR0_14 0x0E
+#define DDR0_14_DLL_BYPASS_MODE_MASK 0x01000000
+#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
+#define DDR0_14_DLL_BYPASS_MODE_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
+#define DDR0_14_REDUC_MASK 0x00010000
+#define DDR0_14_REDUC_64BITS 0x00000000
+#define DDR0_14_REDUC_32BITS 0x00010000
+#define DDR0_14_REDUC_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
+#define DDR0_14_REDUC_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
+#define DDR0_14_REG_DIMM_ENABLE_MASK 0x00000100
+#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
+#define DDR0_14_REG_DIMM_ENABLE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
+
+#define DDR0_17 0x11
+#define DDR0_17_DLL_DQS_DELAY_0_MASK 0x7F000000
+#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
+#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
+#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */
+#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000
+#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000
+#define DDR0_17_DLLLOCKREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
+#define DDR0_17_DLLLOCKREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
+#define DDR0_17_DLL_LOCK_MASK 0x00007F00 /* Read only */
+#define DDR0_17_DLL_LOCK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
+#define DDR0_17_DLL_LOCK_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
+
+#define DDR0_18 0x12
+#define DDR0_18_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
+#define DDR0_18_DLL_DQS_DELAY_4_MASK 0x7F000000
+#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
+#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
+#define DDR0_18_DLL_DQS_DELAY_3_MASK 0x007F0000
+#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
+#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
+#define DDR0_18_DLL_DQS_DELAY_2_MASK 0x00007F00
+#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
+#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
+#define DDR0_18_DLL_DQS_DELAY_1_MASK 0x0000007F
+#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
+#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
+
+#define DDR0_19 0x13
+#define DDR0_19_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
+#define DDR0_19_DLL_DQS_DELAY_8_MASK 0x7F000000
+#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
+#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
+#define DDR0_19_DLL_DQS_DELAY_7_MASK 0x007F0000
+#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
+#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
+#define DDR0_19_DLL_DQS_DELAY_6_MASK 0x00007F00
+#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
+#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
+#define DDR0_19_DLL_DQS_DELAY_5_MASK 0x0000007F
+#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
+#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
+
+#define DDR0_20 0x14
+#define DDR0_20_DLL_DQS_BYPASS_3_MASK 0x7F000000
+#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
+#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
+#define DDR0_20_DLL_DQS_BYPASS_2_MASK 0x007F0000
+#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
+#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
+#define DDR0_20_DLL_DQS_BYPASS_1_MASK 0x00007F00
+#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
+#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
+#define DDR0_20_DLL_DQS_BYPASS_0_MASK 0x0000007F
+#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
+#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
+
+#define DDR0_21 0x15
+#define DDR0_21_DLL_DQS_BYPASS_7_MASK 0x7F000000
+#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
+#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
+#define DDR0_21_DLL_DQS_BYPASS_6_MASK 0x007F0000
+#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
+#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
+#define DDR0_21_DLL_DQS_BYPASS_5_MASK 0x00007F00
+#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
+#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
+#define DDR0_21_DLL_DQS_BYPASS_4_MASK 0x0000007F
+#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
+#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
+
+#define DDR0_22 0x16
+#define DDR0_22_CTRL_RAW_MASK 0x03000000
+#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not being used */
+#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC checking is on, but no attempts to correct */
+#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* No ECC RAM storage available */
+#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC checking and correcting on */
+#define DDR0_22_CTRL_RAW_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
+#define DDR0_22_CTRL_RAW_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
+#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000
+#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
+#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
+#define DDR0_22_DQS_OUT_SHIFT_MASK 0x00007F00
+#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
+#define DDR0_22_DQS_OUT_SHIFT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
+#define DDR0_22_DLL_DQS_BYPASS_8_MASK 0x0000007F
+#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
+#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
+
+#define DDR0_23 0x17
+#define DDR0_23_ODT_RD_MAP_CS0_MASK 0x03000000
+#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
+#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
+#define DDR0_23_ECC_C_SYND_MASK 0x00FF0000 /* Read only */
+#define DDR0_23_ECC_C_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
+#define DDR0_23_ECC_C_SYND_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
+#define DDR0_23_ECC_U_SYND_MASK 0x0000FF00 /* Read only */
+#define DDR0_23_ECC_U_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
+#define DDR0_23_ECC_U_SYND_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
+#define DDR0_23_FWC_MASK 0x00000001 /* Write only */
+#define DDR0_23_FWC_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
+#define DDR0_23_FWC_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
+
+#define DDR0_24 0x18
+#define DDR0_24_RTT_PAD_TERMINATION_MASK 0x03000000
+#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
+#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
+#define DDR0_24_ODT_WR_MAP_CS1_MASK 0x00030000
+#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
+#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>16)&0x3)
+#define DDR0_24_ODT_RD_MAP_CS1_MASK 0x00000300
+#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<8)
+#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>8)&0x3)
+#define DDR0_24_ODT_WR_MAP_CS0_MASK 0x00000003
+#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<0)
+#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>0)&0x3)
+
+#define DDR0_25 0x19
+#define DDR0_25_VERSION_MASK 0xFFFF0000 /* Read only */
+#define DDR0_25_VERSION_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
+#define DDR0_25_VERSION_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
+#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK 0x000003FF /* Read only */
+#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
+#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
+
+#define DDR0_26 0x1A
+#define DDR0_26_TRAS_MAX_MASK 0xFFFF0000
+#define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
+#define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
+#define DDR0_26_TREF_MASK 0x00003FFF
+#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0)
+#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF)
+
+#define DDR0_27 0x1B
+#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000
+#define DDR0_27_EMRS_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16)
+#define DDR0_27_EMRS_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF)
+#define DDR0_27_TINIT_MASK 0x0000FFFF
+#define DDR0_27_TINIT_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0)
+#define DDR0_27_TINIT_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF)
+
+#define DDR0_28 0x1C
+#define DDR0_28_EMRS3_DATA_MASK 0x3FFF0000
+#define DDR0_28_EMRS3_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16)
+#define DDR0_28_EMRS3_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF)
+#define DDR0_28_EMRS2_DATA_MASK 0x00003FFF
+#define DDR0_28_EMRS2_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0)
+#define DDR0_28_EMRS2_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF)
+
+#define DDR0_31 0x1F
+#define DDR0_31_XOR_CHECK_BITS_MASK 0x0000FFFF
+#define DDR0_31_XOR_CHECK_BITS_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0)
+#define DDR0_31_XOR_CHECK_BITS_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF)
+
+#define DDR0_32 0x20
+#define DDR0_32_OUT_OF_RANGE_ADDR_MASK 0xFFFFFFFF /* Read only */
+#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
+#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_33 0x21
+#define DDR0_33_OUT_OF_RANGE_ADDR_MASK 0x00000001 /* Read only */
+#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
+#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
+
+#define DDR0_34 0x22
+#define DDR0_34_ECC_U_ADDR_MASK 0xFFFFFFFF /* Read only */
+#define DDR0_34_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
+#define DDR0_34_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_35 0x23
+#define DDR0_35_ECC_U_ADDR_MASK 0x00000001 /* Read only */
+#define DDR0_35_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
+#define DDR0_35_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
+
+#define DDR0_36 0x24
+#define DDR0_36_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
+#define DDR0_36_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
+#define DDR0_36_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_37 0x25
+#define DDR0_37_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
+#define DDR0_37_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
+#define DDR0_37_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_38 0x26
+#define DDR0_38_ECC_C_ADDR_MASK 0xFFFFFFFF /* Read only */
+#define DDR0_38_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
+#define DDR0_38_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_39 0x27
+#define DDR0_39_ECC_C_ADDR_MASK 0x00000001 /* Read only */
+#define DDR0_39_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
+#define DDR0_39_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
+
+#define DDR0_40 0x28
+#define DDR0_40_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
+#define DDR0_40_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
+#define DDR0_40_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_41 0x29
+#define DDR0_41_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
+#define DDR0_41_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
+#define DDR0_41_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_42 0x2A
+#define DDR0_42_ADDR_PINS_MASK 0x07000000
+#define DDR0_42_ADDR_PINS_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
+#define DDR0_42_ADDR_PINS_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
+#define DDR0_42_CASLAT_LIN_GATE_MASK 0x0000000F
+#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n) ((((unsigned long)(n))&0xF)<<0)
+#define DDR0_42_CASLAT_LIN_GATE_DECODE(n) ((((unsigned long)(n))>>0)&0xF)
+
+#define DDR0_43 0x2B
+#define DDR0_43_TWR_MASK 0x07000000
+#define DDR0_43_TWR_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
+#define DDR0_43_TWR_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
+#define DDR0_43_APREBIT_MASK 0x000F0000
+#define DDR0_43_APREBIT_ENCODE(n) ((((unsigned long)(n))&0xF)<<16)
+#define DDR0_43_APREBIT_DECODE(n) ((((unsigned long)(n))>>16)&0xF)
+#define DDR0_43_COLUMN_SIZE_MASK 0x00000700
+#define DDR0_43_COLUMN_SIZE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
+#define DDR0_43_COLUMN_SIZE_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
+#define DDR0_43_EIGHT_BANK_MODE_MASK 0x00000001
+#define DDR0_43_EIGHT_BANK_MODE_8_BANKS 0x00000001
+#define DDR0_43_EIGHT_BANK_MODE_4_BANKS 0x00000000
+#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
+#define DDR0_43_EIGHT_BANK_MODE_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
+
+#define DDR0_44 0x2C
+#define DDR0_44_TRCD_MASK 0x000000FF
+#define DDR0_44_TRCD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
+#define DDR0_44_TRCD_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
+
+#endif /* CONFIG_440EPX */
+
/*-----------------------------------------------------------------------------
| External Bus Controller
+----------------------------------------------------------------------------*/
-#define EBC_DCR_BASE 0x12
-#define ebccfga (EBC_DCR_BASE+0x0) /* External bus controller addr reg */
-#define ebccfgd (EBC_DCR_BASE+0x1) /* External bus controller data reg */
/* values for ebccfga register - indirect addressing of these regs */
#define pb0cr 0x00 /* periph bank 0 config reg */
#define pb1cr 0x01 /* periph bank 1 config reg */
#define SDR0_CP440_NTO1_NTO1 0x00000002
#define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1)
#define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01)
-#define SDR0_CFGADDR 0x00E /*already defined line 277 */
-#define SDR0_CFGDATA 0x00F
-
#define SDR0_SDSTP0 0x0020
#define SDR0_SDSTP0_ENG_MASK 0x80000000
/******************************************************************************
* GPIO macro register defines
******************************************************************************/
-#define GPIO0 0
-#define GPIO1 1
-
#if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000700)
#define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000B00)
#define GPIO1_BASE (CFG_PERIPHERAL_BASE+0x00000C00)
-/* Offsets */
-#define GPIOx_OR 0x00 /* GPIO Output Register */
-#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */
-#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */
-#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */
-#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */
-#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */
-#define GPIOx_ODR 0x18 /* GPIO Open drain Register */
-#define GPIOx_IR 0x1C /* GPIO Input Register */
-#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */
-#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */
-#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */
-#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */
-#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */
-#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */
-#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */
-#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */
-#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */
-
-#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Register High or Low */
-#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */
-#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */
-#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */
-#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */
-
#define GPIO0_OR (GPIO0_BASE+0x0)
#define GPIO0_TCR (GPIO0_BASE+0x4)
#define GPIO0_OSRL (GPIO0_BASE+0x8)
#define GPIO1_ISR3H (GPIO1_BASE+0x44)
#endif
-/*
- * Macros for accessing the indirect EBC registers
- */
-#define mtebc(reg, data) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,data); } while (0)
-#define mfebc(reg, data) do { mtdcr(ebccfga,reg);data = mfdcr(ebccfgd); } while (0)
-
-/*
- * Macros for accessing the indirect SDRAM controller registers
- */
-#define mtsdram(reg, data) do { mtdcr(memcfga,reg);mtdcr(memcfgd,data); } while (0)
-#define mfsdram(reg, data) do { mtdcr(memcfga,reg);data = mfdcr(memcfgd); } while (0)
-
-/*
- * Macros for accessing the indirect clocking controller registers
- */
-#define mtclk(reg, data) do { mtdcr(clkcfga,reg);mtdcr(clkcfgd,data); } while (0)
-#define mfclk(reg, data) do { mtdcr(clkcfga,reg);data = mfdcr(clkcfgd); } while (0)
-
-/*
- * Macros for accessing the sdr controller registers
- */
-#define mtsdr(reg, data) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); } while (0)
-#define mfsdr(reg, data) do { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); } while (0)
-
-/*
- * All 44x except 440GP have CPR registers (indirect DCR)
- */
-#if !defined(CONFIG_440GP)
-#define CPR0_CFGADDR 0x00C
-#define CPR0_CFGDATA 0x00D
-
-#define mtcpr(reg, data) do { \
- mtdcr(CPR0_CFGADDR, reg); \
- mtdcr(CPR0_CFGDATA, data); \
- } while (0)
-
-#define mfcpr(reg, data) do { \
- mtdcr(CPR0_CFGADDR, reg); \
- data = mfdcr(CPR0_CFGDATA); \
- } while (0)
-#endif
-
#ifndef __ASSEMBLY__
-typedef struct {
- unsigned long pllFwdDivA;
- unsigned long pllFwdDivB;
- unsigned long pllFbkDiv;
- unsigned long pllOpbDiv;
- unsigned long pllPciDiv;
- unsigned long pllExtBusDiv;
- unsigned long freqVCOMhz; /* in MHz */
- unsigned long freqProcessor;
- unsigned long freqTmrClk;
- unsigned long freqPLB;
- unsigned long freqOPB;
- unsigned long freqEPB;
- unsigned long freqPCI;
-#ifdef CONFIG_440SPE
- unsigned long freqDDR;
-#endif
- unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */
- unsigned long pciClkSync; /* PCI clock is synchronous */
-} PPC440_SYS_INFO;
-
static inline u32 get_mcsr(void)
{
u32 val;
#endif /* _ASMLANGUAGE */
-#define RESET_VECTOR 0xfffffffc
-#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for */
- /* cache line aligned data. */
-
#endif /* __PPC440_H__ */
#ifndef __PPC4XX_H__
#define __PPC4XX_H__
-#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
-#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000)
-
#if defined(CONFIG_440)
#include <ppc440.h>
#else
#include <ppc405.h>
#endif
+/*
+ * Common stuff for 4xx (405 and 440)
+ */
+
+#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
+#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000)
+
+#define RESET_VECTOR 0xfffffffc
+#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache
+ line aligned data. */
+
+#define CPR0_DCR_BASE 0x0C
+#define cprcfga (CPR0_DCR_BASE+0x0)
+#define cprcfgd (CPR0_DCR_BASE+0x1)
+
+#define SDR_DCR_BASE 0x0E
+#define sdrcfga (SDR_DCR_BASE+0x0)
+#define sdrcfgd (SDR_DCR_BASE+0x1)
+
+#define SDRAM_DCR_BASE 0x10
+#define memcfga (SDRAM_DCR_BASE+0x0)
+#define memcfgd (SDRAM_DCR_BASE+0x1)
+
+#define EBC_DCR_BASE 0x12
+#define ebccfga (EBC_DCR_BASE+0x0)
+#define ebccfgd (EBC_DCR_BASE+0x1)
+
+/*
+ * Macros for indirect DCR access
+ */
+#define mtcpr(reg, d) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0)
+#define mfcpr(reg, d) do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0)
+
+#define mtebc(reg, d) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0)
+#define mfebc(reg, d) do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0)
+
+#define mtsdram(reg, d) do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0)
+#define mfsdram(reg, d) do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0)
+
+#define mtsdr(reg, d) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0)
+#define mfsdr(reg, d) do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0)
+
+#ifndef __ASSEMBLY__
+
+typedef struct
+{
+ unsigned long freqDDR;
+ unsigned long freqEBC;
+ unsigned long freqOPB;
+ unsigned long freqPCI;
+ unsigned long freqPLB;
+ unsigned long freqTmrClk;
+ unsigned long freqUART;
+ unsigned long freqProcessor;
+ unsigned long freqVCOHz;
+ unsigned long freqVCOMhz; /* in MHz */
+ unsigned long pciClkSync; /* PCI clock is synchronous */
+ unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */
+ unsigned long pllExtBusDiv;
+ unsigned long pllFbkDiv;
+ unsigned long pllFwdDiv;
+ unsigned long pllFwdDivA;
+ unsigned long pllFwdDivB;
+ unsigned long pllOpbDiv;
+ unsigned long pllPciDiv;
+ unsigned long pllPlbDiv;
+} PPC4xx_SYS_INFO;
+
+#endif /* __ASSEMBLY__ */
+
#endif /* __PPC4XX_H__ */
uint32_t emac_ier;
volatile mal_desc_t *tx;
volatile mal_desc_t *rx;
+ u32 tx_phys;
+ u32 rx_phys;
bd_t *bis; /* for eth_init upon mal error */
mal_desc_t *alloc_tx_buf;
mal_desc_t *alloc_rx_buf;
#endif
#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_405EX)
#define SDR0_PFC1_EM_1000 (0x00200000)
#endif
-/*ZMII Bridge Register addresses */
+/* ZMII Bridge Register addresses */
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00)
/* RGMII Register Addresses */
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define RGMII_BASE (CFG_PERIPHERAL_BASE + 0x1000)
+#elif defined(CONFIG_405EX)
+#define RGMII_BASE (CFG_PERIPHERAL_BASE + 0xB00)
#else
#define RGMII_BASE (CFG_PERIPHERAL_BASE + 0x0790)
#endif
#define RGMII_SSR_SP_100MBPS (0x02)
#define RGMII_SSR_SP_1000MBPS (0x04)
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_405EX)
#define RGMII_SSR_V(__x) ((__x) * 8)
#else
#define RGMII_SSR_V(__x) ((__x -2) * 8)
#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800)
#endif
#else
-#if defined(CONFIG_405EZ)
+#if defined(CONFIG_405EZ) || defined(CONFIG_405EX)
#define EMAC_BASE 0xEF600900
#else
#define EMAC_BASE 0xEF600800
/* on 440GX EMAC_MR1 has a different layout! */
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_405EX)
/* MODE Reg 1 */
#define EMAC_M1_FDE (0x80000000)
#define EMAC_M1_ILE (0x40000000)
extern struct serial_device serial_scc_device;
extern struct serial_device * default_serial_console (void);
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
- || defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_MPC5xxx)
+#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || \
+ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \
+ defined(CONFIG_MPC5xxx)
extern struct serial_device serial0_device;
extern struct serial_device serial1_device;
#if defined(CFG_NS16550_SERIAL)
dma_alloc_init();
board_init_info();
+ enable_interrupts();
+
bd->bi_flashstart = 0;
bd->bi_flashsize = 0;
bd->bi_flashoffset = 0;
sr = sysreg_read(SR);
asm volatile("ssrf %0" : : "n"(SYSREG_GM_OFFSET));
- return SYSREG_BFEXT(GM, sr);
+ return !SYSREG_BFEXT(GM, sr);
}
*/
#include <common.h>
-
+#include <asm/cache.h>
void flush_cache (ulong start_addr, ulong size)
{
--- /dev/null
+#
+# Copyright (c) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(ARCH).a
+
+SOBJS =
+
+COBJS = board.o sh_linux.o # time.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <devices.h>
+#include <version.h>
+#include <net.h>
+#include <environment.h>
+
+extern void malloc_bin_reloc (void);
+extern int cpu_init(void);
+extern int board_init(void);
+extern int dram_init(void);
+extern int watchdog_init(void);
+extern int timer_init(void);
+
+const char version_string[] = U_BOOT_VERSION" (" __DATE__ " - " __TIME__ ")";
+
+unsigned long monitor_flash_len = CFG_MONITOR_LEN;
+
+static unsigned long mem_malloc_start;
+static unsigned long mem_malloc_end;
+static unsigned long mem_malloc_brk;
+
+static void mem_malloc_init (void)
+{
+
+ mem_malloc_start = (TEXT_BASE - CFG_GBL_DATA_SIZE - CFG_MALLOC_LEN);
+ mem_malloc_end = (mem_malloc_start + CFG_MALLOC_LEN - 16);
+ mem_malloc_brk = mem_malloc_start;
+ memset ((void *) mem_malloc_start, 0,
+ (mem_malloc_end - mem_malloc_start));
+}
+
+void *sbrk (ptrdiff_t increment)
+{
+ unsigned long old = mem_malloc_brk;
+ unsigned long new = old + increment;
+
+ if ((new < mem_malloc_start) ||
+ (new > mem_malloc_end)) {
+ return NULL;
+ }
+
+ mem_malloc_brk = new;
+ return (void *) old;
+}
+
+static int sh_flash_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_flashsize = flash_init();
+ printf("FLASH: %dMB\n", gd->bd->bi_flashsize / (1024*1024));
+
+ return 0;
+}
+
+#if defined(CONFIG_CMD_NAND)
+void nand_init (void);
+static int sh_nand_init(void)
+{
+ printf("NAND: ");
+ nand_init(); /* go init the NAND */
+ return 0;
+}
+#endif /* CONFIG_CMD_NAND */
+
+#if defined(CONFIG_CMD_IDE)
+#include <ide.h>
+static int sh_marubun_init(void)
+{
+ puts ("IDE: ");
+ ide_init();
+ return 0;
+}
+#endif /* (CONFIG_CMD_IDE) */
+
+static int sh_mem_env_init(void)
+{
+ mem_malloc_init();
+ malloc_bin_reloc();
+ env_relocate();
+ jumptable_init();
+ return 0;
+}
+
+static int sh_net_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ char *s, *e;
+ int i;
+
+ gd->bd->bi_ip_addr = getenv_IPaddr("ipaddr");
+ s = getenv("ethaddr");
+ for (i = 0; i < 6; ++i) {
+ gd->bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0;
+ if (s) s = (*e) ? e + 1 : e;
+ }
+
+ return 0;
+}
+
+typedef int (init_fnc_t) (void);
+
+init_fnc_t *init_sequence[] =
+{
+ cpu_init, /* basic cpu dependent setup */
+ board_init, /* basic board dependent setup */
+ interrupt_init, /* set up exceptions */
+ env_init, /* event init */
+ serial_init, /* SCIF init */
+ watchdog_init, /* watchdog init */
+ console_init_f,
+ display_options,
+ checkcpu,
+ checkboard, /* Check support board */
+ dram_init, /* SDRAM init */
+ timer_init, /* SuperH Timer (TCNT0 only) init */
+ sh_flash_init, /* Flash memory(NOR) init*/
+ sh_mem_env_init,
+#if defined(CONFIG_CMD_NAND)
+ sh_nand_init, /* Flash memory (NAND) init */
+#endif
+ devices_init,
+ console_init_r,
+ interrupt_init,
+#ifdef BOARD_LATE_INIT
+ board_late_init,
+#endif
+#if defined(CONFIG_CMD_NET)
+ sh_net_init, /* SH specific eth init */
+#endif
+ NULL /* Terminate this list */
+};
+
+void sh_generic_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ bd_t *bd;
+ init_fnc_t **init_fnc_ptr;
+ char *s;
+ int i;
+
+ memset (gd, 0, CFG_GBL_DATA_SIZE);
+
+ gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
+
+ gd->bd = (bd_t *) (gd + 1); /* At end of global data */
+ gd->baudrate = CONFIG_BAUDRATE;
+
+ gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
+
+ bd = gd->bd;
+ bd->bi_memstart = CFG_SDRAM_BASE;
+ bd->bi_memsize = CFG_SDRAM_SIZE;
+ bd->bi_flashstart = CFG_FLASH_BASE;
+#if defined(CFG_SRAM_BASE) && defined(CFG_SRAM_SIZE)
+ bd->bi_sramstart= CFG_SRAM_BASE;
+ bd->bi_sramsize = CFG_SRAM_SIZE;
+#endif
+ bd->bi_baudrate = CONFIG_BAUDRATE;
+
+ for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr , i++) {
+ if ((*init_fnc_ptr) () != 0) {
+ hang();
+ }
+ }
+
+#if defined(CONFIG_CMD_NET)
+ puts ("Net: ");
+ eth_initialize(gd->bd);
+
+ if ((s = getenv ("bootfile")) != NULL) {
+ copy_filename (BootFile, s, sizeof (BootFile));
+ }
+#endif /* CONFIG_CMD_NET */
+
+ while (1) {
+ main_loop();
+ }
+}
+
+/***********************************************************************/
+
+void hang (void)
+{
+ puts ("Board ERROR\n");
+ for (;;);
+}
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/byteorder.h>
+
+extern image_header_t header; /* common/cmd_bootm.c */
+
+/* The SH kernel reads arguments from the empty zero page at location
+ * 0 at the start of SDRAM. The following are copied from
+ * arch/sh/kernel/setup.c and may require tweaking if the kernel sources
+ * change.
+ */
+#define PARAM ((unsigned char *)CFG_SDRAM_BASE + 0x1000)
+
+#define MOUNT_ROOT_RDONLY (*(unsigned long *) (PARAM+0x000))
+#define RAMDISK_FLAGS (*(unsigned long *) (PARAM+0x004))
+#define ORIG_ROOT_DEV (*(unsigned long *) (PARAM+0x008))
+#define LOADER_TYPE (*(unsigned long *) (PARAM+0x00c))
+#define INITRD_START (*(unsigned long *) (PARAM+0x010))
+#define INITRD_SIZE (*(unsigned long *) (PARAM+0x014))
+/* ... */
+#define COMMAND_LINE ((char *) (PARAM+0x100))
+
+#define RAMDISK_IMAGE_START_MASK 0x07FF
+
+#ifdef CFG_DEBUG
+static void hexdump (unsigned char *buf, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++) {
+ if ((i % 16) == 0)
+ printf ("%s%08x: ", i ? "\n" : "", (unsigned int) &buf[i]);
+ printf ("%02x ", buf[i]);
+ }
+ printf ("\n");
+}
+#endif
+
+void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
+ ulong addr, ulong *len_ptr, int verify)
+{
+ image_header_t *hdr = &header;
+ char *bootargs = getenv("bootargs");
+ void (*kernel) (void) = (void (*)(void)) ntohl (hdr->ih_ep);
+
+ /* Setup parameters */
+ memset(PARAM, 0, 0x1000); /* Clear zero page */
+ strcpy(COMMAND_LINE, bootargs);
+
+ kernel();
+}
--- /dev/null
+/*
+ * Copyright (c) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processer.h>
+
+static void tmu_timer_start (unsigned int timer)
+{
+ if (timer > 2)
+ return;
+
+ *((volatile unsigned char *) TSTR0) |= (1 << timer);
+}
+
+int timer_init (void)
+{
+ *(volatile u16 *)TCR0 = 0;
+
+ tmu_timer_start (0);
+ return 0;
+}
+
+unsigned long long get_ticks (void)
+{
+ return (0 - *((volatile unsigned int *) TCNT0));
+}
+
+unsigned long get_timer (unsigned long base)
+{
+ return ((0 - *((volatile unsigned int *) TCNT0)) - base);
+}
+
+void set_timer (unsigned long t)
+{
+ *((volatile unsigned int *) TCNT0) = (0 - t);
+}
+
+void reset_timer (void)
+{
+ set_timer (0);
+}
+
+void udelay (unsigned long usec)
+{
+ unsigned int start = get_timer (0);
+ unsigned int end = start + (usec * ((CFG_HZ + 500000) / 1000000));
+
+ while (get_timer (0) < end)
+ continue;
+}
+
+unsigned long get_tbclk (void)
+{
+ return CFG_HZ;
+}
AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL
-SOBJS = start.o resetvec.o
+SOBJS = start.o resetvec.o cache.o
COBJS = gpio.o nand_boot.o nand_ecc.o memory.o ndfc.o pll.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
# create symbolic links for common files
# from cpu directory
+$(obj)cache.S:
+ @rm -f $(obj)cache.S
+ ln -s $(SRCTREE)/cpu/ppc4xx/cache.S $(obj)cache.S
+
$(obj)gpio.c:
@rm -f $(obj)gpio.c
ln -s $(SRCTREE)/cpu/ppc4xx/gpio.c $(obj)gpio.c
* not enough free space to implement the complete I2C SPD DDR autodetection
* routines. Therefore the Bamboo only supports the onboard 64MBytes of SDRAM
* when booting from NAND flash.
+ *
+ * Note:
+ * As found out by Eugene O'Brien <eugene.obrien@advantechamt.com>, the fixed
+ * DDR setup has problems (U-Boot crashes randomly upon TFTP), when the DIMM
+ * modules are still plugged in. So it is recommended to remove the DIMM
+ * modules while using the NAND booting code with the fixed SDRAM setup!
*/
void early_sdram_init(void)
{
--- /dev/null
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
+
+LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
+LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+AFLAGS += -DCONFIG_NAND_SPL
+CFLAGS += -DCONFIG_NAND_SPL
+
+SOBJS = start.o init.o resetvec.o cache.o
+COBJS = memory.o nand_boot.o nand_ecc.o ndfc.o
+
+SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS := $(SOBJS) $(COBJS)
+LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
+
+nandobj := $(OBJTREE)/nand_spl/
+
+ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
+
+all: $(obj).depend $(ALL)
+
+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+
+$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
+ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(nandobj)u-boot-spl: $(OBJS)
+ cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
+ -Map $(nandobj)u-boot-spl.map \
+ -o $(nandobj)u-boot-spl
+
+# create symbolic links for common files
+
+# from cpu directory
+$(obj)cache.S:
+ @rm -f $(obj)cache.S
+ ln -s $(SRCTREE)/cpu/ppc4xx/cache.S $(obj)cache.S
+
+$(obj)ndfc.c:
+ @rm -f $(obj)ndfc.c
+ ln -s $(SRCTREE)/cpu/ppc4xx/ndfc.c $(obj)ndfc.c
+
+$(obj)resetvec.S:
+ @rm -f $(obj)resetvec.S
+ ln -s $(SRCTREE)/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
+
+$(obj)start.S:
+ @rm -f $(obj)start.S
+ ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S
+
+# from board directory
+$(obj)init.S:
+ @rm -f $(obj)init.S
+ ln -s $(SRCTREE)/board/amcc/kilauea/init.S $(obj)init.S
+
+$(obj)memory.c:
+ @rm -f $(obj)memory.c
+ ln -s $(SRCTREE)/board/amcc/kilauea/memory.c $(obj)memory.c
+
+# from nand_spl directory
+$(obj)nand_boot.c:
+ @rm -f $(obj)nand_boot.c
+ ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c
+
+# from drivers/nand directory
+$(obj)nand_ecc.c:
+ @rm -f $(obj)nand_ecc.c
+ ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c
+
+#########################################################################
+
+$(obj)%.o: $(obj)%.S
+ $(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o: $(obj)%.c
+ $(CC) $(CFLAGS) -c -o $@ $<
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+# AMCC 405EX Reference Platform (Kilauea) board
+#
+
+#
+# TEXT_BASE for SPL:
+#
+# On 4xx platforms the SPL is located at 0xfffff000...0xffffffff,
+# in the last 4kBytes of memory space in cache.
+# We will copy this SPL into instruction-cache in start.S. So we set
+# TEXT_BASE to starting address in i-cache here.
+#
+TEXT_BASE = 0x00800000
+
+# PAD_TO used to generate a 16kByte binary needed for the combined image
+# -> PAD_TO = TEXT_BASE + 0x4000
+PAD_TO = 0x00804000
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc:common)
+SECTIONS
+{
+ .resetvec 0x00800FFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .text :
+ {
+ start.o (.text)
+ init.o (.text)
+ nand_boot.o (.text)
+ ndfc.o (.text)
+
+ *(.text)
+ *(.fixup)
+ }
+ _etext = .;
+
+ .data :
+ {
+ *(.rodata*)
+ *(.data*)
+ *(.sdata*)
+ __got2_start = .;
+ *(.got2)
+ __got2_end = .;
+ }
+
+ _edata = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss)
+ *(.bss)
+ }
+
+ _end = . ;
+}
+++ /dev/null
-#
-# (C) Copyright 2002-2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-
-LIB = libpostlwmon5.a
-
-COBJS = ecc.o
-
-include $(TOPDIR)/post/rules.mk
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Developed for DENX Software Engineering GmbH.
- *
- * Author: Pavel Kolesnikov <concord@emcraft.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* define DEBUG for debugging output (obviously ;-)) */
-#if 0
-#define DEBUG
-#endif
-
-#include <common.h>
-#include <watchdog.h>
-
-#ifdef CONFIG_POST
-
-#include <post.h>
-
-#if CONFIG_POST & CFG_POST_ECC
-
-/*
- * MEMORY ECC test
- *
- * This test performs the checks ECC facility of memory.
- */
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <ppc440.h>
-
-#include "../../../board/lwmon5/sdram.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-const static unsigned char syndrome_codes[] = {
- 0xF4, 0XF1, 0XEC ,0XEA, 0XE9, 0XE6, 0XE5, 0XE3,
- 0XDC, 0XDA, 0XD9, 0XD6, 0XD5, 0XD3, 0XCE, 0XCB,
- 0xB5, 0XB0, 0XAD, 0XAB, 0XA8, 0XA7, 0XA4, 0XA2,
- 0X9D, 0X9B, 0X98, 0X97, 0X94, 0X92, 0X8F, 0X8A,
- 0x75, 0x70, 0X6D, 0X6B, 0X68, 0X67, 0X64, 0X62,
- 0X5E, 0X5B, 0X58, 0X57, 0X54, 0X52, 0X4F, 0X4A,
- 0x34, 0x31, 0X2C, 0X2A, 0X29, 0X26, 0X25, 0X23,
- 0X1C, 0X1A, 0X19, 0X16, 0X15, 0X13, 0X0E, 0X0B,
- 0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01
-};
-
-#define ECC_START_ADDR 0x10
-#define ECC_STOP_ADDR 0x2000
-#define ECC_PATTERN 0x0101010101010101ull
-#define ECC_PATTERN_CORR 0x0101010101010100ull
-#define ECC_PATTERN_UNCORR 0x010101010101010Full
-
-static int test_ecc_error(void)
-{
- unsigned long value;
- unsigned long hdata, ldata, haddr, laddr;
- unsigned int bit;
-
- int ret = 0;
-
- mfsdram(DDR0_23, value);
-
- for (bit = 0; bit < sizeof(syndrome_codes); bit++)
- if (syndrome_codes[bit] == ((value >> 16) & 0xff))
- break;
-
- mfsdram(DDR0_00, value);
-
- if (value & DDR0_00_INT_STATUS_BIT0) {
- debug("Bit0. A single access outside the defined PHYSICAL"
- " memory space detected\n");
- mfsdram(DDR0_32, laddr);
- mfsdram(DDR0_33, haddr);
- debug(" addr = 0x%08x%08x\n", haddr, laddr);
- ret = 1;
- }
- if (value & DDR0_00_INT_STATUS_BIT1) {
- debug("Bit1. Multiple accesses outside the defined PHYSICAL"
- " memory space detected\n");
- ret = 2;
- }
- if (value & DDR0_00_INT_STATUS_BIT2) {
- debug("Bit2. Single correctable ECC event detected\n");
- mfsdram(DDR0_38, laddr);
- mfsdram(DDR0_39, haddr);
- mfsdram(DDR0_40, ldata);
- mfsdram(DDR0_41, hdata);
- debug(" 0x%08x - 0x%08x%08x, bit - %d\n",
- laddr, hdata, ldata, bit);
- ret = 3;
- }
- if (value & DDR0_00_INT_STATUS_BIT3) {
- debug("Bit3. Multiple correctable ECC events detected\n");
- mfsdram(DDR0_38, laddr);
- mfsdram(DDR0_39, haddr);
- mfsdram(DDR0_40, ldata);
- mfsdram(DDR0_41, hdata);
- debug(" 0x%08x - 0x%08x%08x, bit - %d\n",
- laddr, hdata, ldata, bit);
- ret = 4;
- }
- if (value & DDR0_00_INT_STATUS_BIT4) {
- debug("Bit4. Single uncorrectable ECC event detected\n");
- mfsdram(DDR0_34, laddr);
- mfsdram(DDR0_35, haddr);
- mfsdram(DDR0_36, ldata);
- mfsdram(DDR0_37, hdata);
- debug(" 0x%08x - 0x%08x%08x, bit - %d\n",
- laddr, hdata, ldata, bit);
- ret = 5;
- }
- if (value & DDR0_00_INT_STATUS_BIT5) {
- debug("Bit5. Multiple uncorrectable ECC events detected\n");
- mfsdram(DDR0_34, laddr);
- mfsdram(DDR0_35, haddr);
- mfsdram(DDR0_36, ldata);
- mfsdram(DDR0_37, hdata);
- debug(" 0x%08x - 0x%08x%08x, bit - %d\n",
- laddr, hdata, ldata, bit);
- ret = 6;
- }
- if (value & DDR0_00_INT_STATUS_BIT6) {
- debug("Bit6. DRAM initialization complete\n");
- ret = 7;
- }
-
- /* error status cleared */
- mfsdram(DDR0_00, value);
- mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL);
-
- return ret;
-}
-
-static int test_ecc(unsigned long ecc_addr)
-{
- volatile unsigned long long *ecc_mem;
- unsigned long value;
- unsigned long ecc_data;
- volatile unsigned long *lecc_mem;
- int pret, ret = 0;
-
- sync();
- eieio();
- WATCHDOG_RESET();
-
- ecc_mem = (unsigned long long *)ecc_addr;
- lecc_mem = (ulong *)ecc_addr;
- *ecc_mem = ECC_PATTERN;
- pret = test_ecc_error();
- if (pret != 0)
- ret = 1;
-
- /* disconnect ecc */
- mfsdram(DDR0_22, value);
- mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK)
- | DDR0_22_CTRL_RAW_ECC_DISABLE);
-
- /* injecting error */
- *ecc_mem = ECC_PATTERN_CORR;
-
- /* enable ecc */
- mfsdram(DDR0_22, value);
- mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK)
- | DDR0_22_CTRL_RAW_ECC_ENABLE);
-
- ecc_data = *lecc_mem;
- pret = test_ecc_error();
- /* if read data ok, 1 correctable error must be fixed */
- if (pret != 3)
- ret = 1;
-
- /* test for uncorrectable error */
- /* disconnect from ecc storage */
- mfsdram(DDR0_22, value);
- mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK)
- | DDR0_22_CTRL_RAW_NO_ECC_RAM);
-
- /* injecting multiply bit error */
-
- *ecc_mem = ECC_PATTERN_UNCORR;
-
- /* enable ecc */
- mfsdram(DDR0_22, value);
- mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK)
- | DDR0_22_CTRL_RAW_ECC_ENABLE);
-
- ecc_data = *lecc_mem;
- /* what the data should be read? */
-
- pret = test_ecc_error();
- /* info about uncorrectable error must appear */
- if (pret != 5)
- ret = 1;
-
- sync();
- eieio();
-
- return ret;
-}
-
-int ecc_post_test (int flags)
-{
- int ret = 0;
- unsigned long value;
- unsigned long iaddr;
-
-#if CONFIG_DDR_ECC
- sync();
- eieio();
-
- /* mask all int */
- mfsdram(DDR0_01, value);
- mtsdram(DDR0_01, (value &~ DDR0_01_INT_MASK_MASK)
- | DDR0_01_INT_MASK_ALL_OFF);
-
- /* clear error status */
- mfsdram(DDR0_00, value);
- mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL);
-
- /* enable full support of ECC */
- mfsdram(DDR0_22, value);
- mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK)
- | DDR0_22_CTRL_RAW_ECC_ENABLE);
-
- for (iaddr = ECC_START_ADDR; iaddr < ECC_STOP_ADDR; iaddr += iaddr) {
- ret = test_ecc(iaddr);
- if (ret)
- break;
- }
-
- /* clear error status */
- mfsdram(DDR0_00, value);
- mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL);
-
- /*
- * Clear possible errors resulting from ECC testing.
- * If not done, then we could get an interrupt later on when
- * exceptions are enabled.
- */
- set_mcsr(get_mcsr());
-#endif
-
- return ret;
-
-}
-
-#endif /* CONFIG_POST & CFG_POST_ECC */
-#endif /* CONFIG_POST */
LIB = libpostppc4xx.a
AOBJS = cache_4xx.o
-COBJS = cache.o ether.o fpu.o spr.o uart.o watchdog.o
+COBJS = cache.o denali_ecc.o ether.o fpu.o spr.o uart.o watchdog.o
include $(TOPDIR)/post/rules.mk
int cache_post_test5 (int tlb, void *p, int size);
int cache_post_test6 (int tlb, void *p, int size);
-static int tlb = -1; /* index to the victim TLB entry */
-
#ifdef CONFIG_440
static unsigned char testarea[CACHE_POST_SIZE]
__attribute__((__aligned__(CACHE_POST_SIZE)));
int cache_post_test (int flags)
{
- void* virt = (void*)CFG_POST_CACHE_ADDR;
+ void *virt = (void *)CFG_POST_CACHE_ADDR;
int ints;
int res = 0;
+ int tlb = -1; /* index to the victim TLB entry */
/*
* All 44x variants deal with cache management differently
#ifdef CONFIG_440
int word0, i;
- if (tlb < 0) {
- /*
- * Allocate a new TLB entry, since we are going to modify
- * the write-through and caching inhibited storage attributes.
- */
- program_tlb((u32)testarea, (u32)virt,
- CACHE_POST_SIZE, TLB_WORD2_I_ENABLE);
-
- /* Find the TLB entry */
- for (i = 0;; i++) {
- if (i >= PPC4XX_TLB_SIZE) {
- printf ("Failed to program tlb entry\n");
- return -1;
- }
- word0 = mftlb1(i);
- if (TLB_WORD0_EPN_DECODE(word0) == (u32)virt) {
- tlb = i;
- break;
- }
+ /*
+ * Allocate a new TLB entry, since we are going to modify
+ * the write-through and caching inhibited storage attributes.
+ */
+ program_tlb((u32)testarea, (u32)virt, CACHE_POST_SIZE,
+ TLB_WORD2_I_ENABLE);
+
+ /* Find the TLB entry */
+ for (i = 0;; i++) {
+ if (i >= PPC4XX_TLB_SIZE) {
+ printf ("Failed to program tlb entry\n");
+ return -1;
+ }
+ word0 = mftlb1(i);
+ if (TLB_WORD0_EPN_DECODE(word0) == (u32)virt) {
+ tlb = i;
+ break;
}
}
#endif
if (ints)
enable_interrupts ();
+#ifdef CONFIG_440
+ remove_tlb((u32)virt, CACHE_POST_SIZE);
+#endif
+
return res;
}
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Developed for DENX Software Engineering GmbH.
+ *
+ * Author: Pavel Kolesnikov <concord@emcraft.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* define DEBUG for debugging output (obviously ;-)) */
+#if 0
+#define DEBUG
+#endif
+
+#include <common.h>
+#include <watchdog.h>
+
+#if defined(CONFIG_POST) && (defined(CONFIG_440EPX) || defined(CONFIG_440GRX))
+
+#include <post.h>
+
+#if CONFIG_POST & CFG_POST_ECC
+
+/*
+ * MEMORY ECC test
+ *
+ * This test performs the checks ECC facility of memory.
+ */
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <ppc440.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const static unsigned char syndrome_codes[] = {
+ 0xF4, 0XF1, 0XEC, 0XEA, 0XE9, 0XE6, 0XE5, 0XE3,
+ 0XDC, 0XDA, 0XD9, 0XD6, 0XD5, 0XD3, 0XCE, 0XCB,
+ 0xB5, 0XB0, 0XAD, 0XAB, 0XA8, 0XA7, 0XA4, 0XA2,
+ 0X9D, 0X9B, 0X98, 0X97, 0X94, 0X92, 0X8F, 0X8A,
+ 0x75, 0x70, 0X6D, 0X6B, 0X68, 0X67, 0X64, 0X62,
+ 0X5E, 0X5B, 0X58, 0X57, 0X54, 0X52, 0X4F, 0X4A,
+ 0x34, 0x31, 0X2C, 0X2A, 0X29, 0X26, 0X25, 0X23,
+ 0X1C, 0X1A, 0X19, 0X16, 0X15, 0X13, 0X0E, 0X0B,
+ 0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01
+};
+
+#define ECC_START_ADDR 0x10
+#define ECC_STOP_ADDR 0x2000
+#define ECC_PATTERN 0x01010101
+#define ECC_PATTERN_CORR 0x11010101
+#define ECC_PATTERN_UNCORR 0xF1010101
+
+static int test_ecc_error(void)
+{
+ unsigned long value;
+ unsigned long hdata, ldata, haddr, laddr;
+ unsigned int bit;
+
+ int ret = 0;
+
+ mfsdram(DDR0_23, value);
+
+ for (bit = 0; bit < sizeof(syndrome_codes); bit++)
+ if (syndrome_codes[bit] == ((value >> 16) & 0xff))
+ break;
+
+ mfsdram(DDR0_00, value);
+
+ if (value & DDR0_00_INT_STATUS_BIT0) {
+ debug("Bit0. A single access outside the defined PHYSICAL"
+ " memory space detected\n");
+ mfsdram(DDR0_32, laddr);
+ mfsdram(DDR0_33, haddr);
+ debug(" addr = 0x%08x%08x\n", haddr, laddr);
+ ret = 1;
+ }
+ if (value & DDR0_00_INT_STATUS_BIT1) {
+ debug("Bit1. Multiple accesses outside the defined PHYSICAL"
+ " memory space detected\n");
+ ret = 2;
+ }
+ if (value & DDR0_00_INT_STATUS_BIT2) {
+ debug("Bit2. Single correctable ECC event detected\n");
+ mfsdram(DDR0_38, laddr);
+ mfsdram(DDR0_39, haddr);
+ mfsdram(DDR0_40, ldata);
+ mfsdram(DDR0_41, hdata);
+ debug(" 0x%08x - 0x%08x%08x, bit - %d\n",
+ laddr, hdata, ldata, bit);
+ ret = 3;
+ }
+ if (value & DDR0_00_INT_STATUS_BIT3) {
+ debug("Bit3. Multiple correctable ECC events detected\n");
+ mfsdram(DDR0_38, laddr);
+ mfsdram(DDR0_39, haddr);
+ mfsdram(DDR0_40, ldata);
+ mfsdram(DDR0_41, hdata);
+ debug(" 0x%08x - 0x%08x%08x, bit - %d\n",
+ laddr, hdata, ldata, bit);
+ ret = 4;
+ }
+ if (value & DDR0_00_INT_STATUS_BIT4) {
+ debug("Bit4. Single uncorrectable ECC event detected\n");
+ mfsdram(DDR0_34, laddr);
+ mfsdram(DDR0_35, haddr);
+ mfsdram(DDR0_36, ldata);
+ mfsdram(DDR0_37, hdata);
+ debug(" 0x%08x - 0x%08x%08x, bit - %d\n",
+ laddr, hdata, ldata, bit);
+ ret = 5;
+ }
+ if (value & DDR0_00_INT_STATUS_BIT5) {
+ debug("Bit5. Multiple uncorrectable ECC events detected\n");
+ mfsdram(DDR0_34, laddr);
+ mfsdram(DDR0_35, haddr);
+ mfsdram(DDR0_36, ldata);
+ mfsdram(DDR0_37, hdata);
+ debug(" 0x%08x - 0x%08x%08x, bit - %d\n",
+ laddr, hdata, ldata, bit);
+ ret = 6;
+ }
+ if (value & DDR0_00_INT_STATUS_BIT6) {
+ debug("Bit6. DRAM initialization complete\n");
+ ret = 7;
+ }
+
+ /* error status cleared */
+ mfsdram(DDR0_00, value);
+ mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL);
+
+ return ret;
+}
+
+static int test_ecc(unsigned long ecc_addr)
+{
+ unsigned long value;
+ volatile unsigned *const ecc_mem = (volatile unsigned *) ecc_addr;
+ int pret;
+ int ret = 0;
+
+ sync();
+ eieio();
+ WATCHDOG_RESET();
+
+ debug("Entering test_ecc(0x%08lX)\n", ecc_addr);
+ out_be32(ecc_mem, ECC_PATTERN);
+ out_be32(ecc_mem + 1, ECC_PATTERN);
+ in_be32(ecc_mem);
+ pret = test_ecc_error();
+ if (pret != 0) {
+ debug("pret: expected 0, got %d\n", pret);
+ ret = 1;
+ }
+ /* test for correctable error */
+ /* disconnect from ecc storage */
+ mfsdram(DDR0_22, value);
+ mtsdram(DDR0_22, (value & ~DDR0_22_CTRL_RAW_MASK)
+ | DDR0_22_CTRL_RAW_ECC_DISABLE);
+
+ /* creating (correctable) single-bit error */
+ out_be32(ecc_mem, ECC_PATTERN_CORR);
+
+ /* enable ecc */
+ mfsdram(DDR0_22, value);
+ mtsdram(DDR0_22, (value & ~DDR0_22_CTRL_RAW_MASK)
+ | DDR0_22_CTRL_RAW_ECC_ENABLE);
+ sync();
+ eieio();
+
+ in_be32(ecc_mem);
+ pret = test_ecc_error();
+ /* if read data ok, 1 correctable error must be fixed */
+ if (pret != 3) {
+ debug("pret: expected 3, got %d\n", pret);
+ ret = 1;
+ }
+ /* test for uncorrectable error */
+ /* disconnect from ecc storage */
+ mfsdram(DDR0_22, value);
+ mtsdram(DDR0_22, (value & ~DDR0_22_CTRL_RAW_MASK)
+ | DDR0_22_CTRL_RAW_NO_ECC_RAM);
+
+ /* creating (uncorrectable) multiple-bit error */
+ out_be32(ecc_mem, ECC_PATTERN_UNCORR);
+
+ /* enable ecc */
+ mfsdram(DDR0_22, value);
+ mtsdram(DDR0_22, (value & ~DDR0_22_CTRL_RAW_MASK)
+ | DDR0_22_CTRL_RAW_ECC_ENABLE);
+ sync();
+ eieio();
+
+ in_be32(ecc_mem);
+ pret = test_ecc_error();
+ /* info about uncorrectable error must appear */
+ if (pret != 5) {
+ debug("pret: expected 5, got %d\n", pret);
+ ret = 1;
+ }
+ /* remove error from SDRAM */
+ out_be32(ecc_mem, ECC_PATTERN);
+ /* clear error caused by read-modify-write */
+ mfsdram(DDR0_00, value);
+ mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL);
+
+ sync();
+ eieio();
+ return ret;
+}
+
+int ecc_post_test (int flags)
+{
+ int ret = 0;
+ unsigned long value;
+ unsigned long iaddr;
+
+ sync();
+ eieio();
+
+ mfsdram(DDR0_22, value);
+ if (0x3 != DDR0_22_CTRL_RAW_DECODE(value)) {
+ debug("SDRAM ECC not enabled, skipping ECC POST.\n");
+ return 0;
+ }
+
+ /* mask all int */
+ mfsdram(DDR0_01, value);
+ mtsdram(DDR0_01, (value & ~DDR0_01_INT_MASK_MASK)
+ | DDR0_01_INT_MASK_ALL_OFF);
+
+ /* clear error status */
+ mfsdram(DDR0_00, value);
+ mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL);
+
+ for (iaddr = ECC_START_ADDR; iaddr <= ECC_STOP_ADDR; iaddr += iaddr) {
+ ret = test_ecc(iaddr);
+ if (ret)
+ break;
+ }
+ /*
+ * Clear possible errors resulting from ECC testing.
+ * If not done, then we could get an interrupt later on when
+ * exceptions are enabled.
+ */
+ set_mcsr(get_mcsr());
+ return ret;
+
+}
+#endif /* CONFIG_POST & CFG_POST_ECC */
+#endif /* defined(CONFIG_POST) && ... */
DECLARE_GLOBAL_DATA_PTR;
+/*
+ * Get count of EMAC devices (doesn't have to be the max. possible number
+ * supported by the cpu)
+ *
+ * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the
+ * EMAC count is possible. As it is needed for the Kilauea/Haleakala
+ * 405EX/405EXr eval board, using the same binary.
+ */
+#if defined(CONFIG_BOARD_EMAC_COUNT)
+#define LAST_EMAC_NUM board_emac_count()
+#else /* CONFIG_BOARD_EMAC_COUNT */
+#if defined(CONFIG_HAS_ETH3)
+#define LAST_EMAC_NUM 4
+#elif defined(CONFIG_HAS_ETH2)
+#define LAST_EMAC_NUM 3
+#elif defined(CONFIG_HAS_ETH1)
+#define LAST_EMAC_NUM 2
+#else
+#define LAST_EMAC_NUM 1
+#endif
+#endif /* CONFIG_BOARD_EMAC_COUNT */
+
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
#endif
static char *tx_buf;
static char *rx_buf;
+int board_emac_count(void);
+
static void ether_post_init (int devnum, int hw_addr)
{
int i;
sync ();
#endif
/* reset emac */
- out32 (EMAC_M0 + hw_addr, EMAC_M0_SRST);
+ out_be32 ((void*)(EMAC_M0 + hw_addr), EMAC_M0_SRST);
sync ();
for (i = 0;; i++) {
- if (!(in32 (EMAC_M0 + hw_addr) & EMAC_M0_SRST))
+ if (!(in_be32 ((void*)(EMAC_M0 + hw_addr)) & EMAC_M0_SRST))
break;
if (i >= 1000) {
printf ("Timeout resetting EMAC\n");
else
mode_reg |= EMAC_M1_OBCI_GT100;
- out32 (EMAC_M1 + hw_addr, mode_reg);
+ out_be32 ((void*)(EMAC_M1 + hw_addr), mode_reg);
#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
rx.ctrl = MAL_TX_CTRL_WRAP | MAL_RX_CTRL_EMPTY;
rx.data_len = 0;
rx.data_ptr = (char*)L1_CACHE_ALIGN((u32)rx_buf);
+ flush_dcache_range((u32)&rx, (u32)&rx + sizeof(mal_desc_t));
+ flush_dcache_range((u32)&tx, (u32)&tx + sizeof(mal_desc_t));
switch (devnum) {
case 1:
/* set internal loopback mode */
#ifdef CFG_POST_ETHER_EXT_LOOPBACK
- out32 (EMAC_M1 + hw_addr, EMAC_M1_FDE | 0 |
- EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
- EMAC_M1_MF_100MBPS | EMAC_M1_IST |
- in32 (EMAC_M1));
+ out_be32 ((void*)(EMAC_M1 + hw_addr), EMAC_M1_FDE | 0 |
+ EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
+ EMAC_M1_MF_100MBPS | EMAC_M1_IST |
+ in_be32 ((void*)(EMAC_M1 + hw_addr)));
#else
- out32 (EMAC_M1 + hw_addr, EMAC_M1_FDE | EMAC_M1_ILE |
- EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
- EMAC_M1_MF_100MBPS | EMAC_M1_IST |
- in32 (EMAC_M1));
+ out_be32 ((void*)(EMAC_M1 + hw_addr), EMAC_M1_FDE | EMAC_M1_ILE |
+ EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
+ EMAC_M1_MF_100MBPS | EMAC_M1_IST |
+ in_be32 ((void*)(EMAC_M1 + hw_addr)));
#endif
/* set transmit enable & receive enable */
- out32 (EMAC_M0 + hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
+ out_be32 ((void*)(EMAC_M0 + hw_addr), EMAC_M0_TXE | EMAC_M0_RXE);
/* enable broadcast address */
- out32 (EMAC_RXM + hw_addr, EMAC_RMR_BAE);
+ out_be32 ((void*)(EMAC_RXM + hw_addr), EMAC_RMR_BAE);
/* set transmit request threshold register */
- out32 (EMAC_TRTR + hw_addr, 0x18000000); /* 256 byte threshold */
+ out_be32 ((void*)(EMAC_TRTR + hw_addr), 0x18000000); /* 256 byte threshold */
/* set receive low/high water mark register */
#if defined(CONFIG_440)
/* 440s has a 64 byte burst length */
- out32 (EMAC_RX_HI_LO_WMARK + hw_addr, 0x80009000);
+ out_be32 ((void*)(EMAC_RX_HI_LO_WMARK + hw_addr), 0x80009000);
#else
/* 405s have a 16 byte burst length */
- out32 (EMAC_RX_HI_LO_WMARK + hw_addr, 0x0f002000);
+ out_be32 ((void*)(EMAC_RX_HI_LO_WMARK + hw_addr), 0x0f002000);
#endif /* defined(CONFIG_440) */
- out32 (EMAC_TXM1 + hw_addr, 0xf8640000);
+ out_be32 ((void*)(EMAC_TXM1 + hw_addr), 0xf8640000);
/* Set fifo limit entry in tx mode 0 */
- out32 (EMAC_TXM0 + hw_addr, 0x00000003);
+ out_be32 ((void*)(EMAC_TXM0 + hw_addr), 0x00000003);
/* Frame gap set */
- out32 (EMAC_I_FRAME_GAP_REG + hw_addr, 0x00000008);
+ out_be32 ((void*)(EMAC_I_FRAME_GAP_REG + hw_addr), 0x00000008);
sync ();
}
udelay (1000);
}
/* emac reset */
- out32 (EMAC_M0 + hw_addr, EMAC_M0_SRST);
+ out_be32 ((void*)(EMAC_M0 + hw_addr), EMAC_M0_SRST);
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
/* remove clocks for EMAC internal loopback */
return;
}
udelay (1000);
+ invalidate_dcache_range((u32)&tx, (u32)&tx + sizeof(mal_desc_t));
}
tx.ctrl = MAL_TX_CTRL_READY | MAL_TX_CTRL_WRAP | MAL_TX_CTRL_LAST |
EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP;
tx.data_len = length;
memcpy (tx.data_ptr, packet, length);
+ flush_dcache_range((u32)&tx, (u32)&tx + sizeof(mal_desc_t));
+ flush_dcache_range((u32)tx.data_ptr, (u32)tx.data_ptr + length);
sync ();
- out32 (EMAC_TXM0 + hw_addr, in32 (EMAC_TXM0 + hw_addr) | EMAC_TXM0_GNP0);
+ out_be32 ((void*)(EMAC_TXM0 + hw_addr), in_be32 ((void*)(EMAC_TXM0 + hw_addr)) | EMAC_TXM0_GNP0);
sync ();
}
return 0;
}
udelay (1000);
+ invalidate_dcache_range((u32)&rx, (u32)&rx + sizeof(mal_desc_t));
}
length = rx.data_len - 4;
- if (length <= max_length)
+ if (length <= max_length) {
+ invalidate_dcache_range((u32)rx.data_ptr, (u32)rx.data_ptr + length);
memcpy(packet, rx.data_ptr, length);
+ }
sync ();
rx.ctrl |= MAL_RX_CTRL_EMPTY;
+ flush_dcache_range((u32)&rx, (u32)&rx + sizeof(mal_desc_t));
sync ();
return length;
int ether_post_test (int flags)
{
int res = 0;
+ int i;
/* Allocate tx & rx packet buffers */
tx_buf = malloc (PKTSIZE_ALIGN + CFG_CACHELINE_SIZE);
goto out_free;
}
- /* EMAC0 */
- if (test_ctlr (0, 0))
- res = -1;
-
- /* EMAC1 */
- if (test_ctlr (1, 0x100))
- res = -1;
+ for (i = 0; i < LAST_EMAC_NUM; i++) {
+ if (test_ctlr (i, i*0x100))
+ res = -1;
+ }
out_free:
free (tx_buf);
#define UCR0_UDIV_POS 0
#define UCR1_UDIV_POS 8
#define UDIV_MAX 127
+#elif defined(CONFIG_405EX)
+#define UART0_BASE 0xef600200
+#define UART1_BASE 0xef600300
+#define CR0_MASK 0x000000ff
+#define CR0_EXTCLK_ENA 0x00800000
+#define CR0_UDIV_POS 0
+#define UDIV_SUBTRACT 0
+#define UART0_SDR sdr_uart0
+#define UART1_SDR sdr_uart1
+#define MFREG(a, d) mfsdr(a, d)
+#define MTREG(a, d) mtsdr(a, d)
#else /* CONFIG_405GP || CONFIG_405CR */
#define UART0_BASE 0xef600300
#define UART1_BASE 0xef600400
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_440)
+#if defined(CONFIG_440) || defined(CONFIG_405EX)
#if !defined(CFG_EXT_SERIAL_CLOCK)
static void serial_divs (int baudrate, unsigned long *pudiv,
unsigned short *pbdiv)
static int uart_post_init (unsigned long dev_base)
{
- unsigned long reg;
+ unsigned long reg = 0;
unsigned long udiv;
unsigned short bdiv;
volatile char val;
#include <watchdog.h>
#include <post.h>
+#include <asm/mmu.h>
#if CONFIG_POST & CFG_POST_CPU
extern int cpu_post_test_string (void);
extern int cpu_post_test_complex (void);
+DECLARE_GLOBAL_DATA_PTR;
+
ulong cpu_post_makecr (long v)
{
ulong cr = 0;
WATCHDOG_RESET();
if (ic)
icache_disable ();
+#ifdef CONFIG_4xx_DCACHE
+ /* disable cache */
+ change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, TLB_WORD2_I_ENABLE);
+#endif
if (ret == 0)
ret = cpu_post_test_cmp ();
if (ic)
icache_enable ();
+#ifdef CONFIG_4xx_DCACHE
+ /* enable cache */
+ change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, 0);
+#endif
WATCHDOG_RESET();
--- /dev/null
+#
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_SH -D__SH__
projects / u-boot / commitdiff