LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o \
+COBJS := $(BOARD).o law.o \
../common/cadmus.o \
../common/eeprom.o \
../common/ft_board.o \
.long FSL_BOOKE_MAS3(CADMUS_BASE_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
entry_end
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000 0x7fff_ffff DDR 2G
- * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
- * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
- * 0xe000_0000 0xe000_ffff CCSR 1M
- * 0xe200_0000 0xe20f_ffff PCI1 IO 1M
- * 0xe210_0000 0xe21f_ffff PCI2 IO 1M
- * 0xf000_0000 0xf7ff_ffff SDRAM 128M
- * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
- * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
- * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
- *
- * Notes:
- * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- * If flash is 8M at default position (last 8M), no LAW needed.
- *
- * The defines below are 1-off of the actual LAWAR0 usage.
- * So LAWAR3 define uses the LAWAR4 register in the ECM.
- */
-
-#define LAWBAR0 0
-#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
-
-#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
-#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
-#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
-#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
-
-#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff)
-#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
-
-/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
-#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
-#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
-
- .section .bootpg, "ax"
- .globl law_entry
-
-law_entry:
- entry_start
- .long 6
- .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
- .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5
- entry_end
--- /dev/null
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000 0x7fff_ffff DDR 2G
+ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
+ * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
+ * 0xe000_0000 0xe000_ffff CCSR 1M
+ * 0xe200_0000 0xe20f_ffff PCI1 IO 1M
+ * 0xe210_0000 0xe21f_ffff PCI2 IO 1M
+ * 0xf000_0000 0xf7ff_ffff SDRAM 128M
+ * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
+ * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
+ * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
+ *
+ * Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+ SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+ SET_LAW_ENTRY(3, CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+ SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
+ SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
+ /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+ SET_LAW_ENTRY(6, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o \
+COBJS := $(BOARD).o law.o \
../common/cadmus.o \
../common/eeprom.o \
../common/ft_board.o \
2:
entry_end
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000 0x7fff_ffff DDR 2G
- * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
- * 0xa000_0000 0xbfff_ffff PCIe MEM 512M
- * 0xc000_0000 0xdfff_ffff RapidIO 512M
- * 0xe000_0000 0xe000_ffff CCSR 1M
- * 0xe200_0000 0xe10f_ffff PCI1 IO 1M
- * 0xe280_0000 0xe20f_ffff PCI2 IO 1M
- * 0xe300_0000 0xe30f_ffff PCIe IO 1M
- * 0xf000_0000 0xf3ff_ffff SDRAM 64M
- * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
- * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
- * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
- *
- * Notes:
- * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- * If flash is 8M at default position (last 8M), no LAW needed.
- *
- * LAW 0 is reserved for boot mapping
- */
-
- .section .bootpg, "ax"
- .globl law_entry
-law_entry:
- entry_start
-
- .long (4f-3f)/8
-3:
- .long 0
- .long (LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
-
-#ifdef CFG_PCI1_MEM_PHYS
- .long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
-
- .long (CFG_PCI1_IO_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
-#endif
-
-#ifdef CFG_PCI2_MEM_PHYS
- .long (CFG_PCI2_MEM_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
-
- .long (CFG_PCI2_IO_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)
-#endif
-
-#ifdef CFG_PCIE1_MEM_PHYS
- .long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
-
- .long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
-#endif
-
- /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
- .long (CFG_LBC_CACHE_BASE>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
-
-#ifdef CFG_RIO_MEM_PHYS
- .long (CFG_RIO_MEM_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)
-#endif
-4:
- entry_end
--- /dev/null
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000 0x7fff_ffff DDR 2G
+ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
+ * 0xa000_0000 0xbfff_ffff PCIe MEM 512M
+ * 0xc000_0000 0xdfff_ffff RapidIO 512M
+ * 0xe000_0000 0xe000_ffff CCSR 1M
+ * 0xe200_0000 0xe10f_ffff PCI1 IO 1M
+ * 0xe280_0000 0xe20f_ffff PCI2 IO 1M
+ * 0xe300_0000 0xe30f_ffff PCIe IO 1M
+ * 0xf000_0000 0xf3ff_ffff SDRAM 64M
+ * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
+ * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
+ * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
+ *
+ * Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ * LAW 0 is reserved for boot mapping
+ */
+
+struct law_entry law_table[] = {
+#ifdef CFG_PCI1_MEM_PHYS
+ SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+ SET_LAW_ENTRY(3, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
+#endif
+#ifdef CFG_PCI2_MEM_PHYS
+ SET_LAW_ENTRY(4, CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+ SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
+#endif
+#ifdef CFG_PCIE1_MEM_PHYS
+ SET_LAW_ENTRY(6, CFG_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
+ SET_LAW_ENTRY(7, CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1),
+#endif
+ /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+ SET_LAW_ENTRY(8, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+#ifdef CFG_RIO_MEM_PHYS
+ SET_LAW_ENTRY(9, CFG_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o \
+COBJS := $(BOARD).o law.o \
../common/cadmus.o \
../common/eeprom.o \
../common/ft_board.o \
.long FSL_BOOKE_MAS3(CADMUS_BASE_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
entry_end
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000 0x7fff_ffff DDR 2G
- * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
- * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
- * 0xe000_0000 0xe000_ffff CCSR 1M
- * 0xe200_0000 0xe20f_ffff PCI1 IO 1M
- * 0xe210_0000 0xe21f_ffff PCI2 IO 1M
- * 0xf000_0000 0xf7ff_ffff SDRAM 128M
- * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
- * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
- * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
- *
- * Notes:
- * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- * If flash is 8M at default position (last 8M), no LAW needed.
- *
- * The defines below are 1-off of the actual LAWAR0 usage.
- * So LAWAR3 define uses the LAWAR4 register in the ECM.
- */
-
-#define LAWBAR0 0
-#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
-
-#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
-#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
-#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
-#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
-
-#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff)
-#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
-
-/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
-#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
-#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
-
- .section .bootpg, "ax"
- .globl law_entry
-
-law_entry:
- entry_start
- .long 6
- .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
- .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5
- entry_end
--- /dev/null
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000 0x7fff_ffff DDR 2G
+ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
+ * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
+ * 0xe000_0000 0xe000_ffff CCSR 1M
+ * 0xe200_0000 0xe20f_ffff PCI1 IO 1M
+ * 0xe210_0000 0xe21f_ffff PCI2 IO 1M
+ * 0xf000_0000 0xf7ff_ffff SDRAM 128M
+ * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
+ * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
+ * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
+ *
+ * Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+ SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+ SET_LAW_ENTRY(3, CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+ SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
+ SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
+ /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+ SET_LAW_ENTRY(6, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
#define CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
/*
* When initializing flash, if we cannot find the manufacturer ID,
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
+#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
/*
* When initializing flash, if we cannot find the manufacturer ID,
#define CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
/*
* When initializing flash, if we cannot find the manufacturer ID,
projects / u-boot / commitdiff