Merge branch 'master' of git://git.denx.de/u-boot

Signed-off-by: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index ae3143c760716906ac8f660114967c43ec0ce2c6..96fbd81d0814766bba5717b0c49dcca70f3ce41e 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -881,6 +881,11 @@ int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
        writel(reg, &anatop->pll_enet);
 
 #ifdef CONFIG_MX6SX
+       /* Disable enet system clcok before switching clock parent */
+       reg = readl(&imx_ccm->CCGR3);
+       reg &= ~MXC_CCM_CCGR3_ENET_MASK;
+       writel(reg, &imx_ccm->CCGR3);
+
        /*
         * Set enet ahb clock to 200MHz
         * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 7b53bfdeb40cd7d32615aafa97e8cf1038817318..dd9479751440ea0dd62204a7ae9837c936271118 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -300,9 +300,17 @@ static void clear_mmdc_ch_mask(void)
        writel(reg, &mxc_ccm->ccdr);
 }
 
+#define OCOTP_MEM0_REFTOP_TRIM_SHIFT          8
+
 static void init_bandgap(void)
 {
        struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+       struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+       struct fuse_bank *bank = &ocotp->bank[1];
+       struct fuse_bank1_regs *fuse =
+               (struct fuse_bank1_regs *)bank->fuse_regs;
+       uint32_t val;
+
        /*
         * Ensure the bandgap has stabilized.
         */
@@ -315,13 +323,26 @@ static void init_bandgap(void)
         */
        writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
        /*
-        * On i.MX6ULL, the LDO 1.2V bandgap voltage is 30mV higher. so set
-        * VBGADJ bits to 2b'110 to adjust it.
+        * On i.MX6ULL,we need to set VBGADJ bits according to the
+        * REFTOP_TRIM[3:0] in fuse table
+        *      000 - set REFTOP_VBGADJ[2:0] to 3b'110,
+        *      110 - set REFTOP_VBGADJ[2:0] to 3b'000,
+        *      001 - set REFTOP_VBGADJ[2:0] to 3b'001,
+        *      010 - set REFTOP_VBGADJ[2:0] to 3b'010,
+        *      011 - set REFTOP_VBGADJ[2:0] to 3b'011,
+        *      100 - set REFTOP_VBGADJ[2:0] to 3b'100,
+        *      101 - set REFTOP_VBGADJ[2:0] to 3b'101,
+        *      111 - set REFTOP_VBGADJ[2:0] to 3b'111,
         */
-       if (is_mx6ull())
-               writel(BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ, &anatop->ana_misc0_set);
-}
+       if (is_mx6ull()) {
+               val = readl(&fuse->mem0);
+               val >>= OCOTP_MEM0_REFTOP_TRIM_SHIFT;
+               val &= 0x7;
 
+               writel(val << BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT,
+                      &anatop->ana_misc0_set);
+       }
+}
 
 #ifdef CONFIG_MX6SL
 static void set_preclk_from_osc(void)

diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index f74737a68e60912f42a2bfc23570a174a87aea54..29674ce54d82b4dfa4125355c9f22303d380cc0d 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -1272,6 +1272,7 @@ struct mxc_ccm_reg {
 
 #define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008
 #define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ 0x60
+#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT 4
 
 #define BM_PMU_MISC2_AUDIO_DIV_MSB (1 << 23)
 #define BP_PMU_MISC2_AUDIO_DIV_MSB 23

diff --git a/board/CarMediaLab/flea3/flea3.c b/board/CarMediaLab/flea3/flea3.c
index 2463077475ace1cb1aecefe3557bd12fac77f3b9..3cd4dc95fe32c111f507ca42c5c09eca3b8830a3 100644 (file)
--- a/board/CarMediaLab/flea3/flea3.c
+++ b/board/CarMediaLab/flea3/flea3.c
@@ -19,6 +19,9 @@
 #include <asm/gpio.h>
 #include <asm/arch/sys_proto.h>
 #include <netdev.h>
+#include <fdt_support.h>
+#include <mtd_node.h>
+#include <jffs2/load_kernel.h>
 
 #ifndef CONFIG_BOARD_EARLY_INIT_F
 #error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
@@ -27,18 +30,6 @@
 #define CCM_CCMR_CONFIG                0x003F4208
 
 #define ESDCTL_DDR2_CONFIG     0x007FFC3F
-#define ESDCTL_0x92220000      0x92220000
-#define ESDCTL_0xA2220000      0xA2220000
-#define ESDCTL_0xB2220000      0xB2220000
-#define ESDCTL_0x82228080      0x82228080
-#define ESDCTL_DDR2_EMR2       0x04000000
-#define ESDCTL_DDR2_EMR3       0x06000000
-#define ESDCTL_PRECHARGE       0x00000400
-#define ESDCTL_DDR2_EN_DLL     0x02000400
-#define ESDCTL_DDR2_RESET_DLL  0x00000333
-#define ESDCTL_DDR2_MR         0x00000233
-#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
-#define ESDCTL_DELAY_LINE5     0x00F49F00
 
 static inline void dram_wait(unsigned int count)
 {
@@ -58,83 +49,6 @@ int dram_init(void)
        return 0;
 }
 
-static void board_setup_sdram_bank(u32 start_address)
-
-{
-       struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
-       u32 *cfg_reg, *ctl_reg;
-       u32 val;
-
-       switch (start_address) {
-       case CSD0_BASE_ADDR:
-               cfg_reg = &esdc->esdcfg0;
-               ctl_reg = &esdc->esdctl0;
-               break;
-       case CSD1_BASE_ADDR:
-               cfg_reg = &esdc->esdcfg1;
-               ctl_reg = &esdc->esdctl1;
-               break;
-       default:
-               return;
-       }
-
-       /* Initialize MISC register for DDR2 */
-       val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
-               ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
-       writel(val, &esdc->esdmisc);
-       val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
-       writel(val, &esdc->esdmisc);
-
-       /*
-        * according to DDR2 specs, wait a while before
-        * the PRECHARGE_ALL command
-        */
-       dram_wait(0x20000);
-
-       /* Load DDR2 config and timing */
-       writel(ESDCTL_DDR2_CONFIG, cfg_reg);
-
-       /* Precharge ALL */
-       writel(ESDCTL_0x92220000,
-               ctl_reg);
-       writel(0xda, start_address + ESDCTL_PRECHARGE);
-
-       /* Load mode */
-       writel(ESDCTL_0xB2220000,
-               ctl_reg);
-       writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
-       writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
-       writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
-       writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
-
-       /* Precharge ALL */
-       writel(ESDCTL_0x92220000,
-               ctl_reg);
-       writel(0xda, start_address + ESDCTL_PRECHARGE);
-
-       /* Set mode auto refresh : at least two refresh are required */
-       writel(ESDCTL_0xA2220000,
-               ctl_reg);
-       writel(0xda, start_address);
-       writel(0xda, start_address);
-
-       writel(ESDCTL_0xB2220000,
-               ctl_reg);
-       writeb(0xda, start_address + ESDCTL_DDR2_MR);
-       writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
-
-       /* OCD mode exit */
-       writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
-
-       /* Set normal mode */
-       writel(ESDCTL_0x82228080,
-               ctl_reg);
-
-       dram_wait(0x20000);
-
-       /* Do not set delay lines, only for MDDR */
-}
-
 static void board_setup_sdram(void)
 {
        struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
@@ -143,7 +57,9 @@ static void board_setup_sdram(void)
        writel(0x2000, &esdc->esdctl0);
        writel(0x2000, &esdc->esdctl1);
 
-       board_setup_sdram_bank(CSD0_BASE_ADDR);
+
+       mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG,
+                            13, 10, 2, 0x8080);
 }
 
 static void setup_iomux_uart3(void)
@@ -206,6 +122,8 @@ static void setup_iomux_fec(void)
                MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
                MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
                MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
+               /* GPIO used to power off ethernet */
+               MX35_PAD_STXFS4__GPIO2_31,
        };
 
        /* setup pins for FEC */
@@ -267,6 +185,11 @@ int board_init(void)
        /* address of boot parameters */
        gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 
+       /* Enable power for ethernet */
+       gpio_direction_output(63, 0);
+
+       udelay(2000);
+
        return 0;
 }
 
@@ -276,3 +199,24 @@ u32 get_board_rev(void)
 
        return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
 }
+
+/*
+ * called prior to booting kernel or by 'fdt boardsetup' command
+ *
+ */
+int ft_board_setup(void *blob, bd_t *bd)
+{
+       struct node_info nodes[] = {
+               { "physmap-flash.0", MTD_DEV_TYPE_NOR, },  /* NOR flash */
+               { "mxc_nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
+       };
+
+       if (getenv("fdt_noauto")) {
+               puts("   Skiping ft_board_setup (fdt_noauto defined)\n");
+               return 0;
+       }
+
+       fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+
+       return 0;
+}

diff --git a/configs/flea3_defconfig b/configs/flea3_defconfig
index 7aa1ba8aea2792aae0090f0679be7ab123084e46..c5ccbd6cd9104a84d9783e855fbc2627f46369b1 100644 (file)
--- a/configs/flea3_defconfig
+++ b/configs/flea3_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_FLEA3=y
 CONFIG_FIT=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_BOOTDELAY=3
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_HUSH_PARSER=y
@@ -12,3 +13,6 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
+# CONFIG_EFI_LOADER is not set

diff --git a/include/configs/flea3.h b/include/configs/flea3.h
index 11d9391139fbcc487cd935491a2c7ba2f723b072..0f7b3c82dbe4a991cd7aef65769906551152e65a 100644 (file)
--- a/include/configs/flea3.h
+++ b/include/configs/flea3.h
@@ -101,10 +101,9 @@
 #define CONFIG_CMDLINE_EDITING
 
 #define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_CBSIZE      256     /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE      512     /* Console I/O Buffer Size */
 /* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS     16      /* max number of command args */
+#define CONFIG_SYS_MAXARGS     32      /* max number of command args */
 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
 
 #define CONFIG_SYS_MEMTEST_START       0       /* memtest works on */
@@ -227,8 +226,8 @@
        "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0"          \
        "load=tftp ${loadaddr} ${u-boot}\0"                             \
        "uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0"         \
-       "update=protect off ${uboot_addr} +40000;"                      \
-               "erase ${uboot_addr} +40000;"                           \
+       "update=protect off ${uboot_addr} +80000;"                      \
+               "erase ${uboot_addr} +80000;"                           \
                "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0"          \
        "upd=if run load;then echo Updating u-boot;if run update;"      \
                "then echo U-Boot updated;"                             \