Add support for Analogue&Micro Adder87x and the older AdderII board.
* Patch by Ming-Len Wu, 09 Jun 2004:
Add suppport for MC9328 (Dargonball) CPU and Motorola MX1ADS board
Changes since U-Boot 1.1.1:
======================================================================
+* Patch by Yuli Barcohen, 09 Jun 2004:
+ Add support for Analogue&Micro Adder87x and the older AdderII board.
+
+* Patch by Ming-Len Wu, 09 Jun 2004:
+ Add suppport for MC9328 (Dargonball) CPU and Motorola MX1ADS board
+
* Patch by Sam Song, 09 Jun 2004:
- Add support for RPXlite_DW board
- Update FLASH driver for 4*AM29DL323DB90VI
D: Unified support for Motorola MPC826xADS/MPC8272ADS/PQ2FADS boards.
D: Support for Zephyr Engineering ZPC.1900 board.
D: Support for Interphase iSPAN boards.
+D: Support for Analogue&Micro Adder boards.
W: http://www.arabellasw.com
N: Jerry van Baren
E: erwin@muffin.org
D: boot support for RTEMS
+N: Paul Ruhland
+E: pruhland@rochester.rr.com
+D: Port to Logic Zoom LH7A40x SDK board(s)
+
N: Neil Russell
E: caret@c-side.com
D: Author of LiMon-1.4.2, which contributed some ideas
E: dave@cray.com
D: Port to Cray L1 board; DHCP vendor extensions
+N: Christian Vejlbo
+E: christian.vejlbo@tellabs.com
+D: FADS860T ethernet support
+
N: Martin Winistoerfer
E: martinwinistoerfer@gmx.ch
D: Port to MPC555/556 microcontrollers and support for cmi board
-N: Christian Vejlbo
-E: christian.vejlbo@tellabs.com
-D: FADS860T ethernet support
+N: Ming-Len Wu
+E: minglen_wu@techware.com.tw
+D: Motorola MX1ADS board support
+W: http://www.techware.com.tw/
+
+N: Xianghua Xiao
+E: x.xiao@motorola.com
+D: Support for Motorola 85xx(PowerQUICC III) chip, MPC8540ADS and MPC8560ADS boards.
N: John Zhan
E: zhanz@sinovee.com
E: azu@sysgo.de
D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM
W: www.elinos.com
-
-N: Xianghua Xiao
-E: x.xiao@motorola.com
-D: Support for Motorola 85xx(PowerQUICC III) chip, MPC8540ADS and MPC8560ADS boards.
-
-N: Paul Ruhland
-E: pruhland@rochester.rr.com
-D: Port to Logic Zoom LH7A40x SDK board(s)
Yuli Barcohen <yuli@arabellasw.com>
+ Adder MPC87x/MPC852T
ISPAN MPC8260
MPC8260ADS MPC826x/MPC827x/MPC8280
ZPC1900 MPC8265
#########################################################################
LIST_8xx=" \
+ Adder GENIETV MBX860T RBC823 \
AdderII GTH MHPC rmu \
ADS860 hermes MPC86xADS RPXClassic \
AMX860 IAD210 MPC885ADS RPXlite \
FPS850L LANTEC QS850 TQM855L \
GEN860T lwmon QS860T TQM860L \
GEN860T_SC MBX R360MPI v37 \
- GENIETV MBX860T RBC823 \
"
#########################################################################
LIST_ARM9=" \
at91rm9200dk integratorcp integratorap \
- lpd7a400 omap1510inn omap1610h2 \
- omap1610inn omap730p2 smdk2400 \
- smdk2410 trab VCMA9 \
- versatile \
+ lpd7a400 mx1ads omap1510inn \
+ omap1610h2 omap1610inn omap730p2 \
+ smdk2400 smdk2410 trab \
+ VCMA9 versatile \
"
#########################################################################
## MPC8xx Systems
#########################################################################
+Adder_config \
+Adder87x_config \
+Adder852_config \
+ : unconfig
+ $(if $(findstring 852,$@), \
+ @echo "#define CONFIG_MPC852T" > include/config.h)
+ @./mkconfig -a Adder ppc mpc8xx adder
+
AdderII_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8xx adderII
xtract_omap730p2 = $(subst _cs0boot,,$(subst _cs3boot,, $(subst _config,,$1)))
-SX1_config : unconfig
- @./mkconfig $(@:_config=) arm arm925t sx1
-
integratorcp_config : unconfig
@./mkconfig $(@:_config=) arm arm926ejs integratorcp
integratorap_config : unconfig
@./mkconfig $(@:_config=) arm arm926ejs integratorap
-versatile_config : unconfig
- @./mkconfig $(@:_config=) arm arm926ejs versatile
+lpd7a400_config: unconfig
+ @./mkconfig $(@:_config=) arm lh7a40x lpd7a40x
omap1510inn_config : unconfig
@./mkconfig $(@:_config=) arm arm925t omap1510inn
smdk2410_config : unconfig
@./mkconfig $(@:_config=) arm arm920t smdk2410
+SX1_config : unconfig
+ @./mkconfig $(@:_config=) arm arm925t sx1
+
+mx1ads_config : unconfig
+ @./mkconfig $(@:_config=) arm mc9328 mx1ads
+
# TRAB default configuration: 8 MB Flash, 32 MB RAM
trab_config \
trab_bigram_config \
VCMA9_config : unconfig
@./mkconfig $(@:_config=) arm arm920t vcma9 mpl
-lpd7a400_config: unconfig
- @./mkconfig $(@:_config=) arm lh7a40x lpd7a40x
+versatile_config : unconfig
+ @./mkconfig $(@:_config=) arm arm926ejs versatile
#########################################################################
## S3C44B0 Systems
@./mkconfig $(@:_config=) arm s3c44b0 B2 dave
#########################################################################
-## ARM720T Systems
+## MC9328 (Dragonball) Systems
#########################################################################
-impa7_config : unconfig
- @./mkconfig $(@:_config=) arm arm720t impa7
+mx1ads_config : unconfig
+ @./mkconfig $(@:_config=) arm mc9328 mx1ads
+
+#########################################################################
+## ARM720T Systems
+#########################################################################
ep7312_config : unconfig
@./mkconfig $(@:_config=) arm arm720t ep7312
+impa7_config : unconfig
+ @./mkconfig $(@:_config=) arm arm720t impa7
+
modnet50_config : unconfig
@./mkconfig $(@:_config=) arm arm720t modnet50
--- /dev/null
+#
+# Copyright (C) 2004 Arabella Software Ltd.
+# Yuli Barcohen <yuli@arabellasw.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := $(BOARD).o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright (C) 2004 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * Support for Analogue&Micro Adder boards family.
+ * Tested on AdderII and Adder87x.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/*
+ * SDRAM is single Samsung K4S643232F-T70 chip.
+ * Minimal CPU frequency is 40MHz.
+ */
+static uint sdram_table[] = {
+ /* Single read (offset 0x00 in UPM RAM) */
+ 0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00,
+ 0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04,
+
+ /* Burst read (offset 0x08 in UPM RAM) */
+ 0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00,
+ 0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44,
+ 0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35,
+ 0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35,
+
+ /* Single write (offset 0x18 in UPM RAM) */
+ 0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47,
+ 0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+ /* Burst write (offset 0x20 in UPM RAM) */
+ 0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
+ 0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04,
+ 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+ 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+ /* Refresh (offset 0x30 in UPM RAM) */
+ 0x1ff5fca4, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+ 0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04,
+ 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+ /* Exception (offset 0x3C in UPM RAM) */
+ 0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04
+};
+
+long int initdram (int board_type)
+{
+ long int msize = CFG_SDRAM_SIZE;
+ volatile immap_t *immap = (volatile immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+ upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint));
+
+ /* Configure SDRAM refresh */
+ memctl->memc_mptpr = MPTPR_PTP_DIV32; /* BRGCLK/32 */
+
+ memctl->memc_mamr = (94 << 24) | CFG_MAMR;
+ memctl->memc_mar = 0x0;
+ udelay(200);
+
+ /* Run precharge from location 0x15 */
+ memctl->memc_mcr = 0x80002115;
+ udelay(200);
+
+ /* Run 8 refresh cycles */
+ memctl->memc_mcr = 0x80002830;
+ udelay(200);
+
+ memctl->memc_mar = 0x88;
+ udelay(200);
+
+ /* Run MRS pattern from location 0x16 */
+ memctl->memc_mcr = 0x80002116;
+ udelay(200);
+
+ return msize;
+}
+
+int checkboard( void )
+{
+ puts("Board: Adder");
+#if defined(CONFIG_MPC885_FAMILY)
+ puts("87x\n");
+#elif defined(CONFIG_MPC866_FAMILY)
+ puts("II\n");
+#endif
+
+ return 0;
+}
--- /dev/null
+#
+# Copyright (C) 2004 Arabella Software Ltd.
+# Yuli Barcohen <yuli@arabellasw.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Analogue&Micro Adder boards family
+#
+TEXT_BASE = 0xFE000000
--- /dev/null
+/*
+ * (C) Copyright 2001-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified by Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc8xx/start.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ . = ALIGN(16);
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
+ENTRY(_start)
--- /dev/null
+#/*
+#* board/mx1ads/Makefile
+#*
+#* (c) Copyright 2004
+#* Techware Information Technology, Inc.
+#* http://www.techware.com.tw/
+#*
+#* Ming-Len Wu <minglen_wu@techware.com.tw>
+#*
+#* This program is free software; you can redistribute it and/or
+#* modify it under the terms of the GNU General Public License as
+#* published by the Free Software Foundation; either version 2 of
+#* the License, or (at your option) any later version.
+#*
+#* This program is distributed in the hope that it will be useful,
+#* but WITHOUT ANY WARRANTY; without even the implied warranty of
+#* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+#* GNU General Public License for more details.
+#*
+#* You should have received a copy of the GNU General Public License
+#* along with this program; if not, write to the Free Software
+#* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+#* MA 02111-1307 USA
+#*/
+
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := mx1ads.o syncflash.o
+SOBJS := memsetup.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- /dev/null
+#/*
+#* board/mx1ads/config.mk
+#*
+#* (c) Copyright 2004
+#* Techware Information Technology, Inc.
+#* http://www.techware.com.tw/
+#*
+#* Ming-Len Wu <minglen_wu@techware.com.tw>
+#*
+#* This program is free software; you can redistribute it and/or
+#* modify it under the terms of the GNU General Public License as
+#* published by the Free Software Foundation; either version 2 of
+#* the License, or (at your option) any later version.
+#*
+#* This program is distributed in the hope that it will be useful,
+#* but WITHOUT ANY WARRANTY; without even the implied warranty of
+#* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+#* GNU General Public License for more details.
+#*
+#* You should have received a copy of the GNU General Public License
+#* along with this program; if not, write to the Free Software
+#* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+#* MA 02111-1307 USA
+#*/
+
+
+TEXT_BASE = 0x08400000
+
--- /dev/null
+/*
+ * board/mx1ads/memsetup.S
+ *
+ * (c) Copyright 2004
+ * Techware Information Technology, Inc.
+ * http://www.techware.com.tw/
+ *
+ * Ming-Len Wu <minglen_wu@techware.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#define SDCTL0 0x221000
+#define SDCTL1 0x221004
+
+
+_TEXT_BASE:
+ .word TEXT_BASE
+
+.globl memsetup
+memsetup:
+/* memory controller init */
+
+ ldr r1, =SDCTL0
+
+/* Set Precharge Command */
+
+ ldr r3, =0x92120200
+/* ldr r3, =0x92120251
+*/
+ str r3, [r1]
+
+/* Issue Precharge All Commad */
+ ldr r3, =0x8200000
+ ldr r2, [r3]
+
+/* Set AutoRefresh Command */
+ ldr r3, =0xA2120200
+ str r3, [r1]
+
+/* Issue AutoRefresh Command */
+ ldr r3, =0x8000000
+ ldr r2, [r3]
+ ldr r2, [r3]
+ ldr r2, [r3]
+ ldr r2, [r3]
+ ldr r2, [r3]
+ ldr r2, [r3]
+ ldr r2, [r3]
+ ldr r2, [r3]
+
+/* Set Mode Register */
+ ldr r3, =0xB2120200
+ str r3, [r1]
+
+/* Issue Mode Register Command */
+ ldr r3, =0x08111800 /* Mode Register Value */
+ ldr r2, [r3]
+
+/* Set Normal Mode */
+ ldr r3, =0x82124200
+ str r3, [r1]
+
+/* everything is fine now */
+ mov pc, lr
+
--- /dev/null
+/*
+ * board/mx1ads/mx1ads.c
+ *
+ * (c) Copyright 2004
+ * Techware Information Technology, Inc.
+ * http://www.techware.com.tw/
+ *
+ * Ming-Len Wu <minglen_wu@techware.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <mc9328.h>
+
+/* ------------------------------------------------------------------------- */
+
+#define FCLK_SPEED 1
+
+#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
+#define M_MDIV 0xC3
+#define M_PDIV 0x4
+#define M_SDIV 0x1
+#elif FCLK_SPEED==1 /* Fout = 202.8MHz */
+#define M_MDIV 0xA1
+#define M_PDIV 0x3
+#define M_SDIV 0x1
+#endif
+
+#define USB_CLOCK 1
+
+#if USB_CLOCK==0
+#define U_M_MDIV 0xA1
+#define U_M_PDIV 0x3
+#define U_M_SDIV 0x1
+#elif USB_CLOCK==1
+#define U_M_MDIV 0x48
+#define U_M_PDIV 0x3
+#define U_M_SDIV 0x2
+#endif
+
+#if 0
+
+static inline void delay (unsigned long loops) {
+ __asm__ volatile ("1:\n"
+ "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0" (loops));
+}
+
+#endif
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+
+void SetAsynchMode(void) {
+ __asm__ (
+ "mrc p15,0,r0,c1,c0,0 \n"
+ "mov r2, #0xC0000000 \n"
+ "orr r0,r2,r0 \n"
+ "mcr p15,0,r0,c1,c0,0 \n"
+ );
+}
+
+static u32 mc9328sid;
+
+int board_init (void) {
+
+ DECLARE_GLOBAL_DATA_PTR;
+
+ volatile unsigned int tmp;
+
+ mc9328sid = MX1_SIDR;
+
+ MX1_GPCR = 0x000003AB; /* I/O pad driving strength */
+
+/* MX1_CS1U = 0x00000A00; */ /* SRAM initialization */
+/* MX1_CS1L = 0x11110601; */
+
+
+ MX1_MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */
+
+/* MX1_MPCTL0 = 0x003f1437; *//* setting for 192 MHz MCU PLL CLK */
+
+
+
+/* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and
+ * BCLK divider to 2 (i.e. BCLK to 48 MHz)
+ */
+ MX1_CSCR = 0xAF000403;
+
+ MX1_CSCR |= 0x00200000; /* Trigger the restart bit(bit 21) */
+ MX1_CSCR &= 0xFFFF7FFF; /* Program PRESC bit(bit 15) to 0 to divide-by-1 */
+
+/* setup cs4 for cs8900 ethernet */
+
+ MX1_CS4U = 0x00000F00; /* Initialize CS4 for CS8900 ethernet */
+ MX1_CS4L = 0x00001501;
+
+ MX1_GIUS_A &= 0xFF3FFFFF;
+ MX1_GPR_A &= 0xFF3FFFFF;
+
+ tmp = *(unsigned int *)(0x1500000C);
+ tmp = *(unsigned int *)(0x1500000C);
+
+/* setup timer 1 as system timer */
+
+ MX1_TPRER1 = 0x1f; /* divide by 32 */
+ MX1_TCTL1 = 0x19; /* clock in from 32k Osc. */
+
+
+ SetAsynchMode();
+
+ gd->bd->bi_arch_number = 160; /* Arch number of MX1ADS Board */
+
+ gd->bd->bi_boot_params = 0x08000100; /* adress of boot parameters */
+
+ icache_enable();
+ dcache_enable();
+
+/* set PERCLKs */
+ MX1_PCDR = 0x00000055; /* set PERCLKS */
+
+/* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes
+ * PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place
+ * all sources selected as normal interrupt
+ */
+ MX1_INTTYPEH = 0;
+ MX1_INTTYPEL = 0;
+
+ return 0;
+}
+
+
+int board_late_init(void) {
+
+ setenv("stdout", "serial");
+ setenv("stderr", "serial");
+
+ switch (mc9328sid) {
+ case 0x0005901d :
+ printf ("MX1ADS board with MC9328 MX1 (0L44N), Silicon ID 0x%08x \n\n",mc9328sid);
+ break;
+ case 0x04d4c01d :
+ printf ("MX1ADS board with MC9328 MXL (1L45N), Silicon ID 0x%08x \n\n",mc9328sid);
+ break;
+ case 0x00d4c01d :
+ printf ("MX1ADS board with MC9328 MXL (2L45N), Silicon ID 0x%08x \n\n",mc9328sid);
+ break;
+
+ default :
+ printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n",mc9328sid);
+ break;
+
+ }
+
+ return 0;
+}
+
+
+int dram_init (void) {
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
--- /dev/null
+/*
+ * board/mx1ads/syncflash.c
+ *
+ * (c) Copyright 2004
+ * Techware Information Technology, Inc.
+ * http://www.techware.com.tw/
+ *
+ * Ming-Len Wu <minglen_wu@techware.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mc9328.h>
+
+typedef unsigned long * p_u32;
+
+/* 4Mx16x2 IAM=0 CSD1 */
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/* Following Setting is for CSD1 */
+#define SFCTL 0x00221004
+#define reg_SFCTL __REG(SFCTL)
+
+#define SYNCFLASH_A10 (0x00100000)
+
+#define CMD_NORMAL (0x81020300) /* Normal Mode */
+#define CMD_PREC (CMD_NORMAL + 0x10000000) /* Precharge Command */
+#define CMD_AUTO (CMD_NORMAL + 0x20000000) /* Auto Refresh Command */
+#define CMD_LMR (CMD_NORMAL + 0x30000000) /* Load Mode Register Command */
+#define CMD_LCR (CMD_NORMAL + 0x60000000) /* LCR Command */
+#define CMD_PROGRAM (CMD_NORMAL + 0x70000000)
+
+#define MODE_REG_VAL (CFG_FLASH_BASE+0x0008CC00) /* Cas Latency 3 */
+
+/* LCR Command */
+#define LCR_READSTATUS (0x0001C000) /* 0x70 */
+#define LCR_ERASE_CONFIRM (0x00008000) /* 0x20 */
+#define LCR_ERASE_NVMODE (0x0000C000) /* 0x30 */
+#define LCR_PROG_NVMODE (0x00028000) /* 0xA0 */
+#define LCR_SR_CLEAR (0x00014000) /* 0x50 */
+
+
+/* Get Status register */
+u32 SF_SR(void) {
+ u32 tmp,tmp1;
+
+ reg_SFCTL = CMD_PROGRAM;
+ tmp = __REG(CFG_FLASH_BASE);
+
+ reg_SFCTL = CMD_NORMAL;
+
+ reg_SFCTL = CMD_LCR; /* Activate LCR Mode */
+ tmp1 = __REG(CFG_FLASH_BASE + LCR_SR_CLEAR);
+
+ return tmp;
+}
+
+/* check if SyncFlash is ready */
+u8 SF_Ready(void) {
+ u32 tmp;
+
+ tmp = SF_SR();
+
+ if ((tmp & 0x00800000) && (tmp & 0x001C0000)) {
+ printf ("SyncFlash Error code %08x\n",tmp);
+ };
+
+ if ((tmp & 0x00000080) && (tmp & 0x0000001C)) {
+ printf ("SyncFlash Error code %08x\n",tmp);
+
+ };
+
+ if (tmp == 0x00800080) /* Test Bit 7 of SR */
+ return 1;
+ else
+ return 0;
+}
+
+/* Issue the precharge all command */
+void SF_PrechargeAll(void) {
+
+ u32 tmp;
+
+ reg_SFCTL = CMD_PREC; /* Set Precharge Command */
+ tmp = __REG(CFG_FLASH_BASE + SYNCFLASH_A10); /* Issue Precharge All Command */
+
+}
+
+/* set SyncFlash to normal mode */
+void SF_Normal(void) {
+
+ SF_PrechargeAll();
+
+ reg_SFCTL = CMD_NORMAL;
+}
+
+/* Erase SyncFlash */
+void SF_Erase(u32 RowAddress) {
+ u32 tmp;
+
+ reg_SFCTL = CMD_NORMAL;
+ tmp = __REG(RowAddress);
+
+ reg_SFCTL = CMD_PREC;
+ tmp = __REG(RowAddress);
+
+ reg_SFCTL = CMD_LCR; /* Set LCR mode */
+ __REG(RowAddress + LCR_ERASE_CONFIRM) = 0; /* Issue Erase Setup Command */
+
+ reg_SFCTL = CMD_NORMAL; /* return to Normal mode */
+ __REG(RowAddress) = 0xD0D0D0D0; /* Confirm */
+
+ while(!SF_Ready());
+}
+
+
+void SF_NvmodeErase(void) {
+ SF_PrechargeAll();
+
+ reg_SFCTL = CMD_LCR; /* Set to LCR mode */
+ __REG(CFG_FLASH_BASE + LCR_ERASE_NVMODE) = 0; /* Issue Erase Nvmode Reg Command */
+
+ reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */
+ __REG(CFG_FLASH_BASE + LCR_ERASE_NVMODE) = 0xC0C0C0C0; /* Confirm */
+
+ while(!SF_Ready());
+}
+
+void SF_NvmodeWrite(void) {
+ SF_PrechargeAll();
+
+ reg_SFCTL = CMD_LCR; /* Set to LCR mode */
+ __REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0; /* Issue Program Nvmode reg command */
+
+ reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */
+ __REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0xC0C0C0C0; /* Confirm not needed */
+
+}
+
+
+/****************************************************************************************/
+
+ulong flash_init(void) {
+ int i, j;
+ u32 tmp;
+
+/* Turn on CSD1 for negating RESETSF of SyncFLash */
+
+ reg_SFCTL |= 0x80000000; /* enable CSD1 for SyncFlash */
+ udelay(200);
+
+ reg_SFCTL = CMD_LMR; /* Set Load Mode Register Command */
+ tmp = __REG(MODE_REG_VAL); /* Issue Load Mode Register Command */
+
+ SF_Normal();
+
+ i = 0;
+
+ flash_info[i].flash_id = FLASH_MAN_MT | FLASH_MT28S4M16LC;
+
+ flash_info[i].size = FLASH_BANK_SIZE;
+ flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+
+ memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+
+ for (j = 0; j < flash_info[i].sector_count; j++) {
+ flash_info[i].start[j] = CFG_FLASH_BASE + j * 0x00100000;
+ }
+
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_FLASH_BASE,
+ CFG_FLASH_BASE + monitor_flash_len - 1,
+ &flash_info[0]);
+
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+ &flash_info[0]);
+
+ return FLASH_BANK_SIZE;
+}
+
+
+void flash_print_info (flash_info_t *info) {
+
+ int i;
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case (FLASH_MAN_MT & FLASH_VENDMASK):
+ printf("Micron: ");
+ break;
+ default:
+ printf("Unknown Vendor ");
+ break;
+ }
+
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case (FLASH_MT28S4M16LC & FLASH_TYPEMASK):
+ printf("2x FLASH_MT28S4M16LC (16MB Total)\n");
+ break;
+ default:
+ printf("Unknown Chip Type\n");
+ return;
+ break;
+ }
+
+ printf(" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf(" Sector Start Addresses: ");
+
+ for (i = 0; i < info->sector_count; i++) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+
+ printf (" %08lX%s", info->start[i],
+ info->protect[i] ? " (RO)" : " ");
+ }
+
+ printf ("\n");
+}
+
+
+/*-----------------------------------------------------------------------*/
+
+int flash_erase (flash_info_t *info, int s_first, int s_last) {
+ int iflag, cflag, prot, sect;
+ int rc = ERR_OK;
+
+/* first look for protection bits */
+
+ if (info->flash_id == FLASH_UNKNOWN)
+ return ERR_UNKNOWN_FLASH_TYPE;
+
+ if ((s_first < 0) || (s_first > s_last))
+ return ERR_INVAL;
+
+ if ((info->flash_id & FLASH_VENDMASK) != (FLASH_MAN_MT & FLASH_VENDMASK))
+ return ERR_UNKNOWN_FLASH_VENDOR;
+
+ prot = 0;
+
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect])
+ prot++;
+ }
+
+ if (prot) {
+ printf("protected!\n");
+ return ERR_PROTECTED;
+ }
+/*
+ * Disable interrupts which might cause a timeout
+ * here. Remember that our exception vectors are
+ * at address 0 in the flash, and we don't want a
+ * (ticker) exception to happen while the flash
+ * chip is in programming mode.
+ */
+
+ cflag = icache_status();
+ icache_disable();
+ iflag = disable_interrupts();
+
+/* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last && !ctrlc(); sect++) {
+
+ printf("Erasing sector %2d ... ", sect);
+
+/* arm simple, non interrupt dependent timer */
+
+ reset_timer_masked();
+
+ SF_NvmodeErase();
+ SF_NvmodeWrite();
+
+ SF_Erase(CFG_FLASH_BASE + (0x0100000 * sect));
+ SF_Normal();
+
+ printf("ok.\n");
+ }
+
+ if (ctrlc())
+ printf("User Interrupt!\n");
+
+ if (iflag)
+ enable_interrupts();
+
+ if (cflag)
+ icache_enable();
+
+ return rc;
+}
+
+
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) {
+ int i;
+
+ for(i = 0; i < cnt; i += 4) {
+
+ SF_PrechargeAll();
+
+ reg_SFCTL = CMD_PROGRAM; /* Enter SyncFlash Program mode */
+ __REG(addr + i) = __REG((u32)src + i);
+
+ while(!SF_Ready());
+ }
+
+ SF_Normal();
+
+ return ERR_OK;
+}
+
+
--- /dev/null
+/*
+ * board/mx1ads/u-boot.lds
+ *
+ * (c) Copyright 2004
+ * Techware Information Technology, Inc.
+ * http://www.techware.com.tw/
+ *
+ * Ming-Len Wu <minglen_wu@techware.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/mc9328/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
--- /dev/null
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(CPU).a
+
+START = start.o
+OBJS = serial.o interrupts.o cpu.o
+
+all: .depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
+ -mshort-load-bytes -msoft-float
+
+PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * CPU specific code
+ */
+
+#include <common.h>
+#include <command.h>
+#include <arm920t.h>
+
+/* read co-processor 15, register #1 (control register) */
+static unsigned long read_p15_c1 (void)
+{
+ unsigned long value;
+
+ __asm__ __volatile__(
+ "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n"
+ : "=r" (value)
+ :
+ : "memory");
+
+#ifdef MMU_DEBUG
+ printf ("p15/c1 is = %08lx\n", value);
+#endif
+ return value;
+}
+
+/* write to co-processor 15, register #1 (control register) */
+static void write_p15_c1 (unsigned long value)
+{
+#ifdef MMU_DEBUG
+ printf ("write %08lx to p15/c1\n", value);
+#endif
+ __asm__ __volatile__(
+ "mcr p15, 0, %0, c1, c0, 0 @ write it back\n"
+ :
+ : "r" (value)
+ : "memory");
+
+ read_p15_c1 ();
+}
+
+static void cp_delay (void)
+{
+ volatile int i;
+
+ /* copro seems to need some delay between reading and writing */
+ for (i = 0; i < 100; i++);
+}
+
+/* See also ARM Ref. Man. */
+#define C1_MMU (1<<0) /* mmu off/on */
+#define C1_ALIGN (1<<1) /* alignment faults off/on */
+#define C1_DC (1<<2) /* dcache off/on */
+#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */
+#define C1_SYS_PROT (1<<8) /* system protection */
+#define C1_ROM_PROT (1<<9) /* ROM protection */
+#define C1_IC (1<<12) /* icache off/on */
+#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */
+#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */
+
+int cpu_init (void)
+{
+ /*
+ * setup up stacks if necessary
+ */
+#ifdef CONFIG_USE_IRQ
+ DECLARE_GLOBAL_DATA_PTR;
+
+ IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
+ FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
+#endif
+ return 0;
+}
+
+int cleanup_before_linux (void)
+{
+ /*
+ * this function is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we turn off caches etc ...
+ */
+
+ unsigned long i;
+
+ disable_interrupts ();
+
+ /* turn off I/D-cache */
+ asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+ i &= ~(C1_DC | C1_IC);
+ asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+
+ /* flush I/D-cache */
+ i = 0;
+ asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
+ return (0);
+}
+
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ extern void reset_cpu (ulong addr);
+
+ disable_interrupts ();
+ reset_cpu (0);
+ /*NOTREACHED*/
+ return (0);
+}
+
+void icache_enable (void)
+{
+ ulong reg;
+
+ reg = read_p15_c1 ();
+ cp_delay ();
+ write_p15_c1 (reg | C1_IC);
+}
+
+void icache_disable (void)
+{
+ ulong reg;
+
+ reg = read_p15_c1 ();
+ cp_delay ();
+ write_p15_c1 (reg & ~C1_IC);
+}
+
+int icache_status (void)
+{
+ return (read_p15_c1 () & C1_IC) != 0;
+}
+
+#ifdef USE_920T_MMU
+/* It makes no sense to use the dcache if the MMU is not enabled */
+void dcache_enable (void)
+{
+ ulong reg;
+
+ reg = read_p15_c1 ();
+ cp_delay ();
+ write_p15_c1 (reg | C1_DC);
+}
+
+void dcache_disable (void)
+{
+ ulong reg;
+
+ reg = read_p15_c1 ();
+ cp_delay ();
+ reg &= ~C1_DC;
+ write_p15_c1 (reg);
+}
+
+int dcache_status (void)
+{
+ return (read_p15_c1 () & C1_DC) != 0;
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <arm920t.h>
+#include <mc9328.h>
+
+#include <asm/proc-armv/ptrace.h>
+
+extern void reset_cpu(ulong addr);
+int timer_load_val = 0;
+
+#ifdef CONFIG_USE_IRQ
+/* enable IRQ interrupts */
+void enable_interrupts (void)
+{
+ unsigned long temp;
+ __asm__ __volatile__("mrs %0, cpsr\n"
+ "bic %0, %0, #0x80\n"
+ "msr cpsr_c, %0"
+ : "=r" (temp)
+ :
+ : "memory");
+}
+
+
+/*
+ * disable IRQ/FIQ interrupts
+ * returns true if interrupts had been enabled before we disabled them
+ */
+int disable_interrupts (void)
+{
+ unsigned long old,temp;
+ __asm__ __volatile__("mrs %0, cpsr\n"
+ "orr %1, %0, #0xc0\n"
+ "msr cpsr_c, %1"
+ : "=r" (old), "=r" (temp)
+ :
+ : "memory");
+ return (old & 0x80) == 0;
+}
+#else
+void enable_interrupts (void)
+{
+ return;
+}
+int disable_interrupts (void)
+{
+ return 0;
+}
+#endif
+
+
+void bad_mode (void)
+{
+ panic ("Resetting CPU ...\n");
+ reset_cpu (0);
+}
+
+void show_regs (struct pt_regs *regs)
+{
+ unsigned long flags;
+ const char *processor_modes[] = {
+ "USER_26", "FIQ_26", "IRQ_26", "SVC_26",
+ "UK4_26", "UK5_26", "UK6_26", "UK7_26",
+ "UK8_26", "UK9_26", "UK10_26", "UK11_26",
+ "UK12_26", "UK13_26", "UK14_26", "UK15_26",
+ "USER_32", "FIQ_32", "IRQ_32", "SVC_32",
+ "UK4_32", "UK5_32", "UK6_32", "ABT_32",
+ "UK8_32", "UK9_32", "UK10_32", "UND_32",
+ "UK12_32", "UK13_32", "UK14_32", "SYS_32",
+ };
+
+ flags = condition_codes (regs);
+
+ printf ("pc : [<%08lx>] lr : [<%08lx>]\n"
+ "sp : %08lx ip : %08lx fp : %08lx\n",
+ instruction_pointer (regs),
+ regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
+ printf ("r10: %08lx r9 : %08lx r8 : %08lx\n",
+ regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
+ printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
+ regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
+ printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
+ regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
+ printf ("Flags: %c%c%c%c",
+ flags & CC_N_BIT ? 'N' : 'n',
+ flags & CC_Z_BIT ? 'Z' : 'z',
+ flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
+ printf (" IRQs %s FIQs %s Mode %s%s\n",
+ interrupts_enabled (regs) ? "on" : "off",
+ fast_interrupts_enabled (regs) ? "on" : "off",
+ processor_modes[processor_mode (regs)],
+ thumb_mode (regs) ? " (T)" : "");
+}
+
+void do_undefined_instruction (struct pt_regs *pt_regs)
+{
+ printf ("undefined instruction\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_software_interrupt (struct pt_regs *pt_regs)
+{
+ printf ("software interrupt\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_prefetch_abort (struct pt_regs *pt_regs)
+{
+ printf ("prefetch abort\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_data_abort (struct pt_regs *pt_regs)
+{
+ printf ("data abort\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_not_used (struct pt_regs *pt_regs)
+{
+ printf ("not used\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_fiq (struct pt_regs *pt_regs)
+{
+ printf ("fast interrupt request\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_irq (struct pt_regs *pt_regs)
+{
+ printf ("interrupt request\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+
+int interrupt_init (void)
+{
+
+/* we don't use interrupt */
+ return(0);
+}
+
+/*
+ * timer without interrupts
+ */
+
+void reset_timer (void)
+{
+ reset_timer_masked ();
+}
+
+ulong get_timer (ulong base)
+{
+ return get_timer_masked ();
+}
+
+void set_timer (ulong t)
+{
+/* Nop */
+}
+
+void udelay (unsigned long usec)
+{
+ udelay_masked (usec);
+}
+
+void reset_timer_masked (void)
+{
+ u32 tmp;
+ MX1_TCTL1 = 0x09;
+ tmp = 0x1f; /* a little delay for timer to reset */
+ MX1_TPRER1 = 0x1f;
+ MX1_TCTL1 = 0x19;
+}
+
+ulong get_timer_masked (void)
+{
+ return MX1_TCN1;
+}
+
+void udelay_masked (unsigned long usec)
+{
+ ulong tmo;
+
+ tmo = usec / 1000;
+ tmo *= CFG_HZ;
+ tmo /= 1000;
+
+ reset_timer_masked ();
+
+ while (get_timer_masked () < tmo);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+
+ulong get_tbclk (void) {
+ return CFG_HZ;
+}
+
--- /dev/null
+/*
+ * cpu/mc9328/serial.c
+ *
+ * (c) Copyright 2004
+ * Techware Information Technology, Inc.
+ * http://www.techware.com.tw/
+ *
+ * Ming-Len Wu <minglen_wu@techware.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <mc9328.h>
+
+#if defined(CONFIG_UART1)
+/* GPIO PORT B */
+
+#define reg_GIUS MX1_GIUS_C
+#define reg_GPR MX1_GPR_B
+#define GPIO_MASK 0xFFFFE1FF
+#define UART_BASE 0x00206000
+
+
+#elif defined (CONFIG_UART2)
+/* GPIO PORT C */
+
+#define reg_GIUS MX1_GIUS_C
+#define reg_GPR MX1_GPR_C
+#define GPIO_MASK 0x0FFFFFFF
+#define UART_BASE 0x207000
+
+#endif
+
+#define reg_URXD (*((volatile u32 *)(UART_BASE+0x00)))
+#define reg_UTXD (*((volatile u32 *)(UART_BASE+0x40)))
+#define reg_UCR1 (*((volatile u32 *)(UART_BASE+0x80)))
+#define reg_UCR2 (*((volatile u32 *)(UART_BASE+0x84)))
+#define reg_UCR3 (*((volatile u32 *)(UART_BASE+0x88)))
+#define reg_UCR4 (*((volatile u32 *)(UART_BASE+0x8C)))
+#define reg_UFCR (*((volatile u32 *)(UART_BASE+0x90)))
+#define reg_USR1 (*((volatile u32 *)(UART_BASE+0x94)))
+#define reg_USR2 (*((volatile u32 *)(UART_BASE+0x98)))
+#define reg_UESC (*((volatile u32 *)(UART_BASE+0x9C)))
+#define reg_UTIM (*((volatile u32 *)(UART_BASE+0xA0)))
+#define reg_UBIR (*((volatile u32 *)(UART_BASE+0xA4)))
+#define reg_UBMR (*((volatile u32 *)(UART_BASE+0xA8)))
+#define reg_UBRC (*((volatile u32 *)(UART_BASE+0xAC)))
+
+#define TXFE_MASK 0x4000 /* Tx buffer empty */
+#define RDR_MASK 0x0001 /* receive data ready */
+
+
+void serial_setbrg (void) {
+
+/* config I/O pins for UART */
+
+ reg_GIUS &= GPIO_MASK;
+ reg_GPR &= GPIO_MASK;
+
+/* config UART */
+
+ reg_UCR1 = 5;
+ reg_UCR2 = 0x4027;
+ reg_UCR4 = 1;
+ reg_UFCR = 0xA81;
+
+ reg_UBIR = 0xF;
+ reg_UBMR = 0x8A;
+ reg_UBRC = 8;
+}
+
+
+
+/*
+ * Initialise the serial port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ *
+ */
+
+int serial_init (void) {
+ serial_setbrg ();
+
+ return (0);
+}
+
+
+
+/*
+ * Read a single byte from the serial port. Returns 1 on success, 0
+ * otherwise. When the function is succesfull, the character read is
+ * written into its argument c.
+ */
+int serial_getc (void) {
+
+ while (!(reg_USR2 & RDR_MASK)) ; /* wait until RDR bit set */
+
+ return (u8)reg_URXD;
+}
+
+
+/*
+ * Output a single byte to the serial port.
+ */
+void serial_putc (const char c) {
+
+ while (!(reg_USR2 & TXFE_MASK)); /* wait until TXFE bit set */
+
+ reg_UTXD = (u16) c;
+
+ if (c == '\n') { /* carriage return ? append line-feed */
+ while (!(reg_USR2 & TXFE_MASK)); /* wait until TXFE bit set */
+ reg_UTXD = '\r';
+ }
+
+}
+
+
+/*
+ * Test whether a character is in the RX buffer
+ */
+int serial_tstc (void) {
+ return reg_USR2 & RDR_MASK;
+}
+
+
+void serial_puts (const char *s) {
+ while (*s) {
+ serial_putc (*s++);
+ }
+}
+
--- /dev/null
+/*
+ * armboot - Startup Code for ARM920 CPU-core
+ *
+ * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
+ * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
+ * Copyright (c) 2002 Gary Jennejohn <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/*
+ *************************************************************************
+ *
+ * Jump vector table as in table 3.1 in [1]
+ *
+ *************************************************************************
+ */
+
+
+.globl _start
+_start: b reset
+ ldr pc, _undefined_instruction
+ ldr pc, _software_interrupt
+ ldr pc, _prefetch_abort
+ ldr pc, _data_abort
+ ldr pc, _not_used
+ ldr pc, _irq
+ ldr pc, _fiq
+
+_undefined_instruction: .word undefined_instruction
+_software_interrupt: .word software_interrupt
+_prefetch_abort: .word prefetch_abort
+_data_abort: .word data_abort
+_not_used: .word not_used
+_irq: .word irq
+_fiq: .word fiq
+
+ .balignl 16,0xdeadbeef
+
+
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from memory!
+ * relocate armboot to ram
+ * setup stack
+ * jump to second stage
+ *
+ *************************************************************************
+ */
+
+_TEXT_BASE:
+ .word TEXT_BASE
+
+.globl _armboot_start
+_armboot_start:
+ .word _start
+
+/*
+ * These are defined in the board-specific linker script.
+ */
+.globl _bss_start
+_bss_start:
+ .word __bss_start
+
+.globl _bss_end
+_bss_end:
+ .word _end
+
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+ .word 0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+ .word 0x0badc0de
+#endif
+
+
+/*
+ * the actual reset code
+ */
+
+reset:
+ /*
+ * set the cpu to SVC32 mode
+ */
+ mrs r0,cpsr
+ bic r0,r0,#0x1f
+ orr r0,r0,#0xd3
+ msr cpsr,r0
+
+ /*
+ * we do sys-critical inits only at reboot,
+ * not when booting from ram!
+ */
+#ifdef CONFIG_INIT_CRITICAL
+ bl cpu_init_crit
+#endif
+
+relocate: /* relocate U-Boot to RAM */
+ adr r0, _start /* r0 <- current position of code */
+ ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
+ cmp r0, r1 /* don't reloc during debug */
+ beq stack_setup
+
+ ldr r2, _armboot_start
+ ldr r3, _bss_start
+ sub r2, r3, r2 /* r2 <- size of armboot */
+ add r2, r0, r2 /* r2 <- source end address */
+
+copy_loop:
+ ldmia r0!, {r3-r10} /* copy from source address [r0] */
+ stmia r1!, {r3-r10} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end addreee [r2] */
+ ble copy_loop
+
+ /* Set up the stack */
+stack_setup:
+ ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
+ sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
+ sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
+#ifdef CONFIG_USE_IRQ
+ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
+#endif
+ sub sp, r0, #12 /* leave 3 words for abort-stack */
+
+clear_bss:
+ ldr r0, _bss_start /* find start of bss segment */
+ ldr r1, _bss_end /* stop here */
+ mov r2, #0x00000000 /* clear */
+
+clbss_l:str r2, [r0] /* clear loop... */
+ add r0, r0, #4
+ cmp r0, r1
+ bne clbss_l
+
+ ldr pc, _start_armboot
+
+_start_armboot: .word start_armboot
+
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+
+
+cpu_init_crit:
+ /*
+ * flush v4 I/D caches
+ */
+ mov r0, #0
+ mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
+ mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
+
+ /*
+ * disable MMU stuff and caches
+ */
+ mrc p15, 0, r0, c1, c0, 0
+ bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
+ bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
+ orr r0, r0, #0x00000002 @ set bit 2 (A) Align
+ orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
+ mcr p15, 0, r0, c1, c0, 0
+
+
+ /*
+ * before relocating, we have to setup RAM timing
+ * because memory timing is board-dependend, you will
+ * find a memsetup.S in your board directory.
+ */
+ mov ip, lr
+ bl memsetup
+ mov lr, ip
+
+ mov pc, lr
+
+
+/*
+ *************************************************************************
+ *
+ * Interrupt handling
+ *
+ *************************************************************************
+ */
+
+@
+@ IRQ stack frame.
+@
+#define S_FRAME_SIZE 72
+
+#define S_OLD_R0 68
+#define S_PSR 64
+#define S_PC 60
+#define S_LR 56
+#define S_SP 52
+
+#define S_IP 48
+#define S_FP 44
+#define S_R10 40
+#define S_R9 36
+#define S_R8 32
+#define S_R7 28
+#define S_R6 24
+#define S_R5 20
+#define S_R4 16
+#define S_R3 12
+#define S_R2 8
+#define S_R1 4
+#define S_R0 0
+
+#define MODE_SVC 0x13
+#define I_BIT 0x80
+
+/*
+ * use bad_save_user_regs for abort/prefetch/undef/swi ...
+ * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
+ */
+
+ .macro bad_save_user_regs
+ sub sp, sp, #S_FRAME_SIZE
+ stmia sp, {r0 - r12} @ Calling r0-r12
+ ldr r2, _armboot_start
+ sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+ sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
+ ldmia r2, {r2 - r3} @ get pc, cpsr
+ add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
+
+ add r5, sp, #S_SP
+ mov r1, lr
+ stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
+ mov r0, sp
+ .endm
+
+ .macro irq_save_user_regs
+ sub sp, sp, #S_FRAME_SIZE
+ stmia sp, {r0 - r12} @ Calling r0-r12
+ add r8, sp, #S_PC
+ stmdb r8, {sp, lr}^ @ Calling SP, LR
+ str lr, [r8, #0] @ Save calling PC
+ mrs r6, spsr
+ str r6, [r8, #4] @ Save CPSR
+ str r0, [r8, #8] @ Save OLD_R0
+ mov r0, sp
+ .endm
+
+ .macro irq_restore_user_regs
+ ldmia sp, {r0 - lr}^ @ Calling r0 - lr
+ mov r0, r0
+ ldr lr, [sp, #S_PC] @ Get PC
+ add sp, sp, #S_FRAME_SIZE
+ subs pc, lr, #4 @ return & move spsr_svc into cpsr
+ .endm
+
+ .macro get_bad_stack
+ ldr r13, _armboot_start @ setup our mode stack
+ sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+ sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
+
+ str lr, [r13] @ save caller lr / spsr
+ mrs lr, spsr
+ str lr, [r13, #4]
+
+ mov r13, #MODE_SVC @ prepare SVC-Mode
+ @ msr spsr_c, r13
+ msr spsr, r13
+ mov lr, pc
+ movs pc, lr
+ .endm
+
+ .macro get_irq_stack @ setup IRQ stack
+ ldr sp, IRQ_STACK_START
+ .endm
+
+ .macro get_fiq_stack @ setup FIQ stack
+ ldr sp, FIQ_STACK_START
+ .endm
+
+/*
+ * exception handlers
+ */
+ .align 5
+undefined_instruction:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_undefined_instruction
+
+ .align 5
+software_interrupt:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_software_interrupt
+
+ .align 5
+prefetch_abort:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_prefetch_abort
+
+ .align 5
+data_abort:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_data_abort
+
+ .align 5
+not_used:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_not_used
+
+#ifdef CONFIG_USE_IRQ
+
+ .align 5
+irq:
+ get_irq_stack
+ irq_save_user_regs
+ bl do_irq
+ irq_restore_user_regs
+
+ .align 5
+fiq:
+ get_fiq_stack
+ /* someone ought to write a more effiction fiq_save_user_regs */
+ irq_save_user_regs
+ bl do_fiq
+ irq_restore_user_regs
+
+#else
+
+ .align 5
+irq:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_irq
+
+ .align 5
+fiq:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_fiq
+
+#endif
+
+ .align 5
+.globl reset_cpu
+reset_cpu:
+ mov ip, #0
+ mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
+ mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
+ mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
+ bic ip, ip, #0x000f @ ............wcam
+ bic ip, ip, #0x2100 @ ..v....s........
+ mcr p15, 0, ip, c1, c0, 0 @ ctrl register
+ mov pc, r0
--- /dev/null
+/*
+ * Copyright (C) 2004 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * Support for Analogue&Micro Adder boards family.
+ * Tested on AdderII and Adder87x.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#if !defined(CONFIG_MPC875) && !defined(CONFIG_MPC852T)
+#define CONFIG_MPC875
+#endif
+
+#define CONFIG_ADDER /* Analogue&Micro Adder board */
+
+#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
+#define CONFIG_BAUDRATE 38400
+
+#define CONFIG_FEC_ENET /* Ethernet is on FEC */
+#ifdef CONFIG_FEC_ENET
+#define CFG_DISCOVER_PHY
+#define FEC_ENET
+#endif /* CONFIG_FEC_ENET */
+
+#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
+ | CFG_CMD_DHCP \
+ | CFG_CMD_IMMAP \
+ | CFG_CMD_MII \
+ | CFG_CMD_PING \
+ )
+
+/* This must be included AFTER the definition of CONFIG_COMMANDS */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */
+#define CONFIG_BOOTCOMMAND "bootm fe040000" /* Autoboot command */
+#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw"
+
+#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */
+#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#define CFG_LONGHELP /* #undef to save memory */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* Max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_LOAD_ADDR 0x100000 /* Default load address */
+
+#define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * RAM configuration (note that CFG_SDRAM_BASE must be zero)
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_SDRAM_SIZE 0x00800000 /* 8 Mbyte */
+
+#define CFG_OR1_PRELIM (0xFF800000 | OR_CSNT_SAM | OR_ACS_DIV2)
+#define CFG_BR1_PRELIM (CFG_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V)
+
+#define CFG_MAMR 0x00802114
+
+#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
+#define CFG_MEMTEST_END 0x00700000 /* 1 ... 7 MB in SDRAM */
+
+#define CFG_RESET_ADDRESS 0x09900000
+
+/*-----------------------------------------------------------------------
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 KB for Monitor */
+#ifdef CONFIG_BZIP2
+#define CFG_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */
+#else
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
+#endif /* CONFIG_BZIP2 */
+
+/*-----------------------------------------------------------------------
+ * Flash organisation
+ */
+#define CFG_FLASH_BASE 0xFE000000
+#define CFG_FLASH_CFI /* The flash is CFI compatible */
+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
+#define CFG_MAX_FLASH_SECT 128 /* Max num of sects on one chip */
+
+/* Environment is in flash */
+#define CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+
+#define CFG_OR0_PRELIM 0xFF000774
+#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_MS_GPCM | BR_V)
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Map Register
+ */
+#define CFG_IMMR 0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR CFG_IMMR
+#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
+#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Configuration registers
+ */
+#ifdef CONFIG_WATCHDOG
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \
+ SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | \
+ SYPCR_SWP)
+#else
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \
+ SYPCR_SWF | SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+#define CFG_SIUMCR (SIUMCR_MLRC01 | SIUMCR_DBGC11)
+
+/* TBSCR - Time Base Status and Control Register */
+#define CFG_TBSCR (TBSCR_TBF | TBSCR_TBE)
+
+/* PISCR - Periodic Interrupt Status and Control */
+#define CFG_PISCR (PISCR_PS | PISCR_PITF)
+
+/* PLPRCR - PLL, Low-Power, and Reset Control Register */
+/* #define CFG_PLPRCR PLPRCR_TEXPS */
+
+/* SCCR - System Clock and reset Control Register */
+#define SCCR_MASK SCCR_EBDF11
+#define CFG_SCCR SCCR_RTSEL
+
+#define CFG_DER 0
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx chips */
+
+/*-----------------------------------------------------------------------
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from flash */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * include/configs/mx1ads.h
+ *
+ * (c) Copyright 2004
+ * Techware Information Technology, Inc.
+ * http://www.techware.com.tw/
+ *
+ * Ming-Len Wu <minglen_wu@techware.com.tw>
+ *
+ * This is the Configuration setting for Motorola MX1ADS board
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * If we are developing, we might want to start armboot from ram
+ * so we MUST NOT initialize critical regs like mem-timing ...
+ */
+#define CONFIG_INIT_CRITICAL /* undef for developing */
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
+#define CONFIG_MC9328 1 /* It's a Motorola MC9328 SoC */
+#define CONFIG_MX1ADS 1 /* on a Motorola MX1ADS Board */
+
+#define BOARD_LATE_INIT 1
+
+
+#define USE_920T_MMU 1
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+#if 0
+#define CFG_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */
+#define CFG_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */
+#define CFG_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */
+#endif
+
+/*
+ * Size of malloc() pool
+ */
+
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+
+/*
+ * CS8900 Ethernet drivers
+ */
+#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */
+#define CS8900_BASE 0x15000300
+#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
+
+/*
+ * select serial console configuration
+ */
+
+#define CONFIG_UART1 1
+/* #define CONFIG_UART2 1 */
+
+#define CONFIG_BAUDRATE 115200
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#define CONFIG_COMMANDS \
+ (CONFIG_CMD_DFL | \
+ CFG_CMD_CACHE | \
+ /*CFG_CMD_NAND |*/ \
+ /*CFG_CMD_EEPROM |*/ \
+ /*CFG_CMD_I2C |*/ \
+ /*CFG_CMD_USB |*/ \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_ELF)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTARGS "root=/dev/docbp mem=48M"
+#define CONFIG_ETHADDR 08:00:3e:26:0a:5c
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.0.22
+#define CONFIG_SERVERIP 192.168.0.11
+#define CONFIG_BOOTFILE "mx1ads"
+/*#define CONFIG_BOOTCOMMAND "tftp; bootm" */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
+ /* what's this ? it's not used anywhere */
+#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CFG_HUSH_PARSER 1
+#define CFG_PROMPT_HUSH_PS2 "> "
+
+#define CFG_LONGHELP /* undef to save memory */
+
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT "MX1ADS$ " /* Monitor Command Prompt */
+#else
+#define CFG_PROMPT "MX1ADS=> " /* Monitor Command Prompt */
+#endif
+
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+ /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x09000000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0AF00000 /* 63 MB in DRAM */
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR 0x08800000 /* default load address */
+
+
+#define CFG_HZ 1000
+
+/* valid baudrates */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+
+
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */
+#define PHYS_SDRAM_1 0x08000000 /* SDRAM on CSD0 */
+#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
+
+#define CFG_MAX_FLASH_BANKS 1 /* 1 bank of SyncFlash */
+#define CFG_FLASH_BASE 0x0C000000 /* SyncFlash on CSD1 */
+#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */
+
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+
+#define CONFIG_SYNCFLASH 1
+#define PHYS_FLASH_SIZE 0x01000000
+#define CFG_MAX_FLASH_SECT (16)
+#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x00ff0000)
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_SIZE 0x0f000 /* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE 0x100000
+#endif /* __CONFIG_H */
#define FLASH_FUJLV650 0x00B4 /* Fujitsu MBM 29LV650UE/651UE */
+#define FLASH_MT28S4M16LC 0x00B5 /* Micron MT28S4M16LC */
#define FLASH_UNKNOWN 0xFFFF /* unknown flash type */
--- /dev/null
+/*
+ * include/mc9328.h
+ *
+ * (c) Copyright 2004
+ * Techware Information Technology, Inc.
+ * http://www.techware.com.tw/
+ *
+ * Ming-Len Wu <minglen_wu@techware.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#ifndef __MC9328_H__
+#define __MC9328_H__
+
+typedef volatile unsigned long VU32;
+typedef VU32 * P_VU32;
+
+#define __REG(x) (*((volatile u32 *)(x)))
+
+
+/*
+ * MX1 Chip selects & internal memory's
+ */
+
+
+#define MX1_DMI_PHYS 0x00000000 /* double map image */
+#define MX1_BROM_PHYS 0x00100000 /* Bootstrape ROM */
+#define MX1_ESRAM_PHYS 0x00300000 /* Embedded SRAM (128KB)*/
+
+#define MX1_CSD0_PHYS 0x08000000 /* CSD0 64MB (SDRAM) */
+#define MX1_CSD1_PHYS 0x0C000000 /* CSD1 64MB (SDRAM) */
+#define MX1_CS0_PHYS 0x10000000 /* CS0 32MB (Flash) */
+#define MX1_CS1_PHYS 0x12000000 /* CS1 16MB (Flash) */
+#define MX1_CS2_PHYS 0x13000000 /* CS2 16MB (Ext SRAM) */
+#define MX1_CS3_PHYS 0x14000000 /* CS3 16MB (Spare) */
+#define MX1_CS4_PHYS 0x15000000 /* CS4 16MB (Spare) */
+#define MX1_CS5_PHYS 0x16000000 /* CS5 16MB (Spare) */
+
+
+
+/*
+ * MX1 Watchdog registers
+ */
+
+#define MX1_WCR __REG(0x00201000) /* Watchdog Control Register */
+#define MX1_WSR __REG(0x00201004) /* Watchdog Service Register */
+#define MX1_WSTR __REG(0x00201008) /* Watchdog Status Register */
+
+
+
+/*
+ * MX1 Timer registers
+ */
+
+#define MX1_TCTL1 __REG(0x00202000) /* Timer 1 Control Register */
+#define MX1_TPRER1 __REG(0x00202004) /* Timer 1 Prescaler Register */
+#define MX1_TCMP1 __REG(0x00202008) /* Timer 1 Compare Register */
+#define MX1_TCR1 __REG(0x0020200C) /* Timer 1 Capture Register */
+#define MX1_TCN1 __REG(0x00202010) /* Timer 1 Counter Register */
+#define MX1_TSTAT1 __REG(0x00202014) /* Timer 1 Status Register */
+
+
+#define MX1_TCTL2 __REG(0x00203000) /* Timer 2 Control Register */
+#define MX1_TPRER2 __REG(0x00203004) /* Timer 2 Prescaler Register */
+#define MX1_TCMP2 __REG(0x00203008) /* Timer 2 Compare Register */
+#define MX1_TCR2 __REG(0x0020300C) /* Timer 2 Capture Register */
+#define MX1_TCN2 __REG(0x00203010) /* Timer 2 Counter Register */
+#define MX1_TSTAT2 __REG(0x00203014) /* Timer 2 Status Register */
+
+
+
+/*
+ * MX1 RTC registers
+ */
+
+#define MX1_HOURMIN __REG(0x00204000) /* RTC Hour & Min Counter Registers */
+#define MX1_SECONDS __REG(0x00204004) /* RTC Seconds Counter Registers */
+#define MX1_ALRM_HM __REG(0x00204008) /* RTC Hour & Min Alarm Registers */
+#define MX1_ALRM_SEC __REG(0x0020400C) /* RTC Seconds Alarm Registers */
+#define MX1_RCCTL __REG(0x00204010) /* RTC Control Registers */
+#define MX1_RTCISR __REG(0x00204014) /* RTC Interrupt Status Registers */
+#define MX1_RTCIENR __REG(0x00204018) /* RTC Interrupt Enable Registers */
+#define MX1_STPWCH __REG(0x0020401C) /* RTC Stopwatch Minutes Registers */
+#define MX1_DAYR __REG(0x00204020) /* RTC Days Counter Registers */
+#define MX1_DAYALARM __REG(0x00204020) /* RTC Day Alarm Registers */
+
+
+/*
+ * MX1 LCD Controller registers
+ */
+
+#define MX1_SSA __REG(0x00205000) /* Screen Start Address Register */
+#define MX1_SIZE __REG(0x00205004) /* Size Register */
+#define MX1_VPW __REG(0x00205008) /* Virtual Page Width Register */
+#define MX1_CPOS __REG(0x0020500C) /* LCD Cursor Position Register */
+#define MX1_LCWHB __REG(0x00205010) /* LCD Cursor Width Height & Blink Register */
+#define MX1_LCHCC __REG(0x00205014) /* LCD Color Cursor Mapping Register */
+#define MX1_PCR __REG(0x00205018) /* LCD Panel Configuration Register */
+#define MX1_HCR __REG(0x0020501C) /* Horizontal Configuration Register */
+#define MX1_VCR __REG(0x00205020) /* Vertical Configuration Register */
+#define MX1_POS __REG(0x00205024) /* Panning Offset Register */
+#define MX1_LGPMR __REG(0x00205028) /* LCD Gray Palette Mapping Register */
+#define MX1_PWMR __REG(0x0020502C) /* PWM Contrast Control Register */
+#define MX1_DMACR __REG(0x00205030) /* DMA Control Register */
+#define MX1_RMCR __REG(0x00205034) /* Refresh Mode Control Register */
+#define MX1_LCDICR __REG(0x00205038) /* Interrupt Configuration Register */
+#define MX1_LCDISR __REG(0x00205040) /* Interrupt Status Register */
+
+
+/*
+ * MX1 UART registers
+ */
+
+/* UART 1 */
+#define MX1_URX0D_1 __REG(0x00206000) /* UART 1 Receiver Register 0 */
+#define MX1_URX1D_1 __REG(0x00206004) /* UART 1 Receiver Register 1 */
+#define MX1_URX2D_1 __REG(0x00206008) /* UART 1 Receiver Register 2 */
+#define MX1_URX3D_1 __REG(0x0020600C) /* UART 1 Receiver Register 3 */
+#define MX1_URX4D_1 __REG(0x00206010) /* UART 1 Receiver Register 4 */
+#define MX1_URX5D_1 __REG(0x00206014) /* UART 1 Receiver Register 5 */
+#define MX1_URX6D_1 __REG(0x00206018) /* UART 1 Receiver Register 6 */
+#define MX1_URX7D_1 __REG(0x0020601C) /* UART 1 Receiver Register 7 */
+#define MX1_URX8D_1 __REG(0x00206020) /* UART 1 Receiver Register 8 */
+#define MX1_URX9D_1 __REG(0x00206024) /* UART 1 Receiver Register 9 */
+#define MX1_URX10D_1 __REG(0x00206028) /* UART 1 Receiver Register 10 */
+#define MX1_URX11D_1 __REG(0x0020602C) /* UART 1 Receiver Register 11 */
+#define MX1_URX12D_1 __REG(0x00206030) /* UART 1 Receiver Register 12 */
+#define MX1_URX13D_1 __REG(0x00206034) /* UART 1 Receiver Register 13 */
+#define MX1_URX14D_1 __REG(0x00206038) /* UART 1 Receiver Register 14 */
+#define MX1_URX15D_1 __REG(0x0020603c) /* UART 1 Receiver Register 15 */
+
+
+#define MX1_UTX0D_1 __REG(0x00206040) /* UART 1 Transmitter Register 0 */
+#define MX1_UTX1D_1 __REG(0x00206044) /* UART 1 Transmitter Register 1 */
+#define MX1_UTX2D_1 __REG(0x00206048) /* UART 1 Transmitter Register 2 */
+#define MX1_UTX3D_1 __REG(0x0020604C) /* UART 1 Transmitter Register 3 */
+#define MX1_UTX4D_1 __REG(0x00206050) /* UART 1 Transmitter Register 4 */
+#define MX1_UTX5D_1 __REG(0x00206054) /* UART 1 Transmitter Register 5 */
+#define MX1_UTX6D_1 __REG(0x00206058) /* UART 1 Transmitter Register 6 */
+#define MX1_UTX7D_1 __REG(0x0020605C) /* UART 1 Transmitter Register 7 */
+#define MX1_UTX8D_1 __REG(0x00206060) /* UART 1 Transmitter Register 8 */
+#define MX1_UTX9D_1 __REG(0x00206064) /* UART 1 Transmitter Register 9 */
+#define MX1_UTX10D_1 __REG(0x00206068) /* UART 1 Transmitter Register 10 */
+#define MX1_UTX11D_1 __REG(0x0020606C) /* UART 1 Transmitter Register 11 */
+#define MX1_UTX12D_1 __REG(0x00206060) /* UART 1 Transmitter Register 12 */
+#define MX1_UTX13D_1 __REG(0x00206074) /* UART 1 Transmitter Register 13 */
+#define MX1_UTX14D_1 __REG(0x00206078) /* UART 1 Transmitter Register 14 */
+#define MX1_UTX15D_1 __REG(0x0020607c) /* UART 1 Transmitter Register 15 */
+
+#define MX1_UCR1_1 __REG(0x00206080) /* UART 1 Control Register 1 */
+#define MX1_UCR2_1 __REG(0x00206084) /* UART 1 Control Register 2 */
+#define MX1_UCR3_1 __REG(0x00206088) /* UART 1 Control Register 3 */
+#define MX1_UCR4_1 __REG(0x0020608C) /* UART 1 Control Register 4 */
+#define MX1_UFCR_1 __REG(0x00206090) /* UART 1 FIFO Control Register */
+#define MX1_USR1_1 __REG(0x00206094) /* UART 1 Status Register 1 */
+#define MX1_USR2_1 __REG(0x00206098) /* UART 1 Status Register 2 */
+#define MX1_UESC_1 __REG(0x0020609C) /* UART 1 Escape Character Register */
+#define MX1_UTIM_1 __REG(0x002060A0) /* UART 1 Escape Timer Register */
+#define MX1_UBIR_1 __REG(0x002060A4) /* UART 1 BRM Incremental Register */
+#define MX1_UBMR_1 __REG(0x002060A8) /* UART 1 BRM Modulator Register */
+#define MX1_UBRC_1 __REG(0x002060AC) /* UART 1 Baud Rate Count Register */
+#define MX1_BIPR1_1 __REG(0x002060B0) /* UART 1 BRM Incremental Preset Register 1 */
+#define MX1_BIPR2_1 __REG(0x002060B4) /* UART 1 BRM Incremental Preset Register 2 */
+#define MX1_BIPR3_1 __REG(0x002060B8) /* UART 1 BRM Incremental Preset Register 3 */
+#define MX1_BIPR4_1 __REG(0x002060BC) /* UART 1 BRM Incremental Preset Register 4 */
+#define MX1_BMPR1_1 __REG(0x002060C0) /* UART 1 BRM Modulator Preset Register 1 */
+#define MX1_BMPR2_1 __REG(0x002060C4) /* UART 1 BRM Modulator Preset Register 2 */
+#define MX1_BMPR3_1 __REG(0x002060C8) /* UART 1 BRM Modulator Preset Register 3 */
+#define MX1_BMPR4_1 __REG(0x002060CC) /* UART 1 BRM Modulator Preset Register 4 */
+#define MX1_UTS_1 __REG(0x002060D0) /* UART 1 Test Register 1 */
+
+
+/* UART 2 */
+#define MX1_URX0D_2 __REG(0x00207000) /* UART 2 Receiver Register 0 */
+#define MX1_URX1D_2 __REG(0x00207004) /* UART 2 Receiver Register 1 */
+#define MX1_URX2D_2 __REG(0x00207008) /* UART 2 Receiver Register 2 */
+#define MX1_URX3D_2 __REG(0x0020700C) /* UART 2 Receiver Register 3 */
+#define MX1_URX4D_2 __REG(0x00207010) /* UART 2 Receiver Register 4 */
+#define MX1_URX5D_2 __REG(0x00207014) /* UART 2 Receiver Register 5 */
+#define MX1_URX6D_2 __REG(0x00207018) /* UART 2 Receiver Register 6 */
+#define MX1_URX7D_2 __REG(0x0020701C) /* UART 2 Receiver Register 7 */
+#define MX1_URX8D_2 __REG(0x00207020) /* UART 2 Receiver Register 8 */
+#define MX1_URX9D_2 __REG(0x00207024) /* UART 2 Receiver Register 9 */
+#define MX1_URX10D_2 __REG(0x00207028) /* UART 2 Receiver Register 10 */
+#define MX1_URX11D_2 __REG(0x0020702C) /* UART 2 Receiver Register 11 */
+#define MX1_URX12D_2 __REG(0x00207030) /* UART 2 Receiver Register 12 */
+#define MX1_URX13D_2 __REG(0x00207034) /* UART 2 Receiver Register 13 */
+#define MX1_URX14D_2 __REG(0x00207038) /* UART 2 Receiver Register 14 */
+#define MX1_URX15D_2 __REG(0x0020703c) /* UART 2 Receiver Register 15 */
+
+
+#define MX1_UTX0D_2 __REG(0x00207040) /* UART 2 Transmitter Register 0 */
+#define MX1_UTX1D_2 __REG(0x00207044) /* UART 2 Transmitter Register 1 */
+#define MX1_UTX2D_2 __REG(0x00207048) /* UART 2 Transmitter Register 2 */
+#define MX1_UTX3D_2 __REG(0x0020704C) /* UART 2 Transmitter Register 3 */
+#define MX1_UTX4D_2 __REG(0x00207050) /* UART 2 Transmitter Register 4 */
+#define MX1_UTX5D_2 __REG(0x00207054) /* UART 2 Transmitter Register 5 */
+#define MX1_UTX6D_2 __REG(0x00207058) /* UART 2 Transmitter Register 6 */
+#define MX1_UTX7D_2 __REG(0x0020705C) /* UART 2 Transmitter Register 7 */
+#define MX1_UTX8D_2 __REG(0x00207060) /* UART 2 Transmitter Register 8 */
+#define MX1_UTX9D_2 __REG(0x00207064) /* UART 2 Transmitter Register 9 */
+#define MX1_UTX10D_2 __REG(0x00207068) /* UART 2 Transmitter Register 10 */
+#define MX1_UTX11D_2 __REG(0x0020706C) /* UART 2 Transmitter Register 11 */
+#define MX1_UTX12D_2 __REG(0x00207060) /* UART 2 Transmitter Register 12 */
+#define MX1_UTX13D_2 __REG(0x00207074) /* UART 2 Transmitter Register 13 */
+#define MX1_UTX14D_2 __REG(0x00207078) /* UART 2 Transmitter Register 14 */
+#define MX1_UTX15D_2 __REG(0x0020707c) /* UART 2 Transmitter Register 15 */
+
+#define MX1_UCR1_2 __REG(0x00207080) /* UART 2 Control Register 1 */
+#define MX1_UCR2_2 __REG(0x00207084) /* UART 2 Control Register 2 */
+#define MX1_UCR3_2 __REG(0x00207088) /* UART 2 Control Register 3 */
+#define MX1_UCR4_2 __REG(0x0020708C) /* UART 2 Control Register 4 */
+#define MX1_UFCR_2 __REG(0x00207090) /* UART 2 FIFO Control Register */
+#define MX1_USR1_2 __REG(0x00207094) /* UART 2 Status Register 1 */
+#define MX1_USR2_2 __REG(0x00207098) /* UART 2 Status Register 2 */
+#define MX1_UESC_2 __REG(0x0020709C) /* UART 2 Escape Character Register */
+#define MX1_UTIM_2 __REG(0x002070A0) /* UART 2 Escape Timer Register */
+#define MX1_UBIR_2 __REG(0x002070A4) /* UART 2 BRM Incremental Register */
+#define MX1_UBMR_2 __REG(0x002070A8) /* UART 2 BRM Modulator Register */
+#define MX1_UBRC_2 __REG(0x002070AC) /* UART 2 Baud Rate Count Register */
+#define MX1_BIPR1_2 __REG(0x002070B0) /* UART 2 BRM Incremental Preset Register 1 */
+#define MX1_BIPR2_2 __REG(0x002070B4) /* UART 2 BRM Incremental Preset Register 2 */
+#define MX1_BIPR3_2 __REG(0x002070B8) /* UART 2 BRM Incremental Preset Register 3 */
+#define MX1_BIPR4_2 __REG(0x002070BC) /* UART 2 BRM Incremental Preset Register 4 */
+#define MX1_BMPR1_2 __REG(0x002070C0) /* UART 2 BRM Modulator Preset Register 1 */
+#define MX1_BMPR2_2 __REG(0x002070C4) /* UART 2 BRM Modulator Preset Register 2 */
+#define MX1_BMPR3_2 __REG(0x002070C8) /* UART 2 BRM Modulator Preset Register 3 */
+#define MX1_BMPR4_2 __REG(0x002070CC) /* UART 2 BRM Modulator Preset Register 4 */
+#define MX1_UTS_2 __REG(0x002070D0) /* UART 2 Test Register 1 */
+
+
+/*
+ * MX1 PWM registers
+ */
+
+#define MX1_PWMC __REG(0x00208000) /* PWM Control Register */
+#define MX1_PWMS __REG(0x00208004) /* PWM Sample Register */
+#define MX1_PWMP __REG(0x00208008) /* PWM Period Register */
+#define MX1_PWMCNT __REG(0x0020800C) /* PWM Counter Register */
+
+
+
+/*
+ * MX1 DMAC registers
+ */
+
+#define MX1_DCR __REG(0x00209000) /* DMA Control Register */
+#define MX1_DISR __REG(0x00209004) /* DMA Interrupt Status Register */
+#define MX1_DIMR __REG(0x00209008) /* DMA Interrupt Mask Register */
+#define MX1_DBTOSR __REG(0x0020900C) /* DMA Burst Time-Out Status Register */
+#define MX1_DRTOSR __REG(0x00209010) /* DMA Request Time-Out Status Register */
+#define MX1_DSESR __REG(0x00209014) /* DMA Request Time-Out Status Register */
+#define MX1_DBOSR __REG(0x00209018) /* DMA Buffer Overflow Status Register */
+#define MX1_DBTOCR __REG(0x0020901C) /* DMA Burst Time-Out Control Register */
+
+#define MX1_WSRA __REG(0x00209040) /* DMA W-Size Register A */
+#define MX1_XSRA __REG(0x00209044) /* DMA X-Size Register A */
+#define MX1_YSRA __REG(0x00209048) /* DMA Y-Size Register A */
+
+#define MX1_WSRB __REG(0x0020904C) /* DMA W-Size Register B */
+#define MX1_XSRB __REG(0x00209050) /* DMA X-Size Register B */
+#define MX1_YSRB __REG(0x00209054) /* DMA Y-Size Register B */
+
+/* Channel 0 */
+
+#define MX1_SAR0 __REG(0x00209080) /* Channel 0 Source Address Register */
+#define MX1_DAR0 __REG(0x00209084) /* Channel 0 Destination Address Register */
+#define MX1_CNTR0 __REG(0x00209088) /* Channel 0 Count Register */
+#define MX1_CCR0 __REG(0x0020908C) /* Channel 0 Control Register */
+#define MX1_RSSR0 __REG(0x00209090) /* Channel 0 Request Source Select Register */
+#define MX1_BLR0 __REG(0x00209094) /* Channel 0 Burst Length Register */
+#define MX1_RTOR0 __REG(0x00209098) /* Channel 0 Request Time-Out Register */
+#define MX1_BUCR0 __REG(0x00209098) /* Channel 0 Bus Utilization Control Register */
+
+
+/* Channel 1 */
+
+#define MX1_SAR1 __REG(0x002090C0) /* Channel 1 Source Address Register */
+#define MX1_DAR1 __REG(0x002090C4) /* Channel 1 Destination Address Register */
+#define MX1_CNTR1 __REG(0x002090C8) /* Channel 1 Count Register */
+#define MX1_CCR1 __REG(0x002090CC) /* Channel 1 Control Register */
+#define MX1_RSSR1 __REG(0x002090D0) /* Channel 1 Request Source Select Register */
+#define MX1_BLR1 __REG(0x002090D4) /* Channel 1 Burst Length Register */
+#define MX1_RTOR1 __REG(0x002090D8) /* Channel 1 Request Time-Out Register */
+#define MX1_BUCR1 __REG(0x002090D8) /* Channel 1 Bus Utilization Control Register */
+
+
+/* Channel 2 */
+
+#define MX1_SAR2 __REG(0x00209100) /* Channel 2 Source Address Register */
+#define MX1_DAR2 __REG(0x00209104) /* Channel 2 Destination Address Register */
+#define MX1_CNTR2 __REG(0x00209108) /* Channel 2 Count Register */
+#define MX1_CCR2 __REG(0x0020910C) /* Channel 2 Control Register */
+#define MX1_RSSR2 __REG(0x00209110) /* Channel 2 Request Source Select Register */
+#define MX1_BLR2 __REG(0x00209114) /* Channel 2 Burst Length Register */
+#define MX1_RTOR2 __REG(0x00209118) /* Channel 2 Request Time-Out Register */
+#define MX1_BUCR2 __REG(0x00209118) /* Channel 2 Bus Utilization Control Register */
+
+
+
+/* Channel 3 */
+
+#define MX1_SAR3 __REG(0x00209140) /* Channel 3 Source Address Register */
+#define MX1_DAR3 __REG(0x00209144) /* Channel 3 Destination Address Register */
+#define MX1_CNTR3 __REG(0x00209148) /* Channel 3 Count Register */
+#define MX1_CCR3 __REG(0x0020914C) /* Channel 3 Control Register */
+#define MX1_RSSR3 __REG(0x00209150) /* Channel 3 Request Source Select Register */
+#define MX1_BLR3 __REG(0x00209154) /* Channel 3 Burst Length Register */
+#define MX1_RTOR3 __REG(0x00209158) /* Channel 3 Request Time-Out Register */
+#define MX1_BUCR3 __REG(0x00209158) /* Channel 3 Bus Utilization Control Register */
+
+
+/* Channel 4 */
+
+#define MX1_SAR4 __REG(0x00209180) /* Channel 4 Source Address Register */
+#define MX1_DAR4 __REG(0x00209184) /* Channel 4 Destination Address Register */
+#define MX1_CNTR4 __REG(0x00209188) /* Channel 4 Count Register */
+#define MX1_CCR4 __REG(0x0020918C) /* Channel 4 Control Register */
+#define MX1_RSSR4 __REG(0x00209190) /* Channel 4 Request Source Select Register */
+#define MX1_BLR4 __REG(0x00209194) /* Channel 4 Burst Length Register */
+#define MX1_RTOR4 __REG(0x00209198) /* Channel 4 Request Time-Out Register */
+#define MX1_BUCR4 __REG(0x00209198) /* Channel 4 Bus Utilization Control Register */
+
+
+/* Channel 5 */
+
+#define MX1_SAR5 __REG(0x002091C0) /* Channel 5 Source Address Register */
+#define MX1_DAR5 __REG(0x002091C4) /* Channel 5 Destination Address Register */
+#define MX1_CNTR5 __REG(0x002091C8) /* Channel 5 Count Register */
+#define MX1_CCR5 __REG(0x002091CC) /* Channel 5 Control Register */
+#define MX1_RSSR5 __REG(0x002091D0) /* Channel 5 Request Source Select Register */
+#define MX1_BLR5 __REG(0x002091D4) /* Channel 5 Burst Length Register */
+#define MX1_RTOR5 __REG(0x002091D8) /* Channel 5 Request Time-Out Register */
+#define MX1_BUCR5 __REG(0x002091D8) /* Channel 5 Bus Utilization Control Register */
+
+
+/* Channel 6 */
+
+#define MX1_SAR6 __REG(0x00209200) /* Channel 6 Source Address Register */
+#define MX1_DAR6 __REG(0x00209204) /* Channel 6 Destination Address Register */
+#define MX1_CNTR6 __REG(0x00209208) /* Channel 6 Count Register */
+#define MX1_CCR6 __REG(0x0020920C) /* Channel 6 Control Register */
+#define MX1_RSSR6 __REG(0x00209210) /* Channel 6 Request Source Select Register */
+#define MX1_BLR6 __REG(0x00209214) /* Channel 6 Burst Length Register */
+#define MX1_RTOR6 __REG(0x00209218) /* Channel 6 Request Time-Out Register */
+#define MX1_BUCR6 __REG(0x00209218) /* Channel 6 Bus Utilization Control Register */
+
+
+/* Channel 7 */
+
+#define MX1_SAR7 __REG(0x00209240) /* Channel 7 Source Address Register */
+#define MX1_DAR7 __REG(0x00209244) /* Channel 7 Destination Address Register */
+#define MX1_CNTR7 __REG(0x00209248) /* Channel 7 Count Register */
+#define MX1_CCR7 __REG(0x0020924C) /* Channel 7 Control Register */
+#define MX1_RSSR7 __REG(0x00209250) /* Channel 7 Request Source Select Register */
+#define MX1_BLR7 __REG(0x00209254) /* Channel 7 Burst Length Register */
+#define MX1_RTOR7 __REG(0x00209258) /* Channel 7 Request Time-Out Register */
+#define MX1_BUCR7 __REG(0x00209258) /* Channel 7 Bus Utilization Control Register */
+
+
+/* Channel 8 */
+
+#define MX1_SAR8 __REG(0x00209280) /* Channel 8 Source Address Register */
+#define MX1_DAR8 __REG(0x00209284) /* Channel 8 Destination Address Register */
+#define MX1_CNTR8 __REG(0x00209288) /* Channel 8 Count Register */
+#define MX1_CCR8 __REG(0x0020928C) /* Channel 8 Control Register */
+#define MX1_RSSR8 __REG(0x00209290) /* Channel 8 Request Source Select Register */
+#define MX1_BLR8 __REG(0x00209294) /* Channel 8 Burst Length Register */
+#define MX1_RTOR8 __REG(0x00209298) /* Channel 8 Request Time-Out Register */
+#define MX1_BUCR8 __REG(0x00209298) /* Channel 8 Bus Utilization Control Register */
+
+
+/* Channel 9 */
+
+#define MX1_SAR9 __REG(0x002092C0) /* Channel 9 Source Address Register */
+#define MX1_DAR9 __REG(0x002092C4) /* Channel 9 Destination Address Register */
+#define MX1_CNTR9 __REG(0x002092C8) /* Channel 9 Count Register */
+#define MX1_CCR9 __REG(0x002092CC) /* Channel 9 Control Register */
+#define MX1_RSSR9 __REG(0x002092D0) /* Channel 9 Request Source Select Register */
+#define MX1_BLR9 __REG(0x002092D4) /* Channel 9 Burst Length Register */
+#define MX1_RTOR9 __REG(0x002092D8) /* Channel 9 Request Time-Out Register */
+#define MX1_BUCR9 __REG(0x002092D8) /* Channel 9 Bus Utilization Control Register */
+
+
+/* Channel 10 */
+
+#define MX1_SAR10 __REG(0x00209300) /* Channel 10 Source Address Register */
+#define MX1_DAR10 __REG(0x00209304) /* Channel 10 Destination Address Register */
+#define MX1_CNTR10 __REG(0x00209308) /* Channel 10 Count Register */
+#define MX1_CCR10 __REG(0x0020930C) /* Channel 10 Control Register */
+#define MX1_RSSR10 __REG(0x00209310) /* Channel 10 Request Source Select Register */
+#define MX1_BLR10 __REG(0x00209314) /* Channel 10 Burst Length Register */
+#define MX1_RTOR10 __REG(0x00209318) /* Channel 10 Request Time-Out Register */
+#define MX1_BUCR10 __REG(0x00209318) /* Channel 10 Bus Utilization Control Register */
+
+
+#define MX1_TCR __REG(0x00209340) /* Test Control Register */
+#define MX1_TFIFOAR __REG(0x00209344) /* Test FIFO A Register */
+#define MX1_TDRR __REG(0x00209348) /* Test DMA Request Register */
+#define MX1_TDIPR __REG(0x0020934C) /* Test DMA In Progress Register */
+#define MX1_TFIFOBR __REG(0x00209350) /* Test FIFO B Register */
+
+
+
+/*
+ * MX1 SIM registers
+ */
+
+#define MX1_PORT_CNTL __REG(0x00211000) /* Port Control Register */
+#define MX1_CNTL __REG(0x00211004) /* Control Register */
+#define MX1_RCV_THRESHOLD __REG(0x00211008)/* Receive Threshold Register */
+#define MX1_ENABLE __REG(0x0021100C) /* Transmit/Receive Enable Register */
+#define MX1_XMT_STATUS __REG(0x00211010) /* Transmit Status Register */
+#define MX1_RCV_STATUS __REG(0x00211014) /* Receive Status Register */
+#define MX1_SIM_INT_MASK __REG(0x00211018) /* Interrupt Mask Register */
+#define MX1_XMT_BUF __REG(0x0021101C) /* Port Transmit Buffer Register */
+#define MX1_RCV_BUF __REG(0x00211020) /* Receive Buffer Register */
+#define MX1_PORT_DETECT __REG(0x00211024) /* Detect Register */
+#define MX1_XMT_THRESHOLD __REG(0x00211028)/* Transmit Threshold Register */
+#define MX1_GUARD_CNTL __REG(0x0021102C) /* Transmit Guard Control Register */
+#define MX1_OD_CONFIG __REG(0x00211030) /* Open-Drain Configuration Control Register */
+#define MX1_RESET_CNTL __REG(0x00211034) /* Reset Control Register */
+#define MX1_CHAR_WAIT __REG(0x00211038) /* Charactor Wait Timer Register */
+#define MX1_GPCNT __REG(0x0021103C) /* General Purpose Counter Register */
+#define MX1_DIVISOR __REG(0x00211040) /* Divisor Register */
+
+
+/*
+ * MX1 USBD registers
+ */
+
+#define MX1_USB_FRAME __REG(0x00212000) /* USB Frame Number and Match Register */
+#define MX1_USB_SPEC __REG(0x00212004) /* USB Spec & Release Number Register */
+#define MX1_USB_STAT __REG(0x00212008) /* USB Status Register */
+#define MX1_USB_CTRL __REG(0x0021200C) /* USB Control Register */
+#define MX1_USB_DADR __REG(0x00212010) /* USB Descriptor RAM Address Register */
+#define MX1_USB_DDAT __REG(0x00212014) /* USB Descriptor RAM/Endpoint buffer Data Register */
+#define MX1_USB_INTR __REG(0x00212018) /* USB Interrupt Status Register */
+#define MX1_USB_MASK __REG(0x0021201C) /* USB Interrupt Mask Register */
+#define MX1_USB_ENAB __REG(0x00212024) /* USB Enable Register */
+
+
+/* Endpoint 0 */
+#define MX1_USB_EP0_STAT __REG(0x00212030) /* Endpoint 0 Status/Control Register */
+#define MX1_USB_EP0_INTR __REG(0x00212034) /* Endpoint 0 Interrupt Status Register */
+#define MX1_USB_EP0_MASK __REG(0x00212038) /* Endpoint 0 Interrupt Mask Register */
+#define MX1_USB_EP0_FDAT __REG(0x0021203C) /* Endpoint 0 FIFO Data Register */
+#define MX1_USB_EP0_FSTAT __REG(0x00212040) /* Endpoint 0 FIFO Status Register */
+#define MX1_USB_EP0_FCTRL __REG(0x00212044) /* Endpoint 0 FIFO Control Register */
+#define MX1_USB_EP0_LRFP __REG(0x00212048) /* Endpoint 0 Last Read Frame Pointer Register */
+#define MX1_USB_EP0_LWFP __REG(0x0021204C) /* Endpoint 0 Last Write Frame Pointer Register */
+#define MX1_USB_EP0_FALRM __REG(0x00212050) /* Endpoint 0 FIFO Alarm Register */
+#define MX1_USB_EP0_FRDP __REG(0x00212054) /* Endpoint 0 FIFO Read Pointer Register */
+#define MX1_USB_EP0_FWRP __REG(0x00212058) /* Endpoint 0 FIFO Write Pointer Register */
+
+
+/* Endpoint 1 */
+#define MX1_USB_EP1_STAT __REG(0x00212060) /* Endpoint 1 Status/Control Register */
+#define MX1_USB_EP1_INTR __REG(0x00212064) /* Endpoint 1 Interrupt Status Register */
+#define MX1_USB_EP1_MASK __REG(0x00212068) /* Endpoint 1 Interrupt Mask Register */
+#define MX1_USB_EP1_FDAT __REG(0x0021206C) /* Endpoint 1 FIFO Data Register */
+#define MX1_USB_EP1_FSTAT __REG(0x00212070) /* Endpoint 1 FIFO Status Register */
+#define MX1_USB_EP1_FCTRL __REG(0x00212074) /* Endpoint 1 FIFO Control Register */
+#define MX1_USB_EP1_LRFP __REG(0x00212078) /* Endpoint 1 Last Read Frame Pointer Register */
+#define MX1_USB_EP1_LWFP __REG(0x0021207C) /* Endpoint 1 Last Write Frame Pointer Register */
+#define MX1_USB_EP1_FALRM __REG(0x00212080) /* Endpoint 1 FIFO Alarm Register */
+#define MX1_USB_EP1_FRDP __REG(0x00212084) /* Endpoint 1 FIFO Read Pointer Register */
+#define MX1_USB_EP1_FWRP __REG(0x00212088) /* Endpoint 1 FIFO Write Pointer Register */
+
+
+/* Endpoint 2 */
+#define MX1_USB_EP2_STAT __REG(0x00212090) /* Endpoint 2 Status/Control Register */
+#define MX1_USB_EP2_INTR __REG(0x00212094) /* Endpoint 2 Interrupt Status Register */
+#define MX1_USB_EP2_MASK __REG(0x00212098) /* Endpoint 2 Interrupt Mask Register */
+#define MX1_USB_EP2_FDAT __REG(0x0021209C) /* Endpoint 2 FIFO Data Register */
+#define MX1_USB_EP2_FSTAT __REG(0x002120A0) /* Endpoint 2 FIFO Status Register */
+#define MX1_USB_EP2_FCTRL __REG(0x002120A4) /* Endpoint 2 FIFO Control Register */
+#define MX1_USB_EP2_LRFP __REG(0x002120A8) /* Endpoint 2 Last Read Frame Pointer Register */
+#define MX1_USB_EP2_LWFP __REG(0x002120AC) /* Endpoint 2 Last Write Frame Pointer Register */
+#define MX1_USB_EP2_FALRM __REG(0x002120B0) /* Endpoint 2 FIFO Alarm Register */
+#define MX1_USB_EP2_FRDP __REG(0x002120B4) /* Endpoint 2 FIFO Read Pointer Register */
+#define MX1_USB_EP2_FWRP __REG(0x002120B8) /* Endpoint 2 FIFO Write Pointer Register */
+
+
+/* Endpoint 3 */
+#define MX1_USB_EP3_STAT __REG(0x002120C0) /* Endpoint 3 Status/Control Register */
+#define MX1_USB_EP3_INTR __REG(0x002120C4) /* Endpoint 3 Interrupt Status Register */
+#define MX1_USB_EP3_MASK __REG(0x002120C8) /* Endpoint 3 Interrupt Mask Register */
+#define MX1_USB_EP3_FDAT __REG(0x002120CC) /* Endpoint 3 FIFO Data Register */
+#define MX1_USB_EP3_FSTAT __REG(0x002120D0) /* Endpoint 3 FIFO Status Register */
+#define MX1_USB_EP3_FCTRL __REG(0x002120D4) /* Endpoint 3 FIFO Control Register */
+#define MX1_USB_EP3_LRFP __REG(0x002120D8) /* Endpoint 3 Last Read Frame Pointer Register */
+#define MX1_USB_EP3_LWFP __REG(0x002120DC) /* Endpoint 3 Last Write Frame Pointer Register */
+#define MX1_USB_EP3_FALRM __REG(0x002120E0) /* Endpoint 3 FIFO Alarm Register */
+#define MX1_USB_EP3_FRDP __REG(0x002120E4) /* Endpoint 3 FIFO Read Pointer Register */
+#define MX1_USB_EP3_FWRP __REG(0x002120E8) /* Endpoint 3 FIFO Write Pointer Register */
+
+
+
+/* Endpoint 4 */
+#define MX1_USB_EP4_STAT __REG(0x002120F0) /* Endpoint 4 Status/Control Register */
+#define MX1_USB_EP4_INTR __REG(0x002120F4) /* Endpoint 4 Interrupt Status Register */
+#define MX1_USB_EP4_MASK __REG(0x002120F8) /* Endpoint 4 Interrupt Mask Register */
+#define MX1_USB_EP4_FDAT __REG(0x002120FC) /* Endpoint 4 FIFO Data Register */
+#define MX1_USB_EP4_FSTAT __REG(0x00212100) /* Endpoint 4 FIFO Status Register */
+#define MX1_USB_EP4_FCTRL __REG(0x00212104) /* Endpoint 4 FIFO Control Register */
+#define MX1_USB_EP4_LRFP __REG(0x00212108) /* Endpoint 4 Last Read Frame Pointer Register */
+#define MX1_USB_EP4_LWFP __REG(0x0021210C) /* Endpoint 4 Last Write Frame Pointer Register */
+#define MX1_USB_EP4_FALRM __REG(0x00212110) /* Endpoint 4 FIFO Alarm Register */
+#define MX1_USB_EP4_FRDP __REG(0x00212114) /* Endpoint 4 FIFO Read Pointer Register */
+#define MX1_USB_EP4_FWRP __REG(0x00212118) /* Endpoint 4 FIFO Write Pointer Register */
+
+
+
+/* Endpoint 5 */
+#define MX1_USB_EP5_STAT __REG(0x00212120) /* Endpoint 5 Status/Control Register */
+#define MX1_USB_EP5_INTR __REG(0x00212124) /* Endpoint 5 Interrupt Status Register */
+#define MX1_USB_EP5_MASK __REG(0x00212128) /* Endpoint 5 Interrupt Mask Register */
+#define MX1_USB_EP5_FDAT __REG(0x0021212C) /* Endpoint 5 FIFO Data Register */
+#define MX1_USB_EP5_FSTAT __REG(0x00212130) /* Endpoint 5 FIFO Status Register */
+#define MX1_USB_EP5_FCTRL __REG(0x00212134) /* Endpoint 5 FIFO Control Register */
+#define MX1_USB_EP5_LRFP __REG(0x00212138) /* Endpoint 5 Last Read Frame Pointer Register */
+#define MX1_USB_EP5_LWFP __REG(0x0021213C) /* Endpoint 5 Last Write Frame Pointer Register */
+#define MX1_USB_EP5_FALRM __REG(0x00212140) /* Endpoint 5 FIFO Alarm Register */
+#define MX1_USB_EP5_FRDP __REG(0x00212144) /* Endpoint 5 FIFO Read Pointer Register */
+#define MX1_USB_EP5_FWRP __REG(0x00212148) /* Endpoint 5 FIFO Write Pointer Register */
+
+
+
+
+/*
+ * MX1 SPI 1 registers
+ */
+
+#define MX1_RXDATAREG1 __REG(0x00213000) /* SPI 1 Rx Data Register */
+#define MX1_TXDATAREG1 __REG(0x00213004) /* SPI 1 Tx Data Register */
+#define MX1_CONTROLREG1 __REG(0x00213008) /* SPI 1 Control Register */
+#define MX1_INTREG1 __REG(0x0021300C) /* SPI 1 Interrupt Control/Status Register */
+#define MX1_TESTREG1 __REG(0x00213010) /* SPI 1 Test Register */
+#define MX1_PERIODREG1 __REG(0x00213014) /* SPI 1 Sample Period Control Register */
+#define MX1_DMAREG1 __REG(0x00213018) /* SPI 1 DMA Control Register */
+#define MX1_RESETREG1 __REG(0x00213018) /* SPI 1 Soft Reset Register */
+
+
+
+
+/*
+ * MX1 MMC/SDHC registers
+ */
+
+#define MX1_STR_STP_CLK __REG(0x00214000) /* MMC/SD Clock Control Register */
+#define MX1_STATUS __REG(0x00214004) /* MMC/SD Status Register */
+#define MX1_CLK_RATE __REG(0x00214008) /* MMC/SD Clock Rate Register */
+#define MX1_CMD_DAT_CONT __REG(0x0021400C) /* MMC/SD Command & Data Control Register */
+#define MX1_RES_TO __REG(0x00214010) /* MMC/SD Response Time Out Register */
+#define MX1_READ_TO __REG(0x00214014) /* MMC/SD Read Time Out Register */
+#define MX1_BLK_LEN __REG(0x00214018) /* MMC/SD Block Length Register */
+#define MX1_NOB __REG(0x0021401C) /* MMC/SD Number of Block Register */
+#define MX1_REV_NO __REG(0x00214020) /* MMC/SD Revision Number Register */
+#define MX1_MMC_INT_MASK __REG(0x00214024) /* MMC/SD Interrupt Mask Register */
+#define MX1_CMD __REG(0x00214028) /* MMC/SD Command Number Register */
+#define MX1_ARGH __REG(0x0021402C) /* MMC/SD Higher Argument Register */
+#define MX1_ARGL __REG(0x00214030) /* MMC/SD Lower Argument Register */
+#define MX1_RES_FIFO __REG(0x00214034) /* MMC/SD Response FIFO Register */
+#define MX1_BUFFER_ACCESS __REG(0x00214038) /* MMC/SD Buffer Access Register */
+
+
+
+/*
+ * MX1 ASP registers
+ */
+
+#define MX1_ASP_PADFIFO __REG(0x00215000) /* Pen Sample FIFO */
+#define MX1_ASP_VADFIFO __REG(0x00215004) /* Voice ADC Register */
+#define MX1_ASP_VDAFIFO __REG(0x00215008) /* Voice DAC Register */
+#define MX1_ASP_VADCOEF __REG(0x0021500C) /* Voice ADC FIR Coefficients RAM */
+#define MX1_ASP_ACNTLCR __REG(0x00215010) /* Control Register */
+#define MX1_ASP_PSMPLRG __REG(0x00215014) /* Pen A/D Sample Rate Control Register */
+#define MX1_ASP_ICNTLR __REG(0x00215018) /* Interrupt Control Register */
+#define MX1_ASP_ISTATR __REG(0x0021501C) /* Interrupt/Error Status Register */
+#define MX1_ASP_VADGAIN __REG(0x00215020) /* Voice ADC Control Register */
+#define MX1_ASP_VDAGAIN __REG(0x00215024) /* Voice DAC Control Register */
+#define MX1_ASP_VDACOEF __REG(0x00215028) /* Voice DAC FIR Coefficients RAM */
+#define MX1_ASP_CLKDIV __REG(0x0021502C) /* Clock Divide Register */
+#define MX1_ASP_CMPCNTL __REG(0x0021502C) /* Compare Control Register */
+
+
+
+/*
+ * MX1 BTA registers
+ */
+
+
+/*
+ * MX1 I2C registers
+ */
+
+#define MX1_IADR __REG(0x00217000) /* I2C Address Register */
+#define MX1_IFDR __REG(0x00217004) /* I2C Frequency Divider Register */
+#define MX1_I2CR __REG(0x00217008) /* I2C Control Register */
+#define MX1_I2CSR __REG(0x0021700C) /* I2C Status Register */
+#define MX1_I2DR __REG(0x00217010) /* I2C Data I/O Register */
+
+
+
+/*
+ * MX1 SSI registers
+ */
+
+#define MX1_STX __REG(0x00218000) /* SSI Transmit Data Register */
+#define MX1_SRX __REG(0x00218004) /* SSI Receive Data Register */
+#define MX1_SCSR __REG(0x00218008) /* SSI Control/Status Register */
+#define MX1_STCR __REG(0x0021800C) /* SSI Transmit Configuration Register */
+#define MX1_SRCR __REG(0x00218010) /* SSI Recieve Configuration Register */
+#define MX1_STCCR __REG(0x00218014) /* SSI Transmit Clock Control Register */
+#define MX1_SRCCR __REG(0x00218018) /* SSI Receive Clock Control Register */
+#define MX1_STSR __REG(0x0021801C) /* SSI Time Slot Register */
+#define MX1_SFCSR __REG(0x00218020) /* SSI FIFO Control/Status Register */
+#define MX1_SOR __REG(0x00218024) /* SSI Option Register */
+
+
+
+/*
+ * MX1 SPI 2 registers
+ */
+
+#define MX1_RXDATAREG2 __REG(0x00219000) /* SPI 2 Rx Data Register */
+#define MX1_TXDATAREG2 __REG(0x00219004) /* SPI 2 Tx Data Register */
+#define MX1_CONTROLREG2 __REG(0x00219008) /* SPI 2 Control Register */
+#define MX1_INTREG2 __REG(0x0021900C) /* SPI 2 Interrupt Control/Status Register */
+#define MX1_TESTREG2 __REG(0x00219010) /* SPI 2 Test Register */
+#define MX1_PERIODREG2 __REG(0x00219014) /* SPI 2 Sample Period Control Register */
+#define MX1_DMAREG2 __REG(0x00219018) /* SPI 2 DMA Control Register */
+#define MX1_RESETREG2 __REG(0x00219018) /* SPI 2 Soft Reset Register */
+
+
+
+/*
+ * MX1 MSHC registers
+ */
+
+#define MX1_MSCMD __REG(0x0021A000) /* Memory Stick Command Register */
+#define MX1_MSCS __REG(0x0021A002) /* Memory Stick Control/Status Register */
+#define MX1_MSTDATA __REG(0x0021A004) /* Memory Stick Transmit FIFO Data Register */
+#define MX1_MSRDATA __REG(0x0021A004) /* Memory Stick Recieve FIFO Data Register */
+#define MX1_MSICS __REG(0x0021A006) /* Memory Stick Interrupt Control/Status Register */
+#define MX1_MSPPCD __REG(0x0021A008) /* Memory Stick Parallel Port Control/Data Register */
+#define MX1_MSC2 __REG(0x0021A00A) /* Memory Stick Control 2 Register */
+#define MX1_MSACD __REG(0x0021A00C) /* Memory Stick Auto Command Register */
+#define MX1_MSFAECS __REG(0x0021A00E) /* Memory Stick FIFO Access Error Control/Status Register */
+#define MX1_MSCLKD __REG(0x0021A010) /* Memory Stick Serial Clock divider Register */
+#define MX1_MSDRQC __REG(0x0021A012) /* Memory Stick DMA Request Control Register */
+
+
+
+/*
+ * MX1 PLLCLK registers
+ */
+
+#define MX1_CSCR __REG(0x0021B000) /* Clock Source Control Register */
+#define MX1_MPCTL0 __REG(0x0021B004) /* MCU PLL Control Register 0 */
+#define MX1_MPCTL1 __REG(0x0021B008) /* MCU PLL & System Clock Control Register 1 */
+#define MX1_UPCTL0 __REG(0x0021B00C) /* USB PLL Control Register 0 */
+#define MX1_UPCTL1 __REG(0x0021B010) /* USB PLL Control Register 1 */
+#define MX1_PCDR __REG(0x0021B020) /* Peripheral Clock Divider Register */
+
+
+/*
+ * MX1 RESET registers
+ */
+
+#define MX1_RSR __REG(0x0021B800) /* Reset Source Register */
+
+
+
+/*
+ * MX1 SYS CTRL registers
+ */
+
+#define MX1_SIDR __REG(0x0021B804) /* Silicon ID Register */
+#define MX1_FMCR __REG(0x0021B808) /* Function MultiPlexing Control Register */
+#define MX1_GPCR __REG(0x0021B80C) /* Global Peripheral Control Register */
+
+
+/*
+ * MX1 GPIO registers
+ */
+
+/* Port A */
+#define MX1_DDIR_A __REG(0x0021C000) /* Port A Data Direction Register */
+#define MX1_OCR1_A __REG(0x0021C004) /* Port A Output Configuration Register 1 */
+#define MX1_OCR2_A __REG(0x0021C008) /* Port A Output Configuration Register 2 */
+#define MX1_ICONFA1_A __REG(0x0021C00C) /* Port A Input Configuration Register A1 */
+#define MX1_ICONFA2_A __REG(0x0021C010) /* Port A Input Configuration Register A2 */
+#define MX1_ICONFB1_A __REG(0x0021C014) /* Port A Input Configuration Register B1 */
+#define MX1_ICONFB2_A __REG(0x0021C018) /* Port A Input Configuration Register B2 */
+#define MX1_DR_A __REG(0x0021C01C) /* Port A Data Register */
+#define MX1_GIUS_A __REG(0x0021C020) /* Port A GPIO In Use Register */
+#define MX1_SSR_A __REG(0x0021C024) /* Port A Sample Status Register */
+#define MX1_ICR1_A __REG(0x0021C028) /* Port A Interrupt Configuration Register 1 */
+#define MX1_ICR2_A __REG(0x0021C02C) /* Port A Interrupt Configuration Register 2 */
+#define MX1_IMR_A __REG(0x0021C030) /* Port A Interrupt Mask Register */
+#define MX1_ISR_A __REG(0x0021C034) /* Port A Interrupt Status Register */
+#define MX1_GPR_A __REG(0x0021C038) /* Port A General Purpose Register */
+#define MX1_SWR_A __REG(0x0021C03C) /* Port A Software Reset Register */
+#define MX1_PUEN_A __REG(0x0021C040) /* Port A Pull Up Enable Register */
+
+
+/* Port B */
+#define MX1_DDIR_B __REG(0x0021C100) /* Port B Data Direction Register */
+#define MX1_OCR1_B __REG(0x0021C104) /* Port B Output Configuration Register 1 */
+#define MX1_OCR2_B __REG(0x0021C108) /* Port B Output Configuration Register 2 */
+#define MX1_ICONFA1_B __REG(0x0021C10C) /* Port B Input Configuration Register A1 */
+#define MX1_ICONFA2_B __REG(0x0021C110) /* Port B Input Configuration Register A2 */
+#define MX1_ICONFB1_B __REG(0x0021C114) /* Port B Input Configuration Register B1 */
+#define MX1_ICONFB2_B __REG(0x0021C118) /* Port B Input Configuration Register B2 */
+#define MX1_DR_B __REG(0x0021C11C) /* Port B Data Register */
+#define MX1_GIUS_B __REG(0x0021C120) /* Port B GPIO In Use Register */
+#define MX1_SSR_B __REG(0x0021C124) /* Port B Sample Status Register */
+#define MX1_ICR1_B __REG(0x0021C128) /* Port B Interrupt Configuration Register 1 */
+#define MX1_ICR2_B __REG(0x0021C12C) /* Port B Interrupt Configuration Register 2 */
+#define MX1_IMR_B __REG(0x0021C130) /* Port B Interrupt Mask Register */
+#define MX1_ISR_B __REG(0x0021C134) /* Port B Interrupt Status Register */
+#define MX1_GPR_B __REG(0x0021C138) /* Port B General Purpose Register */
+#define MX1_SWR_B __REG(0x0021C13C) /* Port B Software Reset Register */
+#define MX1_PUEN_B __REG(0x0021C140) /* Port B Pull Up Enable Register */
+
+
+
+/* Port C */
+#define MX1_DDIR_C __REG(0x0021C200) /* Port C Data Direction Register */
+#define MX1_OCR1_C __REG(0x0021C204) /* Port C Output Configuration Register 1 */
+#define MX1_OCR2_C __REG(0x0021C208) /* Port C Output Configuration Register 2 */
+#define MX1_ICONFA1_C __REG(0x0021C20C) /* Port C Input Configuration Register A1 */
+#define MX1_ICONFA2_C __REG(0x0021C210) /* Port C Input Configuration Register A2 */
+#define MX1_ICONFB1_C __REG(0x0021C214) /* Port C Input Configuration Register B1 */
+#define MX1_ICONFB2_C __REG(0x0021C218) /* Port C Input Configuration Register B2 */
+#define MX1_DR_C __REG(0x0021C21C) /* Port C Data Register */
+#define MX1_GIUS_C __REG(0x0021C220) /* Port C GPIO In Use Register */
+#define MX1_SSR_C __REG(0x0021C224) /* Port C Sample Status Register */
+#define MX1_ICR1_C __REG(0x0021C228) /* Port C Interrupt Configuration Register 1 */
+#define MX1_ICR2_C __REG(0x0021C22C) /* Port C Interrupt Configuration Register 2 */
+#define MX1_IMR_C __REG(0x0021C230) /* Port C Interrupt Mask Register */
+#define MX1_ISR_C __REG(0x0021C234) /* Port C Interrupt Status Register */
+#define MX1_GPR_C __REG(0x0021C238) /* Port C General Purpose Register */
+#define MX1_SWR_C __REG(0x0021C23C) /* Port C Software Reset Register */
+#define MX1_PUEN_C __REG(0x0021C240) /* Port C Pull Up Enable Register */
+
+
+
+/* Port D */
+#define MX1_DDIR_D __REG(0x0021C300) /* Port D Data Direction Register */
+#define MX1_OCR1_D __REG(0x0021C304) /* Port D Output Configuration Register 1 */
+#define MX1_OCR2_D __REG(0x0021C308) /* Port D Output Configuration Register 2 */
+#define MX1_ICONFA1_D __REG(0x0021C30C) /* Port D Input Configuration Register A1 */
+#define MX1_ICONFA2_D __REG(0x0021C310) /* Port D Input Configuration Register A2 */
+#define MX1_ICONFB1_D __REG(0x0021C314) /* Port D Input Configuration Register B1 */
+#define MX1_ICONFB2_D __REG(0x0021C318) /* Port D Input Configuration Register B2 */
+#define MX1_DR_D __REG(0x0021C31C) /* Port D Data Register */
+#define MX1_GIUS_D __REG(0x0021C320) /* Port D GPIO In Use Register */
+#define MX1_SSR_D __REG(0x0021C324) /* Port D Sample Status Register */
+#define MX1_ICR1_D __REG(0x0021C328) /* Port D Interrupt Configuration Register 1 */
+#define MX1_ICR2_D __REG(0x0021C32C) /* Port D Interrupt Configuration Register 2 */
+#define MX1_IMR_D __REG(0x0021C330) /* Port D Interrupt Mask Register */
+#define MX1_ISR_D __REG(0x0021C334) /* Port D Interrupt Status Register */
+#define MX1_GPR_D __REG(0x0021C338) /* Port D General Purpose Register */
+#define MX1_SWR_D __REG(0x0021C33C) /* Port D Software Reset Register */
+#define MX1_PUEN_D __REG(0x0021C340) /* Port D Pull Up Enable Register */
+
+
+
+/*
+ * MX1 EIM registers
+ */
+
+#define MX1_CS0U __REG(0x00220000) /* Chip Select 0 Upper Control Register */
+#define MX1_CS0L __REG(0x00220004) /* Chip Select 0 Lower Control Register */
+#define MX1_CS1U __REG(0x00220008) /* Chip Select 1 Upper Control Register */
+#define MX1_CS1L __REG(0x0022000C) /* Chip Select 1 Lower Control Register */
+#define MX1_CS2U __REG(0x00220010) /* Chip Select 2 Upper Control Register */
+#define MX1_CS2L __REG(0x00220014) /* Chip Select 2 Lower Control Register */
+#define MX1_CS3U __REG(0x00220018) /* Chip Select 3 Upper Control Register */
+#define MX1_CS3L __REG(0x0022001C) /* Chip Select 3 Lower Control Register */
+#define MX1_CS4U __REG(0x00220020) /* Chip Select 4 Upper Control Register */
+#define MX1_CS4L __REG(0x00220024) /* Chip Select 4 Lower Control Register */
+#define MX1_CS5U __REG(0x00220028) /* Chip Select 5 Upper Control Register */
+#define MX1_CS5L __REG(0x0022002C) /* Chip Select 5 Lower Control Register */
+#define MX1_WEIM __REG(0x00220030) /* weim cONFIGURATION Register */
+
+
+
+/*
+ * MX1 SDRAMC registers
+ */
+
+#define MX1_SDCTL0 __REG(0x00221000) /* SDRAM 0 Control Register */
+#define MX1_SDCTL1 __REG(0x00221004) /* SDRAM 1 Control Register */
+#define MX1_MISCELLANEOUS __REG(0x00221014) /* Miscellaneous Register */
+#define MX1_SDRST __REG(0x00221018) /* SDRAM Reset Register */
+
+
+
+/*
+ * MX1 MMA registers
+ */
+
+#define MX1_MMA_MAC_MOD __REG(0x00222000) /* MMA MAC Module Register */
+#define MX1_MMA_MAC_CTRL __REG(0x00222004) /* MMA MAC Control Register */
+#define MX1_MMA_MAC_MULT __REG(0x00222008) /* MMA MAC Multiply Counter Register */
+#define MX1_MMA_MAC_ACCU __REG(0x0022200C) /* MMA MAC Accumulate Counter Register */
+#define MX1_MMA_MAC_INTR __REG(0x00222010) /* MMA MAC Interrupt Register */
+#define MX1_MMA_MAC_INTR_MASK __REG(0x00222014) /* MMA MAC Interrupt Mask Register */
+#define MX1_MMA_MAC_FIFO __REG(0x00222018) /* MMA MAC FIFO Register */
+#define MX1_MMA_MAC_FIFO_STAT __REG(0x0022201C) /* MMA MAC FIFO Status Register */
+#define MX1_MMA_MAC_BURST __REG(0x00222020) /* MMA MAC Burst Count Register */
+#define MX1_MMA_MAC_BITSEL __REG(0x00222024) /* MMA MAC Bit Select Register */
+
+#define MX1_MMA_MAC_XBASE __REG(0x00222200) /* MMA MAC X Base Address Register */
+#define MX1_MMA_MAC_XINDEX __REG(0x00222204) /* MMA MAC X Index Register */
+#define MX1_MMA_MAC_XLENGTH __REG(0x00222208) /* MMA MAC X Length Register */
+#define MX1_MMA_MAC_XMODIFY __REG(0x0022220C) /* MMA MAC X Modify Register */
+#define MX1_MMA_MAC_XINCR __REG(0x00222210) /* MMA MAC X Increment Register */
+#define MX1_MMA_MAC_XCOUNT __REG(0x00222214) /* MMA MAC X Count Register */
+
+
+#define MX1_MMA_MAC_YBASE __REG(0x00222300) /* MMA MAC Y Base Address Register */
+#define MX1_MMA_MAC_YINDEX __REG(0x00222304) /* MMA MAC Y Index Register */
+#define MX1_MMA_MAC_YLENGTH __REG(0x00222308) /* MMA MAC Y Length Register */
+#define MX1_MMA_MAC_YMODIFY __REG(0x0022230C) /* MMA MAC Y Modify Register */
+#define MX1_MMA_MAC_YINCR __REG(0x00222310) /* MMA MAC Y Increment Register */
+#define MX1_MMA_MAC_YCOUNT __REG(0x00222314) /* MMA MAC Y Count Register */
+
+
+#define MX1_MMA_DCTCTRL __REG(0x00222400) /* DCT/iDCT Control Register */
+#define MX1_MMA_DCTVERSION __REG(0x00222404) /* DCT/iDCT Version Register */
+#define MX1_MMA_DCTIRQENA __REG(0x00222408) /* DCT/iDCT IRQ Enable Register */
+#define MX1_MMA_DCTIRQSTAT __REG(0x0022240C) /* DCT/iDCT IRQ Status Register */
+#define MX1_MMA_DCTSRCDATA __REG(0x00222410) /* DCT/iDCT Source Data Address */
+#define MX1_MMA_DCTDESDATA __REG(0x00222414) /* DCT/iDCT Destination Data Address */
+#define MX1_MMA_DCTXOFF __REG(0x00222418) /* DCT/iDCT X-Offset Address */
+#define MX1_MMA_DCTYOFF __REG(0x0022241C) /* DCT/iDCT Y-Offset Address */
+#define MX1_MMA_DCTXYCNT __REG(0x00222420) /* DCT/iDCT XY Count */
+#define MX1_MMA_DCTSKIP __REG(0x00222424) /* DCT/iDCT Skip Address */
+#define MX1_MMA_DCTFIFO __REG(0x00222500) /* DCT/iDCT Data FIFO */
+
+
+
+
+/*
+ * MX1 AITC registers
+ */
+
+#define MX1_INTCNTL __REG(0x00223000) /* Interrupt Control Register */
+#define MX1_NIMASK __REG(0x00223004) /* Normal Interrupt Mask Register */
+#define MX1_INTENNUM __REG(0x00223008) /* Interrupt Enable Number Register */
+#define MX1_INTDISNUM __REG(0x0022300C) /* Interrupt Disable Number Register */
+#define MX1_INTENABLEH __REG(0x00223010) /* Interrupt Enable Register High */
+#define MX1_INTENABLEL __REG(0x00223014) /* Interrupt Enable Register Low */
+#define MX1_INTTYPEH __REG(0x00223018) /* Interrupt Type Register High */
+#define MX1_INTTYPEL __REG(0x0022301C) /* Interrupt Type Register Low */
+#define MX1_NIPRIORITY7 __REG(0x00223020) /* Normal Interrupt Priority Level Register 7*/
+#define MX1_NIPRIORITY6 __REG(0x00223024) /* Normal Interrupt Priority Level Register 6*/
+#define MX1_NIPRIORITY5 __REG(0x00223028) /* Normal Interrupt Priority Level Register 5*/
+#define MX1_NIPRIORITY4 __REG(0x0022302C) /* Normal Interrupt Priority Level Register 4*/
+#define MX1_NIPRIORITY3 __REG(0x00223030) /* Normal Interrupt Priority Level Register 3*/
+#define MX1_NIPRIORITY2 __REG(0x00223034) /* Normal Interrupt Priority Level Register 2*/
+#define MX1_NIPRIORITY1 __REG(0x00223038) /* Normal Interrupt Priority Level Register 1*/
+#define MX1_NIPRIORITY0 __REG(0x0022303C) /* Normal Interrupt Priority Level Register 0*/
+#define MX1_NIVECSR __REG(0x00223040) /* Normal Interrupt Vector & Status Register */
+#define MX1_FIVECSR __REG(0x00223044) /* Fast Interrupt Vector & Status Register */
+#define MX1_INTSRCH __REG(0x00223048) /* Interrupt Source Register High */
+#define MX1_INTSRCL __REG(0x0022304C) /* Interrupt Source Register Low */
+#define MX1_INTFRCH __REG(0x00223050) /* Interrupt Force Register High */
+#define MX1_INTFRCL __REG(0x00223054) /* Interrupt Force Register Low */
+#define MX1_NIPNDH __REG(0x00223058) /* Normal Interrupt Pending Register High */
+#define MX1_NIPNDL __REG(0x0022305C) /* Normal Interrupt Pending Register Low */
+#define MX1_FIPNDH __REG(0x00223060) /* Fast Interrupt Pending Register High */
+#define MX1_FIPNDL __REG(0x00223064) /* Fast Interrupt Pending Register Low */
+
+
+/*
+ * MX1 CSI registers
+ */
+
+#define MX1_CSICR1 __REG(0x00224000) /* CSI Control Register 1 */
+#define MX1_CSICR2 __REG(0x00224004) /* CSI Control Register 2 */
+#define MX1_CSISR __REG(0x00224008) /* CSI Status Register 1 */
+#define MX1_CSISTATR __REG(0x0022400C) /* CSI Statistic FIFO Register 1 */
+#define MX1_CSIRXR __REG(0x00224010) /* CSI RxFIFO Register 1 */
+
+
+
+#endif /* __MC9328_H__ */
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+#if 0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+/*
+ MX1 dma definition
+*/
+
+#define MAX_DMA_ADDRESS 0xffffffff
+
+//#define MAX_DMA_CHANNELS 0
+
+#define MAX_DMA_CHANNELS 11
+#define MAX_DMA_2D_REGSET 2
+
+/* MX1 DMA module registers' address */
+
+#define MX1_DMA_BASE IO_ADDRESS(0x00209000)
+#define MX1_DMA_DCR (MX1_DMA_BASE + 0x00) // DMA control register
+#define MX1_DMA_DISR (MX1_DMA_BASE + 0x04) // DMA interrupt status register
+#define MX1_DMA_DIMR (MX1_DMA_BASE + 0x08) // DMA interrupt mask register
+#define MX1_DMA_DBTOSR (MX1_DMA_BASE + 0x0C) // DMA burst time-out status register
+#define MX1_DMA_DRTOSR (MX1_DMA_BASE + 0x10) // DMA request time-out status register
+#define MX1_DMA_DSESR (MX1_DMA_BASE + 0x14) // DMA transfer error status register
+#define MX1_DMA_DBOSR (MX1_DMA_BASE + 0x18) // DMA buffer overflow status register
+#define MX1_DMA_DBTOCR (MX1_DMA_BASE + 0x1C) // DMA burst time-out control register
+#define MX1_DMA_WSRA (MX1_DMA_BASE + 0x40) // W-size register A
+#define MX1_DMA_XSRA (MX1_DMA_BASE + 0x44) // X-size register A
+#define MX1_DMA_YSRA (MX1_DMA_BASE + 0x48) // Y-size register A
+#define MX1_DMA_WSRB (MX1_DMA_BASE + 0x4C) // W-size register B
+#define MX1_DMA_XSRB (MX1_DMA_BASE + 0x50) // X-size register B
+#define MX1_DMA_YSRB (MX1_DMA_BASE + 0x54) // Y-size register B
+
+#define MX1_DMA_SAR0 (MX1_DMA_BASE + 0x80) // source address register 0
+#define MX1_DMA_DAR0 (MX1_DMA_BASE + 0x84) // destination address register 0
+#define MX1_DMA_CNTR0 (MX1_DMA_BASE + 0x88) // count register 0
+#define MX1_DMA_CCR0 (MX1_DMA_BASE + 0x8C) // channel control register 0
+#define MX1_DMA_RSSR0 (MX1_DMA_BASE + 0x90) // request source select register 0
+#define MX1_DMA_BLR0 (MX1_DMA_BASE + 0x94) // burst length register 0
+#define MX1_DMA_RTOR0 (MX1_DMA_BASE + 0x98) // request time-out register 0
+#define MX1_DMA_BUCR0 (MX1_DMA_BASE + 0x98) // bus utilization control register 0
+
+/* register set 1 to 10 are offseted by 0x40 each = 0x10 pointers away */
+
+#define DMA_REG_SET_OFS 0x10
+
+
+/* MX1 DMA module registers */
+#define _reg_DMA_DCR (*((P_VU32)MX1_DMA_DCR))
+#define _reg_DMA_DISR (*((P_VU32)MX1_DMA_DISR))
+#define _reg_DMA_DIMR (*((P_VU32)MX1_DMA_DIMR))
+#define _reg_DMA_DBTOSR (*((P_VU32)MX1_DMA_DBTOSR))
+#define _reg_DMA_DRTOSR (*((P_VU32)MX1_DMA_DRTOSR))
+#define _reg_DMA_DSESR (*((P_VU32)MX1_DMA_DSESR))
+#define _reg_DMA_DBOSR (*((P_VU32)MX1_DMA_DBOSR))
+#define _reg_DMA_DBTOCR (*((P_VU32)MX1_DMA_DBTOCR))
+#define _reg_DMA_WSRA (*((P_VU32)MX1_DMA_WSRA))
+#define _reg_DMA_XSRA (*((P_VU32)MX1_DMA_XSRA))
+#define _reg_DMA_YSRA (*((P_VU32)MX1_DMA_YSRA))
+#define _reg_DMA_WSRB (*((P_VU32)MX1_DMA_WSRB))
+#define _reg_DMA_XSRB (*((P_VU32)MX1_DMA_XSRB))
+#define _reg_DMA_YSRB (*((P_VU32)MX1_DMA_YSRB))
+#define _reg_DMA_SAR0 (*((P_VU32)MX1_DMA_SAR0))
+#define _reg_DMA_DAR0 (*((P_VU32)MX1_DMA_DAR0))
+#define _reg_DMA_CNTR0 (*((P_VU32)MX1_DMA_CNTR0))
+#define _reg_DMA_CCR0 (*((P_VU32)MX1_DMA_CCR0))
+#define _reg_DMA_RSSR0 (*((P_VU32)MX1_DMA_RSSR0))
+#define _reg_DMA_BLR0 (*((P_VU32)MX1_DMA_BLR0))
+#define _reg_DMA_RTOR0 (*((P_VU32)MX1_DMA_RTOR0))
+#define _reg_DMA_BUCR0 (*((P_VU32)MX1_DMA_BUCR0))
+
+/* DMA error type definition */
+#define MX1_DMA_ERR_BTO 0 // burst time-out
+#define MX1_DMA_ERR_RTO 1 // request time-out
+#define MX1_DMA_ERR_TE 2 // transfer error
+#define MX1_DMA_ERR_BO 3 // buffer overflow
+
+
+/* Embedded SRAM */
+
+#define MX1_SRAM_BASE 0x00300000
+#define MX1_SRAM_SIZE 0x00020000
+
+#define
+
+
+#define MX1ADS_SFLASH_BASE 0x0C000000
+#define MX1ADS_SFLASH_SIZE SZ_16M
+
+#define MX1ADS_IO_BASE 0x00200000
+#define MX1ADS_IO_SIZE SZ_256K
+
+#define MX1ADS_VID_BASE 0x00300000
+#define MX1ADS_VID_SIZE 0x26000
+
+#define MX1ADS_VID_START IO_ADDRESS(MX1ADS_VID_BASE)
+
+#define MX1_GPIO_BASE 0x0021C000 // GPIO
+#define MX1_EXT_UART_BASE 0x15000000 // external UART
+#define MX1_TMR1_BASE 0x00202000 // Timer1
+#define MX1ADS_FLASH_BASE 0x0C000000 // sync FLASH
+#define MX1_ESRAM_BASE 0x00300000 // embedded SRAM
+#define MX1ADS_SDRAM_DISK_BASE 0x0B000000 // SDRAM disk base (last 16M of SDRAM)
+
+/* ------------------------------------------------------------------------
+ * Motorola MX1 system registers
+ * ------------------------------------------------------------------------
+ *
+ */
+
+/*
+ * Register offests.
+ *
+ */
+
+#define MX1ADS_AIPI1_OFFSET 0x00000
+#define MX1ADS_WDT_OFFSET 0x01000
+#define MX1ADS_TIM1_OFFSET 0x02000
+#define MX1ADS_TIM2_OFFSET 0x03000
+#define MX1ADS_RTC_OFFSET 0x04000
+#define MX1ADS_LCDC_OFFSET 0x05000
+#define MX1ADS_UART1_OFFSET 0x06000
+#define MX1ADS_UART2_OFFSET 0x07000
+#define MX1ADS_PWM_OFFSET 0x08000
+#define MX1ADS_DMAC_OFFSET 0x09000
+#define MX1ADS_AIPI2_OFFSET 0x10000
+#define MX1ADS_SIM_OFFSET 0x11000
+#define MX1ADS_USBD_OFFSET 0x12000
+#define MX1ADS_SPI1_OFFSET 0x13000
+#define MX1ADS_MMC_OFFSET 0x14000
+#define MX1ADS_ASP_OFFSET 0x15000
+#define MX1ADS_BTA_OFFSET 0x16000
+#define MX1ADS_I2C_OFFSET 0x17000
+#define MX1ADS_SSI_OFFSET 0x18000
+#define MX1ADS_SPI2_OFFSET 0x19000
+#define MX1ADS_MSHC_OFFSET 0x1A000
+#define MX1ADS_PLL_OFFSET 0x1B000
+#define MX1ADS_GPIO_OFFSET 0x1C000
+#define MX1ADS_EIM_OFFSET 0x20000
+#define MX1ADS_SDRAMC_OFFSET 0x21000
+#define MX1ADS_MMA_OFFSET 0x22000
+#define MX1ADS_AITC_OFFSET 0x23000
+#define MX1ADS_CSI_OFFSET 0x24000
+
+
+/*
+ * Register BASEs, based on OFFSETs
+ *
+ */
+
+#define MX1ADS_AIPI1_BASE (MX1ADS_AIPI1_OFFSET + MX1ADS_IO_BASE)
+#define MX1ADS_WDT_BASE (MX1ADS_WDT_OFFSET + MX1ADS_IO_BASE)
+#define MX1ADS_TIM1_BASE (MX1ADS_TIM1_OFFSET + MX1ADS_IO_BASE)
+#define MX1ADS_TIM2_BASE (MX1ADS_TIM2_OFFSET + MX1ADS_IO_BASE)
+#define MX1ADS_RTC_BASE (MX1ADS_RTC_OFFSET + MX1ADS_IO_BASE)
+#define MX1ADS_LCDC_BASE (MX1ADS_LCDC_OFFSET + MX1ADS_IO_BASE)
+#define MX1ADS_UART1_BASE (MX1ADS_UART1_OFFSET + MX1ADS_IO_BASE)
+#define MX1ADS_UART2_BASE (MX1ADS_UART2_OFFSET + MX1ADS_IO_BASE)
+#define MX1ADS_PWM_BASE (MX1ADS_PWM_OFFSET + MX1ADS_IO_BASE)
+#define MX1ADS_DMAC_BASE (MX1ADS_DMAC_OFFSET + MX1ADS_IO_BASE)
+#define MX1ADS_AIPI2_BASE (MX1ADS_AIPI2_OFFSET + MX1ADS_IO_BASE)
+#define MX1ADS_SIM_BASE (MX1ADS_SIM_OFFSET + MX1ADS_IO_BASE)
+#define MX1ADS_USBD_BASE (MX1ADS_USBD_OFFSET + MX1ADS_IO_BASE)
+#define MX1ADS_SPI1_BASE (MX1ADS_SPI1_OFFSET + MX1ADS_IO_BASE)
+#define MX1ADS_MMC_BASE (MX1ADS_MMC_OFFSET + MX1ADS_IO_BASE)
+#define MX1ADS_ASP_BASE (MX1ADS_ASP_OFFSET + MX1ADS_IO_BASE)
+#define MX1ADS_BTA_BASE (MX1ADS_BTA_OFFSET + MX1ADS_IO_BASE)
+#define MX1ADS_I2C_BASE (MX1ADS_I2C_OFFSET + MX1ADS_IO_BASE)
+#define MX1ADS_SSI_BASE (MX1ADS_SSI_OFFSET + MX1ADS_IO_BASE)
+#define MX1ADS_SPI2_BASE (MX1ADS_SPI2_OFFSET + MX1ADS_IO_BASE)
+#define MX1ADS_MSHC_BASE (MX1ADS_MSHC_OFFSET + MX1ADS_IO_BASE)
+#define MX1ADS_PLL_BASE (MX1ADS_PLL_OFFSET + MX1ADS_IO_BASE)
+#define MX1ADS_GPIO_BASE (MX1ADS_GPIO_OFFSET + MX1ADS_IO_BASE)
+#define MX1ADS_EIM_BASE (MX1ADS_EIM_OFFSET + MX1ADS_IO_BASE)
+#define MX1ADS_SDRAMC_BASE (MX1ADS_SDRAMC_OFFSET + MX1ADS_IO_BASE)
+#define MX1ADS_MMA_BASE (MX1ADS_MMA_OFFSET + MX1ADS_IO_BASE)
+#define MX1ADS_AITC_BASE (MX1ADS_AITC_OFFSET + MX1ADS_IO_BASE)
+#define MX1ADS_CSI_BASE (MX1ADS_CSI_OFFSET + MX1ADS_IO_BASE)
+
+
+/*
+ * MX1 Interrupt numbers
+ *
+ */
+#define INT_SOFTINT 0
+#define CSI_INT 6
+#define DSPA_MAC_INT 7
+#define DSPA_INT 8
+#define COMP_INT 9
+#define MSHC_XINT 10
+#define GPIO_INT_PORTA 11
+#define GPIO_INT_PORTB 12
+#define GPIO_INT_PORTC 13
+#define LCDC_INT 14
+#define SIM_INT 15
+#define SIM_DATA_INT 16
+#define RTC_INT 17
+#define RTC_SAMINT 18
+#define UART2_MINT_PFERR 19
+#define UART2_MINT_RTS 20
+#define UART2_MINT_DTR 21
+#define UART2_MINT_UARTC 22
+#define UART2_MINT_TX 23
+#define UART2_MINT_RX 24
+#define UART1_MINT_PFERR 25
+#define UART1_MINT_RTS 26
+#define UART1_MINT_DTR 27
+#define UART1_MINT_UARTC 28
+#define UART1_MINT_TX 29
+#define UART1_MINT_RX 30
+#define VOICE_DAC_INT 31
+#define VOICE_ADC_INT 32
+#define PEN_DATA_INT 33
+#define PWM_INT 34
+#define SDHC_INT 35
+#define I2C_INT 39
+#define CSPI_INT 41
+#define SSI_TX_INT 42
+#define SSI_TX_ERR_INT 43
+#define SSI_RX_INT 44
+#define SSI_RX_ERR_INT 45
+#define TOUCH_INT 46
+#define USBD_INT0 47
+#define USBD_INT1 48
+#define USBD_INT2 49
+#define USBD_INT3 50
+#define USBD_INT4 51
+#define USBD_INT5 52
+#define USBD_INT6 53
+#define BTSYS_INT 55
+#define BTTIM_INT 56
+#define BTWUI_INT 57
+#define TIMER2_INT 58
+#define TIMER1_INT 59
+#define DMA_ERR 60
+#define DMA_INT 61
+#define GPIO_INT_PORTD 62
+
+
+#define MAXIRQNUM 62
+#define MAXFIQNUM 62
+#define MAXSWINUM 62
+
+
+#define TICKS_PER_uSEC 24
+
+/*
+ * These are useconds NOT ticks.
+ *
+ */
+#define mSEC_1 1000
+#define mSEC_5 (mSEC_1 * 5)
+#define mSEC_10 (mSEC_1 * 10)
+#define mSEC_25 (mSEC_1 * 25)
+#define SEC_1 (mSEC_1 * 1000)
+
+
+#endif
+
+
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