]> git.sur5r.net Git - u-boot/commitdiff
ARM: OMAP5/DRA7: Get rid of control_std_fuse_opp_vdd_mpu_2
authorNishanth Menon <nm@ti.com>
Thu, 21 Apr 2016 19:34:22 +0000 (14:34 -0500)
committerTom Rini <trini@konsulko.com>
Mon, 25 Apr 2016 19:10:38 +0000 (15:10 -0400)
This information is already available under vcores->volts.efuse.reg.
There is no reason for duplicating the information since AVS Class 0
definitions are common for OMAP5 and DRA7 and defined with
STD_FUSE_OPP_* macros. This allows a central location of defining
the ABB and voltage definitions especially since they are reused.

This also makes it simpler to prevent mistakes involved when changing
the boot OPP for the device.

Signed-off-by: Nishanth Menon <nm@ti.com>
arch/arm/cpu/armv7/omap-common/clocks-common.c
arch/arm/cpu/armv7/omap5/prcm-regs.c
arch/arm/include/asm/omap_common.h

index cb41055b91e635c0fc06bdf68120e0895c6144a2..27e6871fde86c3421d99a4fc4ecff039bd761ac4 100644 (file)
@@ -584,7 +584,7 @@ void scale_vcores(struct vcores_data const *vcores)
        debug("mpu: %d\n", vcores->mpu.value);
        do_scale_vcore(vcores->mpu.addr, vcores->mpu.value, vcores->mpu.pmic);
        /* Configure MPU ABB LDO after scale */
-       abb_setup((*ctrl)->control_std_fuse_opp_vdd_mpu_2,
+       abb_setup(vcores->mpu.efuse.reg,
                  (*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl,
                  (*prcm)->prm_abbldo_mpu_setup,
                  (*prcm)->prm_abbldo_mpu_ctrl,
@@ -621,7 +621,7 @@ void scale_vcores(struct vcores_data const *vcores)
        do_scale_vcore(vcores->mpu.addr, val, vcores->mpu.pmic);
 
        /* Configure MPU ABB LDO after scale */
-       abb_setup((*ctrl)->control_std_fuse_opp_vdd_mpu_2,
+       abb_setup(vcores->mpu.efuse.reg,
                  (*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl,
                  (*prcm)->prm_abbldo_mpu_setup,
                  (*prcm)->prm_abbldo_mpu_ctrl,
index cd289ddd2be338267167e074c19dd28bdbd0b6ef..c55c6af9e566c1bb126192f9cd9306ee0a6819ac 100644 (file)
@@ -297,7 +297,6 @@ struct prcm_regs const omap5_es1_prcm = {
 
 struct omap_sys_ctrl_regs const omap5_ctrl = {
        .control_status                         = 0x4A002134,
-       .control_std_fuse_opp_vdd_mpu_2         = 0x4A0021B4,
        .control_std_fuse_die_id_0              = 0x4A002200,
        .control_std_fuse_die_id_1              = 0x4A002208,
        .control_std_fuse_die_id_2              = 0x4A00220C,
@@ -440,7 +439,6 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = {
        .control_srcomp_code_latch              = 0x4A002E84,
        .control_ddr_control_ext_0              = 0x4A002E88,
        .control_padconf_core_base              = 0x4A003400,
-       .control_std_fuse_opp_vdd_mpu_2         = 0x4A003B20,
        .control_port_emif1_sdram_config        = 0x4AE0C110,
        .control_port_emif1_lpddr2_nvm_config   = 0x4AE0C114,
        .control_port_emif2_sdram_config        = 0x4AE0C118,
index 8c85f46db6ef66b3093ced39ae45efdaa2303a5d..2daa440432c3db459d75e3a25f1d164643bae1be 100644 (file)
@@ -363,7 +363,6 @@ struct omap_sys_ctrl_regs {
        u32 control_core_mac_id_0_hi;
        u32 control_core_mac_id_1_lo;
        u32 control_core_mac_id_1_hi;
-       u32 control_std_fuse_opp_vdd_mpu_2;
        u32 control_phy_power_usb;
        u32 control_core_mmr_lock1;
        u32 control_core_mmr_lock2;