Program EPLD to force full duplex mode for PHY.

EPLD forces modes of PHY operation. By default full duplex is turned off.
This fix turns it on.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>

diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c
index 7b16f8a39ac0cbfa15e4d6e0e3521a2455ccff36..1bd7efa0baebaa7bdd8ca86e6648d4ea5d42d0a3 100644 (file)
--- a/board/amcc/luan/luan.c
+++ b/board/amcc/luan/luan.c
@@ -39,8 +39,6 @@ extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
  ************************************************************************/
 int board_early_init_f(void)
 {
-       volatile epld_t *x = (epld_t *) CFG_EPLD_BASE;
-
        mtebc( pb0ap,  0x03800000 );    /* set chip selects */
        mtebc( pb0cr,  0xffc58000 );    /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
        mtebc( pb1ap,  0x03800000 );
@@ -66,8 +64,6 @@ int board_early_init_f(void)
        mtdcr( uic0sr, 0x00000000 );    /* clear all interrupts */
        mtdcr( uic0sr, 0xffffffff );
 
-       x->ethuart &= ~EPLD2_RESET_ETH_N; /* put Ethernet+PHY in reset */
-
        return  0;
 }
 
@@ -79,7 +75,18 @@ int board_early_init_f(void)
 int misc_init_r(void)
 {
        volatile epld_t *x = (epld_t *) CFG_EPLD_BASE;
-       x->ethuart |= EPLD2_RESET_ETH_N; /* take Ethernet+PHY out of reset */
+
+       /* set modes of operation */
+       x->ethuart |= EPLD2_ETH_MODE_10 | EPLD2_ETH_MODE_100 |
+               EPLD2_ETH_MODE_1000 | EPLD2_ETH_DUPLEX_MODE;
+       /* clear ETHERNET_AUTO_NEGO bit to turn on autonegotiation */
+       x->ethuart &= ~EPLD2_ETH_AUTO_NEGO;
+       
+       /* put Ethernet+PHY in reset */
+       x->ethuart &= ~EPLD2_RESET_ETH_N;
+       udelay(10000);
+       /* take Ethernet+PHY out of reset */
+       x->ethuart |= EPLD2_RESET_ETH_N;
 
        return  0;
 }

diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c
index cc8e7346dac13467360655d702dbacd00db86349..4e9a05e5bd29d1240b4aa94d1629a3e789f140ca 100644 (file)
--- a/cpu/ppc4xx/4xx_enet.c
+++ b/cpu/ppc4xx/4xx_enet.c
@@ -138,7 +138,8 @@
 #define BI_PHYMODE_MII   7
 #endif
 
-#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || \
+       defined(CONFIG_440GRX) || defined(CONFIG_440SP)
 #define SDR0_MFR_ETH_CLK_SEL_V(n)      ((0x01<<27) / (n+1))
 #endif
 
@@ -408,7 +409,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
        int ethgroup = -1;
 #endif
 #endif
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+       defined(CONFIG_440SPE) || defined(CONFIG_440SP)
        unsigned long mfr;
 #endif
 
@@ -500,7 +502,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
        __asm__ volatile ("eieio");
 
        /* reset emac so we have access to the phy */
-#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+       defined(CONFIG_440SP)
        /* provide clocks for EMAC internal loopback  */
        mfsdr (sdr_mfr, mfr);
        mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum);
@@ -518,7 +521,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
        if (failsafe <= 0)
                printf("\nProblem resetting EMAC!\n");
 
-#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+       defined(CONFIG_440SP)
        /* remove clocks for EMAC internal loopback  */
        mfsdr (sdr_mfr, mfr);
        mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum);