mpc83xx: Rename CONFIG_SYS_DDR_CONFIG and cleanup DDR csbnds code

Rename CONFIG_SYS_DDR_CONFIG to include which CS it is configuring
Cleanup the setting of the csnbds to respect the setting of
CONFIG_SYS_DDR_SDRAM_BASE
Use __ilog2 instead of writing the code to compute it
Disable unused CS configs
Ensure ddrlaw.bar is configured

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c
index 7aede136d6e236c5bdd4ceaccda3ca58598b4abc..a9a2ba47065936134a7c5bd2bb58c96c0ea31cb1 100644 (file)
--- a/board/freescale/mpc8313erdb/sdram.c
+++ b/board/freescale/mpc8313erdb/sdram.c
@@ -74,8 +74,14 @@ static long fixed_sdram(void)
         */
        __udelay(50000);
 
-       im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
-       im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
+#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#warning Chip select bounds is only configurable in 16MB increments
+#endif
+       im->ddr.csbnds[0].csbnds =
+               ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+               (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
+                       CSBNDS_EA);
+       im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
 
        /* Currently we use only one CS, so disable the other bank. */
        im->ddr.cs_config[1] = 0;

diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c
index 620540f830759b6675bd995d1eb13239647479fa..ebd5274a5650bb2da623fde2895ab122fef6664a 100644 (file)
--- a/board/freescale/mpc8349emds/mpc8349emds.c
+++ b/board/freescale/mpc8349emds/mpc8349emds.c
@@ -101,18 +101,10 @@ phys_size_t initdram (int board_type)
 int fixed_sdram(void)
 {
        volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-       u32 msize = 0;
-       u32 ddr_size;
-       u32 ddr_size_log2;
-
-       msize = CONFIG_SYS_DDR_SIZE;
-       for (ddr_size = msize << 20, ddr_size_log2 = 0;
-            (ddr_size > 1);
-            ddr_size = ddr_size>>1, ddr_size_log2++) {
-               if (ddr_size & 1) {
-                       return -1;
-               }
-       }
+       u32 msize = CONFIG_SYS_DDR_SIZE;
+       u32 ddr_size = msize << 20;     /* DDR size in bytes */
+       u32 ddr_size_log2 = __ilog2(ddr_size);
+
        im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
        im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
 
@@ -133,8 +125,15 @@ int fixed_sdram(void)
        im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
        im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
 #else
-       im->ddr.csbnds[2].csbnds = 0x0000000f;
-       im->ddr.cs_config[2] = CONFIG_SYS_DDR_CONFIG;
+
+#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#warning Chip select bounds is only configurable in 16MB increments
+#endif
+       im->ddr.csbnds[2].csbnds =
+               ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+               (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
+                               CSBNDS_EA_SHIFT) & CSBNDS_EA);
+       im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
 
        /* currently we use only one CS, so disable the other banks */
        im->ddr.cs_config[0] = 0;

diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c
index 56475795b68246c4cf7448cf52c71ff27c1c9bfc..9cc808ed7d6978d81f9a549e625c28a9338491dd 100644 (file)
--- a/board/freescale/mpc8349itx/mpc8349itx.c
+++ b/board/freescale/mpc8349itx/mpc8349itx.c
@@ -43,23 +43,27 @@
 int fixed_sdram(void)
 {
        volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-       u32 ddr_size;           /* The size of RAM, in bytes */
-       u32 ddr_size_log2 = 0;
-
-       for (ddr_size = CONFIG_SYS_DDR_SIZE * 0x100000; ddr_size > 1; ddr_size >>= 1) {
-               if (ddr_size & 1) {
-                       return -1;
-               }
-               ddr_size_log2++;
-       }
+       /* The size of RAM, in bytes */
+       u32 ddr_size = CONFIG_SYS_DDR_SIZE << 20;
+       u32 ddr_size_log2 = __ilog2(ddr_size);
 
        im->sysconf.ddrlaw[0].ar =
            LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
        im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
 
-       /* Only one CS0 for DDR */
-       im->ddr.csbnds[0].csbnds = 0x0000000f;
-       im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
+#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#warning Chip select bounds is only configurable in 16MB increments
+#endif
+       im->ddr.csbnds[0].csbnds =
+               ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+               (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
+                               CSBNDS_EA_SHIFT) & CSBNDS_EA);
+       im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+
+       /* Only one CS for DDR */
+       im->ddr.cs_config[1] = 0;
+       im->ddr.cs_config[2] = 0;
+       im->ddr.cs_config[3] = 0;
 
        debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);
        debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);

diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c
index 51d8035203fec240e0e247e28fdbea977f47dd65..a0114f6c299c478c5bc2bc9f6fed8c38724fc139 100644 (file)
--- a/board/freescale/mpc8360emds/mpc8360emds.c
+++ b/board/freescale/mpc8360emds/mpc8360emds.c
@@ -216,19 +216,15 @@ phys_size_t initdram(int board_type)
 int fixed_sdram(void)
 {
        volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-       u32 msize = 0;
-       u32 ddr_size;
-       u32 ddr_size_log2;
-
-       msize = CONFIG_SYS_DDR_SIZE;
-       for (ddr_size = msize << 20, ddr_size_log2 = 0;
-            (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
-               if (ddr_size & 1) {
-                       return -1;
-               }
-       }
+       u32 msize = CONFIG_SYS_DDR_SIZE;
+       u32 ddr_size = msize << 20;
+       u32 ddr_size_log2 = __ilog2(ddr_size);
+       u32 half_ddr_size = ddr_size >> 1;
+
+       im->sysconf.ddrlaw[0].bar =
+               CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
        im->sysconf.ddrlaw[0].ar =
-           LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
+               LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
 #if (CONFIG_SYS_DDR_SIZE != 256)
 #warning Currenly any ddr size other than 256 is not supported
 #endif
@@ -246,11 +242,25 @@ int fixed_sdram(void)
        im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
        im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
 #else
-       im->ddr.csbnds[0].csbnds = 0x00000007;
-       im->ddr.csbnds[1].csbnds = 0x0008000f;
 
-       im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
-       im->ddr.cs_config[1] = CONFIG_SYS_DDR_CONFIG;
+#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#warning Chip select bounds is only configurable in 16MB increments
+#endif
+       im->ddr.csbnds[0].csbnds =
+               ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+               (((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size - 1) >>
+                               CSBNDS_EA_SHIFT) & CSBNDS_EA);
+       im->ddr.csbnds[1].csbnds =
+               (((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size) >>
+                               CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+               (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
+                               CSBNDS_EA_SHIFT) & CSBNDS_EA);
+
+       im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+       im->ddr.cs_config[1] = CONFIG_SYS_DDR_CS1_CONFIG;
+
+       im->ddr.cs_config[2] = 0;
+       im->ddr.cs_config[3] = 0;
 
        im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
        im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;

diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c
index 50fae7c367382d6aa9e14ce044d1bb3d82175bda..42f4c1ef06774506a204641e6869c689dbcb4173 100644 (file)
--- a/board/sbc8349/sbc8349.c
+++ b/board/sbc8349/sbc8349.c
@@ -89,26 +89,25 @@ phys_size_t initdram (int board_type)
 int fixed_sdram(void)
 {
        volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-       u32 msize = 0;
-       u32 ddr_size;
-       u32 ddr_size_log2;
-
-       msize = CONFIG_SYS_DDR_SIZE;
-       for (ddr_size = msize << 20, ddr_size_log2 = 0;
-            (ddr_size > 1);
-            ddr_size = ddr_size>>1, ddr_size_log2++) {
-               if (ddr_size & 1) {
-                       return -1;
-               }
-       }
+       u32 msize = CONFIG_SYS_DDR_SIZE;
+       u32 ddr_size = msize << 20;     /* DDR size in bytes */
+       u32 ddr_size_log2 = __ilog2(msize);
+
        im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
        im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
 
 #if (CONFIG_SYS_DDR_SIZE != 256)
 #warning Currently any ddr size other than 256 is not supported
 #endif
-       im->ddr.csbnds[2].csbnds = 0x0000000f;
-       im->ddr.cs_config[2] = CONFIG_SYS_DDR_CONFIG;
+
+#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#warning Chip select bounds is only configurable in 16MB increments
+#endif
+       im->ddr.csbnds[2].csbnds =
+               ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+               (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
+                               CSBNDS_EA_SHIFT) & CSBNDS_EA);
+       im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
 
        /* currently we use only one CS, so disable the other banks */
        im->ddr.cs_config[0] = 0;

diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c
index 166e459a39051894a553fcf5a0896b1a5126ea18..924d87112305b14ffa1a1252a4195b59c8cb9e78 100644 (file)
--- a/board/ve8313/ve8313.c
+++ b/board/ve8313/ve8313.c
@@ -65,8 +65,14 @@ static long fixed_sdram(void)
         */
        __udelay(50000);
 
-       out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
-       out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CONFIG);
+#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#warning Chip select bounds is only configurable in 16MB increments
+#endif
+       out_be32(&im->ddr.csbnds[0].csbnds,
+               ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+               (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
+                       CSBNDS_EA));
+       out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
 
        /* Currently we use only one CS, so disable the other bank. */
        out_be32(&im->ddr.cs_config[1], 0);

diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 21771fd0116aef12c0a4ec3cb71731e6cd7c2b9f..31503af5d239eb9d37142e6f1e868d69f3ba9fe6 100644 (file)
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -130,7 +130,7 @@
  * seem to have the SPD connected to I2C.
  */
 #define CONFIG_SYS_DDR_SIZE    128             /* MB */
-#define CONFIG_SYS_DDR_CONFIG  (CSCONFIG_EN \
+#define CONFIG_SYS_DDR_CS0_CONFIG      (CSCONFIG_EN \
                                | CSCONFIG_ODT_RD_NEVER \
                                | CSCONFIG_ODT_WR_ONLY_CURRENT \
                                | CSCONFIG_ROW_BIT_13 \

diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index a6aebb76cef6878f73e7ba210ff06da63d7b5ce6..c76455ab80c2d86435d7a4912c4cfbbfbb84edc7 100644 (file)
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -142,7 +142,7 @@
 #define CONFIG_SYS_DDR_SDRAM_CFG       0x43000000
 #define CONFIG_SYS_DDR_SDRAM_CFG2      0x00401000
 #else
-#define CONFIG_SYS_DDR_CONFIG  (CSCONFIG_EN \
+#define CONFIG_SYS_DDR_CS2_CONFIG      (CSCONFIG_EN \
                                | CSCONFIG_ROW_BIT_13 \
                                | CSCONFIG_COL_BIT_10)
 #define CONFIG_SYS_DDR_TIMING_1        0x36332321

diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index a2ceba7ae33fafa37cd7c787737bb6921dbe3626..04f2da9b81877e6cae8017c440684c220cf7b28e 100644 (file)
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -206,7 +206,7 @@
 /* No SPD? Then manually set up DDR parameters */
 #ifndef CONFIG_SPD_EEPROM
     #define CONFIG_SYS_DDR_SIZE                256     /* Mb */
-    #define CONFIG_SYS_DDR_CONFIG      (CSCONFIG_EN \
+    #define CONFIG_SYS_DDR_CS0_CONFIG  (CSCONFIG_EN \
                                        | CSCONFIG_ROW_BIT_13 \
                                        | CSCONFIG_COL_BIT_10)
 

diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index aaff93f09ab0b305e234c5b11ddb7666e874f7b9..e81f3d4df8584bc3799f443e4ecac127a9a12c2a 100644 (file)
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -145,9 +145,10 @@
 #define CONFIG_SYS_DDR_SDRAM_CFG       0x43000000
 #define CONFIG_SYS_DDR_SDRAM_CFG2      0x00401000
 #else
-#define CONFIG_SYS_DDR_CONFIG  (CSCONFIG_EN \
-                               | CSCONFIG_ROW_BIT_13 \
-                               | CSCONFIG_COL_BIT_9)
+#define CONFIG_SYS_DDR_CS0_CONFIG      (CSCONFIG_EN \
+                                       | CSCONFIG_ROW_BIT_13 \
+                                       | CSCONFIG_COL_BIT_9)
+#define CONFIG_SYS_DDR_CS1_CONFIG      CONFIG_SYS_DDR_CS0_CONFIG
 #define CONFIG_SYS_DDR_TIMING_1        0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
 #define CONFIG_SYS_DDR_TIMING_2        0x00000800 /* may need tuning */
 #define CONFIG_SYS_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */

diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 4812f686d56e79407a429ffb4744ed37892daeba..e50d82963226350e2736cc0cc7d2df7b18ba967f 100644 (file)
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -114,7 +114,7 @@
  * NB: manual DDR setup untested on sbc834x
  */
 #define CONFIG_SYS_DDR_SIZE            256             /* MB */
-#define CONFIG_SYS_DDR_CONFIG          (CSCONFIG_EN \
+#define CONFIG_SYS_DDR_CS2_CONFIG      (CSCONFIG_EN \
                                        | CSCONFIG_ROW_BIT_13 \
                                        | CSCONFIG_COL_BIT_10)
 #define CONFIG_SYS_DDR_TIMING_1        0x36332321

diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h
index 1d458898a877eb58f1d0342688672592b6558dea..bf50d09d0764ba9cb07b397f7e2bfd52e901da63 100644 (file)
--- a/include/configs/ve8313.h
+++ b/include/configs/ve8313.h
@@ -79,7 +79,7 @@
  * have the SPD connected to I2C.
  */
 #define CONFIG_SYS_DDR_SIZE    128     /* MB */
-#define CONFIG_SYS_DDR_CONFIG  (CSCONFIG_EN \
+#define CONFIG_SYS_DDR_CS0_CONFIG      (CSCONFIG_EN \
                                | CSCONFIG_AP \
                                | CSCONFIG_ODT_RD_NEVER \
                                | CSCONFIG_ODT_WR_ALL \