timer.o
ifdef CONFIG_SPL_BUILD
-obj-y += spl.o spl_boot.o
+obj-y += spl.o
obj-$(CONFIG_SPEAR600) += spear600.o
obj-$(CONFIG_DDR_MT47H64M16) += spr600_mt47h64m16_3_333_cl5_psync.o
obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_333_cl5_psync.o
#include <asm/arch/spr_misc.h>
#include <asm/arch/spr_defs.h>
+void spear_late_init(void)
+{
+ struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+ writel(0x80000007, &misc_p->arb_icm_ml1);
+ writel(0x80000007, &misc_p->arb_icm_ml2);
+ writel(0x80000007, &misc_p->arb_icm_ml3);
+ writel(0x80000007, &misc_p->arb_icm_ml4);
+ writel(0x80000007, &misc_p->arb_icm_ml5);
+ writel(0x80000007, &misc_p->arb_icm_ml6);
+ writel(0x80000007, &misc_p->arb_icm_ml7);
+ writel(0x80000007, &misc_p->arb_icm_ml8);
+ writel(0x80000007, &misc_p->arb_icm_ml9);
+}
+
static void sel_1v8(void)
{
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
}
}
-/*
- * soc_init:
- */
-void soc_init(void)
-{
- /* Nothing to be done for SPEAr600 */
-}
-
/*
* xxx_boot_selected:
*
*/
#include <common.h>
+#include <spl.h>
#include <version.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/spr_defs.h>
#include <asm/arch/spr_misc.h>
#include <asm/arch/spr_syscntl.h>
+#include <linux/mtd/st_smi.h>
static void ddr_clock_init(void)
{
#endif
}
-void lowlevel_init(void)
+/*
+ * SNOR (Serial NOR flash) related functions
+ */
+static void snor_init(void)
+{
+ struct smi_regs *const smicntl =
+ (struct smi_regs * const)CONFIG_SYS_SMI_BASE;
+
+ /* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */
+ writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4,
+ &smicntl->smi_cr1);
+}
+
+u32 spl_boot_device(void)
+{
+ u32 mode;
+
+ /* Currently only SNOR is supported as the only */
+ if (snor_boot_selected()) {
+ /* SNOR-SMI initialization */
+ snor_init();
+
+ mode = BOOT_DEVICE_NOR;
+ }
+
+ return mode;
+}
+
+void board_init_f(ulong dummy)
{
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
- const char *u_boot_rev = U_BOOT_VERSION;
/* Initialize PLLs */
sys_init();
- /* Initialize UART */
- serial_init();
-
- /* Print U-Boot SPL version string */
- serial_puts("\nU-Boot SPL ");
- /* Avoid a second "U-Boot" coming from this string */
- u_boot_rev = &u_boot_rev[7];
- serial_puts(u_boot_rev);
- serial_puts(" (");
- serial_puts(U_BOOT_DATE);
- serial_puts(" - ");
- serial_puts(U_BOOT_TIME);
- serial_puts(")\n");
-
-#if defined(CONFIG_OS_BOOT)
- writel(readl(&misc_p->periph1_clken) | PERIPH_UART1,
- &misc_p->periph1_clken);
-#endif
+ preloader_console_init();
+ arch_cpu_init();
/* Enable IPs (release reset) */
writel(PERIPH_RST_ALL, &misc_p->periph1_rst);
/* Initialize MPMC */
- serial_puts("Configure DDR\n");
+ puts("Configure DDR\n");
mpmc_init();
+ spear_late_init();
- /* SoC specific initialization */
- soc_init();
-}
-
-void spear_late_init(void)
-{
- struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-
- writel(0x80000007, &misc_p->arb_icm_ml1);
- writel(0x80000007, &misc_p->arb_icm_ml2);
- writel(0x80000007, &misc_p->arb_icm_ml3);
- writel(0x80000007, &misc_p->arb_icm_ml4);
- writel(0x80000007, &misc_p->arb_icm_ml5);
- writel(0x80000007, &misc_p->arb_icm_ml6);
- writel(0x80000007, &misc_p->arb_icm_ml7);
- writel(0x80000007, &misc_p->arb_icm_ml8);
- writel(0x80000007, &misc_p->arb_icm_ml9);
+ board_init_r(NULL, 0);
}
+++ /dev/null
-/*
- * (C) Copyright 2000-2009
- * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
- *
- * Copyright (C) 2012 Stefan Roese <sr@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <image.h>
-#include <linux/compiler.h>
-#include <asm/io.h>
-#include <asm/arch/spr_defs.h>
-#include <linux/mtd/st_smi.h>
-
-static const char kernel_name[] = "Linux";
-static const char loader_name[] = "U-Boot";
-
-int image_check_header(image_header_t *hdr, const char *name)
-{
- if (image_check_magic(hdr) &&
- (!strncmp(image_get_name(hdr), name, strlen(name))) &&
- image_check_hcrc(hdr)) {
- return 1;
- }
- return 0;
-}
-
-int image_check_data(image_header_t *hdr)
-{
- if (image_check_dcrc(hdr))
- return 1;
-
- return 0;
-}
-
-/*
- * SNOR (Serial NOR flash) related functions
- */
-void snor_init(void)
-{
- struct smi_regs *const smicntl =
- (struct smi_regs * const)CONFIG_SYS_SMI_BASE;
-
- /* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */
- writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4,
- &smicntl->smi_cr1);
-}
-
-static int snor_image_load(u8 *load_addr, void (**image_p)(void),
- const char *image_name)
-{
- image_header_t *header;
-
- /*
- * Since calculating the crc in the SNOR flash does not
- * work, we copy the image to the destination address
- * minus the header size. And point the header to this
- * new destination. This will not work for address 0
- * of course.
- */
- header = (image_header_t *)load_addr;
- memcpy((ulong *)(image_get_load(header) - sizeof(image_header_t)),
- (const ulong *)load_addr,
- image_get_data_size(header) + sizeof(image_header_t));
- header = (image_header_t *)(image_get_load(header) -
- sizeof(image_header_t));
-
- if (image_check_header(header, image_name)) {
- if (image_check_data(header)) {
- /* Jump to boot image */
- *image_p = (void *)image_get_load(header);
- return 1;
- }
- }
-
- return 0;
-}
-
-static void boot_image(void (*image)(void))
-{
- void (*funcp)(void) __noreturn = (void *)image;
-
- (*funcp)();
-}
-
-/*
- * spl_boot:
- *
- * All supported booting types of all supported SoCs are listed here.
- * Generic readback APIs are provided for each supported booting type
- * eg. nand_read_skip_bad
- */
-u32 spl_boot(void)
-{
- void (*image)(void);
-
-#ifdef CONFIG_SPEAR_USBTTY
- plat_late_init();
- return 1;
-#endif
-
- /*
- * All the supported booting devices are listed here. Each of
- * the booting type supported by the platform would define the
- * macro xxx_BOOT_SUPPORTED to true.
- */
-
- if (SNOR_BOOT_SUPPORTED && snor_boot_selected()) {
- /* SNOR-SMI initialization */
- snor_init();
-
- serial_puts("Booting via SNOR\n");
- /* Serial NOR booting */
- if (1 == snor_image_load((u8 *)CONFIG_SYS_UBOOT_BASE,
- &image, loader_name)) {
- /* Platform related late initialasations */
- plat_late_init();
-
- /* Jump to boot image */
- serial_puts("Jumping to U-Boot\n");
- boot_image(image);
- return 1;
- }
- }
-
- if (NAND_BOOT_SUPPORTED && nand_boot_selected()) {
- /* NAND booting */
- /* Not ported from XLoader to SPL yet */
- return 0;
- }
-
- if (PNOR_BOOT_SUPPORTED && pnor_boot_selected()) {
- /* PNOR booting */
- /* Not ported from XLoader to SPL yet */
- return 0;
- }
-
- if (MMC_BOOT_SUPPORTED && mmc_boot_selected()) {
- /* MMC booting */
- /* Not ported from XLoader to SPL yet */
- return 0;
- }
-
- if (SPI_BOOT_SUPPORTED && spi_boot_selected()) {
- /* SPI booting */
- /* Not supported for any platform as of now */
- return 0;
- }
-
- if (I2C_BOOT_SUPPORTED && i2c_boot_selected()) {
- /* I2C booting */
- /* Not supported for any platform as of now */
- return 0;
- }
-
- /*
- * All booting types without memory are listed as below
- * Control has to be returned to BootROM in case of all
- * the following booting scenarios
- */
-
- if (USB_BOOT_SUPPORTED && usb_boot_selected()) {
- plat_late_init();
- return 1;
- }
-
- if (TFTP_BOOT_SUPPORTED && tftp_boot_selected()) {
- plat_late_init();
- return 1;
- }
-
- if (UART_BOOT_SUPPORTED && uart_boot_selected()) {
- plat_late_init();
- return 1;
- }
-
- /* Ideally, the control should not reach here. */
- hang();
-}
* BSS area lies in the DDR location which is not yet initialized
* bss is assumed to be uninitialized.
*/
- bl spl_boot
ldmia sp!, {r0-r12,pc}
/*
* Go setup Memory and board specific bits prior to relocation.
*/
stmdb sp!, {lr}
- bl lowlevel_init /* go setup pll,mux,memory */
+ bl _main /* _main will call board_init_f */
ldmia sp!, {pc}
/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ *
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* SPDX-License-Identifier: GPL-2.0+
*/
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+ LENGTH = CONFIG_SPL_MAX_SIZE }
+
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
+ .text :
{
+ __start = .;
*(.vectors)
- arch/arm/cpu/arm926ejs/spear/start.o (.text*)
+ CPUDIR/spear/start.o (.text*)
*(.text*)
- }
+ } > .sram
. = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+ .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
. = ALIGN(4);
- .data : {
- *(.data*)
- }
+ .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
. = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ } > .sram
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
- }
+ . = ALIGN(4);
+ __image_copy_end = .;
+ _end = .;
- .bss : {
+ .bss :
+ {
. = ALIGN(4);
__bss_start = .;
*(.bss*)
. = ALIGN(4);
__bss_end = .;
- }
-
- .end :
- {
- *(.__end)
- }
-
- _image_binary_end = .;
-
- .dynsym _image_binary_end : { *(.dynsym) }
- .dynbss : { *(.dynbss) }
- .dynstr : { *(.dynstr*) }
- .dynamic : { *(.dynamic*) }
- .hash : { *(.hash*) }
- .plt : { *(.plt*) }
- .interp : { *(.interp*) }
- .gnu : { *(.gnu*) }
- .ARM.exidx : { *(.ARM.exidx*) }
+ } > .sram
}
extern unsigned int setfreq_sz;
void plat_ddr_init(void);
-void soc_init(void);
void spear_late_init(void);
-void plat_late_init(void);
int snor_boot_selected(void);
int nand_boot_selected(void);
* (C) Copyright 2009
* Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
*
- * Copyright (C) 2012 Stefan Roese <sr@denx.de>
+ * Copyright (C) 2012, 2015 Stefan Roese <sr@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* Use last 2 lwords in internal SRAM for bootcounter */
#define CONFIG_BOOTCOUNT_LIMIT
-#define CONFIG_SYS_BOOTCOUNT_ADDR 0xd2801ff8
+#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SRAM_BASE + \
+ CONFIG_SRAM_SIZE)
#define CONFIG_HOSTNAME x600
#define CONFIG_UBI_PART ubi0
#define PHYS_SDRAM_1_MAXSIZE 0x40000000
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xD2800000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
+#define CONFIG_SRAM_BASE 0xd2800000
+/* Preserve the last 2 lwords for the boot-counter */
+#define CONFIG_SRAM_SIZE ((8 << 10) - 0x8)
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SRAM_BASE
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SRAM_SIZE
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* SPL related defines
*/
-#define CONFIG_SPL_TEXT_BASE 0xd2800b00
+#define CONFIG_SPL_TEXT_BASE 0xd2800b00
+#define CONFIG_SPL_MAX_SIZE (CONFIG_SRAM_SIZE - 0xb00)
#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear"
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds"
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_NOR_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */
#define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */
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