ARM: align MVBAR on 32 byte boundary

The lower 5 bit of MVBAR is UNK/SBZP.
So, Monitor Vector Base Address must be 32-byte aligned.
On the other hand, the secure monitor handler does not need
32-byte alignment.

This commit moves ".algin 5" directive to the correct place.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Andre Przywara <andre.przywara@linaro.org>
Acked-by: Andre Przywara <andre.przywara@linaro.org>

diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
index 24b4c18bd452fa155bcd5ed94c755aa05a33efe7..6367e09612bcd04056c079c35dbd79033d49a157 100644 (file)
--- a/arch/arm/cpu/armv7/nonsec_virt.S
+++ b/arch/arm/cpu/armv7/nonsec_virt.S
@@ -14,6 +14,7 @@
 .arch_extension sec
 .arch_extension virt
 
+       .align  5
 /* the vector table for secure state and HYP mode */
 _monitor_vectors:
        .word 0 /* reset */
@@ -32,7 +33,6 @@ _monitor_vectors:
  * to non-secure state.
  * We use only r0 and r1 here, due to constraints in the caller.
  */
-       .align  5
 _secure_monitor:
        mrc     p15, 0, r1, c1, c1, 0           @ read SCR
        bic     r1, r1, #0x4e                   @ clear IRQ, FIQ, EA, nET bits