/*
- * Copyright 2017 Armadeus Systems <support@armadeus.com>
+ * Copyright 2018 Armadeus Systems <support@armadeus.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
/* eMMC */
&usdhc1 {
+ u-boot,dm-spl;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
bus-width = <8>;
};
pinctrl_usdhc1: usdhc1grp {
+ u-boot,dm-spl;
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
};
&uart1 {
+ u-boot,dm-spl;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
pinctrl_uart1: uart1grp {
+ u-boot,dm-spl;
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
#size-cells = <1>;
reg = <0x02000000 0x40000>;
ranges;
+ u-boot,dm-spl;
ecspi1: ecspi@02008000 {
#address-cells = <1>;
int opos6ul_board_late_init(void);
-#ifdef CONFIG_SPL_BUILD
-void opos6ul_setup_uart_debug(void);
-#endif
-
#endif
select DM_MMC
select DM_THERMAL
select SUPPORT_SPL
+ select SPL_DM if SPL
+ select SPL_OF_CONTROL if SPL
+ select SPL_SEPARATE_BSS if SPL
+ select SPL_PINCTRL if SPL
config MX6ULL
select SYS_L2CACHE_OFF
/*
- * Copyright (C) 2017 Armadeus Systems
+ * Copyright (C) 2018 Armadeus Systems
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
-#include <asm/arch/mx6ul_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
#include <common.h>
#include <environment.h>
-#include <fsl_esdhc.h>
-#include <mmc.h>
DECLARE_GLOBAL_DATA_PTR;
return opos6ul_board_late_init();
}
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- return cfg->esdhc_base == USDHC1_BASE_ADDR;
-}
-
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
#ifdef CONFIG_SPL_BUILD
#include <asm/arch/mx6-ddr.h>
-#include <asm/arch/opos6ul.h>
#include <linux/libfdt.h>
#include <spl.h>
-#define USDHC_PAD_CTRL ( \
- PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST \
-)
-
-struct fsl_esdhc_cfg usdhc_cfg[1] = {
- {USDHC1_BASE_ADDR, 0, 8},
-};
-
-static iomux_v3_cfg_t const usdhc1_pads[] = {
- MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-};
-
static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
.grp_addds = 0x00000030,
.grp_ddrmode_ctl = 0x00020000,
.trasmin = 3750,
};
-int board_mmc_init(bd_t *bis)
-{
- imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
-}
-
static void ccgr_init(void)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
}
+void spl_board_init(void)
+{
+ preloader_console_init();
+}
+
void board_init_f(ulong dummy)
{
ccgr_init();
/* setup GP timer */
timer_init();
- /* UART clocks enabled and gd valid - init serial console */
- opos6ul_setup_uart_debug();
- preloader_console_init();
-
/* DDR initialization */
spl_dram_init();
}
/*
- * Copyright (C) 2017 Armadeus Systems
+ * Copyright (C) 2018 Armadeus Systems
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/arch/clock.h>
#include <asm/arch/mx6-pins.h>
-#include <asm/arch/opos6ul.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
return 0;
}
-
-#ifdef CONFIG_SPL_BUILD
-#define UART_PAD_CTRL ( \
- PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST \
-)
-
-static iomux_v3_cfg_t const uart1_pads[] = {
- MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-void opos6ul_setup_uart_debug(void)
-{
- imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
-}
-#endif /* CONFIG_SPL_BUILD */
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_OPOS6ULDEV=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-opos6uldev"
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x400
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttymxc0,115200"
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="imx6ul-opos6uldev.dtb"
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
#include "imx6_spl.h"
#ifdef CONFIG_SPL_BUILD
-#undef CONFIG_DM_GPIO
-#undef CONFIG_DM_MMC
-#undef CONFIG_BLK
-
-#define CONFIG_MXC_UART_BASE UART1_BASE
+#undef CONFIG_DM_REGULATOR
#endif
#endif
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* MMC */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SUPPORT_EMMC_BOOT
/* USB */
#endif
/* LCD */
+#ifndef CONFIG_SPL_BUILD
#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_LOGO
#define CONFIG_SPLASH_SCREEN
#define CONFIG_VIDEO_MXS
#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR
#endif
+#endif
/* Environment is stored in the eMMC boot partition */
#define CONFIG_SYS_MMC_ENV_DEV 0