]> git.sur5r.net Git - u-boot/commitdiff
fpga: zynqmp: Fix the nonsecure bitstream loading issue
authorSiva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Wed, 14 Mar 2018 18:47:24 +0000 (00:17 +0530)
committerMichal Simek <michal.simek@xilinx.com>
Mon, 9 Apr 2018 10:14:50 +0000 (12:14 +0200)
Xilfpga library expects the size of bitstream in a pointer
but currenly we are passing the size as a value. This patch
fixes this issue.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
drivers/fpga/zynqmppl.c

index aae0efc7348ee8b9cdb5974a8edadcf3cba37a4a..43e8b2520e353802172fef8a0f8a8ad765229899 100644 (file)
@@ -11,6 +11,7 @@
 #include <zynqmppl.h>
 #include <linux/sizes.h>
 #include <asm/arch/sys_proto.h>
+#include <memalign.h>
 
 #define DUMMY_WORD     0xffffffff
 
@@ -195,6 +196,7 @@ static int zynqmp_validate_bitstream(xilinx_desc *desc, const void *buf,
 static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
                     bitstream_type bstype)
 {
+       ALLOC_CACHE_ALIGN_BUFFER(u32, bsizeptr, 1);
        u32 swap;
        ulong bin_buf;
        int ret;
@@ -205,15 +207,17 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
                return FPGA_FAIL;
 
        bin_buf = zynqmp_align_dma_buffer((u32 *)buf, bsize, swap);
+       bsizeptr = (u32 *)&bsize;
 
        debug("%s called!\n", __func__);
        flush_dcache_range(bin_buf, bin_buf + bsize);
+       flush_dcache_range((ulong)bsizeptr, (ulong)bsizeptr + sizeof(size_t));
 
        buf_lo = (u32)bin_buf;
        buf_hi = upper_32_bits(bin_buf);
        bstype |= BIT(ZYNQMP_FPGA_BIT_NS);
-       ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi, bsize,
-                        bstype, ret_payload);
+       ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi,
+                        (u32)(uintptr_t)bsizeptr, bstype, ret_payload);
        if (ret)
                debug("PL FPGA LOAD fail\n");