powerpc mpc85xx: Only clear TSR:WIS in watchdog_reset.

We should only write TSR_WIS to the SPRN_TSR register in
reset_85xx_watchdog.

The old code would cause the timer interrupt to be acknowledged when the
watchdog was reset, and we would then get no more timer interrupts.
This bug would affect all mpc85xx boards that have the watchdog enabled.

Signed-off-by: Mark Marshall <Mark.Marshall@omicron.at>
Signed-off-by: Andy Fleming <afleming@freescale.com>

diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 5ddb29435c139a7f0541a59e4a859b83919408df..a5048a130647383cb7925f8128cbed2800ed1281 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -270,10 +270,7 @@ reset_85xx_watchdog(void)
        /*
         * Clear TSR(WIS) bit by writing 1
         */
-       unsigned long val;
-       val = mfspr(SPRN_TSR);
-       val |= TSR_WIS;
-       mtspr(SPRN_TSR, val);
+       mtspr(SPRN_TSR, TSR_WIS);
 }
 #endif /* CONFIG_WATCHDOG */