]> git.sur5r.net Git - u-boot/commitdiff
lpc32xx: move common SLC NAND defines to arch/config.h
authorVladimir Zapolskiy <vz@mleia.com>
Tue, 11 Aug 2015 16:57:09 +0000 (19:57 +0300)
committerTom Rini <trini@konsulko.com>
Tue, 18 Aug 2015 17:45:55 +0000 (13:45 -0400)
A number of LPC32xx SLC NAND defines is dictated by controller
hardware limits and OOB layout is defined by operating system, the
definitions are common for all users. Since those macro are used
in out of NAND SLC driver code (simple NAND SPL framework), they can
not be placed into the driver, therefore move them from board config
files to arch/config.h

The change also adds OOB layout details specific to small page NAND
devices taken from Linux kernel.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
arch/arm/include/asm/arch-lpc32xx/config.h
include/configs/devkit3250.h

index d57bc4877ea939d6d0e6129ced89fb3394e20975..d161ad213a16b163c5cdd521601e6df5a0ded879 100644 (file)
 /* Ethernet */
 #define LPC32XX_ETH_BASE ETHERNET_BASE
 
+/* NAND */
+#if defined(CONFIG_NAND_LPC32XX_SLC)
+#define NAND_LARGE_BLOCK_PAGE_SIZE     0x800
+#define NAND_SMALL_BLOCK_PAGE_SIZE     0x200
+
+#if !defined(CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE      NAND_LARGE_BLOCK_PAGE_SIZE
+#endif
+
+#if (CONFIG_SYS_NAND_PAGE_SIZE == NAND_LARGE_BLOCK_PAGE_SIZE)
+#define CONFIG_SYS_NAND_OOBSIZE                64
+#define CONFIG_SYS_NAND_ECCPOS         { 40, 41, 42, 43, 44, 45, 46, 47, \
+                                         48, 49, 50, 51, 52, 53, 54, 55, \
+                                         56, 57, 58, 59, 60, 61, 62, 63, }
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS  NAND_LARGE_BADBLOCK_POS
+#elif (CONFIG_SYS_NAND_PAGE_SIZE == NAND_SMALL_BLOCK_PAGE_SIZE)
+#define CONFIG_SYS_NAND_OOBSIZE                16
+#define CONFIG_SYS_NAND_ECCPOS         { 10, 11, 12, 13, 14, 15, }
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS  0
+#else
+#error "CONFIG_SYS_NAND_PAGE_SIZE set to an invalid value"
+#endif
+
+#define CONFIG_SYS_NAND_ECCSIZE                0x100
+#define CONFIG_SYS_NAND_ECCBYTES       3
+#define CONFIG_SYS_NAND_PAGE_COUNT     (CONFIG_SYS_NAND_BLOCK_SIZE / \
+                                               CONFIG_SYS_NAND_PAGE_SIZE)
+#endif /* CONFIG_NAND_LPC32XX_SLC */
+
 /* NOR Flash */
 #if defined(CONFIG_SYS_FLASH_CFI)
 #define CONFIG_FLASH_CFI_DRIVER
index cc6a53e6753e3b9ec524f88820380b7ee616d7fe..d3b7620af11e9648e0fa68ec80740aec6ccd46b0 100644 (file)
 #define CONFIG_LPC32XX_NAND_SLC_RHOLD          200000000
 #define CONFIG_LPC32XX_NAND_SLC_RSETUP         50000000
 
+#define CONFIG_SYS_NAND_BLOCK_SIZE             0x20000
+#define CONFIG_SYS_NAND_PAGE_SIZE              NAND_LARGE_BLOCK_PAGE_SIZE
 #define CONFIG_SYS_NAND_USE_FLASH_BBT
+
 #define CONFIG_CMD_NAND
 
 /*
 #define CONFIG_SPL_NAND_SUPPORT
 #define CONFIG_SPL_NAND_DRIVERS
 
-#define CONFIG_SYS_NAND_BLOCK_SIZE     0x20000
-#define CONFIG_SYS_NAND_PAGE_SIZE      0x800
-#define CONFIG_SYS_NAND_ECCSIZE                0x100
-#define CONFIG_SYS_NAND_OOBSIZE                64
-#define CONFIG_SYS_NAND_ECCPOS         { 40, 41, 42, 43, 44, 45, 46, 47, \
-                                         48, 49, 50, 51, 52, 53, 54, 55, \
-                                         56, 57, 58, 59, 60, 61, 62, 63, }
-#define CONFIG_SYS_NAND_ECCBYTES       3
-#define CONFIG_SYS_NAND_PAGE_COUNT     64
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS  NAND_LARGE_BADBLOCK_POS
-
 #define CONFIG_SPL_NAND_ECC
 #define CONFIG_SPL_NAND_SOFTECC