]> git.sur5r.net Git - u-boot/commitdiff
ls102xa: fdt: Disable QSPI and DSPI in NOR/NAND/SD boot
authorAlison Wang <b18965@freescale.com>
Fri, 26 Dec 2014 05:14:01 +0000 (13:14 +0800)
committerYork Sun <yorksun@freescale.com>
Sat, 24 Jan 2015 04:29:14 +0000 (22:29 -0600)
As QSPI/DSPI and IFC are pin multiplexed, QSPI and DSPI are
only enabled in QSPI boot, and disabled in other boot modes.
IFC is enabled in NOR/NAND/SD boot, and disabled in QSPI boot.
This patch will add fdt support for the above rules.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
arch/arm/cpu/armv7/ls102xa/fdt.c
arch/arm/include/asm/arch-ls102xa/config.h

index 0fda694bdd3718626c49567886590cef7d27ddbd..e0288b8c3fa91833d8996e4a71ff0f346b6e17b9 100644 (file)
@@ -150,4 +150,17 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 
        do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan",
                               "clock-frequency", busclk / 2, 1);
+
+#ifdef CONFIG_QSPI_BOOT
+       off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
+                                           CONFIG_SYS_IFC_ADDR);
+       fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
+#else
+       off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT,
+                                           QSPI0_BASE_ADDR);
+       fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
+       off = fdt_node_offset_by_compat_reg(blob, FSL_DSPI_COMPAT,
+                                           DSPI1_BASE_ADDR);
+       fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
+#endif
 }
index a06ef9dcbfff076bd0e7d90b8bc18ccd6507e483..791551841c71ac81b7e203ce0da9af3992102a47 100644 (file)
 #error SoC not defined
 #endif
 
+#define FSL_IFC_COMPAT         "fsl,ifc"
+#define FSL_QSPI_COMPAT                "fsl,ls1-qspi"
+#define FSL_DSPI_COMPAT                "fsl,vf610-dspi"
+
 #endif /* _ASM_ARMV7_LS102XA_CONFIG_ */