The watchdog on 8610 board is enabled by setting sw[6]
to on. Once enabled, the watchdog can not be disabled
by software. So feed the dog in u-boot is necessary for
normal operation.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
 void
 watchdog_reset(void)
 {
+#if defined(CONFIG_MPC8610)
+       /*
+        * This actually feed the hard enabled watchdog.
+        */
+       volatile immap_t *immap = (immap_t *)CFG_IMMR;
+       volatile ccsr_wdt_t *wdt = &immap->im_wdt;
+       volatile ccsr_gur_t *gur = &immap->im_gur;
+       u32 tmp = gur->pordevsr;
+
+       if (tmp & 0x4000) {
+               wdt->swsrr = 0x556c;
+               wdt->swsrr = 0xaa39;
+       }
+#endif
 }
 #endif /* CONFIG_WATCHDOG */
 
 
 #include <command.h>
 #include <asm/processor.h>
 #include <ppc_asm.tmpl>
+#include <watchdog.h>
 
 unsigned long decrementer_count;    /* count value for 1e6/HZ microseconds */
 unsigned long timestamp;
 
        uint    lynxdcr1;        /* 0xe0f08 - Lynx debug control register 1*/
        int     res14[6];
        uint    ddrioovcr;      /* 0xe0f24 - DDR IO Overdrive Control register */
-       char    res15[61656];
+       char    res15[216];
 } ccsr_gur_t;
 
+/*
+ * Watchdog register block(0xe_4000-0xe_4fff)
+ */
+typedef struct ccsr_wdt {
+       uint    res0;
+       uint    swcrr; /* System watchdog control register */
+       uint    swcnr; /* System watchdog count register */
+       char    res1[2];
+       ushort  swsrr; /* System watchdog service register */
+       char    res2[4080];
+} ccsr_wdt_t;
+
 typedef struct immap {
        ccsr_local_mcm_t        im_local_mcm;
        ccsr_ddr_t              im_ddr1;
        char                    res5[389120];
        ccsr_rio_t              im_rio;
        ccsr_gur_t              im_gur;
+       char                    res6[12288];
+       ccsr_wdt_t              im_wdt;
 } immap_t;
 
 extern immap_t  *immr;
 
 #endif
 
 
-#undef CONFIG_WATCHDOG                 /* watchdog disabled */
+#define CONFIG_WATCHDOG                        /* watchdog enabled */
+#define CFG_WATCHDOG_FREQ      5000    /* Feed interval, 5s */
 
 /*DIU Configuration*/
 #define DIU_CONNECT_TO_DVI             /* DIU controller connects to DVI encoder*/