ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
obj-y += clock_manager_s10.o
+obj-y += reset_manager_s10.o
obj-y += wrap_pll_config_s10.o
endif
ifdef CONFIG_SPL_BUILD
#include <asm/arch/reset_manager_gen5.h>
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
#include <asm/arch/reset_manager_arria10.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#include <asm/arch/reset_manager_s10.h>
#endif
#endif /* _RESET_MANAGER_H_ */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef _RESET_MANAGER_S10_
+#define _RESET_MANAGER_S10_
+
+void reset_cpu(ulong addr);
+void reset_deassert_peripherals_handoff(void);
+
+void socfpga_bridges_reset(int enable);
+
+void socfpga_per_reset(u32 reset, int set);
+void socfpga_per_reset_all(void);
+
+struct socfpga_reset_manager {
+ u32 status;
+ u32 mpu_rst_stat;
+ u32 misc_stat;
+ u32 padding1;
+ u32 hdsk_en;
+ u32 hdsk_req;
+ u32 hdsk_ack;
+ u32 hdsk_stall;
+ u32 mpumodrst;
+ u32 per0modrst;
+ u32 per1modrst;
+ u32 brgmodrst;
+ u32 padding2;
+ u32 cold_mod_reset;
+ u32 padding3;
+ u32 dbg_mod_reset;
+ u32 tap_mod_reset;
+ u32 padding4;
+ u32 padding5;
+ u32 brg_warm_mask;
+ u32 padding6[3];
+ u32 tst_stat;
+ u32 padding7;
+ u32 hdsk_timeout;
+ u32 mpul2flushtimeout;
+ u32 dbghdsktimeout;
+};
+
+#define RSTMGR_MPUMODRST_CORE0 0
+#define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00
+#define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040
+
+/*
+ * Define a reset identifier, from which a permodrst bank ID
+ * and reset ID can be extracted using the subsequent macros
+ * RSTMGR_RESET() and RSTMGR_BANK().
+ */
+#define RSTMGR_BANK_OFFSET 8
+#define RSTMGR_BANK_MASK 0x7
+#define RSTMGR_RESET_OFFSET 0
+#define RSTMGR_RESET_MASK 0x1f
+#define RSTMGR_DEFINE(_bank, _offset) \
+ ((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET)
+
+/* Extract reset ID from the reset identifier. */
+#define RSTMGR_RESET(_reset) \
+ (((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK)
+
+/* Extract bank ID from the reset identifier. */
+#define RSTMGR_BANK(_reset) \
+ (((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
+
+/*
+ * SocFPGA Stratix10 reset IDs, bank mapping is as follows:
+ * 0 ... mpumodrst
+ * 1 ... per0modrst
+ * 2 ... per1modrst
+ * 3 ... brgmodrst
+ */
+#define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0)
+#define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1)
+#define RSTMGR_EMAC2 RSTMGR_DEFINE(1, 2)
+#define RSTMGR_USB0 RSTMGR_DEFINE(1, 3)
+#define RSTMGR_USB1 RSTMGR_DEFINE(1, 4)
+#define RSTMGR_NAND RSTMGR_DEFINE(1, 5)
+#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 7)
+#define RSTMGR_EMAC0_OCP RSTMGR_DEFINE(1, 8)
+#define RSTMGR_EMAC1_OCP RSTMGR_DEFINE(1, 9)
+#define RSTMGR_EMAC2_OCP RSTMGR_DEFINE(1, 10)
+#define RSTMGR_USB0_OCP RSTMGR_DEFINE(1, 11)
+#define RSTMGR_USB1_OCP RSTMGR_DEFINE(1, 12)
+#define RSTMGR_NAND_OCP RSTMGR_DEFINE(1, 13)
+#define RSTMGR_SDMMC_OCP RSTMGR_DEFINE(1, 15)
+#define RSTMGR_DMA RSTMGR_DEFINE(1, 16)
+#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 17)
+#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 18)
+#define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0)
+#define RSTMGR_L4WD1 RSTMGR_DEFINE(2, 1)
+#define RSTMGR_L4WD2 RSTMGR_DEFINE(2, 2)
+#define RSTMGR_L4WD3 RSTMGR_DEFINE(2, 3)
+#define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(2, 4)
+#define RSTMGR_I2C0 RSTMGR_DEFINE(2, 8)
+#define RSTMGR_I2C1 RSTMGR_DEFINE(2, 9)
+#define RSTMGR_I2C2 RSTMGR_DEFINE(2, 10)
+#define RSTMGR_I2C3 RSTMGR_DEFINE(2, 11)
+#define RSTMGR_I2C4 RSTMGR_DEFINE(2, 12)
+#define RSTMGR_UART0 RSTMGR_DEFINE(2, 16)
+#define RSTMGR_UART1 RSTMGR_DEFINE(2, 17)
+#define RSTMGR_GPIO0 RSTMGR_DEFINE(2, 24)
+#define RSTMGR_GPIO1 RSTMGR_DEFINE(2, 25)
+#define RSTMGR_SDR RSTMGR_DEFINE(3, 6)
+
+void socfpga_emac_manage_reset(const unsigned int of_reset_id, u32 state);
+
+/* Create a human-readable reference to SoCFPGA reset. */
+#define SOCFPGA_RESET(_name) RSTMGR_##_name
+
+#endif /* _RESET_MANAGER_S10_ */
#include <asm/io.h>
#include <asm/arch/reset_manager.h>
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#include <asm/arch/mailbox_s10.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if !defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
static const struct socfpga_reset_manager *reset_manager_base =
(void *)SOCFPGA_RSTMGR_ADDRESS;
+#endif
/*
* Write the reset manager register to cause reset
void reset_cpu(ulong addr)
{
/* request a warm reset */
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+ puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n");
+ mbox_reset_cold();
+#else
writel(1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB,
&reset_manager_base->ctrl);
+#endif
/*
* infinite loop here as watchdog will trigger and reset
* the processor
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <dt-bindings/reset/altr,rst-mgr-s10.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_reset_manager *reset_manager_base =
+ (void *)SOCFPGA_RSTMGR_ADDRESS;
+static const struct socfpga_system_manager *system_manager_base =
+ (void *)SOCFPGA_SYSMGR_ADDRESS;
+
+/* Assert or de-assert SoCFPGA reset manager reset. */
+void socfpga_per_reset(u32 reset, int set)
+{
+ const void *reg;
+
+ if (RSTMGR_BANK(reset) == 0)
+ reg = &reset_manager_base->mpumodrst;
+ else if (RSTMGR_BANK(reset) == 1)
+ reg = &reset_manager_base->per0modrst;
+ else if (RSTMGR_BANK(reset) == 2)
+ reg = &reset_manager_base->per1modrst;
+ else if (RSTMGR_BANK(reset) == 3)
+ reg = &reset_manager_base->brgmodrst;
+ else /* Invalid reset register, do nothing */
+ return;
+
+ if (set)
+ setbits_le32(reg, 1 << RSTMGR_RESET(reset));
+ else
+ clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
+}
+
+/*
+ * Assert reset on every peripheral but L4WD0.
+ * Watchdog must be kept intact to prevent glitches
+ * and/or hangs.
+ */
+void socfpga_per_reset_all(void)
+{
+ const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
+
+ /* disable all except OCP and l4wd0. OCP disable later */
+ writel(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK),
+ &reset_manager_base->per0modrst);
+ writel(~l4wd0, &reset_manager_base->per0modrst);
+ writel(0xffffffff, &reset_manager_base->per1modrst);
+}
+
+void socfpga_bridges_reset(int enable)
+{
+ if (enable) {
+ /* clear idle request to all bridges */
+ setbits_le32(&system_manager_base->noc_idlereq_clr, ~0);
+
+ /* Release bridges from reset state per handoff value */
+ clrbits_le32(&reset_manager_base->brgmodrst, ~0);
+
+ /* Poll until all idleack to 0 */
+ while (readl(&system_manager_base->noc_idleack))
+ ;
+ } else {
+ /* set idle request to all bridges */
+ writel(~0, &system_manager_base->noc_idlereq_set);
+
+ /* Enable the NOC timeout */
+ writel(1, &system_manager_base->noc_timeout);
+
+ /* Poll until all idleack to 1 */
+ while ((readl(&system_manager_base->noc_idleack) ^
+ (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
+ ;
+
+ /* Poll until all idlestatus to 1 */
+ while ((readl(&system_manager_base->noc_idlestatus) ^
+ (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
+ ;
+
+ /* Put all bridges (except NOR DDR scheduler) into reset */
+ setbits_le32(&reset_manager_base->brgmodrst,
+ ~RSTMGR_BRGMODRST_DDRSCH_MASK);
+
+ /* Disable NOC timeout */
+ writel(0, &system_manager_base->noc_timeout);
+ }
+}
+
+/* of_reset_id: emac reset id
+ * state: 0 - disable reset, !0 - enable reset
+ */
+void socfpga_emac_manage_reset(const unsigned int of_reset_id, u32 state)
+{
+ u32 reset_emac;
+ u32 reset_emacocp;
+
+ /* hardcode this now */
+ switch (of_reset_id) {
+ case EMAC0_RESET:
+ reset_emac = SOCFPGA_RESET(EMAC0);
+ reset_emacocp = SOCFPGA_RESET(EMAC0_OCP);
+ break;
+ case EMAC1_RESET:
+ reset_emac = SOCFPGA_RESET(EMAC1);
+ reset_emacocp = SOCFPGA_RESET(EMAC1_OCP);
+ break;
+ case EMAC2_RESET:
+ reset_emac = SOCFPGA_RESET(EMAC2);
+ reset_emacocp = SOCFPGA_RESET(EMAC2_OCP);
+ break;
+ default:
+ printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
+ hang();
+ break;
+ }
+
+ /* Reset ECC OCP first */
+ socfpga_per_reset(reset_emacocp, state);
+
+ /* Release the EMAC controller from reset */
+ socfpga_per_reset(reset_emac, state);
+}
+
+/*
+ * Release peripherals from reset based on handoff
+ */
+void reset_deassert_peripherals_handoff(void)
+{
+ writel(0, &reset_manager_base->per1modrst);
+ /* Enable OCP first */
+ writel(~RSTMGR_PER0MODRST_OCP_MASK, &reset_manager_base->per0modrst);
+ writel(0, &reset_manager_base->per0modrst);
+}
projects / u-boot / commitdiff