Fix PCI I/O space mapping on Freescale MPC85x0ADS

The PCI I/O space mapping for Freescale MPC8540ADS board was broken by commit
52c7a68b8d587ebcf5a6b051b58b3d3ffa377ddc which failed to update the #define's
describing the local address window used for the PCI I/O space accesses -- fix
this and carry over the necessary changes into the MPC8560ADS code since the
PCI I/O space mapping was also broken for this board (by the earlier commit
087454609e47295443af793a282cddcd91a5f49c).  Add the comments clarifying how
the PCI I/O space must be mapped to all the MPC85xx board config. headers.

Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
 board/mpc8540ads/init.S      |    4 ++--
 board/mpc8560ads/init.S      |    4 ++--
 include/configs/MPC8540ADS.h |    5 ++---
 include/configs/MPC8541CDS.h |    2 +-
 include/configs/MPC8548CDS.h |    2 +-
 include/configs/MPC8560ADS.h |    8 ++++----
 6 files changed, 12 insertions(+), 13 deletions(-)

diff --git a/board/mpc8540ads/init.S b/board/mpc8540ads/init.S
index 242cb9fbc1dafda157e4cf0a2254f7ef087ae5d0..544fde94c43461370fccd2083fc71fedee65acf3 100644 (file)
--- a/board/mpc8540ads/init.S
+++ b/board/mpc8540ads/init.S
@@ -260,8 +260,8 @@ tlb1_entry:
 #define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
 #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
 
-#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
-#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))
+#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
+#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_1M))
 
 /*
  * Rapid IO at 0xc000_0000 for 512 M

diff --git a/board/mpc8560ads/init.S b/board/mpc8560ads/init.S
index 242cb9fbc1dafda157e4cf0a2254f7ef087ae5d0..544fde94c43461370fccd2083fc71fedee65acf3 100644 (file)
--- a/board/mpc8560ads/init.S
+++ b/board/mpc8560ads/init.S
@@ -260,8 +260,8 @@ tlb1_entry:
 #define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
 #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
 
-#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
-#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))
+#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
+#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_1M))
 
 /*
  * Rapid IO at 0xc000_0000 for 512 M

diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 74a84f4e86ab259c8477c9cc4a064a20c09297dd..5aeea586800eb9587ae1e289305387736753c14b 100644 (file)
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -330,13 +330,12 @@
 
 /*
  * General PCI
- * Addresses are mapped 1-1.
+ * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 #define CFG_PCI1_MEM_BASE      0x80000000
 #define CFG_PCI1_MEM_PHYS      CFG_PCI1_MEM_BASE
 #define CFG_PCI1_MEM_SIZE      0x20000000      /* 512M */
-
-#define CFG_PCI1_IO_BASE       0x0
+#define CFG_PCI1_IO_BASE       0x00000000
 #define CFG_PCI1_IO_PHYS       0xe2000000
 #define CFG_PCI1_IO_SIZE       0x100000        /* 1M */
 

diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index db389cfe676255598816e957c01205055548491f..fb360d282cd4cf653d2a09a569127555172c3cd2 100644 (file)
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -334,7 +334,7 @@ extern unsigned long get_clock_freq(void);
 
 /*
  * General PCI
- * Addresses are mapped 1-1.
+ * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 #define CFG_PCI1_MEM_BASE      0x80000000
 #define CFG_PCI1_MEM_PHYS      CFG_PCI1_MEM_BASE

diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 687fe84850de385a765f5a3176521e8482273c75..14936c28ae5ee3683e397074b0fc18b165f90244 100644 (file)
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -340,7 +340,7 @@ extern unsigned long get_clock_freq(void);
 
 /*
  * General PCI
- * Addresses are mapped 1-1.
+ * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 #define CFG_PCI1_MEM_BASE      0x80000000
 #define CFG_PCI1_MEM_PHYS      CFG_PCI1_MEM_BASE

diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 835bf5cb64e6a27613c396e044403031a6d4a9db..21e663768059e23496457b3c02a9267e0caa4f17 100644 (file)
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -320,14 +320,14 @@
 
 /*
  * General PCI
- * Addresses are mapped 1-1.
+ * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 #define CFG_PCI1_MEM_BASE      0x80000000
 #define CFG_PCI1_MEM_PHYS      CFG_PCI1_MEM_BASE
 #define CFG_PCI1_MEM_SIZE      0x20000000      /* 512M */
-#define CFG_PCI1_IO_BASE       0xe2000000
-#define CFG_PCI1_IO_PHYS       CFG_PCI1_IO_BASE
-#define CFG_PCI1_IO_SIZE       0x1000000       /* 16M */
+#define CFG_PCI1_IO_BASE       0x00000000
+#define CFG_PCI1_IO_PHYS       0xe2000000
+#define CFG_PCI1_IO_SIZE       0x100000        /* 1M */
 
 #if defined(CONFIG_PCI)