]> git.sur5r.net Git - u-boot/commitdiff
[ColdFire MCF5271 family] Add CPU detection based on the value of Chip
authorBartlomiej Sieka <tur@semihalf.com>
Tue, 23 Jan 2007 12:25:22 +0000 (13:25 +0100)
committerBartlomiej Sieka <tur@semihalf.com>
Tue, 23 Jan 2007 12:25:22 +0000 (13:25 +0100)
Identification Register (CIR).

cpu/mcf52x2/cpu.c
include/asm-m68k/m5271.h

index aa6b2bd670cea9c61025ccbe1478fb55c4446df7..ce59d39cfab4f65f8db3968eaf87c3a6c88fb410 100644 (file)
 #endif
 
 #ifdef CONFIG_M5271
+/*
+ * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
+ * determine which one we are running on, based on the Chip Identification
+ * Register (CIR).
+ */
 int checkcpu (void)
 {
        char buf[32];
+       unsigned short cir;     /* Chip Identification Register */
+       unsigned short pin;     /* Part identification number */
+       unsigned char prn;      /* Part revision number */
+       char *cpu_model;
+
+       cir = mbar_readShort(MCF_CCM_CIR);
+       pin = cir >> MCF_CCM_CIR_PIN_LEN;
+       prn = cir & MCF_CCM_CIR_PRN_MASK;
+
+       switch (pin) {
+       case MCF_CCM_CIR_PIN_MCF5270:
+               cpu_model = "5270";
+               break;
+       case MCF_CCM_CIR_PIN_MCF5271:
+               cpu_model = "5271";
+               break;
+       default:
+               cpu_model = NULL;
+               break;
+       }
+
+       if (cpu_model)
+               printf("CPU:   Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
+                       cpu_model, prn, strmhz(buf, CFG_CLK));
+       else
+               printf("CPU:   Unknown - Freescale ColdFire MCF5271 family"
+                       " (PIN: 0x%x) rev. %hu, at %s MHz\n",
+                       pin, prn, strmhz(buf, CFG_CLK));
 
-       printf ("CPU:   Freescale Coldfire MCF5271 at %s MHz\n", strmhz(buf, CFG_CLK));
        return 0;
 }
 
index 765414fdc328cc1c6028477f7da05f05d22972dc..e0f02cf7fdfc087efbdac5e9b9703b73d7f09781 100644 (file)
 #define MCF_GPIO_PAR_FECI2C                    0x100047
 #define MCF_GPIO_PAR_UART                      0x100048
 
+#define MCF_CCM_CIR                            0x11000A
+#define MCF_CCM_CIR_PRN_MASK                   0x3F
+#define MCF_CCM_CIR_PIN_LEN                    6
+#define MCF_CCM_CIR_PIN_MCF5270                        0x2e
+#define MCF_CCM_CIR_PIN_MCF5271                        0x80
+
 #define MCF_GPIO_AD_ADDR23                     0x80
 #define MCF_GPIO_AD_ADDR22                     0x40
 #define MCF_GPIO_AD_ADDR21                     0x20