Some armv7 targets are missing a cache line size declaration.
In preparation for "arm: cache: Implement cache range check for v7"
patch, add these declarations with the appropriate value for
the target's SoC or CPU.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
/*
* High Level Configuration Options
*/
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
/*
* High Level Configuration Options
*/
#include <asm/hardware.h>
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
#define CONFIG_SYS_TEXT_BASE 0x26f00000
/* ARM asynchronous clock */
#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_CACHELINE_SIZE 64
/*
* Memory configuration
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
/*
* High Level Configuration Options
*/
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
/*
* High Level Configuration Options
*/
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
#include <asm/arch/imx-regs.h>
#define CONFIG_VF610
#undef DEBUG
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
#define CONFIG_SH73A0
#define CONFIG_KZM_A9_GT
#define CONFIG_RMOBILE_BOARD_STRING "KMC KZM-A9-GT"
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
/*
* High Level Configuration Options
*/
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
#include <asm/arch/imx-regs.h>
#define CONFIG_VF610
#ifndef __RCAR_GEN2_COMMON_H
#define __RCAR_GEN2_COMMON_H
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
#include <asm/arch/rmobile.h>
#define CONFIG_CMD_DFL
#ifndef __CONFIG_RK3036_COMMON_H
#define __CONFIG_RK3036_COMMON_H
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
#include <asm/arch/hardware.h>
#define CONFIG_SYS_NO_FLASH
#ifndef __CONFIG_RK3288_COMMON_H
#define __CONFIG_RK3288_COMMON_H
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
#include <asm/arch/hardware.h>
#define CONFIG_SYS_NO_FLASH
#define CONFIG_S5PC110 1 /* which is in a S5PC110 */
#define CONFIG_MACH_GONI 1 /* working with Goni */
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
#include <linux/sizes.h>
#include <asm/arch/cpu.h> /* get chip and board defs */
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
/*
* High Level Configuration Options
* (easy to change)
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
/*
* High Level Configuration Options
*/
#ifndef __CONFIG_TI814X_EVM_H
#define __CONFIG_TI814X_EVM_H
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
#define CONFIG_TI81XX
#define CONFIG_TI814X
#define CONFIG_SYS_NO_FLASH
#ifndef __CONFIG_TI816X_EVM_H
#define __CONFIG_TI816X_EVM_H
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
#define CONFIG_TI81XX
#define CONFIG_TI816X
#define CONFIG_SYS_NO_FLASH
#ifndef __CONFIG_TI_OMAP3_COMMON_H__
#define __CONFIG_TI_OMAP3_COMMON_H__
+/*
+ * High Level Configuration Options
+ */
+
+#define CONFIG_SYS_CACHELINE_SIZE 64
#include <asm/arch/cpu.h>
#include <asm/arch/omap.h>
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
/* High Level Configuration Options */
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_OMAP /* in a TI OMAP core */
#define CONFIG_SYS_MEMTEST_START V2M_BASE
#define CONFIG_SYS_MEMTEST_END 0x20000000
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_SYS_L2CACHE_OFF 1
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
#include <asm/arch/imx-regs.h>
#define CONFIG_VF610